mirrors/Ryujinx
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Update CpuTestSimdMove.cs

Browse source
This commit is contained in:
LDj3SNuD 2018-04-12 16:41:03 +02:00 • committed by GitHub
parent e97144f6b2
commit b52963ebf5
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 48 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

52
Ryujinx.Tests/Cpu/CpuTestSimdMove.cs
View file

@ -6,8 +6,8 @@ namespace Ryujinx.Tests.Cpu
public class CpuTestSimdMove : CpuTest
{
[Test, Description("trn1 v0.4s, v1.4s, v2.4s")]
public void Trn1_V([Random(2)] uint A0, [Random(2)] uint A1, [Random(2)] uint A2, [Random(2)] uint A3,
[Random(2)] uint B0, [Random(2)] uint B1, [Random(2)] uint B2, [Random(2)] uint B3)
public void Trn1_V_4S([Random(2)] uint A0, [Random(2)] uint A1, [Random(2)] uint A2, [Random(2)] uint A3,
[Random(2)] uint B0, [Random(2)] uint B1, [Random(2)] uint B2, [Random(2)] uint B3)
{
uint Opcode = 0x4E822820;
AVec V1 = new AVec { W0 = A0, W1 = A1, W2 = A2, W3 = A3 };
@ -21,9 +21,31 @@ namespace Ryujinx.Tests.Cpu
Assert.That(ThreadState.V0.W3, Is.EqualTo(B2));
}
[Test, Description("trn1 v0.8b, v1.8b, v2.8b")]
public void Trn1_V_8B([Random(2)] byte A0, [Random(1)] byte A1, [Random(2)] byte A2, [Random(1)] byte A3,
[Random(2)] byte A4, [Random(1)] byte A5, [Random(2)] byte A6, [Random(1)] byte A7,
[Random(2)] byte B0, [Random(1)] byte B1, [Random(2)] byte B2, [Random(1)] byte B3,
[Random(2)] byte B4, [Random(1)] byte B5, [Random(2)] byte B6, [Random(1)] byte B7)
{
uint Opcode = 0x0E022820;
AVec V1 = new AVec { B0 = A0, B1 = A1, B2 = A2, B3 = A3, B4 = A4, B5 = A5, B6 = A6, B7 = A7 };
AVec V2 = new AVec { B0 = B0, B1 = B1, B2 = B2, B3 = B3, B4 = B4, B5 = B5, B6 = B6, B7 = B7 };
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
Assert.That(ThreadState.V0.B0, Is.EqualTo(A0));
Assert.That(ThreadState.V0.B1, Is.EqualTo(B0));
Assert.That(ThreadState.V0.B2, Is.EqualTo(A2));
Assert.That(ThreadState.V0.B3, Is.EqualTo(B2));
Assert.That(ThreadState.V0.B4, Is.EqualTo(A4));
Assert.That(ThreadState.V0.B5, Is.EqualTo(B4));
Assert.That(ThreadState.V0.B6, Is.EqualTo(A6));
Assert.That(ThreadState.V0.B7, Is.EqualTo(B6));
}
[Test, Description("trn2 v0.4s, v1.4s, v2.4s")]
public void Trn2_V([Random(2)] uint A0, [Random(2)] uint A1, [Random(2)] uint A2, [Random(2)] uint A3,
[Random(2)] uint B0, [Random(2)] uint B1, [Random(2)] uint B2, [Random(2)] uint B3)
public void Trn2_V_4S([Random(2)] uint A0, [Random(2)] uint A1, [Random(2)] uint A2, [Random(2)] uint A3,
[Random(2)] uint B0, [Random(2)] uint B1, [Random(2)] uint B2, [Random(2)] uint B3)
{
uint Opcode = 0x4E826820;
AVec V1 = new AVec { W0 = A0, W1 = A1, W2 = A2, W3 = A3 };
@ -37,6 +59,28 @@ namespace Ryujinx.Tests.Cpu
Assert.That(ThreadState.V0.W3, Is.EqualTo(B3));
}
[Test, Description("trn2 v0.8b, v1.8b, v2.8b")]
public void Trn2_V_8B([Random(1)] byte A0, [Random(2)] byte A1, [Random(1)] byte A2, [Random(2)] byte A3,
[Random(1)] byte A4, [Random(2)] byte A5, [Random(1)] byte A6, [Random(2)] byte A7,
[Random(1)] byte B0, [Random(2)] byte B1, [Random(1)] byte B2, [Random(2)] byte B3,
[Random(1)] byte B4, [Random(2)] byte B5, [Random(1)] byte B6, [Random(2)] byte B7)
{
uint Opcode = 0x0E026820;
AVec V1 = new AVec { B0 = A0, B1 = A1, B2 = A2, B3 = A3, B4 = A4, B5 = A5, B6 = A6, B7 = A7 };
AVec V2 = new AVec { B0 = B0, B1 = B1, B2 = B2, B3 = B3, B4 = B4, B5 = B5, B6 = B6, B7 = B7 };
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1, V2: V2);
Assert.That(ThreadState.V0.B0, Is.EqualTo(A1));
Assert.That(ThreadState.V0.B1, Is.EqualTo(B1));
Assert.That(ThreadState.V0.B2, Is.EqualTo(A3));
Assert.That(ThreadState.V0.B3, Is.EqualTo(B3));
Assert.That(ThreadState.V0.B4, Is.EqualTo(A5));
Assert.That(ThreadState.V0.B5, Is.EqualTo(B5));
Assert.That(ThreadState.V0.B6, Is.EqualTo(A7));
Assert.That(ThreadState.V0.B7, Is.EqualTo(B7));
}
[TestCase(0u, 0u, 0x2313221221112010ul, 0x0000000000000000ul)]
[TestCase(1u, 0u, 0x2313221221112010ul, 0x2717261625152414ul)]
[TestCase(0u, 1u, 0x2322131221201110ul, 0x0000000000000000ul)]