mirrors/Ryujinx
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Zero out bits 63:32 of scalar float operations with SSE intrinsics

Browse source
This commit is contained in:
gdkchan 2018-07-15 18:38:30 -03:00
commit b79f3749a8
4 changed files with 69 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

16
ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
View file

@ -234,7 +234,7 @@ namespace ChocolArm64.Instruction
{ {
if (AOptimizations.UseSse && AOptimizations.UseSse2) if (AOptimizations.UseSse && AOptimizations.UseSse2)
{ {
EmitSseOrSse2CallF(Context, nameof(Sse.AddScalar)); EmitScalarSseOrSse2CallF(Context, nameof(Sse.AddScalar));
} }
else else
{ {
@ -246,7 +246,7 @@ namespace ChocolArm64.Instruction
{ {
if (AOptimizations.UseSse && AOptimizations.UseSse2) if (AOptimizations.UseSse && AOptimizations.UseSse2)
{ {
EmitSseOrSse2CallF(Context, nameof(Sse.Add)); EmitVectorSseOrSse2CallF(Context, nameof(Sse.Add));
} }
else else
{ {
@ -304,7 +304,7 @@ namespace ChocolArm64.Instruction
{ {
if (AOptimizations.UseSse && AOptimizations.UseSse2) if (AOptimizations.UseSse && AOptimizations.UseSse2)
{ {
EmitSseOrSse2CallF(Context, nameof(Sse.DivideScalar)); EmitScalarSseOrSse2CallF(Context, nameof(Sse.DivideScalar));
} }
else else
{ {
@ -316,7 +316,7 @@ namespace ChocolArm64.Instruction
{ {
if (AOptimizations.UseSse && AOptimizations.UseSse2) if (AOptimizations.UseSse && AOptimizations.UseSse2)
{ {
EmitSseOrSse2CallF(Context, nameof(Sse.Divide)); EmitVectorSseOrSse2CallF(Context, nameof(Sse.Divide));
} }
else else
{ {
@ -487,7 +487,7 @@ namespace ChocolArm64.Instruction
{ {
if (AOptimizations.UseSse && AOptimizations.UseSse2) if (AOptimizations.UseSse && AOptimizations.UseSse2)
{ {
EmitSseOrSse2CallF(Context, nameof(Sse.MultiplyScalar)); EmitScalarSseOrSse2CallF(Context, nameof(Sse.MultiplyScalar));
} }
else else
{ {
@ -504,7 +504,7 @@ namespace ChocolArm64.Instruction
{ {
if (AOptimizations.UseSse && AOptimizations.UseSse2) if (AOptimizations.UseSse && AOptimizations.UseSse2)
{ {
EmitSseOrSse2CallF(Context, nameof(Sse.Multiply)); EmitVectorSseOrSse2CallF(Context, nameof(Sse.Multiply));
} }
else else
{ {
@ -871,7 +871,7 @@ namespace ChocolArm64.Instruction
{ {
if (AOptimizations.UseSse && AOptimizations.UseSse2) if (AOptimizations.UseSse && AOptimizations.UseSse2)
{ {
EmitSseOrSse2CallF(Context, nameof(Sse.SubtractScalar)); EmitScalarSseOrSse2CallF(Context, nameof(Sse.SubtractScalar));
} }
else else
{ {
@ -883,7 +883,7 @@ namespace ChocolArm64.Instruction
{ {
if (AOptimizations.UseSse && AOptimizations.UseSse2) if (AOptimizations.UseSse && AOptimizations.UseSse2)
{ {
EmitSseOrSse2CallF(Context, nameof(Sse.Subtract)); EmitVectorSseOrSse2CallF(Context, nameof(Sse.Subtract));
} }
else else
{ {

12
ChocolArm64/Instruction/AInstEmitSimdCmp.cs
View file

@ -158,7 +158,7 @@ namespace ChocolArm64.Instruction
if (Context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse if (Context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse
&& AOptimizations.UseSse2) && AOptimizations.UseSse2)
{ {
EmitSseOrSse2CallF(Context, nameof(Sse.CompareEqualScalar)); EmitScalarSseOrSse2CallF(Context, nameof(Sse.CompareEqualScalar));
} }
else else
{ {
@ -171,7 +171,7 @@ namespace ChocolArm64.Instruction
if (Context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse if (Context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse
&& AOptimizations.UseSse2) && AOptimizations.UseSse2)
{ {
EmitSseOrSse2CallF(Context, nameof(Sse.CompareEqual)); EmitVectorSseOrSse2CallF(Context, nameof(Sse.CompareEqual));
} }
else else
{ {
@ -184,7 +184,7 @@ namespace ChocolArm64.Instruction
if (Context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse if (Context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse
&& AOptimizations.UseSse2) && AOptimizations.UseSse2)
{ {
EmitSseOrSse2CallF(Context, nameof(Sse.CompareGreaterThanOrEqualScalar)); EmitScalarSseOrSse2CallF(Context, nameof(Sse.CompareGreaterThanOrEqualScalar));
} }
else else
{ {
@ -197,7 +197,7 @@ namespace ChocolArm64.Instruction
if (Context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse if (Context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse
&& AOptimizations.UseSse2) && AOptimizations.UseSse2)
{ {
EmitSseOrSse2CallF(Context, nameof(Sse.CompareGreaterThanOrEqual)); EmitVectorSseOrSse2CallF(Context, nameof(Sse.CompareGreaterThanOrEqual));
} }
else else
{ {
@ -210,7 +210,7 @@ namespace ChocolArm64.Instruction
if (Context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse if (Context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse
&& AOptimizations.UseSse2) && AOptimizations.UseSse2)
{ {
EmitSseOrSse2CallF(Context, nameof(Sse.CompareGreaterThanScalar)); EmitScalarSseOrSse2CallF(Context, nameof(Sse.CompareGreaterThanScalar));
} }
else else
{ {
@ -223,7 +223,7 @@ namespace ChocolArm64.Instruction
if (Context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse if (Context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse
&& AOptimizations.UseSse2) && AOptimizations.UseSse2)
{ {
EmitSseOrSse2CallF(Context, nameof(Sse.CompareGreaterThan)); EmitVectorSseOrSse2CallF(Context, nameof(Sse.CompareGreaterThan));
} }
else else
{ {

34
ChocolArm64/Instruction/AInstEmitSimdHelper.cs
View file

@ -110,7 +110,17 @@ namespace ChocolArm64.Instruction
} }
} }
public static void EmitSseOrSse2CallF(AILEmitterCtx Context, string Name) public static void EmitScalarSseOrSse2CallF(AILEmitterCtx Context, string Name)
{
EmitSseOrSse2CallF(Context, Name, true);
}
public static void EmitVectorSseOrSse2CallF(AILEmitterCtx Context, string Name)
{
EmitSseOrSse2CallF(Context, Name, false);
}
public static void EmitSseOrSse2CallF(AILEmitterCtx Context, string Name, bool Scalar)
{ {
AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
@ -160,7 +170,18 @@ namespace ChocolArm64.Instruction
Context.EmitStvec(Op.Rd); Context.EmitStvec(Op.Rd);
if (Op.RegisterSize == ARegisterSize.SIMD64) if (Scalar)
{
if (SizeF == 0)
{
EmitVectorZero32_128(Context, Op.Rd);
}
else /* if (SizeF == 1) */
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
else if (Op.RegisterSize == ARegisterSize.SIMD64)
{ {
EmitVectorZeroUpper(Context, Op.Rd); EmitVectorZeroUpper(Context, Op.Rd);
} }
@ -968,6 +989,15 @@ namespace ChocolArm64.Instruction
EmitVectorInsert(Context, Rd, 1, 3, 0); EmitVectorInsert(Context, Rd, 1, 3, 0);
} }
public static void EmitVectorZero32_128(AILEmitterCtx Context, int Reg)
{
Context.EmitLdvec(Reg);
AVectorHelper.EmitCall(Context, nameof(AVectorHelper.VectorZero32_128));
Context.EmitStvec(Reg);
}
public static void EmitVectorInsert(AILEmitterCtx Context, int Reg, int Index, int Size) public static void EmitVectorInsert(AILEmitterCtx Context, int Reg, int Index, int Size)
{ {
ThrowIfInvalid(Index, Size); ThrowIfInvalid(Index, Size);

23
ChocolArm64/Instruction/AVectorHelper.cs
View file

@ -9,6 +9,18 @@ namespace ChocolArm64.Instruction
{ {
static class AVectorHelper static class AVectorHelper
{ {
private static readonly Vector128<float> Zero32_128Mask;
static AVectorHelper()
{
if (!Sse2.IsSupported)
{
throw new PlatformNotSupportedException();
}
Zero32_128Mask = Sse.StaticCast<uint, float>(Sse2.SetVector128(0, 0, 0, 0xffffffff));
}
public static void EmitCall(AILEmitterCtx Context, string Name64, string Name128) public static void EmitCall(AILEmitterCtx Context, string Name64, string Name128)
{ {
bool IsSimd64 = Context.CurrOp.RegisterSize == ARegisterSize.SIMD64; bool IsSimd64 = Context.CurrOp.RegisterSize == ARegisterSize.SIMD64;
@ -528,6 +540,17 @@ namespace ChocolArm64.Instruction
throw new PlatformNotSupportedException(); throw new PlatformNotSupportedException();
} }
[MethodImpl(MethodImplOptions.AggressiveInlining)]
public static Vector128<float> VectorZero32_128(Vector128<float> Vector)
{
if (Sse.IsSupported)
{
return Sse.And(Vector, Zero32_128Mask);
}
throw new PlatformNotSupportedException();
}
[MethodImpl(MethodImplOptions.AggressiveInlining)] [MethodImpl(MethodImplOptions.AggressiveInlining)]
public static Vector128<sbyte> VectorSingleToSByte(Vector128<float> Vector) public static Vector128<sbyte> VectorSingleToSByte(Vector128<float> Vector)
{ {