From ba73bcba4fd5253f4d08ac7938a128bb4c5f676d Mon Sep 17 00:00:00 2001 From: unknown Date: Wed, 28 Feb 2018 00:37:17 +0100 Subject: [PATCH] add ASRV test --- Ryujinx.Tests/Cpu/CpuTestAlu.cs | 98 +++++++++++++++------- Ryujinx.Tests/Cpu/CpuTestMisc.cs | 7 +- Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs | 5 -- 3 files changed, 73 insertions(+), 37 deletions(-) diff --git a/Ryujinx.Tests/Cpu/CpuTestAlu.cs b/Ryujinx.Tests/Cpu/CpuTestAlu.cs index c13da7a17f..ce05dcb3f7 100644 --- a/Ryujinx.Tests/Cpu/CpuTestAlu.cs +++ b/Ryujinx.Tests/Cpu/CpuTestAlu.cs @@ -27,11 +27,14 @@ namespace Ryujinx.Tests.Cpu { //ADCS (X0/W0), (X1, W1), (X2/W2) AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B, Carry: CarryState); - Assert.AreEqual(Negative, ThreadState.Negative); - Assert.IsFalse(ThreadState.Overflow); - Assert.AreEqual(Zero, ThreadState.Zero); - Assert.AreEqual(Carry, ThreadState.Carry); - Assert.AreEqual(Result, ThreadState.X0); + Assert.Multiple(() => + { + Assert.IsFalse(ThreadState.Overflow); + Assert.AreEqual(Negative, ThreadState.Negative); + Assert.AreEqual(Zero, ThreadState.Zero); + Assert.AreEqual(Carry, ThreadState.Carry); + Assert.AreEqual(Result, ThreadState.X0); + }); } [Test] @@ -51,11 +54,14 @@ namespace Ryujinx.Tests.Cpu { //ADDS WZR, WSP, #5 AThreadState ThreadState = SingleOpcode(0x310017FF, X31: A); - Assert.IsFalse(ThreadState.Negative); - Assert.AreEqual(Zero, ThreadState.Zero); - Assert.AreEqual(Carry, ThreadState.Carry); - Assert.IsFalse(ThreadState.Overflow); - Assert.AreEqual(A, ThreadState.X31); + Assert.Multiple(() => + { + Assert.IsFalse(ThreadState.Negative); + Assert.IsFalse(ThreadState.Overflow); + Assert.AreEqual(Zero, ThreadState.Zero); + Assert.AreEqual(Carry, ThreadState.Carry); + Assert.AreEqual(A, ThreadState.X31); + }); } [TestCase(0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFul, true, false)] @@ -66,26 +72,55 @@ namespace Ryujinx.Tests.Cpu // ANDS W0, W1, W2 uint Opcode = 0x6A020020; AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B); - Assert.AreEqual(Result, ThreadState.X0); - Assert.AreEqual(Negative, ThreadState.Negative); - Assert.AreEqual(Zero, ThreadState.Zero); + Assert.Multiple(() => + { + Assert.AreEqual(Result, ThreadState.X0); + Assert.AreEqual(Negative, ThreadState.Negative); + Assert.AreEqual(Zero, ThreadState.Zero); + }); } - [Test] - public void OrrBitmasks() + [TestCase(0x0000FF44u, 0x00000004u, 0x00000FF4u)] + [TestCase(0x00000000u, 0x00000004u, 0x00000000u)] + [TestCase(0x0000FF44u, 0x00000008u, 0x000000FFu)] + [TestCase(0xFFFFFFFFu, 0x00000004u, 0xFFFFFFFFu)] + [TestCase(0xFFFFFFFFu, 0x00000008u, 0xFFFFFFFFu)] + [TestCase(0xFFFFFFFFu, 0x00000020u, 0xFFFFFFFFu)] + [TestCase(0x0FFFFFFFu, 0x0000001Cu, 0x00000000u)] + [TestCase(0x80000000u, 0x0000001Fu, 0xFFFFFFFFu)] + [TestCase(0xCAFE0000u, 0x00000020u, 0xCAFE0000u)] + public void Asrv32(uint A, uint ShiftValue, uint Result) { - // ORR W0, WZR, #0x01010101 - Assert.AreEqual(0x01010101, SingleOpcode(0x3200C3E0).X0); + // ASRV W0, W1, W2 + AThreadState ThreadState = SingleOpcode(0x1AC22820, X1: A, X2: ShiftValue); + Assert.AreEqual(Result, ThreadState.X0); + } - Reset(); + [TestCase(0x000000000000FF44ul, 0x00000004u, 0x0000000000000FF4ul)] + [TestCase(0x0000000000000000ul, 0x00000004u, 0x0000000000000000ul)] + [TestCase(0x000000000000FF44ul, 0x00000008u, 0x00000000000000FFul)] + [TestCase(0x00000000FFFFFFFFul, 0x00000004u, 0x000000000FFFFFFFul)] + [TestCase(0x00000000FFFFFFFFul, 0x00000008u, 0x0000000000FFFFFFul)] + [TestCase(0x00000000FFFFFFFFul, 0x00000020u, 0x0000000000000000ul)] + [TestCase(0x000000000FFFFFFFul, 0x0000001Cu, 0x0000000000000000ul)] + [TestCase(0x000CC4488FFFFFFFul, 0x0000001Cu, 0x0000000000CC4488ul)] + [TestCase(0xFFFFFFFFFFFFFFFFul, 0x0000001Cu, 0xFFFFFFFFFFFFFFFFul)] + [TestCase(0x8000000000000000ul, 0x0000003Fu, 0xFFFFFFFFFFFFFFFFul)] + [TestCase(0xCAFE000000000000ul, 0x00000040u, 0xCAFE000000000000ul)] + public void Asrv64(ulong A, uint ShiftValue, ulong Result) + { + // ASRV X0, X1, X2 + AThreadState ThreadState = SingleOpcode(0x9AC22820, X1: A, X2: ShiftValue); + Assert.AreEqual(Result, ThreadState.X0); + } - // ORR W1, WZR, #0x00F000F0 - Assert.AreEqual(0x00F000F0, SingleOpcode(0x320C8FE1).X1); - - Reset(); - - // ORR W2, WZR, #1 - Assert.AreEqual(0x00000001, SingleOpcode(0x320003E2).X2); + [TestCase(0x01010101u, 0x3200C3E2u)] + [TestCase(0x00F000F0u, 0x320C8FE2u)] + [TestCase(0x00000001u, 0x320003E2u)] + public void OrrBitmasks(uint Bitmask, uint Opcode) + { + // ORR W2, WZR, #Bitmask + Assert.AreEqual(Bitmask, SingleOpcode(Opcode).X2); } [Test] @@ -114,11 +149,14 @@ namespace Ryujinx.Tests.Cpu { //SBCS (X0/W0), (X1, W1), (X2/W2) AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B, Carry: CarryState); - Assert.AreEqual(Negative, ThreadState.Negative); - Assert.IsFalse(ThreadState.Overflow); - Assert.AreEqual(Zero, ThreadState.Zero); - Assert.AreEqual(Carry, ThreadState.Carry); - Assert.AreEqual(Result, ThreadState.X0); + Assert.Multiple(() => + { + Assert.IsFalse(ThreadState.Overflow); + Assert.AreEqual(Negative, ThreadState.Negative); + Assert.AreEqual(Zero, ThreadState.Zero); + Assert.AreEqual(Carry, ThreadState.Carry); + Assert.AreEqual(Result, ThreadState.X0); + }); } } } diff --git a/Ryujinx.Tests/Cpu/CpuTestMisc.cs b/Ryujinx.Tests/Cpu/CpuTestMisc.cs index 97947b9a93..3a995fe261 100644 --- a/Ryujinx.Tests/Cpu/CpuTestMisc.cs +++ b/Ryujinx.Tests/Cpu/CpuTestMisc.cs @@ -197,8 +197,11 @@ namespace Ryujinx.Tests.Cpu Opcode(0xD4200000); Opcode(0xD65F03C0); ExecuteOpcodes(); - Assert.AreEqual(0, GetThreadState().X0); - Assert.IsTrue(GetThreadState().Zero); + Assert.Multiple(() => + { + Assert.AreEqual(0, GetThreadState().X0); + Assert.IsTrue(GetThreadState().Zero); + }); } [Test] diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs index fd193ddb05..6b11f495f4 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdArithmetic.cs @@ -13,7 +13,6 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x40733333u, 'M', false, 0x40400000u)] [TestCase(0x3F99999Au, 'Z', false, 0x3F800000u)] [TestCase(0x3FE66666u, 'Z', false, 0x3F800000u)] - //+/-0 [TestCase(0x00000000u, 'N', false, 0x00000000u)] [TestCase(0x00000000u, 'P', false, 0x00000000u)] [TestCase(0x00000000u, 'M', false, 0x00000000u)] @@ -22,17 +21,14 @@ namespace Ryujinx.Tests.Cpu [TestCase(0x80000000u, 'P', false, 0x80000000u)] [TestCase(0x80000000u, 'M', false, 0x80000000u)] [TestCase(0x80000000u, 'Z', false, 0x80000000u)] - //+inf [TestCase(0x7F800000u, 'N', false, 0x7F800000u)] [TestCase(0x7F800000u, 'P', false, 0x7F800000u)] [TestCase(0x7F800000u, 'M', false, 0x7F800000u)] [TestCase(0x7F800000u, 'Z', false, 0x7F800000u)] - //-inf [TestCase(0xFF800000u, 'N', false, 0xFF800000u)] [TestCase(0xFF800000u, 'P', false, 0xFF800000u)] [TestCase(0xFF800000u, 'M', false, 0xFF800000u)] [TestCase(0xFF800000u, 'Z', false, 0xFF800000u)] - //SNaN [TestCase(0xFF800001u, 'N', false, 0xFFC00001u)] [TestCase(0xFF800001u, 'P', false, 0xFFC00001u)] [TestCase(0xFF800001u, 'M', false, 0xFFC00001u)] @@ -41,7 +37,6 @@ namespace Ryujinx.Tests.Cpu [TestCase(0xFF800001u, 'P', true, 0x7FC00000u)] [TestCase(0xFF800001u, 'M', true, 0x7FC00000u)] [TestCase(0xFF800001u, 'Z', true, 0x7FC00000u)] - //QNaN [TestCase(0x7FC00002u, 'N', false, 0x7FC00002u)] [TestCase(0x7FC00002u, 'P', false, 0x7FC00002u)] [TestCase(0x7FC00002u, 'M', false, 0x7FC00002u)]