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Remove Tmp stuff, EmitLd/Stvectmp2() & Dup. Nits.

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LDj3SNuD 2019-03-10 00:16:45 +01:00 • committed by GitHub
commit c4fe61103b
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1 changed files with 33 additions and 46 deletions
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77
ChocolArm64/Instructions/InstEmitSimdHelper.cs
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@ -592,12 +592,9 @@ namespace ChocolArm64.Instructions
emit(); emit();
EmitVectorInsertTmp(context, index, op.Size); EmitVectorInsert(context, op.Rd, index, op.Size);
} }
context.EmitLdvectmp();
context.EmitStvec(op.Rd);
if (op.RegisterSize == RegisterSize.Simd64) if (op.RegisterSize == RegisterSize.Simd64)
{ {
EmitVectorZeroUpper(context, op.Rd); EmitVectorZeroUpper(context, op.Rd);
@ -898,20 +895,13 @@ namespace ChocolArm64.Instructions
Type[] types = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) }; Type[] types = new Type[] { typeof(Vector128<float>), typeof(Vector128<float>) };
context.EmitLdvec(op.Rn); context.EmitLdvec(op.Rn);
context.Emit(OpCodes.Dup);
context.EmitStvectmp();
context.EmitLdvec(op.Rm); context.EmitLdvec(op.Rm);
context.Emit(OpCodes.Dup);
context.EmitStvectmp2();
context.EmitLdc_I4(2 << 6 | 0 << 4 | 2 << 2 | 0 << 0); context.EmitLdc_I4(2 << 6 | 0 << 4 | 2 << 2 | 0 << 0);
context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Shuffle), typesSfl)); context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Shuffle), typesSfl));
context.EmitLdvectmp(); context.EmitLdvec(op.Rn);
context.EmitLdvectmp2(); context.EmitLdvec(op.Rm);
context.EmitLdc_I4(3 << 6 | 1 << 4 | 3 << 2 | 1 << 0); context.EmitLdc_I4(3 << 6 | 1 << 4 | 3 << 2 | 1 << 0);
context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Shuffle), typesSfl)); context.EmitCall(typeof(Sse).GetMethod(nameof(Sse.Shuffle), typesSfl));
@ -926,19 +916,12 @@ namespace ChocolArm64.Instructions
Type[] types = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) }; Type[] types = new Type[] { typeof(Vector128<double>), typeof(Vector128<double>) };
context.EmitLdvec(op.Rn); context.EmitLdvec(op.Rn);
context.Emit(OpCodes.Dup);
context.EmitStvectmp();
context.EmitLdvec(op.Rm); context.EmitLdvec(op.Rm);
context.Emit(OpCodes.Dup);
context.EmitStvectmp2();
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.UnpackLow), types)); context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.UnpackLow), types));
context.EmitLdvectmp(); context.EmitLdvec(op.Rn);
context.EmitLdvectmp2(); context.EmitLdvec(op.Rm);
context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.UnpackHigh), types)); context.EmitCall(typeof(Sse2).GetMethod(nameof(Sse2.UnpackHigh), types));
@ -985,11 +968,6 @@ namespace ChocolArm64.Instructions
int bytes = op.GetBitsCount() >> 3; int bytes = op.GetBitsCount() >> 3;
int elems = !scalar ? bytes >> op.Size : 1; int elems = !scalar ? bytes >> op.Size : 1;
if (scalar)
{
EmitVectorZeroLowerTmp(context);
}
for (int index = 0; index < elems; index++) for (int index = 0; index < elems; index++)
{ {
EmitVectorExtractSx(context, op.Rn, index, op.Size); EmitVectorExtractSx(context, op.Rn, index, op.Size);
@ -1005,13 +983,15 @@ namespace ChocolArm64.Instructions
EmitUnarySignedSatQAbsOrNeg(context); EmitUnarySignedSatQAbsOrNeg(context);
} }
EmitVectorInsertTmp(context, index, op.Size); if (scalar)
{
EmitVectorZeroAll(context, op.Rd);
} }
context.EmitLdvectmp(); EmitVectorInsert(context, op.Rd, index, op.Size);
context.EmitStvec(op.Rd); }
if ((op.RegisterSize == RegisterSize.Simd64) || scalar) if (op.RegisterSize == RegisterSize.Simd64)
{ {
EmitVectorZeroUpper(context, op.Rd); EmitVectorZeroUpper(context, op.Rd);
} }
@ -1052,11 +1032,6 @@ namespace ChocolArm64.Instructions
int bytes = op.GetBitsCount() >> 3; int bytes = op.GetBitsCount() >> 3;
int elems = !scalar ? bytes >> op.Size : 1; int elems = !scalar ? bytes >> op.Size : 1;
if (scalar)
{
EmitVectorZeroLowerTmp(context);
}
if (add || sub) if (add || sub)
{ {
for (int index = 0; index < elems; index++) for (int index = 0; index < elems; index++)
@ -1082,7 +1057,12 @@ namespace ChocolArm64.Instructions
} }
} }
EmitVectorInsertTmp(context, index, op.Size); if (scalar)
{
EmitVectorZeroAll(context, op.Rd);
}
EmitVectorInsert(context, op.Rd, index, op.Size);
} }
} }
else if (accumulate) else if (accumulate)
@ -1103,7 +1083,12 @@ namespace ChocolArm64.Instructions
EmitBinarySatQAccumulate(context, signed); EmitBinarySatQAccumulate(context, signed);
} }
EmitVectorInsertTmp(context, index, op.Size); if (scalar)
{
EmitVectorZeroAll(context, op.Rd);
}
EmitVectorInsert(context, op.Rd, index, op.Size);
} }
} }
else else
@ -1117,14 +1102,16 @@ namespace ChocolArm64.Instructions
EmitSatQ(context, op.Size, true, signed); EmitSatQ(context, op.Size, true, signed);
EmitVectorInsertTmp(context, index, op.Size); if (scalar)
{
EmitVectorZeroAll(context, op.Rd);
}
EmitVectorInsert(context, op.Rd, index, op.Size);
} }
} }
context.EmitLdvectmp(); if (op.RegisterSize == RegisterSize.Simd64)
context.EmitStvec(op.Rd);
if ((op.RegisterSize == RegisterSize.Simd64) || scalar)
{ {
EmitVectorZeroUpper(context, op.Rd); EmitVectorZeroUpper(context, op.Rd);
} }
@ -1190,7 +1177,7 @@ namespace ChocolArm64.Instructions
// TSrc (16bit, 32bit, 64bit; signed, unsigned) > TDst (8bit, 16bit, 32bit; signed, unsigned). // TSrc (16bit, 32bit, 64bit; signed, unsigned) > TDst (8bit, 16bit, 32bit; signed, unsigned).
public static void EmitSatQ(ILEmitterCtx context, int sizeDst, bool signedSrc, bool signedDst) public static void EmitSatQ(ILEmitterCtx context, int sizeDst, bool signedSrc, bool signedDst)
{ {
if ((uint)sizeDst > 2) if ((uint)sizeDst > 2u)
{ {
throw new ArgumentOutOfRangeException(nameof(sizeDst)); throw new ArgumentOutOfRangeException(nameof(sizeDst));
} }
@ -1381,7 +1368,7 @@ namespace ChocolArm64.Instructions
if (Optimizations.UseSse) if (Optimizations.UseSse)
{ {
//TODO: Use Sse2.MoveScalar once it is fixed, //TODO: Use Sse2.MoveScalar once it is fixed,
//as of the time of writing it just crashes the JIT (SDK 2.1.503). //as of the time of writing it just crashes the JIT (SDK 2.1.504).
/*Type[] typesMov = new Type[] { typeof(Vector128<ulong>) }; /*Type[] typesMov = new Type[] { typeof(Vector128<ulong>) };