From c5d76ee79aa7943b72c077df56342e8bb2c322bf Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Sat, 14 Jul 2018 21:05:58 +0200
Subject: [PATCH] Update AInstEmitSimdHelper.cs

---
 ChocolArm64/Instruction/AInstEmitSimdHelper.cs | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
index 1f7a2dad13..7716e2987a 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs
@@ -813,6 +813,7 @@ namespace ChocolArm64.Instruction
             AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp;
 
             int Elems = !Scalar ? 8 >> Op.Size : 1;
+
             int ESize = 8 << Op.Size;
 
             int Part = !Scalar && (Op.RegisterSize == ARegisterSize.SIMD128) ? Elems : 0;
@@ -823,6 +824,12 @@ namespace ChocolArm64.Instruction
             Context.EmitLdc_I8(0L);
             Context.EmitSttmp();
 
+            if (Part != 0)
+            {
+                Context.EmitLdvec(Op.Rd);
+                Context.EmitStvectmp();
+            }
+
             for (int Index = 0; Index < Elems; Index++)
             {
                 AILLabel LblLe    = new AILLabel();
@@ -867,9 +874,12 @@ namespace ChocolArm64.Instruction
                     EmitVectorZeroLower(Context, Op.Rd);
                 }
 
-                EmitVectorInsert(Context, Op.Rd, Part + Index, Op.Size);
+                EmitVectorInsertTmp(Context, Part + Index, Op.Size);
             }
 
+            Context.EmitLdvectmp();
+            Context.EmitStvec(Op.Rd);
+
             if (Part == 0)
             {
                 EmitVectorZeroUpper(Context, Op.Rd);