From c5ff4fac01985296ac0439c6c9feaf24cb6f36fc Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Wed, 29 Aug 2018 00:13:24 +0200
Subject: [PATCH] Update AInstEmitSimdArithmetic.cs

---
 .../Instruction/AInstEmitSimdArithmetic.cs        | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
index 76547d0f1a..a291a7e51d 100644
--- a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
+++ b/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
@@ -1032,6 +1032,11 @@ namespace ChocolArm64.Instruction
             EmitAddLongPairwise(Context, Signed: true, Accumulate: true);
         }
 
+        public static void Saddl_V(AILEmitterCtx Context)
+        {
+            EmitVectorWidenRnRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Add));
+        }
+
         public static void Saddlp_V(AILEmitterCtx Context)
         {
             EmitAddLongPairwise(Context, Signed: true, Accumulate: false);
@@ -1217,6 +1222,11 @@ namespace ChocolArm64.Instruction
             });
         }
 
+        public static void Ssubl_V(AILEmitterCtx Context)
+        {
+            EmitVectorWidenRnRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Sub));
+        }
+
         public static void Ssubw_V(AILEmitterCtx Context)
         {
             EmitVectorWidenRmBinaryOpSx(Context, () => Context.Emit(OpCodes.Sub));
@@ -1468,6 +1478,11 @@ namespace ChocolArm64.Instruction
             EmitVectorSaturatingBinaryOpZx(Context, SaturatingFlags.Accumulate);
         }
 
+        public static void Usubl_V(AILEmitterCtx Context)
+        {
+            EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));
+        }
+
         public static void Usubw_V(AILEmitterCtx Context)
         {
             EmitVectorWidenRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Sub));