diff --git a/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs b/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs index 5ae7e493f1..65901e80cc 100644 --- a/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs +++ b/ARMeilleure/CodeGen/RegisterAllocators/CopyResolver.cs @@ -45,16 +45,13 @@ namespace ARMeilleure.CodeGen.RegisterAllocators Dictionary types = new Dictionary(); Queue pendingQueue = new Queue(); - - Queue readyQueue = new Queue(); + Queue readyQueue = new Queue(); foreach (Copy copy in _copies) { locations[copy.Source] = copy.Source; - - sources[copy.Dest] = copy.Source; - - types[copy.Dest] = copy.Type; + sources[copy.Dest] = copy.Source; + types[copy.Dest] = copy.Type; pendingQueue.Enqueue(copy.Dest); } diff --git a/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs b/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs index c04e492515..9a827420bb 100644 --- a/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs +++ b/ARMeilleure/CodeGen/RegisterAllocators/HybridAllocator.cs @@ -11,7 +11,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators class HybridAllocator : IRegisterAllocator { private const int RegistersCount = 16; - private const int MaxIROperands = 4; + private const int MaxIROperands = 4; private struct BlockInfo { @@ -323,7 +323,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators private static int SelectSpillTemps(int mask0, int mask1) { int selection = 0; - int count = 0; + int count = 0; while (count < MaxIROperands && mask0 != 0) { diff --git a/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs b/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs index 4eec2eca37..6d5ecc1416 100644 --- a/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs +++ b/ARMeilleure/CodeGen/RegisterAllocators/LinearScanAllocator.cs @@ -267,8 +267,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators int availableRegisters = context.Masks.GetAvailableRegisters(regType); - int[] usePositions = new int[RegistersCount]; - + int[] usePositions = new int[RegistersCount]; int[] blockedPositions = new int[RegistersCount]; for (int index = 0; index < RegistersCount; index++) @@ -425,8 +424,7 @@ namespace ARMeilleure.CodeGen.RegisterAllocators if (higuest < current) { - higuest = current; - + higuest = current; selected = index; if (current == int.MaxValue) diff --git a/ARMeilleure/CodeGen/X86/Assembler.cs b/ARMeilleure/CodeGen/X86/Assembler.cs index 3733bfce5a..c64838945f 100644 --- a/ARMeilleure/CodeGen/X86/Assembler.cs +++ b/ARMeilleure/CodeGen/X86/Assembler.cs @@ -7,13 +7,11 @@ namespace ARMeilleure.CodeGen.X86 { class Assembler { - private const int BadOp = 0; - + private const int BadOp = 0; private const int OpModRMBits = 24; private const byte RexPrefix = 0x40; private const byte RexWPrefix = 0x48; - private const byte LockPrefix = 0xf0; [Flags] @@ -1036,8 +1034,7 @@ namespace ARMeilleure.CodeGen.X86 } } - bool needsSibByte = false; - + bool needsSibByte = false; bool needsDisplacement = false; int sib = 0; @@ -1049,8 +1046,7 @@ namespace ARMeilleure.CodeGen.X86 X86Register baseRegLow = (X86Register)(baseReg.Index & 0b111); - needsSibByte = memOp.Index != null || baseRegLow == X86Register.Rsp; - + needsSibByte = memOp.Index != null || baseRegLow == X86Register.Rsp; needsDisplacement = memOp.Displacement != 0 || baseRegLow == X86Register.Rbp; if (needsDisplacement) diff --git a/ARMeilleure/CodeGen/X86/CodeGenContext.cs b/ARMeilleure/CodeGen/X86/CodeGenContext.cs index 81f7cec0e4..d719b51640 100644 --- a/ARMeilleure/CodeGen/X86/CodeGenContext.cs +++ b/ARMeilleure/CodeGen/X86/CodeGenContext.cs @@ -116,7 +116,10 @@ namespace ARMeilleure.CodeGen.X86 int frameSize = calleeSaveRegionSize + allocResult.SpillRegionSize; - int callArgsAndFrameSize = frameSize + argsCount * 16; //FIXME * 16 => calc + // TODO: Instead of always multiplying by 16 (the largest possible size of a variable, + // since a V128 has 16 bytes), we should calculate the exact size consumed by the + // arguments passed to the called functions on the stack. + int callArgsAndFrameSize = frameSize + argsCount * 16; // Ensure that the Stack Pointer will be aligned to 16 bytes. callArgsAndFrameSize = (callArgsAndFrameSize + 0xf) & ~0xf; diff --git a/ARMeilleure/CodeGen/X86/CodeGenerator.cs b/ARMeilleure/CodeGen/X86/CodeGenerator.cs index d13dab8409..f5ce4503e8 100644 --- a/ARMeilleure/CodeGen/X86/CodeGenerator.cs +++ b/ARMeilleure/CodeGen/X86/CodeGenerator.cs @@ -1090,7 +1090,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateVectorExtract(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; //Value + Operand dest = operation.Destination; //Value Operand src1 = operation.GetSource(0); //Vector Operand src2 = operation.GetSource(1); //Index @@ -1176,7 +1176,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateVectorExtract16(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; //Value + Operand dest = operation.Destination; //Value Operand src1 = operation.GetSource(0); //Vector Operand src2 = operation.GetSource(1); //Index @@ -1192,7 +1192,7 @@ namespace ARMeilleure.CodeGen.X86 private static void GenerateVectorExtract8(CodeGenContext context, Operation operation) { - Operand dest = operation.Destination; //Value + Operand dest = operation.Destination; //Value Operand src1 = operation.GetSource(0); //Vector Operand src2 = operation.GetSource(1); //Index @@ -1308,7 +1308,6 @@ namespace ARMeilleure.CodeGen.X86 int mask1 = 0b11_10_01_00; mask0 = BitUtils.RotateRight(mask0, index * 2, 8); - //mask1 = BitUtils.RotateLeft (mask1, index * 2, 8); mask1 = BitUtils.RotateRight(mask1, 8 - index * 2, 8); context.Assembler.Pshufd(src1, src1, (byte)mask0); // Lane to be inserted in position 0. diff --git a/ARMeilleure/Decoders/OpCode32BImm.cs b/ARMeilleure/Decoders/OpCode32BImm.cs index 100977dbb3..ea6443bc80 100644 --- a/ARMeilleure/Decoders/OpCode32BImm.cs +++ b/ARMeilleure/Decoders/OpCode32BImm.cs @@ -8,7 +8,7 @@ namespace ARMeilleure.Decoders { uint pc = GetPc(); - // When the codition is never, the instruction is BLX to Thumb mode. + // When the condition is never, the instruction is BLX to Thumb mode. if (Cond != Condition.Nv) { pc &= ~3u; diff --git a/ARMeilleure/Decoders/OpCode32Mem.cs b/ARMeilleure/Decoders/OpCode32Mem.cs index 27c1b27009..f4e88d5924 100644 --- a/ARMeilleure/Decoders/OpCode32Mem.cs +++ b/ARMeilleure/Decoders/OpCode32Mem.cs @@ -4,8 +4,8 @@ namespace ARMeilleure.Decoders { class OpCode32Mem : OpCode32, IOpCode32Mem { - public int Rt { get; private set; } - public int Rn { get; private set; } + public int Rt { get; private set; } + public int Rn { get; private set; } public int Immediate { get; protected set; } diff --git a/ARMeilleure/Decoders/OpCodeAdr.cs b/ARMeilleure/Decoders/OpCodeAdr.cs index 3c4afa5741..fc8219f6c6 100644 --- a/ARMeilleure/Decoders/OpCodeAdr.cs +++ b/ARMeilleure/Decoders/OpCodeAdr.cs @@ -2,7 +2,8 @@ namespace ARMeilleure.Decoders { class OpCodeAdr : OpCode { - public int Rd { get; private set; } + public int Rd { get; private set; } + public long Immediate { get; private set; } public OpCodeAdr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) diff --git a/ARMeilleure/Decoders/OpCodeMov.cs b/ARMeilleure/Decoders/OpCodeMov.cs index 6cf353e280..b65178cff3 100644 --- a/ARMeilleure/Decoders/OpCodeMov.cs +++ b/ARMeilleure/Decoders/OpCodeMov.cs @@ -2,9 +2,11 @@ namespace ARMeilleure.Decoders { class OpCodeMov : OpCode { - public int Rd { get; private set; } + public int Rd { get; private set; } + public long Immediate { get; private set; } - public int Bit { get; private set; } + + public int Bit { get; private set; } public OpCodeMov(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { @@ -18,11 +20,12 @@ namespace ARMeilleure.Decoders return; } - Rd = (opCode >> 0) & 0x1f; + Rd = (opCode >> 0) & 0x1f; Immediate = (opCode >> 5) & 0xffff; - Bit = (opCode >> 21) & 0x3; + Bit = (opCode >> 21) & 0x3; Bit <<= 4; + Immediate <<= Bit; RegisterSize = (opCode >> 31) != 0 diff --git a/ARMeilleure/Decoders/OpCodeT16AluImm8.cs b/ARMeilleure/Decoders/OpCodeT16AluImm8.cs index 35d1a3bbab..197d3b091f 100644 --- a/ARMeilleure/Decoders/OpCodeT16AluImm8.cs +++ b/ARMeilleure/Decoders/OpCodeT16AluImm8.cs @@ -13,8 +13,8 @@ namespace ARMeilleure.Decoders public OpCodeT16AluImm8(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Immediate = (opCode >> 0) & 0xff; - _rdn = (opCode >> 8) & 0x7; + Immediate = (opCode >> 0) & 0xff; + _rdn = (opCode >> 8) & 0x7; } } } \ No newline at end of file diff --git a/Ryujinx/Config.jsonc b/Ryujinx/Config.jsonc index f6f5743c45..637e91c962 100644 --- a/Ryujinx/Config.jsonc +++ b/Ryujinx/Config.jsonc @@ -56,9 +56,6 @@ // Use old ChocolArm64 ARM emulator "enable_legacy_jit": false, - // Enable or disable aggressive CPU optimizations - "enable_aggressive_cpu_opts": true, - // Enable or disable ignoring missing services, this may cause instability "ignore_missing_services": false, diff --git a/Ryujinx/Configuration.cs b/Ryujinx/Configuration.cs index 98684ae991..0d5392d9ae 100644 --- a/Ryujinx/Configuration.cs +++ b/Ryujinx/Configuration.cs @@ -113,11 +113,6 @@ namespace Ryujinx /// public bool EnableLegacyJit { get; private set; } - /// - /// Enable or Disable aggressive CPU optimizations - /// - public bool EnableAggressiveCpuOpts { get; private set; } - /// /// Enable or disable ignoring missing services /// @@ -247,11 +242,6 @@ namespace Ryujinx device.System.UseLegacyJit = Instance.EnableLegacyJit; - if (Instance.EnableAggressiveCpuOpts) - { - Optimizations.AssumeStrictAbiCompliance = true; - } - ServiceConfiguration.IgnoreMissingServices = Instance.IgnoreMissingServices; if (Instance.GamepadControls.Enabled) diff --git a/Ryujinx/_schema.json b/Ryujinx/_schema.json index 83bb9cb842..021728d2d9 100644 --- a/Ryujinx/_schema.json +++ b/Ryujinx/_schema.json @@ -21,7 +21,6 @@ "enable_fs_integrity_checks", "fs_global_access_log_mode", "enable_legacy_jit", - "enable_aggressive_cpu_opts", "controller_type", "enable_keyboard", "keyboard_controls", @@ -463,17 +462,6 @@ false ] }, - "enable_aggressive_cpu_opts": { - "$id": "#/properties/enable_aggressive_cpu_opts", - "type": "boolean", - "title": "Enable Aggressive CPU Optimizations", - "description": "Enable or disable aggressive CPU optimizations", - "default": true, - "examples": [ - true, - false - ] - }, "ignore_missing_services": { "$id": "#/properties/ignore_missing_services", "type": "boolean",