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Update AInstEmitSimdMove.cs

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LDj3SNuD 2018-10-13 01:08:33 +02:00 • committed by GitHub
commit d1f6e97fb0
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1 changed files with 13 additions and 1 deletions
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14
ChocolArm64/Instruction/AInstEmitSimdMove.cs
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@ -249,6 +249,17 @@ namespace ChocolArm64.Instruction
EmitVectorImmUnaryOp(Context, () => Context.Emit(OpCodes.Not)); EmitVectorImmUnaryOp(Context, () => Context.Emit(OpCodes.Not));
} }
public static void Smov_S(AILEmitterCtx Context)
{
AOpCodeSimdIns Op = (AOpCodeSimdIns)Context.CurrOp;
EmitVectorExtractSx(Context, Op.Rn, Op.DstIndex, Op.Size);
EmitIntZeroUpperIfNeeded(Context);
Context.EmitStintzr(Op.Rd);
}
public static void Tbl_V(AILEmitterCtx Context) public static void Tbl_V(AILEmitterCtx Context)
{ {
AOpCodeSimdTbl Op = (AOpCodeSimdTbl)Context.CurrOp; AOpCodeSimdTbl Op = (AOpCodeSimdTbl)Context.CurrOp;
@ -421,7 +432,8 @@ namespace ChocolArm64.Instruction
private static void EmitIntZeroUpperIfNeeded(AILEmitterCtx Context) private static void EmitIntZeroUpperIfNeeded(AILEmitterCtx Context)
{ {
if (Context.CurrOp.RegisterSize == ARegisterSize.Int32) if (Context.CurrOp.RegisterSize == ARegisterSize.Int32 ||
Context.CurrOp.RegisterSize == ARegisterSize.SIMD64)
{ {
Context.Emit(OpCodes.Conv_U4); Context.Emit(OpCodes.Conv_U4);
Context.Emit(OpCodes.Conv_U8); Context.Emit(OpCodes.Conv_U8);