From d78acb3aac52c23abfc6c1e6444f5f5ea7dc934d Mon Sep 17 00:00:00 2001 From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> Date: Sat, 4 Aug 2018 19:10:01 +0200 Subject: [PATCH] Opt. (retest). --- ChocolArm64/Instruction/AInstEmitSimdHelper.cs | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs index e66dae022b..161c44ea26 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs +++ b/ChocolArm64/Instruction/AInstEmitSimdHelper.cs @@ -891,9 +891,9 @@ namespace ChocolArm64.Instruction EmitVectorZeroLowerTmp(Context); } - for (int Index = 0; Index < Elems; Index++) + if (Add || Sub) { - if (Add || Sub) + for (int Index = 0; Index < Elems; Index++) { EmitVectorExtract(Context, Op.Rn, Index, Op.Size, Signed); EmitVectorExtract(Context, ((AOpCodeSimdReg)Op).Rm, Index, Op.Size, Signed); @@ -915,9 +915,13 @@ namespace ChocolArm64.Instruction EmitBinarySatQSub(Context, Signed); } } - } - if (Accumulate) + EmitVectorInsertTmp(Context, Index, Op.Size); + } + } + else if (Accumulate) + { + for (int Index = 0; Index < Elems; Index++) { EmitVectorExtract(Context, Op.Rn, Index, Op.Size, !Signed); EmitVectorExtract(Context, Op.Rd, Index, Op.Size, Signed); @@ -932,9 +936,9 @@ namespace ChocolArm64.Instruction { EmitBinarySatQAccumulate(Context, Signed); } - } - EmitVectorInsertTmp(Context, Index, Op.Size); + EmitVectorInsertTmp(Context, Index, Op.Size); + } } Context.EmitLdvectmp();