From d8c213a2e589a69c498140f7ef27c9ea913f8d6b Mon Sep 17 00:00:00 2001 From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> Date: Wed, 15 Aug 2018 02:27:35 +0200 Subject: [PATCH] Create AInstEmitSimdHash.cs --- ChocolArm64/Instruction/AInstEmitSimdHash.cs | 61 ++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 ChocolArm64/Instruction/AInstEmitSimdHash.cs diff --git a/ChocolArm64/Instruction/AInstEmitSimdHash.cs b/ChocolArm64/Instruction/AInstEmitSimdHash.cs new file mode 100644 index 0000000000..6b642acb58 --- /dev/null +++ b/ChocolArm64/Instruction/AInstEmitSimdHash.cs @@ -0,0 +1,61 @@ +using ChocolArm64.Decoder; +using ChocolArm64.Translation; + +namespace ChocolArm64.Instruction +{ + static partial class AInstEmit + { +#region "Sha256" + public static void Sha256h_V(AILEmitterCtx Context) + { + AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp; + + Context.EmitLdvec(Op.Rd); + Context.EmitLdvec(Op.Rn); + Context.EmitLdvec(Op.Rm); + + ASoftFallback.EmitCall(Context, nameof(ASoftFallback.HashLower)); + + Context.EmitStvec(Op.Rd); + } + + public static void Sha256h2_V(AILEmitterCtx Context) + { + AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp; + + Context.EmitLdvec(Op.Rd); + Context.EmitLdvec(Op.Rn); + Context.EmitLdvec(Op.Rm); + + ASoftFallback.EmitCall(Context, nameof(ASoftFallback.HashUpper)); + + Context.EmitStvec(Op.Rd); + } + + public static void Sha256su0_V(AILEmitterCtx Context) + { + AOpCodeSimd Op = (AOpCodeSimd)Context.CurrOp; + + Context.EmitLdvec(Op.Rd); + Context.EmitLdvec(Op.Rn); + + ASoftFallback.EmitCall(Context, nameof(ASoftFallback.SchedulePart1)); + + Context.EmitStvec(Op.Rd); + } + + public static void Sha256su1_V(AILEmitterCtx Context) + { + AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp; + + Context.EmitLdvec(Op.Rd); + Context.EmitLdvec(Op.Rn); + Context.EmitLdvec(Op.Rm); + + ASoftFallback.EmitCall(Context, nameof(ASoftFallback.SchedulePart2)); + + Context.EmitStvec(Op.Rd); + } +#endregion + } +}