Update CpuTestSimdShImm.cs
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@ -194,6 +194,24 @@ namespace Ryujinx.Tests.Cpu
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};
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}
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private static uint[] _SU_Cvt_F_V_Fixed_2S_4S_()
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{
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return new uint[]
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{
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0x0F20E400u, // SCVTF V0.2S, V0.2S, #32
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0x2F20E400u // UCVTF V0.2S, V0.2S, #32
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};
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}
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private static uint[] _SU_Cvt_F_V_Fixed_2D_()
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{
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return new uint[]
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{
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0x4F40E400u, // SCVTF V0.2D, V0.2D, #64
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0x6F40E400u // UCVTF V0.2D, V0.2D, #64
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};
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}
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private static uint[] _SU_Shll_V_8B8H_16B8H_()
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{
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return new uint[]
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@ -454,6 +472,50 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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}
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[Test, Pairwise] [Explicit]
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public void SU_Cvt_F_V_Fixed_2S_4S([ValueSource("_SU_Cvt_F_V_Fixed_2S_4S_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong z,
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[ValueSource("_2S_")] [Random(RndCnt)] ulong a,
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[Values(1u, 32u)] [Random(2u, 31u, RndCntFBits)] uint fBits,
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[Values(0b0u, 0b1u)] uint q) // <2S, 4S>
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{
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uint immHb = (64 - fBits) & 0x7F;
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (immHb << 16);
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opcodes |= ((q & 1) << 30);
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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Vector128<float> v1 = MakeVectorE0E1(a, a * q);
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SingleOpcode(opcodes, v0: v0, v1: v1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise] [Explicit]
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public void SU_Cvt_F_V_Fixed_2D([ValueSource("_SU_Cvt_F_V_Fixed_2D_")] uint opcodes,
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[Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong z,
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[ValueSource("_1D_")] [Random(RndCnt)] ulong a,
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[Values(1u, 64u)] [Random(2u, 63u, RndCntFBits)] uint fBits)
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{
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uint immHb = (128 - fBits) & 0x7F;
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opcodes |= ((rn & 31) << 5) | ((rd & 31) << 0);
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opcodes |= (immHb << 16);
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Vector128<float> v0 = MakeVectorE0E1(z, z);
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Vector128<float> v1 = MakeVectorE0E1(a, a);
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SingleOpcode(opcodes, v0: v0, v1: v1);
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CompareAgainstUnicorn(fpTolerances: FpTolerances.UpToOneUlpsD); // unsigned
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}
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[Test, Pairwise, Description("SHL <V><d>, <V><n>, #<shift>")]
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public void Shl_S_D([Values(0u)] uint rd,
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[Values(1u, 0u)] uint rn,
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