Update CpuTestSimdReg.cs
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1 changed files with 59 additions and 51 deletions
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@ -112,11 +112,11 @@ namespace Ryujinx.Tests.Cpu
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for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
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{
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ulong Grbg = TestContext.CurrentContext.Random.NextUInt();
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ulong Val1 = GenNormal_S();
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ulong Val2 = GenSubNormal_S();
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ulong Rnd1 = GenNormal_S();
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ulong Rnd2 = GenSubNormal_S();
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yield return (Grbg << 32) | Val1;
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yield return (Grbg << 32) | Val2;
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yield return (Grbg << 32) | Rnd1;
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yield return (Grbg << 32) | Rnd2;
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}
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}
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@ -153,11 +153,11 @@ namespace Ryujinx.Tests.Cpu
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for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
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{
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ulong Val1 = GenNormal_S();
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ulong Val2 = GenSubNormal_S();
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ulong Rnd1 = GenNormal_S();
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ulong Rnd2 = GenSubNormal_S();
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yield return (Val1 << 32) | Val1;
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yield return (Val2 << 32) | Val2;
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yield return (Rnd1 << 32) | Rnd1;
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yield return (Rnd2 << 32) | Rnd2;
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}
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}
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@ -194,53 +194,61 @@ namespace Ryujinx.Tests.Cpu
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for (int Cnt = 1; Cnt <= RndCnt; Cnt++)
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{
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ulong Val1 = GenNormal_D();
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ulong Val2 = GenSubNormal_D();
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ulong Rnd1 = GenNormal_D();
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ulong Rnd2 = GenSubNormal_D();
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yield return Val1;
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yield return Val2;
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yield return Rnd1;
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yield return Rnd2;
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}
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}
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _F_Max_Min_S_S_()
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private static uint[] _F_Max_Min_Nm_S_S_()
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{
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return new uint[]
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{
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0x1E224820u, // FMAX S0, S1, S2
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0x1E225820u // FMIN S0, S1, S2
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0x1E224820u, // FMAX S0, S1, S2
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0x1E226820u, // FMAXNM S0, S1, S2
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0x1E225820u, // FMIN S0, S1, S2
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0x1E227820u // FMINNM S0, S1, S2
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};
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}
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private static uint[] _F_Max_Min_S_D_()
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private static uint[] _F_Max_Min_Nm_S_D_()
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{
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return new uint[]
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{
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0x1E624820u, // FMAX D0, D1, D2
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0x1E625820u // FMIN D0, D1, D2
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0x1E624820u, // FMAX D0, D1, D2
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0x1E626820u, // FMAXNM D0, D1, D2
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0x1E625820u, // FMIN D0, D1, D2
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0x1E627820u // FMINNM D0, D1, D2
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};
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}
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private static uint[] _F_Max_Min_P_V_2S_4S_()
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private static uint[] _F_Max_Min_Nm_P_V_2S_4S_()
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{
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return new uint[]
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{
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0x0E20F400u, // FMAX V0.2S, V0.2S, V0.2S
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0x2E20F400u, // FMAXP V0.2S, V0.2S, V0.2S
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0x0EA0F400u, // FMIN V0.2S, V0.2S, V0.2S
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0x2EA0F400u // FMINP V0.2S, V0.2S, V0.2S
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0x0E20F400u, // FMAX V0.2S, V0.2S, V0.2S
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0x0E20C400u, // FMAXNM V0.2S, V0.2S, V0.2S
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0x2E20F400u, // FMAXP V0.2S, V0.2S, V0.2S
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0x0EA0F400u, // FMIN V0.2S, V0.2S, V0.2S
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0x0EA0C400u, // FMINNM V0.2S, V0.2S, V0.2S
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0x2EA0F400u // FMINP V0.2S, V0.2S, V0.2S
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};
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}
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private static uint[] _F_Max_Min_P_V_2D_()
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private static uint[] _F_Max_Min_Nm_P_V_2D_()
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{
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return new uint[]
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{
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0x4E60F400u, // FMAX V0.2D, V0.2D, V0.2D
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0x6E60F400u, // FMAXP V0.2D, V0.2D, V0.2D
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0x4EE0F400u, // FMIN V0.2D, V0.2D, V0.2D
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0x6EE0F400u // FMINP V0.2D, V0.2D, V0.2D
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0x4E60F400u, // FMAX V0.2D, V0.2D, V0.2D
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0x4E60C400u, // FMAXNM V0.2D, V0.2D, V0.2D
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0x6E60F400u, // FMAXP V0.2D, V0.2D, V0.2D
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0x4EE0F400u, // FMIN V0.2D, V0.2D, V0.2D
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0x4EE0C400u, // FMINNM V0.2D, V0.2D, V0.2D
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0x6EE0F400u // FMINP V0.2D, V0.2D, V0.2D
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};
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}
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#endregion
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@ -1048,7 +1056,7 @@ namespace Ryujinx.Tests.Cpu
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, V3: V3/*, Fpcr: Fpcr*/);
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CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IOC, */FpSkips: FpSkips.IfNaN_S);
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CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IOC, */FpSkips: FpSkips.IfNaN_S/*, FpUseTolerance: FpUseTolerance.OneUlps_S*/);
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}
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[Test, Pairwise, Description("FMADD <Dd>, <Dn>, <Dm>, <Da>")]
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@ -1066,13 +1074,13 @@ namespace Ryujinx.Tests.Cpu
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2, V3: V3);
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CompareAgainstUnicorn(FpSkips: FpSkips.IfNaN_D);
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CompareAgainstUnicorn(FpSkips: FpSkips.IfNaN_D/*, FpUseTolerance: FpUseTolerance.OneUlps_D*/);
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}
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[Test, Pairwise]
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public void F_Max_Min_S_S([ValueSource("_F_Max_Min_S_S_")] uint Opcodes,
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[ValueSource("_1S_F_")] ulong A,
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[ValueSource("_1S_F_")] ulong B)
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public void F_Max_Min_Nm_S_S([ValueSource("_F_Max_Min_Nm_S_S_")] uint Opcodes,
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[ValueSource("_1S_F_")] ulong A,
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[ValueSource("_1S_F_")] ulong B)
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{
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//const int DNFlagBit = 25; // Default NaN mode control bit.
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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@ -1091,9 +1099,9 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise]
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public void F_Max_Min_S_D([ValueSource("_F_Max_Min_S_D_")] uint Opcodes,
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[ValueSource("_1D_F_")] ulong A,
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[ValueSource("_1D_F_")] ulong B)
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public void F_Max_Min_Nm_S_D([ValueSource("_F_Max_Min_Nm_S_D_")] uint Opcodes,
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[ValueSource("_1D_F_")] ulong A,
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[ValueSource("_1D_F_")] ulong B)
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{
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ulong Z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> V0 = MakeVectorE1(Z);
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@ -1106,14 +1114,14 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise]
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public void F_Max_Min_P_V_2S_4S([ValueSource("_F_Max_Min_P_V_2S_4S_")] uint Opcodes,
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[Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[Values(2u, 0u)] uint Rm,
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[ValueSource("_2S_F_")] ulong Z,
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[ValueSource("_2S_F_")] ulong A,
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[ValueSource("_2S_F_")] ulong B,
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[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
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public void F_Max_Min_Nm_P_V_2S_4S([ValueSource("_F_Max_Min_Nm_P_V_2S_4S_")] uint Opcodes,
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[Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[Values(2u, 0u)] uint Rm,
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[ValueSource("_2S_F_")] ulong Z,
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[ValueSource("_2S_F_")] ulong A,
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[ValueSource("_2S_F_")] ulong B,
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[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
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{
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//const int DNFlagBit = 25; // Default NaN mode control bit.
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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@ -1134,13 +1142,13 @@ namespace Ryujinx.Tests.Cpu
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}
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[Test, Pairwise]
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public void F_Max_Min_P_V_2D([ValueSource("_F_Max_Min_P_V_2D_")] uint Opcodes,
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[Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[Values(2u, 0u)] uint Rm,
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[ValueSource("_1D_F_")] ulong Z,
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[ValueSource("_1D_F_")] ulong A,
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[ValueSource("_1D_F_")] ulong B)
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public void F_Max_Min_Nm_P_V_2D([ValueSource("_F_Max_Min_Nm_P_V_2D_")] uint Opcodes,
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[Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[Values(2u, 0u)] uint Rm,
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[ValueSource("_1D_F_")] ulong Z,
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[ValueSource("_1D_F_")] ulong A,
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[ValueSource("_1D_F_")] ulong B)
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{
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Opcodes |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
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