From dd778df1ed5441cd85b786c1d5ce84412311913a Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Fri, 5 Oct 2018 00:33:06 +0200
Subject: [PATCH] Update CpuTestSimdReg.cs

---
 Ryujinx.Tests/Cpu/CpuTestSimdReg.cs | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
index 8c8a066734..7d47416f0c 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
@@ -1151,7 +1151,7 @@ namespace Ryujinx.Tests.Cpu
 
             AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, V2: V2, Fpcr: Fpcr);
 
-            CompareAgainstUnicorn(FPSR.IOC | FPSR.DZC);
+            CompareAgainstUnicorn(FpsrMask: FPSR.IOC | FPSR.DZC);
         }
 
         [Test, Pairwise]
@@ -1168,7 +1168,7 @@ namespace Ryujinx.Tests.Cpu
 
             AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, V2: V2, Fpcr: Fpcr);
 
-            CompareAgainstUnicorn(FPSR.IOC | FPSR.DZC);
+            CompareAgainstUnicorn(FpsrMask: FPSR.IOC | FPSR.DZC);
         }
 
         [Test, Pairwise]
@@ -1192,7 +1192,7 @@ namespace Ryujinx.Tests.Cpu
 
             AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, V2: V2, Fpcr: Fpcr);
 
-            CompareAgainstUnicorn(FPSR.IOC | FPSR.DZC);
+            CompareAgainstUnicorn(FpsrMask: FPSR.IOC | FPSR.DZC);
         }
 
         [Test, Pairwise]
@@ -1214,7 +1214,7 @@ namespace Ryujinx.Tests.Cpu
 
             AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1, V2: V2, Fpcr: Fpcr);
 
-            CompareAgainstUnicorn(FPSR.IOC | FPSR.DZC);
+            CompareAgainstUnicorn(FpsrMask: FPSR.IOC | FPSR.DZC);
         }
 
         [Test, Pairwise] // Fused.