From ded51fdb070957610a33faada1bf5c4d1e02e7ab Mon Sep 17 00:00:00 2001 From: Alex Barney Date: Tue, 30 Oct 2018 12:27:01 -0500 Subject: [PATCH] Remove prefix from ChocolArm64 classes - Part 1 --- ChocolArm64/AOpCodeTable.cs | 713 ------------------ ChocolArm64/AThread.cs | 6 +- ChocolArm64/{ABitUtils.cs => BitUtils.cs} | 2 +- ChocolArm64/Decoder/ADecoder.cs | 70 +- ChocolArm64/Decoder/AOpCode.cs | 20 +- ChocolArm64/Decoder/AOpCodeBImm.cs | 11 - ChocolArm64/Decoder/AOpCodeBImmAl.cs | 12 - ChocolArm64/Decoder/AOpCodeBImmCmp.cs | 21 - ChocolArm64/Decoder/AOpCodeBImmCond.cs | 25 - ChocolArm64/Decoder/AOpCodeCcmpImm.cs | 11 - ChocolArm64/Decoder/AOpCodeCcmpReg.cs | 15 - ChocolArm64/Decoder/AOpCodeCsel.cs | 17 - ChocolArm64/Decoder/AOpCodeSimdFcond.cs | 17 - ChocolArm64/Decoder/AOpCodeSimdShImm.cs | 16 - ChocolArm64/Decoder/{ABlock.cs => Block.cs} | 10 +- ChocolArm64/Decoder/{ACond.cs => Cond.cs} | 2 +- ChocolArm64/Decoder/{ADataOp.cs => DataOp.cs} | 2 +- .../{ADecoderHelper.cs => DecoderHelper.cs} | 16 +- ChocolArm64/Decoder/IAOpCodeCond.cs | 7 - .../Decoder/{IAOpCode.cs => IOpCode.cs} | 6 +- .../Decoder/{IAOpCodeAlu.cs => IOpCodeAlu.cs} | 4 +- .../{IAOpCodeAluImm.cs => IOpCodeAluImm.cs} | 2 +- .../{IAOpCodeAluRs.cs => IOpCodeAluRs.cs} | 4 +- .../{IAOpCodeAluRx.cs => IOpCodeAluRx.cs} | 4 +- ChocolArm64/Decoder/IOpCodeCond.cs | 7 + .../Decoder/{IAOpCodeLit.cs => IOpCodeLit.cs} | 2 +- .../{IAOpCodeSimd.cs => IOpCodeSimd.cs} | 2 +- .../Decoder/{AIntType.cs => IntType.cs} | 2 +- .../Decoder/{AOpCodeAdr.cs => OpCodeAdr.cs} | 6 +- .../Decoder/{AOpCodeAlu.cs => OpCodeAlu.cs} | 12 +- .../{AOpCodeAluImm.cs => OpCodeAluImm.cs} | 12 +- .../{AOpCodeAluRs.cs => OpCodeAluRs.cs} | 10 +- .../{AOpCodeAluRx.cs => OpCodeAluRx.cs} | 8 +- ChocolArm64/Decoder/OpCodeBImm.cs | 11 + ChocolArm64/Decoder/OpCodeBImmAl.cs | 12 + ChocolArm64/Decoder/OpCodeBImmCmp.cs | 21 + ChocolArm64/Decoder/OpCodeBImmCond.cs | 25 + .../{AOpCodeBImmTest.cs => OpCodeBImmTest.cs} | 6 +- .../Decoder/{AOpCodeBReg.cs => OpCodeBReg.cs} | 6 +- .../Decoder/{AOpCodeBfm.cs => OpCodeBfm.cs} | 8 +- .../Decoder/{AOpCodeCcmp.cs => OpCodeCcmp.cs} | 10 +- ChocolArm64/Decoder/OpCodeCcmpImm.cs | 11 + ChocolArm64/Decoder/OpCodeCcmpReg.cs | 15 + ChocolArm64/Decoder/OpCodeCsel.cs | 17 + ...AOpCodeException.cs => OpCodeException.cs} | 4 +- .../Decoder/{AOpCodeMem.cs => OpCodeMem.cs} | 4 +- .../{AOpCodeMemEx.cs => OpCodeMemEx.cs} | 4 +- .../{AOpCodeMemImm.cs => OpCodeMemImm.cs} | 4 +- .../{AOpCodeMemLit.cs => OpCodeMemLit.cs} | 6 +- .../{AOpCodeMemPair.cs => OpCodeMemPair.cs} | 4 +- .../{AOpCodeMemReg.cs => OpCodeMemReg.cs} | 8 +- .../Decoder/{AOpCodeMov.cs => OpCodeMov.cs} | 10 +- .../Decoder/{AOpCodeMul.cs => OpCodeMul.cs} | 4 +- .../Decoder/{AOpCodeSimd.cs => OpCodeSimd.cs} | 8 +- .../{AOpCodeSimdCvt.cs => OpCodeSimdCvt.cs} | 8 +- .../{AOpCodeSimdExt.cs => OpCodeSimdExt.cs} | 4 +- ChocolArm64/Decoder/OpCodeSimdFcond.cs | 17 + .../{AOpCodeSimdFmov.cs => OpCodeSimdFmov.cs} | 8 +- .../{AOpCodeSimdImm.cs => OpCodeSimdImm.cs} | 10 +- .../{AOpCodeSimdIns.cs => OpCodeSimdIns.cs} | 6 +- ...pCodeSimdMemImm.cs => OpCodeSimdMemImm.cs} | 4 +- ...pCodeSimdMemLit.cs => OpCodeSimdMemLit.cs} | 8 +- ...AOpCodeSimdMemMs.cs => OpCodeSimdMemMs.cs} | 12 +- ...odeSimdMemPair.cs => OpCodeSimdMemPair.cs} | 4 +- ...pCodeSimdMemReg.cs => OpCodeSimdMemReg.cs} | 4 +- ...AOpCodeSimdMemSs.cs => OpCodeSimdMemSs.cs} | 14 +- .../{AOpCodeSimdReg.cs => OpCodeSimdReg.cs} | 4 +- ...odeSimdRegElem.cs => OpCodeSimdRegElem.cs} | 6 +- ...eSimdRegElemF.cs => OpCodeSimdRegElemF.cs} | 6 +- ChocolArm64/Decoder/OpCodeSimdShImm.cs | 16 + .../{AOpCodeSimdTbl.cs => OpCodeSimdTbl.cs} | 4 +- .../{AOpCodeSystem.cs => OpCodeSystem.cs} | 4 +- .../Decoder/{AShiftType.cs => ShiftType.cs} | 2 +- ChocolArm64/Decoder32/A32OpCode.cs | 6 +- ChocolArm64/Decoder32/A32OpCodeBImmAl.cs | 2 +- ...TraceEventArgs.cs => CpuTraceEventArgs.cs} | 4 +- ...EventArgs.cs => InstExceptionEventArgs.cs} | 4 +- ...EventArgs.cs => InstUndefinedEventArgs.cs} | 4 +- ...EventArgs.cs => InvalidAccessEventArgs.cs} | 4 +- ChocolArm64/Instruction/AInst.cs | 20 - ChocolArm64/Instruction/AInstEmitHash.cs | 115 --- ChocolArm64/Instruction/AInstEmitMul.cs | 80 -- .../Instruction/AInstEmitSimdCrypto.cs | 54 -- ChocolArm64/Instruction/AInstEmitSimdHash.cs | 140 ---- .../{ACryptoHelper.cs => CryptoHelper.cs} | 6 +- ChocolArm64/Instruction/Inst.cs | 20 + .../{AInstEmitAlu.cs => InstEmitAlu.cs} | 136 ++-- ...tEmitAluHelper.cs => InstEmitAluHelper.cs} | 78 +- .../{AInstEmitBfm.cs => InstEmitBfm.cs} | 48 +- .../{AInstEmitCcmp.cs => InstEmitCcmp.cs} | 24 +- .../{AInstEmitCsel.cs => InstEmitCsel.cs} | 18 +- ...tEmitException.cs => InstEmitException.cs} | 20 +- .../{AInstEmitFlow.cs => InstEmitFlow.cs} | 54 +- ChocolArm64/Instruction/InstEmitHash.cs | 115 +++ .../{AInstEmitMemory.cs => InstEmitMemory.cs} | 72 +- ...nstEmitMemoryEx.cs => InstEmitMemoryEx.cs} | 68 +- ...emoryHelper.cs => InstEmitMemoryHelper.cs} | 20 +- .../{AInstEmitMove.cs => InstEmitMove.cs} | 14 +- ChocolArm64/Instruction/InstEmitMul.cs | 80 ++ ...rithmetic.cs => InstEmitSimdArithmetic.cs} | 584 +++++++------- ...AInstEmitSimdCmp.cs => InstEmitSimdCmp.cs} | 166 ++-- ChocolArm64/Instruction/InstEmitSimdCrypto.cs | 54 ++ ...AInstEmitSimdCvt.cs => InstEmitSimdCvt.cs} | 212 +++--- ChocolArm64/Instruction/InstEmitSimdHash.cs | 140 ++++ ...mitSimdHelper.cs => InstEmitSimdHelper.cs} | 432 +++++------ ...tSimdLogical.cs => InstEmitSimdLogical.cs} | 74 +- ...mitSimdMemory.cs => InstEmitSimdMemory.cs} | 34 +- ...nstEmitSimdMove.cs => InstEmitSimdMove.cs} | 172 ++--- ...tEmitSimdShift.cs => InstEmitSimdShift.cs} | 200 ++--- .../{AInstEmitSystem.cs => InstEmitSystem.cs} | 30 +- .../{AInstEmitter.cs => InstEmitter.cs} | 2 +- ...AInstInterpreter.cs => InstInterpreter.cs} | 2 +- .../{ASoftFallback.cs => SoftFallback.cs} | 80 +- .../{ASoftFloat.cs => SoftFloat.cs} | 494 ++++++------ .../{AVectorHelper.cs => VectorHelper.cs} | 30 +- .../Instruction32/A32InstInterpretHelper.cs | 30 +- ChocolArm64/Memory/AMemory.cs | 8 +- ChocolArm64/Memory/IAMemory.cs | 2 +- ChocolArm64/OpCodeTable.cs | 713 ++++++++++++++++++ .../{AOptimizations.cs => Optimizations.cs} | 2 +- ChocolArm64/State/AThreadState.cs | 30 +- .../{AExecutionMode.cs => ExecutionMode.cs} | 2 +- ChocolArm64/State/{AFpExc.cs => FpExc.cs} | 2 +- ChocolArm64/State/{AFpType.cs => FpType.cs} | 2 +- ChocolArm64/State/{AFpcr.cs => Fpcr.cs} | 2 +- ChocolArm64/State/{AFpsr.cs => Fpsr.cs} | 2 +- ChocolArm64/State/{APState.cs => PState.cs} | 2 +- .../State/{ARegister.cs => Register.cs} | 24 +- .../{ARegisterSize.cs => RegisterSize.cs} | 2 +- .../{ARegisterType.cs => RegisterType.cs} | 2 +- .../State/{ARoundMode.cs => RoundMode.cs} | 2 +- .../{ATranslatedSub.cs => TranslatedSub.cs} | 16 +- ...nslatedSubType.cs => TranslatedSubType.cs} | 2 +- ChocolArm64/Translation/AILBarrier.cs | 7 - ChocolArm64/Translation/AILOpCodeLoad.cs | 75 -- ChocolArm64/Translation/AILOpCodeStore.cs | 75 -- ChocolArm64/Translation/IAILEmit.cs | 7 - ChocolArm64/Translation/IILEmit.cs | 7 + ChocolArm64/Translation/ILBarrier.cs | 7 + .../Translation/{AILBlock.cs => ILBlock.cs} | 40 +- .../{AILEmitter.cs => ILEmitter.cs} | 72 +- .../{AILEmitterCtx.cs => ILEmitterCtx.cs} | 208 ++--- ChocolArm64/Translation/ILGeneratorEx.cs | 2 +- .../Translation/{AILLabel.cs => ILLabel.cs} | 6 +- .../Translation/{AILOpCode.cs => ILOpCode.cs} | 6 +- .../{AILOpCodeBranch.cs => ILOpCodeBranch.cs} | 8 +- .../{AILOpCodeCall.cs => ILOpCodeCall.cs} | 6 +- .../{AILOpCodeConst.cs => ILOpCodeConst.cs} | 14 +- ChocolArm64/Translation/ILOpCodeLoad.cs | 75 ++ .../{AILOpCodeLog.cs => ILOpCodeLog.cs} | 6 +- ChocolArm64/Translation/ILOpCodeStore.cs | 75 ++ .../Translation/{AIoType.cs => IoType.cs} | 2 +- .../{ALocalAlloc.cs => LocalAlloc.cs} | 50 +- ChocolArm64/{ATranslator.cs => Translator.cs} | 44 +- ...ATranslatorCache.cs => TranslatorCache.cs} | 14 +- Ryujinx.Graphics/Memory/NvGpuVmm.cs | 2 +- Ryujinx.Graphics/Texture/ImageUtils.cs | 2 +- Ryujinx.Graphics/Texture/TextureHelper.cs | 2 +- Ryujinx.HLE/HOS/Kernel/SvcHandler.cs | 2 +- Ryujinx.HLE/HOS/Process.cs | 14 +- Ryujinx.Tests/Cpu/CpuTest.cs | 2 +- 161 files changed, 3500 insertions(+), 3500 deletions(-) delete mode 100644 ChocolArm64/AOpCodeTable.cs rename ChocolArm64/{ABitUtils.cs => BitUtils.cs} (97%) delete mode 100644 ChocolArm64/Decoder/AOpCodeBImm.cs delete mode 100644 ChocolArm64/Decoder/AOpCodeBImmAl.cs delete mode 100644 ChocolArm64/Decoder/AOpCodeBImmCmp.cs delete mode 100644 ChocolArm64/Decoder/AOpCodeBImmCond.cs delete mode 100644 ChocolArm64/Decoder/AOpCodeCcmpImm.cs delete mode 100644 ChocolArm64/Decoder/AOpCodeCcmpReg.cs delete mode 100644 ChocolArm64/Decoder/AOpCodeCsel.cs delete mode 100644 ChocolArm64/Decoder/AOpCodeSimdFcond.cs delete mode 100644 ChocolArm64/Decoder/AOpCodeSimdShImm.cs rename ChocolArm64/Decoder/{ABlock.cs => Block.cs} (75%) rename ChocolArm64/Decoder/{ACond.cs => Cond.cs} (95%) rename ChocolArm64/Decoder/{ADataOp.cs => DataOp.cs} (89%) rename ChocolArm64/Decoder/{ADecoderHelper.cs => DecoderHelper.cs} (82%) delete mode 100644 ChocolArm64/Decoder/IAOpCodeCond.cs rename ChocolArm64/Decoder/{IAOpCode.cs => IOpCode.cs} (54%) rename ChocolArm64/Decoder/{IAOpCodeAlu.cs => IOpCodeAlu.cs} (57%) rename ChocolArm64/Decoder/{IAOpCodeAluImm.cs => IOpCodeAluImm.cs} (62%) rename ChocolArm64/Decoder/{IAOpCodeAluRs.cs => IOpCodeAluRs.cs} (55%) rename ChocolArm64/Decoder/{IAOpCodeAluRx.cs => IOpCodeAluRx.cs} (56%) create mode 100644 ChocolArm64/Decoder/IOpCodeCond.cs rename ChocolArm64/Decoder/{IAOpCodeLit.cs => IOpCodeLit.cs} (84%) rename ChocolArm64/Decoder/{IAOpCodeSimd.cs => IOpCodeSimd.cs} (65%) rename ChocolArm64/Decoder/{AIntType.cs => IntType.cs} (91%) rename ChocolArm64/Decoder/{AOpCodeAdr.cs => OpCodeAdr.cs} (59%) rename ChocolArm64/Decoder/{AOpCodeAlu.cs => OpCodeAlu.cs} (53%) rename ChocolArm64/Decoder/{AOpCodeAluImm.cs => OpCodeAluImm.cs} (61%) rename ChocolArm64/Decoder/{AOpCodeAluRs.cs => OpCodeAluRs.cs} (57%) rename ChocolArm64/Decoder/{AOpCodeAluRx.cs => OpCodeAluRx.cs} (53%) create mode 100644 ChocolArm64/Decoder/OpCodeBImm.cs create mode 100644 ChocolArm64/Decoder/OpCodeBImmAl.cs create mode 100644 ChocolArm64/Decoder/OpCodeBImmCmp.cs create mode 100644 ChocolArm64/Decoder/OpCodeBImmCond.cs rename ChocolArm64/Decoder/{AOpCodeBImmTest.cs => OpCodeBImmTest.cs} (59%) rename ChocolArm64/Decoder/{AOpCodeBReg.cs => OpCodeBReg.cs} (68%) rename ChocolArm64/Decoder/{AOpCodeBfm.cs => OpCodeBfm.cs} (67%) rename ChocolArm64/Decoder/{AOpCodeCcmp.cs => OpCodeCcmp.cs} (61%) create mode 100644 ChocolArm64/Decoder/OpCodeCcmpImm.cs create mode 100644 ChocolArm64/Decoder/OpCodeCcmpReg.cs create mode 100644 ChocolArm64/Decoder/OpCodeCsel.cs rename ChocolArm64/Decoder/{AOpCodeException.cs => OpCodeException.cs} (56%) rename ChocolArm64/Decoder/{AOpCodeMem.cs => OpCodeMem.cs} (77%) rename ChocolArm64/Decoder/{AOpCodeMemEx.cs => OpCodeMemEx.cs} (66%) rename ChocolArm64/Decoder/{AOpCodeMemImm.cs => OpCodeMemImm.cs} (91%) rename ChocolArm64/Decoder/{AOpCodeMemLit.cs => OpCodeMemLit.cs} (77%) rename ChocolArm64/Decoder/{AOpCodeMemPair.cs => OpCodeMemPair.cs} (79%) rename ChocolArm64/Decoder/{AOpCodeMemReg.cs => OpCodeMemReg.cs} (60%) rename ChocolArm64/Decoder/{AOpCodeMov.cs => OpCodeMov.cs} (72%) rename ChocolArm64/Decoder/{AOpCodeMul.cs => OpCodeMul.cs} (67%) rename ChocolArm64/Decoder/{AOpCodeSimd.cs => OpCodeSimd.cs} (70%) rename ChocolArm64/Decoder/{AOpCodeSimdCvt.cs => OpCodeSimdCvt.cs} (71%) rename ChocolArm64/Decoder/{AOpCodeSimdExt.cs => OpCodeSimdExt.cs} (56%) create mode 100644 ChocolArm64/Decoder/OpCodeSimdFcond.cs rename ChocolArm64/Decoder/{AOpCodeSimdFmov.cs => OpCodeSimdFmov.cs} (68%) rename ChocolArm64/Decoder/{AOpCodeSimdImm.cs => OpCodeSimdImm.cs} (90%) rename ChocolArm64/Decoder/{AOpCodeSimdIns.cs => OpCodeSimdIns.cs} (79%) rename ChocolArm64/Decoder/{AOpCodeSimdMemImm.cs => OpCodeSimdMemImm.cs} (62%) rename ChocolArm64/Decoder/{AOpCodeSimdMemLit.cs => OpCodeSimdMemLit.cs} (64%) rename ChocolArm64/Decoder/{AOpCodeSimdMemMs.cs => OpCodeSimdMemMs.cs} (77%) rename ChocolArm64/Decoder/{AOpCodeSimdMemPair.cs => OpCodeSimdMemPair.cs} (55%) rename ChocolArm64/Decoder/{AOpCodeSimdMemReg.cs => OpCodeSimdMemReg.cs} (51%) rename ChocolArm64/Decoder/{AOpCodeSimdMemSs.cs => OpCodeSimdMemSs.cs} (84%) rename ChocolArm64/Decoder/{AOpCodeSimdReg.cs => OpCodeSimdReg.cs} (73%) rename ChocolArm64/Decoder/{AOpCodeSimdRegElem.cs => OpCodeSimdRegElem.cs} (71%) rename ChocolArm64/Decoder/{AOpCodeSimdRegElemF.cs => OpCodeSimdRegElemF.cs} (73%) create mode 100644 ChocolArm64/Decoder/OpCodeSimdShImm.cs rename ChocolArm64/Decoder/{AOpCodeSimdTbl.cs => OpCodeSimdTbl.cs} (50%) rename ChocolArm64/Decoder/{AOpCodeSystem.cs => OpCodeSystem.cs} (82%) rename ChocolArm64/Decoder/{AShiftType.cs => ShiftType.cs} (82%) rename ChocolArm64/Events/{ACpuTraceEventArgs.cs => CpuTraceEventArgs.cs} (62%) rename ChocolArm64/Events/{AInstExceptionEventArgs.cs => InstExceptionEventArgs.cs} (67%) rename ChocolArm64/Events/{AInstUndefinedEventArgs.cs => InstUndefinedEventArgs.cs} (67%) rename ChocolArm64/Events/{AInvalidAccessEventArgs.cs => InvalidAccessEventArgs.cs} (60%) delete mode 100644 ChocolArm64/Instruction/AInst.cs delete mode 100644 ChocolArm64/Instruction/AInstEmitHash.cs delete mode 100644 ChocolArm64/Instruction/AInstEmitMul.cs delete mode 100644 ChocolArm64/Instruction/AInstEmitSimdCrypto.cs delete mode 100644 ChocolArm64/Instruction/AInstEmitSimdHash.cs rename ChocolArm64/Instruction/{ACryptoHelper.cs => CryptoHelper.cs} (99%) create mode 100644 ChocolArm64/Instruction/Inst.cs rename ChocolArm64/Instruction/{AInstEmitAlu.cs => InstEmitAlu.cs} (58%) rename ChocolArm64/Instruction/{AInstEmitAluHelper.cs => InstEmitAluHelper.cs} (58%) rename ChocolArm64/Instruction/{AInstEmitBfm.cs => InstEmitBfm.cs} (72%) rename ChocolArm64/Instruction/{AInstEmitCcmp.cs => InstEmitCcmp.cs} (65%) rename ChocolArm64/Instruction/{AInstEmitCsel.cs => InstEmitCsel.cs} (60%) rename ChocolArm64/Instruction/{AInstEmitException.cs => InstEmitException.cs} (76%) rename ChocolArm64/Instruction/{AInstEmitFlow.cs => InstEmitFlow.cs} (68%) create mode 100644 ChocolArm64/Instruction/InstEmitHash.cs rename ChocolArm64/Instruction/{AInstEmitMemory.cs => InstEmitMemory.cs} (69%) rename ChocolArm64/Instruction/{AInstEmitMemoryEx.cs => InstEmitMemoryEx.cs} (59%) rename ChocolArm64/Instruction/{AInstEmitMemoryHelper.cs => InstEmitMemoryHelper.cs} (85%) rename ChocolArm64/Instruction/{AInstEmitMove.cs => InstEmitMove.cs} (62%) create mode 100644 ChocolArm64/Instruction/InstEmitMul.cs rename ChocolArm64/Instruction/{AInstEmitSimdArithmetic.cs => InstEmitSimdArithmetic.cs} (78%) rename ChocolArm64/Instruction/{AInstEmitSimdCmp.cs => InstEmitSimdCmp.cs} (66%) create mode 100644 ChocolArm64/Instruction/InstEmitSimdCrypto.cs rename ChocolArm64/Instruction/{AInstEmitSimdCvt.cs => InstEmitSimdCvt.cs} (65%) create mode 100644 ChocolArm64/Instruction/InstEmitSimdHash.cs rename ChocolArm64/Instruction/{AInstEmitSimdHelper.cs => InstEmitSimdHelper.cs} (64%) rename ChocolArm64/Instruction/{AInstEmitSimdLogical.cs => InstEmitSimdLogical.cs} (77%) rename ChocolArm64/Instruction/{AInstEmitSimdMemory.cs => InstEmitSimdMemory.cs} (78%) rename ChocolArm64/Instruction/{AInstEmitSimdMove.cs => InstEmitSimdMove.cs} (70%) rename ChocolArm64/Instruction/{AInstEmitSimdShift.cs => InstEmitSimdShift.cs} (77%) rename ChocolArm64/Instruction/{AInstEmitSystem.cs => InstEmitSystem.cs} (81%) rename ChocolArm64/Instruction/{AInstEmitter.cs => InstEmitter.cs} (55%) rename ChocolArm64/Instruction/{AInstInterpreter.cs => InstInterpreter.cs} (56%) rename ChocolArm64/Instruction/{ASoftFallback.cs => SoftFallback.cs} (92%) rename ChocolArm64/Instruction/{ASoftFloat.cs => SoftFloat.cs} (77%) rename ChocolArm64/Instruction/{AVectorHelper.cs => VectorHelper.cs} (95%) create mode 100644 ChocolArm64/OpCodeTable.cs rename ChocolArm64/{AOptimizations.cs => Optimizations.cs} (95%) rename ChocolArm64/State/{AExecutionMode.cs => ExecutionMode.cs} (76%) rename ChocolArm64/State/{AFpExc.cs => FpExc.cs} (92%) rename ChocolArm64/State/{AFpType.cs => FpType.cs} (87%) rename ChocolArm64/State/{AFpcr.cs => Fpcr.cs} (90%) rename ChocolArm64/State/{AFpsr.cs => Fpsr.cs} (83%) rename ChocolArm64/State/{APState.cs => PState.cs} (94%) rename ChocolArm64/State/{ARegister.cs => Register.cs} (88%) rename ChocolArm64/State/{ARegisterSize.cs => RegisterSize.cs} (82%) rename ChocolArm64/State/{ARegisterType.cs => RegisterType.cs} (78%) rename ChocolArm64/State/{ARoundMode.cs => RoundMode.cs} (89%) rename ChocolArm64/{ATranslatedSub.cs => TranslatedSub.cs} (89%) rename ChocolArm64/{ATranslatedSubType.cs => TranslatedSubType.cs} (72%) delete mode 100644 ChocolArm64/Translation/AILBarrier.cs delete mode 100644 ChocolArm64/Translation/AILOpCodeLoad.cs delete mode 100644 ChocolArm64/Translation/AILOpCodeStore.cs delete mode 100644 ChocolArm64/Translation/IAILEmit.cs create mode 100644 ChocolArm64/Translation/IILEmit.cs create mode 100644 ChocolArm64/Translation/ILBarrier.cs rename ChocolArm64/Translation/{AILBlock.cs => ILBlock.cs} (52%) rename ChocolArm64/Translation/{AILEmitter.cs => ILEmitter.cs} (59%) rename ChocolArm64/Translation/{AILEmitterCtx.cs => ILEmitterCtx.cs} (62%) rename ChocolArm64/Translation/{AILLabel.cs => ILLabel.cs} (76%) rename ChocolArm64/Translation/{AILOpCode.cs => ILOpCode.cs} (65%) rename ChocolArm64/Translation/{AILOpCodeBranch.cs => ILOpCodeBranch.cs} (61%) rename ChocolArm64/Translation/{AILOpCodeCall.cs => ILOpCodeCall.cs} (68%) rename ChocolArm64/Translation/{AILOpCodeConst.cs => ILOpCodeConst.cs} (78%) create mode 100644 ChocolArm64/Translation/ILOpCodeLoad.cs rename ChocolArm64/Translation/{AILOpCodeLog.cs => ILOpCodeLog.cs} (62%) create mode 100644 ChocolArm64/Translation/ILOpCodeStore.cs rename ChocolArm64/Translation/{AIoType.cs => IoType.cs} (90%) rename ChocolArm64/Translation/{ALocalAlloc.cs => LocalAlloc.cs} (80%) rename ChocolArm64/{ATranslator.cs => Translator.cs} (70%) rename ChocolArm64/{ATranslatorCache.cs => TranslatorCache.cs} (90%) diff --git a/ChocolArm64/AOpCodeTable.cs b/ChocolArm64/AOpCodeTable.cs deleted file mode 100644 index 3e0b373880..0000000000 --- a/ChocolArm64/AOpCodeTable.cs +++ /dev/null @@ -1,713 +0,0 @@ -using ChocolArm64.Decoder; -using ChocolArm64.Decoder32; -using ChocolArm64.Instruction; -using ChocolArm64.Instruction32; -using ChocolArm64.State; -using System; -using System.Collections.Generic; - -namespace ChocolArm64 -{ - static class AOpCodeTable - { - static AOpCodeTable() - { -#region "OpCode Table (AArch32)" - //Integer - SetA32("<<<<1010xxxxxxxxxxxxxxxxxxxxxxxx", A32InstInterpret.B, typeof(A32OpCodeBImmAl)); - SetA32("<<<<1011xxxxxxxxxxxxxxxxxxxxxxxx", A32InstInterpret.Bl, typeof(A32OpCodeBImmAl)); - SetA32("1111101xxxxxxxxxxxxxxxxxxxxxxxxx", A32InstInterpret.Blx, typeof(A32OpCodeBImmAl)); -#endregion - -#region "OpCode Table (AArch64)" - //Integer - SetA64("x0011010000xxxxx000000xxxxxxxxxx", AInstEmit.Adc, typeof(AOpCodeAluRs)); - SetA64("x0111010000xxxxx000000xxxxxxxxxx", AInstEmit.Adcs, typeof(AOpCodeAluRs)); - SetA64("x00100010xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Add, typeof(AOpCodeAluImm)); - SetA64("00001011<<0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Add, typeof(AOpCodeAluRs)); - SetA64("10001011<<0xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Add, typeof(AOpCodeAluRs)); - SetA64("x0001011001xxxxxxxx0xxxxxxxxxxxx", AInstEmit.Add, typeof(AOpCodeAluRx)); - SetA64("x0001011001xxxxxxxx100xxxxxxxxxx", AInstEmit.Add, typeof(AOpCodeAluRx)); - SetA64("x01100010xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Adds, typeof(AOpCodeAluImm)); - SetA64("00101011<<0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Adds, typeof(AOpCodeAluRs)); - SetA64("10101011<<0xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Adds, typeof(AOpCodeAluRs)); - SetA64("x0101011001xxxxxxxx0xxxxxxxxxxxx", AInstEmit.Adds, typeof(AOpCodeAluRx)); - SetA64("x0101011001xxxxxxxx100xxxxxxxxxx", AInstEmit.Adds, typeof(AOpCodeAluRx)); - SetA64("0xx10000xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Adr, typeof(AOpCodeAdr)); - SetA64("1xx10000xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Adrp, typeof(AOpCodeAdr)); - SetA64("0001001000xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.And, typeof(AOpCodeAluImm)); - SetA64("100100100xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.And, typeof(AOpCodeAluImm)); - SetA64("00001010xx0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.And, typeof(AOpCodeAluRs)); - SetA64("10001010xx0xxxxxxxxxxxxxxxxxxxxx", AInstEmit.And, typeof(AOpCodeAluRs)); - SetA64("0111001000xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ands, typeof(AOpCodeAluImm)); - SetA64("111100100xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ands, typeof(AOpCodeAluImm)); - SetA64("01101010xx0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Ands, typeof(AOpCodeAluRs)); - SetA64("11101010xx0xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ands, typeof(AOpCodeAluRs)); - SetA64("x0011010110xxxxx001010xxxxxxxxxx", AInstEmit.Asrv, typeof(AOpCodeAluRs)); - SetA64("000101xxxxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.B, typeof(AOpCodeBImmAl)); - SetA64("01010100xxxxxxxxxxxxxxxxxxx0xxxx", AInstEmit.B_Cond, typeof(AOpCodeBImmCond)); - SetA64("00110011000xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Bfm, typeof(AOpCodeBfm)); - SetA64("1011001101xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Bfm, typeof(AOpCodeBfm)); - SetA64("00001010xx1xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Bic, typeof(AOpCodeAluRs)); - SetA64("10001010xx1xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Bic, typeof(AOpCodeAluRs)); - SetA64("01101010xx1xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Bics, typeof(AOpCodeAluRs)); - SetA64("11101010xx1xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Bics, typeof(AOpCodeAluRs)); - SetA64("100101xxxxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Bl, typeof(AOpCodeBImmAl)); - SetA64("1101011000111111000000xxxxx00000", AInstEmit.Blr, typeof(AOpCodeBReg)); - SetA64("1101011000011111000000xxxxx00000", AInstEmit.Br, typeof(AOpCodeBReg)); - SetA64("11010100001xxxxxxxxxxxxxxxx00000", AInstEmit.Brk, typeof(AOpCodeException)); - SetA64("x0110101xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Cbnz, typeof(AOpCodeBImmCmp)); - SetA64("x0110100xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Cbz, typeof(AOpCodeBImmCmp)); - SetA64("x0111010010xxxxxxxxx10xxxxx0xxxx", AInstEmit.Ccmn, typeof(AOpCodeCcmpImm)); - SetA64("x0111010010xxxxxxxxx00xxxxx0xxxx", AInstEmit.Ccmn, typeof(AOpCodeCcmpReg)); - SetA64("x1111010010xxxxxxxxx10xxxxx0xxxx", AInstEmit.Ccmp, typeof(AOpCodeCcmpImm)); - SetA64("x1111010010xxxxxxxxx00xxxxx0xxxx", AInstEmit.Ccmp, typeof(AOpCodeCcmpReg)); - SetA64("11010101000000110011xxxx01011111", AInstEmit.Clrex, typeof(AOpCodeSystem)); - SetA64("x101101011000000000101xxxxxxxxxx", AInstEmit.Cls, typeof(AOpCodeAlu)); - SetA64("x101101011000000000100xxxxxxxxxx", AInstEmit.Clz, typeof(AOpCodeAlu)); - SetA64("00011010110xxxxx010000xxxxxxxxxx", AInstEmit.Crc32b, typeof(AOpCodeAluRs)); - SetA64("00011010110xxxxx010001xxxxxxxxxx", AInstEmit.Crc32h, typeof(AOpCodeAluRs)); - SetA64("00011010110xxxxx010010xxxxxxxxxx", AInstEmit.Crc32w, typeof(AOpCodeAluRs)); - SetA64("10011010110xxxxx010011xxxxxxxxxx", AInstEmit.Crc32x, typeof(AOpCodeAluRs)); - SetA64("00011010110xxxxx010100xxxxxxxxxx", AInstEmit.Crc32cb, typeof(AOpCodeAluRs)); - SetA64("00011010110xxxxx010101xxxxxxxxxx", AInstEmit.Crc32ch, typeof(AOpCodeAluRs)); - SetA64("00011010110xxxxx010110xxxxxxxxxx", AInstEmit.Crc32cw, typeof(AOpCodeAluRs)); - SetA64("10011010110xxxxx010111xxxxxxxxxx", AInstEmit.Crc32cx, typeof(AOpCodeAluRs)); - SetA64("x0011010100xxxxxxxxx00xxxxxxxxxx", AInstEmit.Csel, typeof(AOpCodeCsel)); - SetA64("x0011010100xxxxxxxxx01xxxxxxxxxx", AInstEmit.Csinc, typeof(AOpCodeCsel)); - SetA64("x1011010100xxxxxxxxx00xxxxxxxxxx", AInstEmit.Csinv, typeof(AOpCodeCsel)); - SetA64("x1011010100xxxxxxxxx01xxxxxxxxxx", AInstEmit.Csneg, typeof(AOpCodeCsel)); - SetA64("11010101000000110011xxxx10111111", AInstEmit.Dmb, typeof(AOpCodeSystem)); - SetA64("11010101000000110011xxxx10011111", AInstEmit.Dsb, typeof(AOpCodeSystem)); - SetA64("01001010xx1xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Eon, typeof(AOpCodeAluRs)); - SetA64("11001010xx1xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Eon, typeof(AOpCodeAluRs)); - SetA64("0101001000xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Eor, typeof(AOpCodeAluImm)); - SetA64("110100100xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Eor, typeof(AOpCodeAluImm)); - SetA64("01001010xx0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Eor, typeof(AOpCodeAluRs)); - SetA64("11001010xx0xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Eor, typeof(AOpCodeAluRs)); - SetA64("00010011100xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Extr, typeof(AOpCodeAluRs)); - SetA64("10010011110xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Extr, typeof(AOpCodeAluRs)); - SetA64("11010101000000110010xxxxxxx11111", AInstEmit.Hint, typeof(AOpCodeSystem)); - SetA64("11010101000000110011xxxx11011111", AInstEmit.Isb, typeof(AOpCodeSystem)); - SetA64("xx001000110xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Ldar, typeof(AOpCodeMemEx)); - SetA64("1x001000011xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Ldaxp, typeof(AOpCodeMemEx)); - SetA64("xx001000010xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Ldaxr, typeof(AOpCodeMemEx)); - SetA64("<<10100xx1xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ldp, typeof(AOpCodeMemPair)); - SetA64("xx111000010xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeMemImm)); - SetA64("xx11100101xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeMemImm)); - SetA64("xx111000011xxxxxxxxx10xxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeMemReg)); - SetA64("xx011000xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.LdrLit, typeof(AOpCodeMemLit)); - SetA64("0x1110001x0xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ldrs, typeof(AOpCodeMemImm)); - SetA64("0x1110011xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ldrs, typeof(AOpCodeMemImm)); - SetA64("10111000100xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ldrs, typeof(AOpCodeMemImm)); - SetA64("1011100110xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ldrs, typeof(AOpCodeMemImm)); - SetA64("0x1110001x1xxxxxxxxx10xxxxxxxxxx", AInstEmit.Ldrs, typeof(AOpCodeMemReg)); - SetA64("10111000101xxxxxxxxx10xxxxxxxxxx", AInstEmit.Ldrs, typeof(AOpCodeMemReg)); - SetA64("xx001000010xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Ldxr, typeof(AOpCodeMemEx)); - SetA64("1x001000011xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Ldxp, typeof(AOpCodeMemEx)); - SetA64("x0011010110xxxxx001000xxxxxxxxxx", AInstEmit.Lslv, typeof(AOpCodeAluRs)); - SetA64("x0011010110xxxxx001001xxxxxxxxxx", AInstEmit.Lsrv, typeof(AOpCodeAluRs)); - SetA64("x0011011000xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Madd, typeof(AOpCodeMul)); - SetA64("0111001010xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Movk, typeof(AOpCodeMov)); - SetA64("111100101xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Movk, typeof(AOpCodeMov)); - SetA64("0001001010xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Movn, typeof(AOpCodeMov)); - SetA64("100100101xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Movn, typeof(AOpCodeMov)); - SetA64("0101001010xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Movz, typeof(AOpCodeMov)); - SetA64("110100101xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Movz, typeof(AOpCodeMov)); - SetA64("110101010011xxxxxxxxxxxxxxxxxxxx", AInstEmit.Mrs, typeof(AOpCodeSystem)); - SetA64("110101010001xxxxxxxxxxxxxxxxxxxx", AInstEmit.Msr, typeof(AOpCodeSystem)); - SetA64("x0011011000xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Msub, typeof(AOpCodeMul)); - SetA64("11010101000000110010000000011111", AInstEmit.Nop, typeof(AOpCodeSystem)); - SetA64("00101010xx1xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Orn, typeof(AOpCodeAluRs)); - SetA64("10101010xx1xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Orn, typeof(AOpCodeAluRs)); - SetA64("0011001000xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Orr, typeof(AOpCodeAluImm)); - SetA64("101100100xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Orr, typeof(AOpCodeAluImm)); - SetA64("00101010xx0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Orr, typeof(AOpCodeAluRs)); - SetA64("10101010xx0xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Orr, typeof(AOpCodeAluRs)); - SetA64("1111100110xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Pfrm, typeof(AOpCodeMemImm)); - SetA64("11111000100xxxxxxxxx00xxxxxxxxxx", AInstEmit.Pfrm, typeof(AOpCodeMemImm)); - SetA64("11011000xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Pfrm, typeof(AOpCodeMemLit)); - SetA64("x101101011000000000000xxxxxxxxxx", AInstEmit.Rbit, typeof(AOpCodeAlu)); - SetA64("1101011001011111000000xxxxx00000", AInstEmit.Ret, typeof(AOpCodeBReg)); - SetA64("x101101011000000000001xxxxxxxxxx", AInstEmit.Rev16, typeof(AOpCodeAlu)); - SetA64("x101101011000000000010xxxxxxxxxx", AInstEmit.Rev32, typeof(AOpCodeAlu)); - SetA64("1101101011000000000011xxxxxxxxxx", AInstEmit.Rev64, typeof(AOpCodeAlu)); - SetA64("x0011010110xxxxx001011xxxxxxxxxx", AInstEmit.Rorv, typeof(AOpCodeAluRs)); - SetA64("x1011010000xxxxx000000xxxxxxxxxx", AInstEmit.Sbc, typeof(AOpCodeAluRs)); - SetA64("x1111010000xxxxx000000xxxxxxxxxx", AInstEmit.Sbcs, typeof(AOpCodeAluRs)); - SetA64("00010011000xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Sbfm, typeof(AOpCodeBfm)); - SetA64("1001001101xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Sbfm, typeof(AOpCodeBfm)); - SetA64("x0011010110xxxxx000011xxxxxxxxxx", AInstEmit.Sdiv, typeof(AOpCodeAluRs)); - SetA64("10011011001xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Smaddl, typeof(AOpCodeMul)); - SetA64("10011011001xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Smsubl, typeof(AOpCodeMul)); - SetA64("10011011010xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Smulh, typeof(AOpCodeMul)); - SetA64("xx001000100xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Stlr, typeof(AOpCodeMemEx)); - SetA64("1x001000001xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Stlxp, typeof(AOpCodeMemEx)); - SetA64("xx001000000xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Stlxr, typeof(AOpCodeMemEx)); - SetA64("x010100xx0xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Stp, typeof(AOpCodeMemPair)); - SetA64("xx111000000xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeMemImm)); - SetA64("xx11100100xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeMemImm)); - SetA64("xx111000001xxxxxxxxx10xxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeMemReg)); - SetA64("1x001000001xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Stxp, typeof(AOpCodeMemEx)); - SetA64("xx001000000xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Stxr, typeof(AOpCodeMemEx)); - SetA64("x10100010xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Sub, typeof(AOpCodeAluImm)); - SetA64("01001011<<0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Sub, typeof(AOpCodeAluRs)); - SetA64("11001011<<0xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Sub, typeof(AOpCodeAluRs)); - SetA64("x1001011001xxxxxxxx0xxxxxxxxxxxx", AInstEmit.Sub, typeof(AOpCodeAluRx)); - SetA64("x1001011001xxxxxxxx100xxxxxxxxxx", AInstEmit.Sub, typeof(AOpCodeAluRx)); - SetA64("x11100010xxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Subs, typeof(AOpCodeAluImm)); - SetA64("01101011<<0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Subs, typeof(AOpCodeAluRs)); - SetA64("11101011<<0xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Subs, typeof(AOpCodeAluRs)); - SetA64("x1101011001xxxxxxxx0xxxxxxxxxxxx", AInstEmit.Subs, typeof(AOpCodeAluRx)); - SetA64("x1101011001xxxxxxxx100xxxxxxxxxx", AInstEmit.Subs, typeof(AOpCodeAluRx)); - SetA64("11010100000xxxxxxxxxxxxxxxx00001", AInstEmit.Svc, typeof(AOpCodeException)); - SetA64("1101010100001xxxxxxxxxxxxxxxxxxx", AInstEmit.Sys, typeof(AOpCodeSystem)); - SetA64("x0110111xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Tbnz, typeof(AOpCodeBImmTest)); - SetA64("x0110110xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Tbz, typeof(AOpCodeBImmTest)); - SetA64("01010011000xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Ubfm, typeof(AOpCodeBfm)); - SetA64("1101001101xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ubfm, typeof(AOpCodeBfm)); - SetA64("x0011010110xxxxx000010xxxxxxxxxx", AInstEmit.Udiv, typeof(AOpCodeAluRs)); - SetA64("10011011101xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Umaddl, typeof(AOpCodeMul)); - SetA64("10011011101xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Umsubl, typeof(AOpCodeMul)); - SetA64("10011011110xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Umulh, typeof(AOpCodeMul)); - - //Vector - SetA64("0101111011100000101110xxxxxxxxxx", AInstEmit.Abs_S, typeof(AOpCodeSimd)); - SetA64("0>001110<<100000101110xxxxxxxxxx", AInstEmit.Abs_V, typeof(AOpCodeSimd)); - SetA64("01011110111xxxxx100001xxxxxxxxxx", AInstEmit.Add_S, typeof(AOpCodeSimdReg)); - SetA64("0>001110<<1xxxxx100001xxxxxxxxxx", AInstEmit.Add_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110<<1xxxxx010000xxxxxxxxxx", AInstEmit.Addhn_V, typeof(AOpCodeSimdReg)); - SetA64("0101111011110001101110xxxxxxxxxx", AInstEmit.Addp_S, typeof(AOpCodeSimd)); - SetA64("0>001110<<1xxxxx101111xxxxxxxxxx", AInstEmit.Addp_V, typeof(AOpCodeSimdReg)); - SetA64("000011100x110001101110xxxxxxxxxx", AInstEmit.Addv_V, typeof(AOpCodeSimd)); - SetA64("01001110<<110001101110xxxxxxxxxx", AInstEmit.Addv_V, typeof(AOpCodeSimd)); - SetA64("0100111000101000010110xxxxxxxxxx", AInstEmit.Aesd_V, typeof(AOpCodeSimd)); - SetA64("0100111000101000010010xxxxxxxxxx", AInstEmit.Aese_V, typeof(AOpCodeSimd)); - SetA64("0100111000101000011110xxxxxxxxxx", AInstEmit.Aesimc_V, typeof(AOpCodeSimd)); - SetA64("0100111000101000011010xxxxxxxxxx", AInstEmit.Aesmc_V, typeof(AOpCodeSimd)); - SetA64("0x001110001xxxxx000111xxxxxxxxxx", AInstEmit.And_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110011xxxxx000111xxxxxxxxxx", AInstEmit.Bic_V, typeof(AOpCodeSimdReg)); - SetA64("0x10111100000xxx<101110<<1xxxxx100011xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimdReg)); - SetA64("0>001110<<100000100110xxxxxxxxxx", AInstEmit.Cmeq_V, typeof(AOpCodeSimd)); - SetA64("01011110111xxxxx001111xxxxxxxxxx", AInstEmit.Cmge_S, typeof(AOpCodeSimdReg)); - SetA64("0111111011100000100010xxxxxxxxxx", AInstEmit.Cmge_S, typeof(AOpCodeSimd)); - SetA64("0>001110<<1xxxxx001111xxxxxxxxxx", AInstEmit.Cmge_V, typeof(AOpCodeSimdReg)); - SetA64("0>101110<<100000100010xxxxxxxxxx", AInstEmit.Cmge_V, typeof(AOpCodeSimd)); - SetA64("01011110111xxxxx001101xxxxxxxxxx", AInstEmit.Cmgt_S, typeof(AOpCodeSimdReg)); - SetA64("0101111011100000100010xxxxxxxxxx", AInstEmit.Cmgt_S, typeof(AOpCodeSimd)); - SetA64("0>001110<<1xxxxx001101xxxxxxxxxx", AInstEmit.Cmgt_V, typeof(AOpCodeSimdReg)); - SetA64("0>001110<<100000100010xxxxxxxxxx", AInstEmit.Cmgt_V, typeof(AOpCodeSimd)); - SetA64("01111110111xxxxx001101xxxxxxxxxx", AInstEmit.Cmhi_S, typeof(AOpCodeSimdReg)); - SetA64("0>101110<<1xxxxx001101xxxxxxxxxx", AInstEmit.Cmhi_V, typeof(AOpCodeSimdReg)); - SetA64("01111110111xxxxx001111xxxxxxxxxx", AInstEmit.Cmhs_S, typeof(AOpCodeSimdReg)); - SetA64("0>101110<<1xxxxx001111xxxxxxxxxx", AInstEmit.Cmhs_V, typeof(AOpCodeSimdReg)); - SetA64("0111111011100000100110xxxxxxxxxx", AInstEmit.Cmle_S, typeof(AOpCodeSimd)); - SetA64("0>101110<<100000100110xxxxxxxxxx", AInstEmit.Cmle_V, typeof(AOpCodeSimd)); - SetA64("0101111011100000101010xxxxxxxxxx", AInstEmit.Cmlt_S, typeof(AOpCodeSimd)); - SetA64("0>001110<<100000101010xxxxxxxxxx", AInstEmit.Cmlt_V, typeof(AOpCodeSimd)); - SetA64("01011110111xxxxx100011xxxxxxxxxx", AInstEmit.Cmtst_S, typeof(AOpCodeSimdReg)); - SetA64("0>001110<<1xxxxx100011xxxxxxxxxx", AInstEmit.Cmtst_V, typeof(AOpCodeSimdReg)); - SetA64("0x00111000100000010110xxxxxxxxxx", AInstEmit.Cnt_V, typeof(AOpCodeSimd)); - SetA64("0x001110000xxxxx000011xxxxxxxxxx", AInstEmit.Dup_Gp, typeof(AOpCodeSimdIns)); - SetA64("01011110000xxxxx000001xxxxxxxxxx", AInstEmit.Dup_S, typeof(AOpCodeSimdIns)); - SetA64("0x001110000xxxxx000001xxxxxxxxxx", AInstEmit.Dup_V, typeof(AOpCodeSimdIns)); - SetA64("0x101110001xxxxx000111xxxxxxxxxx", AInstEmit.Eor_V, typeof(AOpCodeSimdReg)); - SetA64("0>101110000xxxxx00011101<100000111110xxxxxxxxxx", AInstEmit.Fabs_V, typeof(AOpCodeSimd)); - SetA64("000111100x1xxxxx001010xxxxxxxxxx", AInstEmit.Fadd_S, typeof(AOpCodeSimdReg)); - SetA64("0>0011100<1xxxxx110101xxxxxxxxxx", AInstEmit.Fadd_V, typeof(AOpCodeSimdReg)); - SetA64("011111100x110000110110xxxxxxxxxx", AInstEmit.Faddp_S, typeof(AOpCodeSimd)); - SetA64("0>1011100<1xxxxx110101xxxxxxxxxx", AInstEmit.Faddp_V, typeof(AOpCodeSimdReg)); - SetA64("000111100x1xxxxxxxxx01xxxxx0xxxx", AInstEmit.Fccmp_S, typeof(AOpCodeSimdFcond)); - SetA64("000111100x1xxxxxxxxx01xxxxx1xxxx", AInstEmit.Fccmpe_S, typeof(AOpCodeSimdFcond)); - SetA64("010111100x1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmeq_S, typeof(AOpCodeSimdReg)); - SetA64("010111101x100000110110xxxxxxxxxx", AInstEmit.Fcmeq_S, typeof(AOpCodeSimd)); - SetA64("0>0011100<1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmeq_V, typeof(AOpCodeSimdReg)); - SetA64("0>0011101<100000110110xxxxxxxxxx", AInstEmit.Fcmeq_V, typeof(AOpCodeSimd)); - SetA64("011111100x1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmge_S, typeof(AOpCodeSimdReg)); - SetA64("011111101x100000110010xxxxxxxxxx", AInstEmit.Fcmge_S, typeof(AOpCodeSimd)); - SetA64("0>1011100<1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmge_V, typeof(AOpCodeSimdReg)); - SetA64("0>1011101<100000110010xxxxxxxxxx", AInstEmit.Fcmge_V, typeof(AOpCodeSimd)); - SetA64("011111101x1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmgt_S, typeof(AOpCodeSimdReg)); - SetA64("010111101x100000110010xxxxxxxxxx", AInstEmit.Fcmgt_S, typeof(AOpCodeSimd)); - SetA64("0>1011101<1xxxxx111001xxxxxxxxxx", AInstEmit.Fcmgt_V, typeof(AOpCodeSimdReg)); - SetA64("0>0011101<100000110010xxxxxxxxxx", AInstEmit.Fcmgt_V, typeof(AOpCodeSimd)); - SetA64("011111101x100000110110xxxxxxxxxx", AInstEmit.Fcmle_S, typeof(AOpCodeSimd)); - SetA64("0>1011101<100000110110xxxxxxxxxx", AInstEmit.Fcmle_V, typeof(AOpCodeSimd)); - SetA64("010111101x100000111010xxxxxxxxxx", AInstEmit.Fcmlt_S, typeof(AOpCodeSimd)); - SetA64("0>0011101<100000111010xxxxxxxxxx", AInstEmit.Fcmlt_V, typeof(AOpCodeSimd)); - SetA64("000111100x1xxxxx001000xxxxx0x000", AInstEmit.Fcmp_S, typeof(AOpCodeSimdReg)); - SetA64("000111100x1xxxxx001000xxxxx1x000", AInstEmit.Fcmpe_S, typeof(AOpCodeSimdReg)); - SetA64("000111100x1xxxxxxxxx11xxxxxxxxxx", AInstEmit.Fcsel_S, typeof(AOpCodeSimdFcond)); - SetA64("000111100x10001xx10000xxxxxxxxxx", AInstEmit.Fcvt_S, typeof(AOpCodeSimd)); - SetA64("x00111100x100100000000xxxxxxxxxx", AInstEmit.Fcvtas_Gp, typeof(AOpCodeSimdCvt)); - SetA64("x00111100x100101000000xxxxxxxxxx", AInstEmit.Fcvtau_Gp, typeof(AOpCodeSimdCvt)); - SetA64("0x0011100x100001011110xxxxxxxxxx", AInstEmit.Fcvtl_V, typeof(AOpCodeSimd)); - SetA64("x00111100x110000000000xxxxxxxxxx", AInstEmit.Fcvtms_Gp, typeof(AOpCodeSimdCvt)); - SetA64("x00111100x110001000000xxxxxxxxxx", AInstEmit.Fcvtmu_Gp, typeof(AOpCodeSimdCvt)); - SetA64("0x0011100x100001011010xxxxxxxxxx", AInstEmit.Fcvtn_V, typeof(AOpCodeSimd)); - SetA64("010111100x100001101010xxxxxxxxxx", AInstEmit.Fcvtns_S, typeof(AOpCodeSimd)); - SetA64("0>0011100<100001101010xxxxxxxxxx", AInstEmit.Fcvtns_V, typeof(AOpCodeSimd)); - SetA64("011111100x100001101010xxxxxxxxxx", AInstEmit.Fcvtnu_S, typeof(AOpCodeSimd)); - SetA64("0>1011100<100001101010xxxxxxxxxx", AInstEmit.Fcvtnu_V, typeof(AOpCodeSimd)); - SetA64("x00111100x101000000000xxxxxxxxxx", AInstEmit.Fcvtps_Gp, typeof(AOpCodeSimdCvt)); - SetA64("x00111100x101001000000xxxxxxxxxx", AInstEmit.Fcvtpu_Gp, typeof(AOpCodeSimdCvt)); - SetA64("x00111100x111000000000xxxxxxxxxx", AInstEmit.Fcvtzs_Gp, typeof(AOpCodeSimdCvt)); - SetA64("x00111100x011000xxxxxxxxxxxxxxxx", AInstEmit.Fcvtzs_Gp_Fix, typeof(AOpCodeSimdCvt)); - SetA64("010111101x100001101110xxxxxxxxxx", AInstEmit.Fcvtzs_S, typeof(AOpCodeSimd)); - SetA64("0>0011101<100001101110xxxxxxxxxx", AInstEmit.Fcvtzs_V, typeof(AOpCodeSimd)); - SetA64("0x0011110>>xxxxx111111xxxxxxxxxx", AInstEmit.Fcvtzs_V, typeof(AOpCodeSimdShImm)); - SetA64("x00111100x111001000000xxxxxxxxxx", AInstEmit.Fcvtzu_Gp, typeof(AOpCodeSimdCvt)); - SetA64("x00111100x011001xxxxxxxxxxxxxxxx", AInstEmit.Fcvtzu_Gp_Fix, typeof(AOpCodeSimdCvt)); - SetA64("011111101x100001101110xxxxxxxxxx", AInstEmit.Fcvtzu_S, typeof(AOpCodeSimd)); - SetA64("0>1011101<100001101110xxxxxxxxxx", AInstEmit.Fcvtzu_V, typeof(AOpCodeSimd)); - SetA64("0x1011110>>xxxxx111111xxxxxxxxxx", AInstEmit.Fcvtzu_V, typeof(AOpCodeSimdShImm)); - SetA64("000111100x1xxxxx000110xxxxxxxxxx", AInstEmit.Fdiv_S, typeof(AOpCodeSimdReg)); - SetA64("0>1011100<1xxxxx111111xxxxxxxxxx", AInstEmit.Fdiv_V, typeof(AOpCodeSimdReg)); - SetA64("000111110x0xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Fmadd_S, typeof(AOpCodeSimdReg)); - SetA64("000111100x1xxxxx010010xxxxxxxxxx", AInstEmit.Fmax_S, typeof(AOpCodeSimdReg)); - SetA64("0>0011100<1xxxxx111101xxxxxxxxxx", AInstEmit.Fmax_V, typeof(AOpCodeSimdReg)); - SetA64("000111100x1xxxxx011010xxxxxxxxxx", AInstEmit.Fmaxnm_S, typeof(AOpCodeSimdReg)); - SetA64("0>0011100<1xxxxx110001xxxxxxxxxx", AInstEmit.Fmaxnm_V, typeof(AOpCodeSimdReg)); - SetA64("0>1011100<1xxxxx111101xxxxxxxxxx", AInstEmit.Fmaxp_V, typeof(AOpCodeSimdReg)); - SetA64("000111100x1xxxxx010110xxxxxxxxxx", AInstEmit.Fmin_S, typeof(AOpCodeSimdReg)); - SetA64("0>0011101<1xxxxx111101xxxxxxxxxx", AInstEmit.Fmin_V, typeof(AOpCodeSimdReg)); - SetA64("000111100x1xxxxx011110xxxxxxxxxx", AInstEmit.Fminnm_S, typeof(AOpCodeSimdReg)); - SetA64("0>0011101<1xxxxx110001xxxxxxxxxx", AInstEmit.Fminnm_V, typeof(AOpCodeSimdReg)); - SetA64("0>1011101<1xxxxx111101xxxxxxxxxx", AInstEmit.Fminp_V, typeof(AOpCodeSimdReg)); - SetA64("010111111xxxxxxx0001x0xxxxxxxxxx", AInstEmit.Fmla_Se, typeof(AOpCodeSimdRegElemF)); - SetA64("0>0011100<1xxxxx110011xxxxxxxxxx", AInstEmit.Fmla_V, typeof(AOpCodeSimdReg)); - SetA64("0>00111110011101<1xxxxx110011xxxxxxxxxx", AInstEmit.Fmls_V, typeof(AOpCodeSimdReg)); - SetA64("0>00111111011100<1xxxxx110111xxxxxxxxxx", AInstEmit.Fmul_V, typeof(AOpCodeSimdReg)); - SetA64("0>00111110011100<1xxxxx110111xxxxxxxxxx", AInstEmit.Fmulx_V, typeof(AOpCodeSimdReg)); - SetA64("0>10111111011101<100000111110xxxxxxxxxx", AInstEmit.Fneg_V, typeof(AOpCodeSimd)); - SetA64("000111110x1xxxxx0xxxxxxxxxxxxxxx", AInstEmit.Fnmadd_S, typeof(AOpCodeSimdReg)); - SetA64("000111110x1xxxxx1xxxxxxxxxxxxxxx", AInstEmit.Fnmsub_S, typeof(AOpCodeSimdReg)); - SetA64("000111100x1xxxxx100010xxxxxxxxxx", AInstEmit.Fnmul_S, typeof(AOpCodeSimdReg)); - SetA64("010111101x100001110110xxxxxxxxxx", AInstEmit.Frecpe_S, typeof(AOpCodeSimd)); - SetA64("0>0011101<100001110110xxxxxxxxxx", AInstEmit.Frecpe_V, typeof(AOpCodeSimd)); - SetA64("010111100x1xxxxx111111xxxxxxxxxx", AInstEmit.Frecps_S, typeof(AOpCodeSimdReg)); - SetA64("0>0011100<1xxxxx111111xxxxxxxxxx", AInstEmit.Frecps_V, typeof(AOpCodeSimdReg)); - SetA64("010111101x100001111110xxxxxxxxxx", AInstEmit.Frecpx_S, typeof(AOpCodeSimd)); - SetA64("000111100x100110010000xxxxxxxxxx", AInstEmit.Frinta_S, typeof(AOpCodeSimd)); - SetA64("0>1011100<100001100010xxxxxxxxxx", AInstEmit.Frinta_V, typeof(AOpCodeSimd)); - SetA64("000111100x100111110000xxxxxxxxxx", AInstEmit.Frinti_S, typeof(AOpCodeSimd)); - SetA64("0>1011101<100001100110xxxxxxxxxx", AInstEmit.Frinti_V, typeof(AOpCodeSimd)); - SetA64("000111100x100101010000xxxxxxxxxx", AInstEmit.Frintm_S, typeof(AOpCodeSimd)); - SetA64("0>0011100<100001100110xxxxxxxxxx", AInstEmit.Frintm_V, typeof(AOpCodeSimd)); - SetA64("000111100x100100010000xxxxxxxxxx", AInstEmit.Frintn_S, typeof(AOpCodeSimd)); - SetA64("0>0011100<100001100010xxxxxxxxxx", AInstEmit.Frintn_V, typeof(AOpCodeSimd)); - SetA64("000111100x100100110000xxxxxxxxxx", AInstEmit.Frintp_S, typeof(AOpCodeSimd)); - SetA64("0>0011101<100001100010xxxxxxxxxx", AInstEmit.Frintp_V, typeof(AOpCodeSimd)); - SetA64("000111100x100111010000xxxxxxxxxx", AInstEmit.Frintx_S, typeof(AOpCodeSimd)); - SetA64("0>1011100<100001100110xxxxxxxxxx", AInstEmit.Frintx_V, typeof(AOpCodeSimd)); - SetA64("011111101x100001110110xxxxxxxxxx", AInstEmit.Frsqrte_S, typeof(AOpCodeSimd)); - SetA64("0>1011101<100001110110xxxxxxxxxx", AInstEmit.Frsqrte_V, typeof(AOpCodeSimd)); - SetA64("010111101x1xxxxx111111xxxxxxxxxx", AInstEmit.Frsqrts_S, typeof(AOpCodeSimdReg)); - SetA64("0>0011101<1xxxxx111111xxxxxxxxxx", AInstEmit.Frsqrts_V, typeof(AOpCodeSimdReg)); - SetA64("000111100x100001110000xxxxxxxxxx", AInstEmit.Fsqrt_S, typeof(AOpCodeSimd)); - SetA64("0>1011101<100001111110xxxxxxxxxx", AInstEmit.Fsqrt_V, typeof(AOpCodeSimd)); - SetA64("000111100x1xxxxx001110xxxxxxxxxx", AInstEmit.Fsub_S, typeof(AOpCodeSimdReg)); - SetA64("0>0011101<1xxxxx110101xxxxxxxxxx", AInstEmit.Fsub_V, typeof(AOpCodeSimdReg)); - SetA64("01001110000xxxxx000111xxxxxxxxxx", AInstEmit.Ins_Gp, typeof(AOpCodeSimdIns)); - SetA64("01101110000xxxxx0xxxx1xxxxxxxxxx", AInstEmit.Ins_V, typeof(AOpCodeSimdIns)); - SetA64("0x00110001000000xxxxxxxxxxxxxxxx", AInstEmit.Ld__Vms, typeof(AOpCodeSimdMemMs)); - SetA64("0x001100110xxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ld__Vms, typeof(AOpCodeSimdMemMs)); - SetA64("0x00110101x00000xxxxxxxxxxxxxxxx", AInstEmit.Ld__Vss, typeof(AOpCodeSimdMemSs)); - SetA64("0x00110111xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ld__Vss, typeof(AOpCodeSimdMemSs)); - SetA64("xx10110xx1xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ldp, typeof(AOpCodeSimdMemPair)); - SetA64("xx111100x10xxxxxxxxx00xxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeSimdMemImm)); - SetA64("xx111100x10xxxxxxxxx01xxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeSimdMemImm)); - SetA64("xx111100x10xxxxxxxxx11xxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeSimdMemImm)); - SetA64("xx111101x1xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeSimdMemImm)); - SetA64("xx111100x11xxxxxxxxx10xxxxxxxxxx", AInstEmit.Ldr, typeof(AOpCodeSimdMemReg)); - SetA64("xx011100xxxxxxxxxxxxxxxxxxxxxxxx", AInstEmit.LdrLit, typeof(AOpCodeSimdMemLit)); - SetA64("0x001110<<1xxxxx100101xxxxxxxxxx", AInstEmit.Mla_V, typeof(AOpCodeSimdReg)); - SetA64("0x101111xxxxxxxx0000x0xxxxxxxxxx", AInstEmit.Mla_Ve, typeof(AOpCodeSimdRegElem)); - SetA64("0x101110<<1xxxxx100101xxxxxxxxxx", AInstEmit.Mls_V, typeof(AOpCodeSimdReg)); - SetA64("0x101111xxxxxxxx0100x0xxxxxxxxxx", AInstEmit.Mls_Ve, typeof(AOpCodeSimdRegElem)); - SetA64("0x00111100000xxx0xx001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm)); - SetA64("0x00111100000xxx10x001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm)); - SetA64("0x00111100000xxx110x01xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm)); - SetA64("0xx0111100000xxx111001xxxxxxxxxx", AInstEmit.Movi_V, typeof(AOpCodeSimdImm)); - SetA64("0x001110<<1xxxxx100111xxxxxxxxxx", AInstEmit.Mul_V, typeof(AOpCodeSimdReg)); - SetA64("0x001111xxxxxxxx1000x0xxxxxxxxxx", AInstEmit.Mul_Ve, typeof(AOpCodeSimdRegElem)); - SetA64("0x10111100000xxx0xx001xxxxxxxxxx", AInstEmit.Mvni_V, typeof(AOpCodeSimdImm)); - SetA64("0x10111100000xxx10x001xxxxxxxxxx", AInstEmit.Mvni_V, typeof(AOpCodeSimdImm)); - SetA64("0x10111100000xxx110x01xxxxxxxxxx", AInstEmit.Mvni_V, typeof(AOpCodeSimdImm)); - SetA64("0111111011100000101110xxxxxxxxxx", AInstEmit.Neg_S, typeof(AOpCodeSimd)); - SetA64("0>101110<<100000101110xxxxxxxxxx", AInstEmit.Neg_V, typeof(AOpCodeSimd)); - SetA64("0x10111000100000010110xxxxxxxxxx", AInstEmit.Not_V, typeof(AOpCodeSimd)); - SetA64("0x001110111xxxxx000111xxxxxxxxxx", AInstEmit.Orn_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110101xxxxx000111xxxxxxxxxx", AInstEmit.Orr_V, typeof(AOpCodeSimdReg)); - SetA64("0x00111100000xxx<>>xxx100011xxxxxxxxxx", AInstEmit.Rshrn_V, typeof(AOpCodeSimdShImm)); - SetA64("0x101110<<1xxxxx011000xxxxxxxxxx", AInstEmit.Rsubhn_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110<<1xxxxx011111xxxxxxxxxx", AInstEmit.Saba_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110<<1xxxxx010100xxxxxxxxxx", AInstEmit.Sabal_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110<<1xxxxx011101xxxxxxxxxx", AInstEmit.Sabd_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110<<1xxxxx011100xxxxxxxxxx", AInstEmit.Sabdl_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110<<100000011010xxxxxxxxxx", AInstEmit.Sadalp_V, typeof(AOpCodeSimd)); - SetA64("0x001110<<1xxxxx000000xxxxxxxxxx", AInstEmit.Saddl_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110<<100000001010xxxxxxxxxx", AInstEmit.Saddlp_V, typeof(AOpCodeSimd)); - SetA64("0x001110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Saddw_V, typeof(AOpCodeSimdReg)); - SetA64("x0011110xx100010000000xxxxxxxxxx", AInstEmit.Scvtf_Gp, typeof(AOpCodeSimdCvt)); - SetA64("010111100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_S, typeof(AOpCodeSimd)); - SetA64("0x0011100x100001110110xxxxxxxxxx", AInstEmit.Scvtf_V, typeof(AOpCodeSimd)); - SetA64("01011110000xxxxx000000xxxxxxxxxx", AInstEmit.Sha1c_V, typeof(AOpCodeSimdReg)); - SetA64("0101111000101000000010xxxxxxxxxx", AInstEmit.Sha1h_V, typeof(AOpCodeSimd)); - SetA64("01011110000xxxxx001000xxxxxxxxxx", AInstEmit.Sha1m_V, typeof(AOpCodeSimdReg)); - SetA64("01011110000xxxxx000100xxxxxxxxxx", AInstEmit.Sha1p_V, typeof(AOpCodeSimdReg)); - SetA64("01011110000xxxxx001100xxxxxxxxxx", AInstEmit.Sha1su0_V, typeof(AOpCodeSimdReg)); - SetA64("0101111000101000000110xxxxxxxxxx", AInstEmit.Sha1su1_V, typeof(AOpCodeSimd)); - SetA64("01011110000xxxxx010000xxxxxxxxxx", AInstEmit.Sha256h_V, typeof(AOpCodeSimdReg)); - SetA64("01011110000xxxxx010100xxxxxxxxxx", AInstEmit.Sha256h2_V, typeof(AOpCodeSimdReg)); - SetA64("0101111000101000001010xxxxxxxxxx", AInstEmit.Sha256su0_V, typeof(AOpCodeSimd)); - SetA64("01011110000xxxxx011000xxxxxxxxxx", AInstEmit.Sha256su1_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Shadd_V, typeof(AOpCodeSimdReg)); - SetA64("0101111101xxxxxx010101xxxxxxxxxx", AInstEmit.Shl_S, typeof(AOpCodeSimdShImm)); - SetA64("0x00111100>>>xxx010101xxxxxxxxxx", AInstEmit.Shl_V, typeof(AOpCodeSimdShImm)); - SetA64("0100111101xxxxxx010101xxxxxxxxxx", AInstEmit.Shl_V, typeof(AOpCodeSimdShImm)); - SetA64("0x101110<<100001001110xxxxxxxxxx", AInstEmit.Shll_V, typeof(AOpCodeSimd)); - SetA64("0x00111100>>>xxx100001xxxxxxxxxx", AInstEmit.Shrn_V, typeof(AOpCodeSimdShImm)); - SetA64("0x001110<<1xxxxx001001xxxxxxxxxx", AInstEmit.Shsub_V, typeof(AOpCodeSimdReg)); - SetA64("0x1011110>>>>xxx010101xxxxxxxxxx", AInstEmit.Sli_V, typeof(AOpCodeSimdShImm)); - SetA64("0x001110<<1xxxxx011001xxxxxxxxxx", AInstEmit.Smax_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110<<1xxxxx101001xxxxxxxxxx", AInstEmit.Smaxp_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110<<1xxxxx011011xxxxxxxxxx", AInstEmit.Smin_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110<<1xxxxx101011xxxxxxxxxx", AInstEmit.Sminp_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110<<1xxxxx100000xxxxxxxxxx", AInstEmit.Smlal_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110<<1xxxxx101000xxxxxxxxxx", AInstEmit.Smlsl_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110000xxxxx001011xxxxxxxxxx", AInstEmit.Smov_S, typeof(AOpCodeSimdIns)); - SetA64("0x001110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Smull_V, typeof(AOpCodeSimdReg)); - SetA64("01011110xx100000011110xxxxxxxxxx", AInstEmit.Sqabs_S, typeof(AOpCodeSimd)); - SetA64("0>001110<<100000011110xxxxxxxxxx", AInstEmit.Sqabs_V, typeof(AOpCodeSimd)); - SetA64("01011110xx1xxxxx000011xxxxxxxxxx", AInstEmit.Sqadd_S, typeof(AOpCodeSimdReg)); - SetA64("0>001110<<1xxxxx000011xxxxxxxxxx", AInstEmit.Sqadd_V, typeof(AOpCodeSimdReg)); - SetA64("01011110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_S, typeof(AOpCodeSimdReg)); - SetA64("01011110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_S, typeof(AOpCodeSimdReg)); - SetA64("0x001110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqdmulh_V, typeof(AOpCodeSimdReg)); - SetA64("01111110xx100000011110xxxxxxxxxx", AInstEmit.Sqneg_S, typeof(AOpCodeSimd)); - SetA64("0>101110<<100000011110xxxxxxxxxx", AInstEmit.Sqneg_V, typeof(AOpCodeSimd)); - SetA64("01111110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_S, typeof(AOpCodeSimdReg)); - SetA64("01111110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_S, typeof(AOpCodeSimdReg)); - SetA64("0x101110011xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_V, typeof(AOpCodeSimdReg)); - SetA64("0x101110101xxxxx101101xxxxxxxxxx", AInstEmit.Sqrdmulh_V, typeof(AOpCodeSimdReg)); - SetA64("0101111100>>>xxx100111xxxxxxxxxx", AInstEmit.Sqrshrn_S, typeof(AOpCodeSimdShImm)); - SetA64("0x00111100>>>xxx100111xxxxxxxxxx", AInstEmit.Sqrshrn_V, typeof(AOpCodeSimdShImm)); - SetA64("0111111100>>>xxx100011xxxxxxxxxx", AInstEmit.Sqrshrun_S, typeof(AOpCodeSimdShImm)); - SetA64("0x10111100>>>xxx100011xxxxxxxxxx", AInstEmit.Sqrshrun_V, typeof(AOpCodeSimdShImm)); - SetA64("0101111100>>>xxx100101xxxxxxxxxx", AInstEmit.Sqshrn_S, typeof(AOpCodeSimdShImm)); - SetA64("0x00111100>>>xxx100101xxxxxxxxxx", AInstEmit.Sqshrn_V, typeof(AOpCodeSimdShImm)); - SetA64("0111111100>>>xxx100001xxxxxxxxxx", AInstEmit.Sqshrun_S, typeof(AOpCodeSimdShImm)); - SetA64("0x10111100>>>xxx100001xxxxxxxxxx", AInstEmit.Sqshrun_V, typeof(AOpCodeSimdShImm)); - SetA64("01011110xx1xxxxx001011xxxxxxxxxx", AInstEmit.Sqsub_S, typeof(AOpCodeSimdReg)); - SetA64("0>001110<<1xxxxx001011xxxxxxxxxx", AInstEmit.Sqsub_V, typeof(AOpCodeSimdReg)); - SetA64("01011110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_S, typeof(AOpCodeSimd)); - SetA64("0x001110<<100001010010xxxxxxxxxx", AInstEmit.Sqxtn_V, typeof(AOpCodeSimd)); - SetA64("01111110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_S, typeof(AOpCodeSimd)); - SetA64("0x101110<<100001001010xxxxxxxxxx", AInstEmit.Sqxtun_V, typeof(AOpCodeSimd)); - SetA64("0x001110<<1xxxxx000101xxxxxxxxxx", AInstEmit.Srhadd_V, typeof(AOpCodeSimdReg)); - SetA64("0101111101xxxxxx001001xxxxxxxxxx", AInstEmit.Srshr_S, typeof(AOpCodeSimdShImm)); - SetA64("0x00111100>>>xxx001001xxxxxxxxxx", AInstEmit.Srshr_V, typeof(AOpCodeSimdShImm)); - SetA64("0100111101xxxxxx001001xxxxxxxxxx", AInstEmit.Srshr_V, typeof(AOpCodeSimdShImm)); - SetA64("0101111101xxxxxx001101xxxxxxxxxx", AInstEmit.Srsra_S, typeof(AOpCodeSimdShImm)); - SetA64("0x00111100>>>xxx001101xxxxxxxxxx", AInstEmit.Srsra_V, typeof(AOpCodeSimdShImm)); - SetA64("0100111101xxxxxx001101xxxxxxxxxx", AInstEmit.Srsra_V, typeof(AOpCodeSimdShImm)); - SetA64("0>001110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Sshl_V, typeof(AOpCodeSimdReg)); - SetA64("0x00111100>>>xxx101001xxxxxxxxxx", AInstEmit.Sshll_V, typeof(AOpCodeSimdShImm)); - SetA64("0101111101xxxxxx000001xxxxxxxxxx", AInstEmit.Sshr_S, typeof(AOpCodeSimdShImm)); - SetA64("0x00111100>>>xxx000001xxxxxxxxxx", AInstEmit.Sshr_V, typeof(AOpCodeSimdShImm)); - SetA64("0100111101xxxxxx000001xxxxxxxxxx", AInstEmit.Sshr_V, typeof(AOpCodeSimdShImm)); - SetA64("0101111101xxxxxx000101xxxxxxxxxx", AInstEmit.Ssra_S, typeof(AOpCodeSimdShImm)); - SetA64("0x00111100>>>xxx000101xxxxxxxxxx", AInstEmit.Ssra_V, typeof(AOpCodeSimdShImm)); - SetA64("0100111101xxxxxx000101xxxxxxxxxx", AInstEmit.Ssra_V, typeof(AOpCodeSimdShImm)); - SetA64("0x001110<<1xxxxx001000xxxxxxxxxx", AInstEmit.Ssubl_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110<<1xxxxx001100xxxxxxxxxx", AInstEmit.Ssubw_V, typeof(AOpCodeSimdReg)); - SetA64("0x00110000000000xxxxxxxxxxxxxxxx", AInstEmit.St__Vms, typeof(AOpCodeSimdMemMs)); - SetA64("0x001100100xxxxxxxxxxxxxxxxxxxxx", AInstEmit.St__Vms, typeof(AOpCodeSimdMemMs)); - SetA64("0x00110100x00000xxxxxxxxxxxxxxxx", AInstEmit.St__Vss, typeof(AOpCodeSimdMemSs)); - SetA64("0x00110110xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.St__Vss, typeof(AOpCodeSimdMemSs)); - SetA64("xx10110xx0xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Stp, typeof(AOpCodeSimdMemPair)); - SetA64("xx111100x00xxxxxxxxx00xxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeSimdMemImm)); - SetA64("xx111100x00xxxxxxxxx01xxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeSimdMemImm)); - SetA64("xx111100x00xxxxxxxxx11xxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeSimdMemImm)); - SetA64("xx111101x0xxxxxxxxxxxxxxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeSimdMemImm)); - SetA64("xx111100x01xxxxxxxxx10xxxxxxxxxx", AInstEmit.Str, typeof(AOpCodeSimdMemReg)); - SetA64("01111110111xxxxx100001xxxxxxxxxx", AInstEmit.Sub_S, typeof(AOpCodeSimdReg)); - SetA64("0>101110<<1xxxxx100001xxxxxxxxxx", AInstEmit.Sub_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110<<1xxxxx011000xxxxxxxxxx", AInstEmit.Subhn_V, typeof(AOpCodeSimdReg)); - SetA64("01011110xx100000001110xxxxxxxxxx", AInstEmit.Suqadd_S, typeof(AOpCodeSimd)); - SetA64("0>001110<<100000001110xxxxxxxxxx", AInstEmit.Suqadd_V, typeof(AOpCodeSimd)); - SetA64("0x001110000xxxxx0xx000xxxxxxxxxx", AInstEmit.Tbl_V, typeof(AOpCodeSimdTbl)); - SetA64("0>001110<<0xxxxx001010xxxxxxxxxx", AInstEmit.Trn1_V, typeof(AOpCodeSimdReg)); - SetA64("0>001110<<0xxxxx011010xxxxxxxxxx", AInstEmit.Trn2_V, typeof(AOpCodeSimdReg)); - SetA64("0x101110<<1xxxxx011111xxxxxxxxxx", AInstEmit.Uaba_V, typeof(AOpCodeSimdReg)); - SetA64("0x101110<<1xxxxx010100xxxxxxxxxx", AInstEmit.Uabal_V, typeof(AOpCodeSimdReg)); - SetA64("0x101110<<1xxxxx011101xxxxxxxxxx", AInstEmit.Uabd_V, typeof(AOpCodeSimdReg)); - SetA64("0x101110<<1xxxxx011100xxxxxxxxxx", AInstEmit.Uabdl_V, typeof(AOpCodeSimdReg)); - SetA64("0x101110<<100000011010xxxxxxxxxx", AInstEmit.Uadalp_V, typeof(AOpCodeSimd)); - SetA64("0x101110<<1xxxxx000000xxxxxxxxxx", AInstEmit.Uaddl_V, typeof(AOpCodeSimdReg)); - SetA64("0x101110<<100000001010xxxxxxxxxx", AInstEmit.Uaddlp_V, typeof(AOpCodeSimd)); - SetA64("001011100x110000001110xxxxxxxxxx", AInstEmit.Uaddlv_V, typeof(AOpCodeSimd)); - SetA64("01101110<<110000001110xxxxxxxxxx", AInstEmit.Uaddlv_V, typeof(AOpCodeSimd)); - SetA64("0x101110<<1xxxxx000100xxxxxxxxxx", AInstEmit.Uaddw_V, typeof(AOpCodeSimdReg)); - SetA64("x0011110xx100011000000xxxxxxxxxx", AInstEmit.Ucvtf_Gp, typeof(AOpCodeSimdCvt)); - SetA64("011111100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_S, typeof(AOpCodeSimd)); - SetA64("0x1011100x100001110110xxxxxxxxxx", AInstEmit.Ucvtf_V, typeof(AOpCodeSimd)); - SetA64("0x101110<<1xxxxx000001xxxxxxxxxx", AInstEmit.Uhadd_V, typeof(AOpCodeSimdReg)); - SetA64("0x101110<<1xxxxx001001xxxxxxxxxx", AInstEmit.Uhsub_V, typeof(AOpCodeSimdReg)); - SetA64("0x101110<<1xxxxx011001xxxxxxxxxx", AInstEmit.Umax_V, typeof(AOpCodeSimdReg)); - SetA64("0x101110<<1xxxxx101001xxxxxxxxxx", AInstEmit.Umaxp_V, typeof(AOpCodeSimdReg)); - SetA64("0x101110<<1xxxxx011011xxxxxxxxxx", AInstEmit.Umin_V, typeof(AOpCodeSimdReg)); - SetA64("0x101110<<1xxxxx101011xxxxxxxxxx", AInstEmit.Uminp_V, typeof(AOpCodeSimdReg)); - SetA64("0x101110<<1xxxxx100000xxxxxxxxxx", AInstEmit.Umlal_V, typeof(AOpCodeSimdReg)); - SetA64("0x101110<<1xxxxx101000xxxxxxxxxx", AInstEmit.Umlsl_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110000xxxxx001111xxxxxxxxxx", AInstEmit.Umov_S, typeof(AOpCodeSimdIns)); - SetA64("0x101110<<1xxxxx110000xxxxxxxxxx", AInstEmit.Umull_V, typeof(AOpCodeSimdReg)); - SetA64("01111110xx1xxxxx000011xxxxxxxxxx", AInstEmit.Uqadd_S, typeof(AOpCodeSimdReg)); - SetA64("0>101110<<1xxxxx000011xxxxxxxxxx", AInstEmit.Uqadd_V, typeof(AOpCodeSimdReg)); - SetA64("0111111100>>>xxx100111xxxxxxxxxx", AInstEmit.Uqrshrn_S, typeof(AOpCodeSimdShImm)); - SetA64("0x10111100>>>xxx100111xxxxxxxxxx", AInstEmit.Uqrshrn_V, typeof(AOpCodeSimdShImm)); - SetA64("0111111100>>>xxx100101xxxxxxxxxx", AInstEmit.Uqshrn_S, typeof(AOpCodeSimdShImm)); - SetA64("0x10111100>>>xxx100101xxxxxxxxxx", AInstEmit.Uqshrn_V, typeof(AOpCodeSimdShImm)); - SetA64("01111110xx1xxxxx001011xxxxxxxxxx", AInstEmit.Uqsub_S, typeof(AOpCodeSimdReg)); - SetA64("0>101110<<1xxxxx001011xxxxxxxxxx", AInstEmit.Uqsub_V, typeof(AOpCodeSimdReg)); - SetA64("01111110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_S, typeof(AOpCodeSimd)); - SetA64("0x101110<<100001010010xxxxxxxxxx", AInstEmit.Uqxtn_V, typeof(AOpCodeSimd)); - SetA64("0x101110<<1xxxxx000101xxxxxxxxxx", AInstEmit.Urhadd_V, typeof(AOpCodeSimdReg)); - SetA64("0111111101xxxxxx001001xxxxxxxxxx", AInstEmit.Urshr_S, typeof(AOpCodeSimdShImm)); - SetA64("0x10111100>>>xxx001001xxxxxxxxxx", AInstEmit.Urshr_V, typeof(AOpCodeSimdShImm)); - SetA64("0110111101xxxxxx001001xxxxxxxxxx", AInstEmit.Urshr_V, typeof(AOpCodeSimdShImm)); - SetA64("0111111101xxxxxx001101xxxxxxxxxx", AInstEmit.Ursra_S, typeof(AOpCodeSimdShImm)); - SetA64("0x10111100>>>xxx001101xxxxxxxxxx", AInstEmit.Ursra_V, typeof(AOpCodeSimdShImm)); - SetA64("0110111101xxxxxx001101xxxxxxxxxx", AInstEmit.Ursra_V, typeof(AOpCodeSimdShImm)); - SetA64("0>101110<<1xxxxx010001xxxxxxxxxx", AInstEmit.Ushl_V, typeof(AOpCodeSimdReg)); - SetA64("0x10111100>>>xxx101001xxxxxxxxxx", AInstEmit.Ushll_V, typeof(AOpCodeSimdShImm)); - SetA64("0111111101xxxxxx000001xxxxxxxxxx", AInstEmit.Ushr_S, typeof(AOpCodeSimdShImm)); - SetA64("0x10111100>>>xxx000001xxxxxxxxxx", AInstEmit.Ushr_V, typeof(AOpCodeSimdShImm)); - SetA64("0110111101xxxxxx000001xxxxxxxxxx", AInstEmit.Ushr_V, typeof(AOpCodeSimdShImm)); - SetA64("01111110xx100000001110xxxxxxxxxx", AInstEmit.Usqadd_S, typeof(AOpCodeSimd)); - SetA64("0>101110<<100000001110xxxxxxxxxx", AInstEmit.Usqadd_V, typeof(AOpCodeSimd)); - SetA64("0111111101xxxxxx000101xxxxxxxxxx", AInstEmit.Usra_S, typeof(AOpCodeSimdShImm)); - SetA64("0x10111100>>>xxx000101xxxxxxxxxx", AInstEmit.Usra_V, typeof(AOpCodeSimdShImm)); - SetA64("0110111101xxxxxx000101xxxxxxxxxx", AInstEmit.Usra_V, typeof(AOpCodeSimdShImm)); - SetA64("0x101110<<1xxxxx001000xxxxxxxxxx", AInstEmit.Usubl_V, typeof(AOpCodeSimdReg)); - SetA64("0x101110<<1xxxxx001100xxxxxxxxxx", AInstEmit.Usubw_V, typeof(AOpCodeSimdReg)); - SetA64("0>001110<<0xxxxx000110xxxxxxxxxx", AInstEmit.Uzp1_V, typeof(AOpCodeSimdReg)); - SetA64("0>001110<<0xxxxx010110xxxxxxxxxx", AInstEmit.Uzp2_V, typeof(AOpCodeSimdReg)); - SetA64("0x001110<<100001001010xxxxxxxxxx", AInstEmit.Xtn_V, typeof(AOpCodeSimd)); - SetA64("0>001110<<0xxxxx001110xxxxxxxxxx", AInstEmit.Zip1_V, typeof(AOpCodeSimdReg)); - SetA64("0>001110<<0xxxxx011110xxxxxxxxxx", AInstEmit.Zip2_V, typeof(AOpCodeSimdReg)); -#endregion - -#region "Generate InstA64FastLookup Table (AArch64)" - var tmp = new List[_fastLookupSize]; - for (int i = 0; i < _fastLookupSize; i++) - { - tmp[i] = new List(); - } - - foreach (var inst in _allInstA64) - { - int mask = ToFastLookupIndex(inst.Mask); - int value = ToFastLookupIndex(inst.Value); - - for (int i = 0; i < _fastLookupSize; i++) - { - if ((i & mask) == value) - { - tmp[i].Add(inst); - } - } - } - - for (int i = 0; i < _fastLookupSize; i++) - { - _instA64FastLookup[i] = tmp[i].ToArray(); - } -#endregion - } - - private class InstInfo - { - public int Mask; - public int Value; - - public AInst Inst; - - public InstInfo(int mask, int value, AInst inst) - { - Mask = mask; - Value = value; - Inst = inst; - } - } - - private static List _allInstA32 = new List(); - private static List _allInstA64 = new List(); - - private static int _fastLookupSize = 0x1000; - private static InstInfo[][] _instA64FastLookup = new InstInfo[_fastLookupSize][]; - - private static void SetA32(string encoding, AInstInterpreter interpreter, Type type) - { - Set(encoding, new AInst(interpreter, null, type), AExecutionMode.AArch32); - } - - private static void SetA64(string encoding, AInstEmitter emitter, Type type) - { - Set(encoding, new AInst(null, emitter, type), AExecutionMode.AArch64); - } - - private static void Set(string encoding, AInst inst, AExecutionMode mode) - { - int bit = encoding.Length - 1; - int value = 0; - int xMask = 0; - int xBits = 0; - - int[] xPos = new int[encoding.Length]; - - int blacklisted = 0; - - for (int index = 0; index < encoding.Length; index++, bit--) - { - //Note: < and > are used on special encodings. - //The < means that we should never have ALL bits with the '<' set. - //So, when the encoding has <<, it means that 00, 01, and 10 are valid, - //but not 11. <<< is 000, 001, ..., 110 but NOT 111, and so on... - //For >, the invalid value is zero. So, for >> 01, 10 and 11 are valid, - //but 00 isn't. - char chr = encoding[index]; - - if (chr == '1') - { - value |= 1 << bit; - } - else if (chr == 'x') - { - xMask |= 1 << bit; - } - else if (chr == '>') - { - xPos[xBits++] = bit; - } - else if (chr == '<') - { - xPos[xBits++] = bit; - - blacklisted |= 1 << bit; - } - else if (chr != '0') - { - throw new ArgumentException(nameof(encoding)); - } - } - - xMask = ~xMask; - - if (xBits == 0) - { - InsertInst(xMask, value, inst, mode); - - return; - } - - for (int index = 0; index < (1 << xBits); index++) - { - int mask = 0; - - for (int x = 0; x < xBits; x++) - { - mask |= ((index >> x) & 1) << xPos[x]; - } - - if (mask != blacklisted) - { - InsertInst(xMask, value | mask, inst, mode); - } - } - } - - private static void InsertInst( - int xMask, - int value, - AInst inst, - AExecutionMode mode) - { - InstInfo info = new InstInfo(xMask, value, inst); - - if (mode == AExecutionMode.AArch64) - { - _allInstA64.Add(info); - } - else - { - _allInstA32.Add(info); - } - } - - public static AInst GetInstA32(int opCode) - { - return GetInstFromList(_allInstA32, opCode); - } - - public static AInst GetInstA64(int opCode) - { - return GetInstFromList(_instA64FastLookup[ToFastLookupIndex(opCode)], opCode); - } - - private static int ToFastLookupIndex(int value) - { - return ((value >> 10) & 0x00F) | ((value >> 18) & 0xFF0); - } - - private static AInst GetInstFromList(IEnumerable instList, int opCode) - { - foreach (var node in instList) - { - if ((opCode & node.Mask) == node.Value) - { - return node.Inst; - } - } - - return AInst.Undefined; - } - } -} diff --git a/ChocolArm64/AThread.cs b/ChocolArm64/AThread.cs index 9488232351..9ec690a33c 100644 --- a/ChocolArm64/AThread.cs +++ b/ChocolArm64/AThread.cs @@ -10,7 +10,7 @@ namespace ChocolArm64 public AThreadState ThreadState { get; private set; } public AMemory Memory { get; private set; } - private ATranslator _translator; + private Translator _translator; public Thread Work; @@ -18,14 +18,14 @@ namespace ChocolArm64 private int _isExecuting; - public AThread(ATranslator translator, AMemory memory, long entryPoint) + public AThread(Translator translator, AMemory memory, long entryPoint) { _translator = translator; Memory = memory; ThreadState = new AThreadState(); - ThreadState.ExecutionMode = AExecutionMode.AArch64; + ThreadState.ExecutionMode = ExecutionMode.AArch64; ThreadState.Running = true; diff --git a/ChocolArm64/ABitUtils.cs b/ChocolArm64/BitUtils.cs similarity index 97% rename from ChocolArm64/ABitUtils.cs rename to ChocolArm64/BitUtils.cs index 9452f7de53..881ee24842 100644 --- a/ChocolArm64/ABitUtils.cs +++ b/ChocolArm64/BitUtils.cs @@ -1,6 +1,6 @@ namespace ChocolArm64 { - static class ABitUtils + static class BitUtils { public static int HighestBitSet32(int value) { diff --git a/ChocolArm64/Decoder/ADecoder.cs b/ChocolArm64/Decoder/ADecoder.cs index b6658fb3ea..ed854d0944 100644 --- a/ChocolArm64/Decoder/ADecoder.cs +++ b/ChocolArm64/Decoder/ADecoder.cs @@ -10,7 +10,7 @@ namespace ChocolArm64.Decoder { static class ADecoder { - private delegate object OpActivator(AInst inst, long position, int opCode); + private delegate object OpActivator(Inst inst, long position, int opCode); private static ConcurrentDictionary _opActivators; @@ -19,31 +19,31 @@ namespace ChocolArm64.Decoder _opActivators = new ConcurrentDictionary(); } - public static ABlock DecodeBasicBlock(AThreadState state, AMemory memory, long start) + public static Block DecodeBasicBlock(AThreadState state, AMemory memory, long start) { - ABlock block = new ABlock(start); + Block block = new Block(start); FillBlock(state, memory, block); return block; } - public static (ABlock[] Graph, ABlock Root) DecodeSubroutine( - ATranslatorCache cache, + public static (Block[] Graph, Block Root) DecodeSubroutine( + TranslatorCache cache, AThreadState state, AMemory memory, long start) { - Dictionary visited = new Dictionary(); - Dictionary visitedEnd = new Dictionary(); + Dictionary visited = new Dictionary(); + Dictionary visitedEnd = new Dictionary(); - Queue blocks = new Queue(); + Queue blocks = new Queue(); - ABlock Enqueue(long position) + Block Enqueue(long position) { - if (!visited.TryGetValue(position, out ABlock output)) + if (!visited.TryGetValue(position, out Block output)) { - output = new ABlock(position); + output = new Block(position); blocks.Enqueue(output); @@ -53,11 +53,11 @@ namespace ChocolArm64.Decoder return output; } - ABlock root = Enqueue(start); + Block root = Enqueue(start); while (blocks.Count > 0) { - ABlock current = blocks.Dequeue(); + Block current = blocks.Dequeue(); FillBlock(state, memory, current); @@ -71,9 +71,9 @@ namespace ChocolArm64.Decoder AOpCode lastOp = current.GetLastOp(); - if (lastOp is AOpCodeBImm op) + if (lastOp is OpCodeBImm op) { - if (op.Emitter == AInstEmit.Bl) + if (op.Emitter == InstEmit.Bl) { hasCachedSub = cache.HasSubroutine(op.Imm); } @@ -83,8 +83,8 @@ namespace ChocolArm64.Decoder } } - if (!((lastOp is AOpCodeBImmAl) || - (lastOp is AOpCodeBReg)) || hasCachedSub) + if (!((lastOp is OpCodeBImmAl) || + (lastOp is OpCodeBReg)) || hasCachedSub) { current.Next = Enqueue(current.EndPosition); } @@ -94,11 +94,11 @@ namespace ChocolArm64.Decoder //then we need to split the bigger block and have two small blocks, //the end position of the bigger "Current" block should then be == to //the position of the "Smaller" block. - while (visitedEnd.TryGetValue(current.EndPosition, out ABlock smaller)) + while (visitedEnd.TryGetValue(current.EndPosition, out Block smaller)) { if (current.Position > smaller.Position) { - ABlock temp = smaller; + Block temp = smaller; smaller = current; current = temp; @@ -119,19 +119,19 @@ namespace ChocolArm64.Decoder } //Make and sort Graph blocks array by position. - ABlock[] graph = new ABlock[visited.Count]; + Block[] graph = new Block[visited.Count]; while (visited.Count > 0) { ulong firstPos = ulong.MaxValue; - foreach (ABlock block in visited.Values) + foreach (Block block in visited.Values) { if (firstPos > (ulong)block.Position) firstPos = (ulong)block.Position; } - ABlock current = visited[(long)firstPos]; + Block current = visited[(long)firstPos]; do { @@ -147,7 +147,7 @@ namespace ChocolArm64.Decoder return (graph, root); } - private static void FillBlock(AThreadState state, AMemory memory, ABlock block) + private static void FillBlock(AThreadState state, AMemory memory, Block block) { long position = block.Position; @@ -170,34 +170,34 @@ namespace ChocolArm64.Decoder private static bool IsBranch(AOpCode opCode) { - return opCode is AOpCodeBImm || - opCode is AOpCodeBReg; + return opCode is OpCodeBImm || + opCode is OpCodeBReg; } private static bool IsException(AOpCode opCode) { - return opCode.Emitter == AInstEmit.Brk || - opCode.Emitter == AInstEmit.Svc || - opCode.Emitter == AInstEmit.Und; + return opCode.Emitter == InstEmit.Brk || + opCode.Emitter == InstEmit.Svc || + opCode.Emitter == InstEmit.Und; } public static AOpCode DecodeOpCode(AThreadState state, AMemory memory, long position) { int opCode = memory.ReadInt32(position); - AInst inst; + Inst inst; - if (state.ExecutionMode == AExecutionMode.AArch64) + if (state.ExecutionMode == ExecutionMode.AArch64) { - inst = AOpCodeTable.GetInstA64(opCode); + inst = OpCodeTable.GetInstA64(opCode); } else { //TODO: Thumb support. - inst = AOpCodeTable.GetInstA32(opCode); + inst = OpCodeTable.GetInstA32(opCode); } - AOpCode decodedOpCode = new AOpCode(AInst.Undefined, position, opCode); + AOpCode decodedOpCode = new AOpCode(Inst.Undefined, position, opCode); if (inst.Type != null) { @@ -207,7 +207,7 @@ namespace ChocolArm64.Decoder return decodedOpCode; } - private static AOpCode MakeOpCode(Type type, AInst inst, long position, int opCode) + private static AOpCode MakeOpCode(Type type, Inst inst, long position, int opCode) { if (type == null) { @@ -221,7 +221,7 @@ namespace ChocolArm64.Decoder private static OpActivator CacheOpActivator(Type type) { - Type[] argTypes = new Type[] { typeof(AInst), typeof(long), typeof(int) }; + Type[] argTypes = new Type[] { typeof(Inst), typeof(long), typeof(int) }; DynamicMethod mthd = new DynamicMethod($"Make{type.Name}", type, argTypes); diff --git a/ChocolArm64/Decoder/AOpCode.cs b/ChocolArm64/Decoder/AOpCode.cs index 2799b18ceb..e990cdc087 100644 --- a/ChocolArm64/Decoder/AOpCode.cs +++ b/ChocolArm64/Decoder/AOpCode.cs @@ -4,21 +4,21 @@ using System; namespace ChocolArm64.Decoder { - class AOpCode : IaOpCode + class AOpCode : IOpCode { public long Position { get; private set; } public int RawOpCode { get; private set; } - public AInstEmitter Emitter { get; protected set; } - public AInstInterpreter Interpreter { get; protected set; } - public ARegisterSize RegisterSize { get; protected set; } + public InstEmitter Emitter { get; protected set; } + public InstInterpreter Interpreter { get; protected set; } + public RegisterSize RegisterSize { get; protected set; } - public AOpCode(AInst inst, long position, int opCode) + public AOpCode(Inst inst, long position, int opCode) { Position = position; RawOpCode = opCode; - RegisterSize = ARegisterSize.Int64; + RegisterSize = RegisterSize.Int64; Emitter = inst.Emitter; Interpreter = inst.Interpreter; @@ -28,10 +28,10 @@ namespace ChocolArm64.Decoder { switch (RegisterSize) { - case ARegisterSize.Int32: return 32; - case ARegisterSize.Int64: return 64; - case ARegisterSize.Simd64: return 64; - case ARegisterSize.Simd128: return 128; + case RegisterSize.Int32: return 32; + case RegisterSize.Int64: return 64; + case RegisterSize.Simd64: return 64; + case RegisterSize.Simd128: return 128; } throw new InvalidOperationException(); diff --git a/ChocolArm64/Decoder/AOpCodeBImm.cs b/ChocolArm64/Decoder/AOpCodeBImm.cs deleted file mode 100644 index 2d6b3d5c2e..0000000000 --- a/ChocolArm64/Decoder/AOpCodeBImm.cs +++ /dev/null @@ -1,11 +0,0 @@ -using ChocolArm64.Instruction; - -namespace ChocolArm64.Decoder -{ - class AOpCodeBImm : AOpCode - { - public long Imm { get; protected set; } - - public AOpCodeBImm(AInst inst, long position, int opCode) : base(inst, position, opCode) { } - } -} \ No newline at end of file diff --git a/ChocolArm64/Decoder/AOpCodeBImmAl.cs b/ChocolArm64/Decoder/AOpCodeBImmAl.cs deleted file mode 100644 index 555be019e0..0000000000 --- a/ChocolArm64/Decoder/AOpCodeBImmAl.cs +++ /dev/null @@ -1,12 +0,0 @@ -using ChocolArm64.Instruction; - -namespace ChocolArm64.Decoder -{ - class AOpCodeBImmAl : AOpCodeBImm - { - public AOpCodeBImmAl(AInst inst, long position, int opCode) : base(inst, position, opCode) - { - Imm = position + ADecoderHelper.DecodeImm26_2(opCode); - } - } -} \ No newline at end of file diff --git a/ChocolArm64/Decoder/AOpCodeBImmCmp.cs b/ChocolArm64/Decoder/AOpCodeBImmCmp.cs deleted file mode 100644 index 40c087567c..0000000000 --- a/ChocolArm64/Decoder/AOpCodeBImmCmp.cs +++ /dev/null @@ -1,21 +0,0 @@ -using ChocolArm64.Instruction; -using ChocolArm64.State; - -namespace ChocolArm64.Decoder -{ - class AOpCodeBImmCmp : AOpCodeBImm - { - public int Rt { get; private set; } - - public AOpCodeBImmCmp(AInst inst, long position, int opCode) : base(inst, position, opCode) - { - Rt = opCode & 0x1f; - - Imm = position + ADecoderHelper.DecodeImmS19_2(opCode); - - RegisterSize = (opCode >> 31) != 0 - ? ARegisterSize.Int64 - : ARegisterSize.Int32; - } - } -} \ No newline at end of file diff --git a/ChocolArm64/Decoder/AOpCodeBImmCond.cs b/ChocolArm64/Decoder/AOpCodeBImmCond.cs deleted file mode 100644 index 9881fa6625..0000000000 --- a/ChocolArm64/Decoder/AOpCodeBImmCond.cs +++ /dev/null @@ -1,25 +0,0 @@ -using ChocolArm64.Instruction; - -namespace ChocolArm64.Decoder -{ - class AOpCodeBImmCond : AOpCodeBImm, IaOpCodeCond - { - public ACond Cond { get; private set; } - - public AOpCodeBImmCond(AInst inst, long position, int opCode) : base(inst, position, opCode) - { - int o0 = (opCode >> 4) & 1; - - if (o0 != 0) - { - Emitter = AInstEmit.Und; - - return; - } - - Cond = (ACond)(opCode & 0xf); - - Imm = position + ADecoderHelper.DecodeImmS19_2(opCode); - } - } -} \ No newline at end of file diff --git a/ChocolArm64/Decoder/AOpCodeCcmpImm.cs b/ChocolArm64/Decoder/AOpCodeCcmpImm.cs deleted file mode 100644 index 629e272c5c..0000000000 --- a/ChocolArm64/Decoder/AOpCodeCcmpImm.cs +++ /dev/null @@ -1,11 +0,0 @@ -using ChocolArm64.Instruction; - -namespace ChocolArm64.Decoder -{ - class AOpCodeCcmpImm : AOpCodeCcmp, IaOpCodeAluImm - { - public long Imm => RmImm; - - public AOpCodeCcmpImm(AInst inst, long position, int opCode) : base(inst, position, opCode) { } - } -} \ No newline at end of file diff --git a/ChocolArm64/Decoder/AOpCodeCcmpReg.cs b/ChocolArm64/Decoder/AOpCodeCcmpReg.cs deleted file mode 100644 index f8500382fc..0000000000 --- a/ChocolArm64/Decoder/AOpCodeCcmpReg.cs +++ /dev/null @@ -1,15 +0,0 @@ -using ChocolArm64.Instruction; - -namespace ChocolArm64.Decoder -{ - class AOpCodeCcmpReg : AOpCodeCcmp, IaOpCodeAluRs - { - public int Rm => RmImm; - - public int Shift => 0; - - public AShiftType ShiftType => AShiftType.Lsl; - - public AOpCodeCcmpReg(AInst inst, long position, int opCode) : base(inst, position, opCode) { } - } -} \ No newline at end of file diff --git a/ChocolArm64/Decoder/AOpCodeCsel.cs b/ChocolArm64/Decoder/AOpCodeCsel.cs deleted file mode 100644 index d5c78bff0c..0000000000 --- a/ChocolArm64/Decoder/AOpCodeCsel.cs +++ /dev/null @@ -1,17 +0,0 @@ -using ChocolArm64.Instruction; - -namespace ChocolArm64.Decoder -{ - class AOpCodeCsel : AOpCodeAlu, IaOpCodeCond - { - public int Rm { get; private set; } - - public ACond Cond { get; private set; } - - public AOpCodeCsel(AInst inst, long position, int opCode) : base(inst, position, opCode) - { - Rm = (opCode >> 16) & 0x1f; - Cond = (ACond)((opCode >> 12) & 0xf); - } - } -} \ No newline at end of file diff --git a/ChocolArm64/Decoder/AOpCodeSimdFcond.cs b/ChocolArm64/Decoder/AOpCodeSimdFcond.cs deleted file mode 100644 index f204a9c4a0..0000000000 --- a/ChocolArm64/Decoder/AOpCodeSimdFcond.cs +++ /dev/null @@ -1,17 +0,0 @@ -using ChocolArm64.Instruction; - -namespace ChocolArm64.Decoder -{ - class AOpCodeSimdFcond : AOpCodeSimdReg, IaOpCodeCond - { - public int Nzcv { get; private set; } - - public ACond Cond { get; private set; } - - public AOpCodeSimdFcond(AInst inst, long position, int opCode) : base(inst, position, opCode) - { - Nzcv = (opCode >> 0) & 0xf; - Cond = (ACond)((opCode >> 12) & 0xf); - } - } -} \ No newline at end of file diff --git a/ChocolArm64/Decoder/AOpCodeSimdShImm.cs b/ChocolArm64/Decoder/AOpCodeSimdShImm.cs deleted file mode 100644 index e83476fee7..0000000000 --- a/ChocolArm64/Decoder/AOpCodeSimdShImm.cs +++ /dev/null @@ -1,16 +0,0 @@ -using ChocolArm64.Instruction; - -namespace ChocolArm64.Decoder -{ - class AOpCodeSimdShImm : AOpCodeSimd - { - public int Imm { get; private set; } - - public AOpCodeSimdShImm(AInst inst, long position, int opCode) : base(inst, position, opCode) - { - Imm = (opCode >> 16) & 0x7f; - - Size = ABitUtils.HighestBitSetNibble(Imm >> 3); - } - } -} diff --git a/ChocolArm64/Decoder/ABlock.cs b/ChocolArm64/Decoder/Block.cs similarity index 75% rename from ChocolArm64/Decoder/ABlock.cs rename to ChocolArm64/Decoder/Block.cs index a865d3d7af..28b7c20fff 100644 --- a/ChocolArm64/Decoder/ABlock.cs +++ b/ChocolArm64/Decoder/Block.cs @@ -2,22 +2,22 @@ using System.Collections.Generic; namespace ChocolArm64.Decoder { - class ABlock + class Block { public long Position { get; set; } public long EndPosition { get; set; } - public ABlock Next { get; set; } - public ABlock Branch { get; set; } + public Block Next { get; set; } + public Block Branch { get; set; } public List OpCodes { get; private set; } - public ABlock() + public Block() { OpCodes = new List(); } - public ABlock(long position) : this() + public Block(long position) : this() { Position = position; } diff --git a/ChocolArm64/Decoder/ACond.cs b/ChocolArm64/Decoder/Cond.cs similarity index 95% rename from ChocolArm64/Decoder/ACond.cs rename to ChocolArm64/Decoder/Cond.cs index 9e3125ac24..fe8c573e8e 100644 --- a/ChocolArm64/Decoder/ACond.cs +++ b/ChocolArm64/Decoder/Cond.cs @@ -1,6 +1,6 @@ namespace ChocolArm64.Decoder { - enum ACond + enum Cond { Eq = 0, Ne = 1, diff --git a/ChocolArm64/Decoder/ADataOp.cs b/ChocolArm64/Decoder/DataOp.cs similarity index 89% rename from ChocolArm64/Decoder/ADataOp.cs rename to ChocolArm64/Decoder/DataOp.cs index a5601a3abc..b34798cb71 100644 --- a/ChocolArm64/Decoder/ADataOp.cs +++ b/ChocolArm64/Decoder/DataOp.cs @@ -1,6 +1,6 @@ namespace ChocolArm64.Decoder { - enum ADataOp + enum DataOp { Adr = 0, Arithmetic = 1, diff --git a/ChocolArm64/Decoder/ADecoderHelper.cs b/ChocolArm64/Decoder/DecoderHelper.cs similarity index 82% rename from ChocolArm64/Decoder/ADecoderHelper.cs rename to ChocolArm64/Decoder/DecoderHelper.cs index d0c1a3d894..8be984a945 100644 --- a/ChocolArm64/Decoder/ADecoderHelper.cs +++ b/ChocolArm64/Decoder/DecoderHelper.cs @@ -2,7 +2,7 @@ using System; namespace ChocolArm64.Decoder { - static class ADecoderHelper + static class DecoderHelper { public struct BitMask { @@ -23,7 +23,7 @@ namespace ChocolArm64.Decoder int n = (opCode >> 22) & 1; int sf = (opCode >> 31) & 1; - int length = ABitUtils.HighestBitSet32((~immS & 0x3f) | (n << 6)); + int length = BitUtils.HighestBitSet32((~immS & 0x3f) | (n << 6)); if (length < 1 || (sf == 0 && n != 0)) { @@ -42,19 +42,19 @@ namespace ChocolArm64.Decoder return BitMask.Invalid; } - long wMask = ABitUtils.FillWithOnes(s + 1); - long tMask = ABitUtils.FillWithOnes(((s - r) & levels) + 1); + long wMask = BitUtils.FillWithOnes(s + 1); + long tMask = BitUtils.FillWithOnes(((s - r) & levels) + 1); if (r > 0) { - wMask = ABitUtils.RotateRight(wMask, r, size); - wMask &= ABitUtils.FillWithOnes(size); + wMask = BitUtils.RotateRight(wMask, r, size); + wMask &= BitUtils.FillWithOnes(size); } return new BitMask() { - WMask = ABitUtils.Replicate(wMask, size), - TMask = ABitUtils.Replicate(tMask, size), + WMask = BitUtils.Replicate(wMask, size), + TMask = BitUtils.Replicate(tMask, size), Pos = immS, Shift = immR diff --git a/ChocolArm64/Decoder/IAOpCodeCond.cs b/ChocolArm64/Decoder/IAOpCodeCond.cs deleted file mode 100644 index fc8f05718c..0000000000 --- a/ChocolArm64/Decoder/IAOpCodeCond.cs +++ /dev/null @@ -1,7 +0,0 @@ -namespace ChocolArm64.Decoder -{ - interface IaOpCodeCond : IaOpCode - { - ACond Cond { get; } - } -} \ No newline at end of file diff --git a/ChocolArm64/Decoder/IAOpCode.cs b/ChocolArm64/Decoder/IOpCode.cs similarity index 54% rename from ChocolArm64/Decoder/IAOpCode.cs rename to ChocolArm64/Decoder/IOpCode.cs index 700f1367b5..66361c3241 100644 --- a/ChocolArm64/Decoder/IAOpCode.cs +++ b/ChocolArm64/Decoder/IOpCode.cs @@ -3,11 +3,11 @@ using ChocolArm64.State; namespace ChocolArm64.Decoder { - interface IaOpCode + interface IOpCode { long Position { get; } - AInstEmitter Emitter { get; } - ARegisterSize RegisterSize { get; } + InstEmitter Emitter { get; } + RegisterSize RegisterSize { get; } } } \ No newline at end of file diff --git a/ChocolArm64/Decoder/IAOpCodeAlu.cs b/ChocolArm64/Decoder/IOpCodeAlu.cs similarity index 57% rename from ChocolArm64/Decoder/IAOpCodeAlu.cs rename to ChocolArm64/Decoder/IOpCodeAlu.cs index ed3ea26166..34b9460095 100644 --- a/ChocolArm64/Decoder/IAOpCodeAlu.cs +++ b/ChocolArm64/Decoder/IOpCodeAlu.cs @@ -1,10 +1,10 @@ namespace ChocolArm64.Decoder { - interface IaOpCodeAlu : IaOpCode + interface IOpCodeAlu : IOpCode { int Rd { get; } int Rn { get; } - ADataOp DataOp { get; } + DataOp DataOp { get; } } } \ No newline at end of file diff --git a/ChocolArm64/Decoder/IAOpCodeAluImm.cs b/ChocolArm64/Decoder/IOpCodeAluImm.cs similarity index 62% rename from ChocolArm64/Decoder/IAOpCodeAluImm.cs rename to ChocolArm64/Decoder/IOpCodeAluImm.cs index 688352d5ac..9e57a896c2 100644 --- a/ChocolArm64/Decoder/IAOpCodeAluImm.cs +++ b/ChocolArm64/Decoder/IOpCodeAluImm.cs @@ -1,6 +1,6 @@ namespace ChocolArm64.Decoder { - interface IaOpCodeAluImm : IaOpCodeAlu + interface IOpCodeAluImm : IOpCodeAlu { long Imm { get; } } diff --git a/ChocolArm64/Decoder/IAOpCodeAluRs.cs b/ChocolArm64/Decoder/IOpCodeAluRs.cs similarity index 55% rename from ChocolArm64/Decoder/IAOpCodeAluRs.cs rename to ChocolArm64/Decoder/IOpCodeAluRs.cs index 384c7e7b0e..52a74ad9a6 100644 --- a/ChocolArm64/Decoder/IAOpCodeAluRs.cs +++ b/ChocolArm64/Decoder/IOpCodeAluRs.cs @@ -1,10 +1,10 @@ namespace ChocolArm64.Decoder { - interface IaOpCodeAluRs : IaOpCodeAlu + interface IOpCodeAluRs : IOpCodeAlu { int Shift { get; } int Rm { get; } - AShiftType ShiftType { get; } + ShiftType ShiftType { get; } } } \ No newline at end of file diff --git a/ChocolArm64/Decoder/IAOpCodeAluRx.cs b/ChocolArm64/Decoder/IOpCodeAluRx.cs similarity index 56% rename from ChocolArm64/Decoder/IAOpCodeAluRx.cs rename to ChocolArm64/Decoder/IOpCodeAluRx.cs index aa031f4e76..9c6219a25a 100644 --- a/ChocolArm64/Decoder/IAOpCodeAluRx.cs +++ b/ChocolArm64/Decoder/IOpCodeAluRx.cs @@ -1,10 +1,10 @@ namespace ChocolArm64.Decoder { - interface IaOpCodeAluRx : IaOpCodeAlu + interface IOpCodeAluRx : IOpCodeAlu { int Shift { get; } int Rm { get; } - AIntType IntType { get; } + IntType IntType { get; } } } \ No newline at end of file diff --git a/ChocolArm64/Decoder/IOpCodeCond.cs b/ChocolArm64/Decoder/IOpCodeCond.cs new file mode 100644 index 0000000000..65fe9f419f --- /dev/null +++ b/ChocolArm64/Decoder/IOpCodeCond.cs @@ -0,0 +1,7 @@ +namespace ChocolArm64.Decoder +{ + interface IOpCodeCond : IOpCode + { + Cond Cond { get; } + } +} \ No newline at end of file diff --git a/ChocolArm64/Decoder/IAOpCodeLit.cs b/ChocolArm64/Decoder/IOpCodeLit.cs similarity index 84% rename from ChocolArm64/Decoder/IAOpCodeLit.cs rename to ChocolArm64/Decoder/IOpCodeLit.cs index 7396fe0714..ec99512997 100644 --- a/ChocolArm64/Decoder/IAOpCodeLit.cs +++ b/ChocolArm64/Decoder/IOpCodeLit.cs @@ -1,6 +1,6 @@ namespace ChocolArm64.Decoder { - interface IaOpCodeLit : IaOpCode + interface IOpCodeLit : IOpCode { int Rt { get; } long Imm { get; } diff --git a/ChocolArm64/Decoder/IAOpCodeSimd.cs b/ChocolArm64/Decoder/IOpCodeSimd.cs similarity index 65% rename from ChocolArm64/Decoder/IAOpCodeSimd.cs rename to ChocolArm64/Decoder/IOpCodeSimd.cs index 1f215e0e29..1148314a58 100644 --- a/ChocolArm64/Decoder/IAOpCodeSimd.cs +++ b/ChocolArm64/Decoder/IOpCodeSimd.cs @@ -1,6 +1,6 @@ namespace ChocolArm64.Decoder { - interface IaOpCodeSimd : IaOpCode + interface IOpCodeSimd : IOpCode { int Size { get; } } diff --git a/ChocolArm64/Decoder/AIntType.cs b/ChocolArm64/Decoder/IntType.cs similarity index 91% rename from ChocolArm64/Decoder/AIntType.cs rename to ChocolArm64/Decoder/IntType.cs index 242fdada14..f8cccaab95 100644 --- a/ChocolArm64/Decoder/AIntType.cs +++ b/ChocolArm64/Decoder/IntType.cs @@ -1,6 +1,6 @@ namespace ChocolArm64.Decoder { - enum AIntType + enum IntType { UInt8 = 0, UInt16 = 1, diff --git a/ChocolArm64/Decoder/AOpCodeAdr.cs b/ChocolArm64/Decoder/OpCodeAdr.cs similarity index 59% rename from ChocolArm64/Decoder/AOpCodeAdr.cs rename to ChocolArm64/Decoder/OpCodeAdr.cs index 1f525bd122..3f38e25158 100644 --- a/ChocolArm64/Decoder/AOpCodeAdr.cs +++ b/ChocolArm64/Decoder/OpCodeAdr.cs @@ -2,16 +2,16 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeAdr : AOpCode + class OpCodeAdr : AOpCode { public int Rd { get; private set; } public long Imm { get; private set; } - public AOpCodeAdr(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeAdr(Inst inst, long position, int opCode) : base(inst, position, opCode) { Rd = opCode & 0x1f; - Imm = ADecoderHelper.DecodeImmS19_2(opCode); + Imm = DecoderHelper.DecodeImmS19_2(opCode); Imm |= ((long)opCode >> 29) & 3; } } diff --git a/ChocolArm64/Decoder/AOpCodeAlu.cs b/ChocolArm64/Decoder/OpCodeAlu.cs similarity index 53% rename from ChocolArm64/Decoder/AOpCodeAlu.cs rename to ChocolArm64/Decoder/OpCodeAlu.cs index 844ef9bf1f..4b3362b7b8 100644 --- a/ChocolArm64/Decoder/AOpCodeAlu.cs +++ b/ChocolArm64/Decoder/OpCodeAlu.cs @@ -3,22 +3,22 @@ using ChocolArm64.State; namespace ChocolArm64.Decoder { - class AOpCodeAlu : AOpCode, IaOpCodeAlu + class OpCodeAlu : AOpCode, IOpCodeAlu { public int Rd { get; protected set; } public int Rn { get; private set; } - public ADataOp DataOp { get; private set; } + public DataOp DataOp { get; private set; } - public AOpCodeAlu(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeAlu(Inst inst, long position, int opCode) : base(inst, position, opCode) { Rd = (opCode >> 0) & 0x1f; Rn = (opCode >> 5) & 0x1f; - DataOp = (ADataOp)((opCode >> 24) & 0x3); + DataOp = (DataOp)((opCode >> 24) & 0x3); RegisterSize = (opCode >> 31) != 0 - ? ARegisterSize.Int64 - : ARegisterSize.Int32; + ? State.RegisterSize.Int64 + : State.RegisterSize.Int32; } } } \ No newline at end of file diff --git a/ChocolArm64/Decoder/AOpCodeAluImm.cs b/ChocolArm64/Decoder/OpCodeAluImm.cs similarity index 61% rename from ChocolArm64/Decoder/AOpCodeAluImm.cs rename to ChocolArm64/Decoder/OpCodeAluImm.cs index e441a84414..2265f9e5d2 100644 --- a/ChocolArm64/Decoder/AOpCodeAluImm.cs +++ b/ChocolArm64/Decoder/OpCodeAluImm.cs @@ -3,13 +3,13 @@ using System; namespace ChocolArm64.Decoder { - class AOpCodeAluImm : AOpCodeAlu, IaOpCodeAluImm + class OpCodeAluImm : OpCodeAlu, IOpCodeAluImm { public long Imm { get; private set; } - public AOpCodeAluImm(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeAluImm(Inst inst, long position, int opCode) : base(inst, position, opCode) { - if (DataOp == ADataOp.Arithmetic) + if (DataOp == DataOp.Arithmetic) { Imm = (opCode >> 10) & 0xfff; @@ -17,13 +17,13 @@ namespace ChocolArm64.Decoder Imm <<= shift * 12; } - else if (DataOp == ADataOp.Logical) + else if (DataOp == DataOp.Logical) { - var bm = ADecoderHelper.DecodeBitMask(opCode, true); + var bm = DecoderHelper.DecodeBitMask(opCode, true); if (bm.IsUndefined) { - Emitter = AInstEmit.Und; + Emitter = InstEmit.Und; return; } diff --git a/ChocolArm64/Decoder/AOpCodeAluRs.cs b/ChocolArm64/Decoder/OpCodeAluRs.cs similarity index 57% rename from ChocolArm64/Decoder/AOpCodeAluRs.cs rename to ChocolArm64/Decoder/OpCodeAluRs.cs index b2f6541a59..21b92c725c 100644 --- a/ChocolArm64/Decoder/AOpCodeAluRs.cs +++ b/ChocolArm64/Decoder/OpCodeAluRs.cs @@ -2,20 +2,20 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeAluRs : AOpCodeAlu, IaOpCodeAluRs + class OpCodeAluRs : OpCodeAlu, IOpCodeAluRs { public int Shift { get; private set; } public int Rm { get; private set; } - public AShiftType ShiftType { get; private set; } + public ShiftType ShiftType { get; private set; } - public AOpCodeAluRs(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeAluRs(Inst inst, long position, int opCode) : base(inst, position, opCode) { int shift = (opCode >> 10) & 0x3f; if (shift >= GetBitsCount()) { - Emitter = AInstEmit.Und; + Emitter = InstEmit.Und; return; } @@ -23,7 +23,7 @@ namespace ChocolArm64.Decoder Shift = shift; Rm = (opCode >> 16) & 0x1f; - ShiftType = (AShiftType)((opCode >> 22) & 0x3); + ShiftType = (ShiftType)((opCode >> 22) & 0x3); } } } \ No newline at end of file diff --git a/ChocolArm64/Decoder/AOpCodeAluRx.cs b/ChocolArm64/Decoder/OpCodeAluRx.cs similarity index 53% rename from ChocolArm64/Decoder/AOpCodeAluRx.cs rename to ChocolArm64/Decoder/OpCodeAluRx.cs index c2cad926c7..3235da0fef 100644 --- a/ChocolArm64/Decoder/AOpCodeAluRx.cs +++ b/ChocolArm64/Decoder/OpCodeAluRx.cs @@ -2,17 +2,17 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeAluRx : AOpCodeAlu, IaOpCodeAluRx + class OpCodeAluRx : OpCodeAlu, IOpCodeAluRx { public int Shift { get; private set; } public int Rm { get; private set; } - public AIntType IntType { get; private set; } + public IntType IntType { get; private set; } - public AOpCodeAluRx(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeAluRx(Inst inst, long position, int opCode) : base(inst, position, opCode) { Shift = (opCode >> 10) & 0x7; - IntType = (AIntType)((opCode >> 13) & 0x7); + IntType = (IntType)((opCode >> 13) & 0x7); Rm = (opCode >> 16) & 0x1f; } } diff --git a/ChocolArm64/Decoder/OpCodeBImm.cs b/ChocolArm64/Decoder/OpCodeBImm.cs new file mode 100644 index 0000000000..1cfedfabb8 --- /dev/null +++ b/ChocolArm64/Decoder/OpCodeBImm.cs @@ -0,0 +1,11 @@ +using ChocolArm64.Instruction; + +namespace ChocolArm64.Decoder +{ + class OpCodeBImm : AOpCode + { + public long Imm { get; protected set; } + + public OpCodeBImm(Inst inst, long position, int opCode) : base(inst, position, opCode) { } + } +} \ No newline at end of file diff --git a/ChocolArm64/Decoder/OpCodeBImmAl.cs b/ChocolArm64/Decoder/OpCodeBImmAl.cs new file mode 100644 index 0000000000..52df0ffcac --- /dev/null +++ b/ChocolArm64/Decoder/OpCodeBImmAl.cs @@ -0,0 +1,12 @@ +using ChocolArm64.Instruction; + +namespace ChocolArm64.Decoder +{ + class OpCodeBImmAl : OpCodeBImm + { + public OpCodeBImmAl(Inst inst, long position, int opCode) : base(inst, position, opCode) + { + Imm = position + DecoderHelper.DecodeImm26_2(opCode); + } + } +} \ No newline at end of file diff --git a/ChocolArm64/Decoder/OpCodeBImmCmp.cs b/ChocolArm64/Decoder/OpCodeBImmCmp.cs new file mode 100644 index 0000000000..0f1c6dc8cb --- /dev/null +++ b/ChocolArm64/Decoder/OpCodeBImmCmp.cs @@ -0,0 +1,21 @@ +using ChocolArm64.Instruction; +using ChocolArm64.State; + +namespace ChocolArm64.Decoder +{ + class OpCodeBImmCmp : OpCodeBImm + { + public int Rt { get; private set; } + + public OpCodeBImmCmp(Inst inst, long position, int opCode) : base(inst, position, opCode) + { + Rt = opCode & 0x1f; + + Imm = position + DecoderHelper.DecodeImmS19_2(opCode); + + RegisterSize = (opCode >> 31) != 0 + ? State.RegisterSize.Int64 + : State.RegisterSize.Int32; + } + } +} \ No newline at end of file diff --git a/ChocolArm64/Decoder/OpCodeBImmCond.cs b/ChocolArm64/Decoder/OpCodeBImmCond.cs new file mode 100644 index 0000000000..c5a727c3a9 --- /dev/null +++ b/ChocolArm64/Decoder/OpCodeBImmCond.cs @@ -0,0 +1,25 @@ +using ChocolArm64.Instruction; + +namespace ChocolArm64.Decoder +{ + class OpCodeBImmCond : OpCodeBImm, IOpCodeCond + { + public Cond Cond { get; private set; } + + public OpCodeBImmCond(Inst inst, long position, int opCode) : base(inst, position, opCode) + { + int o0 = (opCode >> 4) & 1; + + if (o0 != 0) + { + Emitter = InstEmit.Und; + + return; + } + + Cond = (Cond)(opCode & 0xf); + + Imm = position + DecoderHelper.DecodeImmS19_2(opCode); + } + } +} \ No newline at end of file diff --git a/ChocolArm64/Decoder/AOpCodeBImmTest.cs b/ChocolArm64/Decoder/OpCodeBImmTest.cs similarity index 59% rename from ChocolArm64/Decoder/AOpCodeBImmTest.cs rename to ChocolArm64/Decoder/OpCodeBImmTest.cs index f438bb7809..6525679404 100644 --- a/ChocolArm64/Decoder/AOpCodeBImmTest.cs +++ b/ChocolArm64/Decoder/OpCodeBImmTest.cs @@ -2,16 +2,16 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeBImmTest : AOpCodeBImm + class OpCodeBImmTest : OpCodeBImm { public int Rt { get; private set; } public int Pos { get; private set; } - public AOpCodeBImmTest(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeBImmTest(Inst inst, long position, int opCode) : base(inst, position, opCode) { Rt = opCode & 0x1f; - Imm = position + ADecoderHelper.DecodeImmS14_2(opCode); + Imm = position + DecoderHelper.DecodeImmS14_2(opCode); Pos = (opCode >> 19) & 0x1f; Pos |= (opCode >> 26) & 0x20; diff --git a/ChocolArm64/Decoder/AOpCodeBReg.cs b/ChocolArm64/Decoder/OpCodeBReg.cs similarity index 68% rename from ChocolArm64/Decoder/AOpCodeBReg.cs rename to ChocolArm64/Decoder/OpCodeBReg.cs index b36ab8c71e..3bd2dfd2bd 100644 --- a/ChocolArm64/Decoder/AOpCodeBReg.cs +++ b/ChocolArm64/Decoder/OpCodeBReg.cs @@ -2,18 +2,18 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeBReg : AOpCode + class OpCodeBReg : AOpCode { public int Rn { get; private set; } - public AOpCodeBReg(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeBReg(Inst inst, long position, int opCode) : base(inst, position, opCode) { int op4 = (opCode >> 0) & 0x1f; int op2 = (opCode >> 16) & 0x1f; if (op2 != 0b11111 || op4 != 0b00000) { - Emitter = AInstEmit.Und; + Emitter = InstEmit.Und; return; } diff --git a/ChocolArm64/Decoder/AOpCodeBfm.cs b/ChocolArm64/Decoder/OpCodeBfm.cs similarity index 67% rename from ChocolArm64/Decoder/AOpCodeBfm.cs rename to ChocolArm64/Decoder/OpCodeBfm.cs index 188b9a05a0..e73bcdc28b 100644 --- a/ChocolArm64/Decoder/AOpCodeBfm.cs +++ b/ChocolArm64/Decoder/OpCodeBfm.cs @@ -2,20 +2,20 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeBfm : AOpCodeAlu + class OpCodeBfm : OpCodeAlu { public long WMask { get; private set; } public long TMask { get; private set; } public int Pos { get; private set; } public int Shift { get; private set; } - public AOpCodeBfm(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeBfm(Inst inst, long position, int opCode) : base(inst, position, opCode) { - var bm = ADecoderHelper.DecodeBitMask(opCode, false); + var bm = DecoderHelper.DecodeBitMask(opCode, false); if (bm.IsUndefined) { - Emitter = AInstEmit.Und; + Emitter = InstEmit.Und; return; } diff --git a/ChocolArm64/Decoder/AOpCodeCcmp.cs b/ChocolArm64/Decoder/OpCodeCcmp.cs similarity index 61% rename from ChocolArm64/Decoder/AOpCodeCcmp.cs rename to ChocolArm64/Decoder/OpCodeCcmp.cs index 61f5ca8917..e187e9856b 100644 --- a/ChocolArm64/Decoder/AOpCodeCcmp.cs +++ b/ChocolArm64/Decoder/OpCodeCcmp.cs @@ -3,26 +3,26 @@ using ChocolArm64.State; namespace ChocolArm64.Decoder { - class AOpCodeCcmp : AOpCodeAlu, IaOpCodeCond + class OpCodeCcmp : OpCodeAlu, IOpCodeCond { public int Nzcv { get; private set; } protected int RmImm; - public ACond Cond { get; private set; } + public Cond Cond { get; private set; } - public AOpCodeCcmp(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeCcmp(Inst inst, long position, int opCode) : base(inst, position, opCode) { int o3 = (opCode >> 4) & 1; if (o3 != 0) { - Emitter = AInstEmit.Und; + Emitter = InstEmit.Und; return; } Nzcv = (opCode >> 0) & 0xf; - Cond = (ACond)((opCode >> 12) & 0xf); + Cond = (Cond)((opCode >> 12) & 0xf); RmImm = (opCode >> 16) & 0x1f; Rd = AThreadState.ZrIndex; diff --git a/ChocolArm64/Decoder/OpCodeCcmpImm.cs b/ChocolArm64/Decoder/OpCodeCcmpImm.cs new file mode 100644 index 0000000000..3223953f93 --- /dev/null +++ b/ChocolArm64/Decoder/OpCodeCcmpImm.cs @@ -0,0 +1,11 @@ +using ChocolArm64.Instruction; + +namespace ChocolArm64.Decoder +{ + class OpCodeCcmpImm : OpCodeCcmp, IOpCodeAluImm + { + public long Imm => RmImm; + + public OpCodeCcmpImm(Inst inst, long position, int opCode) : base(inst, position, opCode) { } + } +} \ No newline at end of file diff --git a/ChocolArm64/Decoder/OpCodeCcmpReg.cs b/ChocolArm64/Decoder/OpCodeCcmpReg.cs new file mode 100644 index 0000000000..f99be6640d --- /dev/null +++ b/ChocolArm64/Decoder/OpCodeCcmpReg.cs @@ -0,0 +1,15 @@ +using ChocolArm64.Instruction; + +namespace ChocolArm64.Decoder +{ + class OpCodeCcmpReg : OpCodeCcmp, IOpCodeAluRs + { + public int Rm => RmImm; + + public int Shift => 0; + + public ShiftType ShiftType => ShiftType.Lsl; + + public OpCodeCcmpReg(Inst inst, long position, int opCode) : base(inst, position, opCode) { } + } +} \ No newline at end of file diff --git a/ChocolArm64/Decoder/OpCodeCsel.cs b/ChocolArm64/Decoder/OpCodeCsel.cs new file mode 100644 index 0000000000..36cf09d266 --- /dev/null +++ b/ChocolArm64/Decoder/OpCodeCsel.cs @@ -0,0 +1,17 @@ +using ChocolArm64.Instruction; + +namespace ChocolArm64.Decoder +{ + class OpCodeCsel : OpCodeAlu, IOpCodeCond + { + public int Rm { get; private set; } + + public Cond Cond { get; private set; } + + public OpCodeCsel(Inst inst, long position, int opCode) : base(inst, position, opCode) + { + Rm = (opCode >> 16) & 0x1f; + Cond = (Cond)((opCode >> 12) & 0xf); + } + } +} \ No newline at end of file diff --git a/ChocolArm64/Decoder/AOpCodeException.cs b/ChocolArm64/Decoder/OpCodeException.cs similarity index 56% rename from ChocolArm64/Decoder/AOpCodeException.cs rename to ChocolArm64/Decoder/OpCodeException.cs index 6600f8dc06..b55d2b5971 100644 --- a/ChocolArm64/Decoder/AOpCodeException.cs +++ b/ChocolArm64/Decoder/OpCodeException.cs @@ -2,11 +2,11 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeException : AOpCode + class OpCodeException : AOpCode { public int Id { get; private set; } - public AOpCodeException(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeException(Inst inst, long position, int opCode) : base(inst, position, opCode) { Id = (opCode >> 5) & 0xffff; } diff --git a/ChocolArm64/Decoder/AOpCodeMem.cs b/ChocolArm64/Decoder/OpCodeMem.cs similarity index 77% rename from ChocolArm64/Decoder/AOpCodeMem.cs rename to ChocolArm64/Decoder/OpCodeMem.cs index 4513985093..91f43c3de7 100644 --- a/ChocolArm64/Decoder/AOpCodeMem.cs +++ b/ChocolArm64/Decoder/OpCodeMem.cs @@ -2,14 +2,14 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeMem : AOpCode + class OpCodeMem : AOpCode { public int Rt { get; protected set; } public int Rn { get; protected set; } public int Size { get; protected set; } public bool Extend64 { get; protected set; } - public AOpCodeMem(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeMem(Inst inst, long position, int opCode) : base(inst, position, opCode) { Rt = (opCode >> 0) & 0x1f; Rn = (opCode >> 5) & 0x1f; diff --git a/ChocolArm64/Decoder/AOpCodeMemEx.cs b/ChocolArm64/Decoder/OpCodeMemEx.cs similarity index 66% rename from ChocolArm64/Decoder/AOpCodeMemEx.cs rename to ChocolArm64/Decoder/OpCodeMemEx.cs index fe25da0111..52a6a023d3 100644 --- a/ChocolArm64/Decoder/AOpCodeMemEx.cs +++ b/ChocolArm64/Decoder/OpCodeMemEx.cs @@ -2,12 +2,12 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeMemEx : AOpCodeMem + class OpCodeMemEx : OpCodeMem { public int Rt2 { get; private set; } public int Rs { get; private set; } - public AOpCodeMemEx(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeMemEx(Inst inst, long position, int opCode) : base(inst, position, opCode) { Rt2 = (opCode >> 10) & 0x1f; Rs = (opCode >> 16) & 0x1f; diff --git a/ChocolArm64/Decoder/AOpCodeMemImm.cs b/ChocolArm64/Decoder/OpCodeMemImm.cs similarity index 91% rename from ChocolArm64/Decoder/AOpCodeMemImm.cs rename to ChocolArm64/Decoder/OpCodeMemImm.cs index e86adfddb5..a3e65a367d 100644 --- a/ChocolArm64/Decoder/AOpCodeMemImm.cs +++ b/ChocolArm64/Decoder/OpCodeMemImm.cs @@ -2,7 +2,7 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeMemImm : AOpCodeMem + class OpCodeMemImm : OpCodeMem { public long Imm { get; protected set; } public bool WBack { get; protected set; } @@ -18,7 +18,7 @@ namespace ChocolArm64.Decoder Unsigned } - public AOpCodeMemImm(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeMemImm(Inst inst, long position, int opCode) : base(inst, position, opCode) { Extend64 = ((opCode >> 22) & 3) == 2; WBack = ((opCode >> 24) & 1) == 0; diff --git a/ChocolArm64/Decoder/AOpCodeMemLit.cs b/ChocolArm64/Decoder/OpCodeMemLit.cs similarity index 77% rename from ChocolArm64/Decoder/AOpCodeMemLit.cs rename to ChocolArm64/Decoder/OpCodeMemLit.cs index 1d33b89427..650b7cfeda 100644 --- a/ChocolArm64/Decoder/AOpCodeMemLit.cs +++ b/ChocolArm64/Decoder/OpCodeMemLit.cs @@ -2,7 +2,7 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeMemLit : AOpCode, IaOpCodeLit + class OpCodeMemLit : AOpCode, IOpCodeLit { public int Rt { get; private set; } public long Imm { get; private set; } @@ -10,11 +10,11 @@ namespace ChocolArm64.Decoder public bool Signed { get; private set; } public bool Prefetch { get; private set; } - public AOpCodeMemLit(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeMemLit(Inst inst, long position, int opCode) : base(inst, position, opCode) { Rt = opCode & 0x1f; - Imm = position + ADecoderHelper.DecodeImmS19_2(opCode); + Imm = position + DecoderHelper.DecodeImmS19_2(opCode); switch ((opCode >> 30) & 3) { diff --git a/ChocolArm64/Decoder/AOpCodeMemPair.cs b/ChocolArm64/Decoder/OpCodeMemPair.cs similarity index 79% rename from ChocolArm64/Decoder/AOpCodeMemPair.cs rename to ChocolArm64/Decoder/OpCodeMemPair.cs index 394fdadf5a..209c9502c8 100644 --- a/ChocolArm64/Decoder/AOpCodeMemPair.cs +++ b/ChocolArm64/Decoder/OpCodeMemPair.cs @@ -2,11 +2,11 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeMemPair : AOpCodeMemImm + class OpCodeMemPair : OpCodeMemImm { public int Rt2 { get; private set; } - public AOpCodeMemPair(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeMemPair(Inst inst, long position, int opCode) : base(inst, position, opCode) { Rt2 = (opCode >> 10) & 0x1f; WBack = ((opCode >> 23) & 0x1) != 0; diff --git a/ChocolArm64/Decoder/AOpCodeMemReg.cs b/ChocolArm64/Decoder/OpCodeMemReg.cs similarity index 60% rename from ChocolArm64/Decoder/AOpCodeMemReg.cs rename to ChocolArm64/Decoder/OpCodeMemReg.cs index afabd1acb1..815664fd75 100644 --- a/ChocolArm64/Decoder/AOpCodeMemReg.cs +++ b/ChocolArm64/Decoder/OpCodeMemReg.cs @@ -2,17 +2,17 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeMemReg : AOpCodeMem + class OpCodeMemReg : OpCodeMem { public bool Shift { get; private set; } public int Rm { get; private set; } - public AIntType IntType { get; private set; } + public IntType IntType { get; private set; } - public AOpCodeMemReg(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeMemReg(Inst inst, long position, int opCode) : base(inst, position, opCode) { Shift = ((opCode >> 12) & 0x1) != 0; - IntType = (AIntType)((opCode >> 13) & 0x7); + IntType = (IntType)((opCode >> 13) & 0x7); Rm = (opCode >> 16) & 0x1f; Extend64 = ((opCode >> 22) & 0x3) == 2; } diff --git a/ChocolArm64/Decoder/AOpCodeMov.cs b/ChocolArm64/Decoder/OpCodeMov.cs similarity index 72% rename from ChocolArm64/Decoder/AOpCodeMov.cs rename to ChocolArm64/Decoder/OpCodeMov.cs index 50e1d77071..b45933b17d 100644 --- a/ChocolArm64/Decoder/AOpCodeMov.cs +++ b/ChocolArm64/Decoder/OpCodeMov.cs @@ -3,20 +3,20 @@ using ChocolArm64.State; namespace ChocolArm64.Decoder { - class AOpCodeMov : AOpCode + class OpCodeMov : AOpCode { public int Rd { get; private set; } public long Imm { get; private set; } public int Pos { get; private set; } - public AOpCodeMov(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeMov(Inst inst, long position, int opCode) : base(inst, position, opCode) { int p1 = (opCode >> 22) & 1; int sf = (opCode >> 31) & 1; if (sf == 0 && p1 != 0) { - Emitter = AInstEmit.Und; + Emitter = InstEmit.Und; return; } @@ -29,8 +29,8 @@ namespace ChocolArm64.Decoder Imm <<= Pos; RegisterSize = (opCode >> 31) != 0 - ? ARegisterSize.Int64 - : ARegisterSize.Int32; + ? State.RegisterSize.Int64 + : State.RegisterSize.Int32; } } } \ No newline at end of file diff --git a/ChocolArm64/Decoder/AOpCodeMul.cs b/ChocolArm64/Decoder/OpCodeMul.cs similarity index 67% rename from ChocolArm64/Decoder/AOpCodeMul.cs rename to ChocolArm64/Decoder/OpCodeMul.cs index c154f5e71c..d49be2bfde 100644 --- a/ChocolArm64/Decoder/AOpCodeMul.cs +++ b/ChocolArm64/Decoder/OpCodeMul.cs @@ -2,12 +2,12 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeMul : AOpCodeAlu + class OpCodeMul : OpCodeAlu { public int Rm { get; private set; } public int Ra { get; private set; } - public AOpCodeMul(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeMul(Inst inst, long position, int opCode) : base(inst, position, opCode) { Ra = (opCode >> 10) & 0x1f; Rm = (opCode >> 16) & 0x1f; diff --git a/ChocolArm64/Decoder/AOpCodeSimd.cs b/ChocolArm64/Decoder/OpCodeSimd.cs similarity index 70% rename from ChocolArm64/Decoder/AOpCodeSimd.cs rename to ChocolArm64/Decoder/OpCodeSimd.cs index eaf1e011ee..b8c0cd807c 100644 --- a/ChocolArm64/Decoder/AOpCodeSimd.cs +++ b/ChocolArm64/Decoder/OpCodeSimd.cs @@ -3,14 +3,14 @@ using ChocolArm64.State; namespace ChocolArm64.Decoder { - class AOpCodeSimd : AOpCode, IaOpCodeSimd + class OpCodeSimd : AOpCode, IOpCodeSimd { public int Rd { get; private set; } public int Rn { get; private set; } public int Opc { get; private set; } public int Size { get; protected set; } - public AOpCodeSimd(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeSimd(Inst inst, long position, int opCode) : base(inst, position, opCode) { Rd = (opCode >> 0) & 0x1f; Rn = (opCode >> 5) & 0x1f; @@ -18,8 +18,8 @@ namespace ChocolArm64.Decoder Size = (opCode >> 22) & 0x3; RegisterSize = ((opCode >> 30) & 1) != 0 - ? ARegisterSize.Simd128 - : ARegisterSize.Simd64; + ? RegisterSize.Simd128 + : RegisterSize.Simd64; } } } \ No newline at end of file diff --git a/ChocolArm64/Decoder/AOpCodeSimdCvt.cs b/ChocolArm64/Decoder/OpCodeSimdCvt.cs similarity index 71% rename from ChocolArm64/Decoder/AOpCodeSimdCvt.cs rename to ChocolArm64/Decoder/OpCodeSimdCvt.cs index 650b742f1a..98a70deca6 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdCvt.cs +++ b/ChocolArm64/Decoder/OpCodeSimdCvt.cs @@ -3,11 +3,11 @@ using ChocolArm64.State; namespace ChocolArm64.Decoder { - class AOpCodeSimdCvt : AOpCodeSimd + class OpCodeSimdCvt : OpCodeSimd { public int FBits { get; private set; } - public AOpCodeSimdCvt(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeSimdCvt(Inst inst, long position, int opCode) : base(inst, position, opCode) { //TODO: //Und of Fixed Point variants. @@ -24,8 +24,8 @@ namespace ChocolArm64.Decoder FBits = 64 - scale; RegisterSize = sf != 0 - ? ARegisterSize.Int64 - : ARegisterSize.Int32; + ? State.RegisterSize.Int64 + : State.RegisterSize.Int32; } } } \ No newline at end of file diff --git a/ChocolArm64/Decoder/AOpCodeSimdExt.cs b/ChocolArm64/Decoder/OpCodeSimdExt.cs similarity index 56% rename from ChocolArm64/Decoder/AOpCodeSimdExt.cs rename to ChocolArm64/Decoder/OpCodeSimdExt.cs index a980f21b04..861168d1a9 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdExt.cs +++ b/ChocolArm64/Decoder/OpCodeSimdExt.cs @@ -2,11 +2,11 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeSimdExt : AOpCodeSimdReg + class OpCodeSimdExt : OpCodeSimdReg { public int Imm4 { get; private set; } - public AOpCodeSimdExt(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeSimdExt(Inst inst, long position, int opCode) : base(inst, position, opCode) { Imm4 = (opCode >> 11) & 0xf; } diff --git a/ChocolArm64/Decoder/OpCodeSimdFcond.cs b/ChocolArm64/Decoder/OpCodeSimdFcond.cs new file mode 100644 index 0000000000..319c5553bd --- /dev/null +++ b/ChocolArm64/Decoder/OpCodeSimdFcond.cs @@ -0,0 +1,17 @@ +using ChocolArm64.Instruction; + +namespace ChocolArm64.Decoder +{ + class OpCodeSimdFcond : OpCodeSimdReg, IOpCodeCond + { + public int Nzcv { get; private set; } + + public Cond Cond { get; private set; } + + public OpCodeSimdFcond(Inst inst, long position, int opCode) : base(inst, position, opCode) + { + Nzcv = (opCode >> 0) & 0xf; + Cond = (Cond)((opCode >> 12) & 0xf); + } + } +} \ No newline at end of file diff --git a/ChocolArm64/Decoder/AOpCodeSimdFmov.cs b/ChocolArm64/Decoder/OpCodeSimdFmov.cs similarity index 68% rename from ChocolArm64/Decoder/AOpCodeSimdFmov.cs rename to ChocolArm64/Decoder/OpCodeSimdFmov.cs index 762985913b..64847c6b91 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdFmov.cs +++ b/ChocolArm64/Decoder/OpCodeSimdFmov.cs @@ -2,20 +2,20 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeSimdFmov : AOpCode, IaOpCodeSimd + class OpCodeSimdFmov : AOpCode, IOpCodeSimd { public int Rd { get; private set; } public long Imm { get; private set; } public int Size { get; private set; } - public AOpCodeSimdFmov(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeSimdFmov(Inst inst, long position, int opCode) : base(inst, position, opCode) { int imm5 = (opCode >> 5) & 0x1f; int type = (opCode >> 22) & 0x3; if (imm5 != 0b00000 || type > 1) { - Emitter = AInstEmit.Und; + Emitter = InstEmit.Und; return; } @@ -27,7 +27,7 @@ namespace ChocolArm64.Decoder Rd = (opCode >> 0) & 0x1f; imm = (opCode >> 13) & 0xff; - Imm = ADecoderHelper.DecodeImm8Float(imm, type); + Imm = DecoderHelper.DecodeImm8Float(imm, type); } } } \ No newline at end of file diff --git a/ChocolArm64/Decoder/AOpCodeSimdImm.cs b/ChocolArm64/Decoder/OpCodeSimdImm.cs similarity index 90% rename from ChocolArm64/Decoder/AOpCodeSimdImm.cs rename to ChocolArm64/Decoder/OpCodeSimdImm.cs index bc8504c80b..3f8ab62c7e 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdImm.cs +++ b/ChocolArm64/Decoder/OpCodeSimdImm.cs @@ -3,13 +3,13 @@ using ChocolArm64.State; namespace ChocolArm64.Decoder { - class AOpCodeSimdImm : AOpCode, IaOpCodeSimd + class OpCodeSimdImm : AOpCode, IOpCodeSimd { public int Rd { get; private set; } public long Imm { get; private set; } public int Size { get; private set; } - public AOpCodeSimdImm(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeSimdImm(Inst inst, long position, int opCode) : base(inst, position, opCode) { Rd = opCode & 0x1f; @@ -54,7 +54,7 @@ namespace ChocolArm64.Decoder case 2: case 3: //Floating point Immediate. - imm = ADecoderHelper.DecodeImm8Float(imm, Size); + imm = DecoderHelper.DecodeImm8Float(imm, Size); break; } } @@ -82,8 +82,8 @@ namespace ChocolArm64.Decoder Imm = imm; RegisterSize = ((opCode >> 30) & 1) != 0 - ? ARegisterSize.Simd128 - : ARegisterSize.Simd64; + ? State.RegisterSize.Simd128 + : State.RegisterSize.Simd64; } private static long ShlOnes(long value, int shift) diff --git a/ChocolArm64/Decoder/AOpCodeSimdIns.cs b/ChocolArm64/Decoder/OpCodeSimdIns.cs similarity index 79% rename from ChocolArm64/Decoder/AOpCodeSimdIns.cs rename to ChocolArm64/Decoder/OpCodeSimdIns.cs index c1070a4a5e..1f9e719278 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdIns.cs +++ b/ChocolArm64/Decoder/OpCodeSimdIns.cs @@ -2,19 +2,19 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeSimdIns : AOpCodeSimd + class OpCodeSimdIns : OpCodeSimd { public int SrcIndex { get; private set; } public int DstIndex { get; private set; } - public AOpCodeSimdIns(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeSimdIns(Inst inst, long position, int opCode) : base(inst, position, opCode) { int imm4 = (opCode >> 11) & 0xf; int imm5 = (opCode >> 16) & 0x1f; if (imm5 == 0b10000) { - Emitter = AInstEmit.Und; + Emitter = InstEmit.Und; return; } diff --git a/ChocolArm64/Decoder/AOpCodeSimdMemImm.cs b/ChocolArm64/Decoder/OpCodeSimdMemImm.cs similarity index 62% rename from ChocolArm64/Decoder/AOpCodeSimdMemImm.cs rename to ChocolArm64/Decoder/OpCodeSimdMemImm.cs index f24256fd15..624f588040 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdMemImm.cs +++ b/ChocolArm64/Decoder/OpCodeSimdMemImm.cs @@ -2,9 +2,9 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeSimdMemImm : AOpCodeMemImm, IaOpCodeSimd + class OpCodeSimdMemImm : OpCodeMemImm, IOpCodeSimd { - public AOpCodeSimdMemImm(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeSimdMemImm(Inst inst, long position, int opCode) : base(inst, position, opCode) { Size |= (opCode >> 21) & 4; diff --git a/ChocolArm64/Decoder/AOpCodeSimdMemLit.cs b/ChocolArm64/Decoder/OpCodeSimdMemLit.cs similarity index 64% rename from ChocolArm64/Decoder/AOpCodeSimdMemLit.cs rename to ChocolArm64/Decoder/OpCodeSimdMemLit.cs index 2d4d0d2b4e..e76b7101f7 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdMemLit.cs +++ b/ChocolArm64/Decoder/OpCodeSimdMemLit.cs @@ -2,7 +2,7 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeSimdMemLit : AOpCode, IaOpCodeSimd, IaOpCodeLit + class OpCodeSimdMemLit : AOpCode, IOpCodeSimd, IOpCodeLit { public int Rt { get; private set; } public long Imm { get; private set; } @@ -10,20 +10,20 @@ namespace ChocolArm64.Decoder public bool Signed => false; public bool Prefetch => false; - public AOpCodeSimdMemLit(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeSimdMemLit(Inst inst, long position, int opCode) : base(inst, position, opCode) { int opc = (opCode >> 30) & 3; if (opc == 3) { - Emitter = AInstEmit.Und; + Emitter = InstEmit.Und; return; } Rt = opCode & 0x1f; - Imm = position + ADecoderHelper.DecodeImmS19_2(opCode); + Imm = position + DecoderHelper.DecodeImmS19_2(opCode); Size = opc + 2; } diff --git a/ChocolArm64/Decoder/AOpCodeSimdMemMs.cs b/ChocolArm64/Decoder/OpCodeSimdMemMs.cs similarity index 77% rename from ChocolArm64/Decoder/AOpCodeSimdMemMs.cs rename to ChocolArm64/Decoder/OpCodeSimdMemMs.cs index d9b48a31e5..02c8d62c88 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdMemMs.cs +++ b/ChocolArm64/Decoder/OpCodeSimdMemMs.cs @@ -3,14 +3,14 @@ using ChocolArm64.State; namespace ChocolArm64.Decoder { - class AOpCodeSimdMemMs : AOpCodeMemReg, IaOpCodeSimd + class OpCodeSimdMemMs : OpCodeMemReg, IOpCodeSimd { public int Reps { get; private set; } public int SElems { get; private set; } public int Elems { get; private set; } public bool WBack { get; private set; } - public AOpCodeSimdMemMs(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeSimdMemMs(Inst inst, long position, int opCode) : base(inst, position, opCode) { switch ((opCode >> 12) & 0xf) { @@ -22,7 +22,7 @@ namespace ChocolArm64.Decoder case 0b1000: Reps = 1; SElems = 2; break; case 0b1010: Reps = 2; SElems = 1; break; - default: inst = AInst.Undefined; return; + default: inst = Inst.Undefined; return; } Size = (opCode >> 10) & 3; @@ -32,7 +32,7 @@ namespace ChocolArm64.Decoder if (!q && Size == 3 && SElems != 1) { - inst = AInst.Undefined; + inst = Inst.Undefined; return; } @@ -40,8 +40,8 @@ namespace ChocolArm64.Decoder Extend64 = false; RegisterSize = q - ? ARegisterSize.Simd128 - : ARegisterSize.Simd64; + ? State.RegisterSize.Simd128 + : State.RegisterSize.Simd64; Elems = (GetBitsCount() >> 3) >> Size; } diff --git a/ChocolArm64/Decoder/AOpCodeSimdMemPair.cs b/ChocolArm64/Decoder/OpCodeSimdMemPair.cs similarity index 55% rename from ChocolArm64/Decoder/AOpCodeSimdMemPair.cs rename to ChocolArm64/Decoder/OpCodeSimdMemPair.cs index 6043ca9528..94f0869c2f 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdMemPair.cs +++ b/ChocolArm64/Decoder/OpCodeSimdMemPair.cs @@ -2,9 +2,9 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeSimdMemPair : AOpCodeMemPair, IaOpCodeSimd + class OpCodeSimdMemPair : OpCodeMemPair, IOpCodeSimd { - public AOpCodeSimdMemPair(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeSimdMemPair(Inst inst, long position, int opCode) : base(inst, position, opCode) { Size = ((opCode >> 30) & 3) + 2; diff --git a/ChocolArm64/Decoder/AOpCodeSimdMemReg.cs b/ChocolArm64/Decoder/OpCodeSimdMemReg.cs similarity index 51% rename from ChocolArm64/Decoder/AOpCodeSimdMemReg.cs rename to ChocolArm64/Decoder/OpCodeSimdMemReg.cs index c1517098bb..70fca565fd 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdMemReg.cs +++ b/ChocolArm64/Decoder/OpCodeSimdMemReg.cs @@ -2,9 +2,9 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeSimdMemReg : AOpCodeMemReg, IaOpCodeSimd + class OpCodeSimdMemReg : OpCodeMemReg, IOpCodeSimd { - public AOpCodeSimdMemReg(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeSimdMemReg(Inst inst, long position, int opCode) : base(inst, position, opCode) { Size |= (opCode >> 21) & 4; diff --git a/ChocolArm64/Decoder/AOpCodeSimdMemSs.cs b/ChocolArm64/Decoder/OpCodeSimdMemSs.cs similarity index 84% rename from ChocolArm64/Decoder/AOpCodeSimdMemSs.cs rename to ChocolArm64/Decoder/OpCodeSimdMemSs.cs index f536d2da1e..7c95ef33cc 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdMemSs.cs +++ b/ChocolArm64/Decoder/OpCodeSimdMemSs.cs @@ -3,14 +3,14 @@ using ChocolArm64.State; namespace ChocolArm64.Decoder { - class AOpCodeSimdMemSs : AOpCodeMemReg, IaOpCodeSimd + class OpCodeSimdMemSs : OpCodeMemReg, IOpCodeSimd { public int SElems { get; private set; } public int Index { get; private set; } public bool Replicate { get; private set; } public bool WBack { get; private set; } - public AOpCodeSimdMemSs(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeSimdMemSs(Inst inst, long position, int opCode) : base(inst, position, opCode) { int size = (opCode >> 10) & 3; int s = (opCode >> 12) & 1; @@ -31,7 +31,7 @@ namespace ChocolArm64.Decoder { if ((size & 1) != 0) { - inst = AInst.Undefined; + inst = Inst.Undefined; return; } @@ -46,7 +46,7 @@ namespace ChocolArm64.Decoder if ((size & 2) != 0 || ((size & 1) != 0 && s != 0)) { - inst = AInst.Undefined; + inst = Inst.Undefined; return; } @@ -69,7 +69,7 @@ namespace ChocolArm64.Decoder { if (l == 0 || s != 0) { - inst = AInst.Undefined; + inst = Inst.Undefined; return; } @@ -91,8 +91,8 @@ namespace ChocolArm64.Decoder WBack = ((opCode >> 23) & 1) != 0; RegisterSize = q != 0 - ? ARegisterSize.Simd128 - : ARegisterSize.Simd64; + ? State.RegisterSize.Simd128 + : State.RegisterSize.Simd64; } } } \ No newline at end of file diff --git a/ChocolArm64/Decoder/AOpCodeSimdReg.cs b/ChocolArm64/Decoder/OpCodeSimdReg.cs similarity index 73% rename from ChocolArm64/Decoder/AOpCodeSimdReg.cs rename to ChocolArm64/Decoder/OpCodeSimdReg.cs index 44d5863c4f..84401b93f8 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdReg.cs +++ b/ChocolArm64/Decoder/OpCodeSimdReg.cs @@ -2,13 +2,13 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeSimdReg : AOpCodeSimd + class OpCodeSimdReg : OpCodeSimd { public bool Bit3 { get; private set; } public int Ra { get; private set; } public int Rm { get; protected set; } - public AOpCodeSimdReg(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeSimdReg(Inst inst, long position, int opCode) : base(inst, position, opCode) { Bit3 = ((opCode >> 3) & 0x1) != 0; Ra = (opCode >> 10) & 0x1f; diff --git a/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs b/ChocolArm64/Decoder/OpCodeSimdRegElem.cs similarity index 71% rename from ChocolArm64/Decoder/AOpCodeSimdRegElem.cs rename to ChocolArm64/Decoder/OpCodeSimdRegElem.cs index f4c5608940..5aad359dd1 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdRegElem.cs +++ b/ChocolArm64/Decoder/OpCodeSimdRegElem.cs @@ -2,11 +2,11 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeSimdRegElem : AOpCodeSimdReg + class OpCodeSimdRegElem : OpCodeSimdReg { public int Index { get; private set; } - public AOpCodeSimdRegElem(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeSimdRegElem(Inst inst, long position, int opCode) : base(inst, position, opCode) { switch (Size) { @@ -24,7 +24,7 @@ namespace ChocolArm64.Decoder break; - default: Emitter = AInstEmit.Und; return; + default: Emitter = InstEmit.Und; return; } } } diff --git a/ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs b/ChocolArm64/Decoder/OpCodeSimdRegElemF.cs similarity index 73% rename from ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs rename to ChocolArm64/Decoder/OpCodeSimdRegElemF.cs index 7db0b1f492..b1c6fbc49e 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdRegElemF.cs +++ b/ChocolArm64/Decoder/OpCodeSimdRegElemF.cs @@ -2,11 +2,11 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeSimdRegElemF : AOpCodeSimdReg + class OpCodeSimdRegElemF : OpCodeSimdReg { public int Index { get; private set; } - public AOpCodeSimdRegElemF(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeSimdRegElemF(Inst inst, long position, int opCode) : base(inst, position, opCode) { switch ((opCode >> 21) & 3) // sz:L { @@ -26,7 +26,7 @@ namespace ChocolArm64.Decoder break; - default: Emitter = AInstEmit.Und; return; + default: Emitter = InstEmit.Und; return; } } } diff --git a/ChocolArm64/Decoder/OpCodeSimdShImm.cs b/ChocolArm64/Decoder/OpCodeSimdShImm.cs new file mode 100644 index 0000000000..a0c2160f65 --- /dev/null +++ b/ChocolArm64/Decoder/OpCodeSimdShImm.cs @@ -0,0 +1,16 @@ +using ChocolArm64.Instruction; + +namespace ChocolArm64.Decoder +{ + class OpCodeSimdShImm : OpCodeSimd + { + public int Imm { get; private set; } + + public OpCodeSimdShImm(Inst inst, long position, int opCode) : base(inst, position, opCode) + { + Imm = (opCode >> 16) & 0x7f; + + Size = BitUtils.HighestBitSetNibble(Imm >> 3); + } + } +} diff --git a/ChocolArm64/Decoder/AOpCodeSimdTbl.cs b/ChocolArm64/Decoder/OpCodeSimdTbl.cs similarity index 50% rename from ChocolArm64/Decoder/AOpCodeSimdTbl.cs rename to ChocolArm64/Decoder/OpCodeSimdTbl.cs index e74bd439cc..604be22e7b 100644 --- a/ChocolArm64/Decoder/AOpCodeSimdTbl.cs +++ b/ChocolArm64/Decoder/OpCodeSimdTbl.cs @@ -2,9 +2,9 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeSimdTbl : AOpCodeSimdReg + class OpCodeSimdTbl : OpCodeSimdReg { - public AOpCodeSimdTbl(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeSimdTbl(Inst inst, long position, int opCode) : base(inst, position, opCode) { Size = ((opCode >> 13) & 3) + 1; } diff --git a/ChocolArm64/Decoder/AOpCodeSystem.cs b/ChocolArm64/Decoder/OpCodeSystem.cs similarity index 82% rename from ChocolArm64/Decoder/AOpCodeSystem.cs rename to ChocolArm64/Decoder/OpCodeSystem.cs index 89c4e38fa6..aca16026e6 100644 --- a/ChocolArm64/Decoder/AOpCodeSystem.cs +++ b/ChocolArm64/Decoder/OpCodeSystem.cs @@ -2,7 +2,7 @@ using ChocolArm64.Instruction; namespace ChocolArm64.Decoder { - class AOpCodeSystem : AOpCode + class OpCodeSystem : AOpCode { public int Rt { get; private set; } public int Op2 { get; private set; } @@ -11,7 +11,7 @@ namespace ChocolArm64.Decoder public int Op1 { get; private set; } public int Op0 { get; private set; } - public AOpCodeSystem(AInst inst, long position, int opCode) : base(inst, position, opCode) + public OpCodeSystem(Inst inst, long position, int opCode) : base(inst, position, opCode) { Rt = (opCode >> 0) & 0x1f; Op2 = (opCode >> 5) & 0x7; diff --git a/ChocolArm64/Decoder/AShiftType.cs b/ChocolArm64/Decoder/ShiftType.cs similarity index 82% rename from ChocolArm64/Decoder/AShiftType.cs rename to ChocolArm64/Decoder/ShiftType.cs index 34ceea2087..0fd8631b19 100644 --- a/ChocolArm64/Decoder/AShiftType.cs +++ b/ChocolArm64/Decoder/ShiftType.cs @@ -1,6 +1,6 @@ namespace ChocolArm64.Decoder { - enum AShiftType + enum ShiftType { Lsl, Lsr, diff --git a/ChocolArm64/Decoder32/A32OpCode.cs b/ChocolArm64/Decoder32/A32OpCode.cs index a8a09adff0..aa92f45b80 100644 --- a/ChocolArm64/Decoder32/A32OpCode.cs +++ b/ChocolArm64/Decoder32/A32OpCode.cs @@ -5,11 +5,11 @@ namespace ChocolArm64.Decoder32 { class A32OpCode : AOpCode { - public ACond Cond { get; private set; } + public Cond Cond { get; private set; } - public A32OpCode(AInst inst, long position, int opCode) : base(inst, position, opCode) + public A32OpCode(Inst inst, long position, int opCode) : base(inst, position, opCode) { - Cond = (ACond)((uint)opCode >> 28); + Cond = (Cond)((uint)opCode >> 28); } } } \ No newline at end of file diff --git a/ChocolArm64/Decoder32/A32OpCodeBImmAl.cs b/ChocolArm64/Decoder32/A32OpCodeBImmAl.cs index 918d8d2493..8ff81e0c90 100644 --- a/ChocolArm64/Decoder32/A32OpCodeBImmAl.cs +++ b/ChocolArm64/Decoder32/A32OpCodeBImmAl.cs @@ -7,7 +7,7 @@ namespace ChocolArm64.Decoder32 public int Imm; public int H; - public A32OpCodeBImmAl(AInst inst, long position, int opCode) : base(inst, position, opCode) + public A32OpCodeBImmAl(Inst inst, long position, int opCode) : base(inst, position, opCode) { Imm = (opCode << 8) >> 6; H = (opCode >> 23) & 2; diff --git a/ChocolArm64/Events/ACpuTraceEventArgs.cs b/ChocolArm64/Events/CpuTraceEventArgs.cs similarity index 62% rename from ChocolArm64/Events/ACpuTraceEventArgs.cs rename to ChocolArm64/Events/CpuTraceEventArgs.cs index e3e27fbc38..c12781ed86 100644 --- a/ChocolArm64/Events/ACpuTraceEventArgs.cs +++ b/ChocolArm64/Events/CpuTraceEventArgs.cs @@ -2,11 +2,11 @@ using System; namespace ChocolArm64.Events { - public class ACpuTraceEventArgs : EventArgs + public class CpuTraceEventArgs : EventArgs { public long Position { get; private set; } - public ACpuTraceEventArgs(long position) + public CpuTraceEventArgs(long position) { Position = position; } diff --git a/ChocolArm64/Events/AInstExceptionEventArgs.cs b/ChocolArm64/Events/InstExceptionEventArgs.cs similarity index 67% rename from ChocolArm64/Events/AInstExceptionEventArgs.cs rename to ChocolArm64/Events/InstExceptionEventArgs.cs index e49e0d4494..e3cc0ba0e0 100644 --- a/ChocolArm64/Events/AInstExceptionEventArgs.cs +++ b/ChocolArm64/Events/InstExceptionEventArgs.cs @@ -2,12 +2,12 @@ using System; namespace ChocolArm64.Events { - public class AInstExceptionEventArgs : EventArgs + public class InstExceptionEventArgs : EventArgs { public long Position { get; private set; } public int Id { get; private set; } - public AInstExceptionEventArgs(long position, int id) + public InstExceptionEventArgs(long position, int id) { Position = position; Id = id; diff --git a/ChocolArm64/Events/AInstUndefinedEventArgs.cs b/ChocolArm64/Events/InstUndefinedEventArgs.cs similarity index 67% rename from ChocolArm64/Events/AInstUndefinedEventArgs.cs rename to ChocolArm64/Events/InstUndefinedEventArgs.cs index 17e345beff..3ad7ea8b9e 100644 --- a/ChocolArm64/Events/AInstUndefinedEventArgs.cs +++ b/ChocolArm64/Events/InstUndefinedEventArgs.cs @@ -2,12 +2,12 @@ using System; namespace ChocolArm64.Events { - public class AInstUndefinedEventArgs : EventArgs + public class InstUndefinedEventArgs : EventArgs { public long Position { get; private set; } public int RawOpCode { get; private set; } - public AInstUndefinedEventArgs(long position, int rawOpCode) + public InstUndefinedEventArgs(long position, int rawOpCode) { Position = position; RawOpCode = rawOpCode; diff --git a/ChocolArm64/Events/AInvalidAccessEventArgs.cs b/ChocolArm64/Events/InvalidAccessEventArgs.cs similarity index 60% rename from ChocolArm64/Events/AInvalidAccessEventArgs.cs rename to ChocolArm64/Events/InvalidAccessEventArgs.cs index f8da786d79..a8046d7375 100644 --- a/ChocolArm64/Events/AInvalidAccessEventArgs.cs +++ b/ChocolArm64/Events/InvalidAccessEventArgs.cs @@ -2,11 +2,11 @@ using System; namespace ChocolArm64.Events { - public class AInvalidAccessEventArgs : EventArgs + public class InvalidAccessEventArgs : EventArgs { public long Position { get; private set; } - public AInvalidAccessEventArgs(long position) + public InvalidAccessEventArgs(long position) { Position = position; } diff --git a/ChocolArm64/Instruction/AInst.cs b/ChocolArm64/Instruction/AInst.cs deleted file mode 100644 index 137ad09c49..0000000000 --- a/ChocolArm64/Instruction/AInst.cs +++ /dev/null @@ -1,20 +0,0 @@ -using System; - -namespace ChocolArm64.Instruction -{ - struct AInst - { - public AInstInterpreter Interpreter { get; private set; } - public AInstEmitter Emitter { get; private set; } - public Type Type { get; private set; } - - public static AInst Undefined => new AInst(null, AInstEmit.Und, null); - - public AInst(AInstInterpreter interpreter, AInstEmitter emitter, Type type) - { - Interpreter = interpreter; - Emitter = emitter; - Type = type; - } - } -} \ No newline at end of file diff --git a/ChocolArm64/Instruction/AInstEmitHash.cs b/ChocolArm64/Instruction/AInstEmitHash.cs deleted file mode 100644 index e3d545a1fa..0000000000 --- a/ChocolArm64/Instruction/AInstEmitHash.cs +++ /dev/null @@ -1,115 +0,0 @@ -using ChocolArm64.Decoder; -using ChocolArm64.State; -using ChocolArm64.Translation; -using System; -using System.Reflection.Emit; -using System.Runtime.Intrinsics.X86; - -namespace ChocolArm64.Instruction -{ - static partial class AInstEmit - { - public static void Crc32b(AilEmitterCtx context) - { - EmitCrc32(context, nameof(ASoftFallback.Crc32B)); - } - - public static void Crc32h(AilEmitterCtx context) - { - EmitCrc32(context, nameof(ASoftFallback.Crc32H)); - } - - public static void Crc32w(AilEmitterCtx context) - { - EmitCrc32(context, nameof(ASoftFallback.Crc32W)); - } - - public static void Crc32x(AilEmitterCtx context) - { - EmitCrc32(context, nameof(ASoftFallback.Crc32X)); - } - - public static void Crc32cb(AilEmitterCtx context) - { - if (AOptimizations.UseSse42) - { - EmitSse42Crc32(context, typeof(uint), typeof(byte)); - } - else - { - EmitCrc32(context, nameof(ASoftFallback.Crc32Cb)); - } - } - - public static void Crc32ch(AilEmitterCtx context) - { - if (AOptimizations.UseSse42) - { - EmitSse42Crc32(context, typeof(uint), typeof(ushort)); - } - else - { - EmitCrc32(context, nameof(ASoftFallback.Crc32Ch)); - } - } - - public static void Crc32cw(AilEmitterCtx context) - { - if (AOptimizations.UseSse42) - { - EmitSse42Crc32(context, typeof(uint), typeof(uint)); - } - else - { - EmitCrc32(context, nameof(ASoftFallback.Crc32Cw)); - } - } - - public static void Crc32cx(AilEmitterCtx context) - { - if (AOptimizations.UseSse42) - { - EmitSse42Crc32(context, typeof(ulong), typeof(ulong)); - } - else - { - EmitCrc32(context, nameof(ASoftFallback.Crc32Cx)); - } - } - - private static void EmitSse42Crc32(AilEmitterCtx context, Type tCrc, Type tData) - { - AOpCodeAluRs op = (AOpCodeAluRs)context.CurrOp; - - context.EmitLdintzr(op.Rn); - context.EmitLdintzr(op.Rm); - - context.EmitCall(typeof(Sse42).GetMethod(nameof(Sse42.Crc32), new Type[] { tCrc, tData })); - - context.EmitStintzr(op.Rd); - } - - private static void EmitCrc32(AilEmitterCtx context, string name) - { - AOpCodeAluRs op = (AOpCodeAluRs)context.CurrOp; - - context.EmitLdintzr(op.Rn); - - if (op.RegisterSize != ARegisterSize.Int32) - { - context.Emit(OpCodes.Conv_U4); - } - - context.EmitLdintzr(op.Rm); - - ASoftFallback.EmitCall(context, name); - - if (op.RegisterSize != ARegisterSize.Int32) - { - context.Emit(OpCodes.Conv_U8); - } - - context.EmitStintzr(op.Rd); - } - } -} diff --git a/ChocolArm64/Instruction/AInstEmitMul.cs b/ChocolArm64/Instruction/AInstEmitMul.cs deleted file mode 100644 index 004855c4dc..0000000000 --- a/ChocolArm64/Instruction/AInstEmitMul.cs +++ /dev/null @@ -1,80 +0,0 @@ -using ChocolArm64.Decoder; -using ChocolArm64.Translation; -using System.Reflection.Emit; - -namespace ChocolArm64.Instruction -{ - static partial class AInstEmit - { - public static void Madd(AilEmitterCtx context) => EmitMul(context, OpCodes.Add); - public static void Msub(AilEmitterCtx context) => EmitMul(context, OpCodes.Sub); - - private static void EmitMul(AilEmitterCtx context, OpCode ilOp) - { - AOpCodeMul op = (AOpCodeMul)context.CurrOp; - - context.EmitLdintzr(op.Ra); - context.EmitLdintzr(op.Rn); - context.EmitLdintzr(op.Rm); - - context.Emit(OpCodes.Mul); - context.Emit(ilOp); - - context.EmitStintzr(op.Rd); - } - - public static void Smaddl(AilEmitterCtx context) => EmitMull(context, OpCodes.Add, true); - public static void Smsubl(AilEmitterCtx context) => EmitMull(context, OpCodes.Sub, true); - public static void Umaddl(AilEmitterCtx context) => EmitMull(context, OpCodes.Add, false); - public static void Umsubl(AilEmitterCtx context) => EmitMull(context, OpCodes.Sub, false); - - private static void EmitMull(AilEmitterCtx context, OpCode addSubOp, bool signed) - { - AOpCodeMul op = (AOpCodeMul)context.CurrOp; - - OpCode castOp = signed - ? OpCodes.Conv_I8 - : OpCodes.Conv_U8; - - context.EmitLdintzr(op.Ra); - context.EmitLdintzr(op.Rn); - - context.Emit(OpCodes.Conv_I4); - context.Emit(castOp); - - context.EmitLdintzr(op.Rm); - - context.Emit(OpCodes.Conv_I4); - context.Emit(castOp); - context.Emit(OpCodes.Mul); - - context.Emit(addSubOp); - - context.EmitStintzr(op.Rd); - } - - public static void Smulh(AilEmitterCtx context) - { - AOpCodeMul op = (AOpCodeMul)context.CurrOp; - - context.EmitLdintzr(op.Rn); - context.EmitLdintzr(op.Rm); - - ASoftFallback.EmitCall(context, nameof(ASoftFallback.SMulHi128)); - - context.EmitStintzr(op.Rd); - } - - public static void Umulh(AilEmitterCtx context) - { - AOpCodeMul op = (AOpCodeMul)context.CurrOp; - - context.EmitLdintzr(op.Rn); - context.EmitLdintzr(op.Rm); - - ASoftFallback.EmitCall(context, nameof(ASoftFallback.UMulHi128)); - - context.EmitStintzr(op.Rd); - } - } -} \ No newline at end of file diff --git a/ChocolArm64/Instruction/AInstEmitSimdCrypto.cs b/ChocolArm64/Instruction/AInstEmitSimdCrypto.cs deleted file mode 100644 index 8cbfe1d0bc..0000000000 --- a/ChocolArm64/Instruction/AInstEmitSimdCrypto.cs +++ /dev/null @@ -1,54 +0,0 @@ -using ChocolArm64.Decoder; -using ChocolArm64.Translation; - -namespace ChocolArm64.Instruction -{ - static partial class AInstEmit - { - public static void Aesd_V(AilEmitterCtx context) - { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; - - context.EmitLdvec(op.Rd); - context.EmitLdvec(op.Rn); - - ASoftFallback.EmitCall(context, nameof(ASoftFallback.Decrypt)); - - context.EmitStvec(op.Rd); - } - - public static void Aese_V(AilEmitterCtx context) - { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; - - context.EmitLdvec(op.Rd); - context.EmitLdvec(op.Rn); - - ASoftFallback.EmitCall(context, nameof(ASoftFallback.Encrypt)); - - context.EmitStvec(op.Rd); - } - - public static void Aesimc_V(AilEmitterCtx context) - { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; - - context.EmitLdvec(op.Rn); - - ASoftFallback.EmitCall(context, nameof(ASoftFallback.InverseMixColumns)); - - context.EmitStvec(op.Rd); - } - - public static void Aesmc_V(AilEmitterCtx context) - { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; - - context.EmitLdvec(op.Rn); - - ASoftFallback.EmitCall(context, nameof(ASoftFallback.MixColumns)); - - context.EmitStvec(op.Rd); - } - } -} diff --git a/ChocolArm64/Instruction/AInstEmitSimdHash.cs b/ChocolArm64/Instruction/AInstEmitSimdHash.cs deleted file mode 100644 index 1d67e7ff4b..0000000000 --- a/ChocolArm64/Instruction/AInstEmitSimdHash.cs +++ /dev/null @@ -1,140 +0,0 @@ -using ChocolArm64.Decoder; -using ChocolArm64.Translation; - -using static ChocolArm64.Instruction.AInstEmitSimdHelper; - -namespace ChocolArm64.Instruction -{ - static partial class AInstEmit - { -#region "Sha1" - public static void Sha1c_V(AilEmitterCtx context) - { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; - - context.EmitLdvec(op.Rd); - EmitVectorExtractZx(context, op.Rn, 0, 2); - context.EmitLdvec(op.Rm); - - ASoftFallback.EmitCall(context, nameof(ASoftFallback.HashChoose)); - - context.EmitStvec(op.Rd); - } - - public static void Sha1h_V(AilEmitterCtx context) - { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; - - EmitVectorExtractZx(context, op.Rn, 0, 2); - - ASoftFallback.EmitCall(context, nameof(ASoftFallback.FixedRotate)); - - EmitScalarSet(context, op.Rd, 2); - } - - public static void Sha1m_V(AilEmitterCtx context) - { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; - - context.EmitLdvec(op.Rd); - EmitVectorExtractZx(context, op.Rn, 0, 2); - context.EmitLdvec(op.Rm); - - ASoftFallback.EmitCall(context, nameof(ASoftFallback.HashMajority)); - - context.EmitStvec(op.Rd); - } - - public static void Sha1p_V(AilEmitterCtx context) - { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; - - context.EmitLdvec(op.Rd); - EmitVectorExtractZx(context, op.Rn, 0, 2); - context.EmitLdvec(op.Rm); - - ASoftFallback.EmitCall(context, nameof(ASoftFallback.HashParity)); - - context.EmitStvec(op.Rd); - } - - public static void Sha1su0_V(AilEmitterCtx context) - { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; - - context.EmitLdvec(op.Rd); - context.EmitLdvec(op.Rn); - context.EmitLdvec(op.Rm); - - ASoftFallback.EmitCall(context, nameof(ASoftFallback.Sha1SchedulePart1)); - - context.EmitStvec(op.Rd); - } - - public static void Sha1su1_V(AilEmitterCtx context) - { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; - - context.EmitLdvec(op.Rd); - context.EmitLdvec(op.Rn); - - ASoftFallback.EmitCall(context, nameof(ASoftFallback.Sha1SchedulePart2)); - - context.EmitStvec(op.Rd); - } -#endregion - -#region "Sha256" - public static void Sha256h_V(AilEmitterCtx context) - { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; - - context.EmitLdvec(op.Rd); - context.EmitLdvec(op.Rn); - context.EmitLdvec(op.Rm); - - ASoftFallback.EmitCall(context, nameof(ASoftFallback.HashLower)); - - context.EmitStvec(op.Rd); - } - - public static void Sha256h2_V(AilEmitterCtx context) - { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; - - context.EmitLdvec(op.Rd); - context.EmitLdvec(op.Rn); - context.EmitLdvec(op.Rm); - - ASoftFallback.EmitCall(context, nameof(ASoftFallback.HashUpper)); - - context.EmitStvec(op.Rd); - } - - public static void Sha256su0_V(AilEmitterCtx context) - { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; - - context.EmitLdvec(op.Rd); - context.EmitLdvec(op.Rn); - - ASoftFallback.EmitCall(context, nameof(ASoftFallback.Sha256SchedulePart1)); - - context.EmitStvec(op.Rd); - } - - public static void Sha256su1_V(AilEmitterCtx context) - { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; - - context.EmitLdvec(op.Rd); - context.EmitLdvec(op.Rn); - context.EmitLdvec(op.Rm); - - ASoftFallback.EmitCall(context, nameof(ASoftFallback.Sha256SchedulePart2)); - - context.EmitStvec(op.Rd); - } -#endregion - } -} diff --git a/ChocolArm64/Instruction/ACryptoHelper.cs b/ChocolArm64/Instruction/CryptoHelper.cs similarity index 99% rename from ChocolArm64/Instruction/ACryptoHelper.cs rename to ChocolArm64/Instruction/CryptoHelper.cs index 27cc70aa04..f2604b7abe 100644 --- a/ChocolArm64/Instruction/ACryptoHelper.cs +++ b/ChocolArm64/Instruction/CryptoHelper.cs @@ -6,7 +6,7 @@ using System.Runtime.Intrinsics.X86; namespace ChocolArm64.Instruction { - static class ACryptoHelper + static class CryptoHelper { #region "LookUp Tables" private static byte[] _sBox = @@ -298,8 +298,8 @@ namespace ChocolArm64.Instruction private static void FromVectorToByteArray(byte[] state, ref Vector128 op) { - ulong uLongLow = AVectorHelper.VectorExtractIntZx((op), (byte)0, 3); - ulong uLongHigh = AVectorHelper.VectorExtractIntZx((op), (byte)1, 3); + ulong uLongLow = VectorHelper.VectorExtractIntZx((op), (byte)0, 3); + ulong uLongHigh = VectorHelper.VectorExtractIntZx((op), (byte)1, 3); for (int idx = 0; idx <= 7; idx++) { diff --git a/ChocolArm64/Instruction/Inst.cs b/ChocolArm64/Instruction/Inst.cs new file mode 100644 index 0000000000..7e67d791a4 --- /dev/null +++ b/ChocolArm64/Instruction/Inst.cs @@ -0,0 +1,20 @@ +using System; + +namespace ChocolArm64.Instruction +{ + struct Inst + { + public InstInterpreter Interpreter { get; private set; } + public InstEmitter Emitter { get; private set; } + public Type Type { get; private set; } + + public static Inst Undefined => new Inst(null, InstEmit.Und, null); + + public Inst(InstInterpreter interpreter, InstEmitter emitter, Type type) + { + Interpreter = interpreter; + Emitter = emitter; + Type = type; + } + } +} \ No newline at end of file diff --git a/ChocolArm64/Instruction/AInstEmitAlu.cs b/ChocolArm64/Instruction/InstEmitAlu.cs similarity index 58% rename from ChocolArm64/Instruction/AInstEmitAlu.cs rename to ChocolArm64/Instruction/InstEmitAlu.cs index 09755c8e71..24ff08132b 100644 --- a/ChocolArm64/Instruction/AInstEmitAlu.cs +++ b/ChocolArm64/Instruction/InstEmitAlu.cs @@ -6,22 +6,22 @@ using System.Reflection; using System.Reflection.Emit; using System.Runtime.Intrinsics.X86; -using static ChocolArm64.Instruction.AInstEmitAluHelper; +using static ChocolArm64.Instruction.InstEmitAluHelper; namespace ChocolArm64.Instruction { - static partial class AInstEmit + static partial class InstEmit { - public static void Adc(AilEmitterCtx context) => EmitAdc(context, false); - public static void Adcs(AilEmitterCtx context) => EmitAdc(context, true); + public static void Adc(ILEmitterCtx context) => EmitAdc(context, false); + public static void Adcs(ILEmitterCtx context) => EmitAdc(context, true); - private static void EmitAdc(AilEmitterCtx context, bool setFlags) + private static void EmitAdc(ILEmitterCtx context, bool setFlags) { EmitDataLoadOpers(context); context.Emit(OpCodes.Add); - context.EmitLdflg((int)ApState.CBit); + context.EmitLdflg((int)PState.CBit); Type[] mthdTypes = new Type[] { typeof(bool) }; @@ -29,7 +29,7 @@ namespace ChocolArm64.Instruction context.EmitCall(mthdInfo); - if (context.CurrOp.RegisterSize != ARegisterSize.Int32) + if (context.CurrOp.RegisterSize != RegisterSize.Int32) { context.Emit(OpCodes.Conv_U8); } @@ -47,9 +47,9 @@ namespace ChocolArm64.Instruction EmitDataStore(context); } - public static void Add(AilEmitterCtx context) => EmitDataOp(context, OpCodes.Add); + public static void Add(ILEmitterCtx context) => EmitDataOp(context, OpCodes.Add); - public static void Adds(AilEmitterCtx context) + public static void Adds(ILEmitterCtx context) { EmitDataLoadOpers(context); @@ -62,9 +62,9 @@ namespace ChocolArm64.Instruction EmitDataStoreS(context); } - public static void And(AilEmitterCtx context) => EmitDataOp(context, OpCodes.And); + public static void And(ILEmitterCtx context) => EmitDataOp(context, OpCodes.And); - public static void Ands(AilEmitterCtx context) + public static void Ands(ILEmitterCtx context) { EmitDataLoadOpers(context); @@ -77,12 +77,12 @@ namespace ChocolArm64.Instruction EmitDataStoreS(context); } - public static void Asrv(AilEmitterCtx context) => EmitDataOpShift(context, OpCodes.Shr); + public static void Asrv(ILEmitterCtx context) => EmitDataOpShift(context, OpCodes.Shr); - public static void Bic(AilEmitterCtx context) => EmitBic(context, false); - public static void Bics(AilEmitterCtx context) => EmitBic(context, true); + public static void Bic(ILEmitterCtx context) => EmitBic(context, false); + public static void Bics(ILEmitterCtx context) => EmitBic(context, true); - private static void EmitBic(AilEmitterCtx context, bool setFlags) + private static void EmitBic(ILEmitterCtx context, bool setFlags) { EmitDataLoadOpers(context); @@ -99,42 +99,42 @@ namespace ChocolArm64.Instruction EmitDataStore(context, setFlags); } - public static void Cls(AilEmitterCtx context) + public static void Cls(ILEmitterCtx context) { - AOpCodeAlu op = (AOpCodeAlu)context.CurrOp; + OpCodeAlu op = (OpCodeAlu)context.CurrOp; context.EmitLdintzr(op.Rn); - context.EmitLdc_I4(op.RegisterSize == ARegisterSize.Int32 ? 32 : 64); + context.EmitLdc_I4(op.RegisterSize == RegisterSize.Int32 ? 32 : 64); - ASoftFallback.EmitCall(context, nameof(ASoftFallback.CountLeadingSigns)); + SoftFallback.EmitCall(context, nameof(SoftFallback.CountLeadingSigns)); context.EmitStintzr(op.Rd); } - public static void Clz(AilEmitterCtx context) + public static void Clz(ILEmitterCtx context) { - AOpCodeAlu op = (AOpCodeAlu)context.CurrOp; + OpCodeAlu op = (OpCodeAlu)context.CurrOp; context.EmitLdintzr(op.Rn); if (Lzcnt.IsSupported) { - Type tValue = op.RegisterSize == ARegisterSize.Int32 ? typeof(uint) : typeof(ulong); + Type tValue = op.RegisterSize == RegisterSize.Int32 ? typeof(uint) : typeof(ulong); context.EmitCall(typeof(Lzcnt).GetMethod(nameof(Lzcnt.LeadingZeroCount), new Type[] { tValue })); } else { - context.EmitLdc_I4(op.RegisterSize == ARegisterSize.Int32 ? 32 : 64); + context.EmitLdc_I4(op.RegisterSize == RegisterSize.Int32 ? 32 : 64); - ASoftFallback.EmitCall(context, nameof(ASoftFallback.CountLeadingZeros)); + SoftFallback.EmitCall(context, nameof(SoftFallback.CountLeadingZeros)); } context.EmitStintzr(op.Rd); } - public static void Eon(AilEmitterCtx context) + public static void Eon(ILEmitterCtx context) { EmitDataLoadOpers(context); @@ -144,12 +144,12 @@ namespace ChocolArm64.Instruction EmitDataStore(context); } - public static void Eor(AilEmitterCtx context) => EmitDataOp(context, OpCodes.Xor); + public static void Eor(ILEmitterCtx context) => EmitDataOp(context, OpCodes.Xor); - public static void Extr(AilEmitterCtx context) + public static void Extr(ILEmitterCtx context) { //TODO: Ensure that the Shift is valid for the Is64Bits. - AOpCodeAluRs op = (AOpCodeAluRs)context.CurrOp; + OpCodeAluRs op = (OpCodeAluRs)context.CurrOp; context.EmitLdintzr(op.Rm); @@ -169,19 +169,19 @@ namespace ChocolArm64.Instruction EmitDataStore(context); } - public static void Lslv(AilEmitterCtx context) => EmitDataOpShift(context, OpCodes.Shl); - public static void Lsrv(AilEmitterCtx context) => EmitDataOpShift(context, OpCodes.Shr_Un); + public static void Lslv(ILEmitterCtx context) => EmitDataOpShift(context, OpCodes.Shl); + public static void Lsrv(ILEmitterCtx context) => EmitDataOpShift(context, OpCodes.Shr_Un); - public static void Sbc(AilEmitterCtx context) => EmitSbc(context, false); - public static void Sbcs(AilEmitterCtx context) => EmitSbc(context, true); + public static void Sbc(ILEmitterCtx context) => EmitSbc(context, false); + public static void Sbcs(ILEmitterCtx context) => EmitSbc(context, true); - private static void EmitSbc(AilEmitterCtx context, bool setFlags) + private static void EmitSbc(ILEmitterCtx context, bool setFlags) { EmitDataLoadOpers(context); context.Emit(OpCodes.Sub); - context.EmitLdflg((int)ApState.CBit); + context.EmitLdflg((int)PState.CBit); Type[] mthdTypes = new Type[] { typeof(bool) }; @@ -193,7 +193,7 @@ namespace ChocolArm64.Instruction context.Emit(OpCodes.Xor); - if (context.CurrOp.RegisterSize != ARegisterSize.Int32) + if (context.CurrOp.RegisterSize != RegisterSize.Int32) { context.Emit(OpCodes.Conv_U8); } @@ -211,9 +211,9 @@ namespace ChocolArm64.Instruction EmitDataStore(context); } - public static void Sub(AilEmitterCtx context) => EmitDataOp(context, OpCodes.Sub); + public static void Sub(ILEmitterCtx context) => EmitDataOp(context, OpCodes.Sub); - public static void Subs(AilEmitterCtx context) + public static void Subs(ILEmitterCtx context) { context.TryOptMarkCondWithoutCmp(); @@ -228,7 +228,7 @@ namespace ChocolArm64.Instruction EmitDataStoreS(context); } - public static void Orn(AilEmitterCtx context) + public static void Orn(ILEmitterCtx context) { EmitDataLoadOpers(context); @@ -238,50 +238,50 @@ namespace ChocolArm64.Instruction EmitDataStore(context); } - public static void Orr(AilEmitterCtx context) => EmitDataOp(context, OpCodes.Or); + public static void Orr(ILEmitterCtx context) => EmitDataOp(context, OpCodes.Or); - public static void Rbit(AilEmitterCtx context) => EmitFallback32_64(context, - nameof(ASoftFallback.ReverseBits32), - nameof(ASoftFallback.ReverseBits64)); + public static void Rbit(ILEmitterCtx context) => EmitFallback32_64(context, + nameof(SoftFallback.ReverseBits32), + nameof(SoftFallback.ReverseBits64)); - public static void Rev16(AilEmitterCtx context) => EmitFallback32_64(context, - nameof(ASoftFallback.ReverseBytes16_32), - nameof(ASoftFallback.ReverseBytes16_64)); + public static void Rev16(ILEmitterCtx context) => EmitFallback32_64(context, + nameof(SoftFallback.ReverseBytes16_32), + nameof(SoftFallback.ReverseBytes16_64)); - public static void Rev32(AilEmitterCtx context) => EmitFallback32_64(context, - nameof(ASoftFallback.ReverseBytes32_32), - nameof(ASoftFallback.ReverseBytes32_64)); + public static void Rev32(ILEmitterCtx context) => EmitFallback32_64(context, + nameof(SoftFallback.ReverseBytes32_32), + nameof(SoftFallback.ReverseBytes32_64)); - private static void EmitFallback32_64(AilEmitterCtx context, string name32, string name64) + private static void EmitFallback32_64(ILEmitterCtx context, string name32, string name64) { - AOpCodeAlu op = (AOpCodeAlu)context.CurrOp; + OpCodeAlu op = (OpCodeAlu)context.CurrOp; context.EmitLdintzr(op.Rn); - if (op.RegisterSize == ARegisterSize.Int32) + if (op.RegisterSize == RegisterSize.Int32) { - ASoftFallback.EmitCall(context, name32); + SoftFallback.EmitCall(context, name32); } else { - ASoftFallback.EmitCall(context, name64); + SoftFallback.EmitCall(context, name64); } context.EmitStintzr(op.Rd); } - public static void Rev64(AilEmitterCtx context) + public static void Rev64(ILEmitterCtx context) { - AOpCodeAlu op = (AOpCodeAlu)context.CurrOp; + OpCodeAlu op = (OpCodeAlu)context.CurrOp; context.EmitLdintzr(op.Rn); - ASoftFallback.EmitCall(context, nameof(ASoftFallback.ReverseBytes64)); + SoftFallback.EmitCall(context, nameof(SoftFallback.ReverseBytes64)); context.EmitStintzr(op.Rd); } - public static void Rorv(AilEmitterCtx context) + public static void Rorv(ILEmitterCtx context) { EmitDataLoadRn(context); EmitDataLoadShift(context); @@ -301,10 +301,10 @@ namespace ChocolArm64.Instruction EmitDataStore(context); } - public static void Sdiv(AilEmitterCtx context) => EmitDiv(context, OpCodes.Div); - public static void Udiv(AilEmitterCtx context) => EmitDiv(context, OpCodes.Div_Un); + public static void Sdiv(ILEmitterCtx context) => EmitDiv(context, OpCodes.Div); + public static void Udiv(ILEmitterCtx context) => EmitDiv(context, OpCodes.Div_Un); - private static void EmitDiv(AilEmitterCtx context, OpCode ilOp) + private static void EmitDiv(ILEmitterCtx context, OpCode ilOp) { //If Rm == 0, Rd = 0 (division by zero). context.EmitLdc_I(0); @@ -313,7 +313,7 @@ namespace ChocolArm64.Instruction context.EmitLdc_I(0); - AilLabel badDiv = new AilLabel(); + ILLabel badDiv = new ILLabel(); context.Emit(OpCodes.Beq_S, badDiv); context.Emit(OpCodes.Pop); @@ -351,7 +351,7 @@ namespace ChocolArm64.Instruction EmitDataStore(context); } - private static void EmitDataOp(AilEmitterCtx context, OpCode ilOp) + private static void EmitDataOp(ILEmitterCtx context, OpCode ilOp) { EmitDataLoadOpers(context); @@ -360,7 +360,7 @@ namespace ChocolArm64.Instruction EmitDataStore(context); } - private static void EmitDataOpShift(AilEmitterCtx context, OpCode ilOp) + private static void EmitDataOpShift(ILEmitterCtx context, OpCode ilOp) { EmitDataLoadRn(context); EmitDataLoadShift(context); @@ -370,7 +370,7 @@ namespace ChocolArm64.Instruction EmitDataStore(context); } - private static void EmitDataLoadShift(AilEmitterCtx context) + private static void EmitDataLoadShift(ILEmitterCtx context) { EmitDataLoadRm(context); @@ -382,21 +382,21 @@ namespace ChocolArm64.Instruction //we need to cast it to a 32-bits integer. This is fine because we //AND the value and only keep the lower 5 or 6 bits anyway -- it //could very well fit on a byte. - if (context.CurrOp.RegisterSize != ARegisterSize.Int32) + if (context.CurrOp.RegisterSize != RegisterSize.Int32) { context.Emit(OpCodes.Conv_I4); } } - private static void EmitZeroCvFlags(AilEmitterCtx context) + private static void EmitZeroCvFlags(ILEmitterCtx context) { context.EmitLdc_I4(0); - context.EmitStflg((int)ApState.VBit); + context.EmitStflg((int)PState.VBit); context.EmitLdc_I4(0); - context.EmitStflg((int)ApState.CBit); + context.EmitStflg((int)PState.CBit); } } } diff --git a/ChocolArm64/Instruction/AInstEmitAluHelper.cs b/ChocolArm64/Instruction/InstEmitAluHelper.cs similarity index 58% rename from ChocolArm64/Instruction/AInstEmitAluHelper.cs rename to ChocolArm64/Instruction/InstEmitAluHelper.cs index 80bf910eb4..db005bc820 100644 --- a/ChocolArm64/Instruction/AInstEmitAluHelper.cs +++ b/ChocolArm64/Instruction/InstEmitAluHelper.cs @@ -5,9 +5,9 @@ using System.Reflection.Emit; namespace ChocolArm64.Instruction { - static class AInstEmitAluHelper + static class InstEmitAluHelper { - public static void EmitAdcsCCheck(AilEmitterCtx context) + public static void EmitAdcsCCheck(ILEmitterCtx context) { //C = (Rd == Rn && CIn) || Rd < Rn context.EmitSttmp(); @@ -18,7 +18,7 @@ namespace ChocolArm64.Instruction context.Emit(OpCodes.Ceq); - context.EmitLdflg((int)ApState.CBit); + context.EmitLdflg((int)PState.CBit); context.Emit(OpCodes.And); @@ -29,10 +29,10 @@ namespace ChocolArm64.Instruction context.Emit(OpCodes.Clt_Un); context.Emit(OpCodes.Or); - context.EmitStflg((int)ApState.CBit); + context.EmitStflg((int)PState.CBit); } - public static void EmitAddsCCheck(AilEmitterCtx context) + public static void EmitAddsCCheck(ILEmitterCtx context) { //C = Rd < Rn context.Emit(OpCodes.Dup); @@ -41,10 +41,10 @@ namespace ChocolArm64.Instruction context.Emit(OpCodes.Clt_Un); - context.EmitStflg((int)ApState.CBit); + context.EmitStflg((int)PState.CBit); } - public static void EmitAddsVCheck(AilEmitterCtx context) + public static void EmitAddsVCheck(ILEmitterCtx context) { //V = (Rd ^ Rn) & ~(Rn ^ Rm) < 0 context.Emit(OpCodes.Dup); @@ -63,17 +63,17 @@ namespace ChocolArm64.Instruction context.Emit(OpCodes.Clt); - context.EmitStflg((int)ApState.VBit); + context.EmitStflg((int)PState.VBit); } - public static void EmitSbcsCCheck(AilEmitterCtx context) + public static void EmitSbcsCCheck(ILEmitterCtx context) { //C = (Rn == Rm && CIn) || Rn > Rm EmitDataLoadOpers(context); context.Emit(OpCodes.Ceq); - context.EmitLdflg((int)ApState.CBit); + context.EmitLdflg((int)PState.CBit); context.Emit(OpCodes.And); @@ -82,10 +82,10 @@ namespace ChocolArm64.Instruction context.Emit(OpCodes.Cgt_Un); context.Emit(OpCodes.Or); - context.EmitStflg((int)ApState.CBit); + context.EmitStflg((int)PState.CBit); } - public static void EmitSubsCCheck(AilEmitterCtx context) + public static void EmitSubsCCheck(ILEmitterCtx context) { //C = Rn == Rm || Rn > Rm = !(Rn < Rm) EmitDataLoadOpers(context); @@ -96,10 +96,10 @@ namespace ChocolArm64.Instruction context.Emit(OpCodes.Xor); - context.EmitStflg((int)ApState.CBit); + context.EmitStflg((int)PState.CBit); } - public static void EmitSubsVCheck(AilEmitterCtx context) + public static void EmitSubsVCheck(ILEmitterCtx context) { //V = (Rd ^ Rn) & (Rn ^ Rm) < 0 context.Emit(OpCodes.Dup); @@ -117,25 +117,25 @@ namespace ChocolArm64.Instruction context.Emit(OpCodes.Clt); - context.EmitStflg((int)ApState.VBit); + context.EmitStflg((int)PState.VBit); } - public static void EmitDataLoadRm(AilEmitterCtx context) + public static void EmitDataLoadRm(ILEmitterCtx context) { - context.EmitLdintzr(((IaOpCodeAluRs)context.CurrOp).Rm); + context.EmitLdintzr(((IOpCodeAluRs)context.CurrOp).Rm); } - public static void EmitDataLoadOpers(AilEmitterCtx context) + public static void EmitDataLoadOpers(ILEmitterCtx context) { EmitDataLoadRn(context); EmitDataLoadOper2(context); } - public static void EmitDataLoadRn(AilEmitterCtx context) + public static void EmitDataLoadRn(ILEmitterCtx context) { - IaOpCodeAlu op = (IaOpCodeAlu)context.CurrOp; + IOpCodeAlu op = (IOpCodeAlu)context.CurrOp; - if (op.DataOp == ADataOp.Logical || op is IaOpCodeAluRs) + if (op.DataOp == DataOp.Logical || op is IOpCodeAluRs) { context.EmitLdintzr(op.Rn); } @@ -145,27 +145,27 @@ namespace ChocolArm64.Instruction } } - public static void EmitDataLoadOper2(AilEmitterCtx context) + public static void EmitDataLoadOper2(ILEmitterCtx context) { switch (context.CurrOp) { - case IaOpCodeAluImm op: + case IOpCodeAluImm op: context.EmitLdc_I(op.Imm); break; - case IaOpCodeAluRs op: + case IOpCodeAluRs op: context.EmitLdintzr(op.Rm); switch (op.ShiftType) { - case AShiftType.Lsl: context.EmitLsl(op.Shift); break; - case AShiftType.Lsr: context.EmitLsr(op.Shift); break; - case AShiftType.Asr: context.EmitAsr(op.Shift); break; - case AShiftType.Ror: context.EmitRor(op.Shift); break; + case ShiftType.Lsl: context.EmitLsl(op.Shift); break; + case ShiftType.Lsr: context.EmitLsr(op.Shift); break; + case ShiftType.Asr: context.EmitAsr(op.Shift); break; + case ShiftType.Ror: context.EmitRor(op.Shift); break; } break; - case IaOpCodeAluRx op: + case IOpCodeAluRx op: context.EmitLdintzr(op.Rm); context.EmitCast(op.IntType); context.EmitLsl(op.Shift); @@ -173,14 +173,14 @@ namespace ChocolArm64.Instruction } } - public static void EmitDataStore(AilEmitterCtx context) => EmitDataStore(context, false); - public static void EmitDataStoreS(AilEmitterCtx context) => EmitDataStore(context, true); + public static void EmitDataStore(ILEmitterCtx context) => EmitDataStore(context, false); + public static void EmitDataStoreS(ILEmitterCtx context) => EmitDataStore(context, true); - public static void EmitDataStore(AilEmitterCtx context, bool setFlags) + public static void EmitDataStore(ILEmitterCtx context, bool setFlags) { - IaOpCodeAlu op = (IaOpCodeAlu)context.CurrOp; + IOpCodeAlu op = (IOpCodeAlu)context.CurrOp; - if (setFlags || op is IaOpCodeAluRs) + if (setFlags || op is IOpCodeAluRs) { context.EmitStintzr(op.Rd); } @@ -190,23 +190,23 @@ namespace ChocolArm64.Instruction } } - public static void EmitSetNzcv(AilEmitterCtx context, int nzcv) + public static void EmitSetNzcv(ILEmitterCtx context, int nzcv) { context.EmitLdc_I4((nzcv >> 0) & 1); - context.EmitStflg((int)ApState.VBit); + context.EmitStflg((int)PState.VBit); context.EmitLdc_I4((nzcv >> 1) & 1); - context.EmitStflg((int)ApState.CBit); + context.EmitStflg((int)PState.CBit); context.EmitLdc_I4((nzcv >> 2) & 1); - context.EmitStflg((int)ApState.ZBit); + context.EmitStflg((int)PState.ZBit); context.EmitLdc_I4((nzcv >> 3) & 1); - context.EmitStflg((int)ApState.NBit); + context.EmitStflg((int)PState.NBit); } } } \ No newline at end of file diff --git a/ChocolArm64/Instruction/AInstEmitBfm.cs b/ChocolArm64/Instruction/InstEmitBfm.cs similarity index 72% rename from ChocolArm64/Instruction/AInstEmitBfm.cs rename to ChocolArm64/Instruction/InstEmitBfm.cs index cbd079fc21..db0a8c23d2 100644 --- a/ChocolArm64/Instruction/AInstEmitBfm.cs +++ b/ChocolArm64/Instruction/InstEmitBfm.cs @@ -5,11 +5,11 @@ using System.Reflection.Emit; namespace ChocolArm64.Instruction { - static partial class AInstEmit + static partial class InstEmit { - public static void Bfm(AilEmitterCtx context) + public static void Bfm(ILEmitterCtx context) { - AOpCodeBfm op = (AOpCodeBfm)context.CurrOp; + OpCodeBfm op = (OpCodeBfm)context.CurrOp; EmitBfmLoadRn(context); @@ -28,9 +28,9 @@ namespace ChocolArm64.Instruction context.EmitStintzr(op.Rd); } - public static void Sbfm(AilEmitterCtx context) + public static void Sbfm(ILEmitterCtx context) { - AOpCodeBfm op = (AOpCodeBfm)context.CurrOp; + OpCodeBfm op = (OpCodeBfm)context.CurrOp; int bitsCount = op.GetBitsCount(); @@ -72,9 +72,9 @@ namespace ChocolArm64.Instruction } } - public static void Ubfm(AilEmitterCtx context) + public static void Ubfm(ILEmitterCtx context) { - AOpCodeBfm op = (AOpCodeBfm)context.CurrOp; + OpCodeBfm op = (OpCodeBfm)context.CurrOp; if (op.Pos + 1 == op.GetBitsCount()) { @@ -104,12 +104,12 @@ namespace ChocolArm64.Instruction } } - private static void EmitSbfiz(AilEmitterCtx context) => EmitBfiz(context, true); - private static void EmitUbfiz(AilEmitterCtx context) => EmitBfiz(context, false); + private static void EmitSbfiz(ILEmitterCtx context) => EmitBfiz(context, true); + private static void EmitUbfiz(ILEmitterCtx context) => EmitBfiz(context, false); - private static void EmitBfiz(AilEmitterCtx context, bool signed) + private static void EmitBfiz(ILEmitterCtx context, bool signed) { - AOpCodeBfm op = (AOpCodeBfm)context.CurrOp; + OpCodeBfm op = (OpCodeBfm)context.CurrOp; int width = op.Pos + 1; @@ -129,25 +129,25 @@ namespace ChocolArm64.Instruction context.EmitStintzr(op.Rd); } - private static void EmitSbfmCast(AilEmitterCtx context, OpCode ilOp) + private static void EmitSbfmCast(ILEmitterCtx context, OpCode ilOp) { EmitBfmCast(context, ilOp, true); } - private static void EmitUbfmCast(AilEmitterCtx context, OpCode ilOp) + private static void EmitUbfmCast(ILEmitterCtx context, OpCode ilOp) { EmitBfmCast(context, ilOp, false); } - private static void EmitBfmCast(AilEmitterCtx context, OpCode ilOp, bool signed) + private static void EmitBfmCast(ILEmitterCtx context, OpCode ilOp, bool signed) { - AOpCodeBfm op = (AOpCodeBfm)context.CurrOp; + OpCodeBfm op = (OpCodeBfm)context.CurrOp; context.EmitLdintzr(op.Rn); context.Emit(ilOp); - if (op.RegisterSize != ARegisterSize.Int32) + if (op.RegisterSize != RegisterSize.Int32) { context.Emit(signed ? OpCodes.Conv_I8 @@ -157,19 +157,19 @@ namespace ChocolArm64.Instruction context.EmitStintzr(op.Rd); } - private static void EmitSbfmShift(AilEmitterCtx context) + private static void EmitSbfmShift(ILEmitterCtx context) { EmitBfmShift(context, true); } - private static void EmitUbfmShift(AilEmitterCtx context) + private static void EmitUbfmShift(ILEmitterCtx context) { EmitBfmShift(context, false); } - private static void EmitBfmShift(AilEmitterCtx context, bool signed) + private static void EmitBfmShift(ILEmitterCtx context, bool signed) { - AOpCodeBfm op = (AOpCodeBfm)context.CurrOp; + OpCodeBfm op = (OpCodeBfm)context.CurrOp; context.EmitLdintzr(op.Rn); context.EmitLdc_I4(op.Shift); @@ -181,9 +181,9 @@ namespace ChocolArm64.Instruction context.EmitStintzr(op.Rd); } - private static void EmitBfmLsl(AilEmitterCtx context) + private static void EmitBfmLsl(ILEmitterCtx context) { - AOpCodeBfm op = (AOpCodeBfm)context.CurrOp; + OpCodeBfm op = (OpCodeBfm)context.CurrOp; context.EmitLdintzr(op.Rn); @@ -192,9 +192,9 @@ namespace ChocolArm64.Instruction context.EmitStintzr(op.Rd); } - private static void EmitBfmLoadRn(AilEmitterCtx context) + private static void EmitBfmLoadRn(ILEmitterCtx context) { - AOpCodeBfm op = (AOpCodeBfm)context.CurrOp; + OpCodeBfm op = (OpCodeBfm)context.CurrOp; context.EmitLdintzr(op.Rn); diff --git a/ChocolArm64/Instruction/AInstEmitCcmp.cs b/ChocolArm64/Instruction/InstEmitCcmp.cs similarity index 65% rename from ChocolArm64/Instruction/AInstEmitCcmp.cs rename to ChocolArm64/Instruction/InstEmitCcmp.cs index fcf3b5148d..f616c9b210 100644 --- a/ChocolArm64/Instruction/AInstEmitCcmp.cs +++ b/ChocolArm64/Instruction/InstEmitCcmp.cs @@ -4,11 +4,11 @@ using ChocolArm64.Translation; using System; using System.Reflection.Emit; -using static ChocolArm64.Instruction.AInstEmitAluHelper; +using static ChocolArm64.Instruction.InstEmitAluHelper; namespace ChocolArm64.Instruction { - static partial class AInstEmit + static partial class InstEmit { private enum CcmpOp { @@ -16,33 +16,33 @@ namespace ChocolArm64.Instruction Cmn } - public static void Ccmn(AilEmitterCtx context) => EmitCcmp(context, CcmpOp.Cmn); - public static void Ccmp(AilEmitterCtx context) => EmitCcmp(context, CcmpOp.Cmp); + public static void Ccmn(ILEmitterCtx context) => EmitCcmp(context, CcmpOp.Cmn); + public static void Ccmp(ILEmitterCtx context) => EmitCcmp(context, CcmpOp.Cmp); - private static void EmitCcmp(AilEmitterCtx context, CcmpOp cmpOp) + private static void EmitCcmp(ILEmitterCtx context, CcmpOp cmpOp) { - AOpCodeCcmp op = (AOpCodeCcmp)context.CurrOp; + OpCodeCcmp op = (OpCodeCcmp)context.CurrOp; - AilLabel lblTrue = new AilLabel(); - AilLabel lblEnd = new AilLabel(); + ILLabel lblTrue = new ILLabel(); + ILLabel lblEnd = new ILLabel(); context.EmitCondBranch(lblTrue, op.Cond); context.EmitLdc_I4((op.Nzcv >> 0) & 1); - context.EmitStflg((int)ApState.VBit); + context.EmitStflg((int)PState.VBit); context.EmitLdc_I4((op.Nzcv >> 1) & 1); - context.EmitStflg((int)ApState.CBit); + context.EmitStflg((int)PState.CBit); context.EmitLdc_I4((op.Nzcv >> 2) & 1); - context.EmitStflg((int)ApState.ZBit); + context.EmitStflg((int)PState.ZBit); context.EmitLdc_I4((op.Nzcv >> 3) & 1); - context.EmitStflg((int)ApState.NBit); + context.EmitStflg((int)PState.NBit); context.Emit(OpCodes.Br_S, lblEnd); diff --git a/ChocolArm64/Instruction/AInstEmitCsel.cs b/ChocolArm64/Instruction/InstEmitCsel.cs similarity index 60% rename from ChocolArm64/Instruction/AInstEmitCsel.cs rename to ChocolArm64/Instruction/InstEmitCsel.cs index f382ccf2ea..30158f0acd 100644 --- a/ChocolArm64/Instruction/AInstEmitCsel.cs +++ b/ChocolArm64/Instruction/InstEmitCsel.cs @@ -4,7 +4,7 @@ using System.Reflection.Emit; namespace ChocolArm64.Instruction { - static partial class AInstEmit + static partial class InstEmit { private enum CselOperation { @@ -14,17 +14,17 @@ namespace ChocolArm64.Instruction Negate } - public static void Csel(AilEmitterCtx context) => EmitCsel(context, CselOperation.None); - public static void Csinc(AilEmitterCtx context) => EmitCsel(context, CselOperation.Increment); - public static void Csinv(AilEmitterCtx context) => EmitCsel(context, CselOperation.Invert); - public static void Csneg(AilEmitterCtx context) => EmitCsel(context, CselOperation.Negate); + public static void Csel(ILEmitterCtx context) => EmitCsel(context, CselOperation.None); + public static void Csinc(ILEmitterCtx context) => EmitCsel(context, CselOperation.Increment); + public static void Csinv(ILEmitterCtx context) => EmitCsel(context, CselOperation.Invert); + public static void Csneg(ILEmitterCtx context) => EmitCsel(context, CselOperation.Negate); - private static void EmitCsel(AilEmitterCtx context, CselOperation cselOp) + private static void EmitCsel(ILEmitterCtx context, CselOperation cselOp) { - AOpCodeCsel op = (AOpCodeCsel)context.CurrOp; + OpCodeCsel op = (OpCodeCsel)context.CurrOp; - AilLabel lblTrue = new AilLabel(); - AilLabel lblEnd = new AilLabel(); + ILLabel lblTrue = new ILLabel(); + ILLabel lblEnd = new ILLabel(); context.EmitCondBranch(lblTrue, op.Cond); context.EmitLdintzr(op.Rm); diff --git a/ChocolArm64/Instruction/AInstEmitException.cs b/ChocolArm64/Instruction/InstEmitException.cs similarity index 76% rename from ChocolArm64/Instruction/AInstEmitException.cs rename to ChocolArm64/Instruction/InstEmitException.cs index 87affad2bb..d6adcba80a 100644 --- a/ChocolArm64/Instruction/AInstEmitException.cs +++ b/ChocolArm64/Instruction/InstEmitException.cs @@ -5,25 +5,25 @@ using System.Reflection.Emit; namespace ChocolArm64.Instruction { - static partial class AInstEmit + static partial class InstEmit { - public static void Brk(AilEmitterCtx context) + public static void Brk(ILEmitterCtx context) { EmitExceptionCall(context, nameof(AThreadState.OnBreak)); } - public static void Svc(AilEmitterCtx context) + public static void Svc(ILEmitterCtx context) { EmitExceptionCall(context, nameof(AThreadState.OnSvcCall)); } - private static void EmitExceptionCall(AilEmitterCtx context, string mthdName) + private static void EmitExceptionCall(ILEmitterCtx context, string mthdName) { - AOpCodeException op = (AOpCodeException)context.CurrOp; + OpCodeException op = (OpCodeException)context.CurrOp; context.EmitStoreState(); - context.EmitLdarg(ATranslatedSub.StateArgIdx); + context.EmitLdarg(TranslatedSub.StateArgIdx); context.EmitLdc_I8(op.Position); context.EmitLdc_I4(op.Id); @@ -32,11 +32,11 @@ namespace ChocolArm64.Instruction //Check if the thread should still be running, if it isn't then we return 0 //to force a return to the dispatcher and then exit the thread. - context.EmitLdarg(ATranslatedSub.StateArgIdx); + context.EmitLdarg(TranslatedSub.StateArgIdx); context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Running)); - AilLabel lblEnd = new AilLabel(); + ILLabel lblEnd = new ILLabel(); context.Emit(OpCodes.Brtrue_S, lblEnd); @@ -58,13 +58,13 @@ namespace ChocolArm64.Instruction } } - public static void Und(AilEmitterCtx context) + public static void Und(ILEmitterCtx context) { AOpCode op = context.CurrOp; context.EmitStoreState(); - context.EmitLdarg(ATranslatedSub.StateArgIdx); + context.EmitLdarg(TranslatedSub.StateArgIdx); context.EmitLdc_I8(op.Position); context.EmitLdc_I4(op.RawOpCode); diff --git a/ChocolArm64/Instruction/AInstEmitFlow.cs b/ChocolArm64/Instruction/InstEmitFlow.cs similarity index 68% rename from ChocolArm64/Instruction/AInstEmitFlow.cs rename to ChocolArm64/Instruction/InstEmitFlow.cs index 8a79528d81..124b7147de 100644 --- a/ChocolArm64/Instruction/AInstEmitFlow.cs +++ b/ChocolArm64/Instruction/InstEmitFlow.cs @@ -5,11 +5,11 @@ using System.Reflection.Emit; namespace ChocolArm64.Instruction { - static partial class AInstEmit + static partial class InstEmit { - public static void B(AilEmitterCtx context) + public static void B(ILEmitterCtx context) { - AOpCodeBImmAl op = (AOpCodeBImmAl)context.CurrOp; + OpCodeBImmAl op = (OpCodeBImmAl)context.CurrOp; if (context.CurrBlock.Branch != null) { @@ -24,16 +24,16 @@ namespace ChocolArm64.Instruction } } - public static void B_Cond(AilEmitterCtx context) + public static void B_Cond(ILEmitterCtx context) { - AOpCodeBImmCond op = (AOpCodeBImmCond)context.CurrOp; + OpCodeBImmCond op = (OpCodeBImmCond)context.CurrOp; EmitBranch(context, op.Cond); } - public static void Bl(AilEmitterCtx context) + public static void Bl(ILEmitterCtx context) { - AOpCodeBImmAl op = (AOpCodeBImmAl)context.CurrOp; + OpCodeBImmAl op = (OpCodeBImmAl)context.CurrOp; context.EmitLdc_I(op.Position + 4); context.EmitStint(AThreadState.LrIndex); @@ -49,7 +49,7 @@ namespace ChocolArm64.Instruction context.EmitLdc_I8(op.Position + 4); - AilLabel lblContinue = new AilLabel(); + ILLabel lblContinue = new ILLabel(); context.Emit(OpCodes.Beq_S, lblContinue); context.Emit(OpCodes.Ret); @@ -68,9 +68,9 @@ namespace ChocolArm64.Instruction } } - public static void Blr(AilEmitterCtx context) + public static void Blr(ILEmitterCtx context) { - AOpCodeBReg op = (AOpCodeBReg)context.CurrOp; + OpCodeBReg op = (OpCodeBReg)context.CurrOp; context.EmitLdc_I(op.Position + 4); context.EmitStint(AThreadState.LrIndex); @@ -80,9 +80,9 @@ namespace ChocolArm64.Instruction context.Emit(OpCodes.Ret); } - public static void Br(AilEmitterCtx context) + public static void Br(ILEmitterCtx context) { - AOpCodeBReg op = (AOpCodeBReg)context.CurrOp; + OpCodeBReg op = (OpCodeBReg)context.CurrOp; context.EmitStoreState(); context.EmitLdintzr(op.Rn); @@ -90,12 +90,12 @@ namespace ChocolArm64.Instruction context.Emit(OpCodes.Ret); } - public static void Cbnz(AilEmitterCtx context) => EmitCb(context, OpCodes.Bne_Un); - public static void Cbz(AilEmitterCtx context) => EmitCb(context, OpCodes.Beq); + public static void Cbnz(ILEmitterCtx context) => EmitCb(context, OpCodes.Bne_Un); + public static void Cbz(ILEmitterCtx context) => EmitCb(context, OpCodes.Beq); - private static void EmitCb(AilEmitterCtx context, OpCode ilOp) + private static void EmitCb(ILEmitterCtx context, OpCode ilOp) { - AOpCodeBImmCmp op = (AOpCodeBImmCmp)context.CurrOp; + OpCodeBImmCmp op = (OpCodeBImmCmp)context.CurrOp; context.EmitLdintzr(op.Rt); context.EmitLdc_I(0); @@ -103,7 +103,7 @@ namespace ChocolArm64.Instruction EmitBranch(context, ilOp); } - public static void Ret(AilEmitterCtx context) + public static void Ret(ILEmitterCtx context) { context.EmitStoreState(); context.EmitLdint(AThreadState.LrIndex); @@ -111,12 +111,12 @@ namespace ChocolArm64.Instruction context.Emit(OpCodes.Ret); } - public static void Tbnz(AilEmitterCtx context) => EmitTb(context, OpCodes.Bne_Un); - public static void Tbz(AilEmitterCtx context) => EmitTb(context, OpCodes.Beq); + public static void Tbnz(ILEmitterCtx context) => EmitTb(context, OpCodes.Bne_Un); + public static void Tbz(ILEmitterCtx context) => EmitTb(context, OpCodes.Beq); - private static void EmitTb(AilEmitterCtx context, OpCode ilOp) + private static void EmitTb(ILEmitterCtx context, OpCode ilOp) { - AOpCodeBImmTest op = (AOpCodeBImmTest)context.CurrOp; + OpCodeBImmTest op = (OpCodeBImmTest)context.CurrOp; context.EmitLdintzr(op.Rt); context.EmitLdc_I(1L << op.Pos); @@ -128,9 +128,9 @@ namespace ChocolArm64.Instruction EmitBranch(context, ilOp); } - private static void EmitBranch(AilEmitterCtx context, ACond cond) + private static void EmitBranch(ILEmitterCtx context, Cond cond) { - AOpCodeBImm op = (AOpCodeBImm)context.CurrOp; + OpCodeBImm op = (OpCodeBImm)context.CurrOp; if (context.CurrBlock.Next != null && context.CurrBlock.Branch != null) @@ -141,7 +141,7 @@ namespace ChocolArm64.Instruction { context.EmitStoreState(); - AilLabel lblTaken = new AilLabel(); + ILLabel lblTaken = new ILLabel(); context.EmitCondBranch(lblTaken, cond); @@ -157,9 +157,9 @@ namespace ChocolArm64.Instruction } } - private static void EmitBranch(AilEmitterCtx context, OpCode ilOp) + private static void EmitBranch(ILEmitterCtx context, OpCode ilOp) { - AOpCodeBImm op = (AOpCodeBImm)context.CurrOp; + OpCodeBImm op = (OpCodeBImm)context.CurrOp; if (context.CurrBlock.Next != null && context.CurrBlock.Branch != null) @@ -170,7 +170,7 @@ namespace ChocolArm64.Instruction { context.EmitStoreState(); - AilLabel lblTaken = new AilLabel(); + ILLabel lblTaken = new ILLabel(); context.Emit(ilOp, lblTaken); diff --git a/ChocolArm64/Instruction/InstEmitHash.cs b/ChocolArm64/Instruction/InstEmitHash.cs new file mode 100644 index 0000000000..8b632cc450 --- /dev/null +++ b/ChocolArm64/Instruction/InstEmitHash.cs @@ -0,0 +1,115 @@ +using ChocolArm64.Decoder; +using ChocolArm64.State; +using ChocolArm64.Translation; +using System; +using System.Reflection.Emit; +using System.Runtime.Intrinsics.X86; + +namespace ChocolArm64.Instruction +{ + static partial class InstEmit + { + public static void Crc32b(ILEmitterCtx context) + { + EmitCrc32(context, nameof(SoftFallback.Crc32B)); + } + + public static void Crc32h(ILEmitterCtx context) + { + EmitCrc32(context, nameof(SoftFallback.Crc32H)); + } + + public static void Crc32w(ILEmitterCtx context) + { + EmitCrc32(context, nameof(SoftFallback.Crc32W)); + } + + public static void Crc32x(ILEmitterCtx context) + { + EmitCrc32(context, nameof(SoftFallback.Crc32X)); + } + + public static void Crc32cb(ILEmitterCtx context) + { + if (Optimizations.UseSse42) + { + EmitSse42Crc32(context, typeof(uint), typeof(byte)); + } + else + { + EmitCrc32(context, nameof(SoftFallback.Crc32Cb)); + } + } + + public static void Crc32ch(ILEmitterCtx context) + { + if (Optimizations.UseSse42) + { + EmitSse42Crc32(context, typeof(uint), typeof(ushort)); + } + else + { + EmitCrc32(context, nameof(SoftFallback.Crc32Ch)); + } + } + + public static void Crc32cw(ILEmitterCtx context) + { + if (Optimizations.UseSse42) + { + EmitSse42Crc32(context, typeof(uint), typeof(uint)); + } + else + { + EmitCrc32(context, nameof(SoftFallback.Crc32Cw)); + } + } + + public static void Crc32cx(ILEmitterCtx context) + { + if (Optimizations.UseSse42) + { + EmitSse42Crc32(context, typeof(ulong), typeof(ulong)); + } + else + { + EmitCrc32(context, nameof(SoftFallback.Crc32Cx)); + } + } + + private static void EmitSse42Crc32(ILEmitterCtx context, Type tCrc, Type tData) + { + OpCodeAluRs op = (OpCodeAluRs)context.CurrOp; + + context.EmitLdintzr(op.Rn); + context.EmitLdintzr(op.Rm); + + context.EmitCall(typeof(Sse42).GetMethod(nameof(Sse42.Crc32), new Type[] { tCrc, tData })); + + context.EmitStintzr(op.Rd); + } + + private static void EmitCrc32(ILEmitterCtx context, string name) + { + OpCodeAluRs op = (OpCodeAluRs)context.CurrOp; + + context.EmitLdintzr(op.Rn); + + if (op.RegisterSize != RegisterSize.Int32) + { + context.Emit(OpCodes.Conv_U4); + } + + context.EmitLdintzr(op.Rm); + + SoftFallback.EmitCall(context, name); + + if (op.RegisterSize != RegisterSize.Int32) + { + context.Emit(OpCodes.Conv_U8); + } + + context.EmitStintzr(op.Rd); + } + } +} diff --git a/ChocolArm64/Instruction/AInstEmitMemory.cs b/ChocolArm64/Instruction/InstEmitMemory.cs similarity index 69% rename from ChocolArm64/Instruction/AInstEmitMemory.cs rename to ChocolArm64/Instruction/InstEmitMemory.cs index 1f43b796a8..240d807250 100644 --- a/ChocolArm64/Instruction/AInstEmitMemory.cs +++ b/ChocolArm64/Instruction/InstEmitMemory.cs @@ -2,36 +2,36 @@ using ChocolArm64.Decoder; using ChocolArm64.Translation; using System.Reflection.Emit; -using static ChocolArm64.Instruction.AInstEmitMemoryHelper; +using static ChocolArm64.Instruction.InstEmitMemoryHelper; namespace ChocolArm64.Instruction { - static partial class AInstEmit + static partial class InstEmit { - public static void Adr(AilEmitterCtx context) + public static void Adr(ILEmitterCtx context) { - AOpCodeAdr op = (AOpCodeAdr)context.CurrOp; + OpCodeAdr op = (OpCodeAdr)context.CurrOp; context.EmitLdc_I(op.Position + op.Imm); context.EmitStintzr(op.Rd); } - public static void Adrp(AilEmitterCtx context) + public static void Adrp(ILEmitterCtx context) { - AOpCodeAdr op = (AOpCodeAdr)context.CurrOp; + OpCodeAdr op = (OpCodeAdr)context.CurrOp; context.EmitLdc_I((op.Position & ~0xfffL) + (op.Imm << 12)); context.EmitStintzr(op.Rd); } - public static void Ldr(AilEmitterCtx context) => EmitLdr(context, false); - public static void Ldrs(AilEmitterCtx context) => EmitLdr(context, true); + public static void Ldr(ILEmitterCtx context) => EmitLdr(context, false); + public static void Ldrs(ILEmitterCtx context) => EmitLdr(context, true); - private static void EmitLdr(AilEmitterCtx context, bool signed) + private static void EmitLdr(ILEmitterCtx context, bool signed) { - AOpCodeMem op = (AOpCodeMem)context.CurrOp; + OpCodeMem op = (OpCodeMem)context.CurrOp; - context.EmitLdarg(ATranslatedSub.MemoryArgIdx); + context.EmitLdarg(TranslatedSub.MemoryArgIdx); EmitLoadAddress(context); @@ -48,7 +48,7 @@ namespace ChocolArm64.Instruction EmitReadZxCall(context, op.Size); } - if (op is IaOpCodeSimd) + if (op is IOpCodeSimd) { context.EmitStvec(op.Rt); } @@ -60,16 +60,16 @@ namespace ChocolArm64.Instruction EmitWBackIfNeeded(context); } - public static void LdrLit(AilEmitterCtx context) + public static void LdrLit(ILEmitterCtx context) { - IaOpCodeLit op = (IaOpCodeLit)context.CurrOp; + IOpCodeLit op = (IOpCodeLit)context.CurrOp; if (op.Prefetch) { return; } - context.EmitLdarg(ATranslatedSub.MemoryArgIdx); + context.EmitLdarg(TranslatedSub.MemoryArgIdx); context.EmitLdc_I8(op.Imm); if (op.Signed) @@ -81,7 +81,7 @@ namespace ChocolArm64.Instruction EmitReadZxCall(context, op.Size); } - if (op is IaOpCodeSimd) + if (op is IOpCodeSimd) { context.EmitStvec(op.Rt); } @@ -91,9 +91,9 @@ namespace ChocolArm64.Instruction } } - public static void Ldp(AilEmitterCtx context) + public static void Ldp(ILEmitterCtx context) { - AOpCodeMemPair op = (AOpCodeMemPair)context.CurrOp; + OpCodeMemPair op = (OpCodeMemPair)context.CurrOp; void EmitReadAndStore(int rt) { @@ -106,7 +106,7 @@ namespace ChocolArm64.Instruction EmitReadZxCall(context, op.Size); } - if (op is IaOpCodeSimd) + if (op is IOpCodeSimd) { context.EmitStvec(rt); } @@ -116,13 +116,13 @@ namespace ChocolArm64.Instruction } } - context.EmitLdarg(ATranslatedSub.MemoryArgIdx); + context.EmitLdarg(TranslatedSub.MemoryArgIdx); EmitLoadAddress(context); EmitReadAndStore(op.Rt); - context.EmitLdarg(ATranslatedSub.MemoryArgIdx); + context.EmitLdarg(TranslatedSub.MemoryArgIdx); context.EmitLdtmp(); context.EmitLdc_I8(1 << op.Size); @@ -133,15 +133,15 @@ namespace ChocolArm64.Instruction EmitWBackIfNeeded(context); } - public static void Str(AilEmitterCtx context) + public static void Str(ILEmitterCtx context) { - AOpCodeMem op = (AOpCodeMem)context.CurrOp; + OpCodeMem op = (OpCodeMem)context.CurrOp; - context.EmitLdarg(ATranslatedSub.MemoryArgIdx); + context.EmitLdarg(TranslatedSub.MemoryArgIdx); EmitLoadAddress(context); - if (op is IaOpCodeSimd) + if (op is IOpCodeSimd) { context.EmitLdvec(op.Rt); } @@ -155,15 +155,15 @@ namespace ChocolArm64.Instruction EmitWBackIfNeeded(context); } - public static void Stp(AilEmitterCtx context) + public static void Stp(ILEmitterCtx context) { - AOpCodeMemPair op = (AOpCodeMemPair)context.CurrOp; + OpCodeMemPair op = (OpCodeMemPair)context.CurrOp; - context.EmitLdarg(ATranslatedSub.MemoryArgIdx); + context.EmitLdarg(TranslatedSub.MemoryArgIdx); EmitLoadAddress(context); - if (op is IaOpCodeSimd) + if (op is IOpCodeSimd) { context.EmitLdvec(op.Rt); } @@ -174,13 +174,13 @@ namespace ChocolArm64.Instruction EmitWriteCall(context, op.Size); - context.EmitLdarg(ATranslatedSub.MemoryArgIdx); + context.EmitLdarg(TranslatedSub.MemoryArgIdx); context.EmitLdtmp(); context.EmitLdc_I8(1 << op.Size); context.Emit(OpCodes.Add); - if (op is IaOpCodeSimd) + if (op is IOpCodeSimd) { context.EmitLdvec(op.Rt2); } @@ -194,11 +194,11 @@ namespace ChocolArm64.Instruction EmitWBackIfNeeded(context); } - private static void EmitLoadAddress(AilEmitterCtx context) + private static void EmitLoadAddress(ILEmitterCtx context) { switch (context.CurrOp) { - case AOpCodeMemImm op: + case OpCodeMemImm op: context.EmitLdint(op.Rn); if (!op.PostIdx) @@ -210,7 +210,7 @@ namespace ChocolArm64.Instruction } break; - case AOpCodeMemReg op: + case OpCodeMemReg op: context.EmitLdint(op.Rn); context.EmitLdintzr(op.Rm); context.EmitCast(op.IntType); @@ -230,11 +230,11 @@ namespace ChocolArm64.Instruction context.EmitSttmp(); } - private static void EmitWBackIfNeeded(AilEmitterCtx context) + private static void EmitWBackIfNeeded(ILEmitterCtx context) { //Check whenever the current OpCode has post-indexed write back, if so write it. //Note: AOpCodeMemPair inherits from AOpCodeMemImm, so this works for both. - if (context.CurrOp is AOpCodeMemImm op && op.WBack) + if (context.CurrOp is OpCodeMemImm op && op.WBack) { context.EmitLdtmp(); diff --git a/ChocolArm64/Instruction/AInstEmitMemoryEx.cs b/ChocolArm64/Instruction/InstEmitMemoryEx.cs similarity index 59% rename from ChocolArm64/Instruction/AInstEmitMemoryEx.cs rename to ChocolArm64/Instruction/InstEmitMemoryEx.cs index 759c72d1c8..7f41f27ba6 100644 --- a/ChocolArm64/Instruction/AInstEmitMemoryEx.cs +++ b/ChocolArm64/Instruction/InstEmitMemoryEx.cs @@ -6,11 +6,11 @@ using System; using System.Reflection.Emit; using System.Threading; -using static ChocolArm64.Instruction.AInstEmitMemoryHelper; +using static ChocolArm64.Instruction.InstEmitMemoryHelper; namespace ChocolArm64.Instruction { - static partial class AInstEmit + static partial class InstEmit { [Flags] private enum AccessType @@ -21,33 +21,33 @@ namespace ChocolArm64.Instruction OrderedEx = Ordered | Exclusive } - public static void Clrex(AilEmitterCtx context) + public static void Clrex(ILEmitterCtx context) { EmitMemoryCall(context, nameof(AMemory.ClearExclusive)); } - public static void Dmb(AilEmitterCtx context) => EmitBarrier(context); - public static void Dsb(AilEmitterCtx context) => EmitBarrier(context); + public static void Dmb(ILEmitterCtx context) => EmitBarrier(context); + public static void Dsb(ILEmitterCtx context) => EmitBarrier(context); - public static void Ldar(AilEmitterCtx context) => EmitLdr(context, AccessType.Ordered); - public static void Ldaxr(AilEmitterCtx context) => EmitLdr(context, AccessType.OrderedEx); - public static void Ldxr(AilEmitterCtx context) => EmitLdr(context, AccessType.Exclusive); - public static void Ldxp(AilEmitterCtx context) => EmitLdp(context, AccessType.Exclusive); - public static void Ldaxp(AilEmitterCtx context) => EmitLdp(context, AccessType.OrderedEx); + public static void Ldar(ILEmitterCtx context) => EmitLdr(context, AccessType.Ordered); + public static void Ldaxr(ILEmitterCtx context) => EmitLdr(context, AccessType.OrderedEx); + public static void Ldxr(ILEmitterCtx context) => EmitLdr(context, AccessType.Exclusive); + public static void Ldxp(ILEmitterCtx context) => EmitLdp(context, AccessType.Exclusive); + public static void Ldaxp(ILEmitterCtx context) => EmitLdp(context, AccessType.OrderedEx); - private static void EmitLdr(AilEmitterCtx context, AccessType accType) + private static void EmitLdr(ILEmitterCtx context, AccessType accType) { EmitLoad(context, accType, false); } - private static void EmitLdp(AilEmitterCtx context, AccessType accType) + private static void EmitLdp(ILEmitterCtx context, AccessType accType) { EmitLoad(context, accType, true); } - private static void EmitLoad(AilEmitterCtx context, AccessType accType, bool pair) + private static void EmitLoad(ILEmitterCtx context, AccessType accType, bool pair) { - AOpCodeMemEx op = (AOpCodeMemEx)context.CurrOp; + OpCodeMemEx op = (OpCodeMemEx)context.CurrOp; bool ordered = (accType & AccessType.Ordered) != 0; bool exclusive = (accType & AccessType.Exclusive) != 0; @@ -65,7 +65,7 @@ namespace ChocolArm64.Instruction context.EmitLdint(op.Rn); context.EmitSttmp(); - context.EmitLdarg(ATranslatedSub.MemoryArgIdx); + context.EmitLdarg(TranslatedSub.MemoryArgIdx); context.EmitLdtmp(); EmitReadZxCall(context, op.Size); @@ -74,7 +74,7 @@ namespace ChocolArm64.Instruction if (pair) { - context.EmitLdarg(ATranslatedSub.MemoryArgIdx); + context.EmitLdarg(TranslatedSub.MemoryArgIdx); context.EmitLdtmp(); context.EmitLdc_I8(1 << op.Size); @@ -86,30 +86,30 @@ namespace ChocolArm64.Instruction } } - public static void Pfrm(AilEmitterCtx context) + public static void Pfrm(ILEmitterCtx context) { //Memory Prefetch, execute as no-op. } - public static void Stlr(AilEmitterCtx context) => EmitStr(context, AccessType.Ordered); - public static void Stlxr(AilEmitterCtx context) => EmitStr(context, AccessType.OrderedEx); - public static void Stxr(AilEmitterCtx context) => EmitStr(context, AccessType.Exclusive); - public static void Stxp(AilEmitterCtx context) => EmitStp(context, AccessType.Exclusive); - public static void Stlxp(AilEmitterCtx context) => EmitStp(context, AccessType.OrderedEx); + public static void Stlr(ILEmitterCtx context) => EmitStr(context, AccessType.Ordered); + public static void Stlxr(ILEmitterCtx context) => EmitStr(context, AccessType.OrderedEx); + public static void Stxr(ILEmitterCtx context) => EmitStr(context, AccessType.Exclusive); + public static void Stxp(ILEmitterCtx context) => EmitStp(context, AccessType.Exclusive); + public static void Stlxp(ILEmitterCtx context) => EmitStp(context, AccessType.OrderedEx); - private static void EmitStr(AilEmitterCtx context, AccessType accType) + private static void EmitStr(ILEmitterCtx context, AccessType accType) { EmitStore(context, accType, false); } - private static void EmitStp(AilEmitterCtx context, AccessType accType) + private static void EmitStp(ILEmitterCtx context, AccessType accType) { EmitStore(context, accType, true); } - private static void EmitStore(AilEmitterCtx context, AccessType accType, bool pair) + private static void EmitStore(ILEmitterCtx context, AccessType accType, bool pair) { - AOpCodeMemEx op = (AOpCodeMemEx)context.CurrOp; + OpCodeMemEx op = (OpCodeMemEx)context.CurrOp; bool ordered = (accType & AccessType.Ordered) != 0; bool exclusive = (accType & AccessType.Exclusive) != 0; @@ -119,8 +119,8 @@ namespace ChocolArm64.Instruction EmitBarrier(context); } - AilLabel lblEx = new AilLabel(); - AilLabel lblEnd = new AilLabel(); + ILLabel lblEx = new ILLabel(); + ILLabel lblEnd = new ILLabel(); if (exclusive) { @@ -136,7 +136,7 @@ namespace ChocolArm64.Instruction context.MarkLabel(lblEx); - context.EmitLdarg(ATranslatedSub.MemoryArgIdx); + context.EmitLdarg(TranslatedSub.MemoryArgIdx); context.EmitLdint(op.Rn); context.EmitLdintzr(op.Rt); @@ -144,7 +144,7 @@ namespace ChocolArm64.Instruction if (pair) { - context.EmitLdarg(ATranslatedSub.MemoryArgIdx); + context.EmitLdarg(TranslatedSub.MemoryArgIdx); context.EmitLdint(op.Rn); context.EmitLdc_I8(1 << op.Size); @@ -166,10 +166,10 @@ namespace ChocolArm64.Instruction context.MarkLabel(lblEnd); } - private static void EmitMemoryCall(AilEmitterCtx context, string name, int rn = -1) + private static void EmitMemoryCall(ILEmitterCtx context, string name, int rn = -1) { - context.EmitLdarg(ATranslatedSub.MemoryArgIdx); - context.EmitLdarg(ATranslatedSub.StateArgIdx); + context.EmitLdarg(TranslatedSub.MemoryArgIdx); + context.EmitLdarg(TranslatedSub.StateArgIdx); context.EmitCallPropGet(typeof(AThreadState), nameof(AThreadState.Core)); @@ -181,7 +181,7 @@ namespace ChocolArm64.Instruction context.EmitCall(typeof(AMemory), name); } - private static void EmitBarrier(AilEmitterCtx context) + private static void EmitBarrier(ILEmitterCtx context) { //Note: This barrier is most likely not necessary, and probably //doesn't make any difference since we need to do a ton of stuff diff --git a/ChocolArm64/Instruction/AInstEmitMemoryHelper.cs b/ChocolArm64/Instruction/InstEmitMemoryHelper.cs similarity index 85% rename from ChocolArm64/Instruction/AInstEmitMemoryHelper.cs rename to ChocolArm64/Instruction/InstEmitMemoryHelper.cs index c43d4807d5..fba0a0a119 100644 --- a/ChocolArm64/Instruction/AInstEmitMemoryHelper.cs +++ b/ChocolArm64/Instruction/InstEmitMemoryHelper.cs @@ -6,7 +6,7 @@ using System.Reflection.Emit; namespace ChocolArm64.Instruction { - static class AInstEmitMemoryHelper + static class InstEmitMemoryHelper { private enum Extension { @@ -15,22 +15,22 @@ namespace ChocolArm64.Instruction Sx64 } - public static void EmitReadZxCall(AilEmitterCtx context, int size) + public static void EmitReadZxCall(ILEmitterCtx context, int size) { EmitReadCall(context, Extension.Zx, size); } - public static void EmitReadSx32Call(AilEmitterCtx context, int size) + public static void EmitReadSx32Call(ILEmitterCtx context, int size) { EmitReadCall(context, Extension.Sx32, size); } - public static void EmitReadSx64Call(AilEmitterCtx context, int size) + public static void EmitReadSx64Call(ILEmitterCtx context, int size) { EmitReadCall(context, Extension.Sx64, size); } - private static void EmitReadCall(AilEmitterCtx context, Extension ext, int size) + private static void EmitReadCall(ILEmitterCtx context, Extension ext, int size) { bool isSimd = GetIsSimd(context); @@ -87,7 +87,7 @@ namespace ChocolArm64.Instruction } } - public static void EmitWriteCall(AilEmitterCtx context, int size) + public static void EmitWriteCall(ILEmitterCtx context, int size) { bool isSimd = GetIsSimd(context); @@ -128,11 +128,11 @@ namespace ChocolArm64.Instruction context.EmitCall(typeof(AMemory), name); } - private static bool GetIsSimd(AilEmitterCtx context) + private static bool GetIsSimd(ILEmitterCtx context) { - return context.CurrOp is IaOpCodeSimd && - !(context.CurrOp is AOpCodeSimdMemMs || - context.CurrOp is AOpCodeSimdMemSs); + return context.CurrOp is IOpCodeSimd && + !(context.CurrOp is OpCodeSimdMemMs || + context.CurrOp is OpCodeSimdMemSs); } } } \ No newline at end of file diff --git a/ChocolArm64/Instruction/AInstEmitMove.cs b/ChocolArm64/Instruction/InstEmitMove.cs similarity index 62% rename from ChocolArm64/Instruction/AInstEmitMove.cs rename to ChocolArm64/Instruction/InstEmitMove.cs index af734d4937..1fe70f2a7b 100644 --- a/ChocolArm64/Instruction/AInstEmitMove.cs +++ b/ChocolArm64/Instruction/InstEmitMove.cs @@ -4,11 +4,11 @@ using System.Reflection.Emit; namespace ChocolArm64.Instruction { - static partial class AInstEmit + static partial class InstEmit { - public static void Movk(AilEmitterCtx context) + public static void Movk(ILEmitterCtx context) { - AOpCodeMov op = (AOpCodeMov)context.CurrOp; + OpCodeMov op = (OpCodeMov)context.CurrOp; context.EmitLdintzr(op.Rd); context.EmitLdc_I(~(0xffffL << op.Pos)); @@ -22,17 +22,17 @@ namespace ChocolArm64.Instruction context.EmitStintzr(op.Rd); } - public static void Movn(AilEmitterCtx context) + public static void Movn(ILEmitterCtx context) { - AOpCodeMov op = (AOpCodeMov)context.CurrOp; + OpCodeMov op = (OpCodeMov)context.CurrOp; context.EmitLdc_I(~op.Imm); context.EmitStintzr(op.Rd); } - public static void Movz(AilEmitterCtx context) + public static void Movz(ILEmitterCtx context) { - AOpCodeMov op = (AOpCodeMov)context.CurrOp; + OpCodeMov op = (OpCodeMov)context.CurrOp; context.EmitLdc_I(op.Imm); context.EmitStintzr(op.Rd); diff --git a/ChocolArm64/Instruction/InstEmitMul.cs b/ChocolArm64/Instruction/InstEmitMul.cs new file mode 100644 index 0000000000..cfbb53f2a8 --- /dev/null +++ b/ChocolArm64/Instruction/InstEmitMul.cs @@ -0,0 +1,80 @@ +using ChocolArm64.Decoder; +using ChocolArm64.Translation; +using System.Reflection.Emit; + +namespace ChocolArm64.Instruction +{ + static partial class InstEmit + { + public static void Madd(ILEmitterCtx context) => EmitMul(context, OpCodes.Add); + public static void Msub(ILEmitterCtx context) => EmitMul(context, OpCodes.Sub); + + private static void EmitMul(ILEmitterCtx context, OpCode ilOp) + { + OpCodeMul op = (OpCodeMul)context.CurrOp; + + context.EmitLdintzr(op.Ra); + context.EmitLdintzr(op.Rn); + context.EmitLdintzr(op.Rm); + + context.Emit(OpCodes.Mul); + context.Emit(ilOp); + + context.EmitStintzr(op.Rd); + } + + public static void Smaddl(ILEmitterCtx context) => EmitMull(context, OpCodes.Add, true); + public static void Smsubl(ILEmitterCtx context) => EmitMull(context, OpCodes.Sub, true); + public static void Umaddl(ILEmitterCtx context) => EmitMull(context, OpCodes.Add, false); + public static void Umsubl(ILEmitterCtx context) => EmitMull(context, OpCodes.Sub, false); + + private static void EmitMull(ILEmitterCtx context, OpCode addSubOp, bool signed) + { + OpCodeMul op = (OpCodeMul)context.CurrOp; + + OpCode castOp = signed + ? OpCodes.Conv_I8 + : OpCodes.Conv_U8; + + context.EmitLdintzr(op.Ra); + context.EmitLdintzr(op.Rn); + + context.Emit(OpCodes.Conv_I4); + context.Emit(castOp); + + context.EmitLdintzr(op.Rm); + + context.Emit(OpCodes.Conv_I4); + context.Emit(castOp); + context.Emit(OpCodes.Mul); + + context.Emit(addSubOp); + + context.EmitStintzr(op.Rd); + } + + public static void Smulh(ILEmitterCtx context) + { + OpCodeMul op = (OpCodeMul)context.CurrOp; + + context.EmitLdintzr(op.Rn); + context.EmitLdintzr(op.Rm); + + SoftFallback.EmitCall(context, nameof(SoftFallback.SMulHi128)); + + context.EmitStintzr(op.Rd); + } + + public static void Umulh(ILEmitterCtx context) + { + OpCodeMul op = (OpCodeMul)context.CurrOp; + + context.EmitLdintzr(op.Rn); + context.EmitLdintzr(op.Rm); + + SoftFallback.EmitCall(context, nameof(SoftFallback.UMulHi128)); + + context.EmitStintzr(op.Rd); + } + } +} \ No newline at end of file diff --git a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs b/ChocolArm64/Instruction/InstEmitSimdArithmetic.cs similarity index 78% rename from ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs rename to ChocolArm64/Instruction/InstEmitSimdArithmetic.cs index e4c8c89e79..e2af283436 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs +++ b/ChocolArm64/Instruction/InstEmitSimdArithmetic.cs @@ -13,26 +13,26 @@ using static ChocolArm64.Instruction.AInstEmitSimdHelper; namespace ChocolArm64.Instruction { - static partial class AInstEmit + static partial class InstEmit { - public static void Abs_S(AilEmitterCtx context) + public static void Abs_S(ILEmitterCtx context) { EmitScalarUnaryOpSx(context, () => EmitAbs(context)); } - public static void Abs_V(AilEmitterCtx context) + public static void Abs_V(ILEmitterCtx context) { EmitVectorUnaryOpSx(context, () => EmitAbs(context)); } - public static void Add_S(AilEmitterCtx context) + public static void Add_S(ILEmitterCtx context) { EmitScalarBinaryOpZx(context, () => context.Emit(OpCodes.Add)); } - public static void Add_V(AilEmitterCtx context) + public static void Add_V(ILEmitterCtx context) { - if (AOptimizations.UseSse2) + if (Optimizations.UseSse2) { EmitSse2Op(context, nameof(Sse2.Add)); } @@ -42,14 +42,14 @@ namespace ChocolArm64.Instruction } } - public static void Addhn_V(AilEmitterCtx context) + public static void Addhn_V(ILEmitterCtx context) { EmitHighNarrow(context, () => context.Emit(OpCodes.Add), round: false); } - public static void Addp_S(AilEmitterCtx context) + public static void Addp_S(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; EmitVectorExtractZx(context, op.Rn, 0, op.Size); EmitVectorExtractZx(context, op.Rn, 1, op.Size); @@ -59,14 +59,14 @@ namespace ChocolArm64.Instruction EmitScalarSet(context, op.Rd, op.Size); } - public static void Addp_V(AilEmitterCtx context) + public static void Addp_V(ILEmitterCtx context) { EmitVectorPairwiseOpZx(context, () => context.Emit(OpCodes.Add)); } - public static void Addv_V(AilEmitterCtx context) + public static void Addv_V(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int bytes = op.GetBitsCount() >> 3; int elems = bytes >> op.Size; @@ -83,9 +83,9 @@ namespace ChocolArm64.Instruction EmitScalarSet(context, op.Rd, op.Size); } - public static void Cls_V(AilEmitterCtx context) + public static void Cls_V(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int bytes = op.GetBitsCount() >> 3; int elems = bytes >> op.Size; @@ -98,20 +98,20 @@ namespace ChocolArm64.Instruction context.EmitLdc_I4(eSize); - ASoftFallback.EmitCall(context, nameof(ASoftFallback.CountLeadingSigns)); + SoftFallback.EmitCall(context, nameof(SoftFallback.CountLeadingSigns)); EmitVectorInsert(context, op.Rd, index, op.Size); } - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - public static void Clz_V(AilEmitterCtx context) + public static void Clz_V(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int bytes = op.GetBitsCount() >> 3; int elems = bytes >> op.Size; @@ -134,23 +134,23 @@ namespace ChocolArm64.Instruction { context.EmitLdc_I4(eSize); - ASoftFallback.EmitCall(context, nameof(ASoftFallback.CountLeadingZeros)); + SoftFallback.EmitCall(context, nameof(SoftFallback.CountLeadingZeros)); } EmitVectorInsert(context, op.Rd, index, op.Size); } - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - public static void Cnt_V(AilEmitterCtx context) + public static void Cnt_V(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; - int elems = op.RegisterSize == ARegisterSize.Simd128 ? 16 : 8; + int elems = op.RegisterSize == RegisterSize.Simd128 ? 16 : 8; for (int index = 0; index < elems; index++) { @@ -162,19 +162,19 @@ namespace ChocolArm64.Instruction } else { - ASoftFallback.EmitCall(context, nameof(ASoftFallback.CountSetBits8)); + SoftFallback.EmitCall(context, nameof(SoftFallback.CountSetBits8)); } EmitVectorInsert(context, op.Rd, index, 0); } - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - public static void Fabd_S(AilEmitterCtx context) + public static void Fabd_S(ILEmitterCtx context) { EmitScalarBinaryOpF(context, () => { @@ -184,7 +184,7 @@ namespace ChocolArm64.Instruction }); } - public static void Fabs_S(AilEmitterCtx context) + public static void Fabs_S(ILEmitterCtx context) { EmitScalarUnaryOpF(context, () => { @@ -192,7 +192,7 @@ namespace ChocolArm64.Instruction }); } - public static void Fabs_V(AilEmitterCtx context) + public static void Fabs_V(ILEmitterCtx context) { EmitVectorUnaryOpF(context, () => { @@ -200,10 +200,10 @@ namespace ChocolArm64.Instruction }); } - public static void Fadd_S(AilEmitterCtx context) + public static void Fadd_S(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse + && Optimizations.UseSse2) { EmitScalarSseOrSse2OpF(context, nameof(Sse.AddScalar)); } @@ -216,10 +216,10 @@ namespace ChocolArm64.Instruction } } - public static void Fadd_V(AilEmitterCtx context) + public static void Fadd_V(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse + && Optimizations.UseSse2) { EmitVectorSseOrSse2OpF(context, nameof(Sse.Add)); } @@ -232,9 +232,9 @@ namespace ChocolArm64.Instruction } } - public static void Faddp_S(AilEmitterCtx context) + public static void Faddp_S(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int sizeF = op.Size & 1; @@ -246,15 +246,15 @@ namespace ChocolArm64.Instruction EmitScalarSetF(context, op.Rd, sizeF); } - public static void Faddp_V(AilEmitterCtx context) + public static void Faddp_V(ILEmitterCtx context) { EmitVectorPairwiseOpF(context, () => context.Emit(OpCodes.Add)); } - public static void Fdiv_S(AilEmitterCtx context) + public static void Fdiv_S(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse + && Optimizations.UseSse2) { EmitScalarSseOrSse2OpF(context, nameof(Sse.DivideScalar)); } @@ -267,10 +267,10 @@ namespace ChocolArm64.Instruction } } - public static void Fdiv_V(AilEmitterCtx context) + public static void Fdiv_V(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse + && Optimizations.UseSse2) { EmitVectorSseOrSse2OpF(context, nameof(Sse.Divide)); } @@ -283,11 +283,11 @@ namespace ChocolArm64.Instruction } } - public static void Fmadd_S(AilEmitterCtx context) + public static void Fmadd_S(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse2) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; if (op.Size == 0) { @@ -329,10 +329,10 @@ namespace ChocolArm64.Instruction } } - public static void Fmax_S(AilEmitterCtx context) + public static void Fmax_S(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse + && Optimizations.UseSse2) { EmitScalarSseOrSse2OpF(context, nameof(Sse.MaxScalar)); } @@ -345,10 +345,10 @@ namespace ChocolArm64.Instruction } } - public static void Fmax_V(AilEmitterCtx context) + public static void Fmax_V(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse + && Optimizations.UseSse2) { EmitVectorSseOrSse2OpF(context, nameof(Sse.Max)); } @@ -361,7 +361,7 @@ namespace ChocolArm64.Instruction } } - public static void Fmaxnm_S(AilEmitterCtx context) + public static void Fmaxnm_S(ILEmitterCtx context) { EmitScalarBinaryOpF(context, () => { @@ -369,7 +369,7 @@ namespace ChocolArm64.Instruction }); } - public static void Fmaxnm_V(AilEmitterCtx context) + public static void Fmaxnm_V(ILEmitterCtx context) { EmitVectorBinaryOpF(context, () => { @@ -377,7 +377,7 @@ namespace ChocolArm64.Instruction }); } - public static void Fmaxp_V(AilEmitterCtx context) + public static void Fmaxp_V(ILEmitterCtx context) { EmitVectorPairwiseOpF(context, () => { @@ -385,10 +385,10 @@ namespace ChocolArm64.Instruction }); } - public static void Fmin_S(AilEmitterCtx context) + public static void Fmin_S(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse + && Optimizations.UseSse2) { EmitScalarSseOrSse2OpF(context, nameof(Sse.MinScalar)); } @@ -401,10 +401,10 @@ namespace ChocolArm64.Instruction } } - public static void Fmin_V(AilEmitterCtx context) + public static void Fmin_V(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse + && Optimizations.UseSse2) { EmitVectorSseOrSse2OpF(context, nameof(Sse.Min)); } @@ -417,7 +417,7 @@ namespace ChocolArm64.Instruction } } - public static void Fminnm_S(AilEmitterCtx context) + public static void Fminnm_S(ILEmitterCtx context) { EmitScalarBinaryOpF(context, () => { @@ -425,7 +425,7 @@ namespace ChocolArm64.Instruction }); } - public static void Fminnm_V(AilEmitterCtx context) + public static void Fminnm_V(ILEmitterCtx context) { EmitVectorBinaryOpF(context, () => { @@ -433,7 +433,7 @@ namespace ChocolArm64.Instruction }); } - public static void Fminp_V(AilEmitterCtx context) + public static void Fminp_V(ILEmitterCtx context) { EmitVectorPairwiseOpF(context, () => { @@ -441,7 +441,7 @@ namespace ChocolArm64.Instruction }); } - public static void Fmla_Se(AilEmitterCtx context) + public static void Fmla_Se(ILEmitterCtx context) { EmitScalarTernaryOpByElemF(context, () => { @@ -450,7 +450,7 @@ namespace ChocolArm64.Instruction }); } - public static void Fmla_V(AilEmitterCtx context) + public static void Fmla_V(ILEmitterCtx context) { EmitVectorTernaryOpF(context, () => { @@ -459,7 +459,7 @@ namespace ChocolArm64.Instruction }); } - public static void Fmla_Ve(AilEmitterCtx context) + public static void Fmla_Ve(ILEmitterCtx context) { EmitVectorTernaryOpByElemF(context, () => { @@ -468,7 +468,7 @@ namespace ChocolArm64.Instruction }); } - public static void Fmls_Se(AilEmitterCtx context) + public static void Fmls_Se(ILEmitterCtx context) { EmitScalarTernaryOpByElemF(context, () => { @@ -477,7 +477,7 @@ namespace ChocolArm64.Instruction }); } - public static void Fmls_V(AilEmitterCtx context) + public static void Fmls_V(ILEmitterCtx context) { EmitVectorTernaryOpF(context, () => { @@ -486,7 +486,7 @@ namespace ChocolArm64.Instruction }); } - public static void Fmls_Ve(AilEmitterCtx context) + public static void Fmls_Ve(ILEmitterCtx context) { EmitVectorTernaryOpByElemF(context, () => { @@ -495,11 +495,11 @@ namespace ChocolArm64.Instruction }); } - public static void Fmsub_S(AilEmitterCtx context) + public static void Fmsub_S(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse2) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; if (op.Size == 0) { @@ -541,10 +541,10 @@ namespace ChocolArm64.Instruction } } - public static void Fmul_S(AilEmitterCtx context) + public static void Fmul_S(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse + && Optimizations.UseSse2) { EmitScalarSseOrSse2OpF(context, nameof(Sse.MultiplyScalar)); } @@ -557,15 +557,15 @@ namespace ChocolArm64.Instruction } } - public static void Fmul_Se(AilEmitterCtx context) + public static void Fmul_Se(ILEmitterCtx context) { EmitScalarBinaryOpByElemF(context, () => context.Emit(OpCodes.Mul)); } - public static void Fmul_V(AilEmitterCtx context) + public static void Fmul_V(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse + && Optimizations.UseSse2) { EmitVectorSseOrSse2OpF(context, nameof(Sse.Multiply)); } @@ -578,12 +578,12 @@ namespace ChocolArm64.Instruction } } - public static void Fmul_Ve(AilEmitterCtx context) + public static void Fmul_Ve(ILEmitterCtx context) { EmitVectorBinaryOpByElemF(context, () => context.Emit(OpCodes.Mul)); } - public static void Fmulx_S(AilEmitterCtx context) + public static void Fmulx_S(ILEmitterCtx context) { EmitScalarBinaryOpF(context, () => { @@ -591,7 +591,7 @@ namespace ChocolArm64.Instruction }); } - public static void Fmulx_Se(AilEmitterCtx context) + public static void Fmulx_Se(ILEmitterCtx context) { EmitScalarBinaryOpByElemF(context, () => { @@ -599,7 +599,7 @@ namespace ChocolArm64.Instruction }); } - public static void Fmulx_V(AilEmitterCtx context) + public static void Fmulx_V(ILEmitterCtx context) { EmitVectorBinaryOpF(context, () => { @@ -607,7 +607,7 @@ namespace ChocolArm64.Instruction }); } - public static void Fmulx_Ve(AilEmitterCtx context) + public static void Fmulx_Ve(ILEmitterCtx context) { EmitVectorBinaryOpByElemF(context, () => { @@ -615,19 +615,19 @@ namespace ChocolArm64.Instruction }); } - public static void Fneg_S(AilEmitterCtx context) + public static void Fneg_S(ILEmitterCtx context) { EmitScalarUnaryOpF(context, () => context.Emit(OpCodes.Neg)); } - public static void Fneg_V(AilEmitterCtx context) + public static void Fneg_V(ILEmitterCtx context) { EmitVectorUnaryOpF(context, () => context.Emit(OpCodes.Neg)); } - public static void Fnmadd_S(AilEmitterCtx context) + public static void Fnmadd_S(ILEmitterCtx context) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; int sizeF = op.Size & 1; @@ -646,9 +646,9 @@ namespace ChocolArm64.Instruction EmitScalarSetF(context, op.Rd, sizeF); } - public static void Fnmsub_S(AilEmitterCtx context) + public static void Fnmsub_S(ILEmitterCtx context) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; int sizeF = op.Size & 1; @@ -664,7 +664,7 @@ namespace ChocolArm64.Instruction EmitScalarSetF(context, op.Rd, sizeF); } - public static void Fnmul_S(AilEmitterCtx context) + public static void Fnmul_S(ILEmitterCtx context) { EmitScalarBinaryOpF(context, () => { @@ -673,27 +673,27 @@ namespace ChocolArm64.Instruction }); } - public static void Frecpe_S(AilEmitterCtx context) + public static void Frecpe_S(ILEmitterCtx context) { EmitScalarUnaryOpF(context, () => { - EmitUnarySoftFloatCall(context, nameof(ASoftFloat.RecipEstimate)); + EmitUnarySoftFloatCall(context, nameof(SoftFloat.RecipEstimate)); }); } - public static void Frecpe_V(AilEmitterCtx context) + public static void Frecpe_V(ILEmitterCtx context) { EmitVectorUnaryOpF(context, () => { - EmitUnarySoftFloatCall(context, nameof(ASoftFloat.RecipEstimate)); + EmitUnarySoftFloatCall(context, nameof(SoftFloat.RecipEstimate)); }); } - public static void Frecps_S(AilEmitterCtx context) + public static void Frecps_S(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse2) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; int sizeF = op.Size & 1; @@ -743,11 +743,11 @@ namespace ChocolArm64.Instruction } } - public static void Frecps_V(AilEmitterCtx context) + public static void Frecps_V(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse2) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; int sizeF = op.Size & 1; @@ -767,7 +767,7 @@ namespace ChocolArm64.Instruction context.EmitStvec(op.Rd); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -798,7 +798,7 @@ namespace ChocolArm64.Instruction } } - public static void Frecpx_S(AilEmitterCtx context) + public static void Frecpx_S(ILEmitterCtx context) { EmitScalarUnaryOpF(context, () => { @@ -806,9 +806,9 @@ namespace ChocolArm64.Instruction }); } - public static void Frinta_S(AilEmitterCtx context) + public static void Frinta_S(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; EmitVectorExtractF(context, op.Rn, 0, op.Size); @@ -817,7 +817,7 @@ namespace ChocolArm64.Instruction EmitScalarSetF(context, op.Rd, op.Size); } - public static void Frinta_V(AilEmitterCtx context) + public static void Frinta_V(ILEmitterCtx context) { EmitVectorUnaryOpF(context, () => { @@ -825,21 +825,21 @@ namespace ChocolArm64.Instruction }); } - public static void Frinti_S(AilEmitterCtx context) + public static void Frinti_S(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; EmitScalarUnaryOpF(context, () => { - context.EmitLdarg(ATranslatedSub.StateArgIdx); + context.EmitLdarg(TranslatedSub.StateArgIdx); if (op.Size == 0) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.RoundF)); + VectorHelper.EmitCall(context, nameof(VectorHelper.RoundF)); } else if (op.Size == 1) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.Round)); + VectorHelper.EmitCall(context, nameof(VectorHelper.Round)); } else { @@ -848,23 +848,23 @@ namespace ChocolArm64.Instruction }); } - public static void Frinti_V(AilEmitterCtx context) + public static void Frinti_V(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int sizeF = op.Size & 1; EmitVectorUnaryOpF(context, () => { - context.EmitLdarg(ATranslatedSub.StateArgIdx); + context.EmitLdarg(TranslatedSub.StateArgIdx); if (sizeF == 0) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.RoundF)); + VectorHelper.EmitCall(context, nameof(VectorHelper.RoundF)); } else if (sizeF == 1) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.Round)); + VectorHelper.EmitCall(context, nameof(VectorHelper.Round)); } else { @@ -873,7 +873,7 @@ namespace ChocolArm64.Instruction }); } - public static void Frintm_S(AilEmitterCtx context) + public static void Frintm_S(ILEmitterCtx context) { EmitScalarUnaryOpF(context, () => { @@ -881,7 +881,7 @@ namespace ChocolArm64.Instruction }); } - public static void Frintm_V(AilEmitterCtx context) + public static void Frintm_V(ILEmitterCtx context) { EmitVectorUnaryOpF(context, () => { @@ -889,9 +889,9 @@ namespace ChocolArm64.Instruction }); } - public static void Frintn_S(AilEmitterCtx context) + public static void Frintn_S(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; EmitVectorExtractF(context, op.Rn, 0, op.Size); @@ -900,7 +900,7 @@ namespace ChocolArm64.Instruction EmitScalarSetF(context, op.Rd, op.Size); } - public static void Frintn_V(AilEmitterCtx context) + public static void Frintn_V(ILEmitterCtx context) { EmitVectorUnaryOpF(context, () => { @@ -908,7 +908,7 @@ namespace ChocolArm64.Instruction }); } - public static void Frintp_S(AilEmitterCtx context) + public static void Frintp_S(ILEmitterCtx context) { EmitScalarUnaryOpF(context, () => { @@ -916,7 +916,7 @@ namespace ChocolArm64.Instruction }); } - public static void Frintp_V(AilEmitterCtx context) + public static void Frintp_V(ILEmitterCtx context) { EmitVectorUnaryOpF(context, () => { @@ -924,21 +924,21 @@ namespace ChocolArm64.Instruction }); } - public static void Frintx_S(AilEmitterCtx context) + public static void Frintx_S(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; EmitScalarUnaryOpF(context, () => { - context.EmitLdarg(ATranslatedSub.StateArgIdx); + context.EmitLdarg(TranslatedSub.StateArgIdx); if (op.Size == 0) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.RoundF)); + VectorHelper.EmitCall(context, nameof(VectorHelper.RoundF)); } else if (op.Size == 1) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.Round)); + VectorHelper.EmitCall(context, nameof(VectorHelper.Round)); } else { @@ -947,21 +947,21 @@ namespace ChocolArm64.Instruction }); } - public static void Frintx_V(AilEmitterCtx context) + public static void Frintx_V(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; EmitVectorUnaryOpF(context, () => { - context.EmitLdarg(ATranslatedSub.StateArgIdx); + context.EmitLdarg(TranslatedSub.StateArgIdx); if (op.Size == 0) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.RoundF)); + VectorHelper.EmitCall(context, nameof(VectorHelper.RoundF)); } else if (op.Size == 1) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.Round)); + VectorHelper.EmitCall(context, nameof(VectorHelper.Round)); } else { @@ -970,27 +970,27 @@ namespace ChocolArm64.Instruction }); } - public static void Frsqrte_S(AilEmitterCtx context) + public static void Frsqrte_S(ILEmitterCtx context) { EmitScalarUnaryOpF(context, () => { - EmitUnarySoftFloatCall(context, nameof(ASoftFloat.InvSqrtEstimate)); + EmitUnarySoftFloatCall(context, nameof(SoftFloat.InvSqrtEstimate)); }); } - public static void Frsqrte_V(AilEmitterCtx context) + public static void Frsqrte_V(ILEmitterCtx context) { EmitVectorUnaryOpF(context, () => { - EmitUnarySoftFloatCall(context, nameof(ASoftFloat.InvSqrtEstimate)); + EmitUnarySoftFloatCall(context, nameof(SoftFloat.InvSqrtEstimate)); }); } - public static void Frsqrts_S(AilEmitterCtx context) + public static void Frsqrts_S(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse2) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; int sizeF = op.Size & 1; @@ -1048,11 +1048,11 @@ namespace ChocolArm64.Instruction } } - public static void Frsqrts_V(AilEmitterCtx context) + public static void Frsqrts_V(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse2) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; int sizeF = op.Size & 1; @@ -1076,7 +1076,7 @@ namespace ChocolArm64.Instruction context.EmitStvec(op.Rd); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -1111,10 +1111,10 @@ namespace ChocolArm64.Instruction } } - public static void Fsqrt_S(AilEmitterCtx context) + public static void Fsqrt_S(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse + && Optimizations.UseSse2) { EmitScalarSseOrSse2OpF(context, nameof(Sse.SqrtScalar)); } @@ -1127,10 +1127,10 @@ namespace ChocolArm64.Instruction } } - public static void Fsqrt_V(AilEmitterCtx context) + public static void Fsqrt_V(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse + && Optimizations.UseSse2) { EmitVectorSseOrSse2OpF(context, nameof(Sse.Sqrt)); } @@ -1143,10 +1143,10 @@ namespace ChocolArm64.Instruction } } - public static void Fsub_S(AilEmitterCtx context) + public static void Fsub_S(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse + && Optimizations.UseSse2) { EmitScalarSseOrSse2OpF(context, nameof(Sse.SubtractScalar)); } @@ -1159,10 +1159,10 @@ namespace ChocolArm64.Instruction } } - public static void Fsub_V(AilEmitterCtx context) + public static void Fsub_V(ILEmitterCtx context) { - if (AOptimizations.FastFP && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (Optimizations.FastFP && Optimizations.UseSse + && Optimizations.UseSse2) { EmitVectorSseOrSse2OpF(context, nameof(Sse.Subtract)); } @@ -1175,7 +1175,7 @@ namespace ChocolArm64.Instruction } } - public static void Mla_V(AilEmitterCtx context) + public static void Mla_V(ILEmitterCtx context) { EmitVectorTernaryOpZx(context, () => { @@ -1184,7 +1184,7 @@ namespace ChocolArm64.Instruction }); } - public static void Mla_Ve(AilEmitterCtx context) + public static void Mla_Ve(ILEmitterCtx context) { EmitVectorTernaryOpByElemZx(context, () => { @@ -1193,7 +1193,7 @@ namespace ChocolArm64.Instruction }); } - public static void Mls_V(AilEmitterCtx context) + public static void Mls_V(ILEmitterCtx context) { EmitVectorTernaryOpZx(context, () => { @@ -1202,7 +1202,7 @@ namespace ChocolArm64.Instruction }); } - public static void Mls_Ve(AilEmitterCtx context) + public static void Mls_Ve(ILEmitterCtx context) { EmitVectorTernaryOpByElemZx(context, () => { @@ -1211,37 +1211,37 @@ namespace ChocolArm64.Instruction }); } - public static void Mul_V(AilEmitterCtx context) + public static void Mul_V(ILEmitterCtx context) { EmitVectorBinaryOpZx(context, () => context.Emit(OpCodes.Mul)); } - public static void Mul_Ve(AilEmitterCtx context) + public static void Mul_Ve(ILEmitterCtx context) { EmitVectorBinaryOpByElemZx(context, () => context.Emit(OpCodes.Mul)); } - public static void Neg_S(AilEmitterCtx context) + public static void Neg_S(ILEmitterCtx context) { EmitScalarUnaryOpSx(context, () => context.Emit(OpCodes.Neg)); } - public static void Neg_V(AilEmitterCtx context) + public static void Neg_V(ILEmitterCtx context) { EmitVectorUnaryOpSx(context, () => context.Emit(OpCodes.Neg)); } - public static void Raddhn_V(AilEmitterCtx context) + public static void Raddhn_V(ILEmitterCtx context) { EmitHighNarrow(context, () => context.Emit(OpCodes.Add), round: true); } - public static void Rsubhn_V(AilEmitterCtx context) + public static void Rsubhn_V(ILEmitterCtx context) { EmitHighNarrow(context, () => context.Emit(OpCodes.Sub), round: true); } - public static void Saba_V(AilEmitterCtx context) + public static void Saba_V(ILEmitterCtx context) { EmitVectorTernaryOpSx(context, () => { @@ -1252,7 +1252,7 @@ namespace ChocolArm64.Instruction }); } - public static void Sabal_V(AilEmitterCtx context) + public static void Sabal_V(ILEmitterCtx context) { EmitVectorWidenRnRmTernaryOpSx(context, () => { @@ -1263,7 +1263,7 @@ namespace ChocolArm64.Instruction }); } - public static void Sabd_V(AilEmitterCtx context) + public static void Sabd_V(ILEmitterCtx context) { EmitVectorBinaryOpSx(context, () => { @@ -1272,7 +1272,7 @@ namespace ChocolArm64.Instruction }); } - public static void Sabdl_V(AilEmitterCtx context) + public static void Sabdl_V(ILEmitterCtx context) { EmitVectorWidenRnRmBinaryOpSx(context, () => { @@ -1281,16 +1281,16 @@ namespace ChocolArm64.Instruction }); } - public static void Sadalp_V(AilEmitterCtx context) + public static void Sadalp_V(ILEmitterCtx context) { EmitAddLongPairwise(context, signed: true, accumulate: true); } - public static void Saddl_V(AilEmitterCtx context) + public static void Saddl_V(ILEmitterCtx context) { - if (AOptimizations.UseSse41) + if (Optimizations.UseSse41) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; Type[] typesSrl = new Type[] { VectorIntTypesPerSizeLog2[op.Size], typeof(byte) }; Type[] typesCvt = new Type[] { VectorIntTypesPerSizeLog2[op.Size] }; @@ -1301,7 +1301,7 @@ namespace ChocolArm64.Instruction nameof(Sse41.ConvertToVector128Int32), nameof(Sse41.ConvertToVector128Int64) }; - int numBytes = op.RegisterSize == ARegisterSize.Simd128 ? 8 : 0; + int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0; EmitLdvecWithSignedCast(context, op.Rn, op.Size); @@ -1327,21 +1327,21 @@ namespace ChocolArm64.Instruction } } - public static void Saddlp_V(AilEmitterCtx context) + public static void Saddlp_V(ILEmitterCtx context) { EmitAddLongPairwise(context, signed: true, accumulate: false); } - public static void Saddw_V(AilEmitterCtx context) + public static void Saddw_V(ILEmitterCtx context) { EmitVectorWidenRmBinaryOpSx(context, () => context.Emit(OpCodes.Add)); } - public static void Shadd_V(AilEmitterCtx context) + public static void Shadd_V(ILEmitterCtx context) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; - if (AOptimizations.UseSse2 && op.Size > 0) + if (Optimizations.UseSse2 && op.Size > 0) { Type[] typesSra = new Type[] { VectorIntTypesPerSizeLog2[op.Size], typeof(byte) }; Type[] typesAndXorAdd = new Type[] { VectorIntTypesPerSizeLog2[op.Size], VectorIntTypesPerSizeLog2[op.Size] }; @@ -1370,7 +1370,7 @@ namespace ChocolArm64.Instruction EmitStvecWithSignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -1387,11 +1387,11 @@ namespace ChocolArm64.Instruction } } - public static void Shsub_V(AilEmitterCtx context) + public static void Shsub_V(ILEmitterCtx context) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; - if (AOptimizations.UseSse2 && op.Size < 2) + if (Optimizations.UseSse2 && op.Size < 2) { Type[] typesSav = new Type[] { IntTypesPerSizeLog2[op.Size] }; Type[] typesAddSub = new Type[] { VectorIntTypesPerSizeLog2 [op.Size], VectorIntTypesPerSizeLog2 [op.Size] }; @@ -1420,7 +1420,7 @@ namespace ChocolArm64.Instruction EmitStvecWithSignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -1437,7 +1437,7 @@ namespace ChocolArm64.Instruction } } - public static void Smax_V(AilEmitterCtx context) + public static void Smax_V(ILEmitterCtx context) { Type[] types = new Type[] { typeof(long), typeof(long) }; @@ -1446,7 +1446,7 @@ namespace ChocolArm64.Instruction EmitVectorBinaryOpSx(context, () => context.EmitCall(mthdInfo)); } - public static void Smaxp_V(AilEmitterCtx context) + public static void Smaxp_V(ILEmitterCtx context) { Type[] types = new Type[] { typeof(long), typeof(long) }; @@ -1455,7 +1455,7 @@ namespace ChocolArm64.Instruction EmitVectorPairwiseOpSx(context, () => context.EmitCall(mthdInfo)); } - public static void Smin_V(AilEmitterCtx context) + public static void Smin_V(ILEmitterCtx context) { Type[] types = new Type[] { typeof(long), typeof(long) }; @@ -1464,7 +1464,7 @@ namespace ChocolArm64.Instruction EmitVectorBinaryOpSx(context, () => context.EmitCall(mthdInfo)); } - public static void Sminp_V(AilEmitterCtx context) + public static void Sminp_V(ILEmitterCtx context) { Type[] types = new Type[] { typeof(long), typeof(long) }; @@ -1473,11 +1473,11 @@ namespace ChocolArm64.Instruction EmitVectorPairwiseOpSx(context, () => context.EmitCall(mthdInfo)); } - public static void Smlal_V(AilEmitterCtx context) + public static void Smlal_V(ILEmitterCtx context) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; - if (AOptimizations.UseSse41 && op.Size < 2) + if (Optimizations.UseSse41 && op.Size < 2) { Type[] typesSrl = new Type[] { VectorIntTypesPerSizeLog2[op.Size], typeof(byte) }; Type[] typesCvt = new Type[] { VectorIntTypesPerSizeLog2[op.Size] }; @@ -1490,7 +1490,7 @@ namespace ChocolArm64.Instruction ? nameof(Sse41.ConvertToVector128Int16) : nameof(Sse41.ConvertToVector128Int32); - int numBytes = op.RegisterSize == ARegisterSize.Simd128 ? 8 : 0; + int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0; EmitLdvecWithSignedCast(context, op.Rd, op.Size + 1); @@ -1524,11 +1524,11 @@ namespace ChocolArm64.Instruction } } - public static void Smlsl_V(AilEmitterCtx context) + public static void Smlsl_V(ILEmitterCtx context) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; - if (AOptimizations.UseSse41 && op.Size < 2) + if (Optimizations.UseSse41 && op.Size < 2) { Type[] typesSrl = new Type[] { VectorIntTypesPerSizeLog2[op.Size], typeof(byte) }; Type[] typesCvt = new Type[] { VectorIntTypesPerSizeLog2[op.Size] }; @@ -1541,7 +1541,7 @@ namespace ChocolArm64.Instruction ? nameof(Sse41.ConvertToVector128Int16) : nameof(Sse41.ConvertToVector128Int32); - int numBytes = op.RegisterSize == ARegisterSize.Simd128 ? 8 : 0; + int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0; EmitLdvecWithSignedCast(context, op.Rd, op.Size + 1); @@ -1575,96 +1575,96 @@ namespace ChocolArm64.Instruction } } - public static void Smull_V(AilEmitterCtx context) + public static void Smull_V(ILEmitterCtx context) { EmitVectorWidenRnRmBinaryOpSx(context, () => context.Emit(OpCodes.Mul)); } - public static void Sqabs_S(AilEmitterCtx context) + public static void Sqabs_S(ILEmitterCtx context) { EmitScalarSaturatingUnaryOpSx(context, () => EmitAbs(context)); } - public static void Sqabs_V(AilEmitterCtx context) + public static void Sqabs_V(ILEmitterCtx context) { EmitVectorSaturatingUnaryOpSx(context, () => EmitAbs(context)); } - public static void Sqadd_S(AilEmitterCtx context) + public static void Sqadd_S(ILEmitterCtx context) { EmitScalarSaturatingBinaryOpSx(context, SaturatingFlags.Add); } - public static void Sqadd_V(AilEmitterCtx context) + public static void Sqadd_V(ILEmitterCtx context) { EmitVectorSaturatingBinaryOpSx(context, SaturatingFlags.Add); } - public static void Sqdmulh_S(AilEmitterCtx context) + public static void Sqdmulh_S(ILEmitterCtx context) { EmitSaturatingBinaryOp(context, () => EmitDoublingMultiplyHighHalf(context, round: false), SaturatingFlags.ScalarSx); } - public static void Sqdmulh_V(AilEmitterCtx context) + public static void Sqdmulh_V(ILEmitterCtx context) { EmitSaturatingBinaryOp(context, () => EmitDoublingMultiplyHighHalf(context, round: false), SaturatingFlags.VectorSx); } - public static void Sqneg_S(AilEmitterCtx context) + public static void Sqneg_S(ILEmitterCtx context) { EmitScalarSaturatingUnaryOpSx(context, () => context.Emit(OpCodes.Neg)); } - public static void Sqneg_V(AilEmitterCtx context) + public static void Sqneg_V(ILEmitterCtx context) { EmitVectorSaturatingUnaryOpSx(context, () => context.Emit(OpCodes.Neg)); } - public static void Sqrdmulh_S(AilEmitterCtx context) + public static void Sqrdmulh_S(ILEmitterCtx context) { EmitSaturatingBinaryOp(context, () => EmitDoublingMultiplyHighHalf(context, round: true), SaturatingFlags.ScalarSx); } - public static void Sqrdmulh_V(AilEmitterCtx context) + public static void Sqrdmulh_V(ILEmitterCtx context) { EmitSaturatingBinaryOp(context, () => EmitDoublingMultiplyHighHalf(context, round: true), SaturatingFlags.VectorSx); } - public static void Sqsub_S(AilEmitterCtx context) + public static void Sqsub_S(ILEmitterCtx context) { EmitScalarSaturatingBinaryOpSx(context, SaturatingFlags.Sub); } - public static void Sqsub_V(AilEmitterCtx context) + public static void Sqsub_V(ILEmitterCtx context) { EmitVectorSaturatingBinaryOpSx(context, SaturatingFlags.Sub); } - public static void Sqxtn_S(AilEmitterCtx context) + public static void Sqxtn_S(ILEmitterCtx context) { EmitSaturatingNarrowOp(context, SaturatingNarrowFlags.ScalarSxSx); } - public static void Sqxtn_V(AilEmitterCtx context) + public static void Sqxtn_V(ILEmitterCtx context) { EmitSaturatingNarrowOp(context, SaturatingNarrowFlags.VectorSxSx); } - public static void Sqxtun_S(AilEmitterCtx context) + public static void Sqxtun_S(ILEmitterCtx context) { EmitSaturatingNarrowOp(context, SaturatingNarrowFlags.ScalarSxZx); } - public static void Sqxtun_V(AilEmitterCtx context) + public static void Sqxtun_V(ILEmitterCtx context) { EmitSaturatingNarrowOp(context, SaturatingNarrowFlags.VectorSxZx); } - public static void Srhadd_V(AilEmitterCtx context) + public static void Srhadd_V(ILEmitterCtx context) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; - if (AOptimizations.UseSse2 && op.Size < 2) + if (Optimizations.UseSse2 && op.Size < 2) { Type[] typesSav = new Type[] { IntTypesPerSizeLog2[op.Size] }; Type[] typesSubAdd = new Type[] { VectorIntTypesPerSizeLog2 [op.Size], VectorIntTypesPerSizeLog2 [op.Size] }; @@ -1691,7 +1691,7 @@ namespace ChocolArm64.Instruction EmitStvecWithSignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -1711,11 +1711,11 @@ namespace ChocolArm64.Instruction } } - public static void Ssubl_V(AilEmitterCtx context) + public static void Ssubl_V(ILEmitterCtx context) { - if (AOptimizations.UseSse41) + if (Optimizations.UseSse41) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; Type[] typesSrl = new Type[] { VectorIntTypesPerSizeLog2[op.Size], typeof(byte) }; Type[] typesCvt = new Type[] { VectorIntTypesPerSizeLog2[op.Size] }; @@ -1726,7 +1726,7 @@ namespace ChocolArm64.Instruction nameof(Sse41.ConvertToVector128Int32), nameof(Sse41.ConvertToVector128Int64) }; - int numBytes = op.RegisterSize == ARegisterSize.Simd128 ? 8 : 0; + int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0; EmitLdvecWithSignedCast(context, op.Rn, op.Size); @@ -1752,19 +1752,19 @@ namespace ChocolArm64.Instruction } } - public static void Ssubw_V(AilEmitterCtx context) + public static void Ssubw_V(ILEmitterCtx context) { EmitVectorWidenRmBinaryOpSx(context, () => context.Emit(OpCodes.Sub)); } - public static void Sub_S(AilEmitterCtx context) + public static void Sub_S(ILEmitterCtx context) { EmitScalarBinaryOpZx(context, () => context.Emit(OpCodes.Sub)); } - public static void Sub_V(AilEmitterCtx context) + public static void Sub_V(ILEmitterCtx context) { - if (AOptimizations.UseSse2) + if (Optimizations.UseSse2) { EmitSse2Op(context, nameof(Sse2.Subtract)); } @@ -1774,22 +1774,22 @@ namespace ChocolArm64.Instruction } } - public static void Subhn_V(AilEmitterCtx context) + public static void Subhn_V(ILEmitterCtx context) { EmitHighNarrow(context, () => context.Emit(OpCodes.Sub), round: false); } - public static void Suqadd_S(AilEmitterCtx context) + public static void Suqadd_S(ILEmitterCtx context) { EmitScalarSaturatingBinaryOpSx(context, SaturatingFlags.Accumulate); } - public static void Suqadd_V(AilEmitterCtx context) + public static void Suqadd_V(ILEmitterCtx context) { EmitVectorSaturatingBinaryOpSx(context, SaturatingFlags.Accumulate); } - public static void Uaba_V(AilEmitterCtx context) + public static void Uaba_V(ILEmitterCtx context) { EmitVectorTernaryOpZx(context, () => { @@ -1800,7 +1800,7 @@ namespace ChocolArm64.Instruction }); } - public static void Uabal_V(AilEmitterCtx context) + public static void Uabal_V(ILEmitterCtx context) { EmitVectorWidenRnRmTernaryOpZx(context, () => { @@ -1811,7 +1811,7 @@ namespace ChocolArm64.Instruction }); } - public static void Uabd_V(AilEmitterCtx context) + public static void Uabd_V(ILEmitterCtx context) { EmitVectorBinaryOpZx(context, () => { @@ -1820,7 +1820,7 @@ namespace ChocolArm64.Instruction }); } - public static void Uabdl_V(AilEmitterCtx context) + public static void Uabdl_V(ILEmitterCtx context) { EmitVectorWidenRnRmBinaryOpZx(context, () => { @@ -1829,16 +1829,16 @@ namespace ChocolArm64.Instruction }); } - public static void Uadalp_V(AilEmitterCtx context) + public static void Uadalp_V(ILEmitterCtx context) { EmitAddLongPairwise(context, signed: false, accumulate: true); } - public static void Uaddl_V(AilEmitterCtx context) + public static void Uaddl_V(ILEmitterCtx context) { - if (AOptimizations.UseSse41) + if (Optimizations.UseSse41) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; Type[] typesSrl = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], typeof(byte) }; Type[] typesCvt = new Type[] { VectorUIntTypesPerSizeLog2[op.Size] }; @@ -1849,7 +1849,7 @@ namespace ChocolArm64.Instruction nameof(Sse41.ConvertToVector128Int32), nameof(Sse41.ConvertToVector128Int64) }; - int numBytes = op.RegisterSize == ARegisterSize.Simd128 ? 8 : 0; + int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0; EmitLdvecWithUnsignedCast(context, op.Rn, op.Size); @@ -1875,14 +1875,14 @@ namespace ChocolArm64.Instruction } } - public static void Uaddlp_V(AilEmitterCtx context) + public static void Uaddlp_V(ILEmitterCtx context) { EmitAddLongPairwise(context, signed: false, accumulate: false); } - public static void Uaddlv_V(AilEmitterCtx context) + public static void Uaddlv_V(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int bytes = op.GetBitsCount() >> 3; int elems = bytes >> op.Size; @@ -1899,16 +1899,16 @@ namespace ChocolArm64.Instruction EmitScalarSet(context, op.Rd, op.Size + 1); } - public static void Uaddw_V(AilEmitterCtx context) + public static void Uaddw_V(ILEmitterCtx context) { EmitVectorWidenRmBinaryOpZx(context, () => context.Emit(OpCodes.Add)); } - public static void Uhadd_V(AilEmitterCtx context) + public static void Uhadd_V(ILEmitterCtx context) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; - if (AOptimizations.UseSse2 && op.Size > 0) + if (Optimizations.UseSse2 && op.Size > 0) { Type[] typesSrl = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], typeof(byte) }; Type[] typesAndXorAdd = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], VectorUIntTypesPerSizeLog2[op.Size] }; @@ -1937,7 +1937,7 @@ namespace ChocolArm64.Instruction EmitStvecWithUnsignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -1954,11 +1954,11 @@ namespace ChocolArm64.Instruction } } - public static void Uhsub_V(AilEmitterCtx context) + public static void Uhsub_V(ILEmitterCtx context) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; - if (AOptimizations.UseSse2 && op.Size < 2) + if (Optimizations.UseSse2 && op.Size < 2) { Type[] typesAvgSub = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], VectorUIntTypesPerSizeLog2[op.Size] }; @@ -1973,7 +1973,7 @@ namespace ChocolArm64.Instruction EmitStvecWithUnsignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -1990,7 +1990,7 @@ namespace ChocolArm64.Instruction } } - public static void Umax_V(AilEmitterCtx context) + public static void Umax_V(ILEmitterCtx context) { Type[] types = new Type[] { typeof(ulong), typeof(ulong) }; @@ -1999,7 +1999,7 @@ namespace ChocolArm64.Instruction EmitVectorBinaryOpZx(context, () => context.EmitCall(mthdInfo)); } - public static void Umaxp_V(AilEmitterCtx context) + public static void Umaxp_V(ILEmitterCtx context) { Type[] types = new Type[] { typeof(ulong), typeof(ulong) }; @@ -2008,7 +2008,7 @@ namespace ChocolArm64.Instruction EmitVectorPairwiseOpZx(context, () => context.EmitCall(mthdInfo)); } - public static void Umin_V(AilEmitterCtx context) + public static void Umin_V(ILEmitterCtx context) { Type[] types = new Type[] { typeof(ulong), typeof(ulong) }; @@ -2017,7 +2017,7 @@ namespace ChocolArm64.Instruction EmitVectorBinaryOpZx(context, () => context.EmitCall(mthdInfo)); } - public static void Uminp_V(AilEmitterCtx context) + public static void Uminp_V(ILEmitterCtx context) { Type[] types = new Type[] { typeof(ulong), typeof(ulong) }; @@ -2026,11 +2026,11 @@ namespace ChocolArm64.Instruction EmitVectorPairwiseOpZx(context, () => context.EmitCall(mthdInfo)); } - public static void Umlal_V(AilEmitterCtx context) + public static void Umlal_V(ILEmitterCtx context) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; - if (AOptimizations.UseSse41 && op.Size < 2) + if (Optimizations.UseSse41 && op.Size < 2) { Type[] typesSrl = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], typeof(byte) }; Type[] typesCvt = new Type[] { VectorUIntTypesPerSizeLog2[op.Size] }; @@ -2043,7 +2043,7 @@ namespace ChocolArm64.Instruction ? nameof(Sse41.ConvertToVector128Int16) : nameof(Sse41.ConvertToVector128Int32); - int numBytes = op.RegisterSize == ARegisterSize.Simd128 ? 8 : 0; + int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0; EmitLdvecWithUnsignedCast(context, op.Rd, op.Size + 1); @@ -2077,11 +2077,11 @@ namespace ChocolArm64.Instruction } } - public static void Umlsl_V(AilEmitterCtx context) + public static void Umlsl_V(ILEmitterCtx context) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; - if (AOptimizations.UseSse41 && op.Size < 2) + if (Optimizations.UseSse41 && op.Size < 2) { Type[] typesSrl = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], typeof(byte) }; Type[] typesCvt = new Type[] { VectorUIntTypesPerSizeLog2[op.Size] }; @@ -2094,7 +2094,7 @@ namespace ChocolArm64.Instruction ? nameof(Sse41.ConvertToVector128Int16) : nameof(Sse41.ConvertToVector128Int32); - int numBytes = op.RegisterSize == ARegisterSize.Simd128 ? 8 : 0; + int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0; EmitLdvecWithUnsignedCast(context, op.Rd, op.Size + 1); @@ -2128,46 +2128,46 @@ namespace ChocolArm64.Instruction } } - public static void Umull_V(AilEmitterCtx context) + public static void Umull_V(ILEmitterCtx context) { EmitVectorWidenRnRmBinaryOpZx(context, () => context.Emit(OpCodes.Mul)); } - public static void Uqadd_S(AilEmitterCtx context) + public static void Uqadd_S(ILEmitterCtx context) { EmitScalarSaturatingBinaryOpZx(context, SaturatingFlags.Add); } - public static void Uqadd_V(AilEmitterCtx context) + public static void Uqadd_V(ILEmitterCtx context) { EmitVectorSaturatingBinaryOpZx(context, SaturatingFlags.Add); } - public static void Uqsub_S(AilEmitterCtx context) + public static void Uqsub_S(ILEmitterCtx context) { EmitScalarSaturatingBinaryOpZx(context, SaturatingFlags.Sub); } - public static void Uqsub_V(AilEmitterCtx context) + public static void Uqsub_V(ILEmitterCtx context) { EmitVectorSaturatingBinaryOpZx(context, SaturatingFlags.Sub); } - public static void Uqxtn_S(AilEmitterCtx context) + public static void Uqxtn_S(ILEmitterCtx context) { EmitSaturatingNarrowOp(context, SaturatingNarrowFlags.ScalarZxZx); } - public static void Uqxtn_V(AilEmitterCtx context) + public static void Uqxtn_V(ILEmitterCtx context) { EmitSaturatingNarrowOp(context, SaturatingNarrowFlags.VectorZxZx); } - public static void Urhadd_V(AilEmitterCtx context) + public static void Urhadd_V(ILEmitterCtx context) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; - if (AOptimizations.UseSse2 && op.Size < 2) + if (Optimizations.UseSse2 && op.Size < 2) { Type[] typesAvg = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], VectorUIntTypesPerSizeLog2[op.Size] }; @@ -2178,7 +2178,7 @@ namespace ChocolArm64.Instruction EmitStvecWithUnsignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -2198,21 +2198,21 @@ namespace ChocolArm64.Instruction } } - public static void Usqadd_S(AilEmitterCtx context) + public static void Usqadd_S(ILEmitterCtx context) { EmitScalarSaturatingBinaryOpZx(context, SaturatingFlags.Accumulate); } - public static void Usqadd_V(AilEmitterCtx context) + public static void Usqadd_V(ILEmitterCtx context) { EmitVectorSaturatingBinaryOpZx(context, SaturatingFlags.Accumulate); } - public static void Usubl_V(AilEmitterCtx context) + public static void Usubl_V(ILEmitterCtx context) { - if (AOptimizations.UseSse41) + if (Optimizations.UseSse41) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; Type[] typesSrl = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], typeof(byte) }; Type[] typesCvt = new Type[] { VectorUIntTypesPerSizeLog2[op.Size] }; @@ -2223,7 +2223,7 @@ namespace ChocolArm64.Instruction nameof(Sse41.ConvertToVector128Int32), nameof(Sse41.ConvertToVector128Int64) }; - int numBytes = op.RegisterSize == ARegisterSize.Simd128 ? 8 : 0; + int numBytes = op.RegisterSize == RegisterSize.Simd128 ? 8 : 0; EmitLdvecWithUnsignedCast(context, op.Rn, op.Size); @@ -2249,14 +2249,14 @@ namespace ChocolArm64.Instruction } } - public static void Usubw_V(AilEmitterCtx context) + public static void Usubw_V(ILEmitterCtx context) { EmitVectorWidenRmBinaryOpZx(context, () => context.Emit(OpCodes.Sub)); } - private static void EmitAbs(AilEmitterCtx context) + private static void EmitAbs(ILEmitterCtx context) { - AilLabel lblTrue = new AilLabel(); + ILLabel lblTrue = new ILLabel(); context.Emit(OpCodes.Dup); context.Emit(OpCodes.Ldc_I4_0); @@ -2267,9 +2267,9 @@ namespace ChocolArm64.Instruction context.MarkLabel(lblTrue); } - private static void EmitAddLongPairwise(AilEmitterCtx context, bool signed, bool accumulate) + private static void EmitAddLongPairwise(ILEmitterCtx context, bool signed, bool accumulate) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int words = op.GetBitsCount() >> 4; int pairs = words >> op.Size; @@ -2296,15 +2296,15 @@ namespace ChocolArm64.Instruction context.EmitLdvectmp(); context.EmitStvec(op.Rd); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - private static void EmitDoublingMultiplyHighHalf(AilEmitterCtx context, bool round) + private static void EmitDoublingMultiplyHighHalf(ILEmitterCtx context, bool round) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; int eSize = 8 << op.Size; @@ -2318,7 +2318,7 @@ namespace ChocolArm64.Instruction { long roundConst = 1L << (eSize - 1); - AilLabel lblTrue = new AilLabel(); + ILLabel lblTrue = new ILLabel(); context.EmitLsl(1); @@ -2338,15 +2338,15 @@ namespace ChocolArm64.Instruction } } - private static void EmitHighNarrow(AilEmitterCtx context, Action emit, bool round) + private static void EmitHighNarrow(ILEmitterCtx context, Action emit, bool round) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; int elems = 8 >> op.Size; int eSize = 8 << op.Size; - int part = op.RegisterSize == ARegisterSize.Simd128 ? elems : 0; + int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0; long roundConst = 1L << (eSize - 1); diff --git a/ChocolArm64/Instruction/AInstEmitSimdCmp.cs b/ChocolArm64/Instruction/InstEmitSimdCmp.cs similarity index 66% rename from ChocolArm64/Instruction/AInstEmitSimdCmp.cs rename to ChocolArm64/Instruction/InstEmitSimdCmp.cs index c04d049914..d29ba83cef 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdCmp.cs +++ b/ChocolArm64/Instruction/InstEmitSimdCmp.cs @@ -5,27 +5,27 @@ using System; using System.Reflection.Emit; using System.Runtime.Intrinsics.X86; -using static ChocolArm64.Instruction.AInstEmitAluHelper; +using static ChocolArm64.Instruction.InstEmitAluHelper; using static ChocolArm64.Instruction.AInstEmitSimdHelper; namespace ChocolArm64.Instruction { - static partial class AInstEmit + static partial class InstEmit { - public static void Cmeq_S(AilEmitterCtx context) + public static void Cmeq_S(ILEmitterCtx context) { EmitCmp(context, OpCodes.Beq_S, scalar: true); } - public static void Cmeq_V(AilEmitterCtx context) + public static void Cmeq_V(ILEmitterCtx context) { - if (context.CurrOp is AOpCodeSimdReg op) + if (context.CurrOp is OpCodeSimdReg op) { - if (op.Size < 3 && AOptimizations.UseSse2) + if (op.Size < 3 && Optimizations.UseSse2) { EmitSse2Op(context, nameof(Sse2.CompareEqual)); } - else if (op.Size == 3 && AOptimizations.UseSse41) + else if (op.Size == 3 && Optimizations.UseSse41) { EmitSse41Op(context, nameof(Sse41.CompareEqual)); } @@ -40,30 +40,30 @@ namespace ChocolArm64.Instruction } } - public static void Cmge_S(AilEmitterCtx context) + public static void Cmge_S(ILEmitterCtx context) { EmitCmp(context, OpCodes.Bge_S, scalar: true); } - public static void Cmge_V(AilEmitterCtx context) + public static void Cmge_V(ILEmitterCtx context) { EmitCmp(context, OpCodes.Bge_S, scalar: false); } - public static void Cmgt_S(AilEmitterCtx context) + public static void Cmgt_S(ILEmitterCtx context) { EmitCmp(context, OpCodes.Bgt_S, scalar: true); } - public static void Cmgt_V(AilEmitterCtx context) + public static void Cmgt_V(ILEmitterCtx context) { - if (context.CurrOp is AOpCodeSimdReg op) + if (context.CurrOp is OpCodeSimdReg op) { - if (op.Size < 3 && AOptimizations.UseSse2) + if (op.Size < 3 && Optimizations.UseSse2) { EmitSse2Op(context, nameof(Sse2.CompareGreaterThan)); } - else if (op.Size == 3 && AOptimizations.UseSse42) + else if (op.Size == 3 && Optimizations.UseSse42) { EmitSse42Op(context, nameof(Sse42.CompareGreaterThan)); } @@ -78,62 +78,62 @@ namespace ChocolArm64.Instruction } } - public static void Cmhi_S(AilEmitterCtx context) + public static void Cmhi_S(ILEmitterCtx context) { EmitCmp(context, OpCodes.Bgt_Un_S, scalar: true); } - public static void Cmhi_V(AilEmitterCtx context) + public static void Cmhi_V(ILEmitterCtx context) { EmitCmp(context, OpCodes.Bgt_Un_S, scalar: false); } - public static void Cmhs_S(AilEmitterCtx context) + public static void Cmhs_S(ILEmitterCtx context) { EmitCmp(context, OpCodes.Bge_Un_S, scalar: true); } - public static void Cmhs_V(AilEmitterCtx context) + public static void Cmhs_V(ILEmitterCtx context) { EmitCmp(context, OpCodes.Bge_Un_S, scalar: false); } - public static void Cmle_S(AilEmitterCtx context) + public static void Cmle_S(ILEmitterCtx context) { EmitCmp(context, OpCodes.Ble_S, scalar: true); } - public static void Cmle_V(AilEmitterCtx context) + public static void Cmle_V(ILEmitterCtx context) { EmitCmp(context, OpCodes.Ble_S, scalar: false); } - public static void Cmlt_S(AilEmitterCtx context) + public static void Cmlt_S(ILEmitterCtx context) { EmitCmp(context, OpCodes.Blt_S, scalar: true); } - public static void Cmlt_V(AilEmitterCtx context) + public static void Cmlt_V(ILEmitterCtx context) { EmitCmp(context, OpCodes.Blt_S, scalar: false); } - public static void Cmtst_S(AilEmitterCtx context) + public static void Cmtst_S(ILEmitterCtx context) { EmitCmtst(context, scalar: true); } - public static void Cmtst_V(AilEmitterCtx context) + public static void Cmtst_V(ILEmitterCtx context) { EmitCmtst(context, scalar: false); } - public static void Fccmp_S(AilEmitterCtx context) + public static void Fccmp_S(ILEmitterCtx context) { - AOpCodeSimdFcond op = (AOpCodeSimdFcond)context.CurrOp; + OpCodeSimdFcond op = (OpCodeSimdFcond)context.CurrOp; - AilLabel lblTrue = new AilLabel(); - AilLabel lblEnd = new AilLabel(); + ILLabel lblTrue = new ILLabel(); + ILLabel lblEnd = new ILLabel(); context.EmitCondBranch(lblTrue, op.Cond); @@ -148,15 +148,15 @@ namespace ChocolArm64.Instruction context.MarkLabel(lblEnd); } - public static void Fccmpe_S(AilEmitterCtx context) + public static void Fccmpe_S(ILEmitterCtx context) { Fccmp_S(context); } - public static void Fcmeq_S(AilEmitterCtx context) + public static void Fcmeq_S(ILEmitterCtx context) { - if (context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (context.CurrOp is OpCodeSimdReg && Optimizations.UseSse + && Optimizations.UseSse2) { EmitScalarSseOrSse2OpF(context, nameof(Sse.CompareEqualScalar)); } @@ -166,10 +166,10 @@ namespace ChocolArm64.Instruction } } - public static void Fcmeq_V(AilEmitterCtx context) + public static void Fcmeq_V(ILEmitterCtx context) { - if (context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (context.CurrOp is OpCodeSimdReg && Optimizations.UseSse + && Optimizations.UseSse2) { EmitVectorSseOrSse2OpF(context, nameof(Sse.CompareEqual)); } @@ -179,10 +179,10 @@ namespace ChocolArm64.Instruction } } - public static void Fcmge_S(AilEmitterCtx context) + public static void Fcmge_S(ILEmitterCtx context) { - if (context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (context.CurrOp is OpCodeSimdReg && Optimizations.UseSse + && Optimizations.UseSse2) { EmitScalarSseOrSse2OpF(context, nameof(Sse.CompareGreaterThanOrEqualScalar)); } @@ -192,10 +192,10 @@ namespace ChocolArm64.Instruction } } - public static void Fcmge_V(AilEmitterCtx context) + public static void Fcmge_V(ILEmitterCtx context) { - if (context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (context.CurrOp is OpCodeSimdReg && Optimizations.UseSse + && Optimizations.UseSse2) { EmitVectorSseOrSse2OpF(context, nameof(Sse.CompareGreaterThanOrEqual)); } @@ -205,10 +205,10 @@ namespace ChocolArm64.Instruction } } - public static void Fcmgt_S(AilEmitterCtx context) + public static void Fcmgt_S(ILEmitterCtx context) { - if (context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (context.CurrOp is OpCodeSimdReg && Optimizations.UseSse + && Optimizations.UseSse2) { EmitScalarSseOrSse2OpF(context, nameof(Sse.CompareGreaterThanScalar)); } @@ -218,10 +218,10 @@ namespace ChocolArm64.Instruction } } - public static void Fcmgt_V(AilEmitterCtx context) + public static void Fcmgt_V(ILEmitterCtx context) { - if (context.CurrOp is AOpCodeSimdReg && AOptimizations.UseSse - && AOptimizations.UseSse2) + if (context.CurrOp is OpCodeSimdReg && Optimizations.UseSse + && Optimizations.UseSse2) { EmitVectorSseOrSse2OpF(context, nameof(Sse.CompareGreaterThan)); } @@ -231,31 +231,31 @@ namespace ChocolArm64.Instruction } } - public static void Fcmle_S(AilEmitterCtx context) + public static void Fcmle_S(ILEmitterCtx context) { EmitScalarFcmp(context, OpCodes.Ble_S); } - public static void Fcmle_V(AilEmitterCtx context) + public static void Fcmle_V(ILEmitterCtx context) { EmitVectorFcmp(context, OpCodes.Ble_S); } - public static void Fcmlt_S(AilEmitterCtx context) + public static void Fcmlt_S(ILEmitterCtx context) { EmitScalarFcmp(context, OpCodes.Blt_S); } - public static void Fcmlt_V(AilEmitterCtx context) + public static void Fcmlt_V(ILEmitterCtx context) { EmitVectorFcmp(context, OpCodes.Blt_S); } - public static void Fcmp_S(AilEmitterCtx context) + public static void Fcmp_S(ILEmitterCtx context) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; - bool cmpWithZero = !(op is AOpCodeSimdFcond) ? op.Bit3 : false; + bool cmpWithZero = !(op is OpCodeSimdFcond) ? op.Bit3 : false; //Handle NaN case. //If any number is NaN, then NZCV = 0011. @@ -271,8 +271,8 @@ namespace ChocolArm64.Instruction context.Emit(OpCodes.Or); } - AilLabel lblNaN = new AilLabel(); - AilLabel lblEnd = new AilLabel(); + ILLabel lblNaN = new ILLabel(); + ILLabel lblEnd = new ILLabel(); context.Emit(OpCodes.Brtrue_S, lblNaN); @@ -303,7 +303,7 @@ namespace ChocolArm64.Instruction context.Emit(OpCodes.Ceq); context.Emit(OpCodes.Dup); - context.EmitStflg((int)ApState.ZBit); + context.EmitStflg((int)PState.ZBit); //C = Rn >= Rm EmitLoadOpers(); @@ -311,19 +311,19 @@ namespace ChocolArm64.Instruction context.Emit(OpCodes.Cgt); context.Emit(OpCodes.Or); - context.EmitStflg((int)ApState.CBit); + context.EmitStflg((int)PState.CBit); //N = Rn < Rm EmitLoadOpers(); context.Emit(OpCodes.Clt); - context.EmitStflg((int)ApState.NBit); + context.EmitStflg((int)PState.NBit); //V = 0 context.EmitLdc_I4(0); - context.EmitStflg((int)ApState.VBit); + context.EmitStflg((int)PState.VBit); context.Emit(OpCodes.Br_S, lblEnd); @@ -334,14 +334,14 @@ namespace ChocolArm64.Instruction context.MarkLabel(lblEnd); } - public static void Fcmpe_S(AilEmitterCtx context) + public static void Fcmpe_S(ILEmitterCtx context) { Fcmp_S(context); } - private static void EmitNaNCheck(AilEmitterCtx context, int reg) + private static void EmitNaNCheck(ILEmitterCtx context, int reg) { - IaOpCodeSimd op = (IaOpCodeSimd)context.CurrOp; + IOpCodeSimd op = (IOpCodeSimd)context.CurrOp; EmitVectorExtractF(context, reg, 0, op.Size); @@ -359,9 +359,9 @@ namespace ChocolArm64.Instruction } } - private static void EmitCmp(AilEmitterCtx context, OpCode ilOp, bool scalar) + private static void EmitCmp(ILEmitterCtx context, OpCode ilOp, bool scalar) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int bytes = op.GetBitsCount() >> 3; int elems = !scalar ? bytes >> op.Size : 1; @@ -372,7 +372,7 @@ namespace ChocolArm64.Instruction { EmitVectorExtractSx(context, op.Rn, index, op.Size); - if (op is AOpCodeSimdReg binOp) + if (op is OpCodeSimdReg binOp) { EmitVectorExtractSx(context, binOp.Rm, index, op.Size); } @@ -381,8 +381,8 @@ namespace ChocolArm64.Instruction context.EmitLdc_I8(0L); } - AilLabel lblTrue = new AilLabel(); - AilLabel lblEnd = new AilLabel(); + ILLabel lblTrue = new ILLabel(); + ILLabel lblEnd = new ILLabel(); context.Emit(ilOp, lblTrue); @@ -397,15 +397,15 @@ namespace ChocolArm64.Instruction context.MarkLabel(lblEnd); } - if ((op.RegisterSize == ARegisterSize.Simd64) || scalar) + if ((op.RegisterSize == RegisterSize.Simd64) || scalar) { EmitVectorZeroUpper(context, op.Rd); } } - private static void EmitCmtst(AilEmitterCtx context, bool scalar) + private static void EmitCmtst(ILEmitterCtx context, bool scalar) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; int bytes = op.GetBitsCount() >> 3; int elems = !scalar ? bytes >> op.Size : 1; @@ -417,8 +417,8 @@ namespace ChocolArm64.Instruction EmitVectorExtractZx(context, op.Rn, index, op.Size); EmitVectorExtractZx(context, op.Rm, index, op.Size); - AilLabel lblTrue = new AilLabel(); - AilLabel lblEnd = new AilLabel(); + ILLabel lblTrue = new ILLabel(); + ILLabel lblEnd = new ILLabel(); context.Emit(OpCodes.And); @@ -437,20 +437,20 @@ namespace ChocolArm64.Instruction context.MarkLabel(lblEnd); } - if ((op.RegisterSize == ARegisterSize.Simd64) || scalar) + if ((op.RegisterSize == RegisterSize.Simd64) || scalar) { EmitVectorZeroUpper(context, op.Rd); } } - private static void EmitScalarFcmp(AilEmitterCtx context, OpCode ilOp) + private static void EmitScalarFcmp(ILEmitterCtx context, OpCode ilOp) { EmitFcmp(context, ilOp, 0, scalar: true); } - private static void EmitVectorFcmp(AilEmitterCtx context, OpCode ilOp) + private static void EmitVectorFcmp(ILEmitterCtx context, OpCode ilOp) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int sizeF = op.Size & 1; @@ -462,15 +462,15 @@ namespace ChocolArm64.Instruction EmitFcmp(context, ilOp, index, scalar: false); } - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - private static void EmitFcmp(AilEmitterCtx context, OpCode ilOp, int index, bool scalar) + private static void EmitFcmp(ILEmitterCtx context, OpCode ilOp, int index, bool scalar) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int sizeF = op.Size & 1; @@ -478,7 +478,7 @@ namespace ChocolArm64.Instruction EmitVectorExtractF(context, op.Rn, index, sizeF); - if (op is AOpCodeSimdReg binOp) + if (op is OpCodeSimdReg binOp) { EmitVectorExtractF(context, binOp.Rm, index, sizeF); } @@ -491,8 +491,8 @@ namespace ChocolArm64.Instruction context.EmitLdc_R8(0d); } - AilLabel lblTrue = new AilLabel(); - AilLabel lblEnd = new AilLabel(); + ILLabel lblTrue = new ILLabel(); + ILLabel lblEnd = new ILLabel(); context.Emit(ilOp, lblTrue); diff --git a/ChocolArm64/Instruction/InstEmitSimdCrypto.cs b/ChocolArm64/Instruction/InstEmitSimdCrypto.cs new file mode 100644 index 0000000000..f711e8ddb2 --- /dev/null +++ b/ChocolArm64/Instruction/InstEmitSimdCrypto.cs @@ -0,0 +1,54 @@ +using ChocolArm64.Decoder; +using ChocolArm64.Translation; + +namespace ChocolArm64.Instruction +{ + static partial class InstEmit + { + public static void Aesd_V(ILEmitterCtx context) + { + OpCodeSimd op = (OpCodeSimd)context.CurrOp; + + context.EmitLdvec(op.Rd); + context.EmitLdvec(op.Rn); + + SoftFallback.EmitCall(context, nameof(SoftFallback.Decrypt)); + + context.EmitStvec(op.Rd); + } + + public static void Aese_V(ILEmitterCtx context) + { + OpCodeSimd op = (OpCodeSimd)context.CurrOp; + + context.EmitLdvec(op.Rd); + context.EmitLdvec(op.Rn); + + SoftFallback.EmitCall(context, nameof(SoftFallback.Encrypt)); + + context.EmitStvec(op.Rd); + } + + public static void Aesimc_V(ILEmitterCtx context) + { + OpCodeSimd op = (OpCodeSimd)context.CurrOp; + + context.EmitLdvec(op.Rn); + + SoftFallback.EmitCall(context, nameof(SoftFallback.InverseMixColumns)); + + context.EmitStvec(op.Rd); + } + + public static void Aesmc_V(ILEmitterCtx context) + { + OpCodeSimd op = (OpCodeSimd)context.CurrOp; + + context.EmitLdvec(op.Rn); + + SoftFallback.EmitCall(context, nameof(SoftFallback.MixColumns)); + + context.EmitStvec(op.Rd); + } + } +} diff --git a/ChocolArm64/Instruction/AInstEmitSimdCvt.cs b/ChocolArm64/Instruction/InstEmitSimdCvt.cs similarity index 65% rename from ChocolArm64/Instruction/AInstEmitSimdCvt.cs rename to ChocolArm64/Instruction/InstEmitSimdCvt.cs index 7810248db7..e95c117f96 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdCvt.cs +++ b/ChocolArm64/Instruction/InstEmitSimdCvt.cs @@ -10,18 +10,18 @@ using static ChocolArm64.Instruction.AInstEmitSimdHelper; namespace ChocolArm64.Instruction { - static partial class AInstEmit + static partial class InstEmit { - public static void Fcvt_S(AilEmitterCtx context) + public static void Fcvt_S(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; - if (AOptimizations.UseSse2) + if (Optimizations.UseSse2) { if (op.Size == 1 && op.Opc == 0) { //Double -> Single. - AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorSingleZero)); + VectorHelper.EmitCall(context, nameof(VectorHelper.VectorSingleZero)); EmitLdvecWithCastToDouble(context, op.Rn); @@ -34,7 +34,7 @@ namespace ChocolArm64.Instruction else if (op.Size == 0 && op.Opc == 1) { //Single -> Double. - AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorDoubleZero)); + VectorHelper.EmitCall(context, nameof(VectorHelper.VectorDoubleZero)); context.EmitLdvec(op.Rn); @@ -60,25 +60,25 @@ namespace ChocolArm64.Instruction } } - public static void Fcvtas_Gp(AilEmitterCtx context) + public static void Fcvtas_Gp(ILEmitterCtx context) { EmitFcvt_s_Gp(context, () => EmitRoundMathCall(context, MidpointRounding.AwayFromZero)); } - public static void Fcvtau_Gp(AilEmitterCtx context) + public static void Fcvtau_Gp(ILEmitterCtx context) { EmitFcvt_u_Gp(context, () => EmitRoundMathCall(context, MidpointRounding.AwayFromZero)); } - public static void Fcvtl_V(AilEmitterCtx context) + public static void Fcvtl_V(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int sizeF = op.Size & 1; int elems = 4 >> sizeF; - int part = op.RegisterSize == ARegisterSize.Simd128 ? elems : 0; + int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0; for (int index = 0; index < elems; index++) { @@ -87,7 +87,7 @@ namespace ChocolArm64.Instruction EmitVectorExtractZx(context, op.Rn, part + index, 1); context.Emit(OpCodes.Conv_U2); - context.EmitLdarg(ATranslatedSub.StateArgIdx); + context.EmitLdarg(TranslatedSub.StateArgIdx); context.EmitCall(typeof(ASoftFloat1632), nameof(ASoftFloat1632.FPConvert)); } @@ -105,25 +105,25 @@ namespace ChocolArm64.Instruction context.EmitStvec(op.Rd); } - public static void Fcvtms_Gp(AilEmitterCtx context) + public static void Fcvtms_Gp(ILEmitterCtx context) { EmitFcvt_s_Gp(context, () => EmitUnaryMathCall(context, nameof(Math.Floor))); } - public static void Fcvtmu_Gp(AilEmitterCtx context) + public static void Fcvtmu_Gp(ILEmitterCtx context) { EmitFcvt_u_Gp(context, () => EmitUnaryMathCall(context, nameof(Math.Floor))); } - public static void Fcvtn_V(AilEmitterCtx context) + public static void Fcvtn_V(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int sizeF = op.Size & 1; int elems = 4 >> sizeF; - int part = op.RegisterSize == ARegisterSize.Simd128 ? elems : 0; + int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0; if (part != 0) { @@ -137,7 +137,7 @@ namespace ChocolArm64.Instruction if (sizeF == 0) { - context.EmitLdarg(ATranslatedSub.StateArgIdx); + context.EmitLdarg(TranslatedSub.StateArgIdx); context.EmitCall(typeof(ASoftFloat3216), nameof(ASoftFloat3216.FPConvert)); @@ -161,83 +161,83 @@ namespace ChocolArm64.Instruction } } - public static void Fcvtns_S(AilEmitterCtx context) + public static void Fcvtns_S(ILEmitterCtx context) { EmitFcvtn(context, signed: true, scalar: true); } - public static void Fcvtns_V(AilEmitterCtx context) + public static void Fcvtns_V(ILEmitterCtx context) { EmitFcvtn(context, signed: true, scalar: false); } - public static void Fcvtnu_S(AilEmitterCtx context) + public static void Fcvtnu_S(ILEmitterCtx context) { EmitFcvtn(context, signed: false, scalar: true); } - public static void Fcvtnu_V(AilEmitterCtx context) + public static void Fcvtnu_V(ILEmitterCtx context) { EmitFcvtn(context, signed: false, scalar: false); } - public static void Fcvtps_Gp(AilEmitterCtx context) + public static void Fcvtps_Gp(ILEmitterCtx context) { EmitFcvt_s_Gp(context, () => EmitUnaryMathCall(context, nameof(Math.Ceiling))); } - public static void Fcvtpu_Gp(AilEmitterCtx context) + public static void Fcvtpu_Gp(ILEmitterCtx context) { EmitFcvt_u_Gp(context, () => EmitUnaryMathCall(context, nameof(Math.Ceiling))); } - public static void Fcvtzs_Gp(AilEmitterCtx context) + public static void Fcvtzs_Gp(ILEmitterCtx context) { EmitFcvt_s_Gp(context, () => { }); } - public static void Fcvtzs_Gp_Fix(AilEmitterCtx context) + public static void Fcvtzs_Gp_Fix(ILEmitterCtx context) { EmitFcvtzs_Gp_Fix(context); } - public static void Fcvtzs_S(AilEmitterCtx context) + public static void Fcvtzs_S(ILEmitterCtx context) { EmitScalarFcvtzs(context); } - public static void Fcvtzs_V(AilEmitterCtx context) + public static void Fcvtzs_V(ILEmitterCtx context) { EmitVectorFcvtzs(context); } - public static void Fcvtzu_Gp(AilEmitterCtx context) + public static void Fcvtzu_Gp(ILEmitterCtx context) { EmitFcvt_u_Gp(context, () => { }); } - public static void Fcvtzu_Gp_Fix(AilEmitterCtx context) + public static void Fcvtzu_Gp_Fix(ILEmitterCtx context) { EmitFcvtzu_Gp_Fix(context); } - public static void Fcvtzu_S(AilEmitterCtx context) + public static void Fcvtzu_S(ILEmitterCtx context) { EmitScalarFcvtzu(context); } - public static void Fcvtzu_V(AilEmitterCtx context) + public static void Fcvtzu_V(ILEmitterCtx context) { EmitVectorFcvtzu(context); } - public static void Scvtf_Gp(AilEmitterCtx context) + public static void Scvtf_Gp(ILEmitterCtx context) { - AOpCodeSimdCvt op = (AOpCodeSimdCvt)context.CurrOp; + OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp; context.EmitLdintzr(op.Rn); - if (context.CurrOp.RegisterSize == ARegisterSize.Int32) + if (context.CurrOp.RegisterSize == RegisterSize.Int32) { context.Emit(OpCodes.Conv_U4); } @@ -247,9 +247,9 @@ namespace ChocolArm64.Instruction EmitScalarSetF(context, op.Rd, op.Size); } - public static void Scvtf_S(AilEmitterCtx context) + public static void Scvtf_S(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; EmitVectorExtractSx(context, op.Rn, 0, op.Size + 2); @@ -258,18 +258,18 @@ namespace ChocolArm64.Instruction EmitScalarSetF(context, op.Rd, op.Size); } - public static void Scvtf_V(AilEmitterCtx context) + public static void Scvtf_V(ILEmitterCtx context) { EmitVectorCvtf(context, signed: true); } - public static void Ucvtf_Gp(AilEmitterCtx context) + public static void Ucvtf_Gp(ILEmitterCtx context) { - AOpCodeSimdCvt op = (AOpCodeSimdCvt)context.CurrOp; + OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp; context.EmitLdintzr(op.Rn); - if (context.CurrOp.RegisterSize == ARegisterSize.Int32) + if (context.CurrOp.RegisterSize == RegisterSize.Int32) { context.Emit(OpCodes.Conv_U4); } @@ -281,9 +281,9 @@ namespace ChocolArm64.Instruction EmitScalarSetF(context, op.Rd, op.Size); } - public static void Ucvtf_S(AilEmitterCtx context) + public static void Ucvtf_S(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; EmitVectorExtractZx(context, op.Rn, 0, op.Size + 2); @@ -294,14 +294,14 @@ namespace ChocolArm64.Instruction EmitScalarSetF(context, op.Rd, op.Size); } - public static void Ucvtf_V(AilEmitterCtx context) + public static void Ucvtf_V(ILEmitterCtx context) { EmitVectorCvtf(context, signed: false); } - private static int GetFBits(AilEmitterCtx context) + private static int GetFBits(ILEmitterCtx context) { - if (context.CurrOp is AOpCodeSimdShImm op) + if (context.CurrOp is OpCodeSimdShImm op) { return GetImmShr(op); } @@ -309,7 +309,7 @@ namespace ChocolArm64.Instruction return 0; } - private static void EmitFloatCast(AilEmitterCtx context, int size) + private static void EmitFloatCast(ILEmitterCtx context, int size) { if (size == 0) { @@ -325,9 +325,9 @@ namespace ChocolArm64.Instruction } } - private static void EmitFcvtn(AilEmitterCtx context, bool signed, bool scalar) + private static void EmitFcvtn(ILEmitterCtx context, bool signed, bool scalar) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int sizeF = op.Size & 1; int sizeI = sizeF + 2; @@ -348,17 +348,17 @@ namespace ChocolArm64.Instruction if (sizeF == 0) { - AVectorHelper.EmitCall(context, signed - ? nameof(AVectorHelper.SatF32ToS32) - : nameof(AVectorHelper.SatF32ToU32)); + VectorHelper.EmitCall(context, signed + ? nameof(VectorHelper.SatF32ToS32) + : nameof(VectorHelper.SatF32ToU32)); context.Emit(OpCodes.Conv_U8); } else /* if (SizeF == 1) */ { - AVectorHelper.EmitCall(context, signed - ? nameof(AVectorHelper.SatF64ToS64) - : nameof(AVectorHelper.SatF64ToU64)); + VectorHelper.EmitCall(context, signed + ? nameof(VectorHelper.SatF64ToS64) + : nameof(VectorHelper.SatF64ToU64)); } EmitVectorInsertTmp(context, index, sizeI); @@ -367,25 +367,25 @@ namespace ChocolArm64.Instruction context.EmitLdvectmp(); context.EmitStvec(op.Rd); - if ((op.RegisterSize == ARegisterSize.Simd64) || scalar) + if ((op.RegisterSize == RegisterSize.Simd64) || scalar) { EmitVectorZeroUpper(context, op.Rd); } } - private static void EmitFcvt_s_Gp(AilEmitterCtx context, Action emit) + private static void EmitFcvt_s_Gp(ILEmitterCtx context, Action emit) { EmitFcvt___Gp(context, emit, true); } - private static void EmitFcvt_u_Gp(AilEmitterCtx context, Action emit) + private static void EmitFcvt_u_Gp(ILEmitterCtx context, Action emit) { EmitFcvt___Gp(context, emit, false); } - private static void EmitFcvt___Gp(AilEmitterCtx context, Action emit, bool signed) + private static void EmitFcvt___Gp(ILEmitterCtx context, Action emit, bool signed) { - AOpCodeSimdCvt op = (AOpCodeSimdCvt)context.CurrOp; + OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp; EmitVectorExtractF(context, op.Rn, 0, op.Size); @@ -400,7 +400,7 @@ namespace ChocolArm64.Instruction EmitScalarFcvtu(context, op.Size, 0); } - if (context.CurrOp.RegisterSize == ARegisterSize.Int32) + if (context.CurrOp.RegisterSize == RegisterSize.Int32) { context.Emit(OpCodes.Conv_U8); } @@ -408,19 +408,19 @@ namespace ChocolArm64.Instruction context.EmitStintzr(op.Rd); } - private static void EmitFcvtzs_Gp_Fix(AilEmitterCtx context) + private static void EmitFcvtzs_Gp_Fix(ILEmitterCtx context) { EmitFcvtz__Gp_Fix(context, true); } - private static void EmitFcvtzu_Gp_Fix(AilEmitterCtx context) + private static void EmitFcvtzu_Gp_Fix(ILEmitterCtx context) { EmitFcvtz__Gp_Fix(context, false); } - private static void EmitFcvtz__Gp_Fix(AilEmitterCtx context, bool signed) + private static void EmitFcvtz__Gp_Fix(ILEmitterCtx context, bool signed) { - AOpCodeSimdCvt op = (AOpCodeSimdCvt)context.CurrOp; + OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp; EmitVectorExtractF(context, op.Rn, 0, op.Size); @@ -433,7 +433,7 @@ namespace ChocolArm64.Instruction EmitScalarFcvtu(context, op.Size, op.FBits); } - if (context.CurrOp.RegisterSize == ARegisterSize.Int32) + if (context.CurrOp.RegisterSize == RegisterSize.Int32) { context.Emit(OpCodes.Conv_U8); } @@ -441,19 +441,19 @@ namespace ChocolArm64.Instruction context.EmitStintzr(op.Rd); } - private static void EmitVectorScvtf(AilEmitterCtx context) + private static void EmitVectorScvtf(ILEmitterCtx context) { EmitVectorCvtf(context, true); } - private static void EmitVectorUcvtf(AilEmitterCtx context) + private static void EmitVectorUcvtf(ILEmitterCtx context) { EmitVectorCvtf(context, false); } - private static void EmitVectorCvtf(AilEmitterCtx context, bool signed) + private static void EmitVectorCvtf(ILEmitterCtx context, bool signed) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int sizeF = op.Size & 1; int sizeI = sizeF + 2; @@ -481,25 +481,25 @@ namespace ChocolArm64.Instruction EmitVectorInsertF(context, op.Rd, index, sizeF); } - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - private static void EmitScalarFcvtzs(AilEmitterCtx context) + private static void EmitScalarFcvtzs(ILEmitterCtx context) { EmitScalarFcvtz(context, true); } - private static void EmitScalarFcvtzu(AilEmitterCtx context) + private static void EmitScalarFcvtzu(ILEmitterCtx context) { EmitScalarFcvtz(context, false); } - private static void EmitScalarFcvtz(AilEmitterCtx context, bool signed) + private static void EmitScalarFcvtz(ILEmitterCtx context, bool signed) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int sizeF = op.Size & 1; int sizeI = sizeF + 2; @@ -512,15 +512,15 @@ namespace ChocolArm64.Instruction if (sizeF == 0) { - AVectorHelper.EmitCall(context, signed - ? nameof(AVectorHelper.SatF32ToS32) - : nameof(AVectorHelper.SatF32ToU32)); + VectorHelper.EmitCall(context, signed + ? nameof(VectorHelper.SatF32ToS32) + : nameof(VectorHelper.SatF32ToU32)); } else /* if (SizeF == 1) */ { - AVectorHelper.EmitCall(context, signed - ? nameof(AVectorHelper.SatF64ToS64) - : nameof(AVectorHelper.SatF64ToU64)); + VectorHelper.EmitCall(context, signed + ? nameof(VectorHelper.SatF64ToS64) + : nameof(VectorHelper.SatF64ToU64)); } if (sizeF == 0) @@ -531,19 +531,19 @@ namespace ChocolArm64.Instruction EmitScalarSet(context, op.Rd, sizeI); } - private static void EmitVectorFcvtzs(AilEmitterCtx context) + private static void EmitVectorFcvtzs(ILEmitterCtx context) { EmitVectorFcvtz(context, true); } - private static void EmitVectorFcvtzu(AilEmitterCtx context) + private static void EmitVectorFcvtzu(ILEmitterCtx context) { EmitVectorFcvtz(context, false); } - private static void EmitVectorFcvtz(AilEmitterCtx context, bool signed) + private static void EmitVectorFcvtz(ILEmitterCtx context, bool signed) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int sizeF = op.Size & 1; int sizeI = sizeF + 2; @@ -561,15 +561,15 @@ namespace ChocolArm64.Instruction if (sizeF == 0) { - AVectorHelper.EmitCall(context, signed - ? nameof(AVectorHelper.SatF32ToS32) - : nameof(AVectorHelper.SatF32ToU32)); + VectorHelper.EmitCall(context, signed + ? nameof(VectorHelper.SatF32ToS32) + : nameof(VectorHelper.SatF32ToU32)); } else /* if (SizeF == 1) */ { - AVectorHelper.EmitCall(context, signed - ? nameof(AVectorHelper.SatF64ToS64) - : nameof(AVectorHelper.SatF64ToU64)); + VectorHelper.EmitCall(context, signed + ? nameof(VectorHelper.SatF64ToS64) + : nameof(VectorHelper.SatF64ToU64)); } if (sizeF == 0) @@ -580,13 +580,13 @@ namespace ChocolArm64.Instruction EmitVectorInsert(context, op.Rd, index, sizeI); } - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - private static void EmitScalarFcvts(AilEmitterCtx context, int size, int fBits) + private static void EmitScalarFcvts(ILEmitterCtx context, int size, int fBits) { if (size < 0 || size > 1) { @@ -595,31 +595,31 @@ namespace ChocolArm64.Instruction EmitF2iFBitsMul(context, size, fBits); - if (context.CurrOp.RegisterSize == ARegisterSize.Int32) + if (context.CurrOp.RegisterSize == RegisterSize.Int32) { if (size == 0) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.SatF32ToS32)); + VectorHelper.EmitCall(context, nameof(VectorHelper.SatF32ToS32)); } else /* if (Size == 1) */ { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.SatF64ToS32)); + VectorHelper.EmitCall(context, nameof(VectorHelper.SatF64ToS32)); } } else { if (size == 0) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.SatF32ToS64)); + VectorHelper.EmitCall(context, nameof(VectorHelper.SatF32ToS64)); } else /* if (Size == 1) */ { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.SatF64ToS64)); + VectorHelper.EmitCall(context, nameof(VectorHelper.SatF64ToS64)); } } } - private static void EmitScalarFcvtu(AilEmitterCtx context, int size, int fBits) + private static void EmitScalarFcvtu(ILEmitterCtx context, int size, int fBits) { if (size < 0 || size > 1) { @@ -628,31 +628,31 @@ namespace ChocolArm64.Instruction EmitF2iFBitsMul(context, size, fBits); - if (context.CurrOp.RegisterSize == ARegisterSize.Int32) + if (context.CurrOp.RegisterSize == RegisterSize.Int32) { if (size == 0) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.SatF32ToU32)); + VectorHelper.EmitCall(context, nameof(VectorHelper.SatF32ToU32)); } else /* if (Size == 1) */ { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.SatF64ToU32)); + VectorHelper.EmitCall(context, nameof(VectorHelper.SatF64ToU32)); } } else { if (size == 0) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.SatF32ToU64)); + VectorHelper.EmitCall(context, nameof(VectorHelper.SatF32ToU64)); } else /* if (Size == 1) */ { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.SatF64ToU64)); + VectorHelper.EmitCall(context, nameof(VectorHelper.SatF64ToU64)); } } } - private static void EmitF2iFBitsMul(AilEmitterCtx context, int size, int fBits) + private static void EmitF2iFBitsMul(ILEmitterCtx context, int size, int fBits) { if (fBits != 0) { @@ -673,7 +673,7 @@ namespace ChocolArm64.Instruction } } - private static void EmitI2fFBitsMul(AilEmitterCtx context, int size, int fBits) + private static void EmitI2fFBitsMul(ILEmitterCtx context, int size, int fBits) { if (fBits != 0) { diff --git a/ChocolArm64/Instruction/InstEmitSimdHash.cs b/ChocolArm64/Instruction/InstEmitSimdHash.cs new file mode 100644 index 0000000000..65c37d792a --- /dev/null +++ b/ChocolArm64/Instruction/InstEmitSimdHash.cs @@ -0,0 +1,140 @@ +using ChocolArm64.Decoder; +using ChocolArm64.Translation; + +using static ChocolArm64.Instruction.AInstEmitSimdHelper; + +namespace ChocolArm64.Instruction +{ + static partial class InstEmit + { +#region "Sha1" + public static void Sha1c_V(ILEmitterCtx context) + { + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; + + context.EmitLdvec(op.Rd); + EmitVectorExtractZx(context, op.Rn, 0, 2); + context.EmitLdvec(op.Rm); + + SoftFallback.EmitCall(context, nameof(SoftFallback.HashChoose)); + + context.EmitStvec(op.Rd); + } + + public static void Sha1h_V(ILEmitterCtx context) + { + OpCodeSimd op = (OpCodeSimd)context.CurrOp; + + EmitVectorExtractZx(context, op.Rn, 0, 2); + + SoftFallback.EmitCall(context, nameof(SoftFallback.FixedRotate)); + + EmitScalarSet(context, op.Rd, 2); + } + + public static void Sha1m_V(ILEmitterCtx context) + { + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; + + context.EmitLdvec(op.Rd); + EmitVectorExtractZx(context, op.Rn, 0, 2); + context.EmitLdvec(op.Rm); + + SoftFallback.EmitCall(context, nameof(SoftFallback.HashMajority)); + + context.EmitStvec(op.Rd); + } + + public static void Sha1p_V(ILEmitterCtx context) + { + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; + + context.EmitLdvec(op.Rd); + EmitVectorExtractZx(context, op.Rn, 0, 2); + context.EmitLdvec(op.Rm); + + SoftFallback.EmitCall(context, nameof(SoftFallback.HashParity)); + + context.EmitStvec(op.Rd); + } + + public static void Sha1su0_V(ILEmitterCtx context) + { + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; + + context.EmitLdvec(op.Rd); + context.EmitLdvec(op.Rn); + context.EmitLdvec(op.Rm); + + SoftFallback.EmitCall(context, nameof(SoftFallback.Sha1SchedulePart1)); + + context.EmitStvec(op.Rd); + } + + public static void Sha1su1_V(ILEmitterCtx context) + { + OpCodeSimd op = (OpCodeSimd)context.CurrOp; + + context.EmitLdvec(op.Rd); + context.EmitLdvec(op.Rn); + + SoftFallback.EmitCall(context, nameof(SoftFallback.Sha1SchedulePart2)); + + context.EmitStvec(op.Rd); + } +#endregion + +#region "Sha256" + public static void Sha256h_V(ILEmitterCtx context) + { + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; + + context.EmitLdvec(op.Rd); + context.EmitLdvec(op.Rn); + context.EmitLdvec(op.Rm); + + SoftFallback.EmitCall(context, nameof(SoftFallback.HashLower)); + + context.EmitStvec(op.Rd); + } + + public static void Sha256h2_V(ILEmitterCtx context) + { + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; + + context.EmitLdvec(op.Rd); + context.EmitLdvec(op.Rn); + context.EmitLdvec(op.Rm); + + SoftFallback.EmitCall(context, nameof(SoftFallback.HashUpper)); + + context.EmitStvec(op.Rd); + } + + public static void Sha256su0_V(ILEmitterCtx context) + { + OpCodeSimd op = (OpCodeSimd)context.CurrOp; + + context.EmitLdvec(op.Rd); + context.EmitLdvec(op.Rn); + + SoftFallback.EmitCall(context, nameof(SoftFallback.Sha256SchedulePart1)); + + context.EmitStvec(op.Rd); + } + + public static void Sha256su1_V(ILEmitterCtx context) + { + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; + + context.EmitLdvec(op.Rd); + context.EmitLdvec(op.Rn); + context.EmitLdvec(op.Rm); + + SoftFallback.EmitCall(context, nameof(SoftFallback.Sha256SchedulePart2)); + + context.EmitStvec(op.Rd); + } +#endregion + } +} diff --git a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs b/ChocolArm64/Instruction/InstEmitSimdHelper.cs similarity index 64% rename from ChocolArm64/Instruction/AInstEmitSimdHelper.cs rename to ChocolArm64/Instruction/InstEmitSimdHelper.cs index 25a08e0ce7..10cff858d5 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdHelper.cs +++ b/ChocolArm64/Instruction/InstEmitSimdHelper.cs @@ -57,40 +57,40 @@ namespace ChocolArm64.Instruction RdRnRm = Rd | Rn | Rm } - public static int GetImmShl(AOpCodeSimdShImm op) + public static int GetImmShl(OpCodeSimdShImm op) { return op.Imm - (8 << op.Size); } - public static int GetImmShr(AOpCodeSimdShImm op) + public static int GetImmShr(OpCodeSimdShImm op) { return (8 << (op.Size + 1)) - op.Imm; } - public static void EmitSse2Op(AilEmitterCtx context, string name) + public static void EmitSse2Op(ILEmitterCtx context, string name) { EmitSseOp(context, name, typeof(Sse2)); } - public static void EmitSse41Op(AilEmitterCtx context, string name) + public static void EmitSse41Op(ILEmitterCtx context, string name) { EmitSseOp(context, name, typeof(Sse41)); } - public static void EmitSse42Op(AilEmitterCtx context, string name) + public static void EmitSse42Op(ILEmitterCtx context, string name) { EmitSseOp(context, name, typeof(Sse42)); } - private static void EmitSseOp(AilEmitterCtx context, string name, Type type) + private static void EmitSseOp(ILEmitterCtx context, string name, Type type) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; EmitLdvecWithSignedCast(context, op.Rn, op.Size); Type baseType = VectorIntTypesPerSizeLog2[op.Size]; - if (op is AOpCodeSimdReg binOp) + if (op is OpCodeSimdReg binOp) { EmitLdvecWithSignedCast(context, binOp.Rm, op.Size); @@ -103,64 +103,64 @@ namespace ChocolArm64.Instruction EmitStvecWithSignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - public static void EmitLdvecWithSignedCast(AilEmitterCtx context, int reg, int size) + public static void EmitLdvecWithSignedCast(ILEmitterCtx context, int reg, int size) { context.EmitLdvec(reg); switch (size) { - case 0: AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorSingleToSByte)); break; - case 1: AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorSingleToInt16)); break; - case 2: AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorSingleToInt32)); break; - case 3: AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorSingleToInt64)); break; + case 0: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorSingleToSByte)); break; + case 1: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorSingleToInt16)); break; + case 2: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorSingleToInt32)); break; + case 3: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorSingleToInt64)); break; default: throw new ArgumentOutOfRangeException(nameof(size)); } } - public static void EmitLdvecWithCastToDouble(AilEmitterCtx context, int reg) + public static void EmitLdvecWithCastToDouble(ILEmitterCtx context, int reg) { context.EmitLdvec(reg); - AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorSingleToDouble)); + VectorHelper.EmitCall(context, nameof(VectorHelper.VectorSingleToDouble)); } - public static void EmitStvecWithCastFromDouble(AilEmitterCtx context, int reg) + public static void EmitStvecWithCastFromDouble(ILEmitterCtx context, int reg) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorDoubleToSingle)); + VectorHelper.EmitCall(context, nameof(VectorHelper.VectorDoubleToSingle)); context.EmitStvec(reg); } - public static void EmitLdvecWithUnsignedCast(AilEmitterCtx context, int reg, int size) + public static void EmitLdvecWithUnsignedCast(ILEmitterCtx context, int reg, int size) { context.EmitLdvec(reg); switch (size) { - case 0: AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorSingleToByte)); break; - case 1: AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorSingleToUInt16)); break; - case 2: AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorSingleToUInt32)); break; - case 3: AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorSingleToUInt64)); break; + case 0: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorSingleToByte)); break; + case 1: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorSingleToUInt16)); break; + case 2: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorSingleToUInt32)); break; + case 3: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorSingleToUInt64)); break; default: throw new ArgumentOutOfRangeException(nameof(size)); } } - public static void EmitStvecWithSignedCast(AilEmitterCtx context, int reg, int size) + public static void EmitStvecWithSignedCast(ILEmitterCtx context, int reg, int size) { switch (size) { - case 0: AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorSByteToSingle)); break; - case 1: AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorInt16ToSingle)); break; - case 2: AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorInt32ToSingle)); break; - case 3: AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorInt64ToSingle)); break; + case 0: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorSByteToSingle)); break; + case 1: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorInt16ToSingle)); break; + case 2: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorInt32ToSingle)); break; + case 3: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorInt64ToSingle)); break; default: throw new ArgumentOutOfRangeException(nameof(size)); } @@ -168,14 +168,14 @@ namespace ChocolArm64.Instruction context.EmitStvec(reg); } - public static void EmitStvecWithUnsignedCast(AilEmitterCtx context, int reg, int size) + public static void EmitStvecWithUnsignedCast(ILEmitterCtx context, int reg, int size) { switch (size) { - case 0: AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorByteToSingle)); break; - case 1: AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorUInt16ToSingle)); break; - case 2: AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorUInt32ToSingle)); break; - case 3: AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorUInt64ToSingle)); break; + case 0: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorByteToSingle)); break; + case 1: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorUInt16ToSingle)); break; + case 2: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorUInt32ToSingle)); break; + case 3: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorUInt64ToSingle)); break; default: throw new ArgumentOutOfRangeException(nameof(size)); } @@ -183,19 +183,19 @@ namespace ChocolArm64.Instruction context.EmitStvec(reg); } - public static void EmitScalarSseOrSse2OpF(AilEmitterCtx context, string name) + public static void EmitScalarSseOrSse2OpF(ILEmitterCtx context, string name) { EmitSseOrSse2OpF(context, name, true); } - public static void EmitVectorSseOrSse2OpF(AilEmitterCtx context, string name) + public static void EmitVectorSseOrSse2OpF(ILEmitterCtx context, string name) { EmitSseOrSse2OpF(context, name, false); } - public static void EmitSseOrSse2OpF(AilEmitterCtx context, string name, bool scalar) + public static void EmitSseOrSse2OpF(ILEmitterCtx context, string name, bool scalar) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int sizeF = op.Size & 1; @@ -205,7 +205,7 @@ namespace ChocolArm64.Instruction if (sizeF == 1) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorSingleToDouble)); + VectorHelper.EmitCall(context, nameof(VectorHelper.VectorSingleToDouble)); } } @@ -225,7 +225,7 @@ namespace ChocolArm64.Instruction baseType = typeof(Vector128); } - if (op is AOpCodeSimdReg binOp) + if (op is OpCodeSimdReg binOp) { Ldvec(binOp.Rm); @@ -238,7 +238,7 @@ namespace ChocolArm64.Instruction if (sizeF == 1) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorDoubleToSingle)); + VectorHelper.EmitCall(context, nameof(VectorHelper.VectorDoubleToSingle)); } context.EmitStvec(op.Rd); @@ -254,15 +254,15 @@ namespace ChocolArm64.Instruction EmitVectorZeroUpper(context, op.Rd); } } - else if (op.RegisterSize == ARegisterSize.Simd64) + else if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - public static void EmitUnaryMathCall(AilEmitterCtx context, string name) + public static void EmitUnaryMathCall(ILEmitterCtx context, string name) { - IaOpCodeSimd op = (IaOpCodeSimd)context.CurrOp; + IOpCodeSimd op = (IOpCodeSimd)context.CurrOp; int sizeF = op.Size & 1; @@ -280,9 +280,9 @@ namespace ChocolArm64.Instruction context.EmitCall(mthdInfo); } - public static void EmitBinaryMathCall(AilEmitterCtx context, string name) + public static void EmitBinaryMathCall(ILEmitterCtx context, string name) { - IaOpCodeSimd op = (IaOpCodeSimd)context.CurrOp; + IOpCodeSimd op = (IOpCodeSimd)context.CurrOp; int sizeF = op.Size & 1; @@ -300,9 +300,9 @@ namespace ChocolArm64.Instruction context.EmitCall(mthdInfo); } - public static void EmitRoundMathCall(AilEmitterCtx context, MidpointRounding roundMode) + public static void EmitRoundMathCall(ILEmitterCtx context, MidpointRounding roundMode) { - IaOpCodeSimd op = (IaOpCodeSimd)context.CurrOp; + IOpCodeSimd op = (IOpCodeSimd)context.CurrOp; int sizeF = op.Size & 1; @@ -322,9 +322,9 @@ namespace ChocolArm64.Instruction context.EmitCall(mthdInfo); } - public static void EmitUnarySoftFloatCall(AilEmitterCtx context, string name) + public static void EmitUnarySoftFloatCall(ILEmitterCtx context, string name) { - IaOpCodeSimd op = (IaOpCodeSimd)context.CurrOp; + IOpCodeSimd op = (IOpCodeSimd)context.CurrOp; int sizeF = op.Size & 1; @@ -332,46 +332,46 @@ namespace ChocolArm64.Instruction if (sizeF == 0) { - mthdInfo = typeof(ASoftFloat).GetMethod(name, new Type[] { typeof(float) }); + mthdInfo = typeof(SoftFloat).GetMethod(name, new Type[] { typeof(float) }); } else /* if (SizeF == 1) */ { - mthdInfo = typeof(ASoftFloat).GetMethod(name, new Type[] { typeof(double) }); + mthdInfo = typeof(SoftFloat).GetMethod(name, new Type[] { typeof(double) }); } context.EmitCall(mthdInfo); } - public static void EmitSoftFloatCall(AilEmitterCtx context, string name) + public static void EmitSoftFloatCall(ILEmitterCtx context, string name) { - IaOpCodeSimd op = (IaOpCodeSimd)context.CurrOp; + IOpCodeSimd op = (IOpCodeSimd)context.CurrOp; Type type = (op.Size & 1) == 0 ? typeof(ASoftFloat32) : typeof(ASoftFloat64); - context.EmitLdarg(ATranslatedSub.StateArgIdx); + context.EmitLdarg(TranslatedSub.StateArgIdx); context.EmitCall(type, name); } - public static void EmitScalarBinaryOpByElemF(AilEmitterCtx context, Action emit) + public static void EmitScalarBinaryOpByElemF(ILEmitterCtx context, Action emit) { - AOpCodeSimdRegElemF op = (AOpCodeSimdRegElemF)context.CurrOp; + OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp; EmitScalarOpByElemF(context, emit, op.Index, ternary: false); } - public static void EmitScalarTernaryOpByElemF(AilEmitterCtx context, Action emit) + public static void EmitScalarTernaryOpByElemF(ILEmitterCtx context, Action emit) { - AOpCodeSimdRegElemF op = (AOpCodeSimdRegElemF)context.CurrOp; + OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp; EmitScalarOpByElemF(context, emit, op.Index, ternary: true); } - public static void EmitScalarOpByElemF(AilEmitterCtx context, Action emit, int elem, bool ternary) + public static void EmitScalarOpByElemF(ILEmitterCtx context, Action emit, int elem, bool ternary) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; int sizeF = op.Size & 1; @@ -388,34 +388,34 @@ namespace ChocolArm64.Instruction EmitScalarSetF(context, op.Rd, sizeF); } - public static void EmitScalarUnaryOpSx(AilEmitterCtx context, Action emit) + public static void EmitScalarUnaryOpSx(ILEmitterCtx context, Action emit) { EmitScalarOp(context, emit, OperFlags.Rn, true); } - public static void EmitScalarBinaryOpSx(AilEmitterCtx context, Action emit) + public static void EmitScalarBinaryOpSx(ILEmitterCtx context, Action emit) { EmitScalarOp(context, emit, OperFlags.RnRm, true); } - public static void EmitScalarUnaryOpZx(AilEmitterCtx context, Action emit) + public static void EmitScalarUnaryOpZx(ILEmitterCtx context, Action emit) { EmitScalarOp(context, emit, OperFlags.Rn, false); } - public static void EmitScalarBinaryOpZx(AilEmitterCtx context, Action emit) + public static void EmitScalarBinaryOpZx(ILEmitterCtx context, Action emit) { EmitScalarOp(context, emit, OperFlags.RnRm, false); } - public static void EmitScalarTernaryOpZx(AilEmitterCtx context, Action emit) + public static void EmitScalarTernaryOpZx(ILEmitterCtx context, Action emit) { EmitScalarOp(context, emit, OperFlags.RdRnRm, false); } - public static void EmitScalarOp(AilEmitterCtx context, Action emit, OperFlags opers, bool signed) + public static void EmitScalarOp(ILEmitterCtx context, Action emit, OperFlags opers, bool signed) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; bool rd = (opers & OperFlags.Rd) != 0; bool rn = (opers & OperFlags.Rn) != 0; @@ -433,7 +433,7 @@ namespace ChocolArm64.Instruction if (rm) { - EmitVectorExtract(context, ((AOpCodeSimdReg)op).Rm, 0, op.Size, signed); + EmitVectorExtract(context, ((OpCodeSimdReg)op).Rm, 0, op.Size, signed); } emit(); @@ -441,24 +441,24 @@ namespace ChocolArm64.Instruction EmitScalarSet(context, op.Rd, op.Size); } - public static void EmitScalarUnaryOpF(AilEmitterCtx context, Action emit) + public static void EmitScalarUnaryOpF(ILEmitterCtx context, Action emit) { EmitScalarOpF(context, emit, OperFlags.Rn); } - public static void EmitScalarBinaryOpF(AilEmitterCtx context, Action emit) + public static void EmitScalarBinaryOpF(ILEmitterCtx context, Action emit) { EmitScalarOpF(context, emit, OperFlags.RnRm); } - public static void EmitScalarTernaryRaOpF(AilEmitterCtx context, Action emit) + public static void EmitScalarTernaryRaOpF(ILEmitterCtx context, Action emit) { EmitScalarOpF(context, emit, OperFlags.RaRnRm); } - public static void EmitScalarOpF(AilEmitterCtx context, Action emit, OperFlags opers) + public static void EmitScalarOpF(ILEmitterCtx context, Action emit, OperFlags opers) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int sizeF = op.Size & 1; @@ -468,7 +468,7 @@ namespace ChocolArm64.Instruction if (ra) { - EmitVectorExtractF(context, ((AOpCodeSimdReg)op).Ra, 0, sizeF); + EmitVectorExtractF(context, ((OpCodeSimdReg)op).Ra, 0, sizeF); } if (rn) @@ -478,7 +478,7 @@ namespace ChocolArm64.Instruction if (rm) { - EmitVectorExtractF(context, ((AOpCodeSimdReg)op).Rm, 0, sizeF); + EmitVectorExtractF(context, ((OpCodeSimdReg)op).Rm, 0, sizeF); } emit(); @@ -486,24 +486,24 @@ namespace ChocolArm64.Instruction EmitScalarSetF(context, op.Rd, sizeF); } - public static void EmitVectorUnaryOpF(AilEmitterCtx context, Action emit) + public static void EmitVectorUnaryOpF(ILEmitterCtx context, Action emit) { EmitVectorOpF(context, emit, OperFlags.Rn); } - public static void EmitVectorBinaryOpF(AilEmitterCtx context, Action emit) + public static void EmitVectorBinaryOpF(ILEmitterCtx context, Action emit) { EmitVectorOpF(context, emit, OperFlags.RnRm); } - public static void EmitVectorTernaryOpF(AilEmitterCtx context, Action emit) + public static void EmitVectorTernaryOpF(ILEmitterCtx context, Action emit) { EmitVectorOpF(context, emit, OperFlags.RdRnRm); } - public static void EmitVectorOpF(AilEmitterCtx context, Action emit, OperFlags opers) + public static void EmitVectorOpF(ILEmitterCtx context, Action emit, OperFlags opers) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int sizeF = op.Size & 1; @@ -528,7 +528,7 @@ namespace ChocolArm64.Instruction if (rm) { - EmitVectorExtractF(context, ((AOpCodeSimdReg)op).Rm, index, sizeF); + EmitVectorExtractF(context, ((OpCodeSimdReg)op).Rm, index, sizeF); } emit(); @@ -536,29 +536,29 @@ namespace ChocolArm64.Instruction EmitVectorInsertF(context, op.Rd, index, sizeF); } - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - public static void EmitVectorBinaryOpByElemF(AilEmitterCtx context, Action emit) + public static void EmitVectorBinaryOpByElemF(ILEmitterCtx context, Action emit) { - AOpCodeSimdRegElemF op = (AOpCodeSimdRegElemF)context.CurrOp; + OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp; EmitVectorOpByElemF(context, emit, op.Index, ternary: false); } - public static void EmitVectorTernaryOpByElemF(AilEmitterCtx context, Action emit) + public static void EmitVectorTernaryOpByElemF(ILEmitterCtx context, Action emit) { - AOpCodeSimdRegElemF op = (AOpCodeSimdRegElemF)context.CurrOp; + OpCodeSimdRegElemF op = (OpCodeSimdRegElemF)context.CurrOp; EmitVectorOpByElemF(context, emit, op.Index, ternary: true); } - public static void EmitVectorOpByElemF(AilEmitterCtx context, Action emit, int elem, bool ternary) + public static void EmitVectorOpByElemF(ILEmitterCtx context, Action emit, int elem, bool ternary) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; int sizeF = op.Size & 1; @@ -583,45 +583,45 @@ namespace ChocolArm64.Instruction context.EmitLdvectmp(); context.EmitStvec(op.Rd); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - public static void EmitVectorUnaryOpSx(AilEmitterCtx context, Action emit) + public static void EmitVectorUnaryOpSx(ILEmitterCtx context, Action emit) { EmitVectorOp(context, emit, OperFlags.Rn, true); } - public static void EmitVectorBinaryOpSx(AilEmitterCtx context, Action emit) + public static void EmitVectorBinaryOpSx(ILEmitterCtx context, Action emit) { EmitVectorOp(context, emit, OperFlags.RnRm, true); } - public static void EmitVectorTernaryOpSx(AilEmitterCtx context, Action emit) + public static void EmitVectorTernaryOpSx(ILEmitterCtx context, Action emit) { EmitVectorOp(context, emit, OperFlags.RdRnRm, true); } - public static void EmitVectorUnaryOpZx(AilEmitterCtx context, Action emit) + public static void EmitVectorUnaryOpZx(ILEmitterCtx context, Action emit) { EmitVectorOp(context, emit, OperFlags.Rn, false); } - public static void EmitVectorBinaryOpZx(AilEmitterCtx context, Action emit) + public static void EmitVectorBinaryOpZx(ILEmitterCtx context, Action emit) { EmitVectorOp(context, emit, OperFlags.RnRm, false); } - public static void EmitVectorTernaryOpZx(AilEmitterCtx context, Action emit) + public static void EmitVectorTernaryOpZx(ILEmitterCtx context, Action emit) { EmitVectorOp(context, emit, OperFlags.RdRnRm, false); } - public static void EmitVectorOp(AilEmitterCtx context, Action emit, OperFlags opers, bool signed) + public static void EmitVectorOp(ILEmitterCtx context, Action emit, OperFlags opers, bool signed) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int bytes = op.GetBitsCount() >> 3; int elems = bytes >> op.Size; @@ -644,7 +644,7 @@ namespace ChocolArm64.Instruction if (rm) { - EmitVectorExtract(context, ((AOpCodeSimdReg)op).Rm, index, op.Size, signed); + EmitVectorExtract(context, ((OpCodeSimdReg)op).Rm, index, op.Size, signed); } emit(); @@ -652,36 +652,36 @@ namespace ChocolArm64.Instruction EmitVectorInsert(context, op.Rd, index, op.Size); } - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - public static void EmitVectorBinaryOpByElemSx(AilEmitterCtx context, Action emit) + public static void EmitVectorBinaryOpByElemSx(ILEmitterCtx context, Action emit) { - AOpCodeSimdRegElem op = (AOpCodeSimdRegElem)context.CurrOp; + OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp; EmitVectorOpByElem(context, emit, op.Index, false, true); } - public static void EmitVectorBinaryOpByElemZx(AilEmitterCtx context, Action emit) + public static void EmitVectorBinaryOpByElemZx(ILEmitterCtx context, Action emit) { - AOpCodeSimdRegElem op = (AOpCodeSimdRegElem)context.CurrOp; + OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp; EmitVectorOpByElem(context, emit, op.Index, false, false); } - public static void EmitVectorTernaryOpByElemZx(AilEmitterCtx context, Action emit) + public static void EmitVectorTernaryOpByElemZx(ILEmitterCtx context, Action emit) { - AOpCodeSimdRegElem op = (AOpCodeSimdRegElem)context.CurrOp; + OpCodeSimdRegElem op = (OpCodeSimdRegElem)context.CurrOp; EmitVectorOpByElem(context, emit, op.Index, true, false); } - public static void EmitVectorOpByElem(AilEmitterCtx context, Action emit, int elem, bool ternary, bool signed) + public static void EmitVectorOpByElem(ILEmitterCtx context, Action emit, int elem, bool ternary, bool signed) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; int bytes = op.GetBitsCount() >> 3; int elems = bytes >> op.Size; @@ -707,25 +707,25 @@ namespace ChocolArm64.Instruction context.EmitLdvectmp(); context.EmitStvec(op.Rd); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - public static void EmitVectorImmUnaryOp(AilEmitterCtx context, Action emit) + public static void EmitVectorImmUnaryOp(ILEmitterCtx context, Action emit) { EmitVectorImmOp(context, emit, false); } - public static void EmitVectorImmBinaryOp(AilEmitterCtx context, Action emit) + public static void EmitVectorImmBinaryOp(ILEmitterCtx context, Action emit) { EmitVectorImmOp(context, emit, true); } - public static void EmitVectorImmOp(AilEmitterCtx context, Action emit, bool binary) + public static void EmitVectorImmOp(ILEmitterCtx context, Action emit, bool binary) { - AOpCodeSimdImm op = (AOpCodeSimdImm)context.CurrOp; + OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp; int bytes = op.GetBitsCount() >> 3; int elems = bytes >> op.Size; @@ -744,29 +744,29 @@ namespace ChocolArm64.Instruction EmitVectorInsert(context, op.Rd, index, op.Size); } - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - public static void EmitVectorWidenRmBinaryOpSx(AilEmitterCtx context, Action emit) + public static void EmitVectorWidenRmBinaryOpSx(ILEmitterCtx context, Action emit) { EmitVectorWidenRmBinaryOp(context, emit, true); } - public static void EmitVectorWidenRmBinaryOpZx(AilEmitterCtx context, Action emit) + public static void EmitVectorWidenRmBinaryOpZx(ILEmitterCtx context, Action emit) { EmitVectorWidenRmBinaryOp(context, emit, false); } - public static void EmitVectorWidenRmBinaryOp(AilEmitterCtx context, Action emit, bool signed) + public static void EmitVectorWidenRmBinaryOp(ILEmitterCtx context, Action emit, bool signed) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; int elems = 8 >> op.Size; - int part = op.RegisterSize == ARegisterSize.Simd128 ? elems : 0; + int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0; for (int index = 0; index < elems; index++) { @@ -782,33 +782,33 @@ namespace ChocolArm64.Instruction context.EmitStvec(op.Rd); } - public static void EmitVectorWidenRnRmBinaryOpSx(AilEmitterCtx context, Action emit) + public static void EmitVectorWidenRnRmBinaryOpSx(ILEmitterCtx context, Action emit) { EmitVectorWidenRnRmOp(context, emit, false, true); } - public static void EmitVectorWidenRnRmBinaryOpZx(AilEmitterCtx context, Action emit) + public static void EmitVectorWidenRnRmBinaryOpZx(ILEmitterCtx context, Action emit) { EmitVectorWidenRnRmOp(context, emit, false, false); } - public static void EmitVectorWidenRnRmTernaryOpSx(AilEmitterCtx context, Action emit) + public static void EmitVectorWidenRnRmTernaryOpSx(ILEmitterCtx context, Action emit) { EmitVectorWidenRnRmOp(context, emit, true, true); } - public static void EmitVectorWidenRnRmTernaryOpZx(AilEmitterCtx context, Action emit) + public static void EmitVectorWidenRnRmTernaryOpZx(ILEmitterCtx context, Action emit) { EmitVectorWidenRnRmOp(context, emit, true, false); } - public static void EmitVectorWidenRnRmOp(AilEmitterCtx context, Action emit, bool ternary, bool signed) + public static void EmitVectorWidenRnRmOp(ILEmitterCtx context, Action emit, bool ternary, bool signed) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; int elems = 8 >> op.Size; - int part = op.RegisterSize == ARegisterSize.Simd128 ? elems : 0; + int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0; for (int index = 0; index < elems; index++) { @@ -829,19 +829,19 @@ namespace ChocolArm64.Instruction context.EmitStvec(op.Rd); } - public static void EmitVectorPairwiseOpSx(AilEmitterCtx context, Action emit) + public static void EmitVectorPairwiseOpSx(ILEmitterCtx context, Action emit) { EmitVectorPairwiseOp(context, emit, true); } - public static void EmitVectorPairwiseOpZx(AilEmitterCtx context, Action emit) + public static void EmitVectorPairwiseOpZx(ILEmitterCtx context, Action emit) { EmitVectorPairwiseOp(context, emit, false); } - public static void EmitVectorPairwiseOp(AilEmitterCtx context, Action emit, bool signed) + public static void EmitVectorPairwiseOp(ILEmitterCtx context, Action emit, bool signed) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; int words = op.GetBitsCount() >> 4; int pairs = words >> op.Size; @@ -867,15 +867,15 @@ namespace ChocolArm64.Instruction context.EmitLdvectmp(); context.EmitStvec(op.Rd); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - public static void EmitVectorPairwiseOpF(AilEmitterCtx context, Action emit) + public static void EmitVectorPairwiseOpF(ILEmitterCtx context, Action emit) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; int sizeF = op.Size & 1; @@ -903,7 +903,7 @@ namespace ChocolArm64.Instruction context.EmitLdvectmp(); context.EmitStvec(op.Rd); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -927,19 +927,19 @@ namespace ChocolArm64.Instruction VectorZx = 0 } - public static void EmitScalarSaturatingUnaryOpSx(AilEmitterCtx context, Action emit) + public static void EmitScalarSaturatingUnaryOpSx(ILEmitterCtx context, Action emit) { EmitSaturatingUnaryOpSx(context, emit, SaturatingFlags.ScalarSx); } - public static void EmitVectorSaturatingUnaryOpSx(AilEmitterCtx context, Action emit) + public static void EmitVectorSaturatingUnaryOpSx(ILEmitterCtx context, Action emit) { EmitSaturatingUnaryOpSx(context, emit, SaturatingFlags.VectorSx); } - public static void EmitSaturatingUnaryOpSx(AilEmitterCtx context, Action emit, SaturatingFlags flags) + public static void EmitSaturatingUnaryOpSx(ILEmitterCtx context, Action emit, SaturatingFlags flags) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; bool scalar = (flags & SaturatingFlags.Scalar) != 0; @@ -972,35 +972,35 @@ namespace ChocolArm64.Instruction context.EmitLdvectmp(); context.EmitStvec(op.Rd); - if ((op.RegisterSize == ARegisterSize.Simd64) || scalar) + if ((op.RegisterSize == RegisterSize.Simd64) || scalar) { EmitVectorZeroUpper(context, op.Rd); } } - public static void EmitScalarSaturatingBinaryOpSx(AilEmitterCtx context, SaturatingFlags flags) + public static void EmitScalarSaturatingBinaryOpSx(ILEmitterCtx context, SaturatingFlags flags) { EmitSaturatingBinaryOp(context, () => { }, SaturatingFlags.ScalarSx | flags); } - public static void EmitScalarSaturatingBinaryOpZx(AilEmitterCtx context, SaturatingFlags flags) + public static void EmitScalarSaturatingBinaryOpZx(ILEmitterCtx context, SaturatingFlags flags) { EmitSaturatingBinaryOp(context, () => { }, SaturatingFlags.ScalarZx | flags); } - public static void EmitVectorSaturatingBinaryOpSx(AilEmitterCtx context, SaturatingFlags flags) + public static void EmitVectorSaturatingBinaryOpSx(ILEmitterCtx context, SaturatingFlags flags) { EmitSaturatingBinaryOp(context, () => { }, SaturatingFlags.VectorSx | flags); } - public static void EmitVectorSaturatingBinaryOpZx(AilEmitterCtx context, SaturatingFlags flags) + public static void EmitVectorSaturatingBinaryOpZx(ILEmitterCtx context, SaturatingFlags flags) { EmitSaturatingBinaryOp(context, () => { }, SaturatingFlags.VectorZx | flags); } - public static void EmitSaturatingBinaryOp(AilEmitterCtx context, Action emit, SaturatingFlags flags) + public static void EmitSaturatingBinaryOp(ILEmitterCtx context, Action emit, SaturatingFlags flags) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; bool scalar = (flags & SaturatingFlags.Scalar) != 0; bool signed = (flags & SaturatingFlags.Signed) != 0; @@ -1023,7 +1023,7 @@ namespace ChocolArm64.Instruction for (int index = 0; index < elems; index++) { EmitVectorExtract(context, op.Rn, index, op.Size, signed); - EmitVectorExtract(context, ((AOpCodeSimdReg)op).Rm, index, op.Size, signed); + EmitVectorExtract(context, ((OpCodeSimdReg)op).Rm, index, op.Size, signed); if (op.Size <= 2) { @@ -1072,7 +1072,7 @@ namespace ChocolArm64.Instruction for (int index = 0; index < elems; index++) { EmitVectorExtract(context, op.Rn, index, op.Size, signed); - EmitVectorExtract(context, ((AOpCodeSimdReg)op).Rm, index, op.Size, signed); + EmitVectorExtract(context, ((OpCodeSimdReg)op).Rm, index, op.Size, signed); emit(); @@ -1085,7 +1085,7 @@ namespace ChocolArm64.Instruction context.EmitLdvectmp(); context.EmitStvec(op.Rd); - if ((op.RegisterSize == ARegisterSize.Simd64) || scalar) + if ((op.RegisterSize == RegisterSize.Simd64) || scalar) { EmitVectorZeroUpper(context, op.Rd); } @@ -1107,9 +1107,9 @@ namespace ChocolArm64.Instruction VectorZxZx = 0 } - public static void EmitSaturatingNarrowOp(AilEmitterCtx context, SaturatingNarrowFlags flags) + public static void EmitSaturatingNarrowOp(ILEmitterCtx context, SaturatingNarrowFlags flags) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; bool scalar = (flags & SaturatingNarrowFlags.Scalar) != 0; bool signedSrc = (flags & SaturatingNarrowFlags.SignedSrc) != 0; @@ -1117,7 +1117,7 @@ namespace ChocolArm64.Instruction int elems = !scalar ? 8 >> op.Size : 1; - int part = !scalar && (op.RegisterSize == ARegisterSize.Simd128) ? elems : 0; + int part = !scalar && (op.RegisterSize == RegisterSize.Simd128) ? elems : 0; if (scalar) { @@ -1150,7 +1150,7 @@ namespace ChocolArm64.Instruction // TSrc (16bit, 32bit, 64bit; signed, unsigned) > TDst (8bit, 16bit, 32bit; signed, unsigned). public static void EmitSatQ( - AilEmitterCtx context, + ILEmitterCtx context, int sizeDst, bool signedSrc, bool signedDst) @@ -1161,95 +1161,95 @@ namespace ChocolArm64.Instruction } context.EmitLdc_I4(sizeDst); - context.EmitLdarg(ATranslatedSub.StateArgIdx); + context.EmitLdarg(TranslatedSub.StateArgIdx); if (signedSrc) { - ASoftFallback.EmitCall(context, signedDst - ? nameof(ASoftFallback.SignedSrcSignedDstSatQ) - : nameof(ASoftFallback.SignedSrcUnsignedDstSatQ)); + SoftFallback.EmitCall(context, signedDst + ? nameof(SoftFallback.SignedSrcSignedDstSatQ) + : nameof(SoftFallback.SignedSrcUnsignedDstSatQ)); } else { - ASoftFallback.EmitCall(context, signedDst - ? nameof(ASoftFallback.UnsignedSrcSignedDstSatQ) - : nameof(ASoftFallback.UnsignedSrcUnsignedDstSatQ)); + SoftFallback.EmitCall(context, signedDst + ? nameof(SoftFallback.UnsignedSrcSignedDstSatQ) + : nameof(SoftFallback.UnsignedSrcUnsignedDstSatQ)); } } // TSrc (64bit) == TDst (64bit); signed. - public static void EmitUnarySignedSatQAbsOrNeg(AilEmitterCtx context) + public static void EmitUnarySignedSatQAbsOrNeg(ILEmitterCtx context) { - if (((AOpCodeSimd)context.CurrOp).Size < 3) + if (((OpCodeSimd)context.CurrOp).Size < 3) { throw new InvalidOperationException(); } - context.EmitLdarg(ATranslatedSub.StateArgIdx); + context.EmitLdarg(TranslatedSub.StateArgIdx); - ASoftFallback.EmitCall(context, nameof(ASoftFallback.UnarySignedSatQAbsOrNeg)); + SoftFallback.EmitCall(context, nameof(SoftFallback.UnarySignedSatQAbsOrNeg)); } // TSrcs (64bit) == TDst (64bit); signed, unsigned. - public static void EmitBinarySatQAdd(AilEmitterCtx context, bool signed) + public static void EmitBinarySatQAdd(ILEmitterCtx context, bool signed) { - if (((AOpCodeSimdReg)context.CurrOp).Size < 3) + if (((OpCodeSimdReg)context.CurrOp).Size < 3) { throw new InvalidOperationException(); } - context.EmitLdarg(ATranslatedSub.StateArgIdx); + context.EmitLdarg(TranslatedSub.StateArgIdx); - ASoftFallback.EmitCall(context, signed - ? nameof(ASoftFallback.BinarySignedSatQAdd) - : nameof(ASoftFallback.BinaryUnsignedSatQAdd)); + SoftFallback.EmitCall(context, signed + ? nameof(SoftFallback.BinarySignedSatQAdd) + : nameof(SoftFallback.BinaryUnsignedSatQAdd)); } // TSrcs (64bit) == TDst (64bit); signed, unsigned. - public static void EmitBinarySatQSub(AilEmitterCtx context, bool signed) + public static void EmitBinarySatQSub(ILEmitterCtx context, bool signed) { - if (((AOpCodeSimdReg)context.CurrOp).Size < 3) + if (((OpCodeSimdReg)context.CurrOp).Size < 3) { throw new InvalidOperationException(); } - context.EmitLdarg(ATranslatedSub.StateArgIdx); + context.EmitLdarg(TranslatedSub.StateArgIdx); - ASoftFallback.EmitCall(context, signed - ? nameof(ASoftFallback.BinarySignedSatQSub) - : nameof(ASoftFallback.BinaryUnsignedSatQSub)); + SoftFallback.EmitCall(context, signed + ? nameof(SoftFallback.BinarySignedSatQSub) + : nameof(SoftFallback.BinaryUnsignedSatQSub)); } // TSrcs (64bit) == TDst (64bit); signed, unsigned. - public static void EmitBinarySatQAccumulate(AilEmitterCtx context, bool signed) + public static void EmitBinarySatQAccumulate(ILEmitterCtx context, bool signed) { - if (((AOpCodeSimd)context.CurrOp).Size < 3) + if (((OpCodeSimd)context.CurrOp).Size < 3) { throw new InvalidOperationException(); } - context.EmitLdarg(ATranslatedSub.StateArgIdx); + context.EmitLdarg(TranslatedSub.StateArgIdx); - ASoftFallback.EmitCall(context, signed - ? nameof(ASoftFallback.BinarySignedSatQAcc) - : nameof(ASoftFallback.BinaryUnsignedSatQAcc)); + SoftFallback.EmitCall(context, signed + ? nameof(SoftFallback.BinarySignedSatQAcc) + : nameof(SoftFallback.BinaryUnsignedSatQAcc)); } - public static void EmitScalarSet(AilEmitterCtx context, int reg, int size) + public static void EmitScalarSet(ILEmitterCtx context, int reg, int size) { EmitVectorZeroAll(context, reg); EmitVectorInsert(context, reg, 0, size); } - public static void EmitScalarSetF(AilEmitterCtx context, int reg, int size) + public static void EmitScalarSetF(ILEmitterCtx context, int reg, int size) { - if (AOptimizations.UseSse41 && size == 0) + if (Optimizations.UseSse41 && size == 0) { //If the type is float, we can perform insertion and //zero the upper bits with a single instruction (INSERTPS); context.EmitLdvec(reg); - AVectorHelper.EmitCall(context, nameof(AVectorHelper.Sse41VectorInsertScalarSingle)); + VectorHelper.EmitCall(context, nameof(VectorHelper.Sse41VectorInsertScalarSingle)); context.EmitStvec(reg); } @@ -1260,17 +1260,17 @@ namespace ChocolArm64.Instruction } } - public static void EmitVectorExtractSx(AilEmitterCtx context, int reg, int index, int size) + public static void EmitVectorExtractSx(ILEmitterCtx context, int reg, int index, int size) { EmitVectorExtract(context, reg, index, size, true); } - public static void EmitVectorExtractZx(AilEmitterCtx context, int reg, int index, int size) + public static void EmitVectorExtractZx(ILEmitterCtx context, int reg, int index, int size) { EmitVectorExtract(context, reg, index, size, false); } - public static void EmitVectorExtract(AilEmitterCtx context, int reg, int index, int size, bool signed) + public static void EmitVectorExtract(ILEmitterCtx context, int reg, int index, int size, bool signed) { ThrowIfInvalid(index, size); @@ -1278,12 +1278,12 @@ namespace ChocolArm64.Instruction context.EmitLdc_I4(index); context.EmitLdc_I4(size); - AVectorHelper.EmitCall(context, signed - ? nameof(AVectorHelper.VectorExtractIntSx) - : nameof(AVectorHelper.VectorExtractIntZx)); + VectorHelper.EmitCall(context, signed + ? nameof(VectorHelper.VectorExtractIntSx) + : nameof(VectorHelper.VectorExtractIntZx)); } - public static void EmitVectorExtractF(AilEmitterCtx context, int reg, int index, int size) + public static void EmitVectorExtractF(ILEmitterCtx context, int reg, int index, int size) { ThrowIfInvalidF(index, size); @@ -1292,11 +1292,11 @@ namespace ChocolArm64.Instruction if (size == 0) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorExtractSingle)); + VectorHelper.EmitCall(context, nameof(VectorHelper.VectorExtractSingle)); } else if (size == 1) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorExtractDouble)); + VectorHelper.EmitCall(context, nameof(VectorHelper.VectorExtractDouble)); } else { @@ -1304,11 +1304,11 @@ namespace ChocolArm64.Instruction } } - public static void EmitVectorZeroAll(AilEmitterCtx context, int rd) + public static void EmitVectorZeroAll(ILEmitterCtx context, int rd) { - if (AOptimizations.UseSse2) + if (Optimizations.UseSse2) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorSingleZero)); + VectorHelper.EmitCall(context, nameof(VectorHelper.VectorSingleZero)); context.EmitStvec(rd); } @@ -1319,19 +1319,19 @@ namespace ChocolArm64.Instruction } } - public static void EmitVectorZeroLower(AilEmitterCtx context, int rd) + public static void EmitVectorZeroLower(ILEmitterCtx context, int rd) { EmitVectorInsert(context, rd, 0, 3, 0); } - public static void EmitVectorZeroLowerTmp(AilEmitterCtx context) + public static void EmitVectorZeroLowerTmp(ILEmitterCtx context) { EmitVectorInsertTmp(context, 0, 3, 0); } - public static void EmitVectorZeroUpper(AilEmitterCtx context, int reg) + public static void EmitVectorZeroUpper(ILEmitterCtx context, int reg) { - if (AOptimizations.UseSse2) + if (Optimizations.UseSse2) { //TODO: Use MoveScalar once it is fixed, as of the //time of writing it just crashes the JIT. @@ -1357,16 +1357,16 @@ namespace ChocolArm64.Instruction } } - public static void EmitVectorZero32_128(AilEmitterCtx context, int reg) + public static void EmitVectorZero32_128(ILEmitterCtx context, int reg) { context.EmitLdvec(reg); - AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorZero32_128)); + VectorHelper.EmitCall(context, nameof(VectorHelper.VectorZero32_128)); context.EmitStvec(reg); } - public static void EmitVectorInsert(AilEmitterCtx context, int reg, int index, int size) + public static void EmitVectorInsert(ILEmitterCtx context, int reg, int index, int size) { ThrowIfInvalid(index, size); @@ -1374,12 +1374,12 @@ namespace ChocolArm64.Instruction context.EmitLdc_I4(index); context.EmitLdc_I4(size); - AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorInsertInt)); + VectorHelper.EmitCall(context, nameof(VectorHelper.VectorInsertInt)); context.EmitStvec(reg); } - public static void EmitVectorInsertTmp(AilEmitterCtx context, int index, int size) + public static void EmitVectorInsertTmp(ILEmitterCtx context, int index, int size) { ThrowIfInvalid(index, size); @@ -1387,12 +1387,12 @@ namespace ChocolArm64.Instruction context.EmitLdc_I4(index); context.EmitLdc_I4(size); - AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorInsertInt)); + VectorHelper.EmitCall(context, nameof(VectorHelper.VectorInsertInt)); context.EmitStvectmp(); } - public static void EmitVectorInsert(AilEmitterCtx context, int reg, int index, int size, long value) + public static void EmitVectorInsert(ILEmitterCtx context, int reg, int index, int size, long value) { ThrowIfInvalid(index, size); @@ -1401,12 +1401,12 @@ namespace ChocolArm64.Instruction context.EmitLdc_I4(index); context.EmitLdc_I4(size); - AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorInsertInt)); + VectorHelper.EmitCall(context, nameof(VectorHelper.VectorInsertInt)); context.EmitStvec(reg); } - public static void EmitVectorInsertTmp(AilEmitterCtx context, int index, int size, long value) + public static void EmitVectorInsertTmp(ILEmitterCtx context, int index, int size, long value) { ThrowIfInvalid(index, size); @@ -1415,12 +1415,12 @@ namespace ChocolArm64.Instruction context.EmitLdc_I4(index); context.EmitLdc_I4(size); - AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorInsertInt)); + VectorHelper.EmitCall(context, nameof(VectorHelper.VectorInsertInt)); context.EmitStvectmp(); } - public static void EmitVectorInsertF(AilEmitterCtx context, int reg, int index, int size) + public static void EmitVectorInsertF(ILEmitterCtx context, int reg, int index, int size) { ThrowIfInvalidF(index, size); @@ -1429,11 +1429,11 @@ namespace ChocolArm64.Instruction if (size == 0) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorInsertSingle)); + VectorHelper.EmitCall(context, nameof(VectorHelper.VectorInsertSingle)); } else if (size == 1) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorInsertDouble)); + VectorHelper.EmitCall(context, nameof(VectorHelper.VectorInsertDouble)); } else { @@ -1443,7 +1443,7 @@ namespace ChocolArm64.Instruction context.EmitStvec(reg); } - public static void EmitVectorInsertTmpF(AilEmitterCtx context, int index, int size) + public static void EmitVectorInsertTmpF(ILEmitterCtx context, int index, int size) { ThrowIfInvalidF(index, size); @@ -1452,11 +1452,11 @@ namespace ChocolArm64.Instruction if (size == 0) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorInsertSingle)); + VectorHelper.EmitCall(context, nameof(VectorHelper.VectorInsertSingle)); } else if (size == 1) { - AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorInsertDouble)); + VectorHelper.EmitCall(context, nameof(VectorHelper.VectorInsertDouble)); } else { diff --git a/ChocolArm64/Instruction/AInstEmitSimdLogical.cs b/ChocolArm64/Instruction/InstEmitSimdLogical.cs similarity index 77% rename from ChocolArm64/Instruction/AInstEmitSimdLogical.cs rename to ChocolArm64/Instruction/InstEmitSimdLogical.cs index a06eee453d..9b0e3b97c3 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdLogical.cs +++ b/ChocolArm64/Instruction/InstEmitSimdLogical.cs @@ -9,11 +9,11 @@ using static ChocolArm64.Instruction.AInstEmitSimdHelper; namespace ChocolArm64.Instruction { - static partial class AInstEmit + static partial class InstEmit { - public static void And_V(AilEmitterCtx context) + public static void And_V(ILEmitterCtx context) { - if (AOptimizations.UseSse2) + if (Optimizations.UseSse2) { EmitSse2Op(context, nameof(Sse2.And)); } @@ -23,11 +23,11 @@ namespace ChocolArm64.Instruction } } - public static void Bic_V(AilEmitterCtx context) + public static void Bic_V(ILEmitterCtx context) { - if (AOptimizations.UseSse2) + if (Optimizations.UseSse2) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; EmitLdvecWithUnsignedCast(context, op.Rm, op.Size); EmitLdvecWithUnsignedCast(context, op.Rn, op.Size); @@ -42,7 +42,7 @@ namespace ChocolArm64.Instruction EmitStvecWithUnsignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -57,7 +57,7 @@ namespace ChocolArm64.Instruction } } - public static void Bic_Vi(AilEmitterCtx context) + public static void Bic_Vi(ILEmitterCtx context) { EmitVectorImmBinaryOp(context, () => { @@ -66,21 +66,21 @@ namespace ChocolArm64.Instruction }); } - public static void Bif_V(AilEmitterCtx context) + public static void Bif_V(ILEmitterCtx context) { EmitBitBif(context, true); } - public static void Bit_V(AilEmitterCtx context) + public static void Bit_V(ILEmitterCtx context) { EmitBitBif(context, false); } - private static void EmitBitBif(AilEmitterCtx context, bool notRm) + private static void EmitBitBif(ILEmitterCtx context, bool notRm) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; - if (AOptimizations.UseSse2) + if (Optimizations.UseSse2) { Type[] types = new Type[] { @@ -104,7 +104,7 @@ namespace ChocolArm64.Instruction EmitStvecWithUnsignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -137,18 +137,18 @@ namespace ChocolArm64.Instruction EmitVectorInsert(context, op.Rd, index, op.Size); } - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } } - public static void Bsl_V(AilEmitterCtx context) + public static void Bsl_V(ILEmitterCtx context) { - if (AOptimizations.UseSse2) + if (Optimizations.UseSse2) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; Type[] types = new Type[] { @@ -171,7 +171,7 @@ namespace ChocolArm64.Instruction EmitStvecWithUnsignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -193,9 +193,9 @@ namespace ChocolArm64.Instruction } } - public static void Eor_V(AilEmitterCtx context) + public static void Eor_V(ILEmitterCtx context) { - if (AOptimizations.UseSse2) + if (Optimizations.UseSse2) { EmitSse2Op(context, nameof(Sse2.Xor)); } @@ -205,12 +205,12 @@ namespace ChocolArm64.Instruction } } - public static void Not_V(AilEmitterCtx context) + public static void Not_V(ILEmitterCtx context) { EmitVectorUnaryOpZx(context, () => context.Emit(OpCodes.Not)); } - public static void Orn_V(AilEmitterCtx context) + public static void Orn_V(ILEmitterCtx context) { EmitVectorBinaryOpZx(context, () => { @@ -219,9 +219,9 @@ namespace ChocolArm64.Instruction }); } - public static void Orr_V(AilEmitterCtx context) + public static void Orr_V(ILEmitterCtx context) { - if (AOptimizations.UseSse2) + if (Optimizations.UseSse2) { EmitSse2Op(context, nameof(Sse2.Or)); } @@ -231,16 +231,16 @@ namespace ChocolArm64.Instruction } } - public static void Orr_Vi(AilEmitterCtx context) + public static void Orr_Vi(ILEmitterCtx context) { EmitVectorImmBinaryOp(context, () => context.Emit(OpCodes.Or)); } - public static void Rbit_V(AilEmitterCtx context) + public static void Rbit_V(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; - int elems = op.RegisterSize == ARegisterSize.Simd128 ? 16 : 8; + int elems = op.RegisterSize == RegisterSize.Simd128 ? 16 : 8; for (int index = 0; index < elems; index++) { @@ -248,37 +248,37 @@ namespace ChocolArm64.Instruction context.Emit(OpCodes.Conv_U4); - ASoftFallback.EmitCall(context, nameof(ASoftFallback.ReverseBits8)); + SoftFallback.EmitCall(context, nameof(SoftFallback.ReverseBits8)); context.Emit(OpCodes.Conv_U8); EmitVectorInsert(context, op.Rd, index, 0); } - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - public static void Rev16_V(AilEmitterCtx context) + public static void Rev16_V(ILEmitterCtx context) { EmitRev_V(context, containerSize: 1); } - public static void Rev32_V(AilEmitterCtx context) + public static void Rev32_V(ILEmitterCtx context) { EmitRev_V(context, containerSize: 2); } - public static void Rev64_V(AilEmitterCtx context) + public static void Rev64_V(ILEmitterCtx context) { EmitRev_V(context, containerSize: 3); } - private static void EmitRev_V(AilEmitterCtx context, int containerSize) + private static void EmitRev_V(ILEmitterCtx context, int containerSize) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; if (op.Size >= containerSize) { @@ -302,7 +302,7 @@ namespace ChocolArm64.Instruction context.EmitLdvectmp(); context.EmitStvec(op.Rd); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } diff --git a/ChocolArm64/Instruction/AInstEmitSimdMemory.cs b/ChocolArm64/Instruction/InstEmitSimdMemory.cs similarity index 78% rename from ChocolArm64/Instruction/AInstEmitSimdMemory.cs rename to ChocolArm64/Instruction/InstEmitSimdMemory.cs index 0fd35ac4b6..3bf149f410 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdMemory.cs +++ b/ChocolArm64/Instruction/InstEmitSimdMemory.cs @@ -4,36 +4,36 @@ using ChocolArm64.Translation; using System; using System.Reflection.Emit; -using static ChocolArm64.Instruction.AInstEmitMemoryHelper; +using static ChocolArm64.Instruction.InstEmitMemoryHelper; using static ChocolArm64.Instruction.AInstEmitSimdHelper; namespace ChocolArm64.Instruction { - static partial class AInstEmit + static partial class InstEmit { - public static void Ld__Vms(AilEmitterCtx context) + public static void Ld__Vms(ILEmitterCtx context) { EmitSimdMemMs(context, isLoad: true); } - public static void Ld__Vss(AilEmitterCtx context) + public static void Ld__Vss(ILEmitterCtx context) { EmitSimdMemSs(context, isLoad: true); } - public static void St__Vms(AilEmitterCtx context) + public static void St__Vms(ILEmitterCtx context) { EmitSimdMemMs(context, isLoad: false); } - public static void St__Vss(AilEmitterCtx context) + public static void St__Vss(ILEmitterCtx context) { EmitSimdMemSs(context, isLoad: false); } - private static void EmitSimdMemMs(AilEmitterCtx context, bool isLoad) + private static void EmitSimdMemMs(ILEmitterCtx context, bool isLoad) { - AOpCodeSimdMemMs op = (AOpCodeSimdMemMs)context.CurrOp; + OpCodeSimdMemMs op = (OpCodeSimdMemMs)context.CurrOp; int offset = 0; @@ -45,7 +45,7 @@ namespace ChocolArm64.Instruction if (isLoad) { - context.EmitLdarg(ATranslatedSub.MemoryArgIdx); + context.EmitLdarg(TranslatedSub.MemoryArgIdx); context.EmitLdint(op.Rn); context.EmitLdc_I8(offset); @@ -55,14 +55,14 @@ namespace ChocolArm64.Instruction EmitVectorInsert(context, rtt, elem, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64 && elem == op.Elems - 1) + if (op.RegisterSize == RegisterSize.Simd64 && elem == op.Elems - 1) { EmitVectorZeroUpper(context, rtt); } } else { - context.EmitLdarg(ATranslatedSub.MemoryArgIdx); + context.EmitLdarg(TranslatedSub.MemoryArgIdx); context.EmitLdint(op.Rn); context.EmitLdc_I8(offset); @@ -82,15 +82,15 @@ namespace ChocolArm64.Instruction } } - private static void EmitSimdMemSs(AilEmitterCtx context, bool isLoad) + private static void EmitSimdMemSs(ILEmitterCtx context, bool isLoad) { - AOpCodeSimdMemSs op = (AOpCodeSimdMemSs)context.CurrOp; + OpCodeSimdMemSs op = (OpCodeSimdMemSs)context.CurrOp; int offset = 0; void EmitMemAddress() { - context.EmitLdarg(ATranslatedSub.MemoryArgIdx); + context.EmitLdarg(TranslatedSub.MemoryArgIdx); context.EmitLdint(op.Rn); context.EmitLdc_I8(offset); @@ -121,7 +121,7 @@ namespace ChocolArm64.Instruction EmitVectorInsert(context, rt, index, op.Size); } - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, rt); } @@ -162,9 +162,9 @@ namespace ChocolArm64.Instruction } } - private static void EmitSimdMemWBack(AilEmitterCtx context, int offset) + private static void EmitSimdMemWBack(ILEmitterCtx context, int offset) { - AOpCodeMemReg op = (AOpCodeMemReg)context.CurrOp; + OpCodeMemReg op = (OpCodeMemReg)context.CurrOp; context.EmitLdint(op.Rn); diff --git a/ChocolArm64/Instruction/AInstEmitSimdMove.cs b/ChocolArm64/Instruction/InstEmitSimdMove.cs similarity index 70% rename from ChocolArm64/Instruction/AInstEmitSimdMove.cs rename to ChocolArm64/Instruction/InstEmitSimdMove.cs index 31a8f70af5..a0bb2f2b2c 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdMove.cs +++ b/ChocolArm64/Instruction/InstEmitSimdMove.cs @@ -9,13 +9,13 @@ using static ChocolArm64.Instruction.AInstEmitSimdHelper; namespace ChocolArm64.Instruction { - static partial class AInstEmit + static partial class InstEmit { - public static void Dup_Gp(AilEmitterCtx context) + public static void Dup_Gp(ILEmitterCtx context) { - AOpCodeSimdIns op = (AOpCodeSimdIns)context.CurrOp; + OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp; - if (AOptimizations.UseSse2) + if (Optimizations.UseSse2) { context.EmitLdintzr(op.Rn); @@ -32,7 +32,7 @@ namespace ChocolArm64.Instruction EmitStvecWithUnsignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -49,25 +49,25 @@ namespace ChocolArm64.Instruction EmitVectorInsert(context, op.Rd, index, op.Size); } - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } } - public static void Dup_S(AilEmitterCtx context) + public static void Dup_S(ILEmitterCtx context) { - AOpCodeSimdIns op = (AOpCodeSimdIns)context.CurrOp; + OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp; EmitVectorExtractZx(context, op.Rn, op.DstIndex, op.Size); EmitScalarSet(context, op.Rd, op.Size); } - public static void Dup_V(AilEmitterCtx context) + public static void Dup_V(ILEmitterCtx context) { - AOpCodeSimdIns op = (AOpCodeSimdIns)context.CurrOp; + OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp; int bytes = op.GetBitsCount() >> 3; int elems = bytes >> op.Size; @@ -79,15 +79,15 @@ namespace ChocolArm64.Instruction EmitVectorInsert(context, op.Rd, index, op.Size); } - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - public static void Ext_V(AilEmitterCtx context) + public static void Ext_V(ILEmitterCtx context) { - AOpCodeSimdExt op = (AOpCodeSimdExt)context.CurrOp; + OpCodeSimdExt op = (OpCodeSimdExt)context.CurrOp; context.EmitLdvec(op.Rd); context.EmitStvectmp(); @@ -112,18 +112,18 @@ namespace ChocolArm64.Instruction context.EmitLdvectmp(); context.EmitStvec(op.Rd); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - public static void Fcsel_S(AilEmitterCtx context) + public static void Fcsel_S(ILEmitterCtx context) { - AOpCodeSimdFcond op = (AOpCodeSimdFcond)context.CurrOp; + OpCodeSimdFcond op = (OpCodeSimdFcond)context.CurrOp; - AilLabel lblTrue = new AilLabel(); - AilLabel lblEnd = new AilLabel(); + ILLabel lblTrue = new ILLabel(); + ILLabel lblEnd = new ILLabel(); context.EmitCondBranch(lblTrue, op.Cond); @@ -140,9 +140,9 @@ namespace ChocolArm64.Instruction EmitScalarSetF(context, op.Rd, op.Size); } - public static void Fmov_Ftoi(AilEmitterCtx context) + public static void Fmov_Ftoi(ILEmitterCtx context) { - AOpCodeSimdCvt op = (AOpCodeSimdCvt)context.CurrOp; + OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp; EmitVectorExtractZx(context, op.Rn, 0, 3); @@ -151,9 +151,9 @@ namespace ChocolArm64.Instruction context.EmitStintzr(op.Rd); } - public static void Fmov_Ftoi1(AilEmitterCtx context) + public static void Fmov_Ftoi1(ILEmitterCtx context) { - AOpCodeSimdCvt op = (AOpCodeSimdCvt)context.CurrOp; + OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp; EmitVectorExtractZx(context, op.Rn, 1, 3); @@ -162,9 +162,9 @@ namespace ChocolArm64.Instruction context.EmitStintzr(op.Rd); } - public static void Fmov_Itof(AilEmitterCtx context) + public static void Fmov_Itof(ILEmitterCtx context) { - AOpCodeSimdCvt op = (AOpCodeSimdCvt)context.CurrOp; + OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp; context.EmitLdintzr(op.Rn); @@ -173,9 +173,9 @@ namespace ChocolArm64.Instruction EmitScalarSet(context, op.Rd, 3); } - public static void Fmov_Itof1(AilEmitterCtx context) + public static void Fmov_Itof1(ILEmitterCtx context) { - AOpCodeSimdCvt op = (AOpCodeSimdCvt)context.CurrOp; + OpCodeSimdCvt op = (OpCodeSimdCvt)context.CurrOp; context.EmitLdintzr(op.Rn); @@ -184,29 +184,29 @@ namespace ChocolArm64.Instruction EmitVectorInsert(context, op.Rd, 1, 3); } - public static void Fmov_S(AilEmitterCtx context) + public static void Fmov_S(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; EmitVectorExtractF(context, op.Rn, 0, op.Size); EmitScalarSetF(context, op.Rd, op.Size); } - public static void Fmov_Si(AilEmitterCtx context) + public static void Fmov_Si(ILEmitterCtx context) { - AOpCodeSimdFmov op = (AOpCodeSimdFmov)context.CurrOp; + OpCodeSimdFmov op = (OpCodeSimdFmov)context.CurrOp; context.EmitLdc_I8(op.Imm); EmitScalarSet(context, op.Rd, op.Size + 2); } - public static void Fmov_V(AilEmitterCtx context) + public static void Fmov_V(ILEmitterCtx context) { - AOpCodeSimdImm op = (AOpCodeSimdImm)context.CurrOp; + OpCodeSimdImm op = (OpCodeSimdImm)context.CurrOp; - int elems = op.RegisterSize == ARegisterSize.Simd128 ? 4 : 2; + int elems = op.RegisterSize == RegisterSize.Simd128 ? 4 : 2; for (int index = 0; index < (elems >> op.Size); index++) { @@ -215,43 +215,43 @@ namespace ChocolArm64.Instruction EmitVectorInsert(context, op.Rd, index, op.Size + 2); } - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - public static void Ins_Gp(AilEmitterCtx context) + public static void Ins_Gp(ILEmitterCtx context) { - AOpCodeSimdIns op = (AOpCodeSimdIns)context.CurrOp; + OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp; context.EmitLdintzr(op.Rn); EmitVectorInsert(context, op.Rd, op.DstIndex, op.Size); } - public static void Ins_V(AilEmitterCtx context) + public static void Ins_V(ILEmitterCtx context) { - AOpCodeSimdIns op = (AOpCodeSimdIns)context.CurrOp; + OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp; EmitVectorExtractZx(context, op.Rn, op.SrcIndex, op.Size); EmitVectorInsert(context, op.Rd, op.DstIndex, op.Size); } - public static void Movi_V(AilEmitterCtx context) + public static void Movi_V(ILEmitterCtx context) { EmitVectorImmUnaryOp(context, () => { }); } - public static void Mvni_V(AilEmitterCtx context) + public static void Mvni_V(ILEmitterCtx context) { EmitVectorImmUnaryOp(context, () => context.Emit(OpCodes.Not)); } - public static void Smov_S(AilEmitterCtx context) + public static void Smov_S(ILEmitterCtx context) { - AOpCodeSimdIns op = (AOpCodeSimdIns)context.CurrOp; + OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp; EmitVectorExtractSx(context, op.Rn, op.DstIndex, op.Size); @@ -260,9 +260,9 @@ namespace ChocolArm64.Instruction context.EmitStintzr(op.Rd); } - public static void Tbl_V(AilEmitterCtx context) + public static void Tbl_V(ILEmitterCtx context) { - AOpCodeSimdTbl op = (AOpCodeSimdTbl)context.CurrOp; + OpCodeSimdTbl op = (OpCodeSimdTbl)context.CurrOp; context.EmitLdvec(op.Rm); @@ -273,21 +273,21 @@ namespace ChocolArm64.Instruction switch (op.Size) { - case 1: AVectorHelper.EmitCall(context, - nameof(AVectorHelper.Tbl1_V64), - nameof(AVectorHelper.Tbl1_V128)); break; + case 1: VectorHelper.EmitCall(context, + nameof(VectorHelper.Tbl1_V64), + nameof(VectorHelper.Tbl1_V128)); break; - case 2: AVectorHelper.EmitCall(context, - nameof(AVectorHelper.Tbl2_V64), - nameof(AVectorHelper.Tbl2_V128)); break; + case 2: VectorHelper.EmitCall(context, + nameof(VectorHelper.Tbl2_V64), + nameof(VectorHelper.Tbl2_V128)); break; - case 3: AVectorHelper.EmitCall(context, - nameof(AVectorHelper.Tbl3_V64), - nameof(AVectorHelper.Tbl3_V128)); break; + case 3: VectorHelper.EmitCall(context, + nameof(VectorHelper.Tbl3_V64), + nameof(VectorHelper.Tbl3_V128)); break; - case 4: AVectorHelper.EmitCall(context, - nameof(AVectorHelper.Tbl4_V64), - nameof(AVectorHelper.Tbl4_V128)); break; + case 4: VectorHelper.EmitCall(context, + nameof(VectorHelper.Tbl4_V64), + nameof(VectorHelper.Tbl4_V128)); break; default: throw new InvalidOperationException(); } @@ -295,51 +295,51 @@ namespace ChocolArm64.Instruction context.EmitStvec(op.Rd); } - public static void Trn1_V(AilEmitterCtx context) + public static void Trn1_V(ILEmitterCtx context) { EmitVectorTranspose(context, part: 0); } - public static void Trn2_V(AilEmitterCtx context) + public static void Trn2_V(ILEmitterCtx context) { EmitVectorTranspose(context, part: 1); } - public static void Umov_S(AilEmitterCtx context) + public static void Umov_S(ILEmitterCtx context) { - AOpCodeSimdIns op = (AOpCodeSimdIns)context.CurrOp; + OpCodeSimdIns op = (OpCodeSimdIns)context.CurrOp; EmitVectorExtractZx(context, op.Rn, op.DstIndex, op.Size); context.EmitStintzr(op.Rd); } - public static void Uzp1_V(AilEmitterCtx context) + public static void Uzp1_V(ILEmitterCtx context) { EmitVectorUnzip(context, part: 0); } - public static void Uzp2_V(AilEmitterCtx context) + public static void Uzp2_V(ILEmitterCtx context) { EmitVectorUnzip(context, part: 1); } - public static void Xtn_V(AilEmitterCtx context) + public static void Xtn_V(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int elems = 8 >> op.Size; - int part = op.RegisterSize == ARegisterSize.Simd128 ? elems : 0; + int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0; - if (AOptimizations.UseSse41 && op.Size < 2) + if (Optimizations.UseSse41 && op.Size < 2) { void EmitZeroVector() { switch (op.Size) { - case 0: AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorInt16Zero)); break; - case 1: AVectorHelper.EmitCall(context, nameof(AVectorHelper.VectorInt32Zero)); break; + case 0: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorInt16Zero)); break; + case 1: VectorHelper.EmitCall(context, nameof(VectorHelper.VectorInt32Zero)); break; } } @@ -420,29 +420,29 @@ namespace ChocolArm64.Instruction } } - public static void Zip1_V(AilEmitterCtx context) + public static void Zip1_V(ILEmitterCtx context) { EmitVectorZip(context, part: 0); } - public static void Zip2_V(AilEmitterCtx context) + public static void Zip2_V(ILEmitterCtx context) { EmitVectorZip(context, part: 1); } - private static void EmitIntZeroUpperIfNeeded(AilEmitterCtx context) + private static void EmitIntZeroUpperIfNeeded(ILEmitterCtx context) { - if (context.CurrOp.RegisterSize == ARegisterSize.Int32 || - context.CurrOp.RegisterSize == ARegisterSize.Simd64) + if (context.CurrOp.RegisterSize == RegisterSize.Int32 || + context.CurrOp.RegisterSize == RegisterSize.Simd64) { context.Emit(OpCodes.Conv_U4); context.Emit(OpCodes.Conv_U8); } } - private static void EmitVectorTranspose(AilEmitterCtx context, int part) + private static void EmitVectorTranspose(ILEmitterCtx context, int part) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; int words = op.GetBitsCount() >> 4; int pairs = words >> op.Size; @@ -461,15 +461,15 @@ namespace ChocolArm64.Instruction context.EmitLdvectmp(); context.EmitStvec(op.Rd); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - private static void EmitVectorUnzip(AilEmitterCtx context, int part) + private static void EmitVectorUnzip(ILEmitterCtx context, int part) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; int words = op.GetBitsCount() >> 4; int pairs = words >> op.Size; @@ -488,17 +488,17 @@ namespace ChocolArm64.Instruction context.EmitLdvectmp(); context.EmitStvec(op.Rd); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - private static void EmitVectorZip(AilEmitterCtx context, int part) + private static void EmitVectorZip(ILEmitterCtx context, int part) { - AOpCodeSimdReg op = (AOpCodeSimdReg)context.CurrOp; + OpCodeSimdReg op = (OpCodeSimdReg)context.CurrOp; - if (AOptimizations.UseSse2) + if (Optimizations.UseSse2) { EmitLdvecWithUnsignedCast(context, op.Rn, op.Size); EmitLdvecWithUnsignedCast(context, op.Rm, op.Size); @@ -509,13 +509,13 @@ namespace ChocolArm64.Instruction VectorUIntTypesPerSizeLog2[op.Size] }; - string name = part == 0 || (part != 0 && op.RegisterSize == ARegisterSize.Simd64) + string name = part == 0 || (part != 0 && op.RegisterSize == RegisterSize.Simd64) ? nameof(Sse2.UnpackLow) : nameof(Sse2.UnpackHigh); context.EmitCall(typeof(Sse2).GetMethod(name, types)); - if (op.RegisterSize == ARegisterSize.Simd64 && part != 0) + if (op.RegisterSize == RegisterSize.Simd64 && part != 0) { context.EmitLdc_I4(8); @@ -526,7 +526,7 @@ namespace ChocolArm64.Instruction EmitStvecWithUnsignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64 && part == 0) + if (op.RegisterSize == RegisterSize.Simd64 && part == 0) { EmitVectorZeroUpper(context, op.Rd); } @@ -552,7 +552,7 @@ namespace ChocolArm64.Instruction context.EmitLdvectmp(); context.EmitStvec(op.Rd); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } diff --git a/ChocolArm64/Instruction/AInstEmitSimdShift.cs b/ChocolArm64/Instruction/InstEmitSimdShift.cs similarity index 77% rename from ChocolArm64/Instruction/AInstEmitSimdShift.cs rename to ChocolArm64/Instruction/InstEmitSimdShift.cs index 8e0f81ed1f..46c5fa303b 100644 --- a/ChocolArm64/Instruction/AInstEmitSimdShift.cs +++ b/ChocolArm64/Instruction/InstEmitSimdShift.cs @@ -11,16 +11,16 @@ using static ChocolArm64.Instruction.AInstEmitSimdHelper; namespace ChocolArm64.Instruction { - static partial class AInstEmit + static partial class InstEmit { - public static void Rshrn_V(AilEmitterCtx context) + public static void Rshrn_V(ILEmitterCtx context) { EmitVectorShrImmNarrowOpZx(context, round: true); } - public static void Shl_S(AilEmitterCtx context) + public static void Shl_S(ILEmitterCtx context) { - AOpCodeSimdShImm op = (AOpCodeSimdShImm)context.CurrOp; + OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; EmitScalarUnaryOpZx(context, () => { @@ -30,11 +30,11 @@ namespace ChocolArm64.Instruction }); } - public static void Shl_V(AilEmitterCtx context) + public static void Shl_V(ILEmitterCtx context) { - AOpCodeSimdShImm op = (AOpCodeSimdShImm)context.CurrOp; + OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; - if (AOptimizations.UseSse2 && op.Size > 0) + if (Optimizations.UseSse2 && op.Size > 0) { Type[] typesSll = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], typeof(byte) }; @@ -45,7 +45,7 @@ namespace ChocolArm64.Instruction EmitStvecWithUnsignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -61,23 +61,23 @@ namespace ChocolArm64.Instruction } } - public static void Shll_V(AilEmitterCtx context) + public static void Shll_V(ILEmitterCtx context) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int shift = 8 << op.Size; EmitVectorShImmWidenBinaryZx(context, () => context.Emit(OpCodes.Shl), shift); } - public static void Shrn_V(AilEmitterCtx context) + public static void Shrn_V(ILEmitterCtx context) { EmitVectorShrImmNarrowOpZx(context, round: false); } - public static void Sli_V(AilEmitterCtx context) + public static void Sli_V(ILEmitterCtx context) { - AOpCodeSimdShImm op = (AOpCodeSimdShImm)context.CurrOp; + OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; int bytes = op.GetBitsCount() >> 3; int elems = bytes >> op.Size; @@ -104,62 +104,62 @@ namespace ChocolArm64.Instruction EmitVectorInsert(context, op.Rd, index, op.Size); } - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } } - public static void Sqrshrn_S(AilEmitterCtx context) + public static void Sqrshrn_S(ILEmitterCtx context) { EmitRoundShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.ScalarSxSx); } - public static void Sqrshrn_V(AilEmitterCtx context) + public static void Sqrshrn_V(ILEmitterCtx context) { EmitRoundShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.VectorSxSx); } - public static void Sqrshrun_S(AilEmitterCtx context) + public static void Sqrshrun_S(ILEmitterCtx context) { EmitRoundShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.ScalarSxZx); } - public static void Sqrshrun_V(AilEmitterCtx context) + public static void Sqrshrun_V(ILEmitterCtx context) { EmitRoundShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.VectorSxZx); } - public static void Sqshrn_S(AilEmitterCtx context) + public static void Sqshrn_S(ILEmitterCtx context) { EmitShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.ScalarSxSx); } - public static void Sqshrn_V(AilEmitterCtx context) + public static void Sqshrn_V(ILEmitterCtx context) { EmitShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.VectorSxSx); } - public static void Sqshrun_S(AilEmitterCtx context) + public static void Sqshrun_S(ILEmitterCtx context) { EmitShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.ScalarSxZx); } - public static void Sqshrun_V(AilEmitterCtx context) + public static void Sqshrun_V(ILEmitterCtx context) { EmitShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.VectorSxZx); } - public static void Srshr_S(AilEmitterCtx context) + public static void Srshr_S(ILEmitterCtx context) { EmitScalarShrImmOpSx(context, ShrImmFlags.Round); } - public static void Srshr_V(AilEmitterCtx context) + public static void Srshr_V(ILEmitterCtx context) { - AOpCodeSimdShImm op = (AOpCodeSimdShImm)context.CurrOp; + OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; - if (AOptimizations.UseSse2 && op.Size > 0 + if (Optimizations.UseSse2 && op.Size > 0 && op.Size < 3) { Type[] typesShs = new Type[] { VectorIntTypesPerSizeLog2[op.Size], typeof(byte) }; @@ -188,7 +188,7 @@ namespace ChocolArm64.Instruction EmitStvecWithSignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -199,16 +199,16 @@ namespace ChocolArm64.Instruction } } - public static void Srsra_S(AilEmitterCtx context) + public static void Srsra_S(ILEmitterCtx context) { EmitScalarShrImmOpSx(context, ShrImmFlags.Round | ShrImmFlags.Accumulate); } - public static void Srsra_V(AilEmitterCtx context) + public static void Srsra_V(ILEmitterCtx context) { - AOpCodeSimdShImm op = (AOpCodeSimdShImm)context.CurrOp; + OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; - if (AOptimizations.UseSse2 && op.Size > 0 + if (Optimizations.UseSse2 && op.Size > 0 && op.Size < 3) { Type[] typesShs = new Type[] { VectorIntTypesPerSizeLog2[op.Size], typeof(byte) }; @@ -239,7 +239,7 @@ namespace ChocolArm64.Instruction EmitStvecWithSignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -250,28 +250,28 @@ namespace ChocolArm64.Instruction } } - public static void Sshl_V(AilEmitterCtx context) + public static void Sshl_V(ILEmitterCtx context) { EmitVectorShl(context, signed: true); } - public static void Sshll_V(AilEmitterCtx context) + public static void Sshll_V(ILEmitterCtx context) { - AOpCodeSimdShImm op = (AOpCodeSimdShImm)context.CurrOp; + OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; EmitVectorShImmWidenBinarySx(context, () => context.Emit(OpCodes.Shl), GetImmShl(op)); } - public static void Sshr_S(AilEmitterCtx context) + public static void Sshr_S(ILEmitterCtx context) { EmitShrImmOp(context, ShrImmFlags.ScalarSx); } - public static void Sshr_V(AilEmitterCtx context) + public static void Sshr_V(ILEmitterCtx context) { - AOpCodeSimdShImm op = (AOpCodeSimdShImm)context.CurrOp; + OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; - if (AOptimizations.UseSse2 && op.Size > 0 + if (Optimizations.UseSse2 && op.Size > 0 && op.Size < 3) { Type[] typesSra = new Type[] { VectorIntTypesPerSizeLog2[op.Size], typeof(byte) }; @@ -283,7 +283,7 @@ namespace ChocolArm64.Instruction EmitStvecWithSignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -294,16 +294,16 @@ namespace ChocolArm64.Instruction } } - public static void Ssra_S(AilEmitterCtx context) + public static void Ssra_S(ILEmitterCtx context) { EmitScalarShrImmOpSx(context, ShrImmFlags.Accumulate); } - public static void Ssra_V(AilEmitterCtx context) + public static void Ssra_V(ILEmitterCtx context) { - AOpCodeSimdShImm op = (AOpCodeSimdShImm)context.CurrOp; + OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; - if (AOptimizations.UseSse2 && op.Size > 0 + if (Optimizations.UseSse2 && op.Size > 0 && op.Size < 3) { Type[] typesSra = new Type[] { VectorIntTypesPerSizeLog2[op.Size], typeof(byte) }; @@ -319,7 +319,7 @@ namespace ChocolArm64.Instruction EmitStvecWithSignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -330,36 +330,36 @@ namespace ChocolArm64.Instruction } } - public static void Uqrshrn_S(AilEmitterCtx context) + public static void Uqrshrn_S(ILEmitterCtx context) { EmitRoundShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.ScalarZxZx); } - public static void Uqrshrn_V(AilEmitterCtx context) + public static void Uqrshrn_V(ILEmitterCtx context) { EmitRoundShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.VectorZxZx); } - public static void Uqshrn_S(AilEmitterCtx context) + public static void Uqshrn_S(ILEmitterCtx context) { EmitShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.ScalarZxZx); } - public static void Uqshrn_V(AilEmitterCtx context) + public static void Uqshrn_V(ILEmitterCtx context) { EmitShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.VectorZxZx); } - public static void Urshr_S(AilEmitterCtx context) + public static void Urshr_S(ILEmitterCtx context) { EmitScalarShrImmOpZx(context, ShrImmFlags.Round); } - public static void Urshr_V(AilEmitterCtx context) + public static void Urshr_V(ILEmitterCtx context) { - AOpCodeSimdShImm op = (AOpCodeSimdShImm)context.CurrOp; + OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; - if (AOptimizations.UseSse2 && op.Size > 0) + if (Optimizations.UseSse2 && op.Size > 0) { Type[] typesShs = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], typeof(byte) }; Type[] typesAdd = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], VectorUIntTypesPerSizeLog2[op.Size] }; @@ -387,7 +387,7 @@ namespace ChocolArm64.Instruction EmitStvecWithUnsignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -398,16 +398,16 @@ namespace ChocolArm64.Instruction } } - public static void Ursra_S(AilEmitterCtx context) + public static void Ursra_S(ILEmitterCtx context) { EmitScalarShrImmOpZx(context, ShrImmFlags.Round | ShrImmFlags.Accumulate); } - public static void Ursra_V(AilEmitterCtx context) + public static void Ursra_V(ILEmitterCtx context) { - AOpCodeSimdShImm op = (AOpCodeSimdShImm)context.CurrOp; + OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; - if (AOptimizations.UseSse2 && op.Size > 0) + if (Optimizations.UseSse2 && op.Size > 0) { Type[] typesShs = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], typeof(byte) }; Type[] typesAdd = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], VectorUIntTypesPerSizeLog2[op.Size] }; @@ -437,7 +437,7 @@ namespace ChocolArm64.Instruction EmitStvecWithUnsignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -448,28 +448,28 @@ namespace ChocolArm64.Instruction } } - public static void Ushl_V(AilEmitterCtx context) + public static void Ushl_V(ILEmitterCtx context) { EmitVectorShl(context, signed: false); } - public static void Ushll_V(AilEmitterCtx context) + public static void Ushll_V(ILEmitterCtx context) { - AOpCodeSimdShImm op = (AOpCodeSimdShImm)context.CurrOp; + OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; EmitVectorShImmWidenBinaryZx(context, () => context.Emit(OpCodes.Shl), GetImmShl(op)); } - public static void Ushr_S(AilEmitterCtx context) + public static void Ushr_S(ILEmitterCtx context) { EmitShrImmOp(context, ShrImmFlags.ScalarZx); } - public static void Ushr_V(AilEmitterCtx context) + public static void Ushr_V(ILEmitterCtx context) { - AOpCodeSimdShImm op = (AOpCodeSimdShImm)context.CurrOp; + OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; - if (AOptimizations.UseSse2 && op.Size > 0) + if (Optimizations.UseSse2 && op.Size > 0) { Type[] typesSrl = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], typeof(byte) }; @@ -480,7 +480,7 @@ namespace ChocolArm64.Instruction EmitStvecWithUnsignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -491,16 +491,16 @@ namespace ChocolArm64.Instruction } } - public static void Usra_S(AilEmitterCtx context) + public static void Usra_S(ILEmitterCtx context) { EmitScalarShrImmOpZx(context, ShrImmFlags.Accumulate); } - public static void Usra_V(AilEmitterCtx context) + public static void Usra_V(ILEmitterCtx context) { - AOpCodeSimdShImm op = (AOpCodeSimdShImm)context.CurrOp; + OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; - if (AOptimizations.UseSse2 && op.Size > 0) + if (Optimizations.UseSse2 && op.Size > 0) { Type[] typesSrl = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], typeof(byte) }; Type[] typesAdd = new Type[] { VectorUIntTypesPerSizeLog2[op.Size], VectorUIntTypesPerSizeLog2[op.Size] }; @@ -515,7 +515,7 @@ namespace ChocolArm64.Instruction EmitStvecWithUnsignedCast(context, op.Rd, op.Size); - if (op.RegisterSize == ARegisterSize.Simd64) + if (op.RegisterSize == RegisterSize.Simd64) { EmitVectorZeroUpper(context, op.Rd); } @@ -526,21 +526,21 @@ namespace ChocolArm64.Instruction } } - private static void EmitVectorShl(AilEmitterCtx context, bool signed) + private static void EmitVectorShl(ILEmitterCtx context, bool signed) { //This instruction shifts the value on vector A by the number of bits //specified on the signed, lower 8 bits of vector B. If the shift value //is greater or equal to the data size of each lane, then the result is zero. //Additionally, negative shifts produces right shifts by the negated shift value. - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int maxShift = 8 << op.Size; Action emit = () => { - AilLabel lblShl = new AilLabel(); - AilLabel lblZero = new AilLabel(); - AilLabel lblEnd = new AilLabel(); + ILLabel lblShl = new ILLabel(); + ILLabel lblZero = new ILLabel(); + ILLabel lblEnd = new ILLabel(); void EmitShift(OpCode ilOp) { @@ -605,29 +605,29 @@ namespace ChocolArm64.Instruction VectorZx = 0 } - private static void EmitScalarShrImmOpSx(AilEmitterCtx context, ShrImmFlags flags) + private static void EmitScalarShrImmOpSx(ILEmitterCtx context, ShrImmFlags flags) { EmitShrImmOp(context, ShrImmFlags.ScalarSx | flags); } - private static void EmitScalarShrImmOpZx(AilEmitterCtx context, ShrImmFlags flags) + private static void EmitScalarShrImmOpZx(ILEmitterCtx context, ShrImmFlags flags) { EmitShrImmOp(context, ShrImmFlags.ScalarZx | flags); } - private static void EmitVectorShrImmOpSx(AilEmitterCtx context, ShrImmFlags flags) + private static void EmitVectorShrImmOpSx(ILEmitterCtx context, ShrImmFlags flags) { EmitShrImmOp(context, ShrImmFlags.VectorSx | flags); } - private static void EmitVectorShrImmOpZx(AilEmitterCtx context, ShrImmFlags flags) + private static void EmitVectorShrImmOpZx(ILEmitterCtx context, ShrImmFlags flags) { EmitShrImmOp(context, ShrImmFlags.VectorZx | flags); } - private static void EmitShrImmOp(AilEmitterCtx context, ShrImmFlags flags) + private static void EmitShrImmOp(ILEmitterCtx context, ShrImmFlags flags) { - AOpCodeSimdShImm op = (AOpCodeSimdShImm)context.CurrOp; + OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; bool scalar = (flags & ShrImmFlags.Scalar) != 0; bool signed = (flags & ShrImmFlags.Signed) != 0; @@ -676,15 +676,15 @@ namespace ChocolArm64.Instruction context.EmitLdvectmp(); context.EmitStvec(op.Rd); - if ((op.RegisterSize == ARegisterSize.Simd64) || scalar) + if ((op.RegisterSize == RegisterSize.Simd64) || scalar) { EmitVectorZeroUpper(context, op.Rd); } } - private static void EmitVectorShrImmNarrowOpZx(AilEmitterCtx context, bool round) + private static void EmitVectorShrImmNarrowOpZx(ILEmitterCtx context, bool round) { - AOpCodeSimdShImm op = (AOpCodeSimdShImm)context.CurrOp; + OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; int shift = GetImmShr(op); @@ -692,7 +692,7 @@ namespace ChocolArm64.Instruction int elems = 8 >> op.Size; - int part = op.RegisterSize == ARegisterSize.Simd128 ? elems : 0; + int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0; if (part != 0) { @@ -745,14 +745,14 @@ namespace ChocolArm64.Instruction VectorZxZx = 0 } - private static void EmitRoundShrImmSaturatingNarrowOp(AilEmitterCtx context, ShrImmSaturatingNarrowFlags flags) + private static void EmitRoundShrImmSaturatingNarrowOp(ILEmitterCtx context, ShrImmSaturatingNarrowFlags flags) { EmitShrImmSaturatingNarrowOp(context, ShrImmSaturatingNarrowFlags.Round | flags); } - private static void EmitShrImmSaturatingNarrowOp(AilEmitterCtx context, ShrImmSaturatingNarrowFlags flags) + private static void EmitShrImmSaturatingNarrowOp(ILEmitterCtx context, ShrImmSaturatingNarrowFlags flags) { - AOpCodeSimdShImm op = (AOpCodeSimdShImm)context.CurrOp; + OpCodeSimdShImm op = (OpCodeSimdShImm)context.CurrOp; bool scalar = (flags & ShrImmSaturatingNarrowFlags.Scalar) != 0; bool signedSrc = (flags & ShrImmSaturatingNarrowFlags.SignedSrc) != 0; @@ -765,7 +765,7 @@ namespace ChocolArm64.Instruction int elems = !scalar ? 8 >> op.Size : 1; - int part = !scalar && (op.RegisterSize == ARegisterSize.Simd128) ? elems : 0; + int part = !scalar && (op.RegisterSize == RegisterSize.Simd128) ? elems : 0; if (scalar) { @@ -816,7 +816,7 @@ namespace ChocolArm64.Instruction // Dst_64 = (Int(Src_64, Signed) + RoundConst) >> Shift; private static void EmitShrImm_64( - AilEmitterCtx context, + ILEmitterCtx context, bool signed, long roundConst, int shift) @@ -824,28 +824,28 @@ namespace ChocolArm64.Instruction context.EmitLdc_I8(roundConst); context.EmitLdc_I4(shift); - ASoftFallback.EmitCall(context, signed - ? nameof(ASoftFallback.SignedShrImm_64) - : nameof(ASoftFallback.UnsignedShrImm_64)); + SoftFallback.EmitCall(context, signed + ? nameof(SoftFallback.SignedShrImm_64) + : nameof(SoftFallback.UnsignedShrImm_64)); } - private static void EmitVectorShImmWidenBinarySx(AilEmitterCtx context, Action emit, int imm) + private static void EmitVectorShImmWidenBinarySx(ILEmitterCtx context, Action emit, int imm) { EmitVectorShImmWidenBinaryOp(context, emit, imm, true); } - private static void EmitVectorShImmWidenBinaryZx(AilEmitterCtx context, Action emit, int imm) + private static void EmitVectorShImmWidenBinaryZx(ILEmitterCtx context, Action emit, int imm) { EmitVectorShImmWidenBinaryOp(context, emit, imm, false); } - private static void EmitVectorShImmWidenBinaryOp(AilEmitterCtx context, Action emit, int imm, bool signed) + private static void EmitVectorShImmWidenBinaryOp(ILEmitterCtx context, Action emit, int imm, bool signed) { - AOpCodeSimd op = (AOpCodeSimd)context.CurrOp; + OpCodeSimd op = (OpCodeSimd)context.CurrOp; int elems = 8 >> op.Size; - int part = op.RegisterSize == ARegisterSize.Simd128 ? elems : 0; + int part = op.RegisterSize == RegisterSize.Simd128 ? elems : 0; for (int index = 0; index < elems; index++) { diff --git a/ChocolArm64/Instruction/AInstEmitSystem.cs b/ChocolArm64/Instruction/InstEmitSystem.cs similarity index 81% rename from ChocolArm64/Instruction/AInstEmitSystem.cs rename to ChocolArm64/Instruction/InstEmitSystem.cs index 41186cb801..f6602726d5 100644 --- a/ChocolArm64/Instruction/AInstEmitSystem.cs +++ b/ChocolArm64/Instruction/InstEmitSystem.cs @@ -7,23 +7,23 @@ using System.Reflection.Emit; namespace ChocolArm64.Instruction { - static partial class AInstEmit + static partial class InstEmit { - public static void Hint(AilEmitterCtx context) + public static void Hint(ILEmitterCtx context) { //Execute as no-op. } - public static void Isb(AilEmitterCtx context) + public static void Isb(ILEmitterCtx context) { //Execute as no-op. } - public static void Mrs(AilEmitterCtx context) + public static void Mrs(ILEmitterCtx context) { - AOpCodeSystem op = (AOpCodeSystem)context.CurrOp; + OpCodeSystem op = (OpCodeSystem)context.CurrOp; - context.EmitLdarg(ATranslatedSub.StateArgIdx); + context.EmitLdarg(TranslatedSub.StateArgIdx); string propName; @@ -54,11 +54,11 @@ namespace ChocolArm64.Instruction context.EmitStintzr(op.Rt); } - public static void Msr(AilEmitterCtx context) + public static void Msr(ILEmitterCtx context) { - AOpCodeSystem op = (AOpCodeSystem)context.CurrOp; + OpCodeSystem op = (OpCodeSystem)context.CurrOp; - context.EmitLdarg(ATranslatedSub.StateArgIdx); + context.EmitLdarg(TranslatedSub.StateArgIdx); context.EmitLdintzr(op.Rt); string propName; @@ -83,17 +83,17 @@ namespace ChocolArm64.Instruction context.EmitCallPropSet(typeof(AThreadState), propName); } - public static void Nop(AilEmitterCtx context) + public static void Nop(ILEmitterCtx context) { //Do nothing. } - public static void Sys(AilEmitterCtx context) + public static void Sys(ILEmitterCtx context) { //This instruction is used to do some operations on the CPU like cache invalidation, //address translation and the like. //We treat it as no-op here since we don't have any cache being emulated anyway. - AOpCodeSystem op = (AOpCodeSystem)context.CurrOp; + OpCodeSystem op = (OpCodeSystem)context.CurrOp; switch (GetPackedId(op)) { @@ -102,7 +102,7 @@ namespace ChocolArm64.Instruction //DC ZVA for (int offs = 0; offs < (4 << AThreadState.DczSizeLog2); offs += 8) { - context.EmitLdarg(ATranslatedSub.MemoryArgIdx); + context.EmitLdarg(TranslatedSub.MemoryArgIdx); context.EmitLdintzr(op.Rt); context.EmitLdc_I(offs); @@ -110,7 +110,7 @@ namespace ChocolArm64.Instruction context.EmitLdc_I8(0); - AInstEmitMemoryHelper.EmitWriteCall(context, 3); + InstEmitMemoryHelper.EmitWriteCall(context, 3); } break; @@ -122,7 +122,7 @@ namespace ChocolArm64.Instruction } } - private static int GetPackedId(AOpCodeSystem op) + private static int GetPackedId(OpCodeSystem op) { int id; diff --git a/ChocolArm64/Instruction/AInstEmitter.cs b/ChocolArm64/Instruction/InstEmitter.cs similarity index 55% rename from ChocolArm64/Instruction/AInstEmitter.cs rename to ChocolArm64/Instruction/InstEmitter.cs index 0343dc4c11..135e4e1335 100644 --- a/ChocolArm64/Instruction/AInstEmitter.cs +++ b/ChocolArm64/Instruction/InstEmitter.cs @@ -2,5 +2,5 @@ using ChocolArm64.Translation; namespace ChocolArm64.Instruction { - delegate void AInstEmitter(AilEmitterCtx context); + delegate void InstEmitter(ILEmitterCtx context); } \ No newline at end of file diff --git a/ChocolArm64/Instruction/AInstInterpreter.cs b/ChocolArm64/Instruction/InstInterpreter.cs similarity index 56% rename from ChocolArm64/Instruction/AInstInterpreter.cs rename to ChocolArm64/Instruction/InstInterpreter.cs index 58e72a1a9a..839818e9f1 100644 --- a/ChocolArm64/Instruction/AInstInterpreter.cs +++ b/ChocolArm64/Instruction/InstInterpreter.cs @@ -4,5 +4,5 @@ using ChocolArm64.State; namespace ChocolArm64.Instruction { - delegate void AInstInterpreter(AThreadState state, AMemory memory, AOpCode opCode); + delegate void InstInterpreter(AThreadState state, AMemory memory, AOpCode opCode); } \ No newline at end of file diff --git a/ChocolArm64/Instruction/ASoftFallback.cs b/ChocolArm64/Instruction/SoftFallback.cs similarity index 92% rename from ChocolArm64/Instruction/ASoftFallback.cs rename to ChocolArm64/Instruction/SoftFallback.cs index 13222f46e7..ecb1807298 100644 --- a/ChocolArm64/Instruction/ASoftFallback.cs +++ b/ChocolArm64/Instruction/SoftFallback.cs @@ -7,13 +7,13 @@ using System.Runtime.Intrinsics.X86; namespace ChocolArm64.Instruction { - using static AVectorHelper; + using static VectorHelper; - static class ASoftFallback + static class SoftFallback { - public static void EmitCall(AilEmitterCtx context, string mthdName) + public static void EmitCall(ILEmitterCtx context, string mthdName) { - context.EmitCall(typeof(ASoftFallback), mthdName); + context.EmitCall(typeof(SoftFallback), mthdName); } #region "ShrImm_64" @@ -112,13 +112,13 @@ namespace ChocolArm64.Instruction if (op > tMaxValue) { - state.SetFpsrFlag(AFpsr.Qc); + state.SetFpsrFlag(Fpsr.Qc); return tMaxValue; } else if (op < tMinValue) { - state.SetFpsrFlag(AFpsr.Qc); + state.SetFpsrFlag(Fpsr.Qc); return tMinValue; } @@ -137,13 +137,13 @@ namespace ChocolArm64.Instruction if (op > (long)tMaxValue) { - state.SetFpsrFlag(AFpsr.Qc); + state.SetFpsrFlag(Fpsr.Qc); return tMaxValue; } else if (op < (long)tMinValue) { - state.SetFpsrFlag(AFpsr.Qc); + state.SetFpsrFlag(Fpsr.Qc); return tMinValue; } @@ -161,7 +161,7 @@ namespace ChocolArm64.Instruction if (op > (ulong)tMaxValue) { - state.SetFpsrFlag(AFpsr.Qc); + state.SetFpsrFlag(Fpsr.Qc); return tMaxValue; } @@ -179,7 +179,7 @@ namespace ChocolArm64.Instruction if (op > tMaxValue) { - state.SetFpsrFlag(AFpsr.Qc); + state.SetFpsrFlag(Fpsr.Qc); return tMaxValue; } @@ -193,7 +193,7 @@ namespace ChocolArm64.Instruction { if (op == long.MinValue) { - state.SetFpsrFlag(AFpsr.Qc); + state.SetFpsrFlag(Fpsr.Qc); return long.MaxValue; } @@ -209,7 +209,7 @@ namespace ChocolArm64.Instruction if ((~(op1 ^ op2) & (op1 ^ add)) < 0L) { - state.SetFpsrFlag(AFpsr.Qc); + state.SetFpsrFlag(Fpsr.Qc); if (op1 < 0L) { @@ -232,7 +232,7 @@ namespace ChocolArm64.Instruction if ((add < op1) && (add < op2)) { - state.SetFpsrFlag(AFpsr.Qc); + state.SetFpsrFlag(Fpsr.Qc); return ulong.MaxValue; } @@ -248,7 +248,7 @@ namespace ChocolArm64.Instruction if (((op1 ^ op2) & (op1 ^ sub)) < 0L) { - state.SetFpsrFlag(AFpsr.Qc); + state.SetFpsrFlag(Fpsr.Qc); if (op1 < 0L) { @@ -271,7 +271,7 @@ namespace ChocolArm64.Instruction if (op1 < op2) { - state.SetFpsrFlag(AFpsr.Qc); + state.SetFpsrFlag(Fpsr.Qc); return ulong.MinValue; } @@ -292,7 +292,7 @@ namespace ChocolArm64.Instruction if ((~op2 & add) < 0L) { - state.SetFpsrFlag(AFpsr.Qc); + state.SetFpsrFlag(Fpsr.Qc); return long.MaxValue; } @@ -306,7 +306,7 @@ namespace ChocolArm64.Instruction // Op1 from (ulong)long.MaxValue + 1UL to ulong.MaxValue // Op2 from (long)ulong.MinValue to long.MaxValue - state.SetFpsrFlag(AFpsr.Qc); + state.SetFpsrFlag(Fpsr.Qc); return long.MaxValue; } @@ -319,7 +319,7 @@ namespace ChocolArm64.Instruction if (add > (ulong)long.MaxValue) { - state.SetFpsrFlag(AFpsr.Qc); + state.SetFpsrFlag(Fpsr.Qc); return long.MaxValue; } @@ -341,7 +341,7 @@ namespace ChocolArm64.Instruction if ((add < (ulong)op1) && (add < op2)) { - state.SetFpsrFlag(AFpsr.Qc); + state.SetFpsrFlag(Fpsr.Qc); return ulong.MaxValue; } @@ -366,7 +366,7 @@ namespace ChocolArm64.Instruction if (add < (long)ulong.MinValue) { - state.SetFpsrFlag(AFpsr.Qc); + state.SetFpsrFlag(Fpsr.Qc); return ulong.MinValue; } @@ -503,7 +503,7 @@ namespace ChocolArm64.Instruction throw new PlatformNotSupportedException(); } - return ACryptoHelper.AesInvSubBytes(ACryptoHelper.AesInvShiftRows(Sse.Xor(value, roundKey))); + return CryptoHelper.AesInvSubBytes(CryptoHelper.AesInvShiftRows(Sse.Xor(value, roundKey))); } [MethodImpl(MethodImplOptions.AggressiveInlining)] @@ -514,19 +514,19 @@ namespace ChocolArm64.Instruction throw new PlatformNotSupportedException(); } - return ACryptoHelper.AesSubBytes(ACryptoHelper.AesShiftRows(Sse.Xor(value, roundKey))); + return CryptoHelper.AesSubBytes(CryptoHelper.AesShiftRows(Sse.Xor(value, roundKey))); } [MethodImpl(MethodImplOptions.AggressiveInlining)] public static Vector128 InverseMixColumns(Vector128 value) { - return ACryptoHelper.AesInvMixColumns(value); + return CryptoHelper.AesInvMixColumns(value); } [MethodImpl(MethodImplOptions.AggressiveInlining)] public static Vector128 MixColumns(Vector128 value) { - return ACryptoHelper.AesMixColumns(value); + return CryptoHelper.AesMixColumns(value); } #endregion @@ -596,7 +596,7 @@ namespace ChocolArm64.Instruction return hashAbcd; } - public static Vector128 Sha1SchedulePart1(Vector128 w0_3, Vector128 w4_7, Vector128 w8_11) + public static Vector128 Sha1SchedulePart1(Vector128 w03, Vector128 w47, Vector128 w811) { if (!Sse.IsSupported) { @@ -605,16 +605,16 @@ namespace ChocolArm64.Instruction Vector128 result = new Vector128(); - ulong t2 = VectorExtractIntZx(w4_7, (byte)0, 3); - ulong t1 = VectorExtractIntZx(w0_3, (byte)1, 3); + ulong t2 = VectorExtractIntZx(w47, (byte)0, 3); + ulong t1 = VectorExtractIntZx(w03, (byte)1, 3); result = VectorInsertInt((ulong)t1, result, (byte)0, 3); result = VectorInsertInt((ulong)t2, result, (byte)1, 3); - return Sse.Xor(result, Sse.Xor(w0_3, w8_11)); + return Sse.Xor(result, Sse.Xor(w03, w811)); } - public static Vector128 Sha1SchedulePart2(Vector128 tw0_3, Vector128 w12_15) + public static Vector128 Sha1SchedulePart2(Vector128 tw03, Vector128 w1215) { if (!Sse2.IsSupported) { @@ -623,8 +623,8 @@ namespace ChocolArm64.Instruction Vector128 result = new Vector128(); - Vector128 t = Sse.Xor(tw0_3, Sse.StaticCast( - Sse2.ShiftRightLogical128BitLane(Sse.StaticCast(w12_15), (byte)4))); + Vector128 t = Sse.Xor(tw03, Sse.StaticCast( + Sse2.ShiftRightLogical128BitLane(Sse.StaticCast(w1215), (byte)4))); uint tE0 = (uint)VectorExtractIntZx(t, (byte)0, 2); uint tE1 = (uint)VectorExtractIntZx(t, (byte)1, 2); @@ -687,17 +687,17 @@ namespace ChocolArm64.Instruction return Sha256Hash(hashAbcd, hashEfgh, wk, false); } - public static Vector128 Sha256SchedulePart1(Vector128 w0_3, Vector128 w4_7) + public static Vector128 Sha256SchedulePart1(Vector128 w03, Vector128 w47) { Vector128 result = new Vector128(); for (int e = 0; e <= 3; e++) { - uint elt = (uint)VectorExtractIntZx(e <= 2 ? w0_3 : w4_7, (byte)(e <= 2 ? e + 1 : 0), 2); + uint elt = (uint)VectorExtractIntZx(e <= 2 ? w03 : w47, (byte)(e <= 2 ? e + 1 : 0), 2); elt = elt.Ror(7) ^ elt.Ror(18) ^ elt.Lsr(3); - elt += (uint)VectorExtractIntZx(w0_3, (byte)e, 2); + elt += (uint)VectorExtractIntZx(w03, (byte)e, 2); result = VectorInsertInt((ulong)elt, result, (byte)e, 2); } @@ -705,11 +705,11 @@ namespace ChocolArm64.Instruction return result; } - public static Vector128 Sha256SchedulePart2(Vector128 w0_3, Vector128 w8_11, Vector128 w12_15) + public static Vector128 Sha256SchedulePart2(Vector128 w03, Vector128 w811, Vector128 w1215) { Vector128 result = new Vector128(); - ulong t1 = VectorExtractIntZx(w12_15, (byte)1, 3); + ulong t1 = VectorExtractIntZx(w1215, (byte)1, 3); for (int e = 0; e <= 1; e++) { @@ -717,8 +717,8 @@ namespace ChocolArm64.Instruction elt = elt.Ror(17) ^ elt.Ror(19) ^ elt.Lsr(10); - elt += (uint)VectorExtractIntZx(w0_3, (byte)e, 2); - elt += (uint)VectorExtractIntZx(w8_11, (byte)(e + 1), 2); + elt += (uint)VectorExtractIntZx(w03, (byte)e, 2); + elt += (uint)VectorExtractIntZx(w811, (byte)(e + 1), 2); result = VectorInsertInt((ulong)elt, result, (byte)e, 2); } @@ -731,8 +731,8 @@ namespace ChocolArm64.Instruction elt = elt.Ror(17) ^ elt.Ror(19) ^ elt.Lsr(10); - elt += (uint)VectorExtractIntZx(w0_3, (byte)e, 2); - elt += (uint)VectorExtractIntZx(e == 2 ? w8_11 : w12_15, (byte)(e == 2 ? 3 : 0), 2); + elt += (uint)VectorExtractIntZx(w03, (byte)e, 2); + elt += (uint)VectorExtractIntZx(e == 2 ? w811 : w1215, (byte)(e == 2 ? 3 : 0), 2); result = VectorInsertInt((ulong)elt, result, (byte)e, 2); } diff --git a/ChocolArm64/Instruction/ASoftFloat.cs b/ChocolArm64/Instruction/SoftFloat.cs similarity index 77% rename from ChocolArm64/Instruction/ASoftFloat.cs rename to ChocolArm64/Instruction/SoftFloat.cs index 64562c9a2d..a6deee690f 100644 --- a/ChocolArm64/Instruction/ASoftFloat.cs +++ b/ChocolArm64/Instruction/SoftFloat.cs @@ -5,9 +5,9 @@ using System.Runtime.CompilerServices; namespace ChocolArm64.Instruction { - static class ASoftFloat + static class SoftFloat { - static ASoftFloat() + static SoftFloat() { RecipEstimateTable = BuildRecipEstimateTable(); InvSqrtEstimateTable = BuildInvSqrtEstimateTable(); @@ -203,13 +203,13 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat16_32.FPConvert: State.Fpcr = 0x{state.Fpcr:X8}"); - double real = valueBits.FPUnpackCv(out FPType type, out bool sign, state); + double real = valueBits.FPUnpackCv(out FpType type, out bool sign, state); float result; - if (type == FPType.SNaN || type == FPType.QNaN) + if (type == FpType.SNaN || type == FpType.QNaN) { - if (state.GetFpcrFlag(AFpcr.Dn)) + if (state.GetFpcrFlag(Fpcr.Dn)) { result = FPDefaultNaN(); } @@ -218,16 +218,16 @@ namespace ChocolArm64.Instruction result = FPConvertNaN(valueBits); } - if (type == FPType.SNaN) + if (type == FpType.SNaN) { - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } } - else if (type == FPType.Infinity) + else if (type == FpType.Infinity) { result = FPInfinity(sign); } - else if (type == FPType.Zero) + else if (type == FpType.Zero) { result = FPZero(sign); } @@ -259,7 +259,7 @@ namespace ChocolArm64.Instruction return sign ? float.MinValue : float.MaxValue; } - private static double FPUnpackCv(this ushort valueBits, out FPType type, out bool sign, AThreadState state) + private static double FPUnpackCv(this ushort valueBits, out FpType type, out bool sign, AThreadState state) { sign = (~(uint)valueBits & 0x8000u) == 0u; @@ -272,31 +272,31 @@ namespace ChocolArm64.Instruction { if (frac16 == 0u) { - type = FPType.Zero; + type = FpType.Zero; real = 0d; } else { - type = FPType.Nonzero; // Subnormal. + type = FpType.Nonzero; // Subnormal. real = Math.Pow(2d, -14) * ((double)frac16 * Math.Pow(2d, -10)); } } - else if (exp16 == 0x1Fu && !state.GetFpcrFlag(AFpcr.Ahp)) + else if (exp16 == 0x1Fu && !state.GetFpcrFlag(Fpcr.Ahp)) { if (frac16 == 0u) { - type = FPType.Infinity; + type = FpType.Infinity; real = Math.Pow(2d, 1000); } else { - type = (~frac16 & 0x0200u) == 0u ? FPType.QNaN : FPType.SNaN; + type = (~frac16 & 0x0200u) == 0u ? FpType.QNaN : FpType.SNaN; real = 0d; } } else { - type = FPType.Nonzero; // Normal. + type = FpType.Nonzero; // Normal. real = Math.Pow(2d, (int)exp16 - 15) * (1d + (double)frac16 * Math.Pow(2d, -10)); } @@ -338,9 +338,9 @@ namespace ChocolArm64.Instruction exponent++; } - if (state.GetFpcrFlag(AFpcr.Fz) && exponent < minimumExp) + if (state.GetFpcrFlag(Fpcr.Fz) && exponent < minimumExp) { - state.SetFpsrFlag(AFpsr.Ufc); + state.SetFpsrFlag(Fpsr.Ufc); return FPZero(sign); } @@ -355,9 +355,9 @@ namespace ChocolArm64.Instruction uint intMant = (uint)Math.Floor(mantissa * Math.Pow(2d, f)); double error = mantissa * Math.Pow(2d, f) - (double)intMant; - if (biasedExp == 0u && (error != 0d || state.GetFpcrFlag(AFpcr.Ufe))) + if (biasedExp == 0u && (error != 0d || state.GetFpcrFlag(Fpcr.Ufe))) { - FPProcessException(AFpExc.Underflow, state); + FPProcessException(FpExc.Underflow, state); } bool overflowToInf; @@ -366,22 +366,22 @@ namespace ChocolArm64.Instruction switch (state.FPRoundingMode()) { default: - case ARoundMode.ToNearest: + case RoundMode.ToNearest: roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u)); overflowToInf = true; break; - case ARoundMode.TowardsPlusInfinity: + case RoundMode.TowardsPlusInfinity: roundUp = (error != 0d && !sign); overflowToInf = !sign; break; - case ARoundMode.TowardsMinusInfinity: + case RoundMode.TowardsMinusInfinity: roundUp = (error != 0d && sign); overflowToInf = sign; break; - case ARoundMode.TowardsZero: + case RoundMode.TowardsZero: roundUp = false; overflowToInf = false; break; @@ -409,7 +409,7 @@ namespace ChocolArm64.Instruction { result = overflowToInf ? FPInfinity(sign) : FPMaxNormal(sign); - FPProcessException(AFpExc.Overflow, state); + FPProcessException(FpExc.Overflow, state); error = 1d; } @@ -421,7 +421,7 @@ namespace ChocolArm64.Instruction if (error != 0d) { - FPProcessException(AFpExc.Inexact, state); + FPProcessException(FpExc.Inexact, state); } return result; @@ -433,7 +433,7 @@ namespace ChocolArm64.Instruction (int)(((uint)valueBits & 0x8000u) << 16 | 0x7FC00000u | ((uint)valueBits & 0x01FFu) << 13)); } - private static void FPProcessException(AFpExc exc, AThreadState state) + private static void FPProcessException(FpExc exc, AThreadState state) { int enable = (int)exc + 8; @@ -454,19 +454,19 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat32_16.FPConvert: State.Fpcr = 0x{state.Fpcr:X8}"); - double real = value.FPUnpackCv(out FPType type, out bool sign, state, out uint valueBits); + double real = value.FPUnpackCv(out FpType type, out bool sign, state, out uint valueBits); - bool altHp = state.GetFpcrFlag(AFpcr.Ahp); + bool altHp = state.GetFpcrFlag(Fpcr.Ahp); ushort resultBits; - if (type == FPType.SNaN || type == FPType.QNaN) + if (type == FpType.SNaN || type == FpType.QNaN) { if (altHp) { resultBits = FPZero(sign); } - else if (state.GetFpcrFlag(AFpcr.Dn)) + else if (state.GetFpcrFlag(Fpcr.Dn)) { resultBits = FPDefaultNaN(); } @@ -475,25 +475,25 @@ namespace ChocolArm64.Instruction resultBits = FPConvertNaN(valueBits); } - if (type == FPType.SNaN || altHp) + if (type == FpType.SNaN || altHp) { - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } } - else if (type == FPType.Infinity) + else if (type == FpType.Infinity) { if (altHp) { resultBits = (ushort)((sign ? 1u : 0u) << 15 | 0x7FFFu); - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } else { resultBits = FPInfinity(sign); } } - else if (type == FPType.Zero) + else if (type == FpType.Zero) { resultBits = FPZero(sign); } @@ -525,7 +525,7 @@ namespace ChocolArm64.Instruction return sign ? (ushort)0xFBFFu : (ushort)0x7BFFu; } - private static double FPUnpackCv(this float value, out FPType type, out bool sign, AThreadState state, out uint valueBits) + private static double FPUnpackCv(this float value, out FpType type, out bool sign, AThreadState state, out uint valueBits) { valueBits = (uint)BitConverter.SingleToInt32Bits(value); @@ -538,16 +538,16 @@ namespace ChocolArm64.Instruction if (exp32 == 0u) { - if (frac32 == 0u || state.GetFpcrFlag(AFpcr.Fz)) + if (frac32 == 0u || state.GetFpcrFlag(Fpcr.Fz)) { - type = FPType.Zero; + type = FpType.Zero; real = 0d; - if (frac32 != 0u) FPProcessException(AFpExc.InputDenorm, state); + if (frac32 != 0u) FPProcessException(FpExc.InputDenorm, state); } else { - type = FPType.Nonzero; // Subnormal. + type = FpType.Nonzero; // Subnormal. real = Math.Pow(2d, -126) * ((double)frac32 * Math.Pow(2d, -23)); } } @@ -555,18 +555,18 @@ namespace ChocolArm64.Instruction { if (frac32 == 0u) { - type = FPType.Infinity; + type = FpType.Infinity; real = Math.Pow(2d, 1000); } else { - type = (~frac32 & 0x00400000u) == 0u ? FPType.QNaN : FPType.SNaN; + type = (~frac32 & 0x00400000u) == 0u ? FpType.QNaN : FpType.SNaN; real = 0d; } } else { - type = FPType.Nonzero; // Normal. + type = FpType.Nonzero; // Normal. real = Math.Pow(2d, (int)exp32 - 127) * (1d + (double)frac32 * Math.Pow(2d, -23)); } @@ -618,9 +618,9 @@ namespace ChocolArm64.Instruction uint intMant = (uint)Math.Floor(mantissa * Math.Pow(2d, f)); double error = mantissa * Math.Pow(2d, f) - (double)intMant; - if (biasedExp == 0u && (error != 0d || state.GetFpcrFlag(AFpcr.Ufe))) + if (biasedExp == 0u && (error != 0d || state.GetFpcrFlag(Fpcr.Ufe))) { - FPProcessException(AFpExc.Underflow, state); + FPProcessException(FpExc.Underflow, state); } bool overflowToInf; @@ -629,22 +629,22 @@ namespace ChocolArm64.Instruction switch (state.FPRoundingMode()) { default: - case ARoundMode.ToNearest: + case RoundMode.ToNearest: roundUp = (error > 0.5d || (error == 0.5d && (intMant & 1u) == 1u)); overflowToInf = true; break; - case ARoundMode.TowardsPlusInfinity: + case RoundMode.TowardsPlusInfinity: roundUp = (error != 0d && !sign); overflowToInf = !sign; break; - case ARoundMode.TowardsMinusInfinity: + case RoundMode.TowardsMinusInfinity: roundUp = (error != 0d && sign); overflowToInf = sign; break; - case ARoundMode.TowardsZero: + case RoundMode.TowardsZero: roundUp = false; overflowToInf = false; break; @@ -668,13 +668,13 @@ namespace ChocolArm64.Instruction ushort resultBits; - if (!state.GetFpcrFlag(AFpcr.Ahp)) + if (!state.GetFpcrFlag(Fpcr.Ahp)) { if (biasedExp >= (uint)Math.Pow(2d, e) - 1u) { resultBits = overflowToInf ? FPInfinity(sign) : FPMaxNormal(sign); - FPProcessException(AFpExc.Overflow, state); + FPProcessException(FpExc.Overflow, state); error = 1d; } @@ -689,7 +689,7 @@ namespace ChocolArm64.Instruction { resultBits = (ushort)((sign ? 1u : 0u) << 15 | 0x7FFFu); - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); error = 0d; } @@ -701,7 +701,7 @@ namespace ChocolArm64.Instruction if (error != 0d) { - FPProcessException(AFpExc.Inexact, state); + FPProcessException(FpExc.Inexact, state); } return resultBits; @@ -712,7 +712,7 @@ namespace ChocolArm64.Instruction return (ushort)((valueBits & 0x80000000u) >> 16 | 0x7E00u | (valueBits & 0x003FE000u) >> 13); } - private static void FPProcessException(AFpExc exc, AThreadState state) + private static void FPProcessException(FpExc exc, AThreadState state) { int enable = (int)exc + 8; @@ -733,21 +733,21 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_32.FPAdd: State.Fpcr = 0x{state.Fpcr:X8}"); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2); float result = FPProcessNaNs(type1, type2, op1, op2, state, out bool done); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FpType.Infinity; bool zero1 = type1 == FpType.Zero; + bool inf2 = type2 == FpType.Infinity; bool zero2 = type2 == FpType.Zero; if (inf1 && inf2 && sign1 == !sign2) { result = FPDefaultNaN(); - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } else if ((inf1 && !sign1) || (inf2 && !sign2)) { @@ -774,27 +774,27 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_32.FPDiv: State.Fpcr = 0x{state.Fpcr:X8}"); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2); float result = FPProcessNaNs(type1, type2, op1, op2, state, out bool done); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FpType.Infinity; bool zero1 = type1 == FpType.Zero; + bool inf2 = type2 == FpType.Infinity; bool zero2 = type2 == FpType.Zero; if ((inf1 && inf2) || (zero1 && zero2)) { result = FPDefaultNaN(); - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } else if (inf1 || zero2) { result = FPInfinity(sign1 ^ sign2); - if (!inf1) FPProcessException(AFpExc.DivideByZero, state); + if (!inf1) FPProcessException(FpExc.DivideByZero, state); } else if (zero1 || inf2) { @@ -813,8 +813,8 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_32.FPMax: State.Fpcr = 0x{state.Fpcr:X8}"); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2); float result = FPProcessNaNs(type1, type2, op1, op2, state, out bool done); @@ -822,11 +822,11 @@ namespace ChocolArm64.Instruction { if (value1 > value2) { - if (type1 == FPType.Infinity) + if (type1 == FpType.Infinity) { result = FPInfinity(sign1); } - else if (type1 == FPType.Zero) + else if (type1 == FpType.Zero) { result = FPZero(sign1 && sign2); } @@ -837,11 +837,11 @@ namespace ChocolArm64.Instruction } else { - if (type2 == FPType.Infinity) + if (type2 == FpType.Infinity) { result = FPInfinity(sign2); } - else if (type2 == FPType.Zero) + else if (type2 == FpType.Zero) { result = FPZero(sign1 && sign2); } @@ -859,14 +859,14 @@ namespace ChocolArm64.Instruction { Debug.WriteIf(state.Fpcr != 0, "ASoftFloat_32.FPMaxNum: "); - value1.FPUnpack(out FPType type1, out _, out _); - value2.FPUnpack(out FPType type2, out _, out _); + value1.FPUnpack(out FpType type1, out _, out _); + value2.FPUnpack(out FpType type2, out _, out _); - if (type1 == FPType.QNaN && type2 != FPType.QNaN) + if (type1 == FpType.QNaN && type2 != FpType.QNaN) { value1 = FPInfinity(true); } - else if (type1 != FPType.QNaN && type2 == FPType.QNaN) + else if (type1 != FpType.QNaN && type2 == FpType.QNaN) { value2 = FPInfinity(true); } @@ -878,8 +878,8 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_32.FPMin: State.Fpcr = 0x{state.Fpcr:X8}"); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2); float result = FPProcessNaNs(type1, type2, op1, op2, state, out bool done); @@ -887,11 +887,11 @@ namespace ChocolArm64.Instruction { if (value1 < value2) { - if (type1 == FPType.Infinity) + if (type1 == FpType.Infinity) { result = FPInfinity(sign1); } - else if (type1 == FPType.Zero) + else if (type1 == FpType.Zero) { result = FPZero(sign1 || sign2); } @@ -902,11 +902,11 @@ namespace ChocolArm64.Instruction } else { - if (type2 == FPType.Infinity) + if (type2 == FpType.Infinity) { result = FPInfinity(sign2); } - else if (type2 == FPType.Zero) + else if (type2 == FpType.Zero) { result = FPZero(sign1 || sign2); } @@ -924,14 +924,14 @@ namespace ChocolArm64.Instruction { Debug.WriteIf(state.Fpcr != 0, "ASoftFloat_32.FPMinNum: "); - value1.FPUnpack(out FPType type1, out _, out _); - value2.FPUnpack(out FPType type2, out _, out _); + value1.FPUnpack(out FpType type1, out _, out _); + value2.FPUnpack(out FpType type2, out _, out _); - if (type1 == FPType.QNaN && type2 != FPType.QNaN) + if (type1 == FpType.QNaN && type2 != FpType.QNaN) { value1 = FPInfinity(false); } - else if (type1 != FPType.QNaN && type2 == FPType.QNaN) + else if (type1 != FpType.QNaN && type2 == FpType.QNaN) { value2 = FPInfinity(false); } @@ -943,21 +943,21 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_32.FPMul: State.Fpcr = 0x{state.Fpcr:X8}"); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2); float result = FPProcessNaNs(type1, type2, op1, op2, state, out bool done); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FpType.Infinity; bool zero1 = type1 == FpType.Zero; + bool inf2 = type2 == FpType.Infinity; bool zero2 = type2 == FpType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { result = FPDefaultNaN(); - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } else if (inf1 || inf2) { @@ -980,25 +980,25 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_32.FPMulAdd: State.Fpcr = 0x{state.Fpcr:X8}"); - valueA = valueA.FPUnpack(out FPType typeA, out bool signA, out uint addend); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2); + valueA = valueA.FPUnpack(out FpType typeA, out bool signA, out uint addend); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2); - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FpType.Infinity; bool zero1 = type1 == FpType.Zero; + bool inf2 = type2 == FpType.Infinity; bool zero2 = type2 == FpType.Zero; float result = FPProcessNaNs3(typeA, type1, type2, addend, op1, op2, state, out bool done); - if (typeA == FPType.QNaN && ((inf1 && zero2) || (zero1 && inf2))) + if (typeA == FpType.QNaN && ((inf1 && zero2) || (zero1 && inf2))) { result = FPDefaultNaN(); - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } if (!done) { - bool infA = typeA == FPType.Infinity; bool zeroA = typeA == FPType.Zero; + bool infA = typeA == FpType.Infinity; bool zeroA = typeA == FpType.Zero; bool signP = sign1 ^ sign2; bool infP = inf1 || inf2; @@ -1008,7 +1008,7 @@ namespace ChocolArm64.Instruction { result = FPDefaultNaN(); - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } else if ((infA && !signA) || (infP && !signP)) { @@ -1048,15 +1048,15 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_32.FPMulX: State.Fpcr = 0x{state.Fpcr:X8}"); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2); float result = FPProcessNaNs(type1, type2, op1, op2, state, out bool done); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FpType.Infinity; bool zero1 = type1 == FpType.Zero; + bool inf2 = type2 == FpType.Infinity; bool zero2 = type2 == FpType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -1085,15 +1085,15 @@ namespace ChocolArm64.Instruction value1 = value1.FPNeg(); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2); float result = FPProcessNaNs(type1, type2, op1, op2, state, out bool done); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FpType.Infinity; bool zero1 = type1 == FpType.Zero; + bool inf2 = type2 == FpType.Infinity; bool zero2 = type2 == FpType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -1119,11 +1119,11 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_32.FPRecpX: State.Fpcr = 0x{state.Fpcr:X8}"); - value.FPUnpack(out FPType type, out bool sign, out uint op); + value.FPUnpack(out FpType type, out bool sign, out uint op); float result; - if (type == FPType.SNaN || type == FPType.QNaN) + if (type == FpType.SNaN || type == FpType.QNaN) { result = FPProcessNaN(type, op, state); } @@ -1145,15 +1145,15 @@ namespace ChocolArm64.Instruction value1 = value1.FPNeg(); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2); float result = FPProcessNaNs(type1, type2, op1, op2, state, out bool done); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FpType.Infinity; bool zero1 = type1 == FpType.Zero; + bool inf2 = type2 == FpType.Infinity; bool zero2 = type2 == FpType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -1179,19 +1179,19 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_32.FPSqrt: State.Fpcr = 0x{state.Fpcr:X8}"); - value = value.FPUnpack(out FPType type, out bool sign, out uint op); + value = value.FPUnpack(out FpType type, out bool sign, out uint op); float result; - if (type == FPType.SNaN || type == FPType.QNaN) + if (type == FpType.SNaN || type == FpType.QNaN) { result = FPProcessNaN(type, op, state); } - else if (type == FPType.Zero) + else if (type == FpType.Zero) { result = FPZero(sign); } - else if (type == FPType.Infinity && !sign) + else if (type == FpType.Infinity && !sign) { result = FPInfinity(sign); } @@ -1199,7 +1199,7 @@ namespace ChocolArm64.Instruction { result = FPDefaultNaN(); - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } else { @@ -1213,21 +1213,21 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_32.FPSub: State.Fpcr = 0x{state.Fpcr:X8}"); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out uint op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out uint op2); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out uint op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out uint op2); float result = FPProcessNaNs(type1, type2, op1, op2, state, out bool done); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FpType.Infinity; bool zero1 = type1 == FpType.Zero; + bool inf2 = type2 == FpType.Infinity; bool zero2 = type2 == FpType.Zero; if (inf1 && inf2 && sign1 == sign2) { result = FPDefaultNaN(); - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } else if ((inf1 && !sign1) || (inf2 && sign2)) { @@ -1280,7 +1280,7 @@ namespace ChocolArm64.Instruction return -value; } - private static float FPUnpack(this float value, out FPType type, out bool sign, out uint valueBits) + private static float FPUnpack(this float value, out FpType type, out bool sign, out uint valueBits) { valueBits = (uint)BitConverter.SingleToInt32Bits(value); @@ -1290,39 +1290,39 @@ namespace ChocolArm64.Instruction { if ((valueBits & 0x007FFFFFu) == 0u) { - type = FPType.Zero; + type = FpType.Zero; } else { - type = FPType.Nonzero; + type = FpType.Nonzero; } } else if ((~valueBits & 0x7F800000u) == 0u) { if ((valueBits & 0x007FFFFFu) == 0u) { - type = FPType.Infinity; + type = FpType.Infinity; } else { type = (~valueBits & 0x00400000u) == 0u - ? FPType.QNaN - : FPType.SNaN; + ? FpType.QNaN + : FpType.SNaN; return FPZero(sign); } } else { - type = FPType.Nonzero; + type = FpType.Nonzero; } return value; } private static float FPProcessNaNs( - FPType type1, - FPType type2, + FpType type1, + FpType type2, uint op1, uint op2, AThreadState state, @@ -1330,19 +1330,19 @@ namespace ChocolArm64.Instruction { done = true; - if (type1 == FPType.SNaN) + if (type1 == FpType.SNaN) { return FPProcessNaN(type1, op1, state); } - else if (type2 == FPType.SNaN) + else if (type2 == FpType.SNaN) { return FPProcessNaN(type2, op2, state); } - else if (type1 == FPType.QNaN) + else if (type1 == FpType.QNaN) { return FPProcessNaN(type1, op1, state); } - else if (type2 == FPType.QNaN) + else if (type2 == FpType.QNaN) { return FPProcessNaN(type2, op2, state); } @@ -1353,9 +1353,9 @@ namespace ChocolArm64.Instruction } private static float FPProcessNaNs3( - FPType type1, - FPType type2, - FPType type3, + FpType type1, + FpType type2, + FpType type3, uint op1, uint op2, uint op3, @@ -1364,27 +1364,27 @@ namespace ChocolArm64.Instruction { done = true; - if (type1 == FPType.SNaN) + if (type1 == FpType.SNaN) { return FPProcessNaN(type1, op1, state); } - else if (type2 == FPType.SNaN) + else if (type2 == FpType.SNaN) { return FPProcessNaN(type2, op2, state); } - else if (type3 == FPType.SNaN) + else if (type3 == FpType.SNaN) { return FPProcessNaN(type3, op3, state); } - else if (type1 == FPType.QNaN) + else if (type1 == FpType.QNaN) { return FPProcessNaN(type1, op1, state); } - else if (type2 == FPType.QNaN) + else if (type2 == FpType.QNaN) { return FPProcessNaN(type2, op2, state); } - else if (type3 == FPType.QNaN) + else if (type3 == FpType.QNaN) { return FPProcessNaN(type3, op3, state); } @@ -1394,16 +1394,16 @@ namespace ChocolArm64.Instruction return FPZero(false); } - private static float FPProcessNaN(FPType type, uint op, AThreadState state) + private static float FPProcessNaN(FpType type, uint op, AThreadState state) { - if (type == FPType.SNaN) + if (type == FpType.SNaN) { op |= 1u << 22; - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } - if (state.GetFpcrFlag(AFpcr.Dn)) + if (state.GetFpcrFlag(Fpcr.Dn)) { return FPDefaultNaN(); } @@ -1411,7 +1411,7 @@ namespace ChocolArm64.Instruction return BitConverter.Int32BitsToSingle((int)op); } - private static void FPProcessException(AFpExc exc, AThreadState state) + private static void FPProcessException(FpExc exc, AThreadState state) { int enable = (int)exc + 8; @@ -1432,21 +1432,21 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_64.FPAdd: State.Fpcr = 0x{state.Fpcr:X8}"); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2); double result = FPProcessNaNs(type1, type2, op1, op2, state, out bool done); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FpType.Infinity; bool zero1 = type1 == FpType.Zero; + bool inf2 = type2 == FpType.Infinity; bool zero2 = type2 == FpType.Zero; if (inf1 && inf2 && sign1 == !sign2) { result = FPDefaultNaN(); - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } else if ((inf1 && !sign1) || (inf2 && !sign2)) { @@ -1473,27 +1473,27 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_64.FPDiv: State.Fpcr = 0x{state.Fpcr:X8}"); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2); double result = FPProcessNaNs(type1, type2, op1, op2, state, out bool done); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FpType.Infinity; bool zero1 = type1 == FpType.Zero; + bool inf2 = type2 == FpType.Infinity; bool zero2 = type2 == FpType.Zero; if ((inf1 && inf2) || (zero1 && zero2)) { result = FPDefaultNaN(); - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } else if (inf1 || zero2) { result = FPInfinity(sign1 ^ sign2); - if (!inf1) FPProcessException(AFpExc.DivideByZero, state); + if (!inf1) FPProcessException(FpExc.DivideByZero, state); } else if (zero1 || inf2) { @@ -1512,8 +1512,8 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_64.FPMax: State.Fpcr = 0x{state.Fpcr:X8}"); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2); double result = FPProcessNaNs(type1, type2, op1, op2, state, out bool done); @@ -1521,11 +1521,11 @@ namespace ChocolArm64.Instruction { if (value1 > value2) { - if (type1 == FPType.Infinity) + if (type1 == FpType.Infinity) { result = FPInfinity(sign1); } - else if (type1 == FPType.Zero) + else if (type1 == FpType.Zero) { result = FPZero(sign1 && sign2); } @@ -1536,11 +1536,11 @@ namespace ChocolArm64.Instruction } else { - if (type2 == FPType.Infinity) + if (type2 == FpType.Infinity) { result = FPInfinity(sign2); } - else if (type2 == FPType.Zero) + else if (type2 == FpType.Zero) { result = FPZero(sign1 && sign2); } @@ -1558,14 +1558,14 @@ namespace ChocolArm64.Instruction { Debug.WriteIf(state.Fpcr != 0, "ASoftFloat_64.FPMaxNum: "); - value1.FPUnpack(out FPType type1, out _, out _); - value2.FPUnpack(out FPType type2, out _, out _); + value1.FPUnpack(out FpType type1, out _, out _); + value2.FPUnpack(out FpType type2, out _, out _); - if (type1 == FPType.QNaN && type2 != FPType.QNaN) + if (type1 == FpType.QNaN && type2 != FpType.QNaN) { value1 = FPInfinity(true); } - else if (type1 != FPType.QNaN && type2 == FPType.QNaN) + else if (type1 != FpType.QNaN && type2 == FpType.QNaN) { value2 = FPInfinity(true); } @@ -1577,8 +1577,8 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_64.FPMin: State.Fpcr = 0x{state.Fpcr:X8}"); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2); double result = FPProcessNaNs(type1, type2, op1, op2, state, out bool done); @@ -1586,11 +1586,11 @@ namespace ChocolArm64.Instruction { if (value1 < value2) { - if (type1 == FPType.Infinity) + if (type1 == FpType.Infinity) { result = FPInfinity(sign1); } - else if (type1 == FPType.Zero) + else if (type1 == FpType.Zero) { result = FPZero(sign1 || sign2); } @@ -1601,11 +1601,11 @@ namespace ChocolArm64.Instruction } else { - if (type2 == FPType.Infinity) + if (type2 == FpType.Infinity) { result = FPInfinity(sign2); } - else if (type2 == FPType.Zero) + else if (type2 == FpType.Zero) { result = FPZero(sign1 || sign2); } @@ -1623,14 +1623,14 @@ namespace ChocolArm64.Instruction { Debug.WriteIf(state.Fpcr != 0, "ASoftFloat_64.FPMinNum: "); - value1.FPUnpack(out FPType type1, out _, out _); - value2.FPUnpack(out FPType type2, out _, out _); + value1.FPUnpack(out FpType type1, out _, out _); + value2.FPUnpack(out FpType type2, out _, out _); - if (type1 == FPType.QNaN && type2 != FPType.QNaN) + if (type1 == FpType.QNaN && type2 != FpType.QNaN) { value1 = FPInfinity(false); } - else if (type1 != FPType.QNaN && type2 == FPType.QNaN) + else if (type1 != FpType.QNaN && type2 == FpType.QNaN) { value2 = FPInfinity(false); } @@ -1642,21 +1642,21 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_64.FPMul: State.Fpcr = 0x{state.Fpcr:X8}"); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2); double result = FPProcessNaNs(type1, type2, op1, op2, state, out bool done); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FpType.Infinity; bool zero1 = type1 == FpType.Zero; + bool inf2 = type2 == FpType.Infinity; bool zero2 = type2 == FpType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { result = FPDefaultNaN(); - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } else if (inf1 || inf2) { @@ -1679,25 +1679,25 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_64.FPMulAdd: State.Fpcr = 0x{state.Fpcr:X8}"); - valueA = valueA.FPUnpack(out FPType typeA, out bool signA, out ulong addend); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2); + valueA = valueA.FPUnpack(out FpType typeA, out bool signA, out ulong addend); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2); - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FpType.Infinity; bool zero1 = type1 == FpType.Zero; + bool inf2 = type2 == FpType.Infinity; bool zero2 = type2 == FpType.Zero; double result = FPProcessNaNs3(typeA, type1, type2, addend, op1, op2, state, out bool done); - if (typeA == FPType.QNaN && ((inf1 && zero2) || (zero1 && inf2))) + if (typeA == FpType.QNaN && ((inf1 && zero2) || (zero1 && inf2))) { result = FPDefaultNaN(); - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } if (!done) { - bool infA = typeA == FPType.Infinity; bool zeroA = typeA == FPType.Zero; + bool infA = typeA == FpType.Infinity; bool zeroA = typeA == FpType.Zero; bool signP = sign1 ^ sign2; bool infP = inf1 || inf2; @@ -1707,7 +1707,7 @@ namespace ChocolArm64.Instruction { result = FPDefaultNaN(); - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } else if ((infA && !signA) || (infP && !signP)) { @@ -1747,15 +1747,15 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_64.FPMulX: State.Fpcr = 0x{state.Fpcr:X8}"); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2); double result = FPProcessNaNs(type1, type2, op1, op2, state, out bool done); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FpType.Infinity; bool zero1 = type1 == FpType.Zero; + bool inf2 = type2 == FpType.Infinity; bool zero2 = type2 == FpType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -1784,15 +1784,15 @@ namespace ChocolArm64.Instruction value1 = value1.FPNeg(); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2); double result = FPProcessNaNs(type1, type2, op1, op2, state, out bool done); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FpType.Infinity; bool zero1 = type1 == FpType.Zero; + bool inf2 = type2 == FpType.Infinity; bool zero2 = type2 == FpType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -1818,11 +1818,11 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_64.FPRecpX: State.Fpcr = 0x{state.Fpcr:X8}"); - value.FPUnpack(out FPType type, out bool sign, out ulong op); + value.FPUnpack(out FpType type, out bool sign, out ulong op); double result; - if (type == FPType.SNaN || type == FPType.QNaN) + if (type == FpType.SNaN || type == FpType.QNaN) { result = FPProcessNaN(type, op, state); } @@ -1844,15 +1844,15 @@ namespace ChocolArm64.Instruction value1 = value1.FPNeg(); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2); double result = FPProcessNaNs(type1, type2, op1, op2, state, out bool done); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FpType.Infinity; bool zero1 = type1 == FpType.Zero; + bool inf2 = type2 == FpType.Infinity; bool zero2 = type2 == FpType.Zero; if ((inf1 && zero2) || (zero1 && inf2)) { @@ -1878,19 +1878,19 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_64.FPSqrt: State.Fpcr = 0x{state.Fpcr:X8}"); - value = value.FPUnpack(out FPType type, out bool sign, out ulong op); + value = value.FPUnpack(out FpType type, out bool sign, out ulong op); double result; - if (type == FPType.SNaN || type == FPType.QNaN) + if (type == FpType.SNaN || type == FpType.QNaN) { result = FPProcessNaN(type, op, state); } - else if (type == FPType.Zero) + else if (type == FpType.Zero) { result = FPZero(sign); } - else if (type == FPType.Infinity && !sign) + else if (type == FpType.Infinity && !sign) { result = FPInfinity(sign); } @@ -1898,7 +1898,7 @@ namespace ChocolArm64.Instruction { result = FPDefaultNaN(); - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } else { @@ -1912,21 +1912,21 @@ namespace ChocolArm64.Instruction { Debug.WriteLineIf(state.Fpcr != 0, $"ASoftFloat_64.FPSub: State.Fpcr = 0x{state.Fpcr:X8}"); - value1 = value1.FPUnpack(out FPType type1, out bool sign1, out ulong op1); - value2 = value2.FPUnpack(out FPType type2, out bool sign2, out ulong op2); + value1 = value1.FPUnpack(out FpType type1, out bool sign1, out ulong op1); + value2 = value2.FPUnpack(out FpType type2, out bool sign2, out ulong op2); double result = FPProcessNaNs(type1, type2, op1, op2, state, out bool done); if (!done) { - bool inf1 = type1 == FPType.Infinity; bool zero1 = type1 == FPType.Zero; - bool inf2 = type2 == FPType.Infinity; bool zero2 = type2 == FPType.Zero; + bool inf1 = type1 == FpType.Infinity; bool zero1 = type1 == FpType.Zero; + bool inf2 = type2 == FpType.Infinity; bool zero2 = type2 == FpType.Zero; if (inf1 && inf2 && sign1 == sign2) { result = FPDefaultNaN(); - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } else if ((inf1 && !sign1) || (inf2 && sign2)) { @@ -1979,7 +1979,7 @@ namespace ChocolArm64.Instruction return -value; } - private static double FPUnpack(this double value, out FPType type, out bool sign, out ulong valueBits) + private static double FPUnpack(this double value, out FpType type, out bool sign, out ulong valueBits) { valueBits = (ulong)BitConverter.DoubleToInt64Bits(value); @@ -1989,39 +1989,39 @@ namespace ChocolArm64.Instruction { if ((valueBits & 0x000FFFFFFFFFFFFFul) == 0ul) { - type = FPType.Zero; + type = FpType.Zero; } else { - type = FPType.Nonzero; + type = FpType.Nonzero; } } else if ((~valueBits & 0x7FF0000000000000ul) == 0ul) { if ((valueBits & 0x000FFFFFFFFFFFFFul) == 0ul) { - type = FPType.Infinity; + type = FpType.Infinity; } else { type = (~valueBits & 0x0008000000000000ul) == 0ul - ? FPType.QNaN - : FPType.SNaN; + ? FpType.QNaN + : FpType.SNaN; return FPZero(sign); } } else { - type = FPType.Nonzero; + type = FpType.Nonzero; } return value; } private static double FPProcessNaNs( - FPType type1, - FPType type2, + FpType type1, + FpType type2, ulong op1, ulong op2, AThreadState state, @@ -2029,19 +2029,19 @@ namespace ChocolArm64.Instruction { done = true; - if (type1 == FPType.SNaN) + if (type1 == FpType.SNaN) { return FPProcessNaN(type1, op1, state); } - else if (type2 == FPType.SNaN) + else if (type2 == FpType.SNaN) { return FPProcessNaN(type2, op2, state); } - else if (type1 == FPType.QNaN) + else if (type1 == FpType.QNaN) { return FPProcessNaN(type1, op1, state); } - else if (type2 == FPType.QNaN) + else if (type2 == FpType.QNaN) { return FPProcessNaN(type2, op2, state); } @@ -2052,9 +2052,9 @@ namespace ChocolArm64.Instruction } private static double FPProcessNaNs3( - FPType type1, - FPType type2, - FPType type3, + FpType type1, + FpType type2, + FpType type3, ulong op1, ulong op2, ulong op3, @@ -2063,27 +2063,27 @@ namespace ChocolArm64.Instruction { done = true; - if (type1 == FPType.SNaN) + if (type1 == FpType.SNaN) { return FPProcessNaN(type1, op1, state); } - else if (type2 == FPType.SNaN) + else if (type2 == FpType.SNaN) { return FPProcessNaN(type2, op2, state); } - else if (type3 == FPType.SNaN) + else if (type3 == FpType.SNaN) { return FPProcessNaN(type3, op3, state); } - else if (type1 == FPType.QNaN) + else if (type1 == FpType.QNaN) { return FPProcessNaN(type1, op1, state); } - else if (type2 == FPType.QNaN) + else if (type2 == FpType.QNaN) { return FPProcessNaN(type2, op2, state); } - else if (type3 == FPType.QNaN) + else if (type3 == FpType.QNaN) { return FPProcessNaN(type3, op3, state); } @@ -2093,16 +2093,16 @@ namespace ChocolArm64.Instruction return FPZero(false); } - private static double FPProcessNaN(FPType type, ulong op, AThreadState state) + private static double FPProcessNaN(FpType type, ulong op, AThreadState state) { - if (type == FPType.SNaN) + if (type == FpType.SNaN) { op |= 1ul << 51; - FPProcessException(AFpExc.InvalidOp, state); + FPProcessException(FpExc.InvalidOp, state); } - if (state.GetFpcrFlag(AFpcr.Dn)) + if (state.GetFpcrFlag(Fpcr.Dn)) { return FPDefaultNaN(); } @@ -2110,7 +2110,7 @@ namespace ChocolArm64.Instruction return BitConverter.Int64BitsToDouble((long)op); } - private static void FPProcessException(AFpExc exc, AThreadState state) + private static void FPProcessException(FpExc exc, AThreadState state) { int enable = (int)exc + 8; diff --git a/ChocolArm64/Instruction/AVectorHelper.cs b/ChocolArm64/Instruction/VectorHelper.cs similarity index 95% rename from ChocolArm64/Instruction/AVectorHelper.cs rename to ChocolArm64/Instruction/VectorHelper.cs index c1bb47c130..6f6fdee389 100644 --- a/ChocolArm64/Instruction/AVectorHelper.cs +++ b/ChocolArm64/Instruction/VectorHelper.cs @@ -7,11 +7,11 @@ using System.Runtime.Intrinsics.X86; namespace ChocolArm64.Instruction { - static class AVectorHelper + static class VectorHelper { private static readonly Vector128 Zero32128Mask; - static AVectorHelper() + static VectorHelper() { if (!Sse2.IsSupported) { @@ -21,16 +21,16 @@ namespace ChocolArm64.Instruction Zero32128Mask = Sse.StaticCast(Sse2.SetVector128(0, 0, 0, 0xffffffff)); } - public static void EmitCall(AilEmitterCtx context, string name64, string name128) + public static void EmitCall(ILEmitterCtx context, string name64, string name128) { - bool isSimd64 = context.CurrOp.RegisterSize == ARegisterSize.Simd64; + bool isSimd64 = context.CurrOp.RegisterSize == RegisterSize.Simd64; - context.EmitCall(typeof(AVectorHelper), isSimd64 ? name64 : name128); + context.EmitCall(typeof(VectorHelper), isSimd64 ? name64 : name128); } - public static void EmitCall(AilEmitterCtx context, string mthdName) + public static void EmitCall(ILEmitterCtx context, string mthdName) { - context.EmitCall(typeof(AVectorHelper), mthdName); + context.EmitCall(typeof(VectorHelper), mthdName); } [MethodImpl(MethodImplOptions.AggressiveInlining)] @@ -109,10 +109,10 @@ namespace ChocolArm64.Instruction { switch (state.FPRoundingMode()) { - case ARoundMode.ToNearest: return Math.Round (value); - case ARoundMode.TowardsPlusInfinity: return Math.Ceiling (value); - case ARoundMode.TowardsMinusInfinity: return Math.Floor (value); - case ARoundMode.TowardsZero: return Math.Truncate(value); + case RoundMode.ToNearest: return Math.Round (value); + case RoundMode.TowardsPlusInfinity: return Math.Ceiling (value); + case RoundMode.TowardsMinusInfinity: return Math.Floor (value); + case RoundMode.TowardsZero: return Math.Truncate(value); } throw new InvalidOperationException(); @@ -122,10 +122,10 @@ namespace ChocolArm64.Instruction { switch (state.FPRoundingMode()) { - case ARoundMode.ToNearest: return MathF.Round (value); - case ARoundMode.TowardsPlusInfinity: return MathF.Ceiling (value); - case ARoundMode.TowardsMinusInfinity: return MathF.Floor (value); - case ARoundMode.TowardsZero: return MathF.Truncate(value); + case RoundMode.ToNearest: return MathF.Round (value); + case RoundMode.TowardsPlusInfinity: return MathF.Ceiling (value); + case RoundMode.TowardsMinusInfinity: return MathF.Floor (value); + case RoundMode.TowardsZero: return MathF.Truncate(value); } throw new InvalidOperationException(); diff --git a/ChocolArm64/Instruction32/A32InstInterpretHelper.cs b/ChocolArm64/Instruction32/A32InstInterpretHelper.cs index b08be34b03..5d750d3f3f 100644 --- a/ChocolArm64/Instruction32/A32InstInterpretHelper.cs +++ b/ChocolArm64/Instruction32/A32InstInterpretHelper.cs @@ -6,24 +6,24 @@ namespace ChocolArm64.Instruction32 { static class A32InstInterpretHelper { - public static bool IsConditionTrue(AThreadState state, ACond cond) + public static bool IsConditionTrue(AThreadState state, Cond cond) { switch (cond) { - case ACond.Eq: return state.Zero; - case ACond.Ne: return !state.Zero; - case ACond.GeUn: return state.Carry; - case ACond.LtUn: return !state.Carry; - case ACond.Mi: return state.Negative; - case ACond.Pl: return !state.Negative; - case ACond.Vs: return state.Overflow; - case ACond.Vc: return !state.Overflow; - case ACond.GtUn: return state.Carry && !state.Zero; - case ACond.LeUn: return !state.Carry && state.Zero; - case ACond.Ge: return state.Negative == state.Overflow; - case ACond.Lt: return state.Negative != state.Overflow; - case ACond.Gt: return state.Negative == state.Overflow && !state.Zero; - case ACond.Le: return state.Negative != state.Overflow && state.Zero; + case Cond.Eq: return state.Zero; + case Cond.Ne: return !state.Zero; + case Cond.GeUn: return state.Carry; + case Cond.LtUn: return !state.Carry; + case Cond.Mi: return state.Negative; + case Cond.Pl: return !state.Negative; + case Cond.Vs: return state.Overflow; + case Cond.Vc: return !state.Overflow; + case Cond.GtUn: return state.Carry && !state.Zero; + case Cond.LeUn: return !state.Carry && state.Zero; + case Cond.Ge: return state.Negative == state.Overflow; + case Cond.Lt: return state.Negative != state.Overflow; + case Cond.Gt: return state.Negative == state.Overflow && !state.Zero; + case Cond.Le: return state.Negative != state.Overflow && state.Zero; } return true; diff --git a/ChocolArm64/Memory/AMemory.cs b/ChocolArm64/Memory/AMemory.cs index 3df94ab453..ea9b5a667a 100644 --- a/ChocolArm64/Memory/AMemory.cs +++ b/ChocolArm64/Memory/AMemory.cs @@ -12,7 +12,7 @@ using System.Threading; namespace ChocolArm64.Memory { - public unsafe class AMemory : IaMemory, IDisposable + public unsafe class AMemory : IAMemory, IDisposable { private const int PtLvl0Bits = 13; private const int PtLvl1Bits = 14; @@ -52,7 +52,7 @@ namespace ChocolArm64.Memory private byte*** _pageTable; - public event EventHandler InvalidAccess; + public event EventHandler InvalidAccess; public AMemory(IntPtr ram) { @@ -515,7 +515,7 @@ Unmapped: return (byte*)ptr + (position & PageMask); } - InvalidAccess?.Invoke(this, new AInvalidAccessEventArgs(position)); + InvalidAccess?.Invoke(this, new InvalidAccessEventArgs(position)); throw new VmmPageFaultException(position); } @@ -565,7 +565,7 @@ Unmapped: return (byte*)ptr + (position & PageMask); } - InvalidAccess?.Invoke(this, new AInvalidAccessEventArgs(position)); + InvalidAccess?.Invoke(this, new InvalidAccessEventArgs(position)); throw new VmmPageFaultException(position); } diff --git a/ChocolArm64/Memory/IAMemory.cs b/ChocolArm64/Memory/IAMemory.cs index 79fc893618..6eebe45691 100644 --- a/ChocolArm64/Memory/IAMemory.cs +++ b/ChocolArm64/Memory/IAMemory.cs @@ -1,6 +1,6 @@ namespace ChocolArm64.Memory { - public interface IaMemory + public interface IAMemory { sbyte ReadSByte(long position); diff --git a/ChocolArm64/OpCodeTable.cs b/ChocolArm64/OpCodeTable.cs new file mode 100644 index 0000000000..724a3891e7 --- /dev/null +++ b/ChocolArm64/OpCodeTable.cs @@ -0,0 +1,713 @@ +using ChocolArm64.Decoder; +using ChocolArm64.Decoder32; +using ChocolArm64.Instruction; +using ChocolArm64.Instruction32; +using ChocolArm64.State; +using System; +using System.Collections.Generic; + +namespace ChocolArm64 +{ + static class OpCodeTable + { + static OpCodeTable() + { +#region "OpCode Table (AArch32)" + //Integer + SetA32("<<<<1010xxxxxxxxxxxxxxxxxxxxxxxx", A32InstInterpret.B, typeof(A32OpCodeBImmAl)); + SetA32("<<<<1011xxxxxxxxxxxxxxxxxxxxxxxx", A32InstInterpret.Bl, typeof(A32OpCodeBImmAl)); + SetA32("1111101xxxxxxxxxxxxxxxxxxxxxxxxx", A32InstInterpret.Blx, typeof(A32OpCodeBImmAl)); +#endregion + +#region "OpCode Table (AArch64)" + //Integer + SetA64("x0011010000xxxxx000000xxxxxxxxxx", InstEmit.Adc, typeof(OpCodeAluRs)); + SetA64("x0111010000xxxxx000000xxxxxxxxxx", InstEmit.Adcs, typeof(OpCodeAluRs)); + SetA64("x00100010xxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Add, typeof(OpCodeAluImm)); + SetA64("00001011<<0xxxxx0xxxxxxxxxxxxxxx", InstEmit.Add, typeof(OpCodeAluRs)); + SetA64("10001011<<0xxxxxxxxxxxxxxxxxxxxx", InstEmit.Add, typeof(OpCodeAluRs)); + SetA64("x0001011001xxxxxxxx0xxxxxxxxxxxx", InstEmit.Add, typeof(OpCodeAluRx)); + SetA64("x0001011001xxxxxxxx100xxxxxxxxxx", InstEmit.Add, typeof(OpCodeAluRx)); + SetA64("x01100010xxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Adds, typeof(OpCodeAluImm)); + SetA64("00101011<<0xxxxx0xxxxxxxxxxxxxxx", InstEmit.Adds, typeof(OpCodeAluRs)); + SetA64("10101011<<0xxxxxxxxxxxxxxxxxxxxx", InstEmit.Adds, typeof(OpCodeAluRs)); + SetA64("x0101011001xxxxxxxx0xxxxxxxxxxxx", InstEmit.Adds, typeof(OpCodeAluRx)); + SetA64("x0101011001xxxxxxxx100xxxxxxxxxx", InstEmit.Adds, typeof(OpCodeAluRx)); + SetA64("0xx10000xxxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Adr, typeof(OpCodeAdr)); + SetA64("1xx10000xxxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Adrp, typeof(OpCodeAdr)); + SetA64("0001001000xxxxxxxxxxxxxxxxxxxxxx", InstEmit.And, typeof(OpCodeAluImm)); + SetA64("100100100xxxxxxxxxxxxxxxxxxxxxxx", InstEmit.And, typeof(OpCodeAluImm)); + SetA64("00001010xx0xxxxx0xxxxxxxxxxxxxxx", InstEmit.And, typeof(OpCodeAluRs)); + SetA64("10001010xx0xxxxxxxxxxxxxxxxxxxxx", InstEmit.And, typeof(OpCodeAluRs)); + SetA64("0111001000xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Ands, typeof(OpCodeAluImm)); + SetA64("111100100xxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Ands, typeof(OpCodeAluImm)); + SetA64("01101010xx0xxxxx0xxxxxxxxxxxxxxx", InstEmit.Ands, typeof(OpCodeAluRs)); + SetA64("11101010xx0xxxxxxxxxxxxxxxxxxxxx", InstEmit.Ands, typeof(OpCodeAluRs)); + SetA64("x0011010110xxxxx001010xxxxxxxxxx", InstEmit.Asrv, typeof(OpCodeAluRs)); + SetA64("000101xxxxxxxxxxxxxxxxxxxxxxxxxx", InstEmit.B, typeof(OpCodeBImmAl)); + SetA64("01010100xxxxxxxxxxxxxxxxxxx0xxxx", InstEmit.B_Cond, typeof(OpCodeBImmCond)); + SetA64("00110011000xxxxx0xxxxxxxxxxxxxxx", InstEmit.Bfm, typeof(OpCodeBfm)); + SetA64("1011001101xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Bfm, typeof(OpCodeBfm)); + SetA64("00001010xx1xxxxx0xxxxxxxxxxxxxxx", InstEmit.Bic, typeof(OpCodeAluRs)); + SetA64("10001010xx1xxxxxxxxxxxxxxxxxxxxx", InstEmit.Bic, typeof(OpCodeAluRs)); + SetA64("01101010xx1xxxxx0xxxxxxxxxxxxxxx", InstEmit.Bics, typeof(OpCodeAluRs)); + SetA64("11101010xx1xxxxxxxxxxxxxxxxxxxxx", InstEmit.Bics, typeof(OpCodeAluRs)); + SetA64("100101xxxxxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Bl, typeof(OpCodeBImmAl)); + SetA64("1101011000111111000000xxxxx00000", InstEmit.Blr, typeof(OpCodeBReg)); + SetA64("1101011000011111000000xxxxx00000", InstEmit.Br, typeof(OpCodeBReg)); + SetA64("11010100001xxxxxxxxxxxxxxxx00000", InstEmit.Brk, typeof(OpCodeException)); + SetA64("x0110101xxxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Cbnz, typeof(OpCodeBImmCmp)); + SetA64("x0110100xxxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Cbz, typeof(OpCodeBImmCmp)); + SetA64("x0111010010xxxxxxxxx10xxxxx0xxxx", InstEmit.Ccmn, typeof(OpCodeCcmpImm)); + SetA64("x0111010010xxxxxxxxx00xxxxx0xxxx", InstEmit.Ccmn, typeof(OpCodeCcmpReg)); + SetA64("x1111010010xxxxxxxxx10xxxxx0xxxx", InstEmit.Ccmp, typeof(OpCodeCcmpImm)); + SetA64("x1111010010xxxxxxxxx00xxxxx0xxxx", InstEmit.Ccmp, typeof(OpCodeCcmpReg)); + SetA64("11010101000000110011xxxx01011111", InstEmit.Clrex, typeof(OpCodeSystem)); + SetA64("x101101011000000000101xxxxxxxxxx", InstEmit.Cls, typeof(OpCodeAlu)); + SetA64("x101101011000000000100xxxxxxxxxx", InstEmit.Clz, typeof(OpCodeAlu)); + SetA64("00011010110xxxxx010000xxxxxxxxxx", InstEmit.Crc32b, typeof(OpCodeAluRs)); + SetA64("00011010110xxxxx010001xxxxxxxxxx", InstEmit.Crc32h, typeof(OpCodeAluRs)); + SetA64("00011010110xxxxx010010xxxxxxxxxx", InstEmit.Crc32w, typeof(OpCodeAluRs)); + SetA64("10011010110xxxxx010011xxxxxxxxxx", InstEmit.Crc32x, typeof(OpCodeAluRs)); + SetA64("00011010110xxxxx010100xxxxxxxxxx", InstEmit.Crc32cb, typeof(OpCodeAluRs)); + SetA64("00011010110xxxxx010101xxxxxxxxxx", InstEmit.Crc32ch, typeof(OpCodeAluRs)); + SetA64("00011010110xxxxx010110xxxxxxxxxx", InstEmit.Crc32cw, typeof(OpCodeAluRs)); + SetA64("10011010110xxxxx010111xxxxxxxxxx", InstEmit.Crc32cx, typeof(OpCodeAluRs)); + SetA64("x0011010100xxxxxxxxx00xxxxxxxxxx", InstEmit.Csel, typeof(OpCodeCsel)); + SetA64("x0011010100xxxxxxxxx01xxxxxxxxxx", InstEmit.Csinc, typeof(OpCodeCsel)); + SetA64("x1011010100xxxxxxxxx00xxxxxxxxxx", InstEmit.Csinv, typeof(OpCodeCsel)); + SetA64("x1011010100xxxxxxxxx01xxxxxxxxxx", InstEmit.Csneg, typeof(OpCodeCsel)); + SetA64("11010101000000110011xxxx10111111", InstEmit.Dmb, typeof(OpCodeSystem)); + SetA64("11010101000000110011xxxx10011111", InstEmit.Dsb, typeof(OpCodeSystem)); + SetA64("01001010xx1xxxxx0xxxxxxxxxxxxxxx", InstEmit.Eon, typeof(OpCodeAluRs)); + SetA64("11001010xx1xxxxxxxxxxxxxxxxxxxxx", InstEmit.Eon, typeof(OpCodeAluRs)); + SetA64("0101001000xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Eor, typeof(OpCodeAluImm)); + SetA64("110100100xxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Eor, typeof(OpCodeAluImm)); + SetA64("01001010xx0xxxxx0xxxxxxxxxxxxxxx", InstEmit.Eor, typeof(OpCodeAluRs)); + SetA64("11001010xx0xxxxxxxxxxxxxxxxxxxxx", InstEmit.Eor, typeof(OpCodeAluRs)); + SetA64("00010011100xxxxx0xxxxxxxxxxxxxxx", InstEmit.Extr, typeof(OpCodeAluRs)); + SetA64("10010011110xxxxxxxxxxxxxxxxxxxxx", InstEmit.Extr, typeof(OpCodeAluRs)); + SetA64("11010101000000110010xxxxxxx11111", InstEmit.Hint, typeof(OpCodeSystem)); + SetA64("11010101000000110011xxxx11011111", InstEmit.Isb, typeof(OpCodeSystem)); + SetA64("xx001000110xxxxx1xxxxxxxxxxxxxxx", InstEmit.Ldar, typeof(OpCodeMemEx)); + SetA64("1x001000011xxxxx1xxxxxxxxxxxxxxx", InstEmit.Ldaxp, typeof(OpCodeMemEx)); + SetA64("xx001000010xxxxx1xxxxxxxxxxxxxxx", InstEmit.Ldaxr, typeof(OpCodeMemEx)); + SetA64("<<10100xx1xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Ldp, typeof(OpCodeMemPair)); + SetA64("xx111000010xxxxxxxxxxxxxxxxxxxxx", InstEmit.Ldr, typeof(OpCodeMemImm)); + SetA64("xx11100101xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Ldr, typeof(OpCodeMemImm)); + SetA64("xx111000011xxxxxxxxx10xxxxxxxxxx", InstEmit.Ldr, typeof(OpCodeMemReg)); + SetA64("xx011000xxxxxxxxxxxxxxxxxxxxxxxx", InstEmit.LdrLit, typeof(OpCodeMemLit)); + SetA64("0x1110001x0xxxxxxxxxxxxxxxxxxxxx", InstEmit.Ldrs, typeof(OpCodeMemImm)); + SetA64("0x1110011xxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Ldrs, typeof(OpCodeMemImm)); + SetA64("10111000100xxxxxxxxxxxxxxxxxxxxx", InstEmit.Ldrs, typeof(OpCodeMemImm)); + SetA64("1011100110xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Ldrs, typeof(OpCodeMemImm)); + SetA64("0x1110001x1xxxxxxxxx10xxxxxxxxxx", InstEmit.Ldrs, typeof(OpCodeMemReg)); + SetA64("10111000101xxxxxxxxx10xxxxxxxxxx", InstEmit.Ldrs, typeof(OpCodeMemReg)); + SetA64("xx001000010xxxxx0xxxxxxxxxxxxxxx", InstEmit.Ldxr, typeof(OpCodeMemEx)); + SetA64("1x001000011xxxxx0xxxxxxxxxxxxxxx", InstEmit.Ldxp, typeof(OpCodeMemEx)); + SetA64("x0011010110xxxxx001000xxxxxxxxxx", InstEmit.Lslv, typeof(OpCodeAluRs)); + SetA64("x0011010110xxxxx001001xxxxxxxxxx", InstEmit.Lsrv, typeof(OpCodeAluRs)); + SetA64("x0011011000xxxxx0xxxxxxxxxxxxxxx", InstEmit.Madd, typeof(OpCodeMul)); + SetA64("0111001010xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Movk, typeof(OpCodeMov)); + SetA64("111100101xxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Movk, typeof(OpCodeMov)); + SetA64("0001001010xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Movn, typeof(OpCodeMov)); + SetA64("100100101xxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Movn, typeof(OpCodeMov)); + SetA64("0101001010xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Movz, typeof(OpCodeMov)); + SetA64("110100101xxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Movz, typeof(OpCodeMov)); + SetA64("110101010011xxxxxxxxxxxxxxxxxxxx", InstEmit.Mrs, typeof(OpCodeSystem)); + SetA64("110101010001xxxxxxxxxxxxxxxxxxxx", InstEmit.Msr, typeof(OpCodeSystem)); + SetA64("x0011011000xxxxx1xxxxxxxxxxxxxxx", InstEmit.Msub, typeof(OpCodeMul)); + SetA64("11010101000000110010000000011111", InstEmit.Nop, typeof(OpCodeSystem)); + SetA64("00101010xx1xxxxx0xxxxxxxxxxxxxxx", InstEmit.Orn, typeof(OpCodeAluRs)); + SetA64("10101010xx1xxxxxxxxxxxxxxxxxxxxx", InstEmit.Orn, typeof(OpCodeAluRs)); + SetA64("0011001000xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Orr, typeof(OpCodeAluImm)); + SetA64("101100100xxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Orr, typeof(OpCodeAluImm)); + SetA64("00101010xx0xxxxx0xxxxxxxxxxxxxxx", InstEmit.Orr, typeof(OpCodeAluRs)); + SetA64("10101010xx0xxxxxxxxxxxxxxxxxxxxx", InstEmit.Orr, typeof(OpCodeAluRs)); + SetA64("1111100110xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Pfrm, typeof(OpCodeMemImm)); + SetA64("11111000100xxxxxxxxx00xxxxxxxxxx", InstEmit.Pfrm, typeof(OpCodeMemImm)); + SetA64("11011000xxxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Pfrm, typeof(OpCodeMemLit)); + SetA64("x101101011000000000000xxxxxxxxxx", InstEmit.Rbit, typeof(OpCodeAlu)); + SetA64("1101011001011111000000xxxxx00000", InstEmit.Ret, typeof(OpCodeBReg)); + SetA64("x101101011000000000001xxxxxxxxxx", InstEmit.Rev16, typeof(OpCodeAlu)); + SetA64("x101101011000000000010xxxxxxxxxx", InstEmit.Rev32, typeof(OpCodeAlu)); + SetA64("1101101011000000000011xxxxxxxxxx", InstEmit.Rev64, typeof(OpCodeAlu)); + SetA64("x0011010110xxxxx001011xxxxxxxxxx", InstEmit.Rorv, typeof(OpCodeAluRs)); + SetA64("x1011010000xxxxx000000xxxxxxxxxx", InstEmit.Sbc, typeof(OpCodeAluRs)); + SetA64("x1111010000xxxxx000000xxxxxxxxxx", InstEmit.Sbcs, typeof(OpCodeAluRs)); + SetA64("00010011000xxxxx0xxxxxxxxxxxxxxx", InstEmit.Sbfm, typeof(OpCodeBfm)); + SetA64("1001001101xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Sbfm, typeof(OpCodeBfm)); + SetA64("x0011010110xxxxx000011xxxxxxxxxx", InstEmit.Sdiv, typeof(OpCodeAluRs)); + SetA64("10011011001xxxxx0xxxxxxxxxxxxxxx", InstEmit.Smaddl, typeof(OpCodeMul)); + SetA64("10011011001xxxxx1xxxxxxxxxxxxxxx", InstEmit.Smsubl, typeof(OpCodeMul)); + SetA64("10011011010xxxxx0xxxxxxxxxxxxxxx", InstEmit.Smulh, typeof(OpCodeMul)); + SetA64("xx001000100xxxxx1xxxxxxxxxxxxxxx", InstEmit.Stlr, typeof(OpCodeMemEx)); + SetA64("1x001000001xxxxx1xxxxxxxxxxxxxxx", InstEmit.Stlxp, typeof(OpCodeMemEx)); + SetA64("xx001000000xxxxx1xxxxxxxxxxxxxxx", InstEmit.Stlxr, typeof(OpCodeMemEx)); + SetA64("x010100xx0xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Stp, typeof(OpCodeMemPair)); + SetA64("xx111000000xxxxxxxxxxxxxxxxxxxxx", InstEmit.Str, typeof(OpCodeMemImm)); + SetA64("xx11100100xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Str, typeof(OpCodeMemImm)); + SetA64("xx111000001xxxxxxxxx10xxxxxxxxxx", InstEmit.Str, typeof(OpCodeMemReg)); + SetA64("1x001000001xxxxx0xxxxxxxxxxxxxxx", InstEmit.Stxp, typeof(OpCodeMemEx)); + SetA64("xx001000000xxxxx0xxxxxxxxxxxxxxx", InstEmit.Stxr, typeof(OpCodeMemEx)); + SetA64("x10100010xxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Sub, typeof(OpCodeAluImm)); + SetA64("01001011<<0xxxxx0xxxxxxxxxxxxxxx", InstEmit.Sub, typeof(OpCodeAluRs)); + SetA64("11001011<<0xxxxxxxxxxxxxxxxxxxxx", InstEmit.Sub, typeof(OpCodeAluRs)); + SetA64("x1001011001xxxxxxxx0xxxxxxxxxxxx", InstEmit.Sub, typeof(OpCodeAluRx)); + SetA64("x1001011001xxxxxxxx100xxxxxxxxxx", InstEmit.Sub, typeof(OpCodeAluRx)); + SetA64("x11100010xxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Subs, typeof(OpCodeAluImm)); + SetA64("01101011<<0xxxxx0xxxxxxxxxxxxxxx", InstEmit.Subs, typeof(OpCodeAluRs)); + SetA64("11101011<<0xxxxxxxxxxxxxxxxxxxxx", InstEmit.Subs, typeof(OpCodeAluRs)); + SetA64("x1101011001xxxxxxxx0xxxxxxxxxxxx", InstEmit.Subs, typeof(OpCodeAluRx)); + SetA64("x1101011001xxxxxxxx100xxxxxxxxxx", InstEmit.Subs, typeof(OpCodeAluRx)); + SetA64("11010100000xxxxxxxxxxxxxxxx00001", InstEmit.Svc, typeof(OpCodeException)); + SetA64("1101010100001xxxxxxxxxxxxxxxxxxx", InstEmit.Sys, typeof(OpCodeSystem)); + SetA64("x0110111xxxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Tbnz, typeof(OpCodeBImmTest)); + SetA64("x0110110xxxxxxxxxxxxxxxxxxxxxxxx", InstEmit.Tbz, typeof(OpCodeBImmTest)); + SetA64("01010011000xxxxx0xxxxxxxxxxxxxxx", InstEmit.Ubfm, typeof(OpCodeBfm)); + SetA64("1101001101xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Ubfm, typeof(OpCodeBfm)); + SetA64("x0011010110xxxxx000010xxxxxxxxxx", InstEmit.Udiv, typeof(OpCodeAluRs)); + SetA64("10011011101xxxxx0xxxxxxxxxxxxxxx", InstEmit.Umaddl, typeof(OpCodeMul)); + SetA64("10011011101xxxxx1xxxxxxxxxxxxxxx", InstEmit.Umsubl, typeof(OpCodeMul)); + SetA64("10011011110xxxxx0xxxxxxxxxxxxxxx", InstEmit.Umulh, typeof(OpCodeMul)); + + //Vector + SetA64("0101111011100000101110xxxxxxxxxx", InstEmit.Abs_S, typeof(OpCodeSimd)); + SetA64("0>001110<<100000101110xxxxxxxxxx", InstEmit.Abs_V, typeof(OpCodeSimd)); + SetA64("01011110111xxxxx100001xxxxxxxxxx", InstEmit.Add_S, typeof(OpCodeSimdReg)); + SetA64("0>001110<<1xxxxx100001xxxxxxxxxx", InstEmit.Add_V, typeof(OpCodeSimdReg)); + SetA64("0x001110<<1xxxxx010000xxxxxxxxxx", InstEmit.Addhn_V, typeof(OpCodeSimdReg)); + SetA64("0101111011110001101110xxxxxxxxxx", InstEmit.Addp_S, typeof(OpCodeSimd)); + SetA64("0>001110<<1xxxxx101111xxxxxxxxxx", InstEmit.Addp_V, typeof(OpCodeSimdReg)); + SetA64("000011100x110001101110xxxxxxxxxx", InstEmit.Addv_V, typeof(OpCodeSimd)); + SetA64("01001110<<110001101110xxxxxxxxxx", InstEmit.Addv_V, typeof(OpCodeSimd)); + SetA64("0100111000101000010110xxxxxxxxxx", InstEmit.Aesd_V, typeof(OpCodeSimd)); + SetA64("0100111000101000010010xxxxxxxxxx", InstEmit.Aese_V, typeof(OpCodeSimd)); + SetA64("0100111000101000011110xxxxxxxxxx", InstEmit.Aesimc_V, typeof(OpCodeSimd)); + SetA64("0100111000101000011010xxxxxxxxxx", InstEmit.Aesmc_V, typeof(OpCodeSimd)); + SetA64("0x001110001xxxxx000111xxxxxxxxxx", InstEmit.And_V, typeof(OpCodeSimdReg)); + SetA64("0x001110011xxxxx000111xxxxxxxxxx", InstEmit.Bic_V, typeof(OpCodeSimdReg)); + SetA64("0x10111100000xxx<101110<<1xxxxx100011xxxxxxxxxx", InstEmit.Cmeq_V, typeof(OpCodeSimdReg)); + SetA64("0>001110<<100000100110xxxxxxxxxx", InstEmit.Cmeq_V, typeof(OpCodeSimd)); + SetA64("01011110111xxxxx001111xxxxxxxxxx", InstEmit.Cmge_S, typeof(OpCodeSimdReg)); + SetA64("0111111011100000100010xxxxxxxxxx", InstEmit.Cmge_S, typeof(OpCodeSimd)); + SetA64("0>001110<<1xxxxx001111xxxxxxxxxx", InstEmit.Cmge_V, typeof(OpCodeSimdReg)); + SetA64("0>101110<<100000100010xxxxxxxxxx", InstEmit.Cmge_V, typeof(OpCodeSimd)); + SetA64("01011110111xxxxx001101xxxxxxxxxx", InstEmit.Cmgt_S, typeof(OpCodeSimdReg)); + SetA64("0101111011100000100010xxxxxxxxxx", InstEmit.Cmgt_S, typeof(OpCodeSimd)); + SetA64("0>001110<<1xxxxx001101xxxxxxxxxx", InstEmit.Cmgt_V, typeof(OpCodeSimdReg)); + SetA64("0>001110<<100000100010xxxxxxxxxx", InstEmit.Cmgt_V, typeof(OpCodeSimd)); + SetA64("01111110111xxxxx001101xxxxxxxxxx", InstEmit.Cmhi_S, typeof(OpCodeSimdReg)); + SetA64("0>101110<<1xxxxx001101xxxxxxxxxx", InstEmit.Cmhi_V, typeof(OpCodeSimdReg)); + SetA64("01111110111xxxxx001111xxxxxxxxxx", InstEmit.Cmhs_S, typeof(OpCodeSimdReg)); + SetA64("0>101110<<1xxxxx001111xxxxxxxxxx", InstEmit.Cmhs_V, typeof(OpCodeSimdReg)); + SetA64("0111111011100000100110xxxxxxxxxx", InstEmit.Cmle_S, typeof(OpCodeSimd)); + SetA64("0>101110<<100000100110xxxxxxxxxx", InstEmit.Cmle_V, typeof(OpCodeSimd)); + SetA64("0101111011100000101010xxxxxxxxxx", InstEmit.Cmlt_S, typeof(OpCodeSimd)); + SetA64("0>001110<<100000101010xxxxxxxxxx", InstEmit.Cmlt_V, typeof(OpCodeSimd)); + SetA64("01011110111xxxxx100011xxxxxxxxxx", InstEmit.Cmtst_S, typeof(OpCodeSimdReg)); + SetA64("0>001110<<1xxxxx100011xxxxxxxxxx", InstEmit.Cmtst_V, typeof(OpCodeSimdReg)); + SetA64("0x00111000100000010110xxxxxxxxxx", InstEmit.Cnt_V, typeof(OpCodeSimd)); + SetA64("0x001110000xxxxx000011xxxxxxxxxx", InstEmit.Dup_Gp, typeof(OpCodeSimdIns)); + SetA64("01011110000xxxxx000001xxxxxxxxxx", InstEmit.Dup_S, typeof(OpCodeSimdIns)); + SetA64("0x001110000xxxxx000001xxxxxxxxxx", InstEmit.Dup_V, typeof(OpCodeSimdIns)); + SetA64("0x101110001xxxxx000111xxxxxxxxxx", InstEmit.Eor_V, typeof(OpCodeSimdReg)); + SetA64("0>101110000xxxxx00011101<100000111110xxxxxxxxxx", InstEmit.Fabs_V, typeof(OpCodeSimd)); + SetA64("000111100x1xxxxx001010xxxxxxxxxx", InstEmit.Fadd_S, typeof(OpCodeSimdReg)); + SetA64("0>0011100<1xxxxx110101xxxxxxxxxx", InstEmit.Fadd_V, typeof(OpCodeSimdReg)); + SetA64("011111100x110000110110xxxxxxxxxx", InstEmit.Faddp_S, typeof(OpCodeSimd)); + SetA64("0>1011100<1xxxxx110101xxxxxxxxxx", InstEmit.Faddp_V, typeof(OpCodeSimdReg)); + SetA64("000111100x1xxxxxxxxx01xxxxx0xxxx", InstEmit.Fccmp_S, typeof(OpCodeSimdFcond)); + SetA64("000111100x1xxxxxxxxx01xxxxx1xxxx", InstEmit.Fccmpe_S, typeof(OpCodeSimdFcond)); + SetA64("010111100x1xxxxx111001xxxxxxxxxx", InstEmit.Fcmeq_S, typeof(OpCodeSimdReg)); + SetA64("010111101x100000110110xxxxxxxxxx", InstEmit.Fcmeq_S, typeof(OpCodeSimd)); + SetA64("0>0011100<1xxxxx111001xxxxxxxxxx", InstEmit.Fcmeq_V, typeof(OpCodeSimdReg)); + SetA64("0>0011101<100000110110xxxxxxxxxx", InstEmit.Fcmeq_V, typeof(OpCodeSimd)); + SetA64("011111100x1xxxxx111001xxxxxxxxxx", InstEmit.Fcmge_S, typeof(OpCodeSimdReg)); + SetA64("011111101x100000110010xxxxxxxxxx", InstEmit.Fcmge_S, typeof(OpCodeSimd)); + SetA64("0>1011100<1xxxxx111001xxxxxxxxxx", InstEmit.Fcmge_V, typeof(OpCodeSimdReg)); + SetA64("0>1011101<100000110010xxxxxxxxxx", InstEmit.Fcmge_V, typeof(OpCodeSimd)); + SetA64("011111101x1xxxxx111001xxxxxxxxxx", InstEmit.Fcmgt_S, typeof(OpCodeSimdReg)); + SetA64("010111101x100000110010xxxxxxxxxx", InstEmit.Fcmgt_S, typeof(OpCodeSimd)); + SetA64("0>1011101<1xxxxx111001xxxxxxxxxx", InstEmit.Fcmgt_V, typeof(OpCodeSimdReg)); + SetA64("0>0011101<100000110010xxxxxxxxxx", InstEmit.Fcmgt_V, typeof(OpCodeSimd)); + SetA64("011111101x100000110110xxxxxxxxxx", InstEmit.Fcmle_S, typeof(OpCodeSimd)); + SetA64("0>1011101<100000110110xxxxxxxxxx", InstEmit.Fcmle_V, typeof(OpCodeSimd)); + SetA64("010111101x100000111010xxxxxxxxxx", InstEmit.Fcmlt_S, typeof(OpCodeSimd)); + SetA64("0>0011101<100000111010xxxxxxxxxx", InstEmit.Fcmlt_V, typeof(OpCodeSimd)); + SetA64("000111100x1xxxxx001000xxxxx0x000", InstEmit.Fcmp_S, typeof(OpCodeSimdReg)); + SetA64("000111100x1xxxxx001000xxxxx1x000", InstEmit.Fcmpe_S, typeof(OpCodeSimdReg)); + SetA64("000111100x1xxxxxxxxx11xxxxxxxxxx", InstEmit.Fcsel_S, typeof(OpCodeSimdFcond)); + SetA64("000111100x10001xx10000xxxxxxxxxx", InstEmit.Fcvt_S, typeof(OpCodeSimd)); + SetA64("x00111100x100100000000xxxxxxxxxx", InstEmit.Fcvtas_Gp, typeof(OpCodeSimdCvt)); + SetA64("x00111100x100101000000xxxxxxxxxx", InstEmit.Fcvtau_Gp, typeof(OpCodeSimdCvt)); + SetA64("0x0011100x100001011110xxxxxxxxxx", InstEmit.Fcvtl_V, typeof(OpCodeSimd)); + SetA64("x00111100x110000000000xxxxxxxxxx", InstEmit.Fcvtms_Gp, typeof(OpCodeSimdCvt)); + SetA64("x00111100x110001000000xxxxxxxxxx", InstEmit.Fcvtmu_Gp, typeof(OpCodeSimdCvt)); + SetA64("0x0011100x100001011010xxxxxxxxxx", InstEmit.Fcvtn_V, typeof(OpCodeSimd)); + SetA64("010111100x100001101010xxxxxxxxxx", InstEmit.Fcvtns_S, typeof(OpCodeSimd)); + SetA64("0>0011100<100001101010xxxxxxxxxx", InstEmit.Fcvtns_V, typeof(OpCodeSimd)); + SetA64("011111100x100001101010xxxxxxxxxx", InstEmit.Fcvtnu_S, typeof(OpCodeSimd)); + SetA64("0>1011100<100001101010xxxxxxxxxx", InstEmit.Fcvtnu_V, typeof(OpCodeSimd)); + SetA64("x00111100x101000000000xxxxxxxxxx", InstEmit.Fcvtps_Gp, typeof(OpCodeSimdCvt)); + SetA64("x00111100x101001000000xxxxxxxxxx", InstEmit.Fcvtpu_Gp, typeof(OpCodeSimdCvt)); + SetA64("x00111100x111000000000xxxxxxxxxx", InstEmit.Fcvtzs_Gp, typeof(OpCodeSimdCvt)); + SetA64("x00111100x011000xxxxxxxxxxxxxxxx", InstEmit.Fcvtzs_Gp_Fix, typeof(OpCodeSimdCvt)); + SetA64("010111101x100001101110xxxxxxxxxx", InstEmit.Fcvtzs_S, typeof(OpCodeSimd)); + SetA64("0>0011101<100001101110xxxxxxxxxx", InstEmit.Fcvtzs_V, typeof(OpCodeSimd)); + SetA64("0x0011110>>xxxxx111111xxxxxxxxxx", InstEmit.Fcvtzs_V, typeof(OpCodeSimdShImm)); + SetA64("x00111100x111001000000xxxxxxxxxx", InstEmit.Fcvtzu_Gp, typeof(OpCodeSimdCvt)); + SetA64("x00111100x011001xxxxxxxxxxxxxxxx", InstEmit.Fcvtzu_Gp_Fix, typeof(OpCodeSimdCvt)); + SetA64("011111101x100001101110xxxxxxxxxx", InstEmit.Fcvtzu_S, typeof(OpCodeSimd)); + SetA64("0>1011101<100001101110xxxxxxxxxx", InstEmit.Fcvtzu_V, typeof(OpCodeSimd)); + SetA64("0x1011110>>xxxxx111111xxxxxxxxxx", InstEmit.Fcvtzu_V, typeof(OpCodeSimdShImm)); + SetA64("000111100x1xxxxx000110xxxxxxxxxx", InstEmit.Fdiv_S, typeof(OpCodeSimdReg)); + SetA64("0>1011100<1xxxxx111111xxxxxxxxxx", InstEmit.Fdiv_V, typeof(OpCodeSimdReg)); + SetA64("000111110x0xxxxx0xxxxxxxxxxxxxxx", InstEmit.Fmadd_S, typeof(OpCodeSimdReg)); + SetA64("000111100x1xxxxx010010xxxxxxxxxx", InstEmit.Fmax_S, typeof(OpCodeSimdReg)); + SetA64("0>0011100<1xxxxx111101xxxxxxxxxx", InstEmit.Fmax_V, typeof(OpCodeSimdReg)); + SetA64("000111100x1xxxxx011010xxxxxxxxxx", InstEmit.Fmaxnm_S, typeof(OpCodeSimdReg)); + SetA64("0>0011100<1xxxxx110001xxxxxxxxxx", InstEmit.Fmaxnm_V, typeof(OpCodeSimdReg)); + SetA64("0>1011100<1xxxxx111101xxxxxxxxxx", InstEmit.Fmaxp_V, typeof(OpCodeSimdReg)); + SetA64("000111100x1xxxxx010110xxxxxxxxxx", InstEmit.Fmin_S, typeof(OpCodeSimdReg)); + SetA64("0>0011101<1xxxxx111101xxxxxxxxxx", InstEmit.Fmin_V, typeof(OpCodeSimdReg)); + SetA64("000111100x1xxxxx011110xxxxxxxxxx", InstEmit.Fminnm_S, typeof(OpCodeSimdReg)); + SetA64("0>0011101<1xxxxx110001xxxxxxxxxx", InstEmit.Fminnm_V, typeof(OpCodeSimdReg)); + SetA64("0>1011101<1xxxxx111101xxxxxxxxxx", InstEmit.Fminp_V, typeof(OpCodeSimdReg)); + SetA64("010111111xxxxxxx0001x0xxxxxxxxxx", InstEmit.Fmla_Se, typeof(OpCodeSimdRegElemF)); + SetA64("0>0011100<1xxxxx110011xxxxxxxxxx", InstEmit.Fmla_V, typeof(OpCodeSimdReg)); + SetA64("0>00111110011101<1xxxxx110011xxxxxxxxxx", InstEmit.Fmls_V, typeof(OpCodeSimdReg)); + SetA64("0>00111111011100<1xxxxx110111xxxxxxxxxx", InstEmit.Fmul_V, typeof(OpCodeSimdReg)); + SetA64("0>00111110011100<1xxxxx110111xxxxxxxxxx", InstEmit.Fmulx_V, typeof(OpCodeSimdReg)); + SetA64("0>10111111011101<100000111110xxxxxxxxxx", InstEmit.Fneg_V, typeof(OpCodeSimd)); + SetA64("000111110x1xxxxx0xxxxxxxxxxxxxxx", InstEmit.Fnmadd_S, typeof(OpCodeSimdReg)); + SetA64("000111110x1xxxxx1xxxxxxxxxxxxxxx", InstEmit.Fnmsub_S, typeof(OpCodeSimdReg)); + SetA64("000111100x1xxxxx100010xxxxxxxxxx", InstEmit.Fnmul_S, typeof(OpCodeSimdReg)); + SetA64("010111101x100001110110xxxxxxxxxx", InstEmit.Frecpe_S, typeof(OpCodeSimd)); + SetA64("0>0011101<100001110110xxxxxxxxxx", InstEmit.Frecpe_V, typeof(OpCodeSimd)); + SetA64("010111100x1xxxxx111111xxxxxxxxxx", InstEmit.Frecps_S, typeof(OpCodeSimdReg)); + SetA64("0>0011100<1xxxxx111111xxxxxxxxxx", InstEmit.Frecps_V, typeof(OpCodeSimdReg)); + SetA64("010111101x100001111110xxxxxxxxxx", InstEmit.Frecpx_S, typeof(OpCodeSimd)); + SetA64("000111100x100110010000xxxxxxxxxx", InstEmit.Frinta_S, typeof(OpCodeSimd)); + SetA64("0>1011100<100001100010xxxxxxxxxx", InstEmit.Frinta_V, typeof(OpCodeSimd)); + SetA64("000111100x100111110000xxxxxxxxxx", InstEmit.Frinti_S, typeof(OpCodeSimd)); + SetA64("0>1011101<100001100110xxxxxxxxxx", InstEmit.Frinti_V, typeof(OpCodeSimd)); + SetA64("000111100x100101010000xxxxxxxxxx", InstEmit.Frintm_S, typeof(OpCodeSimd)); + SetA64("0>0011100<100001100110xxxxxxxxxx", InstEmit.Frintm_V, typeof(OpCodeSimd)); + SetA64("000111100x100100010000xxxxxxxxxx", InstEmit.Frintn_S, typeof(OpCodeSimd)); + SetA64("0>0011100<100001100010xxxxxxxxxx", InstEmit.Frintn_V, typeof(OpCodeSimd)); + SetA64("000111100x100100110000xxxxxxxxxx", InstEmit.Frintp_S, typeof(OpCodeSimd)); + SetA64("0>0011101<100001100010xxxxxxxxxx", InstEmit.Frintp_V, typeof(OpCodeSimd)); + SetA64("000111100x100111010000xxxxxxxxxx", InstEmit.Frintx_S, typeof(OpCodeSimd)); + SetA64("0>1011100<100001100110xxxxxxxxxx", InstEmit.Frintx_V, typeof(OpCodeSimd)); + SetA64("011111101x100001110110xxxxxxxxxx", InstEmit.Frsqrte_S, typeof(OpCodeSimd)); + SetA64("0>1011101<100001110110xxxxxxxxxx", InstEmit.Frsqrte_V, typeof(OpCodeSimd)); + SetA64("010111101x1xxxxx111111xxxxxxxxxx", InstEmit.Frsqrts_S, typeof(OpCodeSimdReg)); + SetA64("0>0011101<1xxxxx111111xxxxxxxxxx", InstEmit.Frsqrts_V, typeof(OpCodeSimdReg)); + SetA64("000111100x100001110000xxxxxxxxxx", InstEmit.Fsqrt_S, typeof(OpCodeSimd)); + SetA64("0>1011101<100001111110xxxxxxxxxx", InstEmit.Fsqrt_V, typeof(OpCodeSimd)); + SetA64("000111100x1xxxxx001110xxxxxxxxxx", InstEmit.Fsub_S, typeof(OpCodeSimdReg)); + SetA64("0>0011101<1xxxxx110101xxxxxxxxxx", InstEmit.Fsub_V, typeof(OpCodeSimdReg)); + SetA64("01001110000xxxxx000111xxxxxxxxxx", InstEmit.Ins_Gp, typeof(OpCodeSimdIns)); + SetA64("01101110000xxxxx0xxxx1xxxxxxxxxx", InstEmit.Ins_V, typeof(OpCodeSimdIns)); + SetA64("0x00110001000000xxxxxxxxxxxxxxxx", InstEmit.Ld__Vms, typeof(OpCodeSimdMemMs)); + SetA64("0x001100110xxxxxxxxxxxxxxxxxxxxx", InstEmit.Ld__Vms, typeof(OpCodeSimdMemMs)); + SetA64("0x00110101x00000xxxxxxxxxxxxxxxx", InstEmit.Ld__Vss, typeof(OpCodeSimdMemSs)); + SetA64("0x00110111xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Ld__Vss, typeof(OpCodeSimdMemSs)); + SetA64("xx10110xx1xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Ldp, typeof(OpCodeSimdMemPair)); + SetA64("xx111100x10xxxxxxxxx00xxxxxxxxxx", InstEmit.Ldr, typeof(OpCodeSimdMemImm)); + SetA64("xx111100x10xxxxxxxxx01xxxxxxxxxx", InstEmit.Ldr, typeof(OpCodeSimdMemImm)); + SetA64("xx111100x10xxxxxxxxx11xxxxxxxxxx", InstEmit.Ldr, typeof(OpCodeSimdMemImm)); + SetA64("xx111101x1xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Ldr, typeof(OpCodeSimdMemImm)); + SetA64("xx111100x11xxxxxxxxx10xxxxxxxxxx", InstEmit.Ldr, typeof(OpCodeSimdMemReg)); + SetA64("xx011100xxxxxxxxxxxxxxxxxxxxxxxx", InstEmit.LdrLit, typeof(OpCodeSimdMemLit)); + SetA64("0x001110<<1xxxxx100101xxxxxxxxxx", InstEmit.Mla_V, typeof(OpCodeSimdReg)); + SetA64("0x101111xxxxxxxx0000x0xxxxxxxxxx", InstEmit.Mla_Ve, typeof(OpCodeSimdRegElem)); + SetA64("0x101110<<1xxxxx100101xxxxxxxxxx", InstEmit.Mls_V, typeof(OpCodeSimdReg)); + SetA64("0x101111xxxxxxxx0100x0xxxxxxxxxx", InstEmit.Mls_Ve, typeof(OpCodeSimdRegElem)); + SetA64("0x00111100000xxx0xx001xxxxxxxxxx", InstEmit.Movi_V, typeof(OpCodeSimdImm)); + SetA64("0x00111100000xxx10x001xxxxxxxxxx", InstEmit.Movi_V, typeof(OpCodeSimdImm)); + SetA64("0x00111100000xxx110x01xxxxxxxxxx", InstEmit.Movi_V, typeof(OpCodeSimdImm)); + SetA64("0xx0111100000xxx111001xxxxxxxxxx", InstEmit.Movi_V, typeof(OpCodeSimdImm)); + SetA64("0x001110<<1xxxxx100111xxxxxxxxxx", InstEmit.Mul_V, typeof(OpCodeSimdReg)); + SetA64("0x001111xxxxxxxx1000x0xxxxxxxxxx", InstEmit.Mul_Ve, typeof(OpCodeSimdRegElem)); + SetA64("0x10111100000xxx0xx001xxxxxxxxxx", InstEmit.Mvni_V, typeof(OpCodeSimdImm)); + SetA64("0x10111100000xxx10x001xxxxxxxxxx", InstEmit.Mvni_V, typeof(OpCodeSimdImm)); + SetA64("0x10111100000xxx110x01xxxxxxxxxx", InstEmit.Mvni_V, typeof(OpCodeSimdImm)); + SetA64("0111111011100000101110xxxxxxxxxx", InstEmit.Neg_S, typeof(OpCodeSimd)); + SetA64("0>101110<<100000101110xxxxxxxxxx", InstEmit.Neg_V, typeof(OpCodeSimd)); + SetA64("0x10111000100000010110xxxxxxxxxx", InstEmit.Not_V, typeof(OpCodeSimd)); + SetA64("0x001110111xxxxx000111xxxxxxxxxx", InstEmit.Orn_V, typeof(OpCodeSimdReg)); + SetA64("0x001110101xxxxx000111xxxxxxxxxx", InstEmit.Orr_V, typeof(OpCodeSimdReg)); + SetA64("0x00111100000xxx<>>xxx100011xxxxxxxxxx", InstEmit.Rshrn_V, typeof(OpCodeSimdShImm)); + SetA64("0x101110<<1xxxxx011000xxxxxxxxxx", InstEmit.Rsubhn_V, typeof(OpCodeSimdReg)); + SetA64("0x001110<<1xxxxx011111xxxxxxxxxx", InstEmit.Saba_V, typeof(OpCodeSimdReg)); + SetA64("0x001110<<1xxxxx010100xxxxxxxxxx", InstEmit.Sabal_V, typeof(OpCodeSimdReg)); + SetA64("0x001110<<1xxxxx011101xxxxxxxxxx", InstEmit.Sabd_V, typeof(OpCodeSimdReg)); + SetA64("0x001110<<1xxxxx011100xxxxxxxxxx", InstEmit.Sabdl_V, typeof(OpCodeSimdReg)); + SetA64("0x001110<<100000011010xxxxxxxxxx", InstEmit.Sadalp_V, typeof(OpCodeSimd)); + SetA64("0x001110<<1xxxxx000000xxxxxxxxxx", InstEmit.Saddl_V, typeof(OpCodeSimdReg)); + SetA64("0x001110<<100000001010xxxxxxxxxx", InstEmit.Saddlp_V, typeof(OpCodeSimd)); + SetA64("0x001110<<1xxxxx000100xxxxxxxxxx", InstEmit.Saddw_V, typeof(OpCodeSimdReg)); + SetA64("x0011110xx100010000000xxxxxxxxxx", InstEmit.Scvtf_Gp, typeof(OpCodeSimdCvt)); + SetA64("010111100x100001110110xxxxxxxxxx", InstEmit.Scvtf_S, typeof(OpCodeSimd)); + SetA64("0x0011100x100001110110xxxxxxxxxx", InstEmit.Scvtf_V, typeof(OpCodeSimd)); + SetA64("01011110000xxxxx000000xxxxxxxxxx", InstEmit.Sha1c_V, typeof(OpCodeSimdReg)); + SetA64("0101111000101000000010xxxxxxxxxx", InstEmit.Sha1h_V, typeof(OpCodeSimd)); + SetA64("01011110000xxxxx001000xxxxxxxxxx", InstEmit.Sha1m_V, typeof(OpCodeSimdReg)); + SetA64("01011110000xxxxx000100xxxxxxxxxx", InstEmit.Sha1p_V, typeof(OpCodeSimdReg)); + SetA64("01011110000xxxxx001100xxxxxxxxxx", InstEmit.Sha1su0_V, typeof(OpCodeSimdReg)); + SetA64("0101111000101000000110xxxxxxxxxx", InstEmit.Sha1su1_V, typeof(OpCodeSimd)); + SetA64("01011110000xxxxx010000xxxxxxxxxx", InstEmit.Sha256h_V, typeof(OpCodeSimdReg)); + SetA64("01011110000xxxxx010100xxxxxxxxxx", InstEmit.Sha256h2_V, typeof(OpCodeSimdReg)); + SetA64("0101111000101000001010xxxxxxxxxx", InstEmit.Sha256su0_V, typeof(OpCodeSimd)); + SetA64("01011110000xxxxx011000xxxxxxxxxx", InstEmit.Sha256su1_V, typeof(OpCodeSimdReg)); + SetA64("0x001110<<1xxxxx000001xxxxxxxxxx", InstEmit.Shadd_V, typeof(OpCodeSimdReg)); + SetA64("0101111101xxxxxx010101xxxxxxxxxx", InstEmit.Shl_S, typeof(OpCodeSimdShImm)); + SetA64("0x00111100>>>xxx010101xxxxxxxxxx", InstEmit.Shl_V, typeof(OpCodeSimdShImm)); + SetA64("0100111101xxxxxx010101xxxxxxxxxx", InstEmit.Shl_V, typeof(OpCodeSimdShImm)); + SetA64("0x101110<<100001001110xxxxxxxxxx", InstEmit.Shll_V, typeof(OpCodeSimd)); + SetA64("0x00111100>>>xxx100001xxxxxxxxxx", InstEmit.Shrn_V, typeof(OpCodeSimdShImm)); + SetA64("0x001110<<1xxxxx001001xxxxxxxxxx", InstEmit.Shsub_V, typeof(OpCodeSimdReg)); + SetA64("0x1011110>>>>xxx010101xxxxxxxxxx", InstEmit.Sli_V, typeof(OpCodeSimdShImm)); + SetA64("0x001110<<1xxxxx011001xxxxxxxxxx", InstEmit.Smax_V, typeof(OpCodeSimdReg)); + SetA64("0x001110<<1xxxxx101001xxxxxxxxxx", InstEmit.Smaxp_V, typeof(OpCodeSimdReg)); + SetA64("0x001110<<1xxxxx011011xxxxxxxxxx", InstEmit.Smin_V, typeof(OpCodeSimdReg)); + SetA64("0x001110<<1xxxxx101011xxxxxxxxxx", InstEmit.Sminp_V, typeof(OpCodeSimdReg)); + SetA64("0x001110<<1xxxxx100000xxxxxxxxxx", InstEmit.Smlal_V, typeof(OpCodeSimdReg)); + SetA64("0x001110<<1xxxxx101000xxxxxxxxxx", InstEmit.Smlsl_V, typeof(OpCodeSimdReg)); + SetA64("0x001110000xxxxx001011xxxxxxxxxx", InstEmit.Smov_S, typeof(OpCodeSimdIns)); + SetA64("0x001110<<1xxxxx110000xxxxxxxxxx", InstEmit.Smull_V, typeof(OpCodeSimdReg)); + SetA64("01011110xx100000011110xxxxxxxxxx", InstEmit.Sqabs_S, typeof(OpCodeSimd)); + SetA64("0>001110<<100000011110xxxxxxxxxx", InstEmit.Sqabs_V, typeof(OpCodeSimd)); + SetA64("01011110xx1xxxxx000011xxxxxxxxxx", InstEmit.Sqadd_S, typeof(OpCodeSimdReg)); + SetA64("0>001110<<1xxxxx000011xxxxxxxxxx", InstEmit.Sqadd_V, typeof(OpCodeSimdReg)); + SetA64("01011110011xxxxx101101xxxxxxxxxx", InstEmit.Sqdmulh_S, typeof(OpCodeSimdReg)); + SetA64("01011110101xxxxx101101xxxxxxxxxx", InstEmit.Sqdmulh_S, typeof(OpCodeSimdReg)); + SetA64("0x001110011xxxxx101101xxxxxxxxxx", InstEmit.Sqdmulh_V, typeof(OpCodeSimdReg)); + SetA64("0x001110101xxxxx101101xxxxxxxxxx", InstEmit.Sqdmulh_V, typeof(OpCodeSimdReg)); + SetA64("01111110xx100000011110xxxxxxxxxx", InstEmit.Sqneg_S, typeof(OpCodeSimd)); + SetA64("0>101110<<100000011110xxxxxxxxxx", InstEmit.Sqneg_V, typeof(OpCodeSimd)); + SetA64("01111110011xxxxx101101xxxxxxxxxx", InstEmit.Sqrdmulh_S, typeof(OpCodeSimdReg)); + SetA64("01111110101xxxxx101101xxxxxxxxxx", InstEmit.Sqrdmulh_S, typeof(OpCodeSimdReg)); + SetA64("0x101110011xxxxx101101xxxxxxxxxx", InstEmit.Sqrdmulh_V, typeof(OpCodeSimdReg)); + SetA64("0x101110101xxxxx101101xxxxxxxxxx", InstEmit.Sqrdmulh_V, typeof(OpCodeSimdReg)); + SetA64("0101111100>>>xxx100111xxxxxxxxxx", InstEmit.Sqrshrn_S, typeof(OpCodeSimdShImm)); + SetA64("0x00111100>>>xxx100111xxxxxxxxxx", InstEmit.Sqrshrn_V, typeof(OpCodeSimdShImm)); + SetA64("0111111100>>>xxx100011xxxxxxxxxx", InstEmit.Sqrshrun_S, typeof(OpCodeSimdShImm)); + SetA64("0x10111100>>>xxx100011xxxxxxxxxx", InstEmit.Sqrshrun_V, typeof(OpCodeSimdShImm)); + SetA64("0101111100>>>xxx100101xxxxxxxxxx", InstEmit.Sqshrn_S, typeof(OpCodeSimdShImm)); + SetA64("0x00111100>>>xxx100101xxxxxxxxxx", InstEmit.Sqshrn_V, typeof(OpCodeSimdShImm)); + SetA64("0111111100>>>xxx100001xxxxxxxxxx", InstEmit.Sqshrun_S, typeof(OpCodeSimdShImm)); + SetA64("0x10111100>>>xxx100001xxxxxxxxxx", InstEmit.Sqshrun_V, typeof(OpCodeSimdShImm)); + SetA64("01011110xx1xxxxx001011xxxxxxxxxx", InstEmit.Sqsub_S, typeof(OpCodeSimdReg)); + SetA64("0>001110<<1xxxxx001011xxxxxxxxxx", InstEmit.Sqsub_V, typeof(OpCodeSimdReg)); + SetA64("01011110<<100001010010xxxxxxxxxx", InstEmit.Sqxtn_S, typeof(OpCodeSimd)); + SetA64("0x001110<<100001010010xxxxxxxxxx", InstEmit.Sqxtn_V, typeof(OpCodeSimd)); + SetA64("01111110<<100001001010xxxxxxxxxx", InstEmit.Sqxtun_S, typeof(OpCodeSimd)); + SetA64("0x101110<<100001001010xxxxxxxxxx", InstEmit.Sqxtun_V, typeof(OpCodeSimd)); + SetA64("0x001110<<1xxxxx000101xxxxxxxxxx", InstEmit.Srhadd_V, typeof(OpCodeSimdReg)); + SetA64("0101111101xxxxxx001001xxxxxxxxxx", InstEmit.Srshr_S, typeof(OpCodeSimdShImm)); + SetA64("0x00111100>>>xxx001001xxxxxxxxxx", InstEmit.Srshr_V, typeof(OpCodeSimdShImm)); + SetA64("0100111101xxxxxx001001xxxxxxxxxx", InstEmit.Srshr_V, typeof(OpCodeSimdShImm)); + SetA64("0101111101xxxxxx001101xxxxxxxxxx", InstEmit.Srsra_S, typeof(OpCodeSimdShImm)); + SetA64("0x00111100>>>xxx001101xxxxxxxxxx", InstEmit.Srsra_V, typeof(OpCodeSimdShImm)); + SetA64("0100111101xxxxxx001101xxxxxxxxxx", InstEmit.Srsra_V, typeof(OpCodeSimdShImm)); + SetA64("0>001110<<1xxxxx010001xxxxxxxxxx", InstEmit.Sshl_V, typeof(OpCodeSimdReg)); + SetA64("0x00111100>>>xxx101001xxxxxxxxxx", InstEmit.Sshll_V, typeof(OpCodeSimdShImm)); + SetA64("0101111101xxxxxx000001xxxxxxxxxx", InstEmit.Sshr_S, typeof(OpCodeSimdShImm)); + SetA64("0x00111100>>>xxx000001xxxxxxxxxx", InstEmit.Sshr_V, typeof(OpCodeSimdShImm)); + SetA64("0100111101xxxxxx000001xxxxxxxxxx", InstEmit.Sshr_V, typeof(OpCodeSimdShImm)); + SetA64("0101111101xxxxxx000101xxxxxxxxxx", InstEmit.Ssra_S, typeof(OpCodeSimdShImm)); + SetA64("0x00111100>>>xxx000101xxxxxxxxxx", InstEmit.Ssra_V, typeof(OpCodeSimdShImm)); + SetA64("0100111101xxxxxx000101xxxxxxxxxx", InstEmit.Ssra_V, typeof(OpCodeSimdShImm)); + SetA64("0x001110<<1xxxxx001000xxxxxxxxxx", InstEmit.Ssubl_V, typeof(OpCodeSimdReg)); + SetA64("0x001110<<1xxxxx001100xxxxxxxxxx", InstEmit.Ssubw_V, typeof(OpCodeSimdReg)); + SetA64("0x00110000000000xxxxxxxxxxxxxxxx", InstEmit.St__Vms, typeof(OpCodeSimdMemMs)); + SetA64("0x001100100xxxxxxxxxxxxxxxxxxxxx", InstEmit.St__Vms, typeof(OpCodeSimdMemMs)); + SetA64("0x00110100x00000xxxxxxxxxxxxxxxx", InstEmit.St__Vss, typeof(OpCodeSimdMemSs)); + SetA64("0x00110110xxxxxxxxxxxxxxxxxxxxxx", InstEmit.St__Vss, typeof(OpCodeSimdMemSs)); + SetA64("xx10110xx0xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Stp, typeof(OpCodeSimdMemPair)); + SetA64("xx111100x00xxxxxxxxx00xxxxxxxxxx", InstEmit.Str, typeof(OpCodeSimdMemImm)); + SetA64("xx111100x00xxxxxxxxx01xxxxxxxxxx", InstEmit.Str, typeof(OpCodeSimdMemImm)); + SetA64("xx111100x00xxxxxxxxx11xxxxxxxxxx", InstEmit.Str, typeof(OpCodeSimdMemImm)); + SetA64("xx111101x0xxxxxxxxxxxxxxxxxxxxxx", InstEmit.Str, typeof(OpCodeSimdMemImm)); + SetA64("xx111100x01xxxxxxxxx10xxxxxxxxxx", InstEmit.Str, typeof(OpCodeSimdMemReg)); + SetA64("01111110111xxxxx100001xxxxxxxxxx", InstEmit.Sub_S, typeof(OpCodeSimdReg)); + SetA64("0>101110<<1xxxxx100001xxxxxxxxxx", InstEmit.Sub_V, typeof(OpCodeSimdReg)); + SetA64("0x001110<<1xxxxx011000xxxxxxxxxx", InstEmit.Subhn_V, typeof(OpCodeSimdReg)); + SetA64("01011110xx100000001110xxxxxxxxxx", InstEmit.Suqadd_S, typeof(OpCodeSimd)); + SetA64("0>001110<<100000001110xxxxxxxxxx", InstEmit.Suqadd_V, typeof(OpCodeSimd)); + SetA64("0x001110000xxxxx0xx000xxxxxxxxxx", InstEmit.Tbl_V, typeof(OpCodeSimdTbl)); + SetA64("0>001110<<0xxxxx001010xxxxxxxxxx", InstEmit.Trn1_V, typeof(OpCodeSimdReg)); + SetA64("0>001110<<0xxxxx011010xxxxxxxxxx", InstEmit.Trn2_V, typeof(OpCodeSimdReg)); + SetA64("0x101110<<1xxxxx011111xxxxxxxxxx", InstEmit.Uaba_V, typeof(OpCodeSimdReg)); + SetA64("0x101110<<1xxxxx010100xxxxxxxxxx", InstEmit.Uabal_V, typeof(OpCodeSimdReg)); + SetA64("0x101110<<1xxxxx011101xxxxxxxxxx", InstEmit.Uabd_V, typeof(OpCodeSimdReg)); + SetA64("0x101110<<1xxxxx011100xxxxxxxxxx", InstEmit.Uabdl_V, typeof(OpCodeSimdReg)); + SetA64("0x101110<<100000011010xxxxxxxxxx", InstEmit.Uadalp_V, typeof(OpCodeSimd)); + SetA64("0x101110<<1xxxxx000000xxxxxxxxxx", InstEmit.Uaddl_V, typeof(OpCodeSimdReg)); + SetA64("0x101110<<100000001010xxxxxxxxxx", InstEmit.Uaddlp_V, typeof(OpCodeSimd)); + SetA64("001011100x110000001110xxxxxxxxxx", InstEmit.Uaddlv_V, typeof(OpCodeSimd)); + SetA64("01101110<<110000001110xxxxxxxxxx", InstEmit.Uaddlv_V, typeof(OpCodeSimd)); + SetA64("0x101110<<1xxxxx000100xxxxxxxxxx", InstEmit.Uaddw_V, typeof(OpCodeSimdReg)); + SetA64("x0011110xx100011000000xxxxxxxxxx", InstEmit.Ucvtf_Gp, typeof(OpCodeSimdCvt)); + SetA64("011111100x100001110110xxxxxxxxxx", InstEmit.Ucvtf_S, typeof(OpCodeSimd)); + SetA64("0x1011100x100001110110xxxxxxxxxx", InstEmit.Ucvtf_V, typeof(OpCodeSimd)); + SetA64("0x101110<<1xxxxx000001xxxxxxxxxx", InstEmit.Uhadd_V, typeof(OpCodeSimdReg)); + SetA64("0x101110<<1xxxxx001001xxxxxxxxxx", InstEmit.Uhsub_V, typeof(OpCodeSimdReg)); + SetA64("0x101110<<1xxxxx011001xxxxxxxxxx", InstEmit.Umax_V, typeof(OpCodeSimdReg)); + SetA64("0x101110<<1xxxxx101001xxxxxxxxxx", InstEmit.Umaxp_V, typeof(OpCodeSimdReg)); + SetA64("0x101110<<1xxxxx011011xxxxxxxxxx", InstEmit.Umin_V, typeof(OpCodeSimdReg)); + SetA64("0x101110<<1xxxxx101011xxxxxxxxxx", InstEmit.Uminp_V, typeof(OpCodeSimdReg)); + SetA64("0x101110<<1xxxxx100000xxxxxxxxxx", InstEmit.Umlal_V, typeof(OpCodeSimdReg)); + SetA64("0x101110<<1xxxxx101000xxxxxxxxxx", InstEmit.Umlsl_V, typeof(OpCodeSimdReg)); + SetA64("0x001110000xxxxx001111xxxxxxxxxx", InstEmit.Umov_S, typeof(OpCodeSimdIns)); + SetA64("0x101110<<1xxxxx110000xxxxxxxxxx", InstEmit.Umull_V, typeof(OpCodeSimdReg)); + SetA64("01111110xx1xxxxx000011xxxxxxxxxx", InstEmit.Uqadd_S, typeof(OpCodeSimdReg)); + SetA64("0>101110<<1xxxxx000011xxxxxxxxxx", InstEmit.Uqadd_V, typeof(OpCodeSimdReg)); + SetA64("0111111100>>>xxx100111xxxxxxxxxx", InstEmit.Uqrshrn_S, typeof(OpCodeSimdShImm)); + SetA64("0x10111100>>>xxx100111xxxxxxxxxx", InstEmit.Uqrshrn_V, typeof(OpCodeSimdShImm)); + SetA64("0111111100>>>xxx100101xxxxxxxxxx", InstEmit.Uqshrn_S, typeof(OpCodeSimdShImm)); + SetA64("0x10111100>>>xxx100101xxxxxxxxxx", InstEmit.Uqshrn_V, typeof(OpCodeSimdShImm)); + SetA64("01111110xx1xxxxx001011xxxxxxxxxx", InstEmit.Uqsub_S, typeof(OpCodeSimdReg)); + SetA64("0>101110<<1xxxxx001011xxxxxxxxxx", InstEmit.Uqsub_V, typeof(OpCodeSimdReg)); + SetA64("01111110<<100001010010xxxxxxxxxx", InstEmit.Uqxtn_S, typeof(OpCodeSimd)); + SetA64("0x101110<<100001010010xxxxxxxxxx", InstEmit.Uqxtn_V, typeof(OpCodeSimd)); + SetA64("0x101110<<1xxxxx000101xxxxxxxxxx", InstEmit.Urhadd_V, typeof(OpCodeSimdReg)); + SetA64("0111111101xxxxxx001001xxxxxxxxxx", InstEmit.Urshr_S, typeof(OpCodeSimdShImm)); + SetA64("0x10111100>>>xxx001001xxxxxxxxxx", InstEmit.Urshr_V, typeof(OpCodeSimdShImm)); + SetA64("0110111101xxxxxx001001xxxxxxxxxx", InstEmit.Urshr_V, typeof(OpCodeSimdShImm)); + SetA64("0111111101xxxxxx001101xxxxxxxxxx", InstEmit.Ursra_S, typeof(OpCodeSimdShImm)); + SetA64("0x10111100>>>xxx001101xxxxxxxxxx", InstEmit.Ursra_V, typeof(OpCodeSimdShImm)); + SetA64("0110111101xxxxxx001101xxxxxxxxxx", InstEmit.Ursra_V, typeof(OpCodeSimdShImm)); + SetA64("0>101110<<1xxxxx010001xxxxxxxxxx", InstEmit.Ushl_V, typeof(OpCodeSimdReg)); + SetA64("0x10111100>>>xxx101001xxxxxxxxxx", InstEmit.Ushll_V, typeof(OpCodeSimdShImm)); + SetA64("0111111101xxxxxx000001xxxxxxxxxx", InstEmit.Ushr_S, typeof(OpCodeSimdShImm)); + SetA64("0x10111100>>>xxx000001xxxxxxxxxx", InstEmit.Ushr_V, typeof(OpCodeSimdShImm)); + SetA64("0110111101xxxxxx000001xxxxxxxxxx", InstEmit.Ushr_V, typeof(OpCodeSimdShImm)); + SetA64("01111110xx100000001110xxxxxxxxxx", InstEmit.Usqadd_S, typeof(OpCodeSimd)); + SetA64("0>101110<<100000001110xxxxxxxxxx", InstEmit.Usqadd_V, typeof(OpCodeSimd)); + SetA64("0111111101xxxxxx000101xxxxxxxxxx", InstEmit.Usra_S, typeof(OpCodeSimdShImm)); + SetA64("0x10111100>>>xxx000101xxxxxxxxxx", InstEmit.Usra_V, typeof(OpCodeSimdShImm)); + SetA64("0110111101xxxxxx000101xxxxxxxxxx", InstEmit.Usra_V, typeof(OpCodeSimdShImm)); + SetA64("0x101110<<1xxxxx001000xxxxxxxxxx", InstEmit.Usubl_V, typeof(OpCodeSimdReg)); + SetA64("0x101110<<1xxxxx001100xxxxxxxxxx", InstEmit.Usubw_V, typeof(OpCodeSimdReg)); + SetA64("0>001110<<0xxxxx000110xxxxxxxxxx", InstEmit.Uzp1_V, typeof(OpCodeSimdReg)); + SetA64("0>001110<<0xxxxx010110xxxxxxxxxx", InstEmit.Uzp2_V, typeof(OpCodeSimdReg)); + SetA64("0x001110<<100001001010xxxxxxxxxx", InstEmit.Xtn_V, typeof(OpCodeSimd)); + SetA64("0>001110<<0xxxxx001110xxxxxxxxxx", InstEmit.Zip1_V, typeof(OpCodeSimdReg)); + SetA64("0>001110<<0xxxxx011110xxxxxxxxxx", InstEmit.Zip2_V, typeof(OpCodeSimdReg)); +#endregion + +#region "Generate InstA64FastLookup Table (AArch64)" + var tmp = new List[_fastLookupSize]; + for (int i = 0; i < _fastLookupSize; i++) + { + tmp[i] = new List(); + } + + foreach (var inst in _allInstA64) + { + int mask = ToFastLookupIndex(inst.Mask); + int value = ToFastLookupIndex(inst.Value); + + for (int i = 0; i < _fastLookupSize; i++) + { + if ((i & mask) == value) + { + tmp[i].Add(inst); + } + } + } + + for (int i = 0; i < _fastLookupSize; i++) + { + _instA64FastLookup[i] = tmp[i].ToArray(); + } +#endregion + } + + private class InstInfo + { + public int Mask; + public int Value; + + public Inst Inst; + + public InstInfo(int mask, int value, Inst inst) + { + Mask = mask; + Value = value; + Inst = inst; + } + } + + private static List _allInstA32 = new List(); + private static List _allInstA64 = new List(); + + private static int _fastLookupSize = 0x1000; + private static InstInfo[][] _instA64FastLookup = new InstInfo[_fastLookupSize][]; + + private static void SetA32(string encoding, InstInterpreter interpreter, Type type) + { + Set(encoding, new Inst(interpreter, null, type), ExecutionMode.AArch32); + } + + private static void SetA64(string encoding, InstEmitter emitter, Type type) + { + Set(encoding, new Inst(null, emitter, type), ExecutionMode.AArch64); + } + + private static void Set(string encoding, Inst inst, ExecutionMode mode) + { + int bit = encoding.Length - 1; + int value = 0; + int xMask = 0; + int xBits = 0; + + int[] xPos = new int[encoding.Length]; + + int blacklisted = 0; + + for (int index = 0; index < encoding.Length; index++, bit--) + { + //Note: < and > are used on special encodings. + //The < means that we should never have ALL bits with the '<' set. + //So, when the encoding has <<, it means that 00, 01, and 10 are valid, + //but not 11. <<< is 000, 001, ..., 110 but NOT 111, and so on... + //For >, the invalid value is zero. So, for >> 01, 10 and 11 are valid, + //but 00 isn't. + char chr = encoding[index]; + + if (chr == '1') + { + value |= 1 << bit; + } + else if (chr == 'x') + { + xMask |= 1 << bit; + } + else if (chr == '>') + { + xPos[xBits++] = bit; + } + else if (chr == '<') + { + xPos[xBits++] = bit; + + blacklisted |= 1 << bit; + } + else if (chr != '0') + { + throw new ArgumentException(nameof(encoding)); + } + } + + xMask = ~xMask; + + if (xBits == 0) + { + InsertInst(xMask, value, inst, mode); + + return; + } + + for (int index = 0; index < (1 << xBits); index++) + { + int mask = 0; + + for (int x = 0; x < xBits; x++) + { + mask |= ((index >> x) & 1) << xPos[x]; + } + + if (mask != blacklisted) + { + InsertInst(xMask, value | mask, inst, mode); + } + } + } + + private static void InsertInst( + int xMask, + int value, + Inst inst, + ExecutionMode mode) + { + InstInfo info = new InstInfo(xMask, value, inst); + + if (mode == ExecutionMode.AArch64) + { + _allInstA64.Add(info); + } + else + { + _allInstA32.Add(info); + } + } + + public static Inst GetInstA32(int opCode) + { + return GetInstFromList(_allInstA32, opCode); + } + + public static Inst GetInstA64(int opCode) + { + return GetInstFromList(_instA64FastLookup[ToFastLookupIndex(opCode)], opCode); + } + + private static int ToFastLookupIndex(int value) + { + return ((value >> 10) & 0x00F) | ((value >> 18) & 0xFF0); + } + + private static Inst GetInstFromList(IEnumerable instList, int opCode) + { + foreach (var node in instList) + { + if ((opCode & node.Mask) == node.Value) + { + return node.Inst; + } + } + + return Inst.Undefined; + } + } +} diff --git a/ChocolArm64/AOptimizations.cs b/ChocolArm64/Optimizations.cs similarity index 95% rename from ChocolArm64/AOptimizations.cs rename to ChocolArm64/Optimizations.cs index 9955f2898a..f2b0ffba1a 100644 --- a/ChocolArm64/AOptimizations.cs +++ b/ChocolArm64/Optimizations.cs @@ -1,6 +1,6 @@ using System.Runtime.Intrinsics.X86; -public static class AOptimizations +public static class Optimizations { internal static bool FastFP = true; diff --git a/ChocolArm64/State/AThreadState.cs b/ChocolArm64/State/AThreadState.cs index 644317988e..08c70d5882 100644 --- a/ChocolArm64/State/AThreadState.cs +++ b/ChocolArm64/State/AThreadState.cs @@ -16,7 +16,7 @@ namespace ChocolArm64.State private const int MinInstForCheck = 4000000; - internal AExecutionMode ExecutionMode; + internal ExecutionMode ExecutionMode; //AArch32 state. public uint R0, R1, R2, R3, @@ -59,10 +59,10 @@ namespace ChocolArm64.State { get { - return (Negative ? (int)ApState.N : 0) | - (Zero ? (int)ApState.Z : 0) | - (Carry ? (int)ApState.C : 0) | - (Overflow ? (int)ApState.V : 0); + return (Negative ? (int)PState.N : 0) | + (Zero ? (int)PState.Z : 0) | + (Carry ? (int)PState.C : 0) | + (Overflow ? (int)PState.V : 0); } } @@ -81,9 +81,9 @@ namespace ChocolArm64.State } public event EventHandler Interrupt; - public event EventHandler Break; - public event EventHandler SvcCall; - public event EventHandler Undefined; + public event EventHandler Break; + public event EventHandler SvcCall; + public event EventHandler Undefined; private static Stopwatch _tickCounter; @@ -133,32 +133,32 @@ namespace ChocolArm64.State internal void OnBreak(long position, int imm) { - Break?.Invoke(this, new AInstExceptionEventArgs(position, imm)); + Break?.Invoke(this, new InstExceptionEventArgs(position, imm)); } internal void OnSvcCall(long position, int imm) { - SvcCall?.Invoke(this, new AInstExceptionEventArgs(position, imm)); + SvcCall?.Invoke(this, new InstExceptionEventArgs(position, imm)); } internal void OnUndefined(long position, int rawOpCode) { - Undefined?.Invoke(this, new AInstUndefinedEventArgs(position, rawOpCode)); + Undefined?.Invoke(this, new InstUndefinedEventArgs(position, rawOpCode)); } - internal bool GetFpcrFlag(AFpcr flag) + internal bool GetFpcrFlag(Fpcr flag) { return (Fpcr & (1 << (int)flag)) != 0; } - internal void SetFpsrFlag(AFpsr flag) + internal void SetFpsrFlag(Fpsr flag) { Fpsr |= 1 << (int)flag; } - internal ARoundMode FPRoundingMode() + internal RoundMode FPRoundingMode() { - return (ARoundMode)((Fpcr >> (int)State.AFpcr.RMode) & 3); + return (RoundMode)((Fpcr >> (int)State.Fpcr.RMode) & 3); } } } diff --git a/ChocolArm64/State/AExecutionMode.cs b/ChocolArm64/State/ExecutionMode.cs similarity index 76% rename from ChocolArm64/State/AExecutionMode.cs rename to ChocolArm64/State/ExecutionMode.cs index 8632da7747..4b8c17cec0 100644 --- a/ChocolArm64/State/AExecutionMode.cs +++ b/ChocolArm64/State/ExecutionMode.cs @@ -1,6 +1,6 @@ namespace ChocolArm64.State { - enum AExecutionMode + enum ExecutionMode { AArch32, AArch64 diff --git a/ChocolArm64/State/AFpExc.cs b/ChocolArm64/State/FpExc.cs similarity index 92% rename from ChocolArm64/State/AFpExc.cs rename to ChocolArm64/State/FpExc.cs index 04c11045dd..5cb7a402ff 100644 --- a/ChocolArm64/State/AFpExc.cs +++ b/ChocolArm64/State/FpExc.cs @@ -1,6 +1,6 @@ namespace ChocolArm64.State { - enum AFpExc + enum FpExc { InvalidOp = 0, DivideByZero = 1, diff --git a/ChocolArm64/State/AFpType.cs b/ChocolArm64/State/FpType.cs similarity index 87% rename from ChocolArm64/State/AFpType.cs rename to ChocolArm64/State/FpType.cs index 1e353e485f..fc2791063a 100644 --- a/ChocolArm64/State/AFpType.cs +++ b/ChocolArm64/State/FpType.cs @@ -1,6 +1,6 @@ namespace ChocolArm64.State { - enum AFpType + enum FpType { Nonzero, Zero, diff --git a/ChocolArm64/State/AFpcr.cs b/ChocolArm64/State/Fpcr.cs similarity index 90% rename from ChocolArm64/State/AFpcr.cs rename to ChocolArm64/State/Fpcr.cs index d794622b0d..908faee5f4 100644 --- a/ChocolArm64/State/AFpcr.cs +++ b/ChocolArm64/State/Fpcr.cs @@ -1,6 +1,6 @@ namespace ChocolArm64.State { - enum AFpcr + enum Fpcr { Ufe = 11, RMode = 22, diff --git a/ChocolArm64/State/AFpsr.cs b/ChocolArm64/State/Fpsr.cs similarity index 83% rename from ChocolArm64/State/AFpsr.cs rename to ChocolArm64/State/Fpsr.cs index a546a62033..ba551eefaa 100644 --- a/ChocolArm64/State/AFpsr.cs +++ b/ChocolArm64/State/Fpsr.cs @@ -1,6 +1,6 @@ namespace ChocolArm64.State { - enum AFpsr + enum Fpsr { Ufc = 3, Qc = 27 diff --git a/ChocolArm64/State/APState.cs b/ChocolArm64/State/PState.cs similarity index 94% rename from ChocolArm64/State/APState.cs rename to ChocolArm64/State/PState.cs index efa65a40ed..40636c8705 100644 --- a/ChocolArm64/State/APState.cs +++ b/ChocolArm64/State/PState.cs @@ -3,7 +3,7 @@ using System; namespace ChocolArm64.State { [Flags] - enum ApState + enum PState { VBit = 28, CBit = 29, diff --git a/ChocolArm64/State/ARegister.cs b/ChocolArm64/State/Register.cs similarity index 88% rename from ChocolArm64/State/ARegister.cs rename to ChocolArm64/State/Register.cs index e414767616..0c74c611c2 100644 --- a/ChocolArm64/State/ARegister.cs +++ b/ChocolArm64/State/Register.cs @@ -3,13 +3,13 @@ using System.Reflection; namespace ChocolArm64.State { - struct ARegister + struct Register { public int Index; - public ARegisterType Type; + public RegisterType Type; - public ARegister(int index, ARegisterType type) + public Register(int index, RegisterType type) { Index = index; Type = type; @@ -22,7 +22,7 @@ namespace ChocolArm64.State public override bool Equals(object obj) { - return obj is ARegister reg && + return obj is Register reg && reg.Index == Index && reg.Type == Type; } @@ -31,9 +31,9 @@ namespace ChocolArm64.State { switch (Type) { - case ARegisterType.Flag: return GetFieldFlag(); - case ARegisterType.Int: return GetFieldInt(); - case ARegisterType.Vector: return GetFieldVector(); + case RegisterType.Flag: return GetFieldFlag(); + case RegisterType.Int: return GetFieldInt(); + case RegisterType.Vector: return GetFieldVector(); } throw new InvalidOperationException(); @@ -41,12 +41,12 @@ namespace ChocolArm64.State private FieldInfo GetFieldFlag() { - switch ((ApState)Index) + switch ((PState)Index) { - case ApState.VBit: return GetField(nameof(AThreadState.Overflow)); - case ApState.CBit: return GetField(nameof(AThreadState.Carry)); - case ApState.ZBit: return GetField(nameof(AThreadState.Zero)); - case ApState.NBit: return GetField(nameof(AThreadState.Negative)); + case PState.VBit: return GetField(nameof(AThreadState.Overflow)); + case PState.CBit: return GetField(nameof(AThreadState.Carry)); + case PState.ZBit: return GetField(nameof(AThreadState.Zero)); + case PState.NBit: return GetField(nameof(AThreadState.Negative)); } throw new InvalidOperationException(); diff --git a/ChocolArm64/State/ARegisterSize.cs b/ChocolArm64/State/RegisterSize.cs similarity index 82% rename from ChocolArm64/State/ARegisterSize.cs rename to ChocolArm64/State/RegisterSize.cs index b513fcd839..7cc9959931 100644 --- a/ChocolArm64/State/ARegisterSize.cs +++ b/ChocolArm64/State/RegisterSize.cs @@ -1,6 +1,6 @@ namespace ChocolArm64.State { - enum ARegisterSize + enum RegisterSize { Int32, Int64, diff --git a/ChocolArm64/State/ARegisterType.cs b/ChocolArm64/State/RegisterType.cs similarity index 78% rename from ChocolArm64/State/ARegisterType.cs rename to ChocolArm64/State/RegisterType.cs index f9776bb7dd..4476d04426 100644 --- a/ChocolArm64/State/ARegisterType.cs +++ b/ChocolArm64/State/RegisterType.cs @@ -1,6 +1,6 @@ namespace ChocolArm64.State { - enum ARegisterType + enum RegisterType { Flag, Int, diff --git a/ChocolArm64/State/ARoundMode.cs b/ChocolArm64/State/RoundMode.cs similarity index 89% rename from ChocolArm64/State/ARoundMode.cs rename to ChocolArm64/State/RoundMode.cs index 297d0137cb..b687cc8e9f 100644 --- a/ChocolArm64/State/ARoundMode.cs +++ b/ChocolArm64/State/RoundMode.cs @@ -1,6 +1,6 @@ namespace ChocolArm64.State { - enum ARoundMode + enum RoundMode { ToNearest = 0, TowardsPlusInfinity = 1, diff --git a/ChocolArm64/ATranslatedSub.cs b/ChocolArm64/TranslatedSub.cs similarity index 89% rename from ChocolArm64/ATranslatedSub.cs rename to ChocolArm64/TranslatedSub.cs index 33417a4ebb..362d439012 100644 --- a/ChocolArm64/ATranslatedSub.cs +++ b/ChocolArm64/TranslatedSub.cs @@ -9,7 +9,7 @@ using System.Reflection.Emit; namespace ChocolArm64 { - class ATranslatedSub + class TranslatedSub { private delegate long Aa64Subroutine(AThreadState register, AMemory memory); @@ -24,17 +24,17 @@ namespace ChocolArm64 public DynamicMethod Method { get; private set; } - public ReadOnlyCollection Params { get; private set; } + public ReadOnlyCollection Params { get; private set; } private HashSet _callers; - private ATranslatedSubType _type; + private TranslatedSubType _type; private int _callCount; private bool _needsReJit; - public ATranslatedSub(DynamicMethod method, List Params) + public TranslatedSub(DynamicMethod method, List Params) { if (method == null) { @@ -54,7 +54,7 @@ namespace ChocolArm64 PrepareDelegate(); } - static ATranslatedSub() + static TranslatedSub() { MethodInfo mthdInfo = typeof(Aa64Subroutine).GetMethod("Invoke"); @@ -89,7 +89,7 @@ namespace ChocolArm64 generator.EmitLdargSeq(FixedArgTypes.Length); - foreach (ARegister reg in Params) + foreach (Register reg in Params) { generator.EmitLdarg(StateArgIdx); @@ -135,11 +135,11 @@ namespace ChocolArm64 } } - public void SetType(ATranslatedSubType type) + public void SetType(TranslatedSubType type) { _type = type; - if (type == ATranslatedSubType.SubTier0) + if (type == TranslatedSubType.SubTier0) { _needsReJit = true; } diff --git a/ChocolArm64/ATranslatedSubType.cs b/ChocolArm64/TranslatedSubType.cs similarity index 72% rename from ChocolArm64/ATranslatedSubType.cs rename to ChocolArm64/TranslatedSubType.cs index 14893abdfa..f57aea945d 100644 --- a/ChocolArm64/ATranslatedSubType.cs +++ b/ChocolArm64/TranslatedSubType.cs @@ -1,6 +1,6 @@ namespace ChocolArm64 { - enum ATranslatedSubType + enum TranslatedSubType { SubTier0, SubTier1 diff --git a/ChocolArm64/Translation/AILBarrier.cs b/ChocolArm64/Translation/AILBarrier.cs deleted file mode 100644 index ee2907a5f4..0000000000 --- a/ChocolArm64/Translation/AILBarrier.cs +++ /dev/null @@ -1,7 +0,0 @@ -namespace ChocolArm64.Translation -{ - struct AilBarrier : IailEmit - { - public void Emit(AilEmitter context) { } - } -} \ No newline at end of file diff --git a/ChocolArm64/Translation/AILOpCodeLoad.cs b/ChocolArm64/Translation/AILOpCodeLoad.cs deleted file mode 100644 index a90328bccb..0000000000 --- a/ChocolArm64/Translation/AILOpCodeLoad.cs +++ /dev/null @@ -1,75 +0,0 @@ -using ChocolArm64.State; -using System.Reflection.Emit; - -namespace ChocolArm64.Translation -{ - struct AilOpCodeLoad : IailEmit - { - public int Index { get; private set; } - - public AIoType IoType { get; private set; } - - public ARegisterSize RegisterSize { get; private set; } - - public AilOpCodeLoad(int index, AIoType ioType, ARegisterSize registerSize = 0) - { - Index = index; - IoType = ioType; - RegisterSize = registerSize; - } - - public void Emit(AilEmitter context) - { - switch (IoType) - { - case AIoType.Arg: context.Generator.EmitLdarg(Index); break; - - case AIoType.Fields: - { - long intInputs = context.LocalAlloc.GetIntInputs(context.GetIlBlock(Index)); - long vecInputs = context.LocalAlloc.GetVecInputs(context.GetIlBlock(Index)); - - LoadLocals(context, intInputs, ARegisterType.Int); - LoadLocals(context, vecInputs, ARegisterType.Vector); - - break; - } - - case AIoType.Flag: EmitLdloc(context, Index, ARegisterType.Flag); break; - case AIoType.Int: EmitLdloc(context, Index, ARegisterType.Int); break; - case AIoType.Vector: EmitLdloc(context, Index, ARegisterType.Vector); break; - } - } - - private void LoadLocals(AilEmitter context, long inputs, ARegisterType baseType) - { - for (int bit = 0; bit < 64; bit++) - { - long mask = 1L << bit; - - if ((inputs & mask) != 0) - { - ARegister reg = AilEmitter.GetRegFromBit(bit, baseType); - - context.Generator.EmitLdarg(ATranslatedSub.StateArgIdx); - context.Generator.Emit(OpCodes.Ldfld, reg.GetField()); - - context.Generator.EmitStloc(context.GetLocalIndex(reg)); - } - } - } - - private void EmitLdloc(AilEmitter context, int index, ARegisterType registerType) - { - ARegister reg = new ARegister(index, registerType); - - context.Generator.EmitLdloc(context.GetLocalIndex(reg)); - - if (registerType == ARegisterType.Int && - RegisterSize == ARegisterSize.Int32) - { - context.Generator.Emit(OpCodes.Conv_U4); - } - } - } -} \ No newline at end of file diff --git a/ChocolArm64/Translation/AILOpCodeStore.cs b/ChocolArm64/Translation/AILOpCodeStore.cs deleted file mode 100644 index 4c7b23867e..0000000000 --- a/ChocolArm64/Translation/AILOpCodeStore.cs +++ /dev/null @@ -1,75 +0,0 @@ -using ChocolArm64.State; -using System.Reflection.Emit; - -namespace ChocolArm64.Translation -{ - struct AilOpCodeStore : IailEmit - { - public int Index { get; private set; } - - public AIoType IoType { get; private set; } - - public ARegisterSize RegisterSize { get; private set; } - - public AilOpCodeStore(int index, AIoType ioType, ARegisterSize registerSize = 0) - { - Index = index; - IoType = ioType; - RegisterSize = registerSize; - } - - public void Emit(AilEmitter context) - { - switch (IoType) - { - case AIoType.Arg: context.Generator.EmitStarg(Index); break; - - case AIoType.Fields: - { - long intOutputs = context.LocalAlloc.GetIntOutputs(context.GetIlBlock(Index)); - long vecOutputs = context.LocalAlloc.GetVecOutputs(context.GetIlBlock(Index)); - - StoreLocals(context, intOutputs, ARegisterType.Int); - StoreLocals(context, vecOutputs, ARegisterType.Vector); - - break; - } - - case AIoType.Flag: EmitStloc(context, Index, ARegisterType.Flag); break; - case AIoType.Int: EmitStloc(context, Index, ARegisterType.Int); break; - case AIoType.Vector: EmitStloc(context, Index, ARegisterType.Vector); break; - } - } - - private void StoreLocals(AilEmitter context, long outputs, ARegisterType baseType) - { - for (int bit = 0; bit < 64; bit++) - { - long mask = 1L << bit; - - if ((outputs & mask) != 0) - { - ARegister reg = AilEmitter.GetRegFromBit(bit, baseType); - - context.Generator.EmitLdarg(ATranslatedSub.StateArgIdx); - context.Generator.EmitLdloc(context.GetLocalIndex(reg)); - - context.Generator.Emit(OpCodes.Stfld, reg.GetField()); - } - } - } - - private void EmitStloc(AilEmitter context, int index, ARegisterType registerType) - { - ARegister reg = new ARegister(index, registerType); - - if (registerType == ARegisterType.Int && - RegisterSize == ARegisterSize.Int32) - { - context.Generator.Emit(OpCodes.Conv_U8); - } - - context.Generator.EmitStloc(context.GetLocalIndex(reg)); - } - } -} \ No newline at end of file diff --git a/ChocolArm64/Translation/IAILEmit.cs b/ChocolArm64/Translation/IAILEmit.cs deleted file mode 100644 index bb4dd550ab..0000000000 --- a/ChocolArm64/Translation/IAILEmit.cs +++ /dev/null @@ -1,7 +0,0 @@ -namespace ChocolArm64.Translation -{ - interface IailEmit - { - void Emit(AilEmitter context); - } -} \ No newline at end of file diff --git a/ChocolArm64/Translation/IILEmit.cs b/ChocolArm64/Translation/IILEmit.cs new file mode 100644 index 0000000000..3c3925ee0a --- /dev/null +++ b/ChocolArm64/Translation/IILEmit.cs @@ -0,0 +1,7 @@ +namespace ChocolArm64.Translation +{ + interface IILEmit + { + void Emit(ILEmitter context); + } +} \ No newline at end of file diff --git a/ChocolArm64/Translation/ILBarrier.cs b/ChocolArm64/Translation/ILBarrier.cs new file mode 100644 index 0000000000..f931e9922d --- /dev/null +++ b/ChocolArm64/Translation/ILBarrier.cs @@ -0,0 +1,7 @@ +namespace ChocolArm64.Translation +{ + struct ILBarrier : IILEmit + { + public void Emit(ILEmitter context) { } + } +} \ No newline at end of file diff --git a/ChocolArm64/Translation/AILBlock.cs b/ChocolArm64/Translation/ILBlock.cs similarity index 52% rename from ChocolArm64/Translation/AILBlock.cs rename to ChocolArm64/Translation/ILBlock.cs index d6eb708bcb..d51e8d9ec3 100644 --- a/ChocolArm64/Translation/AILBlock.cs +++ b/ChocolArm64/Translation/ILBlock.cs @@ -2,7 +2,7 @@ using System.Collections.Generic; namespace ChocolArm64.Translation { - class AilBlock : IailEmit + class ILBlock : IILEmit { public long IntInputs { get; private set; } public long IntOutputs { get; private set; } @@ -14,19 +14,19 @@ namespace ChocolArm64.Translation public bool HasStateStore { get; private set; } - public List IlEmitters { get; private set; } + public List IlEmitters { get; private set; } - public AilBlock Next { get; set; } - public AilBlock Branch { get; set; } + public ILBlock Next { get; set; } + public ILBlock Branch { get; set; } - public AilBlock() + public ILBlock() { - IlEmitters = new List(); + IlEmitters = new List(); } - public void Add(IailEmit ilEmitter) + public void Add(IILEmit ilEmitter) { - if (ilEmitter is AilBarrier) + if (ilEmitter is ILBarrier) { //Those barriers are used to separate the groups of CIL //opcodes emitted by each ARM instruction. @@ -35,28 +35,28 @@ namespace ChocolArm64.Translation IntAwOutputs = IntOutputs; VecAwOutputs = VecOutputs; } - else if (ilEmitter is AilOpCodeLoad ld && AilEmitter.IsRegIndex(ld.Index)) + else if (ilEmitter is IlOpCodeLoad ld && ILEmitter.IsRegIndex(ld.Index)) { switch (ld.IoType) { - case AIoType.Flag: IntInputs |= ((1L << ld.Index) << 32) & ~IntAwOutputs; break; - case AIoType.Int: IntInputs |= (1L << ld.Index) & ~IntAwOutputs; break; - case AIoType.Vector: VecInputs |= (1L << ld.Index) & ~VecAwOutputs; break; + case IoType.Flag: IntInputs |= ((1L << ld.Index) << 32) & ~IntAwOutputs; break; + case IoType.Int: IntInputs |= (1L << ld.Index) & ~IntAwOutputs; break; + case IoType.Vector: VecInputs |= (1L << ld.Index) & ~VecAwOutputs; break; } } - else if (ilEmitter is AilOpCodeStore st) + else if (ilEmitter is IlOpCodeStore st) { - if (AilEmitter.IsRegIndex(st.Index)) + if (ILEmitter.IsRegIndex(st.Index)) { switch (st.IoType) { - case AIoType.Flag: IntOutputs |= (1L << st.Index) << 32; break; - case AIoType.Int: IntOutputs |= 1L << st.Index; break; - case AIoType.Vector: VecOutputs |= 1L << st.Index; break; + case IoType.Flag: IntOutputs |= (1L << st.Index) << 32; break; + case IoType.Int: IntOutputs |= 1L << st.Index; break; + case IoType.Vector: VecOutputs |= 1L << st.Index; break; } } - if (st.IoType == AIoType.Fields) + if (st.IoType == IoType.Fields) { HasStateStore = true; } @@ -65,9 +65,9 @@ namespace ChocolArm64.Translation IlEmitters.Add(ilEmitter); } - public void Emit(AilEmitter context) + public void Emit(ILEmitter context) { - foreach (IailEmit ilEmitter in IlEmitters) + foreach (IILEmit ilEmitter in IlEmitters) { ilEmitter.Emit(context); } diff --git a/ChocolArm64/Translation/AILEmitter.cs b/ChocolArm64/Translation/ILEmitter.cs similarity index 59% rename from ChocolArm64/Translation/AILEmitter.cs rename to ChocolArm64/Translation/ILEmitter.cs index ca12cac424..916e15da76 100644 --- a/ChocolArm64/Translation/AILEmitter.cs +++ b/ChocolArm64/Translation/ILEmitter.cs @@ -7,33 +7,33 @@ using System.Runtime.Intrinsics; namespace ChocolArm64.Translation { - class AilEmitter + class ILEmitter { - public ALocalAlloc LocalAlloc { get; private set; } + public LocalAlloc LocalAlloc { get; private set; } public ILGenerator Generator { get; private set; } - private Dictionary _locals; + private Dictionary _locals; - private AilBlock[] _ilBlocks; + private ILBlock[] _ilBlocks; - private AilBlock _root; + private ILBlock _root; - private ATranslatedSub _subroutine; + private TranslatedSub _subroutine; private string _subName; private int _localsCount; - public AilEmitter(ABlock[] graph, ABlock root, string subName) + public ILEmitter(Block[] graph, Block root, string subName) { _subName = subName; - _locals = new Dictionary(); + _locals = new Dictionary(); - _ilBlocks = new AilBlock[graph.Length]; + _ilBlocks = new ILBlock[graph.Length]; - AilBlock GetBlock(int index) + ILBlock GetBlock(int index) { if (index < 0 || index >= _ilBlocks.Length) { @@ -42,7 +42,7 @@ namespace ChocolArm64.Translation if (_ilBlocks[index] == null) { - _ilBlocks[index] = new AilBlock(); + _ilBlocks[index] = new ILBlock(); } return _ilBlocks[index]; @@ -50,7 +50,7 @@ namespace ChocolArm64.Translation for (int index = 0; index < _ilBlocks.Length; index++) { - AilBlock block = GetBlock(index); + ILBlock block = GetBlock(index); block.Next = GetBlock(Array.IndexOf(graph, graph[index].Next)); block.Branch = GetBlock(Array.IndexOf(graph, graph[index].Branch)); @@ -59,16 +59,16 @@ namespace ChocolArm64.Translation _root = _ilBlocks[Array.IndexOf(graph, root)]; } - public AilBlock GetIlBlock(int index) => _ilBlocks[index]; + public ILBlock GetIlBlock(int index) => _ilBlocks[index]; - public ATranslatedSub GetSubroutine() + public TranslatedSub GetSubroutine() { - LocalAlloc = new ALocalAlloc(_ilBlocks, _root); + LocalAlloc = new LocalAlloc(_ilBlocks, _root); InitSubroutine(); InitLocals(); - foreach (AilBlock ilBlock in _ilBlocks) + foreach (ILBlock ilBlock in _ilBlocks) { ilBlock.Emit(this); } @@ -78,9 +78,9 @@ namespace ChocolArm64.Translation private void InitSubroutine() { - List Params = new List(); + List Params = new List(); - void SetParams(long inputs, ARegisterType baseType) + void SetParams(long inputs, RegisterType baseType) { for (int bit = 0; bit < 64; bit++) { @@ -93,34 +93,34 @@ namespace ChocolArm64.Translation } } - SetParams(LocalAlloc.GetIntInputs(_root), ARegisterType.Int); - SetParams(LocalAlloc.GetVecInputs(_root), ARegisterType.Vector); + SetParams(LocalAlloc.GetIntInputs(_root), RegisterType.Int); + SetParams(LocalAlloc.GetVecInputs(_root), RegisterType.Vector); DynamicMethod mthd = new DynamicMethod(_subName, typeof(long), GetParamTypes(Params)); Generator = mthd.GetILGenerator(); - _subroutine = new ATranslatedSub(mthd, Params); + _subroutine = new TranslatedSub(mthd, Params); } private void InitLocals() { - int paramsStart = ATranslatedSub.FixedArgTypes.Length; + int paramsStart = TranslatedSub.FixedArgTypes.Length; - _locals = new Dictionary(); + _locals = new Dictionary(); for (int index = 0; index < _subroutine.Params.Count; index++) { - ARegister reg = _subroutine.Params[index]; + Register reg = _subroutine.Params[index]; Generator.EmitLdarg(index + paramsStart); Generator.EmitStloc(GetLocalIndex(reg)); } } - private Type[] GetParamTypes(IList Params) + private Type[] GetParamTypes(IList Params) { - Type[] fixedArgs = ATranslatedSub.FixedArgTypes; + Type[] fixedArgs = TranslatedSub.FixedArgTypes; Type[] output = new Type[Params.Count + fixedArgs.Length]; @@ -136,7 +136,7 @@ namespace ChocolArm64.Translation return output; } - public int GetLocalIndex(ARegister reg) + public int GetLocalIndex(Register reg) { if (!_locals.TryGetValue(reg, out int index)) { @@ -150,29 +150,29 @@ namespace ChocolArm64.Translation return index; } - public Type GetLocalType(ARegister reg) => GetFieldType(reg.Type); + public Type GetLocalType(Register reg) => GetFieldType(reg.Type); - public Type GetFieldType(ARegisterType regType) + public Type GetFieldType(RegisterType regType) { switch (regType) { - case ARegisterType.Flag: return typeof(bool); - case ARegisterType.Int: return typeof(ulong); - case ARegisterType.Vector: return typeof(Vector128); + case RegisterType.Flag: return typeof(bool); + case RegisterType.Int: return typeof(ulong); + case RegisterType.Vector: return typeof(Vector128); } throw new ArgumentException(nameof(regType)); } - public static ARegister GetRegFromBit(int bit, ARegisterType baseType) + public static Register GetRegFromBit(int bit, RegisterType baseType) { if (bit < 32) { - return new ARegister(bit, baseType); + return new Register(bit, baseType); } - else if (baseType == ARegisterType.Int) + else if (baseType == RegisterType.Int) { - return new ARegister(bit & 0x1f, ARegisterType.Flag); + return new Register(bit & 0x1f, RegisterType.Flag); } else { diff --git a/ChocolArm64/Translation/AILEmitterCtx.cs b/ChocolArm64/Translation/ILEmitterCtx.cs similarity index 62% rename from ChocolArm64/Translation/AILEmitterCtx.cs rename to ChocolArm64/Translation/ILEmitterCtx.cs index 50bda3c724..b0acd31563 100644 --- a/ChocolArm64/Translation/AILEmitterCtx.cs +++ b/ChocolArm64/Translation/ILEmitterCtx.cs @@ -8,23 +8,23 @@ using System.Reflection.Emit; namespace ChocolArm64.Translation { - class AilEmitterCtx + class ILEmitterCtx { - private ATranslatorCache _cache; + private TranslatorCache _cache; - private Dictionary _labels; + private Dictionary _labels; private int _blkIndex; private int _opcIndex; - private ABlock[] _graph; - private ABlock _root; - public ABlock CurrBlock => _graph[_blkIndex]; + private Block[] _graph; + private Block _root; + public Block CurrBlock => _graph[_blkIndex]; public AOpCode CurrOp => _graph[_blkIndex].OpCodes[_opcIndex]; - private AilEmitter _emitter; + private ILEmitter _emitter; - private AilBlock _ilBlock; + private ILBlock _ilBlock; private AOpCode _optOpLastCompare; private AOpCode _optOpLastFlagSet; @@ -40,19 +40,19 @@ namespace ChocolArm64.Translation private const int Tmp5Index = -5; private const int Tmp6Index = -6; - public AilEmitterCtx( - ATranslatorCache cache, - ABlock[] graph, - ABlock root, + public ILEmitterCtx( + TranslatorCache cache, + Block[] graph, + Block root, string subName) { _cache = cache ?? throw new ArgumentNullException(nameof(cache)); _graph = graph ?? throw new ArgumentNullException(nameof(graph)); _root = root ?? throw new ArgumentNullException(nameof(root)); - _labels = new Dictionary(); + _labels = new Dictionary(); - _emitter = new AilEmitter(graph, root, subName); + _emitter = new ILEmitter(graph, root, subName); _ilBlock = _emitter.GetIlBlock(0); @@ -64,7 +64,7 @@ namespace ChocolArm64.Translation } } - public ATranslatedSub GetSubroutine() + public TranslatedSub GetSubroutine() { return _emitter.GetSubroutine(); } @@ -102,12 +102,12 @@ namespace ChocolArm64.Translation CurrOp.Emitter(this); - _ilBlock.Add(new AilBarrier()); + _ilBlock.Add(new ILBarrier()); } private void EmitSynchronization() { - EmitLdarg(ATranslatedSub.StateArgIdx); + EmitLdarg(TranslatedSub.StateArgIdx); EmitLdc_I4(CurrBlock.OpCodes.Count); @@ -115,7 +115,7 @@ namespace ChocolArm64.Translation EmitLdc_I4(0); - AilLabel lblContinue = new AilLabel(); + ILLabel lblContinue = new ILLabel(); Emit(OpCodes.Bne_Un_S, lblContinue); @@ -133,28 +133,28 @@ namespace ChocolArm64.Translation return false; } - if (CurrOp.Emitter != AInstEmit.Bl) + if (CurrOp.Emitter != InstEmit.Bl) { return false; } - if (!_cache.TryGetSubroutine(((AOpCodeBImmAl)CurrOp).Imm, out ATranslatedSub subroutine)) + if (!_cache.TryGetSubroutine(((OpCodeBImmAl)CurrOp).Imm, out TranslatedSub subroutine)) { return false; } - for (int index = 0; index < ATranslatedSub.FixedArgTypes.Length; index++) + for (int index = 0; index < TranslatedSub.FixedArgTypes.Length; index++) { EmitLdarg(index); } - foreach (ARegister reg in subroutine.Params) + foreach (Register reg in subroutine.Params) { switch (reg.Type) { - case ARegisterType.Flag: Ldloc(reg.Index, AIoType.Flag); break; - case ARegisterType.Int: Ldloc(reg.Index, AIoType.Int); break; - case ARegisterType.Vector: Ldloc(reg.Index, AIoType.Vector); break; + case RegisterType.Flag: Ldloc(reg.Index, IoType.Flag); break; + case RegisterType.Int: Ldloc(reg.Index, IoType.Int); break; + case RegisterType.Vector: Ldloc(reg.Index, IoType.Vector); break; } } @@ -169,37 +169,37 @@ namespace ChocolArm64.Translation { _optOpLastCompare = CurrOp; - AInstEmitAluHelper.EmitDataLoadOpers(this); + InstEmitAluHelper.EmitDataLoadOpers(this); - Stloc(Tmp4Index, AIoType.Int); - Stloc(Tmp3Index, AIoType.Int); + Stloc(Tmp4Index, IoType.Int); + Stloc(Tmp3Index, IoType.Int); } - private Dictionary _branchOps = new Dictionary() + private Dictionary _branchOps = new Dictionary() { - { ACond.Eq, OpCodes.Beq }, - { ACond.Ne, OpCodes.Bne_Un }, - { ACond.GeUn, OpCodes.Bge_Un }, - { ACond.LtUn, OpCodes.Blt_Un }, - { ACond.GtUn, OpCodes.Bgt_Un }, - { ACond.LeUn, OpCodes.Ble_Un }, - { ACond.Ge, OpCodes.Bge }, - { ACond.Lt, OpCodes.Blt }, - { ACond.Gt, OpCodes.Bgt }, - { ACond.Le, OpCodes.Ble } + { Cond.Eq, OpCodes.Beq }, + { Cond.Ne, OpCodes.Bne_Un }, + { Cond.GeUn, OpCodes.Bge_Un }, + { Cond.LtUn, OpCodes.Blt_Un }, + { Cond.GtUn, OpCodes.Bgt_Un }, + { Cond.LeUn, OpCodes.Ble_Un }, + { Cond.Ge, OpCodes.Bge }, + { Cond.Lt, OpCodes.Blt }, + { Cond.Gt, OpCodes.Bgt }, + { Cond.Le, OpCodes.Ble } }; - public void EmitCondBranch(AilLabel target, ACond cond) + public void EmitCondBranch(ILLabel target, Cond cond) { - OpCode ilOp; + System.Reflection.Emit.OpCode ilOp; int intCond = (int)cond; if (_optOpLastCompare != null && _optOpLastCompare == _optOpLastFlagSet && _branchOps.ContainsKey(cond)) { - Ldloc(Tmp3Index, AIoType.Int, _optOpLastCompare.RegisterSize); - Ldloc(Tmp4Index, AIoType.Int, _optOpLastCompare.RegisterSize); + Ldloc(Tmp3Index, IoType.Int, _optOpLastCompare.RegisterSize); + Ldloc(Tmp4Index, IoType.Int, _optOpLastCompare.RegisterSize); ilOp = _branchOps[cond]; } @@ -209,14 +209,14 @@ namespace ChocolArm64.Translation switch (condTrue) { - case 0: EmitLdflg((int)ApState.ZBit); break; - case 1: EmitLdflg((int)ApState.CBit); break; - case 2: EmitLdflg((int)ApState.NBit); break; - case 3: EmitLdflg((int)ApState.VBit); break; + case 0: EmitLdflg((int)PState.ZBit); break; + case 1: EmitLdflg((int)PState.CBit); break; + case 2: EmitLdflg((int)PState.NBit); break; + case 3: EmitLdflg((int)PState.VBit); break; case 4: - EmitLdflg((int)ApState.CBit); - EmitLdflg((int)ApState.ZBit); + EmitLdflg((int)PState.CBit); + EmitLdflg((int)PState.ZBit); Emit(OpCodes.Not); Emit(OpCodes.And); @@ -224,14 +224,14 @@ namespace ChocolArm64.Translation case 5: case 6: - EmitLdflg((int)ApState.NBit); - EmitLdflg((int)ApState.VBit); + EmitLdflg((int)PState.NBit); + EmitLdflg((int)PState.VBit); Emit(OpCodes.Ceq); if (condTrue == 6) { - EmitLdflg((int)ApState.ZBit); + EmitLdflg((int)PState.ZBit); Emit(OpCodes.Not); Emit(OpCodes.And); @@ -251,31 +251,31 @@ namespace ChocolArm64.Translation Emit(ilOp, target); } - public void EmitCast(AIntType intType) + public void EmitCast(IntType intType) { switch (intType) { - case AIntType.UInt8: Emit(OpCodes.Conv_U1); break; - case AIntType.UInt16: Emit(OpCodes.Conv_U2); break; - case AIntType.UInt32: Emit(OpCodes.Conv_U4); break; - case AIntType.UInt64: Emit(OpCodes.Conv_U8); break; - case AIntType.Int8: Emit(OpCodes.Conv_I1); break; - case AIntType.Int16: Emit(OpCodes.Conv_I2); break; - case AIntType.Int32: Emit(OpCodes.Conv_I4); break; - case AIntType.Int64: Emit(OpCodes.Conv_I8); break; + case IntType.UInt8: Emit(OpCodes.Conv_U1); break; + case IntType.UInt16: Emit(OpCodes.Conv_U2); break; + case IntType.UInt32: Emit(OpCodes.Conv_U4); break; + case IntType.UInt64: Emit(OpCodes.Conv_U8); break; + case IntType.Int8: Emit(OpCodes.Conv_I1); break; + case IntType.Int16: Emit(OpCodes.Conv_I2); break; + case IntType.Int32: Emit(OpCodes.Conv_I4); break; + case IntType.Int64: Emit(OpCodes.Conv_I8); break; } - bool sz64 = CurrOp.RegisterSize != ARegisterSize.Int32; + bool sz64 = CurrOp.RegisterSize != RegisterSize.Int32; - if (sz64 == (intType == AIntType.UInt64 || - intType == AIntType.Int64)) + if (sz64 == (intType == IntType.UInt64 || + intType == IntType.Int64)) { return; } if (sz64) { - Emit(intType >= AIntType.Int8 + Emit(intType >= IntType.Int8 ? OpCodes.Conv_I8 : OpCodes.Conv_U8); } @@ -289,7 +289,7 @@ namespace ChocolArm64.Translation public void EmitLsr(int amount) => EmitIlShift(amount, OpCodes.Shr_Un); public void EmitAsr(int amount) => EmitIlShift(amount, OpCodes.Shr); - private void EmitIlShift(int amount, OpCode ilOp) + private void EmitIlShift(int amount, System.Reflection.Emit.OpCode ilOp) { if (amount > 0) { @@ -303,14 +303,14 @@ namespace ChocolArm64.Translation { if (amount > 0) { - Stloc(Tmp2Index, AIoType.Int); - Ldloc(Tmp2Index, AIoType.Int); + Stloc(Tmp2Index, IoType.Int); + Ldloc(Tmp2Index, IoType.Int); EmitLdc_I4(amount); Emit(OpCodes.Shr_Un); - Ldloc(Tmp2Index, AIoType.Int); + Ldloc(Tmp2Index, IoType.Int); EmitLdc_I4(CurrOp.GetBitsCount() - amount); @@ -319,11 +319,11 @@ namespace ChocolArm64.Translation } } - public AilLabel GetLabel(long position) + public ILLabel GetLabel(long position) { - if (!_labels.TryGetValue(position, out AilLabel output)) + if (!_labels.TryGetValue(position, out ILLabel output)) { - output = new AilLabel(); + output = new ILLabel(); _labels.Add(position, output); } @@ -331,29 +331,29 @@ namespace ChocolArm64.Translation return output; } - public void MarkLabel(AilLabel label) + public void MarkLabel(ILLabel label) { _ilBlock.Add(label); } - public void Emit(OpCode ilOp) + public void Emit(System.Reflection.Emit.OpCode ilOp) { - _ilBlock.Add(new AilOpCode(ilOp)); + _ilBlock.Add(new ILOpCode(ilOp)); } - public void Emit(OpCode ilOp, AilLabel label) + public void Emit(System.Reflection.Emit.OpCode ilOp, ILLabel label) { - _ilBlock.Add(new AilOpCodeBranch(ilOp, label)); + _ilBlock.Add(new ILOpCodeBranch(ilOp, label)); } public void Emit(string text) { - _ilBlock.Add(new AilOpCodeLog(text)); + _ilBlock.Add(new ILOpCodeLog(text)); } public void EmitLdarg(int index) { - _ilBlock.Add(new AilOpCodeLoad(index, AIoType.Arg)); + _ilBlock.Add(new IlOpCodeLoad(index, IoType.Arg)); } public void EmitLdintzr(int index) @@ -380,14 +380,14 @@ namespace ChocolArm64.Translation } } - public void EmitLoadState(ABlock retBlk) + public void EmitLoadState(Block retBlk) { - _ilBlock.Add(new AilOpCodeLoad(Array.IndexOf(_graph, retBlk), AIoType.Fields)); + _ilBlock.Add(new IlOpCodeLoad(Array.IndexOf(_graph, retBlk), IoType.Fields)); } public void EmitStoreState() { - _ilBlock.Add(new AilOpCodeStore(Array.IndexOf(_graph, CurrBlock), AIoType.Fields)); + _ilBlock.Add(new IlOpCodeStore(Array.IndexOf(_graph, CurrBlock), IoType.Fields)); } public void EmitLdtmp() => EmitLdint(Tmp1Index); @@ -399,33 +399,33 @@ namespace ChocolArm64.Translation public void EmitLdvectmp2() => EmitLdvec(Tmp6Index); public void EmitStvectmp2() => EmitStvec(Tmp6Index); - public void EmitLdint(int index) => Ldloc(index, AIoType.Int); - public void EmitStint(int index) => Stloc(index, AIoType.Int); + public void EmitLdint(int index) => Ldloc(index, IoType.Int); + public void EmitStint(int index) => Stloc(index, IoType.Int); - public void EmitLdvec(int index) => Ldloc(index, AIoType.Vector); - public void EmitStvec(int index) => Stloc(index, AIoType.Vector); + public void EmitLdvec(int index) => Ldloc(index, IoType.Vector); + public void EmitStvec(int index) => Stloc(index, IoType.Vector); - public void EmitLdflg(int index) => Ldloc(index, AIoType.Flag); + public void EmitLdflg(int index) => Ldloc(index, IoType.Flag); public void EmitStflg(int index) { _optOpLastFlagSet = CurrOp; - Stloc(index, AIoType.Flag); + Stloc(index, IoType.Flag); } - private void Ldloc(int index, AIoType ioType) + private void Ldloc(int index, IoType ioType) { - _ilBlock.Add(new AilOpCodeLoad(index, ioType, CurrOp.RegisterSize)); + _ilBlock.Add(new IlOpCodeLoad(index, ioType, CurrOp.RegisterSize)); } - private void Ldloc(int index, AIoType ioType, ARegisterSize registerSize) + private void Ldloc(int index, IoType ioType, RegisterSize registerSize) { - _ilBlock.Add(new AilOpCodeLoad(index, ioType, registerSize)); + _ilBlock.Add(new IlOpCodeLoad(index, ioType, registerSize)); } - private void Stloc(int index, AIoType ioType) + private void Stloc(int index, IoType ioType) { - _ilBlock.Add(new AilOpCodeStore(index, ioType, CurrOp.RegisterSize)); + _ilBlock.Add(new IlOpCodeStore(index, ioType, CurrOp.RegisterSize)); } public void EmitCallPropGet(Type objType, string propName) @@ -495,12 +495,12 @@ namespace ChocolArm64.Translation throw new ArgumentNullException(nameof(mthdInfo)); } - _ilBlock.Add(new AilOpCodeCall(mthdInfo)); + _ilBlock.Add(new ILOpCodeCall(mthdInfo)); } public void EmitLdc_I(long value) { - if (CurrOp.RegisterSize == ARegisterSize.Int32) + if (CurrOp.RegisterSize == RegisterSize.Int32) { EmitLdc_I4((int)value); } @@ -512,36 +512,36 @@ namespace ChocolArm64.Translation public void EmitLdc_I4(int value) { - _ilBlock.Add(new AilOpCodeConst(value)); + _ilBlock.Add(new ILOpCodeConst(value)); } public void EmitLdc_I8(long value) { - _ilBlock.Add(new AilOpCodeConst(value)); + _ilBlock.Add(new ILOpCodeConst(value)); } public void EmitLdc_R4(float value) { - _ilBlock.Add(new AilOpCodeConst(value)); + _ilBlock.Add(new ILOpCodeConst(value)); } public void EmitLdc_R8(double value) { - _ilBlock.Add(new AilOpCodeConst(value)); + _ilBlock.Add(new ILOpCodeConst(value)); } public void EmitZnFlagCheck() { - EmitZnCheck(OpCodes.Ceq, (int)ApState.ZBit); - EmitZnCheck(OpCodes.Clt, (int)ApState.NBit); + EmitZnCheck(OpCodes.Ceq, (int)PState.ZBit); + EmitZnCheck(OpCodes.Clt, (int)PState.NBit); } - private void EmitZnCheck(OpCode ilCmpOp, int flag) + private void EmitZnCheck(System.Reflection.Emit.OpCode ilCmpOp, int flag) { Emit(OpCodes.Dup); Emit(OpCodes.Ldc_I4_0); - if (CurrOp.RegisterSize != ARegisterSize.Int32) + if (CurrOp.RegisterSize != RegisterSize.Int32) { Emit(OpCodes.Conv_I8); } diff --git a/ChocolArm64/Translation/ILGeneratorEx.cs b/ChocolArm64/Translation/ILGeneratorEx.cs index b910d5753a..318098cc78 100644 --- a/ChocolArm64/Translation/ILGeneratorEx.cs +++ b/ChocolArm64/Translation/ILGeneratorEx.cs @@ -4,7 +4,7 @@ namespace ChocolArm64 { using System.Reflection.Emit; - static class IlGeneratorEx + static class ILGeneratorEx { public static void EmitLdc_I4(this ILGenerator generator, int value) { diff --git a/ChocolArm64/Translation/AILLabel.cs b/ChocolArm64/Translation/ILLabel.cs similarity index 76% rename from ChocolArm64/Translation/AILLabel.cs rename to ChocolArm64/Translation/ILLabel.cs index 4bd9dd0eee..4f96edccf1 100644 --- a/ChocolArm64/Translation/AILLabel.cs +++ b/ChocolArm64/Translation/ILLabel.cs @@ -2,18 +2,18 @@ using System.Reflection.Emit; namespace ChocolArm64.Translation { - class AilLabel : IailEmit + class ILLabel : IILEmit { private bool _hasLabel; private Label _lbl; - public void Emit(AilEmitter context) + public void Emit(ILEmitter context) { context.Generator.MarkLabel(GetLabel(context)); } - public Label GetLabel(AilEmitter context) + public Label GetLabel(ILEmitter context) { if (!_hasLabel) { diff --git a/ChocolArm64/Translation/AILOpCode.cs b/ChocolArm64/Translation/ILOpCode.cs similarity index 65% rename from ChocolArm64/Translation/AILOpCode.cs rename to ChocolArm64/Translation/ILOpCode.cs index d228598183..eb91639e63 100644 --- a/ChocolArm64/Translation/AILOpCode.cs +++ b/ChocolArm64/Translation/ILOpCode.cs @@ -2,16 +2,16 @@ using System.Reflection.Emit; namespace ChocolArm64.Translation { - struct AilOpCode : IailEmit + struct ILOpCode : IILEmit { private OpCode _ilOp; - public AilOpCode(OpCode ilOp) + public ILOpCode(OpCode ilOp) { _ilOp = ilOp; } - public void Emit(AilEmitter context) + public void Emit(ILEmitter context) { context.Generator.Emit(_ilOp); } diff --git a/ChocolArm64/Translation/AILOpCodeBranch.cs b/ChocolArm64/Translation/ILOpCodeBranch.cs similarity index 61% rename from ChocolArm64/Translation/AILOpCodeBranch.cs rename to ChocolArm64/Translation/ILOpCodeBranch.cs index f80c4888cc..b0ba23313f 100644 --- a/ChocolArm64/Translation/AILOpCodeBranch.cs +++ b/ChocolArm64/Translation/ILOpCodeBranch.cs @@ -2,18 +2,18 @@ using System.Reflection.Emit; namespace ChocolArm64.Translation { - struct AilOpCodeBranch : IailEmit + struct ILOpCodeBranch : IILEmit { private OpCode _ilOp; - private AilLabel _label; + private ILLabel _label; - public AilOpCodeBranch(OpCode ilOp, AilLabel label) + public ILOpCodeBranch(OpCode ilOp, ILLabel label) { _ilOp = ilOp; _label = label; } - public void Emit(AilEmitter context) + public void Emit(ILEmitter context) { context.Generator.Emit(_ilOp, _label.GetLabel(context)); } diff --git a/ChocolArm64/Translation/AILOpCodeCall.cs b/ChocolArm64/Translation/ILOpCodeCall.cs similarity index 68% rename from ChocolArm64/Translation/AILOpCodeCall.cs rename to ChocolArm64/Translation/ILOpCodeCall.cs index 6ba1ba2e0d..0b591d46ce 100644 --- a/ChocolArm64/Translation/AILOpCodeCall.cs +++ b/ChocolArm64/Translation/ILOpCodeCall.cs @@ -3,16 +3,16 @@ using System.Reflection.Emit; namespace ChocolArm64.Translation { - struct AilOpCodeCall : IailEmit + struct ILOpCodeCall : IILEmit { private MethodInfo _mthdInfo; - public AilOpCodeCall(MethodInfo mthdInfo) + public ILOpCodeCall(MethodInfo mthdInfo) { _mthdInfo = mthdInfo; } - public void Emit(AilEmitter context) + public void Emit(ILEmitter context) { context.Generator.Emit(OpCodes.Call, _mthdInfo); } diff --git a/ChocolArm64/Translation/AILOpCodeConst.cs b/ChocolArm64/Translation/ILOpCodeConst.cs similarity index 78% rename from ChocolArm64/Translation/AILOpCodeConst.cs rename to ChocolArm64/Translation/ILOpCodeConst.cs index 4259e2bd16..5497eba16f 100644 --- a/ChocolArm64/Translation/AILOpCodeConst.cs +++ b/ChocolArm64/Translation/ILOpCodeConst.cs @@ -3,7 +3,7 @@ using System.Runtime.InteropServices; namespace ChocolArm64.Translation { - class AilOpCodeConst : IailEmit + class ILOpCodeConst : IILEmit { [StructLayout(LayoutKind.Explicit, Size = 8)] private struct ImmVal @@ -26,32 +26,32 @@ namespace ChocolArm64.Translation private ConstType _type; - private AilOpCodeConst(ConstType type) + private ILOpCodeConst(ConstType type) { _type = type; } - public AilOpCodeConst(int value) : this(ConstType.Int32) + public ILOpCodeConst(int value) : this(ConstType.Int32) { _value = new ImmVal { I4 = value }; } - public AilOpCodeConst(long value) : this(ConstType.Int64) + public ILOpCodeConst(long value) : this(ConstType.Int64) { _value = new ImmVal { I8 = value }; } - public AilOpCodeConst(float value) : this(ConstType.Single) + public ILOpCodeConst(float value) : this(ConstType.Single) { _value = new ImmVal { R4 = value }; } - public AilOpCodeConst(double value) : this(ConstType.Double) + public ILOpCodeConst(double value) : this(ConstType.Double) { _value = new ImmVal { R8 = value }; } - public void Emit(AilEmitter context) + public void Emit(ILEmitter context) { switch (_type) { diff --git a/ChocolArm64/Translation/ILOpCodeLoad.cs b/ChocolArm64/Translation/ILOpCodeLoad.cs new file mode 100644 index 0000000000..9dae10cc4b --- /dev/null +++ b/ChocolArm64/Translation/ILOpCodeLoad.cs @@ -0,0 +1,75 @@ +using ChocolArm64.State; +using System.Reflection.Emit; + +namespace ChocolArm64.Translation +{ + struct IlOpCodeLoad : IILEmit + { + public int Index { get; private set; } + + public IoType IoType { get; private set; } + + public RegisterSize RegisterSize { get; private set; } + + public IlOpCodeLoad(int index, IoType ioType, RegisterSize registerSize = 0) + { + Index = index; + IoType = ioType; + RegisterSize = registerSize; + } + + public void Emit(ILEmitter context) + { + switch (IoType) + { + case IoType.Arg: context.Generator.EmitLdarg(Index); break; + + case IoType.Fields: + { + long intInputs = context.LocalAlloc.GetIntInputs(context.GetIlBlock(Index)); + long vecInputs = context.LocalAlloc.GetVecInputs(context.GetIlBlock(Index)); + + LoadLocals(context, intInputs, RegisterType.Int); + LoadLocals(context, vecInputs, RegisterType.Vector); + + break; + } + + case IoType.Flag: EmitLdloc(context, Index, RegisterType.Flag); break; + case IoType.Int: EmitLdloc(context, Index, RegisterType.Int); break; + case IoType.Vector: EmitLdloc(context, Index, RegisterType.Vector); break; + } + } + + private void LoadLocals(ILEmitter context, long inputs, RegisterType baseType) + { + for (int bit = 0; bit < 64; bit++) + { + long mask = 1L << bit; + + if ((inputs & mask) != 0) + { + Register reg = ILEmitter.GetRegFromBit(bit, baseType); + + context.Generator.EmitLdarg(TranslatedSub.StateArgIdx); + context.Generator.Emit(OpCodes.Ldfld, reg.GetField()); + + context.Generator.EmitStloc(context.GetLocalIndex(reg)); + } + } + } + + private void EmitLdloc(ILEmitter context, int index, RegisterType registerType) + { + Register reg = new Register(index, registerType); + + context.Generator.EmitLdloc(context.GetLocalIndex(reg)); + + if (registerType == RegisterType.Int && + RegisterSize == RegisterSize.Int32) + { + context.Generator.Emit(OpCodes.Conv_U4); + } + } + } +} \ No newline at end of file diff --git a/ChocolArm64/Translation/AILOpCodeLog.cs b/ChocolArm64/Translation/ILOpCodeLog.cs similarity index 62% rename from ChocolArm64/Translation/AILOpCodeLog.cs rename to ChocolArm64/Translation/ILOpCodeLog.cs index 9fda19f427..2c77021b10 100644 --- a/ChocolArm64/Translation/AILOpCodeLog.cs +++ b/ChocolArm64/Translation/ILOpCodeLog.cs @@ -1,15 +1,15 @@ namespace ChocolArm64.Translation { - struct AilOpCodeLog : IailEmit + struct ILOpCodeLog : IILEmit { private string _text; - public AilOpCodeLog(string text) + public ILOpCodeLog(string text) { _text = text; } - public void Emit(AilEmitter context) + public void Emit(ILEmitter context) { context.Generator.EmitWriteLine(_text); } diff --git a/ChocolArm64/Translation/ILOpCodeStore.cs b/ChocolArm64/Translation/ILOpCodeStore.cs new file mode 100644 index 0000000000..41326fe127 --- /dev/null +++ b/ChocolArm64/Translation/ILOpCodeStore.cs @@ -0,0 +1,75 @@ +using ChocolArm64.State; +using System.Reflection.Emit; + +namespace ChocolArm64.Translation +{ + struct IlOpCodeStore : IILEmit + { + public int Index { get; private set; } + + public IoType IoType { get; private set; } + + public RegisterSize RegisterSize { get; private set; } + + public IlOpCodeStore(int index, IoType ioType, RegisterSize registerSize = 0) + { + Index = index; + IoType = ioType; + RegisterSize = registerSize; + } + + public void Emit(ILEmitter context) + { + switch (IoType) + { + case IoType.Arg: context.Generator.EmitStarg(Index); break; + + case IoType.Fields: + { + long intOutputs = context.LocalAlloc.GetIntOutputs(context.GetIlBlock(Index)); + long vecOutputs = context.LocalAlloc.GetVecOutputs(context.GetIlBlock(Index)); + + StoreLocals(context, intOutputs, RegisterType.Int); + StoreLocals(context, vecOutputs, RegisterType.Vector); + + break; + } + + case IoType.Flag: EmitStloc(context, Index, RegisterType.Flag); break; + case IoType.Int: EmitStloc(context, Index, RegisterType.Int); break; + case IoType.Vector: EmitStloc(context, Index, RegisterType.Vector); break; + } + } + + private void StoreLocals(ILEmitter context, long outputs, RegisterType baseType) + { + for (int bit = 0; bit < 64; bit++) + { + long mask = 1L << bit; + + if ((outputs & mask) != 0) + { + Register reg = ILEmitter.GetRegFromBit(bit, baseType); + + context.Generator.EmitLdarg(TranslatedSub.StateArgIdx); + context.Generator.EmitLdloc(context.GetLocalIndex(reg)); + + context.Generator.Emit(OpCodes.Stfld, reg.GetField()); + } + } + } + + private void EmitStloc(ILEmitter context, int index, RegisterType registerType) + { + Register reg = new Register(index, registerType); + + if (registerType == RegisterType.Int && + RegisterSize == RegisterSize.Int32) + { + context.Generator.Emit(OpCodes.Conv_U8); + } + + context.Generator.EmitStloc(context.GetLocalIndex(reg)); + } + } +} \ No newline at end of file diff --git a/ChocolArm64/Translation/AIoType.cs b/ChocolArm64/Translation/IoType.cs similarity index 90% rename from ChocolArm64/Translation/AIoType.cs rename to ChocolArm64/Translation/IoType.cs index 94f8908142..290b159fc5 100644 --- a/ChocolArm64/Translation/AIoType.cs +++ b/ChocolArm64/Translation/IoType.cs @@ -3,7 +3,7 @@ using System; namespace ChocolArm64.Translation { [Flags] - enum AIoType + enum IoType { Arg, Fields, diff --git a/ChocolArm64/Translation/ALocalAlloc.cs b/ChocolArm64/Translation/LocalAlloc.cs similarity index 80% rename from ChocolArm64/Translation/ALocalAlloc.cs rename to ChocolArm64/Translation/LocalAlloc.cs index 942275e85f..8237bd5454 100644 --- a/ChocolArm64/Translation/ALocalAlloc.cs +++ b/ChocolArm64/Translation/LocalAlloc.cs @@ -2,27 +2,27 @@ using System.Collections.Generic; namespace ChocolArm64.Translation { - class ALocalAlloc + class LocalAlloc { private class PathIo { - private Dictionary _allInputs; - private Dictionary _cmnOutputs; + private Dictionary _allInputs; + private Dictionary _cmnOutputs; private long _allOutputs; public PathIo() { - _allInputs = new Dictionary(); - _cmnOutputs = new Dictionary(); + _allInputs = new Dictionary(); + _cmnOutputs = new Dictionary(); } - public PathIo(AilBlock root, long inputs, long outputs) : this() + public PathIo(ILBlock root, long inputs, long outputs) : this() { Set(root, inputs, outputs); } - public void Set(AilBlock root, long inputs, long outputs) + public void Set(ILBlock root, long inputs, long outputs) { if (!_allInputs.TryAdd(root, inputs)) { @@ -37,7 +37,7 @@ namespace ChocolArm64.Translation _allOutputs |= outputs; } - public long GetInputs(AilBlock root) + public long GetInputs(ILBlock root) { if (_allInputs.TryGetValue(root, out long inputs)) { @@ -53,13 +53,13 @@ namespace ChocolArm64.Translation } } - private Dictionary _intPaths; - private Dictionary _vecPaths; + private Dictionary _intPaths; + private Dictionary _vecPaths; private struct BlockIo { - public AilBlock Block; - public AilBlock Entry; + public ILBlock Block; + public ILBlock Entry; public long IntInputs; public long VecInputs; @@ -69,10 +69,10 @@ namespace ChocolArm64.Translation private const int MaxOptGraphLength = 40; - public ALocalAlloc(AilBlock[] graph, AilBlock root) + public LocalAlloc(ILBlock[] graph, ILBlock root) { - _intPaths = new Dictionary(); - _vecPaths = new Dictionary(); + _intPaths = new Dictionary(); + _vecPaths = new Dictionary(); if (graph.Length > 1 && graph.Length < MaxOptGraphLength) @@ -85,7 +85,7 @@ namespace ChocolArm64.Translation } } - private void InitializeOptimal(AilBlock[] graph, AilBlock root) + private void InitializeOptimal(ILBlock[] graph, ILBlock root) { //This will go through all possible paths on the graph, //and store all inputs/outputs for each block. A register @@ -144,7 +144,7 @@ namespace ChocolArm64.Translation vecPath.Set(current.Entry, current.VecInputs, current.VecOutputs); } - void EnqueueFromCurrent(AilBlock block, bool retTarget) + void EnqueueFromCurrent(ILBlock block, bool retTarget) { BlockIo blkIO = new BlockIo() { Block = block }; @@ -176,14 +176,14 @@ namespace ChocolArm64.Translation } } - private void InitializeFast(AilBlock[] graph) + private void InitializeFast(ILBlock[] graph) { //This is WAY faster than InitializeOptimal, but results in //uneeded loads and stores, so the resulting code will be slower. long intInputs = 0, intOutputs = 0; long vecInputs = 0, vecOutputs = 0; - foreach (AilBlock block in graph) + foreach (ILBlock block in graph) { intInputs |= block.IntInputs; intOutputs |= block.IntOutputs; @@ -201,17 +201,17 @@ namespace ChocolArm64.Translation vecInputs |= vecOutputs; } - foreach (AilBlock block in graph) + foreach (ILBlock block in graph) { _intPaths.Add(block, new PathIo(block, intInputs, intOutputs)); _vecPaths.Add(block, new PathIo(block, vecInputs, vecOutputs)); } } - public long GetIntInputs(AilBlock root) => GetInputsImpl(root, _intPaths.Values); - public long GetVecInputs(AilBlock root) => GetInputsImpl(root, _vecPaths.Values); + public long GetIntInputs(ILBlock root) => GetInputsImpl(root, _intPaths.Values); + public long GetVecInputs(ILBlock root) => GetInputsImpl(root, _vecPaths.Values); - private long GetInputsImpl(AilBlock root, IEnumerable values) + private long GetInputsImpl(ILBlock root, IEnumerable values) { long inputs = 0; @@ -223,7 +223,7 @@ namespace ChocolArm64.Translation return inputs; } - public long GetIntOutputs(AilBlock block) => _intPaths[block].GetOutputs(); - public long GetVecOutputs(AilBlock block) => _vecPaths[block].GetOutputs(); + public long GetIntOutputs(ILBlock block) => _intPaths[block].GetOutputs(); + public long GetVecOutputs(ILBlock block) => _vecPaths[block].GetOutputs(); } } \ No newline at end of file diff --git a/ChocolArm64/ATranslator.cs b/ChocolArm64/Translator.cs similarity index 70% rename from ChocolArm64/ATranslator.cs rename to ChocolArm64/Translator.cs index 3d17edd02b..a44c39c7e5 100644 --- a/ChocolArm64/ATranslator.cs +++ b/ChocolArm64/Translator.cs @@ -8,17 +8,17 @@ using System.Reflection.Emit; namespace ChocolArm64 { - public class ATranslator + public class Translator { - private ATranslatorCache _cache; + private TranslatorCache _cache; - public event EventHandler CpuTrace; + public event EventHandler CpuTrace; public bool EnableCpuTrace { get; set; } - public ATranslator() + public Translator() { - _cache = new ATranslatorCache(); + _cache = new TranslatorCache(); } internal void ExecuteSubroutine(AThread thread, long position) @@ -29,7 +29,7 @@ namespace ChocolArm64 AThreadState state = thread.ThreadState; AMemory memory = thread.Memory; - if (state.ExecutionMode == AExecutionMode.AArch32) + if (state.ExecutionMode == ExecutionMode.AArch32) { ExecuteSubroutineA32(state, memory); } @@ -56,10 +56,10 @@ namespace ChocolArm64 { if (EnableCpuTrace) { - CpuTrace?.Invoke(this, new ACpuTraceEventArgs(position)); + CpuTrace?.Invoke(this, new CpuTraceEventArgs(position)); } - if (!_cache.TryGetSubroutine(position, out ATranslatedSub sub)) + if (!_cache.TryGetSubroutine(position, out TranslatedSub sub)) { sub = TranslateTier0(state, memory, position); } @@ -79,15 +79,15 @@ namespace ChocolArm64 return _cache.HasSubroutine(position); } - private ATranslatedSub TranslateTier0(AThreadState state, AMemory memory, long position) + private TranslatedSub TranslateTier0(AThreadState state, AMemory memory, long position) { - ABlock block = ADecoder.DecodeBasicBlock(state, memory, position); + Block block = ADecoder.DecodeBasicBlock(state, memory, position); - ABlock[] graph = new ABlock[] { block }; + Block[] graph = new Block[] { block }; string subName = GetSubroutineName(position); - AilEmitterCtx context = new AilEmitterCtx(_cache, graph, block, subName); + ILEmitterCtx context = new ILEmitterCtx(_cache, graph, block, subName); do { @@ -95,9 +95,9 @@ namespace ChocolArm64 } while (context.AdvanceOpCode()); - ATranslatedSub subroutine = context.GetSubroutine(); + TranslatedSub subroutine = context.GetSubroutine(); - subroutine.SetType(ATranslatedSubType.SubTier0); + subroutine.SetType(TranslatedSubType.SubTier0); _cache.AddOrUpdate(position, subroutine, block.OpCodes.Count); @@ -108,11 +108,11 @@ namespace ChocolArm64 private void TranslateTier1(AThreadState state, AMemory memory, long position) { - (ABlock[] graph, ABlock root) = ADecoder.DecodeSubroutine(_cache, state, memory, position); + (Block[] graph, Block root) = ADecoder.DecodeSubroutine(_cache, state, memory, position); string subName = GetSubroutineName(position); - AilEmitterCtx context = new AilEmitterCtx(_cache, graph, root, subName); + ILEmitterCtx context = new ILEmitterCtx(_cache, graph, root, subName); if (context.CurrBlock.Position != position) { @@ -127,20 +127,20 @@ namespace ChocolArm64 //Mark all methods that calls this method for ReJiting, //since we can now call it directly which is faster. - if (_cache.TryGetSubroutine(position, out ATranslatedSub oldSub)) + if (_cache.TryGetSubroutine(position, out TranslatedSub oldSub)) { foreach (long callerPos in oldSub.GetCallerPositions()) { - if (_cache.TryGetSubroutine(position, out ATranslatedSub callerSub)) + if (_cache.TryGetSubroutine(position, out TranslatedSub callerSub)) { callerSub.MarkForReJit(); } } } - ATranslatedSub subroutine = context.GetSubroutine(); + TranslatedSub subroutine = context.GetSubroutine(); - subroutine.SetType(ATranslatedSubType.SubTier1); + subroutine.SetType(TranslatedSubType.SubTier1); _cache.AddOrUpdate(position, subroutine, GetGraphInstCount(graph)); } @@ -150,11 +150,11 @@ namespace ChocolArm64 return $"Sub{position:x16}"; } - private int GetGraphInstCount(ABlock[] graph) + private int GetGraphInstCount(Block[] graph) { int size = 0; - foreach (ABlock block in graph) + foreach (Block block in graph) { size += block.OpCodes.Count; } diff --git a/ChocolArm64/ATranslatorCache.cs b/ChocolArm64/TranslatorCache.cs similarity index 90% rename from ChocolArm64/ATranslatorCache.cs rename to ChocolArm64/TranslatorCache.cs index 3d3b53c9c8..7d65035777 100644 --- a/ChocolArm64/ATranslatorCache.cs +++ b/ChocolArm64/TranslatorCache.cs @@ -7,7 +7,7 @@ using System.Threading; namespace ChocolArm64 { - class ATranslatorCache + class TranslatorCache { //Maximum size of the cache, in bytes, measured in ARM code size. private const int MaxTotalSize = 4 * 1024 * 256; @@ -20,7 +20,7 @@ namespace ChocolArm64 private class CacheBucket { - public ATranslatedSub Subroutine { get; private set; } + public TranslatedSub Subroutine { get; private set; } public LinkedListNode Node { get; private set; } @@ -30,7 +30,7 @@ namespace ChocolArm64 public long Timestamp { get; private set; } - public CacheBucket(ATranslatedSub subroutine, LinkedListNode node, int size) + public CacheBucket(TranslatedSub subroutine, LinkedListNode node, int size) { Subroutine = subroutine; Size = size; @@ -52,14 +52,14 @@ namespace ChocolArm64 private int _totalSize; - public ATranslatorCache() + public TranslatorCache() { _cache = new ConcurrentDictionary(); _sortedCache = new LinkedList(); } - public void AddOrUpdate(long position, ATranslatedSub subroutine, int size) + public void AddOrUpdate(long position, TranslatedSub subroutine, int size) { ClearCacheIfNeeded(); @@ -88,7 +88,7 @@ namespace ChocolArm64 } [MethodImpl(MethodImplOptions.AggressiveInlining)] - public bool TryGetSubroutine(long position, out ATranslatedSub subroutine) + public bool TryGetSubroutine(long position, out TranslatedSub subroutine) { if (_cache.TryGetValue(position, out CacheBucket bucket)) { @@ -116,7 +116,7 @@ namespace ChocolArm64 return true; } - subroutine = default(ATranslatedSub); + subroutine = default(TranslatedSub); return false; } diff --git a/Ryujinx.Graphics/Memory/NvGpuVmm.cs b/Ryujinx.Graphics/Memory/NvGpuVmm.cs index 501f437f01..0082fb2751 100644 --- a/Ryujinx.Graphics/Memory/NvGpuVmm.cs +++ b/Ryujinx.Graphics/Memory/NvGpuVmm.cs @@ -4,7 +4,7 @@ using System; namespace Ryujinx.Graphics.Memory { - public class NvGpuVmm : IaMemory, IGalMemory + public class NvGpuVmm : IAMemory, IGalMemory { public const long AddrSize = 1L << 40; diff --git a/Ryujinx.Graphics/Texture/ImageUtils.cs b/Ryujinx.Graphics/Texture/ImageUtils.cs index 03402625b7..d2172c2ef8 100644 --- a/Ryujinx.Graphics/Texture/ImageUtils.cs +++ b/Ryujinx.Graphics/Texture/ImageUtils.cs @@ -216,7 +216,7 @@ namespace Ryujinx.Graphics.Texture throw new NotImplementedException(Format.ToString()); } - public static byte[] ReadTexture(IaMemory Memory, GalImage Image, long Position) + public static byte[] ReadTexture(IAMemory Memory, GalImage Image, long Position) { AMemory CpuMemory; diff --git a/Ryujinx.Graphics/Texture/TextureHelper.cs b/Ryujinx.Graphics/Texture/TextureHelper.cs index 1af5ef9503..9e966e6bd0 100644 --- a/Ryujinx.Graphics/Texture/TextureHelper.cs +++ b/Ryujinx.Graphics/Texture/TextureHelper.cs @@ -28,7 +28,7 @@ namespace Ryujinx.Graphics.Texture } public static (AMemory Memory, long Position) GetMemoryAndPosition( - IaMemory Memory, + IAMemory Memory, long Position) { if (Memory is NvGpuVmm Vmm) diff --git a/Ryujinx.HLE/HOS/Kernel/SvcHandler.cs b/Ryujinx.HLE/HOS/Kernel/SvcHandler.cs index d098aab0e5..4be0c6e8bf 100644 --- a/Ryujinx.HLE/HOS/Kernel/SvcHandler.cs +++ b/Ryujinx.HLE/HOS/Kernel/SvcHandler.cs @@ -101,7 +101,7 @@ namespace Ryujinx.HLE.HOS.Kernel Rng = new Random(); } - public void SvcCall(object sender, AInstExceptionEventArgs e) + public void SvcCall(object sender, InstExceptionEventArgs e) { AThreadState ThreadState = (AThreadState)sender; diff --git a/Ryujinx.HLE/HOS/Process.cs b/Ryujinx.HLE/HOS/Process.cs index 1d8bfeb8f5..faeedf537e 100644 --- a/Ryujinx.HLE/HOS/Process.cs +++ b/Ryujinx.HLE/HOS/Process.cs @@ -33,7 +33,7 @@ namespace Ryujinx.HLE.HOS public int ProcessId { get; private set; } - private ATranslator Translator; + private Translator Translator; public AMemory Memory { get; private set; } @@ -283,14 +283,14 @@ namespace Ryujinx.HLE.HOS Device.System.Scheduler.ContextSwitch(); } - private void BreakHandler(object sender, AInstExceptionEventArgs e) + private void BreakHandler(object sender, InstExceptionEventArgs e) { PrintStackTraceForCurrentThread(); throw new GuestBrokeExecutionException(); } - private void UndefinedHandler(object sender, AInstUndefinedEventArgs e) + private void UndefinedHandler(object sender, InstUndefinedEventArgs e) { PrintStackTraceForCurrentThread(); @@ -307,7 +307,7 @@ namespace Ryujinx.HLE.HOS Translator.EnableCpuTrace = false; } - private void CpuTraceHandler(object sender, ACpuTraceEventArgs e) + private void CpuTraceHandler(object sender, CpuTraceEventArgs e) { Executable Exe = GetExecutable(e.Position); @@ -328,11 +328,11 @@ namespace Ryujinx.HLE.HOS Logger.PrintDebug(LogClass.Cpu, ExeNameWithAddr + " " + SubName); } - private ATranslator GetTranslator() + private Translator GetTranslator() { if (Translator == null) { - Translator = new ATranslator(); + Translator = new Translator(); Translator.CpuTrace += CpuTraceHandler; } @@ -340,7 +340,7 @@ namespace Ryujinx.HLE.HOS return Translator; } - private void CpuInvalidAccessHandler(object sender, AInvalidAccessEventArgs e) + private void CpuInvalidAccessHandler(object sender, InvalidAccessEventArgs e) { PrintStackTraceForCurrentThread(); } diff --git a/Ryujinx.Tests/Cpu/CpuTest.cs b/Ryujinx.Tests/Cpu/CpuTest.cs index 4587189b90..9d1fc342d0 100644 --- a/Ryujinx.Tests/Cpu/CpuTest.cs +++ b/Ryujinx.Tests/Cpu/CpuTest.cs @@ -48,7 +48,7 @@ namespace Ryujinx.Tests.Cpu EntryPoint = Position; - ATranslator Translator = new ATranslator(); + Translator Translator = new Translator(); RamPointer = Marshal.AllocHGlobal(new IntPtr(Size)); Memory = new AMemory(RamPointer); Memory.Map(Position, 0, Size);