From df8fbd77f2a4c2e829cec7c8b94f7b8832ac41d0 Mon Sep 17 00:00:00 2001
From: unknown <mgnjulien@gmail.com>
Date: Fri, 23 Feb 2018 19:08:40 +0100
Subject: [PATCH] add 'ADC 32bit and Overflow' test

---
 Ryujinx.Tests/Cpu/CpuTestAlu.cs | 36 +++++++++++++++++++++++++++------
 1 file changed, 30 insertions(+), 6 deletions(-)

diff --git a/Ryujinx.Tests/Cpu/CpuTestAlu.cs b/Ryujinx.Tests/Cpu/CpuTestAlu.cs
index b73212ac58..877bd4e513 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAlu.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAlu.cs
@@ -5,13 +5,37 @@ namespace Ryujinx.Tests.Cpu
 {
     public class CpuTestAlu : CpuTest
     {
-        [TestCase(2u, 3u, 6ul, true)]
-        [TestCase(2u, 3u, 5ul, false)]
-        public void Adc(uint A, uint B, ulong Result, bool CarryTest)
+        public void Adc()
         {
-            // ADC X0, X1, X2
-            AThreadState ThreadState = SingleOpcode(0x9A020020, X1: A, X2: B, Carry: CarryTest);
-            Assert.AreEqual(Result, ThreadState.X0);
+            // ADC X0, X1, X2 64bit
+            AThreadState ThreadState = SingleOpcode(0x9A020020, X1: 2, X2: 3, Carry: true);
+            Assert.AreEqual(6, ThreadState.X0);
+
+            Reset();
+
+            ThreadState = SingleOpcode(0x9A020020, X1: 2, X2: 3, Carry: false);
+            Assert.AreEqual(5, ThreadState.X0);
+
+            Reset();
+
+            // ADC W0, W1, W2 32bit
+            ThreadState = SingleOpcode(0x1A020020, X1: 2, X2: 3, Carry: true);
+            Assert.AreEqual(6, ThreadState.X0);
+
+            Reset();
+
+            ThreadState = SingleOpcode(0x1A020020, X1: 2, X2: 3, Carry: false);
+            Assert.AreEqual(5, ThreadState.X0);
+
+            Reset();
+
+            // ADC Overflow
+            ThreadState = SingleOpcode(0x1A020020, X1: 0xFFFFFFFF, X2: 0x2, Carry: false);
+            Assert.AreEqual(0x1, ThreadState.X0);
+            Assert.AreEqual(true, ThreadState.Carry);
+
+            Reset();
+
         }
     
         [Test]