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Update CpuTestSimdReg.cs

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LDj3SNuD 2018-10-03 23:23:27 +02:00 • committed by GitHub
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1 changed files with 45 additions and 41 deletions
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Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
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@ -204,46 +204,50 @@ namespace Ryujinx.Tests.Cpu
#endregion #endregion
#region "ValueSource (Opcodes)" #region "ValueSource (Opcodes)"
private static uint[] _F_Add_Div_Mul_Sub_S_S_() private static uint[] _F_Add_Div_Mul_MulX_Sub_S_S_()
{ {
return new uint[] return new uint[]
{ {
0x1E222820u, // FADD S0, S1, S2 0x1E222820u, // FADD S0, S1, S2
0x1E221820u, // FDIV S0, S1, S2 0x1E221820u, // FDIV S0, S1, S2
0x1E220820u, // FMUL S0, S1, S2 0x1E220820u, // FMUL S0, S1, S2
0x5E22DC20u, // FMULX S0, S1, S2
0x1E223820u // FSUB S0, S1, S2 0x1E223820u // FSUB S0, S1, S2
}; };
} }
private static uint[] _F_Add_Div_Mul_Sub_S_D_() private static uint[] _F_Add_Div_Mul_MulX_Sub_S_D_()
{ {
return new uint[] return new uint[]
{ {
0x1E622820u, // FADD D0, D1, D2 0x1E622820u, // FADD D0, D1, D2
0x1E621820u, // FDIV D0, D1, D2 0x1E621820u, // FDIV D0, D1, D2
0x1E620820u, // FMUL D0, D1, D2 0x1E620820u, // FMUL D0, D1, D2
0x5E62DC20u, // FMULX D0, D1, D2
0x1E623820u // FSUB D0, D1, D2 0x1E623820u // FSUB D0, D1, D2
}; };
} }
private static uint[] _F_Add_Div_Mul_Sub_V_2S_4S_() private static uint[] _F_Add_Div_Mul_MulX_Sub_V_2S_4S_()
{ {
return new uint[] return new uint[]
{ {
0x0E20D400u, // FADD V0.2S, V0.2S, V0.2S 0x0E20D400u, // FADD V0.2S, V0.2S, V0.2S
0x2E20FC00u, // FDIV V0.2S, V0.2S, V0.2S 0x2E20FC00u, // FDIV V0.2S, V0.2S, V0.2S
0x2E20DC00u, // FMUL V0.2S, V0.2S, V0.2S 0x2E20DC00u, // FMUL V0.2S, V0.2S, V0.2S
0x0E20DC00u, // FMULX V0.2S, V0.2S, V0.2S
0x0EA0D400u // FSUB V0.2S, V0.2S, V0.2S 0x0EA0D400u // FSUB V0.2S, V0.2S, V0.2S
}; };
} }
private static uint[] _F_Add_Div_Mul_Sub_V_2D_() private static uint[] _F_Add_Div_Mul_MulX_Sub_V_2D_()
{ {
return new uint[] return new uint[]
{ {
0x4E60D400u, // FADD V0.2D, V0.2D, V0.2D 0x4E60D400u, // FADD V0.2D, V0.2D, V0.2D
0x6E60FC00u, // FDIV V0.2D, V0.2D, V0.2D 0x6E60FC00u, // FDIV V0.2D, V0.2D, V0.2D
0x6E60DC00u, // FMUL V0.2D, V0.2D, V0.2D 0x6E60DC00u, // FMUL V0.2D, V0.2D, V0.2D
0x4E60DC00u, // FMULX V0.2D, V0.2D, V0.2D
0x4EE0D400u // FSUB V0.2D, V0.2D, V0.2D 0x4EE0D400u // FSUB V0.2D, V0.2D, V0.2D
}; };
} }
@ -1134,7 +1138,7 @@ namespace Ryujinx.Tests.Cpu
} }
[Test, Pairwise] [Test, Pairwise]
public void F_Add_Div_Mul_Sub_S_S([ValueSource("_F_Add_Div_Mul_Sub_S_S_")] uint Opcodes, public void F_Add_Div_Mul_MulX_Sub_S_S([ValueSource("_F_Add_Div_Mul_MulX_Sub_S_S_")] uint Opcodes,
[ValueSource("_1S_F_")] ulong A, [ValueSource("_1S_F_")] ulong A,
[ValueSource("_1S_F_")] ulong B) [ValueSource("_1S_F_")] ulong B)
{ {
@ -1151,7 +1155,7 @@ namespace Ryujinx.Tests.Cpu
} }
[Test, Pairwise] [Test, Pairwise]
public void F_Add_Div_Mul_Sub_S_D([ValueSource("_F_Add_Div_Mul_Sub_S_D_")] uint Opcodes, public void F_Add_Div_Mul_MulX_Sub_S_D([ValueSource("_F_Add_Div_Mul_MulX_Sub_S_D_")] uint Opcodes,
[ValueSource("_1D_F_")] ulong A, [ValueSource("_1D_F_")] ulong A,
[ValueSource("_1D_F_")] ulong B) [ValueSource("_1D_F_")] ulong B)
{ {
@ -1168,7 +1172,7 @@ namespace Ryujinx.Tests.Cpu
} }
[Test, Pairwise] [Test, Pairwise]
public void F_Add_Div_Mul_Sub_V_2S_4S([ValueSource("_F_Add_Div_Mul_Sub_V_2S_4S_")] uint Opcodes, public void F_Add_Div_Mul_MulX_Sub_V_2S_4S([ValueSource("_F_Add_Div_Mul_MulX_Sub_V_2S_4S_")] uint Opcodes,
[Values(0u)] uint Rd, [Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn, [Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm, [Values(2u, 0u)] uint Rm,
@ -1192,7 +1196,7 @@ namespace Ryujinx.Tests.Cpu
} }
[Test, Pairwise] [Test, Pairwise]
public void F_Add_Div_Mul_Sub_V_2D([ValueSource("_F_Add_Div_Mul_Sub_V_2D_")] uint Opcodes, public void F_Add_Div_Mul_MulX_Sub_V_2D([ValueSource("_F_Add_Div_Mul_MulX_Sub_V_2D_")] uint Opcodes,
[Values(0u)] uint Rd, [Values(0u)] uint Rd,
[Values(1u, 0u)] uint Rn, [Values(1u, 0u)] uint Rn,
[Values(2u, 0u)] uint Rm, [Values(2u, 0u)] uint Rm,