Create CpuTestSimdIns.cs
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Ryujinx.Tests/Cpu/CpuTestSimdIns.cs
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74
Ryujinx.Tests/Cpu/CpuTestSimdIns.cs
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#define SimdIns
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using ChocolArm64.State;
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using NUnit.Framework;
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using System.Runtime.Intrinsics;
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namespace Ryujinx.Tests.Cpu
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{
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[Category("SimdIns")] // Tested: second half of 2018.
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public sealed class CpuTestSimdIns : CpuTest
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{
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#if SimdIns
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#region "ValueSource"
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private static uint[] _W_()
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{
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return new uint[] { 0x00000000u, 0x0000007Fu,
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0x00000080u, 0x000000FFu,
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0x00007FFFu, 0x00008000u,
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0x0000FFFFu, 0x7FFFFFFFu,
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0x80000000u, 0xFFFFFFFFu };
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}
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private static ulong[] _X_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
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0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
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}
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#endregion
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private const int RndCnt = 2;
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[Test, Pairwise, Description("DUP <Vd>.<T>, <R><n>")]
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public void Dup_Gp_W([Values(0u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[ValueSource("_W_")] [Random(RndCnt)] uint Wn,
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[Values(0, 1, 2)] int Size, // Q0: <8B, 4H, 2S>
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[Values(0b0u, 0b1u)] uint Q) // Q1: <16B, 8H, 4S>
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{
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uint Imm5 = (1U << Size) & 0x1F;
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uint Opcode = 0x0E000C00; // RESERVED
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= (Imm5 << 16);
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Opcode |= ((Q & 1) << 30);
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ulong Z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Wn, V0: V0);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("DUP <Vd>.<T>, <R><n>")]
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public void Dup_Gp_X([Values(0u)] uint Rd,
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[Values(1u, 31u)] uint Rn,
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[ValueSource("_X_")] [Random(RndCnt)] ulong Xn)
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{
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uint Opcode = 0x4E080C00; // DUP V0.2D, X0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong Z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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AThreadState ThreadState = SingleOpcode(Opcode, X1: Xn, V0: V0);
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CompareAgainstUnicorn();
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}
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#endif
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}
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}
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