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LDj3SNuD 2018-04-19 22:41:29 +02:00 • committed by GitHub
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#define Simd
using ChocolArm64.State;
using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
using Tester;
using Tester.Types;
[Category("Simd")]
public sealed class CpuTestSimd : CpuTest
{
#if Simd
[SetUp]
public void SetupTester()
{
AArch64.TakeReset(false);
}
[Test, Description("ABS <V><d>, <V><n>")]
public void Abs_S_D([Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong A)
{
uint Opcode = 0x5EE0B820; // ABS D0, D1
Bits Op = new Bits(Opcode);
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
AVec V1 = new AVec { X0 = A };
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
AArch64.V(1, new Bits(A));
SimdFp.Abs_S(Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
Assert.That(ThreadState.V0.X1, Is.Zero);
}
[Test, Description("ABS <Vd>.<T>, <Vn>.<T>")]
public void Abs_V_8B_4H_2S([Random(4)] ulong A,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint Opcode = 0x0E20B820; // ABS V0.8B, V1.8B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
AVec V1 = new AVec { X0 = A };
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
AArch64.V(1, new Bits(A));
SimdFp.Abs_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
Assert.That(ThreadState.V0.X1, Is.Zero);
}
[Test, Description("ABS <Vd>.<T>, <Vn>.<T>")]
public void Abs_V_16B_8H_4S_2D([Random(4)] ulong A0, [Random(4)] ulong A1,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
{
uint Opcode = 0x4E20B820; // ABS V0.16B, V1.16B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
AVec V1 = new AVec { X0 = A0, X1 = A1 };
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
AArch64.Vpart(1, 0, new Bits(A0));
AArch64.Vpart(1, 1, new Bits(A1));
SimdFp.Abs_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
}
[Test, Description("NEG <V><d>, <V><n>")]
public void Neg_S_D([Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong A)
{
uint Opcode = 0x7EE0B820; // NEG D0, D1
Bits Op = new Bits(Opcode);
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
AVec V1 = new AVec { X0 = A };
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
AArch64.V(1, new Bits(A));
SimdFp.Neg_S(Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
Assert.That(ThreadState.V0.X1, Is.Zero);
}
[Test, Description("NEG <Vd>.<T>, <Vn>.<T>")]
public void Neg_V_8B_4H_2S([Random(4)] ulong A,
[Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
{
uint Opcode = 0x2E20B820; // NEG V0.8B, V1.8B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
AVec V0 = new AVec { X1 = TestContext.CurrentContext.Random.NextULong() };
AVec V1 = new AVec { X0 = A };
AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
AArch64.V(1, new Bits(A));
SimdFp.Neg_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.V(64, 0).ToUInt64()));
Assert.That(ThreadState.V0.X1, Is.Zero);
}
[Test, Description("NEG <Vd>.<T>, <Vn>.<T>")]
public void Neg_V_16B_8H_4S_2D([Random(4)] ulong A0, [Random(4)] ulong A1,
[Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
{
uint Opcode = 0x6E20B820; // NEG V0.16B, V1.16B
Opcode |= ((size & 3) << 22);
Bits Op = new Bits(Opcode);
AVec V1 = new AVec { X0 = A0, X1 = A1 };
AThreadState ThreadState = SingleOpcode(Opcode, V1: V1);
AArch64.Vpart(1, 0, new Bits(A0));
AArch64.Vpart(1, 1, new Bits(A1));
SimdFp.Neg_V(Op[30], Op[23, 22], Op[9, 5], Op[4, 0]);
Assert.Multiple(() =>
{
Assert.That(ThreadState.V0.X0, Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
Assert.That(ThreadState.V0.X1, Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
});
}
#endif
}
}