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Fix some assignment alignments, remove some unused usings

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This commit is contained in:
gdkchan 2018-11-30 11:45:11 -03:00
commit f162e30958
14 changed files with 18 additions and 25 deletions
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5
ChocolArm64/Decoders/OpCodeAlu64.cs
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@ -1,5 +1,4 @@
using ChocolArm64.Instructions; using ChocolArm64.Instructions;
using ChocolArm64.State;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
@ -12,8 +11,8 @@ namespace ChocolArm64.Decoders
public OpCodeAlu64(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeAlu64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rd = (opCode >> 0) & 0x1f; Rd = (opCode >> 0) & 0x1f;
Rn = (opCode >> 5) & 0x1f; Rn = (opCode >> 5) & 0x1f;
DataOp = (DataOp)((opCode >> 24) & 0x3); DataOp = (DataOp)((opCode >> 24) & 0x3);
RegisterSize = (opCode >> 31) != 0 RegisterSize = (opCode >> 31) != 0

2
ChocolArm64/Decoders/OpCodeAluRs64.cs
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@ -22,7 +22,7 @@ namespace ChocolArm64.Decoders
Shift = shift; Shift = shift;
Rm = (opCode >> 16) & 0x1f; Rm = (opCode >> 16) & 0x1f;
ShiftType = (ShiftType)((opCode >> 22) & 0x3); ShiftType = (ShiftType)((opCode >> 22) & 0x3);
} }
} }

4
ChocolArm64/Decoders/OpCodeAluRx64.cs
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@ -11,9 +11,9 @@ namespace ChocolArm64.Decoders
public OpCodeAluRx64(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeAluRx64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Shift = (opCode >> 10) & 0x7; Shift = (opCode >> 10) & 0x7;
IntType = (IntType)((opCode >> 13) & 0x7); IntType = (IntType)((opCode >> 13) & 0x7);
Rm = (opCode >> 16) & 0x1f; Rm = (opCode >> 16) & 0x1f;
} }
} }
} }

1
ChocolArm64/Decoders/OpCodeBImmCmp64.cs
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@ -1,5 +1,4 @@
using ChocolArm64.Instructions; using ChocolArm64.Instructions;
using ChocolArm64.State;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {

4
ChocolArm64/Decoders/OpCodeCcmp64.cs
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@ -21,9 +21,9 @@ namespace ChocolArm64.Decoders
return; return;
} }
Nzcv = (opCode >> 0) & 0xf; Nzcv = (opCode >> 0) & 0xf;
Cond = (Cond)((opCode >> 12) & 0xf); Cond = (Cond)((opCode >> 12) & 0xf);
RmImm = (opCode >> 16) & 0x1f; RmImm = (opCode >> 16) & 0x1f;
Rd = CpuThreadState.ZrIndex; Rd = CpuThreadState.ZrIndex;
} }

2
ChocolArm64/Decoders/OpCodeCsel64.cs
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@ -10,7 +10,7 @@ namespace ChocolArm64.Decoders
public OpCodeCsel64(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeCsel64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Rm = (opCode >> 16) & 0x1f; Rm = (opCode >> 16) & 0x1f;
Cond = (Cond)((opCode >> 12) & 0xf); Cond = (Cond)((opCode >> 12) & 0xf);
} }
} }

2
ChocolArm64/Decoders/OpCodeMemImm64.cs
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@ -41,7 +41,7 @@ namespace ChocolArm64.Decoders
if (WBack || Unscaled) if (WBack || Unscaled)
{ {
//9-bits Signed Immediate. //9-bits Signed Immediate.
Imm = (opCode << 43) >> 55; Imm = (opCode << 11) >> 23;
} }
else else
{ {

6
ChocolArm64/Decoders/OpCodeMemReg64.cs
View file

@ -11,10 +11,10 @@ namespace ChocolArm64.Decoders
public OpCodeMemReg64(Inst inst, long position, int opCode) : base(inst, position, opCode) public OpCodeMemReg64(Inst inst, long position, int opCode) : base(inst, position, opCode)
{ {
Shift = ((opCode >> 12) & 0x1) != 0; Shift = ((opCode >> 12) & 0x1) != 0;
IntType = (IntType)((opCode >> 13) & 0x7); IntType = (IntType)((opCode >> 13) & 0x7);
Rm = (opCode >> 16) & 0x1f; Rm = (opCode >> 16) & 0x1f;
Extend64 = ((opCode >> 22) & 0x3) == 2; Extend64 = ((opCode >> 22) & 0x3) == 2;
} }
} }
} }

1
ChocolArm64/Decoders/OpCodeMov64.cs
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@ -1,5 +1,4 @@
using ChocolArm64.Instructions; using ChocolArm64.Instructions;
using ChocolArm64.State;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {

1
ChocolArm64/Decoders/OpCodeSimdCvt64.cs
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@ -1,5 +1,4 @@
using ChocolArm64.Instructions; using ChocolArm64.Instructions;
using ChocolArm64.State;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {

5
ChocolArm64/Decoders/OpCodeSimdImm64.cs
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@ -1,5 +1,4 @@
using ChocolArm64.Instructions; using ChocolArm64.Instructions;
using ChocolArm64.State;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {
@ -61,12 +60,12 @@ namespace ChocolArm64.Decoders
else if ((modeHigh & 0b110) == 0b100) else if ((modeHigh & 0b110) == 0b100)
{ {
//16-bits shifted Immediate. //16-bits shifted Immediate.
Size = 1; imm <<= (modeHigh & 1) << 3; Size = 1; imm <<= (modeHigh & 1) << 3;
} }
else if ((modeHigh & 0b100) == 0b000) else if ((modeHigh & 0b100) == 0b000)
{ {
//32-bits shifted Immediate. //32-bits shifted Immediate.
Size = 2; imm <<= modeHigh << 3; Size = 2; imm <<= modeHigh << 3;
} }
else if ((modeHigh & 0b111) == 0b110) else if ((modeHigh & 0b111) == 0b110)
{ {

1
ChocolArm64/Decoders/OpCodeSimdMemMs64.cs
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@ -1,5 +1,4 @@
using ChocolArm64.Instructions; using ChocolArm64.Instructions;
using ChocolArm64.State;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {

1
ChocolArm64/Decoders/OpCodeSimdMemSs64.cs
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@ -1,5 +1,4 @@
using ChocolArm64.Instructions; using ChocolArm64.Instructions;
using ChocolArm64.State;
namespace ChocolArm64.Decoders namespace ChocolArm64.Decoders
{ {

8
ChocolArm64/Decoders/ShiftType.cs
View file

@ -2,9 +2,9 @@ namespace ChocolArm64.Decoders
{ {
enum ShiftType enum ShiftType
{ {
Lsl, Lsl = 0,
Lsr, Lsr = 1,
Asr, Asr = 2,
Ror Ror = 3
} }
} }