From f4d5c0c1a1e2c7a4685ad47eae48b3838f25e594 Mon Sep 17 00:00:00 2001
From: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
Date: Fri, 20 Apr 2018 13:02:16 +0200
Subject: [PATCH] Update CpuTestSimd.cs

Provide a better supply of input values for the 20 Simd Tests.
---
 Ryujinx.Tests/Cpu/CpuTestSimd.cs | 40 +++++++++++++++++++++++++-------
 1 file changed, 32 insertions(+), 8 deletions(-)

diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
index 9d81beece1..2bea719885 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs
@@ -21,7 +21,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Description("ABS <V><d>, <V><n>")]
         public void Abs_S_D([Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
-                                    0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong A)
+                                    0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong A)
         {
             uint Opcode = 0x5EE0B820; // ABS D0, D1
             Bits Op = new Bits(Opcode);
@@ -38,7 +38,10 @@ namespace Ryujinx.Tests.Cpu
         }
 
         [Test, Description("ABS <Vd>.<T>, <Vn>.<T>")]
-        public void Abs_V_8B_4H_2S([Random(4)] ulong A,
+        public void Abs_V_8B_4H_2S([Values(0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+                                           0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
+                                           0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
+                                           0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong A,
                                    [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
         {
             uint Opcode = 0x0E20B820; // ABS V0.8B, V1.8B
@@ -56,8 +59,17 @@ namespace Ryujinx.Tests.Cpu
             Assert.That(ThreadState.V0.X1, Is.Zero);
         }
 
-        [Test, Description("ABS <Vd>.<T>, <Vn>.<T>")]
-        public void Abs_V_16B_8H_4S_2D([Random(4)] ulong A0, [Random(4)] ulong A1,
+        [Test, Pairwise, Description("ABS <Vd>.<T>, <Vn>.<T>")]
+        public void Abs_V_16B_8H_4S_2D([Values(0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+                                               0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
+                                               0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
+                                               0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
+                                               0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong A0,
+                                       [Values(0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+                                               0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
+                                               0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
+                                               0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
+                                               0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong A1,
                                        [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
         {
             uint Opcode = 0x4E20B820; // ABS V0.16B, V1.16B
@@ -80,7 +92,7 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Description("NEG <V><d>, <V><n>")]
         public void Neg_S_D([Values(0x0000000000000000ul, 0x7FFFFFFFFFFFFFFFul,
-                                    0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(4)] ulong A)
+                                    0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong A)
         {
             uint Opcode = 0x7EE0B820; // NEG D0, D1
             Bits Op = new Bits(Opcode);
@@ -97,7 +109,10 @@ namespace Ryujinx.Tests.Cpu
         }
 
         [Test, Description("NEG <Vd>.<T>, <Vn>.<T>")]
-        public void Neg_V_8B_4H_2S([Random(4)] ulong A,
+        public void Neg_V_8B_4H_2S([Values(0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+                                           0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
+                                           0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
+                                           0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong A,
                                    [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
         {
             uint Opcode = 0x2E20B820; // NEG V0.8B, V1.8B
@@ -115,8 +130,17 @@ namespace Ryujinx.Tests.Cpu
             Assert.That(ThreadState.V0.X1, Is.Zero);
         }
 
-        [Test, Description("NEG <Vd>.<T>, <Vn>.<T>")]
-        public void Neg_V_16B_8H_4S_2D([Random(4)] ulong A0, [Random(4)] ulong A1,
+        [Test, Pairwise, Description("NEG <Vd>.<T>, <Vn>.<T>")]
+        public void Neg_V_16B_8H_4S_2D([Values(0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+                                               0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
+                                               0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
+                                               0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
+                                               0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong A0,
+                                       [Values(0x0000000000000000ul, 0x7F7F7F7F7F7F7F7Ful,
+                                               0x8080808080808080ul, 0x7FFF7FFF7FFF7FFFul,
+                                               0x8000800080008000ul, 0x7FFFFFFF7FFFFFFFul,
+                                               0x8000000080000000ul, 0x7FFFFFFFFFFFFFFFul,
+                                               0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul)] [Random(1)] ulong A1,
                                        [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D>
         {
             uint Opcode = 0x6E20B820; // NEG V0.16B, V1.16B