Update CpuTestSimd.cs
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1 changed files with 78 additions and 114 deletions
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@ -14,7 +14,7 @@ namespace Ryujinx.Tests.Cpu
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{
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#if Simd
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#region "ValueSource"
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#region "ValueSource (Types)"
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private static ulong[] _1B1H1S1D_()
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{
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return new ulong[] { 0x0000000000000000ul, 0x000000000000007Ful,
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@ -204,12 +204,58 @@ namespace Ryujinx.Tests.Cpu
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}
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#endregion
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#region "ValueSource (Opcodes)"
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private static uint[] _F_Cvt_NZ_SU_S_S_()
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{
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return new uint[]
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{
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0x5E21A820u, // FCVTNS S0, S1
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0x7E21A820u, // FCVTNU S0, S1
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0x5EA1B820u, // FCVTZS S0, S1
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0x7EA1B820u // FCVTZU S0, S1
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};
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}
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private static uint[] _F_Cvt_NZ_SU_S_D_()
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{
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return new uint[]
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{
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0x5E61A820u, // FCVTNS D0, D1
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0x7E61A820u, // FCVTNU D0, D1
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0x5EE1B820u, // FCVTZS D0, D1
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0x7EE1B820u // FCVTZU D0, D1
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};
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}
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private static uint[] _F_Cvt_NZ_SU_V_2S_4S_()
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{
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return new uint[]
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{
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0x0E21A800u, // FCVTNS V0.2S, V0.2S
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0x2E21A800u, // FCVTNU V0.2S, V0.2S
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0x0EA1B800u, // FCVTZS V0.2S, V0.2S
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0x2EA1B800u // FCVTZU V0.2S, V0.2S
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};
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}
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private static uint[] _F_Cvt_NZ_SU_V_2D_()
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{
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return new uint[]
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{
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0x4E61A800u, // FCVTNS V0.2D, V0.2D
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0x6E61A800u, // FCVTNU V0.2D, V0.2D
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0x4EE1B800u, // FCVTZS V0.2D, V0.2D
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0x6EE1B800u // FCVTZU V0.2D, V0.2D
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};
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}
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#endregion
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private const int RndCnt = 2;
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private static readonly bool NoZeros = false;
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private static readonly bool NoInfs = false;
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private static readonly bool NoNaNs = false;
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private const int RndCnt = 2;
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[Test, Pairwise, Description("ABS <V><d>, <V><n>")]
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public void Abs_S_D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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@ -739,150 +785,68 @@ namespace Ryujinx.Tests.Cpu
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("FCVTNS <V><d>, <V><n>")]
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public void Fcvtns_S_S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1S_F_")] ulong Z,
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[ValueSource("_1S_F_")] ulong A)
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[Test, Pairwise]
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public void F_Cvt_NZ_SU_S_S([ValueSource("_F_Cvt_NZ_SU_S_S_")] uint Opcodes,
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[ValueSource("_1S_F_")] ulong A)
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{
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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uint Opcode = 0x5E21A800; // FCVTNS S0, S0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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ulong Z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
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}
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[Test, Pairwise, Description("FCVTNS <V><d>, <V><n>")]
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public void Fcvtns_S_D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1D_F_")] ulong Z,
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[ValueSource("_1D_F_")] ulong A)
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[Test, Pairwise]
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public void F_Cvt_NZ_SU_S_D([ValueSource("_F_Cvt_NZ_SU_S_D_")] uint Opcodes,
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[ValueSource("_1D_F_")] ulong A)
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{
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uint Opcode = 0x5E61A800; // FCVTNS D0, D0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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ulong Z = TestContext.CurrentContext.Random.NextULong();
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Vector128<float> V0 = MakeVectorE1(Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("FCVTNS <Vd>.<T>, <Vn>.<T>")]
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public void Fcvtns_V_2S_4S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_2S_F_")] ulong Z,
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[ValueSource("_2S_F_")] ulong A,
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[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
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[Test, Pairwise]
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public void F_Cvt_NZ_SU_V_2S_4S([ValueSource("_F_Cvt_NZ_SU_V_2S_4S_")] uint Opcodes,
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[Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_2S_F_")] ulong Z,
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[ValueSource("_2S_F_")] ulong A,
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[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
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{
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uint Opcode = 0x0E21A800; // FCVTNS V0.2S, V0.2S
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((Q & 1) << 30);
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Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcodes |= ((Q & 1) << 30);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("FCVTNS <Vd>.<T>, <Vn>.<T>")]
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public void Fcvtns_V_2D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1D_F_")] ulong Z,
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[ValueSource("_1D_F_")] ulong A)
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[Test, Pairwise]
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public void F_Cvt_NZ_SU_V_2D([ValueSource("_F_Cvt_NZ_SU_V_2D_")] uint Opcodes,
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[Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1D_F_")] ulong Z,
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[ValueSource("_1D_F_")] ulong A)
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{
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uint Opcode = 0x4E61A800; // FCVTNS V0.2D, V0.2D
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("FCVTNU <V><d>, <V><n>")]
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public void Fcvtnu_S_S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1S_F_")] ulong Z,
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[ValueSource("_1S_F_")] ulong A)
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{
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//const int FZFlagBit = 24; // Flush-to-zero mode control bit.
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uint Opcode = 0x7E21A800; // FCVTNU S0, S0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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//int Fpcr = 1 << FZFlagBit; // Flush-to-zero mode enabled.
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1/*, Fpcr: Fpcr*/);
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CompareAgainstUnicorn(/*FpsrMask: FPSR.IDC | FPSR.IXC | FPSR.IOC*/);
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}
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[Test, Pairwise, Description("FCVTNU <V><d>, <V><n>")]
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public void Fcvtnu_S_D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1D_F_")] ulong Z,
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[ValueSource("_1D_F_")] ulong A)
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{
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uint Opcode = 0x7E61A800; // FCVTNU D0, D0
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0(A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("FCVTNU <Vd>.<T>, <Vn>.<T>")]
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public void Fcvtnu_V_2S_4S([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_2S_F_")] ulong Z,
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[ValueSource("_2S_F_")] ulong A,
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[Values(0b0u, 0b1u)] uint Q) // <2S, 4S>
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{
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uint Opcode = 0x2E21A800; // FCVTNU V0.2S, V0.2S
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Opcode |= ((Q & 1) << 30);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A * Q);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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CompareAgainstUnicorn();
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}
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[Test, Pairwise, Description("FCVTNU <Vd>.<T>, <Vn>.<T>")]
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public void Fcvtnu_V_2D([Values(0u)] uint Rd,
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[Values(1u, 0u)] uint Rn,
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[ValueSource("_1D_F_")] ulong Z,
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[ValueSource("_1D_F_")] ulong A)
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{
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uint Opcode = 0x6E61A800; // FCVTNU V0.2D, V0.2D
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Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
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Vector128<float> V0 = MakeVectorE0E1(Z, Z);
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Vector128<float> V1 = MakeVectorE0E1(A, A);
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AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1);
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AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
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CompareAgainstUnicorn();
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}
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