Update Instructions.cs
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@ -1699,6 +1699,7 @@ namespace Ryujinx.Tests.Cpu.Tester
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Bits result = new Bits(datasize);
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Bits operand = V(datasize, n);
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BigInteger element;
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for (int e = 0; e <= elements - 1; e++)
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@ -1742,6 +1743,7 @@ namespace Ryujinx.Tests.Cpu.Tester
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Bits result = new Bits(datasize);
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Bits operand = V(datasize, n);
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BigInteger element;
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for (int e = 0; e <= elements - 1; e++)
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@ -1810,6 +1812,90 @@ namespace Ryujinx.Tests.Cpu.Tester
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V(d, Reduce(op, operand, esize));
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}
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// https://meriac.github.io/archex/A64_v83A_ISA/cls_advsimd.xml
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public static void Cls_V(bool Q, Bits size, Bits Rn, Bits Rd)
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{
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bool U = false;
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/* Decode */
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int d = (int)UInt(Rd);
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int n = (int)UInt(Rn);
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/* if size == '11' then ReservedValue(); */
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int esize = 8 << (int)UInt(size);
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int datasize = (Q ? 128 : 64);
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int elements = datasize / esize;
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CountOp countop = (U ? CountOp.CountOp_CLZ : CountOp.CountOp_CLS);
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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Bits result = new Bits(datasize);
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Bits operand = V(datasize, n);
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BigInteger count;
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for (int e = 0; e <= elements - 1; e++)
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{
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if (countop == CountOp.CountOp_CLS)
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{
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count = (BigInteger)CountLeadingSignBits(Elem(operand, e, esize));
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}
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else
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{
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count = (BigInteger)CountLeadingZeroBits(Elem(operand, e, esize));
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}
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Elem(result, e, esize, count.SubBigInteger(esize - 1, 0));
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}
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V(d, result);
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}
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// https://meriac.github.io/archex/A64_v83A_ISA/clz_advsimd.xml
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public static void Clz_V(bool Q, Bits size, Bits Rn, Bits Rd)
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{
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bool U = true;
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/* Decode */
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int d = (int)UInt(Rd);
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int n = (int)UInt(Rn);
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/* if size == '11' then ReservedValue(); */
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int esize = 8 << (int)UInt(size);
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int datasize = (Q ? 128 : 64);
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int elements = datasize / esize;
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CountOp countop = (U ? CountOp.CountOp_CLZ : CountOp.CountOp_CLS);
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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Bits result = new Bits(datasize);
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Bits operand = V(datasize, n);
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BigInteger count;
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for (int e = 0; e <= elements - 1; e++)
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{
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if (countop == CountOp.CountOp_CLS)
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{
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count = (BigInteger)CountLeadingSignBits(Elem(operand, e, esize));
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}
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else
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{
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count = (BigInteger)CountLeadingZeroBits(Elem(operand, e, esize));
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}
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Elem(result, e, esize, count.SubBigInteger(esize - 1, 0));
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}
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V(d, result);
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}
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// https://meriac.github.io/archex/A64_v83A_ISA/neg_advsimd.xml#NEG_asisdmisc_R
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public static void Neg_S(Bits size, Bits Rn, Bits Rd)
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{
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@ -1832,6 +1918,7 @@ namespace Ryujinx.Tests.Cpu.Tester
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Bits result = new Bits(datasize);
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Bits operand = V(datasize, n);
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BigInteger element;
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for (int e = 0; e <= elements - 1; e++)
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@ -1875,6 +1962,7 @@ namespace Ryujinx.Tests.Cpu.Tester
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Bits result = new Bits(datasize);
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Bits operand = V(datasize, n);
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BigInteger element;
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for (int e = 0; e <= elements - 1; e++)
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@ -2077,6 +2165,163 @@ namespace Ryujinx.Tests.Cpu.Tester
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V(d, result);
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}
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// https://meriac.github.io/archex/A64_v83A_ISA/and_advsimd.xml
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public static void And_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
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{
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/* Decode */
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int d = (int)UInt(Rd);
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int n = (int)UInt(Rn);
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int m = (int)UInt(Rm);
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int datasize = (Q ? 128 : 64);
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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Bits operand1 = V(datasize, n);
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Bits operand2 = V(datasize, m);
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Bits result = AND(operand1, operand2);
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V(d, result);
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}
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// https://meriac.github.io/archex/A64_v83A_ISA/bic_advsimd_reg.xml
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public static void Bic_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
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{
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/* Decode */
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int d = (int)UInt(Rd);
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int n = (int)UInt(Rn);
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int m = (int)UInt(Rm);
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int datasize = (Q ? 128 : 64);
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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Bits operand1 = V(datasize, n);
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Bits operand2 = V(datasize, m);
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operand2 = NOT(operand2);
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Bits result = AND(operand1, operand2);
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V(d, result);
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}
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// https://meriac.github.io/archex/A64_v83A_ISA/bif_advsimd.xml
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public static void Bif_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
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{
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/* Decode */
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int d = (int)UInt(Rd);
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int n = (int)UInt(Rn);
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int m = (int)UInt(Rm);
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int datasize = (Q ? 128 : 64);
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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Bits operand1;
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Bits operand3;
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Bits operand4 = V(datasize, n);
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operand1 = V(datasize, d);
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operand3 = NOT(V(datasize, m));
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V(d, EOR(operand1, AND(EOR(operand1, operand4), operand3)));
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}
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// https://meriac.github.io/archex/A64_v83A_ISA/bit_advsimd.xml
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public static void Bit_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
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{
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/* Decode */
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int d = (int)UInt(Rd);
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int n = (int)UInt(Rn);
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int m = (int)UInt(Rm);
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int datasize = (Q ? 128 : 64);
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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Bits operand1;
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Bits operand3;
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Bits operand4 = V(datasize, n);
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operand1 = V(datasize, d);
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operand3 = V(datasize, m);
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V(d, EOR(operand1, AND(EOR(operand1, operand4), operand3)));
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}
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// https://meriac.github.io/archex/A64_v83A_ISA/bsl_advsimd.xml
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public static void Bsl_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
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{
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/* Decode */
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int d = (int)UInt(Rd);
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int n = (int)UInt(Rn);
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int m = (int)UInt(Rm);
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int datasize = (Q ? 128 : 64);
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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Bits operand1;
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Bits operand3;
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Bits operand4 = V(datasize, n);
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operand1 = V(datasize, m);
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operand3 = V(datasize, d);
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V(d, EOR(operand1, AND(EOR(operand1, operand4), operand3)));
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}
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// https://meriac.github.io/archex/A64_v83A_ISA/orn_advsimd.xml
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public static void Orn_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
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{
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/* Decode */
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int d = (int)UInt(Rd);
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int n = (int)UInt(Rn);
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int m = (int)UInt(Rm);
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int datasize = (Q ? 128 : 64);
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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Bits operand1 = V(datasize, n);
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Bits operand2 = V(datasize, m);
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operand2 = NOT(operand2);
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Bits result = OR(operand1, operand2);
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V(d, result);
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}
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// https://meriac.github.io/archex/A64_v83A_ISA/orr_advsimd_reg.xml
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public static void Orr_V(bool Q, Bits Rm, Bits Rn, Bits Rd)
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{
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/* Decode */
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int d = (int)UInt(Rd);
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int n = (int)UInt(Rn);
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int m = (int)UInt(Rm);
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int datasize = (Q ? 128 : 64);
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/* Operation */
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/* CheckFPAdvSIMDEnabled64(); */
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Bits operand1 = V(datasize, n);
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Bits operand2 = V(datasize, m);
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Bits result = OR(operand1, operand2);
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V(d, result);
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}
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// https://meriac.github.io/archex/A64_v83A_ISA/raddhn_advsimd.xml
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public static void Raddhn_V(bool Q, Bits size, Bits Rm, Bits Rn, Bits Rd)
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{
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