Fix typo in ordered/exclusive stores.

This commit is contained in:
riperiperi 2020-01-11 15:59:49 +00:00
parent 6b947cd282
commit fc2d482616
3 changed files with 4 additions and 5 deletions

View file

@ -4,7 +4,7 @@ namespace ARMeilleure.Decoders
{
class OpCode32Mem : OpCode32, IOpCode32Mem
{
public int Rt { get; private set; }
public int Rt { get; protected set; }
public int Rn { get; private set; }
public int Immediate { get; protected set; }

View file

@ -7,7 +7,6 @@ namespace ARMeilleure.Decoders
class OpCode32MemStEx : OpCode32Mem, IOpCode32MemEx
{
public int Rd { get; internal set; }
public new int Rt { get; private set; }
public OpCode32MemStEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Rd = (opCode >> 12) & 0xf;

View file

@ -203,7 +203,7 @@ namespace ARMeilleure.Instructions
context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
Operand leResult = context.BitwiseOr(lo, context.ShiftLeft(hi, Const(32)));
Operand leS = EmitExStore(context, address, leResult, true, size);
Operand leS = EmitExStore(context, address, leResult, exclusive, size);
if (exclusive) SetIntA32(context, op.Rd, leS);
context.Branch(lblEnd);
@ -211,7 +211,7 @@ namespace ARMeilleure.Instructions
context.MarkLabel(lblBigEndian);
Operand beResult = context.BitwiseOr(hi, context.ShiftLeft(lo, Const(32)));
Operand beS = EmitExStore(context, address, beResult, true, size);
Operand beS = EmitExStore(context, address, beResult, exclusive, size);
if (exclusive) SetIntA32(context, op.Rd, beS);
context.MarkLabel(lblEnd);
@ -219,7 +219,7 @@ namespace ARMeilleure.Instructions
else
{
s = EmitExStore(context, address, context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt)), true, size);
s = EmitExStore(context, address, context.ZeroExtend32(OperandType.I64, GetIntA32(context, op.Rt)), exclusive, size);
// This is only needed for exclusive stores. The function returns 0
// when the store is successful, and 1 otherwise.
if (exclusive) SetIntA32(context, op.Rd, s);