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Update broken tests (#489)
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It seems like #484 broke the LLVM IR tests; this PR updates the .ll files to match what's now being produced.
This commit is contained in:
Violet 2025-09-02 16:14:54 -07:00 • committed by GitHub
commit 08f7e874e3
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GPG key ID: B5690EEEBB952194
132 changed files with 4283 additions and 4283 deletions
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44
ptx/src/test/ll/abs.ll
View file

@ -1,29 +1,29 @@
define amdgpu_kernel void @abs(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #0 {
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i32, align 4, addrspace(5)
%"36" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @abs(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i32, align 4, addrspace(5)
%"39" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"30"
br label %"33"
"30": ; preds = %1
%"37" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"37", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"38", ptr addrspace(5) %"34", align 8
%"40" = load i64, ptr addrspace(5) %"33", align 8
%"45" = inttoptr i64 %"40" to ptr
%"39" = load i32, ptr %"45", align 4
store i32 %"39", ptr addrspace(5) %"35", align 4
%"42" = load i32, ptr addrspace(5) %"35", align 4
%2 = call i32 @llvm.abs.i32(i32 %"42", i1 false)
store i32 %2, ptr addrspace(5) %"36", align 4
%"43" = load i64, ptr addrspace(5) %"34", align 8
%"44" = load i32, ptr addrspace(5) %"36", align 4
%"46" = inttoptr i64 %"43" to ptr
store i32 %"44", ptr %"46", align 4
"33": ; preds = %1
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"48" = inttoptr i64 %"43" to ptr
%"42" = load i32, ptr %"48", align 4
store i32 %"42", ptr addrspace(5) %"38", align 4
%"45" = load i32, ptr addrspace(5) %"38", align 4
%2 = call i32 @llvm.abs.i32(i32 %"45", i1 false)
store i32 %2, ptr addrspace(5) %"39", align 4
%"46" = load i64, ptr addrspace(5) %"37", align 8
%"47" = load i32, ptr addrspace(5) %"39", align 4
%"49" = inttoptr i64 %"46" to ptr
store i32 %"47", ptr %"49", align 4
ret void
}

26
ptx/src/test/ll/activemask.ll
View file

@ -1,22 +1,22 @@
declare hidden i32 @__zluda_ptx_impl_activemask() #0
define amdgpu_kernel void @activemask(ptr addrspace(4) byref(i64) %"29", ptr addrspace(4) byref(i64) %"30") #1 {
%"31" = alloca i64, align 8, addrspace(5)
%"32" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @activemask(ptr addrspace(4) byref(i64) %"32", ptr addrspace(4) byref(i64) %"33") #1 {
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"28"
br label %"31"
"28": ; preds = %1
%"33" = load i64, ptr addrspace(4) %"30", align 8
store i64 %"33", ptr addrspace(5) %"31", align 8
%"34" = call i32 @__zluda_ptx_impl_activemask()
store i32 %"34", ptr addrspace(5) %"32", align 4
%"35" = load i64, ptr addrspace(5) %"31", align 8
%"36" = load i32, ptr addrspace(5) %"32", align 4
%"37" = inttoptr i64 %"35" to ptr
store i32 %"36", ptr %"37", align 4
"31": ; preds = %1
%"36" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"36", ptr addrspace(5) %"34", align 8
%"37" = call i32 @__zluda_ptx_impl_activemask()
store i32 %"37", ptr addrspace(5) %"35", align 4
%"38" = load i64, ptr addrspace(5) %"34", align 8
%"39" = load i32, ptr addrspace(5) %"35", align 4
%"40" = inttoptr i64 %"38" to ptr
store i32 %"39", ptr %"40", align 4
ret void
}

44
ptx/src/test/ll/add.ll
View file

@ -1,30 +1,30 @@
define amdgpu_kernel void @add(ptr addrspace(4) byref(i64) %"32", ptr addrspace(4) byref(i64) %"33") #0 {
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @add(ptr addrspace(4) byref(i64) %"35", ptr addrspace(4) byref(i64) %"36") #0 {
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"31"
br label %"34"
"31": ; preds = %1
%"38" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"38", ptr addrspace(5) %"34", align 8
%"39" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"39", ptr addrspace(5) %"35", align 8
%"41" = load i64, ptr addrspace(5) %"34", align 8
%"46" = inttoptr i64 %"41" to ptr
%"40" = load i64, ptr %"46", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"42" = add i64 %"43", 1
store i64 %"42", ptr addrspace(5) %"37", align 8
%"44" = load i64, ptr addrspace(5) %"35", align 8
%"45" = load i64, ptr addrspace(5) %"37", align 8
%"47" = inttoptr i64 %"44" to ptr
store i64 %"45", ptr %"47", align 8
"34": ; preds = %1
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"44" = load i64, ptr addrspace(5) %"37", align 8
%"49" = inttoptr i64 %"44" to ptr
%"43" = load i64, ptr %"49", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"46" = load i64, ptr addrspace(5) %"39", align 8
%"45" = add i64 %"46", 1
store i64 %"45", ptr addrspace(5) %"40", align 8
%"47" = load i64, ptr addrspace(5) %"38", align 8
%"48" = load i64, ptr addrspace(5) %"40", align 8
%"50" = inttoptr i64 %"47" to ptr
store i64 %"48", ptr %"50", align 8
ret void
}
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="preserve-sign" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="preserve-sign" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }

44
ptx/src/test/ll/add_non_coherent.ll
View file

@ -1,30 +1,30 @@
define amdgpu_kernel void @add_non_coherent(ptr addrspace(4) byref(i64) %"32", ptr addrspace(4) byref(i64) %"33") #0 {
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @add_non_coherent(ptr addrspace(4) byref(i64) %"35", ptr addrspace(4) byref(i64) %"36") #0 {
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"31"
br label %"34"
"31": ; preds = %1
%"38" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"38", ptr addrspace(5) %"34", align 8
%"39" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"39", ptr addrspace(5) %"35", align 8
%"41" = load i64, ptr addrspace(5) %"34", align 8
%"46" = inttoptr i64 %"41" to ptr addrspace(1)
%"40" = load i64, ptr addrspace(1) %"46", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"42" = add i64 %"43", 1
store i64 %"42", ptr addrspace(5) %"37", align 8
%"44" = load i64, ptr addrspace(5) %"35", align 8
%"45" = load i64, ptr addrspace(5) %"37", align 8
%"47" = inttoptr i64 %"44" to ptr addrspace(1)
store i64 %"45", ptr addrspace(1) %"47", align 8
"34": ; preds = %1
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"44" = load i64, ptr addrspace(5) %"37", align 8
%"49" = inttoptr i64 %"44" to ptr addrspace(1)
%"43" = load i64, ptr addrspace(1) %"49", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"46" = load i64, ptr addrspace(5) %"39", align 8
%"45" = add i64 %"46", 1
store i64 %"45", ptr addrspace(5) %"40", align 8
%"47" = load i64, ptr addrspace(5) %"38", align 8
%"48" = load i64, ptr addrspace(5) %"40", align 8
%"50" = inttoptr i64 %"47" to ptr addrspace(1)
store i64 %"48", ptr addrspace(1) %"50", align 8
ret void
}
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="preserve-sign" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="preserve-sign" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }

76
ptx/src/test/ll/add_s32_sat.ll
View file

@ -1,46 +1,46 @@
define amdgpu_kernel void @add_s32_sat(ptr addrspace(4) byref(i64) %"37", ptr addrspace(4) byref(i64) %"38") #0 {
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i32, align 4, addrspace(5)
%"42" = alloca i32, align 4, addrspace(5)
%"43" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @add_s32_sat(ptr addrspace(4) byref(i64) %"40", ptr addrspace(4) byref(i64) %"41") #0 {
%"42" = alloca i64, align 8, addrspace(5)
%"43" = alloca i64, align 8, addrspace(5)
%"44" = alloca i32, align 4, addrspace(5)
%"45" = alloca i32, align 4, addrspace(5)
%"46" = alloca i32, align 4, addrspace(5)
%"47" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"36"
br label %"39"
"36": ; preds = %1
%"45" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"45", ptr addrspace(5) %"39", align 8
%"46" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"46", ptr addrspace(5) %"40", align 8
%"48" = load i64, ptr addrspace(5) %"39", align 8
%"61" = inttoptr i64 %"48" to ptr
%"47" = load i32, ptr %"61", align 4
store i32 %"47", ptr addrspace(5) %"41", align 4
%"49" = load i64, ptr addrspace(5) %"39", align 8
%"62" = inttoptr i64 %"49" to ptr
%"33" = getelementptr inbounds i8, ptr %"62", i64 4
%"50" = load i32, ptr %"33", align 4
store i32 %"50", ptr addrspace(5) %"42", align 4
%"52" = load i32, ptr addrspace(5) %"41", align 4
%"53" = load i32, ptr addrspace(5) %"42", align 4
%"51" = call i32 @llvm.sadd.sat.i32(i32 %"52", i32 %"53")
store i32 %"51", ptr addrspace(5) %"43", align 4
%"55" = load i32, ptr addrspace(5) %"41", align 4
%"56" = load i32, ptr addrspace(5) %"42", align 4
%"54" = add i32 %"55", %"56"
store i32 %"54", ptr addrspace(5) %"44", align 4
%"57" = load i64, ptr addrspace(5) %"40", align 8
%"58" = load i32, ptr addrspace(5) %"43", align 4
%"63" = inttoptr i64 %"57" to ptr
store i32 %"58", ptr %"63", align 4
%"59" = load i64, ptr addrspace(5) %"40", align 8
%"64" = inttoptr i64 %"59" to ptr
%"35" = getelementptr inbounds i8, ptr %"64", i64 4
%"60" = load i32, ptr addrspace(5) %"44", align 4
store i32 %"60", ptr %"35", align 4
"39": ; preds = %1
%"48" = load i64, ptr addrspace(4) %"40", align 8
store i64 %"48", ptr addrspace(5) %"42", align 8
%"49" = load i64, ptr addrspace(4) %"41", align 8
store i64 %"49", ptr addrspace(5) %"43", align 8
%"51" = load i64, ptr addrspace(5) %"42", align 8
%"64" = inttoptr i64 %"51" to ptr
%"50" = load i32, ptr %"64", align 4
store i32 %"50", ptr addrspace(5) %"44", align 4
%"52" = load i64, ptr addrspace(5) %"42", align 8
%"65" = inttoptr i64 %"52" to ptr
%"36" = getelementptr inbounds i8, ptr %"65", i64 4
%"53" = load i32, ptr %"36", align 4
store i32 %"53", ptr addrspace(5) %"45", align 4
%"55" = load i32, ptr addrspace(5) %"44", align 4
%"56" = load i32, ptr addrspace(5) %"45", align 4
%"54" = call i32 @llvm.sadd.sat.i32(i32 %"55", i32 %"56")
store i32 %"54", ptr addrspace(5) %"46", align 4
%"58" = load i32, ptr addrspace(5) %"44", align 4
%"59" = load i32, ptr addrspace(5) %"45", align 4
%"57" = add i32 %"58", %"59"
store i32 %"57", ptr addrspace(5) %"47", align 4
%"60" = load i64, ptr addrspace(5) %"43", align 8
%"61" = load i32, ptr addrspace(5) %"46", align 4
%"66" = inttoptr i64 %"60" to ptr
store i32 %"61", ptr %"66", align 4
%"62" = load i64, ptr addrspace(5) %"43", align 8
%"67" = inttoptr i64 %"62" to ptr
%"38" = getelementptr inbounds i8, ptr %"67", i64 4
%"63" = load i32, ptr addrspace(5) %"47", align 4
store i32 %"63", ptr %"38", align 4
ret void
}

44
ptx/src/test/ll/add_tuning.ll
View file

@ -1,30 +1,30 @@
define amdgpu_kernel void @add_tuning(ptr addrspace(4) byref(i64) %"32", ptr addrspace(4) byref(i64) %"33") #0 {
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @add_tuning(ptr addrspace(4) byref(i64) %"35", ptr addrspace(4) byref(i64) %"36") #0 {
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"31"
br label %"34"
"31": ; preds = %1
%"38" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"38", ptr addrspace(5) %"34", align 8
%"39" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"39", ptr addrspace(5) %"35", align 8
%"41" = load i64, ptr addrspace(5) %"34", align 8
%"46" = inttoptr i64 %"41" to ptr
%"40" = load i64, ptr %"46", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"42" = add i64 %"43", 1
store i64 %"42", ptr addrspace(5) %"37", align 8
%"44" = load i64, ptr addrspace(5) %"35", align 8
%"45" = load i64, ptr addrspace(5) %"37", align 8
%"47" = inttoptr i64 %"44" to ptr
store i64 %"45", ptr %"47", align 8
"34": ; preds = %1
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"44" = load i64, ptr addrspace(5) %"37", align 8
%"49" = inttoptr i64 %"44" to ptr
%"43" = load i64, ptr %"49", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"46" = load i64, ptr addrspace(5) %"39", align 8
%"45" = add i64 %"46", 1
store i64 %"45", ptr addrspace(5) %"40", align 8
%"47" = load i64, ptr addrspace(5) %"38", align 8
%"48" = load i64, ptr addrspace(5) %"40", align 8
%"50" = inttoptr i64 %"47" to ptr
store i64 %"48", ptr %"50", align 8
ret void
}
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="preserve-sign" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="preserve-sign" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }

56
ptx/src/test/ll/and.ll
View file

@ -1,35 +1,35 @@
define amdgpu_kernel void @and(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i32, align 4, addrspace(5)
%"38" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @and(ptr addrspace(4) byref(i64) %"36", ptr addrspace(4) byref(i64) %"37") #0 {
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i32, align 4, addrspace(5)
%"41" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"32"
br label %"35"
"32": ; preds = %1
%"39" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"39", ptr addrspace(5) %"35", align 8
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"42" = load i64, ptr addrspace(5) %"35", align 8
%"50" = inttoptr i64 %"42" to ptr
%"41" = load i32, ptr %"50", align 4
store i32 %"41", ptr addrspace(5) %"37", align 4
%"43" = load i64, ptr addrspace(5) %"35", align 8
%"51" = inttoptr i64 %"43" to ptr
%"31" = getelementptr inbounds i8, ptr %"51", i64 4
%"44" = load i32, ptr %"31", align 4
store i32 %"44", ptr addrspace(5) %"38", align 4
%"46" = load i32, ptr addrspace(5) %"37", align 4
%"47" = load i32, ptr addrspace(5) %"38", align 4
%"52" = and i32 %"46", %"47"
store i32 %"52", ptr addrspace(5) %"37", align 4
%"48" = load i64, ptr addrspace(5) %"36", align 8
%"49" = load i32, ptr addrspace(5) %"37", align 4
%"55" = inttoptr i64 %"48" to ptr
store i32 %"49", ptr %"55", align 4
"35": ; preds = %1
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"43" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"45" = load i64, ptr addrspace(5) %"38", align 8
%"53" = inttoptr i64 %"45" to ptr
%"44" = load i32, ptr %"53", align 4
store i32 %"44", ptr addrspace(5) %"40", align 4
%"46" = load i64, ptr addrspace(5) %"38", align 8
%"54" = inttoptr i64 %"46" to ptr
%"34" = getelementptr inbounds i8, ptr %"54", i64 4
%"47" = load i32, ptr %"34", align 4
store i32 %"47", ptr addrspace(5) %"41", align 4
%"49" = load i32, ptr addrspace(5) %"40", align 4
%"50" = load i32, ptr addrspace(5) %"41", align 4
%"55" = and i32 %"49", %"50"
store i32 %"55", ptr addrspace(5) %"40", align 4
%"51" = load i64, ptr addrspace(5) %"39", align 8
%"52" = load i32, ptr addrspace(5) %"40", align 4
%"58" = inttoptr i64 %"51" to ptr
store i32 %"52", ptr %"58", align 4
ret void
}

86
ptx/src/test/ll/assertfail.ll
View file

@ -1,62 +1,62 @@
declare hidden void @__zluda_ptx_impl___assertfail(i64, i64, i32, i64, i64) #0
define amdgpu_kernel void @assertfail(ptr addrspace(4) byref(i64) %"86", ptr addrspace(4) byref(i64) %"87") #1 {
%"88" = alloca i64, align 8, addrspace(5)
%"89" = alloca i64, align 8, addrspace(5)
%"90" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @assertfail(ptr addrspace(4) byref(i64) %"89", ptr addrspace(4) byref(i64) %"90") #1 {
%"91" = alloca i64, align 8, addrspace(5)
%"94" = alloca i32, align 4, addrspace(5)
%"96" = alloca i64, align 8, addrspace(5)
%"92" = alloca i64, align 8, addrspace(5)
%"93" = alloca i64, align 8, addrspace(5)
%"94" = alloca i64, align 8, addrspace(5)
%"97" = alloca i32, align 4, addrspace(5)
%"99" = alloca i64, align 8, addrspace(5)
%"102" = alloca i32, align 4, addrspace(5)
%"105" = alloca i64, align 8, addrspace(5)
%"102" = alloca i64, align 8, addrspace(5)
%"105" = alloca i32, align 4, addrspace(5)
%"108" = alloca i64, align 8, addrspace(5)
%"111" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"84"
br label %"87"
"84": ; preds = %1
%"92" = load i64, ptr addrspace(4) %"86", align 8
store i64 %"92", ptr addrspace(5) %"88", align 8
%"93" = load i64, ptr addrspace(4) %"87", align 8
store i64 %"93", ptr addrspace(5) %"89", align 8
store i32 0, ptr addrspace(5) %"94", align 4
%"97" = getelementptr inbounds i8, ptr addrspace(5) %"96", i64 0
%"98" = load i64, ptr addrspace(5) %"88", align 8
store i64 %"98", ptr addrspace(5) %"97", align 8
"87": ; preds = %1
%"95" = load i64, ptr addrspace(4) %"89", align 8
store i64 %"95", ptr addrspace(5) %"91", align 8
%"96" = load i64, ptr addrspace(4) %"90", align 8
store i64 %"96", ptr addrspace(5) %"92", align 8
store i32 0, ptr addrspace(5) %"97", align 4
%"100" = getelementptr inbounds i8, ptr addrspace(5) %"99", i64 0
%"101" = load i64, ptr addrspace(5) %"88", align 8
%"101" = load i64, ptr addrspace(5) %"91", align 8
store i64 %"101", ptr addrspace(5) %"100", align 8
%"103" = getelementptr inbounds i8, ptr addrspace(5) %"102", i64 0
%"104" = load i32, ptr addrspace(5) %"94", align 4
store i32 %"104", ptr addrspace(5) %"103", align 4
%"104" = load i64, ptr addrspace(5) %"91", align 8
store i64 %"104", ptr addrspace(5) %"103", align 8
%"106" = getelementptr inbounds i8, ptr addrspace(5) %"105", i64 0
%"107" = load i64, ptr addrspace(5) %"88", align 8
store i64 %"107", ptr addrspace(5) %"106", align 8
%"107" = load i32, ptr addrspace(5) %"97", align 4
store i32 %"107", ptr addrspace(5) %"106", align 4
%"109" = getelementptr inbounds i8, ptr addrspace(5) %"108", i64 0
%"110" = load i64, ptr addrspace(5) %"88", align 8
%"110" = load i64, ptr addrspace(5) %"91", align 8
store i64 %"110", ptr addrspace(5) %"109", align 8
%"74" = load i64, ptr addrspace(5) %"96", align 8
%"75" = load i64, ptr addrspace(5) %"99", align 8
%"76" = load i32, ptr addrspace(5) %"102", align 4
%"77" = load i64, ptr addrspace(5) %"105", align 8
%"78" = load i64, ptr addrspace(5) %"108", align 8
call void @__zluda_ptx_impl___assertfail(i64 %"74", i64 %"75", i32 %"76", i64 %"77", i64 %"78")
br label %"85"
%"112" = getelementptr inbounds i8, ptr addrspace(5) %"111", i64 0
%"113" = load i64, ptr addrspace(5) %"91", align 8
store i64 %"113", ptr addrspace(5) %"112", align 8
%"77" = load i64, ptr addrspace(5) %"99", align 8
%"78" = load i64, ptr addrspace(5) %"102", align 8
%"79" = load i32, ptr addrspace(5) %"105", align 4
%"80" = load i64, ptr addrspace(5) %"108", align 8
%"81" = load i64, ptr addrspace(5) %"111", align 8
call void @__zluda_ptx_impl___assertfail(i64 %"77", i64 %"78", i32 %"79", i64 %"80", i64 %"81")
br label %"88"
"85": ; preds = %"84"
%"112" = load i64, ptr addrspace(5) %"88", align 8
%"122" = inttoptr i64 %"112" to ptr
%"111" = load i64, ptr %"122", align 8
store i64 %"111", ptr addrspace(5) %"90", align 8
%"114" = load i64, ptr addrspace(5) %"90", align 8
%"113" = add i64 %"114", 1
store i64 %"113", ptr addrspace(5) %"91", align 8
%"115" = load i64, ptr addrspace(5) %"89", align 8
%"116" = load i64, ptr addrspace(5) %"91", align 8
%"123" = inttoptr i64 %"115" to ptr
store i64 %"116", ptr %"123", align 8
"88": ; preds = %"87"
%"115" = load i64, ptr addrspace(5) %"91", align 8
%"125" = inttoptr i64 %"115" to ptr
%"114" = load i64, ptr %"125", align 8
store i64 %"114", ptr addrspace(5) %"93", align 8
%"117" = load i64, ptr addrspace(5) %"93", align 8
%"116" = add i64 %"117", 1
store i64 %"116", ptr addrspace(5) %"94", align 8
%"118" = load i64, ptr addrspace(5) %"92", align 8
%"119" = load i64, ptr addrspace(5) %"94", align 8
%"126" = inttoptr i64 %"118" to ptr
store i64 %"119", ptr %"126", align 8
ret void
}

72
ptx/src/test/ll/atom_add.ll
View file

@ -1,45 +1,45 @@
@shared_mem = external addrspace(3) global [1024 x i8], align 4
define amdgpu_kernel void @atom_add(ptr addrspace(4) byref(i64) %"36", ptr addrspace(4) byref(i64) %"37") #0 {
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i32, align 4, addrspace(5)
%"41" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @atom_add(ptr addrspace(4) byref(i64) %"39", ptr addrspace(4) byref(i64) %"40") #0 {
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i64, align 8, addrspace(5)
%"43" = alloca i32, align 4, addrspace(5)
%"44" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"35"
br label %"38"
"35": ; preds = %1
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"43" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"45" = load i64, ptr addrspace(5) %"38", align 8
%"56" = inttoptr i64 %"45" to ptr
%"44" = load i32, ptr %"56", align 4
store i32 %"44", ptr addrspace(5) %"40", align 4
%"46" = load i64, ptr addrspace(5) %"38", align 8
%"57" = inttoptr i64 %"46" to ptr
%"32" = getelementptr inbounds i8, ptr %"57", i64 4
%"47" = load i32, ptr %"32", align 4
store i32 %"47", ptr addrspace(5) %"41", align 4
%"48" = load i32, ptr addrspace(5) %"40", align 4
store i32 %"48", ptr addrspace(3) @shared_mem, align 4
%"50" = load i32, ptr addrspace(5) %"41", align 4
%2 = atomicrmw add ptr addrspace(3) @shared_mem, i32 %"50" syncscope("agent-one-as") monotonic, align 4
store i32 %2, ptr addrspace(5) %"40", align 4
%"51" = load i32, ptr addrspace(3) @shared_mem, align 4
store i32 %"51", ptr addrspace(5) %"41", align 4
%"52" = load i64, ptr addrspace(5) %"39", align 8
%"53" = load i32, ptr addrspace(5) %"40", align 4
%"61" = inttoptr i64 %"52" to ptr
store i32 %"53", ptr %"61", align 4
%"54" = load i64, ptr addrspace(5) %"39", align 8
%"62" = inttoptr i64 %"54" to ptr
%"34" = getelementptr inbounds i8, ptr %"62", i64 4
%"55" = load i32, ptr addrspace(5) %"41", align 4
store i32 %"55", ptr %"34", align 4
"38": ; preds = %1
%"45" = load i64, ptr addrspace(4) %"39", align 8
store i64 %"45", ptr addrspace(5) %"41", align 8
%"46" = load i64, ptr addrspace(4) %"40", align 8
store i64 %"46", ptr addrspace(5) %"42", align 8
%"48" = load i64, ptr addrspace(5) %"41", align 8
%"59" = inttoptr i64 %"48" to ptr
%"47" = load i32, ptr %"59", align 4
store i32 %"47", ptr addrspace(5) %"43", align 4
%"49" = load i64, ptr addrspace(5) %"41", align 8
%"60" = inttoptr i64 %"49" to ptr
%"35" = getelementptr inbounds i8, ptr %"60", i64 4
%"50" = load i32, ptr %"35", align 4
store i32 %"50", ptr addrspace(5) %"44", align 4
%"51" = load i32, ptr addrspace(5) %"43", align 4
store i32 %"51", ptr addrspace(3) @shared_mem, align 4
%"53" = load i32, ptr addrspace(5) %"44", align 4
%2 = atomicrmw add ptr addrspace(3) @shared_mem, i32 %"53" syncscope("agent-one-as") monotonic, align 4
store i32 %2, ptr addrspace(5) %"43", align 4
%"54" = load i32, ptr addrspace(3) @shared_mem, align 4
store i32 %"54", ptr addrspace(5) %"44", align 4
%"55" = load i64, ptr addrspace(5) %"42", align 8
%"56" = load i32, ptr addrspace(5) %"43", align 4
%"64" = inttoptr i64 %"55" to ptr
store i32 %"56", ptr %"64", align 4
%"57" = load i64, ptr addrspace(5) %"42", align 8
%"65" = inttoptr i64 %"57" to ptr
%"37" = getelementptr inbounds i8, ptr %"65", i64 4
%"58" = load i32, ptr addrspace(5) %"44", align 4
store i32 %"58", ptr %"37", align 4
ret void
}

72
ptx/src/test/ll/atom_add_float.ll
View file

@ -1,45 +1,45 @@
@shared_mem = external addrspace(3) global [1024 x i8], align 4
define amdgpu_kernel void @atom_add_float(ptr addrspace(4) byref(i64) %"36", ptr addrspace(4) byref(i64) %"37") #0 {
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca float, align 4, addrspace(5)
%"41" = alloca float, align 4, addrspace(5)
define amdgpu_kernel void @atom_add_float(ptr addrspace(4) byref(i64) %"39", ptr addrspace(4) byref(i64) %"40") #0 {
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i64, align 8, addrspace(5)
%"43" = alloca float, align 4, addrspace(5)
%"44" = alloca float, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"35"
br label %"38"
"35": ; preds = %1
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"43" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"45" = load i64, ptr addrspace(5) %"38", align 8
%"56" = inttoptr i64 %"45" to ptr
%"44" = load float, ptr %"56", align 4
store float %"44", ptr addrspace(5) %"40", align 4
%"46" = load i64, ptr addrspace(5) %"38", align 8
%"57" = inttoptr i64 %"46" to ptr
%"32" = getelementptr inbounds i8, ptr %"57", i64 4
%"47" = load float, ptr %"32", align 4
store float %"47", ptr addrspace(5) %"41", align 4
%"48" = load float, ptr addrspace(5) %"40", align 4
store float %"48", ptr addrspace(3) @shared_mem, align 4
%"50" = load float, ptr addrspace(5) %"41", align 4
%2 = atomicrmw fadd ptr addrspace(3) @shared_mem, float %"50" syncscope("agent-one-as") monotonic, align 4
store float %2, ptr addrspace(5) %"40", align 4
%"51" = load float, ptr addrspace(3) @shared_mem, align 4
store float %"51", ptr addrspace(5) %"41", align 4
%"52" = load i64, ptr addrspace(5) %"39", align 8
%"53" = load float, ptr addrspace(5) %"40", align 4
%"61" = inttoptr i64 %"52" to ptr
store float %"53", ptr %"61", align 4
%"54" = load i64, ptr addrspace(5) %"39", align 8
%"62" = inttoptr i64 %"54" to ptr
%"34" = getelementptr inbounds i8, ptr %"62", i64 4
%"55" = load float, ptr addrspace(5) %"41", align 4
store float %"55", ptr %"34", align 4
"38": ; preds = %1
%"45" = load i64, ptr addrspace(4) %"39", align 8
store i64 %"45", ptr addrspace(5) %"41", align 8
%"46" = load i64, ptr addrspace(4) %"40", align 8
store i64 %"46", ptr addrspace(5) %"42", align 8
%"48" = load i64, ptr addrspace(5) %"41", align 8
%"59" = inttoptr i64 %"48" to ptr
%"47" = load float, ptr %"59", align 4
store float %"47", ptr addrspace(5) %"43", align 4
%"49" = load i64, ptr addrspace(5) %"41", align 8
%"60" = inttoptr i64 %"49" to ptr
%"35" = getelementptr inbounds i8, ptr %"60", i64 4
%"50" = load float, ptr %"35", align 4
store float %"50", ptr addrspace(5) %"44", align 4
%"51" = load float, ptr addrspace(5) %"43", align 4
store float %"51", ptr addrspace(3) @shared_mem, align 4
%"53" = load float, ptr addrspace(5) %"44", align 4
%2 = atomicrmw fadd ptr addrspace(3) @shared_mem, float %"53" syncscope("agent-one-as") monotonic, align 4
store float %2, ptr addrspace(5) %"43", align 4
%"54" = load float, ptr addrspace(3) @shared_mem, align 4
store float %"54", ptr addrspace(5) %"44", align 4
%"55" = load i64, ptr addrspace(5) %"42", align 8
%"56" = load float, ptr addrspace(5) %"43", align 4
%"64" = inttoptr i64 %"55" to ptr
store float %"56", ptr %"64", align 4
%"57" = load i64, ptr addrspace(5) %"42", align 8
%"65" = inttoptr i64 %"57" to ptr
%"37" = getelementptr inbounds i8, ptr %"65", i64 4
%"58" = load float, ptr addrspace(5) %"44", align 4
store float %"58", ptr %"37", align 4
ret void
}

68
ptx/src/test/ll/atom_cas.ll
View file

@ -1,43 +1,43 @@
define amdgpu_kernel void @atom_cas(ptr addrspace(4) byref(i64) %"38", ptr addrspace(4) byref(i64) %"39") #0 {
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i32, align 4, addrspace(5)
%"43" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @atom_cas(ptr addrspace(4) byref(i64) %"41", ptr addrspace(4) byref(i64) %"42") #0 {
%"43" = alloca i64, align 8, addrspace(5)
%"44" = alloca i64, align 8, addrspace(5)
%"45" = alloca i32, align 4, addrspace(5)
%"46" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"37"
br label %"40"
"37": ; preds = %1
%"44" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"44", ptr addrspace(5) %"40", align 8
%"45" = load i64, ptr addrspace(4) %"39", align 8
store i64 %"45", ptr addrspace(5) %"41", align 8
%"47" = load i64, ptr addrspace(5) %"40", align 8
%"57" = inttoptr i64 %"47" to ptr
%"46" = load i32, ptr %"57", align 4
store i32 %"46", ptr addrspace(5) %"42", align 4
%"48" = load i64, ptr addrspace(5) %"40", align 8
%"58" = inttoptr i64 %"48" to ptr
%"31" = getelementptr inbounds i8, ptr %"58", i64 4
%"50" = load i32, ptr addrspace(5) %"42", align 4
%2 = cmpxchg ptr %"31", i32 %"50", i32 100 syncscope("agent-one-as") monotonic monotonic, align 4
%"59" = extractvalue { i32, i1 } %2, 0
store i32 %"59", ptr addrspace(5) %"42", align 4
%"51" = load i64, ptr addrspace(5) %"40", align 8
"40": ; preds = %1
%"47" = load i64, ptr addrspace(4) %"41", align 8
store i64 %"47", ptr addrspace(5) %"43", align 8
%"48" = load i64, ptr addrspace(4) %"42", align 8
store i64 %"48", ptr addrspace(5) %"44", align 8
%"50" = load i64, ptr addrspace(5) %"43", align 8
%"60" = inttoptr i64 %"50" to ptr
%"49" = load i32, ptr %"60", align 4
store i32 %"49", ptr addrspace(5) %"45", align 4
%"51" = load i64, ptr addrspace(5) %"43", align 8
%"61" = inttoptr i64 %"51" to ptr
%"34" = getelementptr inbounds i8, ptr %"61", i64 4
%"52" = load i32, ptr %"34", align 4
store i32 %"52", ptr addrspace(5) %"43", align 4
%"53" = load i64, ptr addrspace(5) %"41", align 8
%"54" = load i32, ptr addrspace(5) %"42", align 4
%"62" = inttoptr i64 %"53" to ptr
store i32 %"54", ptr %"62", align 4
%"55" = load i64, ptr addrspace(5) %"41", align 8
%"63" = inttoptr i64 %"55" to ptr
%"36" = getelementptr inbounds i8, ptr %"63", i64 4
%"56" = load i32, ptr addrspace(5) %"43", align 4
store i32 %"56", ptr %"36", align 4
%"53" = load i32, ptr addrspace(5) %"45", align 4
%2 = cmpxchg ptr %"34", i32 %"53", i32 100 syncscope("agent-one-as") monotonic monotonic, align 4
%"62" = extractvalue { i32, i1 } %2, 0
store i32 %"62", ptr addrspace(5) %"45", align 4
%"54" = load i64, ptr addrspace(5) %"43", align 8
%"64" = inttoptr i64 %"54" to ptr
%"37" = getelementptr inbounds i8, ptr %"64", i64 4
%"55" = load i32, ptr %"37", align 4
store i32 %"55", ptr addrspace(5) %"46", align 4
%"56" = load i64, ptr addrspace(5) %"44", align 8
%"57" = load i32, ptr addrspace(5) %"45", align 4
%"65" = inttoptr i64 %"56" to ptr
store i32 %"57", ptr %"65", align 4
%"58" = load i64, ptr addrspace(5) %"44", align 8
%"66" = inttoptr i64 %"58" to ptr
%"39" = getelementptr inbounds i8, ptr %"66", i64 4
%"59" = load i32, ptr addrspace(5) %"46", align 4
store i32 %"59", ptr %"39", align 4
ret void
}

76
ptx/src/test/ll/atom_inc.ll
View file

@ -1,45 +1,45 @@
define amdgpu_kernel void @atom_inc(ptr addrspace(4) byref(i64) %"38", ptr addrspace(4) byref(i64) %"39") #0 {
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i32, align 4, addrspace(5)
%"43" = alloca i32, align 4, addrspace(5)
%"44" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @atom_inc(ptr addrspace(4) byref(i64) %"41", ptr addrspace(4) byref(i64) %"42") #0 {
%"43" = alloca i64, align 8, addrspace(5)
%"44" = alloca i64, align 8, addrspace(5)
%"45" = alloca i32, align 4, addrspace(5)
%"46" = alloca i32, align 4, addrspace(5)
%"47" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"37"
br label %"40"
"37": ; preds = %1
%"45" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"45", ptr addrspace(5) %"40", align 8
%"46" = load i64, ptr addrspace(4) %"39", align 8
store i64 %"46", ptr addrspace(5) %"41", align 8
%"48" = load i64, ptr addrspace(5) %"40", align 8
%"59" = inttoptr i64 %"48" to ptr
%2 = atomicrmw uinc_wrap ptr %"59", i32 101 syncscope("agent-one-as") monotonic, align 4
store i32 %2, ptr addrspace(5) %"42", align 4
%"50" = load i64, ptr addrspace(5) %"40", align 8
%"60" = inttoptr i64 %"50" to ptr addrspace(1)
%3 = atomicrmw uinc_wrap ptr addrspace(1) %"60", i32 101 syncscope("agent-one-as") monotonic, align 4
store i32 %3, ptr addrspace(5) %"43", align 4
%"52" = load i64, ptr addrspace(5) %"40", align 8
%"61" = inttoptr i64 %"52" to ptr
%"51" = load i32, ptr %"61", align 4
store i32 %"51", ptr addrspace(5) %"44", align 4
%"53" = load i64, ptr addrspace(5) %"41", align 8
%"54" = load i32, ptr addrspace(5) %"42", align 4
%"62" = inttoptr i64 %"53" to ptr
store i32 %"54", ptr %"62", align 4
%"55" = load i64, ptr addrspace(5) %"41", align 8
%"63" = inttoptr i64 %"55" to ptr
%"34" = getelementptr inbounds i8, ptr %"63", i64 4
%"56" = load i32, ptr addrspace(5) %"43", align 4
store i32 %"56", ptr %"34", align 4
%"57" = load i64, ptr addrspace(5) %"41", align 8
%"64" = inttoptr i64 %"57" to ptr
%"36" = getelementptr inbounds i8, ptr %"64", i64 8
%"58" = load i32, ptr addrspace(5) %"44", align 4
store i32 %"58", ptr %"36", align 4
"40": ; preds = %1
%"48" = load i64, ptr addrspace(4) %"41", align 8
store i64 %"48", ptr addrspace(5) %"43", align 8
%"49" = load i64, ptr addrspace(4) %"42", align 8
store i64 %"49", ptr addrspace(5) %"44", align 8
%"51" = load i64, ptr addrspace(5) %"43", align 8
%"62" = inttoptr i64 %"51" to ptr
%2 = atomicrmw uinc_wrap ptr %"62", i32 101 syncscope("agent-one-as") monotonic, align 4
store i32 %2, ptr addrspace(5) %"45", align 4
%"53" = load i64, ptr addrspace(5) %"43", align 8
%"63" = inttoptr i64 %"53" to ptr addrspace(1)
%3 = atomicrmw uinc_wrap ptr addrspace(1) %"63", i32 101 syncscope("agent-one-as") monotonic, align 4
store i32 %3, ptr addrspace(5) %"46", align 4
%"55" = load i64, ptr addrspace(5) %"43", align 8
%"64" = inttoptr i64 %"55" to ptr
%"54" = load i32, ptr %"64", align 4
store i32 %"54", ptr addrspace(5) %"47", align 4
%"56" = load i64, ptr addrspace(5) %"44", align 8
%"57" = load i32, ptr addrspace(5) %"45", align 4
%"65" = inttoptr i64 %"56" to ptr
store i32 %"57", ptr %"65", align 4
%"58" = load i64, ptr addrspace(5) %"44", align 8
%"66" = inttoptr i64 %"58" to ptr
%"37" = getelementptr inbounds i8, ptr %"66", i64 4
%"59" = load i32, ptr addrspace(5) %"46", align 4
store i32 %"59", ptr %"37", align 4
%"60" = load i64, ptr addrspace(5) %"44", align 8
%"67" = inttoptr i64 %"60" to ptr
%"39" = getelementptr inbounds i8, ptr %"67", i64 8
%"61" = load i32, ptr addrspace(5) %"47", align 4
store i32 %"61", ptr %"39", align 4
ret void
}

46
ptx/src/test/ll/b64tof64.ll
View file

@ -1,30 +1,30 @@
define amdgpu_kernel void @b64tof64(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #0 {
%"33" = alloca double, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @b64tof64(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca double, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"30"
br label %"33"
"30": ; preds = %1
%"37" = load double, ptr addrspace(4) %"31", align 8
store double %"37", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"38", ptr addrspace(5) %"35", align 8
%"40" = load double, ptr addrspace(5) %"33", align 8
%"46" = bitcast double %"40" to i64
store i64 %"46", ptr addrspace(5) %"34", align 8
%"42" = load i64, ptr addrspace(5) %"34", align 8
%"47" = inttoptr i64 %"42" to ptr
%"41" = load i64, ptr %"47", align 8
store i64 %"41", ptr addrspace(5) %"36", align 8
%"43" = load i64, ptr addrspace(5) %"35", align 8
%"44" = load i64, ptr addrspace(5) %"36", align 8
%"48" = inttoptr i64 %"43" to ptr
store i64 %"44", ptr %"48", align 8
"33": ; preds = %1
%"40" = load double, ptr addrspace(4) %"34", align 8
store double %"40", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"38", align 8
%"43" = load double, ptr addrspace(5) %"36", align 8
%"49" = bitcast double %"43" to i64
store i64 %"49", ptr addrspace(5) %"37", align 8
%"45" = load i64, ptr addrspace(5) %"37", align 8
%"50" = inttoptr i64 %"45" to ptr
%"44" = load i64, ptr %"50", align 8
store i64 %"44", ptr addrspace(5) %"39", align 8
%"46" = load i64, ptr addrspace(5) %"38", align 8
%"47" = load i64, ptr addrspace(5) %"39", align 8
%"51" = inttoptr i64 %"46" to ptr
store i64 %"47", ptr %"51", align 8
ret void
}
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="preserve-sign" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="preserve-sign" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }

188
ptx/src/test/ll/bar_red_and_pred.ll
View file

@ -4,116 +4,116 @@ declare hidden i1 @__zluda_ptx_impl_bar_red_or_pred(i32, i1, i1) #0
declare hidden i32 @__zluda_ptx_impl_sreg_tid(i8) #0
define amdgpu_kernel void @bar_red_and_pred(ptr addrspace(4) byref(i64) %"73", ptr addrspace(4) byref(i64) %"74") #1 {
%"75" = alloca i64, align 8, addrspace(5)
%"76" = alloca i64, align 8, addrspace(5)
%"77" = alloca i32, align 4, addrspace(5)
%"78" = alloca i32, align 4, addrspace(5)
%"79" = alloca i1, align 1, addrspace(5)
%"80" = alloca i1, align 1, addrspace(5)
define amdgpu_kernel void @bar_red_and_pred(ptr addrspace(4) byref(i64) %"76", ptr addrspace(4) byref(i64) %"77") #1 {
%"78" = alloca i64, align 8, addrspace(5)
%"79" = alloca i64, align 8, addrspace(5)
%"80" = alloca i32, align 4, addrspace(5)
%"81" = alloca i32, align 4, addrspace(5)
%"82" = alloca i1, align 1, addrspace(5)
%"83" = alloca i1, align 1, addrspace(5)
%"84" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"70"
br label %"73"
"70": ; preds = %1
%"82" = load i64, ptr addrspace(4) %"74", align 8
store i64 %"82", ptr addrspace(5) %"75", align 8
%"44" = call i32 @__zluda_ptx_impl_sreg_tid(i8 0)
br label %"71"
"73": ; preds = %1
%"85" = load i64, ptr addrspace(4) %"77", align 8
store i64 %"85", ptr addrspace(5) %"78", align 8
%"47" = call i32 @__zluda_ptx_impl_sreg_tid(i8 0)
br label %"74"
"71": ; preds = %"70"
store i32 %"44", ptr addrspace(5) %"77", align 4
%"85" = load i32, ptr addrspace(5) %"77", align 4
%"84" = urem i32 %"85", 2
store i32 %"84", ptr addrspace(5) %"78", align 4
%"87" = load i32, ptr addrspace(5) %"78", align 4
%2 = icmp eq i32 %"87", 0
store i1 %2, ptr addrspace(5) %"80", align 1
store i32 0, ptr addrspace(5) %"81", align 4
%"90" = load i1, ptr addrspace(5) %"80", align 1
%"89" = call i1 @__zluda_ptx_impl_bar_red_and_pred(i32 1, i1 %"90", i1 false)
store i1 %"89", ptr addrspace(5) %"79", align 1
%"91" = load i1, ptr addrspace(5) %"79", align 1
br i1 %"91", label %"17", label %"18"
"74": ; preds = %"73"
store i32 %"47", ptr addrspace(5) %"80", align 4
%"88" = load i32, ptr addrspace(5) %"80", align 4
%"87" = urem i32 %"88", 2
store i32 %"87", ptr addrspace(5) %"81", align 4
%"90" = load i32, ptr addrspace(5) %"81", align 4
%2 = icmp eq i32 %"90", 0
store i1 %2, ptr addrspace(5) %"83", align 1
store i32 0, ptr addrspace(5) %"84", align 4
%"93" = load i1, ptr addrspace(5) %"83", align 1
%"92" = call i1 @__zluda_ptx_impl_bar_red_and_pred(i32 1, i1 %"93", i1 false)
store i1 %"92", ptr addrspace(5) %"82", align 1
%"94" = load i1, ptr addrspace(5) %"82", align 1
br i1 %"94", label %"18", label %"19"
"17": ; preds = %"71"
%"93" = load i32, ptr addrspace(5) %"81", align 4
%"92" = add i32 %"93", 1
store i32 %"92", ptr addrspace(5) %"81", align 4
br label %"18"
"18": ; preds = %"74"
%"96" = load i32, ptr addrspace(5) %"84", align 4
%"95" = add i32 %"96", 1
store i32 %"95", ptr addrspace(5) %"84", align 4
br label %"19"
"18": ; preds = %"17", %"71"
%"95" = load i1, ptr addrspace(5) %"80", align 1
%"94" = call i1 @__zluda_ptx_impl_bar_red_or_pred(i32 1, i1 %"95", i1 false)
store i1 %"94", ptr addrspace(5) %"79", align 1
%"96" = load i1, ptr addrspace(5) %"79", align 1
br i1 %"96", label %"19", label %"20"
"19": ; preds = %"18", %"74"
%"98" = load i1, ptr addrspace(5) %"83", align 1
%"97" = call i1 @__zluda_ptx_impl_bar_red_or_pred(i32 1, i1 %"98", i1 false)
store i1 %"97", ptr addrspace(5) %"82", align 1
%"99" = load i1, ptr addrspace(5) %"82", align 1
br i1 %"99", label %"20", label %"21"
"19": ; preds = %"18"
%"98" = load i32, ptr addrspace(5) %"81", align 4
%"97" = add i32 %"98", 1
store i32 %"97", ptr addrspace(5) %"81", align 4
br label %"20"
"20": ; preds = %"19"
%"101" = load i32, ptr addrspace(5) %"84", align 4
%"100" = add i32 %"101", 1
store i32 %"100", ptr addrspace(5) %"84", align 4
br label %"21"
"20": ; preds = %"19", %"18"
store i1 true, ptr addrspace(5) %"80", align 1
%"101" = load i1, ptr addrspace(5) %"80", align 1
%"100" = call i1 @__zluda_ptx_impl_bar_red_and_pred(i32 1, i1 %"101", i1 false)
store i1 %"100", ptr addrspace(5) %"79", align 1
%"102" = load i1, ptr addrspace(5) %"79", align 1
br i1 %"102", label %"21", label %"22"
"21": ; preds = %"20", %"19"
store i1 true, ptr addrspace(5) %"83", align 1
%"104" = load i1, ptr addrspace(5) %"83", align 1
%"103" = call i1 @__zluda_ptx_impl_bar_red_and_pred(i32 1, i1 %"104", i1 false)
store i1 %"103", ptr addrspace(5) %"82", align 1
%"105" = load i1, ptr addrspace(5) %"82", align 1
br i1 %"105", label %"22", label %"23"
"21": ; preds = %"20"
%"104" = load i32, ptr addrspace(5) %"81", align 4
%"103" = add i32 %"104", 1
store i32 %"103", ptr addrspace(5) %"81", align 4
br label %"22"
"22": ; preds = %"21"
%"107" = load i32, ptr addrspace(5) %"84", align 4
%"106" = add i32 %"107", 1
store i32 %"106", ptr addrspace(5) %"84", align 4
br label %"23"
"22": ; preds = %"21", %"20"
store i1 false, ptr addrspace(5) %"80", align 1
%"107" = load i1, ptr addrspace(5) %"80", align 1
%"106" = call i1 @__zluda_ptx_impl_bar_red_or_pred(i32 1, i1 %"107", i1 false)
store i1 %"106", ptr addrspace(5) %"79", align 1
%"108" = load i1, ptr addrspace(5) %"79", align 1
br i1 %"108", label %"23", label %"24"
"23": ; preds = %"22", %"21"
store i1 false, ptr addrspace(5) %"83", align 1
%"110" = load i1, ptr addrspace(5) %"83", align 1
%"109" = call i1 @__zluda_ptx_impl_bar_red_or_pred(i32 1, i1 %"110", i1 false)
store i1 %"109", ptr addrspace(5) %"82", align 1
%"111" = load i1, ptr addrspace(5) %"82", align 1
br i1 %"111", label %"24", label %"25"
"23": ; preds = %"22"
%"110" = load i32, ptr addrspace(5) %"81", align 4
%"109" = add i32 %"110", 1
store i32 %"109", ptr addrspace(5) %"81", align 4
br label %"24"
"24": ; preds = %"23"
%"113" = load i32, ptr addrspace(5) %"84", align 4
%"112" = add i32 %"113", 1
store i32 %"112", ptr addrspace(5) %"84", align 4
br label %"25"
"24": ; preds = %"23", %"22"
store i1 true, ptr addrspace(5) %"80", align 1
%"113" = load i1, ptr addrspace(5) %"80", align 1
%"112" = call i1 @__zluda_ptx_impl_bar_red_and_pred(i32 1, i1 %"113", i1 true)
store i1 %"112", ptr addrspace(5) %"79", align 1
%"114" = load i1, ptr addrspace(5) %"79", align 1
br i1 %"114", label %"25", label %"26"
"25": ; preds = %"24", %"23"
store i1 true, ptr addrspace(5) %"83", align 1
%"116" = load i1, ptr addrspace(5) %"83", align 1
%"115" = call i1 @__zluda_ptx_impl_bar_red_and_pred(i32 1, i1 %"116", i1 true)
store i1 %"115", ptr addrspace(5) %"82", align 1
%"117" = load i1, ptr addrspace(5) %"82", align 1
br i1 %"117", label %"26", label %"27"
"25": ; preds = %"24"
%"116" = load i32, ptr addrspace(5) %"81", align 4
%"115" = add i32 %"116", 1
store i32 %"115", ptr addrspace(5) %"81", align 4
br label %"26"
"26": ; preds = %"25"
%"119" = load i32, ptr addrspace(5) %"84", align 4
%"118" = add i32 %"119", 1
store i32 %"118", ptr addrspace(5) %"84", align 4
br label %"27"
"26": ; preds = %"25", %"24"
%"118" = load i32, ptr addrspace(5) %"77", align 4
%"117" = zext i32 %"118" to i64
store i64 %"117", ptr addrspace(5) %"76", align 8
%"120" = load i64, ptr addrspace(5) %"76", align 8
%"119" = mul i64 %"120", 4
store i64 %"119", ptr addrspace(5) %"76", align 8
%"122" = load i64, ptr addrspace(5) %"75", align 8
%"123" = load i64, ptr addrspace(5) %"76", align 8
%"121" = add i64 %"122", %"123"
store i64 %"121", ptr addrspace(5) %"75", align 8
%"124" = load i64, ptr addrspace(5) %"75", align 8
%"125" = load i32, ptr addrspace(5) %"81", align 4
%"126" = inttoptr i64 %"124" to ptr
store i32 %"125", ptr %"126", align 4
"27": ; preds = %"26", %"25"
%"121" = load i32, ptr addrspace(5) %"80", align 4
%"120" = zext i32 %"121" to i64
store i64 %"120", ptr addrspace(5) %"79", align 8
%"123" = load i64, ptr addrspace(5) %"79", align 8
%"122" = mul i64 %"123", 4
store i64 %"122", ptr addrspace(5) %"79", align 8
%"125" = load i64, ptr addrspace(5) %"78", align 8
%"126" = load i64, ptr addrspace(5) %"79", align 8
%"124" = add i64 %"125", %"126"
store i64 %"124", ptr addrspace(5) %"78", align 8
%"127" = load i64, ptr addrspace(5) %"78", align 8
%"128" = load i32, ptr addrspace(5) %"84", align 4
%"129" = inttoptr i64 %"127" to ptr
store i32 %"128", ptr %"129", align 4
ret void
}

70
ptx/src/test/ll/bfe.ll
View file

@ -1,44 +1,44 @@
declare hidden i32 @__zluda_ptx_impl_bfe_u32(i32, i32, i32) #0
define amdgpu_kernel void @bfe(ptr addrspace(4) byref(i64) %"36", ptr addrspace(4) byref(i64) %"37") #1 {
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i32, align 4, addrspace(5)
%"41" = alloca i32, align 4, addrspace(5)
%"42" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @bfe(ptr addrspace(4) byref(i64) %"39", ptr addrspace(4) byref(i64) %"40") #1 {
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i64, align 8, addrspace(5)
%"43" = alloca i32, align 4, addrspace(5)
%"44" = alloca i32, align 4, addrspace(5)
%"45" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"35"
br label %"38"
"35": ; preds = %1
%"43" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"43", ptr addrspace(5) %"38", align 8
%"44" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"44", ptr addrspace(5) %"39", align 8
%"46" = load i64, ptr addrspace(5) %"38", align 8
%"57" = inttoptr i64 %"46" to ptr
%"45" = load i32, ptr %"57", align 4
store i32 %"45", ptr addrspace(5) %"40", align 4
%"47" = load i64, ptr addrspace(5) %"38", align 8
%"58" = inttoptr i64 %"47" to ptr
%"32" = getelementptr inbounds i8, ptr %"58", i64 4
%"48" = load i32, ptr %"32", align 4
store i32 %"48", ptr addrspace(5) %"41", align 4
%"49" = load i64, ptr addrspace(5) %"38", align 8
%"59" = inttoptr i64 %"49" to ptr
%"34" = getelementptr inbounds i8, ptr %"59", i64 8
%"50" = load i32, ptr %"34", align 4
store i32 %"50", ptr addrspace(5) %"42", align 4
%"52" = load i32, ptr addrspace(5) %"40", align 4
%"53" = load i32, ptr addrspace(5) %"41", align 4
%"54" = load i32, ptr addrspace(5) %"42", align 4
%"51" = call i32 @__zluda_ptx_impl_bfe_u32(i32 %"52", i32 %"53", i32 %"54")
store i32 %"51", ptr addrspace(5) %"40", align 4
%"55" = load i64, ptr addrspace(5) %"39", align 8
%"56" = load i32, ptr addrspace(5) %"40", align 4
%"60" = inttoptr i64 %"55" to ptr
store i32 %"56", ptr %"60", align 4
"38": ; preds = %1
%"46" = load i64, ptr addrspace(4) %"39", align 8
store i64 %"46", ptr addrspace(5) %"41", align 8
%"47" = load i64, ptr addrspace(4) %"40", align 8
store i64 %"47", ptr addrspace(5) %"42", align 8
%"49" = load i64, ptr addrspace(5) %"41", align 8
%"60" = inttoptr i64 %"49" to ptr
%"48" = load i32, ptr %"60", align 4
store i32 %"48", ptr addrspace(5) %"43", align 4
%"50" = load i64, ptr addrspace(5) %"41", align 8
%"61" = inttoptr i64 %"50" to ptr
%"35" = getelementptr inbounds i8, ptr %"61", i64 4
%"51" = load i32, ptr %"35", align 4
store i32 %"51", ptr addrspace(5) %"44", align 4
%"52" = load i64, ptr addrspace(5) %"41", align 8
%"62" = inttoptr i64 %"52" to ptr
%"37" = getelementptr inbounds i8, ptr %"62", i64 8
%"53" = load i32, ptr %"37", align 4
store i32 %"53", ptr addrspace(5) %"45", align 4
%"55" = load i32, ptr addrspace(5) %"43", align 4
%"56" = load i32, ptr addrspace(5) %"44", align 4
%"57" = load i32, ptr addrspace(5) %"45", align 4
%"54" = call i32 @__zluda_ptx_impl_bfe_u32(i32 %"55", i32 %"56", i32 %"57")
store i32 %"54", ptr addrspace(5) %"43", align 4
%"58" = load i64, ptr addrspace(5) %"42", align 8
%"59" = load i32, ptr addrspace(5) %"43", align 4
%"63" = inttoptr i64 %"58" to ptr
store i32 %"59", ptr %"63", align 4
ret void
}

80
ptx/src/test/ll/bfi.ll
View file

@ -1,51 +1,51 @@
declare hidden i32 @__zluda_ptx_impl_bfi_b32(i32, i32, i32, i32) #0
define amdgpu_kernel void @bfi(ptr addrspace(4) byref(i64) %"39", ptr addrspace(4) byref(i64) %"40") #1 {
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i64, align 8, addrspace(5)
%"43" = alloca i32, align 4, addrspace(5)
%"44" = alloca i32, align 4, addrspace(5)
%"45" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @bfi(ptr addrspace(4) byref(i64) %"42", ptr addrspace(4) byref(i64) %"43") #1 {
%"44" = alloca i64, align 8, addrspace(5)
%"45" = alloca i64, align 8, addrspace(5)
%"46" = alloca i32, align 4, addrspace(5)
%"47" = alloca i32, align 4, addrspace(5)
%"48" = alloca i32, align 4, addrspace(5)
%"49" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"38"
br label %"41"
"38": ; preds = %1
%"47" = load i64, ptr addrspace(4) %"39", align 8
store i64 %"47", ptr addrspace(5) %"41", align 8
%"48" = load i64, ptr addrspace(4) %"40", align 8
store i64 %"48", ptr addrspace(5) %"42", align 8
%"50" = load i64, ptr addrspace(5) %"41", align 8
%"64" = inttoptr i64 %"50" to ptr
%"49" = load i32, ptr %"64", align 4
store i32 %"49", ptr addrspace(5) %"43", align 4
%"51" = load i64, ptr addrspace(5) %"41", align 8
%"65" = inttoptr i64 %"51" to ptr
%"33" = getelementptr inbounds i8, ptr %"65", i64 4
%"52" = load i32, ptr %"33", align 4
store i32 %"52", ptr addrspace(5) %"44", align 4
%"53" = load i64, ptr addrspace(5) %"41", align 8
%"66" = inttoptr i64 %"53" to ptr
%"35" = getelementptr inbounds i8, ptr %"66", i64 8
%"54" = load i32, ptr %"35", align 4
store i32 %"54", ptr addrspace(5) %"45", align 4
%"55" = load i64, ptr addrspace(5) %"41", align 8
%"67" = inttoptr i64 %"55" to ptr
%"37" = getelementptr inbounds i8, ptr %"67", i64 12
%"56" = load i32, ptr %"37", align 4
store i32 %"56", ptr addrspace(5) %"46", align 4
%"58" = load i32, ptr addrspace(5) %"43", align 4
%"59" = load i32, ptr addrspace(5) %"44", align 4
%"60" = load i32, ptr addrspace(5) %"45", align 4
"41": ; preds = %1
%"50" = load i64, ptr addrspace(4) %"42", align 8
store i64 %"50", ptr addrspace(5) %"44", align 8
%"51" = load i64, ptr addrspace(4) %"43", align 8
store i64 %"51", ptr addrspace(5) %"45", align 8
%"53" = load i64, ptr addrspace(5) %"44", align 8
%"67" = inttoptr i64 %"53" to ptr
%"52" = load i32, ptr %"67", align 4
store i32 %"52", ptr addrspace(5) %"46", align 4
%"54" = load i64, ptr addrspace(5) %"44", align 8
%"68" = inttoptr i64 %"54" to ptr
%"36" = getelementptr inbounds i8, ptr %"68", i64 4
%"55" = load i32, ptr %"36", align 4
store i32 %"55", ptr addrspace(5) %"47", align 4
%"56" = load i64, ptr addrspace(5) %"44", align 8
%"69" = inttoptr i64 %"56" to ptr
%"38" = getelementptr inbounds i8, ptr %"69", i64 8
%"57" = load i32, ptr %"38", align 4
store i32 %"57", ptr addrspace(5) %"48", align 4
%"58" = load i64, ptr addrspace(5) %"44", align 8
%"70" = inttoptr i64 %"58" to ptr
%"40" = getelementptr inbounds i8, ptr %"70", i64 12
%"59" = load i32, ptr %"40", align 4
store i32 %"59", ptr addrspace(5) %"49", align 4
%"61" = load i32, ptr addrspace(5) %"46", align 4
%"68" = call i32 @__zluda_ptx_impl_bfi_b32(i32 %"58", i32 %"59", i32 %"60", i32 %"61")
store i32 %"68", ptr addrspace(5) %"43", align 4
%"62" = load i64, ptr addrspace(5) %"42", align 8
%"63" = load i32, ptr addrspace(5) %"43", align 4
%"71" = inttoptr i64 %"62" to ptr
store i32 %"63", ptr %"71", align 4
%"62" = load i32, ptr addrspace(5) %"47", align 4
%"63" = load i32, ptr addrspace(5) %"48", align 4
%"64" = load i32, ptr addrspace(5) %"49", align 4
%"71" = call i32 @__zluda_ptx_impl_bfi_b32(i32 %"61", i32 %"62", i32 %"63", i32 %"64")
store i32 %"71", ptr addrspace(5) %"46", align 4
%"65" = load i64, ptr addrspace(5) %"45", align 8
%"66" = load i32, ptr addrspace(5) %"46", align 4
%"74" = inttoptr i64 %"65" to ptr
store i32 %"66", ptr %"74", align 4
ret void
}

50
ptx/src/test/ll/block.ll
View file

@ -1,34 +1,34 @@
define amdgpu_kernel void @block(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @block(ptr addrspace(4) byref(i64) %"37", ptr addrspace(4) byref(i64) %"38") #0 {
%"39" = alloca i64, align 8, addrspace(5)
%"46" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i64, align 8, addrspace(5)
%"49" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"33"
br label %"36"
"33": ; preds = %1
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"51" = inttoptr i64 %"43" to ptr
%"42" = load i64, ptr %"51", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"45" = load i64, ptr addrspace(5) %"38", align 8
%"44" = add i64 %"45", 1
store i64 %"44", ptr addrspace(5) %"39", align 8
%"48" = load i64, ptr addrspace(5) %"46", align 8
"36": ; preds = %1
%"43" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"44" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"44", ptr addrspace(5) %"40", align 8
%"46" = load i64, ptr addrspace(5) %"39", align 8
%"54" = inttoptr i64 %"46" to ptr
%"45" = load i64, ptr %"54", align 8
store i64 %"45", ptr addrspace(5) %"41", align 8
%"48" = load i64, ptr addrspace(5) %"41", align 8
%"47" = add i64 %"48", 1
store i64 %"47", ptr addrspace(5) %"46", align 8
%"49" = load i64, ptr addrspace(5) %"37", align 8
%"50" = load i64, ptr addrspace(5) %"39", align 8
%"52" = inttoptr i64 %"49" to ptr
store i64 %"50", ptr %"52", align 8
store i64 %"47", ptr addrspace(5) %"42", align 8
%"51" = load i64, ptr addrspace(5) %"49", align 8
%"50" = add i64 %"51", 1
store i64 %"50", ptr addrspace(5) %"49", align 8
%"52" = load i64, ptr addrspace(5) %"40", align 8
%"53" = load i64, ptr addrspace(5) %"42", align 8
%"55" = inttoptr i64 %"52" to ptr
store i64 %"53", ptr %"55", align 8
ret void
}
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="preserve-sign" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="preserve-sign" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }

52
ptx/src/test/ll/bra.ll
View file

@ -1,36 +1,36 @@
define amdgpu_kernel void @bra(ptr addrspace(4) byref(i64) %"36", ptr addrspace(4) byref(i64) %"37") #0 {
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @bra(ptr addrspace(4) byref(i64) %"39", ptr addrspace(4) byref(i64) %"40") #0 {
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i64, align 8, addrspace(5)
%"43" = alloca i64, align 8, addrspace(5)
%"44" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"35"
br label %"38"
"35": ; preds = %1
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"43" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"45" = load i64, ptr addrspace(5) %"38", align 8
%"50" = inttoptr i64 %"45" to ptr
%"44" = load i64, ptr %"50", align 8
store i64 %"44", ptr addrspace(5) %"40", align 8
br label %"10"
"38": ; preds = %1
%"45" = load i64, ptr addrspace(4) %"39", align 8
store i64 %"45", ptr addrspace(5) %"41", align 8
%"46" = load i64, ptr addrspace(4) %"40", align 8
store i64 %"46", ptr addrspace(5) %"42", align 8
%"48" = load i64, ptr addrspace(5) %"41", align 8
%"53" = inttoptr i64 %"48" to ptr
%"47" = load i64, ptr %"53", align 8
store i64 %"47", ptr addrspace(5) %"43", align 8
br label %"11"
"10": ; preds = %"35"
%"47" = load i64, ptr addrspace(5) %"40", align 8
%"46" = add i64 %"47", 1
store i64 %"46", ptr addrspace(5) %"41", align 8
br label %"12"
"11": ; preds = %"38"
%"50" = load i64, ptr addrspace(5) %"43", align 8
%"49" = add i64 %"50", 1
store i64 %"49", ptr addrspace(5) %"44", align 8
br label %"13"
"12": ; preds = %"10"
%"48" = load i64, ptr addrspace(5) %"39", align 8
%"49" = load i64, ptr addrspace(5) %"41", align 8
%"51" = inttoptr i64 %"48" to ptr
store i64 %"49", ptr %"51", align 8
"13": ; preds = %"11"
%"51" = load i64, ptr addrspace(5) %"42", align 8
%"52" = load i64, ptr addrspace(5) %"44", align 8
%"54" = inttoptr i64 %"51" to ptr
store i64 %"52", ptr %"54", align 8
ret void
}
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="preserve-sign" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="preserve-sign" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }

42
ptx/src/test/ll/brev.ll
View file

@ -1,28 +1,28 @@
define amdgpu_kernel void @brev(ptr addrspace(4) byref(i64) %"30", ptr addrspace(4) byref(i64) %"31") #0 {
%"32" = alloca i64, align 8, addrspace(5)
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @brev(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"29"
br label %"32"
"29": ; preds = %1
%"35" = load i64, ptr addrspace(4) %"30", align 8
store i64 %"35", ptr addrspace(5) %"32", align 8
%"36" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"36", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(5) %"32", align 8
%"43" = inttoptr i64 %"38" to ptr
%"37" = load i32, ptr %"43", align 4
store i32 %"37", ptr addrspace(5) %"34", align 4
%"40" = load i32, ptr addrspace(5) %"34", align 4
%"39" = call i32 @llvm.bitreverse.i32(i32 %"40")
store i32 %"39", ptr addrspace(5) %"34", align 4
%"41" = load i64, ptr addrspace(5) %"33", align 8
%"42" = load i32, ptr addrspace(5) %"34", align 4
%"44" = inttoptr i64 %"41" to ptr
store i32 %"42", ptr %"44", align 4
"32": ; preds = %1
%"38" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"38", ptr addrspace(5) %"35", align 8
%"39" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"39", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(5) %"35", align 8
%"46" = inttoptr i64 %"41" to ptr
%"40" = load i32, ptr %"46", align 4
store i32 %"40", ptr addrspace(5) %"37", align 4
%"43" = load i32, ptr addrspace(5) %"37", align 4
%"42" = call i32 @llvm.bitreverse.i32(i32 %"43")
store i32 %"42", ptr addrspace(5) %"37", align 4
%"44" = load i64, ptr addrspace(5) %"36", align 8
%"45" = load i32, ptr addrspace(5) %"37", align 4
%"47" = inttoptr i64 %"44" to ptr
store i32 %"45", ptr %"47", align 4
ret void
}

92
ptx/src/test/ll/call.ll
View file

@ -1,62 +1,62 @@
define hidden i64 @incr(i64 %"43") #0 {
%"63" = alloca i64, align 8, addrspace(5)
%"64" = alloca i64, align 8, addrspace(5)
%"65" = alloca i64, align 8, addrspace(5)
define hidden i64 @incr(i64 %"46") #0 {
%"66" = alloca i64, align 8, addrspace(5)
%"67" = alloca i64, align 8, addrspace(5)
%"68" = alloca i64, align 8, addrspace(5)
%"69" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"46"
br label %"49"
"46": ; preds = %1
store i64 %"43", ptr addrspace(5) %"65", align 8
%"67" = load i64, ptr addrspace(5) %"65", align 8
store i64 %"67", ptr addrspace(5) %"66", align 8
%"69" = load i64, ptr addrspace(5) %"66", align 8
%"68" = add i64 %"69", 1
store i64 %"68", ptr addrspace(5) %"66", align 8
%"70" = load i64, ptr addrspace(5) %"66", align 8
store i64 %"70", ptr addrspace(5) %"64", align 8
%"71" = load i64, ptr addrspace(5) %"64", align 8
store i64 %"71", ptr addrspace(5) %"63", align 8
%2 = load i64, ptr addrspace(5) %"63", align 8
"49": ; preds = %1
store i64 %"46", ptr addrspace(5) %"68", align 8
%"70" = load i64, ptr addrspace(5) %"68", align 8
store i64 %"70", ptr addrspace(5) %"69", align 8
%"72" = load i64, ptr addrspace(5) %"69", align 8
%"71" = add i64 %"72", 1
store i64 %"71", ptr addrspace(5) %"69", align 8
%"73" = load i64, ptr addrspace(5) %"69", align 8
store i64 %"73", ptr addrspace(5) %"67", align 8
%"74" = load i64, ptr addrspace(5) %"67", align 8
store i64 %"74", ptr addrspace(5) %"66", align 8
%2 = load i64, ptr addrspace(5) %"66", align 8
ret i64 %2
}
define amdgpu_kernel void @call(ptr addrspace(4) byref(i64) %"48", ptr addrspace(4) byref(i64) %"49") #1 {
%"50" = alloca i64, align 8, addrspace(5)
%"51" = alloca i64, align 8, addrspace(5)
%"52" = alloca i64, align 8, addrspace(5)
%"57" = alloca i64, align 8, addrspace(5)
%"58" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @call(ptr addrspace(4) byref(i64) %"51", ptr addrspace(4) byref(i64) %"52") #1 {
%"53" = alloca i64, align 8, addrspace(5)
%"54" = alloca i64, align 8, addrspace(5)
%"55" = alloca i64, align 8, addrspace(5)
%"60" = alloca i64, align 8, addrspace(5)
%"61" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"44"
br label %"47"
"44": ; preds = %1
%"53" = load i64, ptr addrspace(4) %"48", align 8
store i64 %"53", ptr addrspace(5) %"50", align 8
%"54" = load i64, ptr addrspace(4) %"49", align 8
store i64 %"54", ptr addrspace(5) %"51", align 8
%"56" = load i64, ptr addrspace(5) %"50", align 8
%"72" = inttoptr i64 %"56" to ptr addrspace(1)
%"55" = load i64, ptr addrspace(1) %"72", align 8
store i64 %"55", ptr addrspace(5) %"52", align 8
%"59" = load i64, ptr addrspace(5) %"52", align 8
store i64 %"59", ptr addrspace(5) %"57", align 8
%"40" = load i64, ptr addrspace(5) %"57", align 8
%"41" = call i64 @incr(i64 %"40")
br label %"45"
"47": ; preds = %1
%"56" = load i64, ptr addrspace(4) %"51", align 8
store i64 %"56", ptr addrspace(5) %"53", align 8
%"57" = load i64, ptr addrspace(4) %"52", align 8
store i64 %"57", ptr addrspace(5) %"54", align 8
%"59" = load i64, ptr addrspace(5) %"53", align 8
%"75" = inttoptr i64 %"59" to ptr addrspace(1)
%"58" = load i64, ptr addrspace(1) %"75", align 8
store i64 %"58", ptr addrspace(5) %"55", align 8
%"62" = load i64, ptr addrspace(5) %"55", align 8
store i64 %"62", ptr addrspace(5) %"60", align 8
%"43" = load i64, ptr addrspace(5) %"60", align 8
%"44" = call i64 @incr(i64 %"43")
br label %"48"
"45": ; preds = %"44"
store i64 %"41", ptr addrspace(5) %"58", align 8
%"60" = load i64, ptr addrspace(5) %"58", align 8
store i64 %"60", ptr addrspace(5) %"52", align 8
%"61" = load i64, ptr addrspace(5) %"51", align 8
%"62" = load i64, ptr addrspace(5) %"52", align 8
%"75" = inttoptr i64 %"61" to ptr addrspace(1)
store i64 %"62", ptr addrspace(1) %"75", align 8
"48": ; preds = %"47"
store i64 %"44", ptr addrspace(5) %"61", align 8
%"63" = load i64, ptr addrspace(5) %"61", align 8
store i64 %"63", ptr addrspace(5) %"55", align 8
%"64" = load i64, ptr addrspace(5) %"54", align 8
%"65" = load i64, ptr addrspace(5) %"55", align 8
%"78" = inttoptr i64 %"64" to ptr addrspace(1)
store i64 %"65", ptr addrspace(1) %"78", align 8
ret void
}

210
ptx/src/test/ll/call_rnd.ll
View file

@ -1,75 +1,72 @@
define hidden float @add_rm(float %"79", float %"80") #0 {
%"128" = alloca float, align 4, addrspace(5)
%"129" = alloca float, align 4, addrspace(5)
%"130" = alloca float, align 4, addrspace(5)
define hidden float @add_rm(float %"82", float %"83") #0 {
%"131" = alloca float, align 4, addrspace(5)
%"132" = alloca float, align 4, addrspace(5)
%"133" = alloca float, align 4, addrspace(5)
%"134" = alloca float, align 4, addrspace(5)
%"135" = alloca float, align 4, addrspace(5)
%"136" = alloca float, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"89"
br label %"92"
"89": ; preds = %1
"92": ; preds = %1
call void @llvm.amdgcn.s.setreg(i32 6145, i32 2)
br label %"87"
br label %"90"
"87": ; preds = %"89"
store float %"79", ptr addrspace(5) %"130", align 4
store float %"80", ptr addrspace(5) %"131", align 4
%"134" = load float, ptr addrspace(5) %"130", align 4
store float %"134", ptr addrspace(5) %"132", align 4
%"135" = load float, ptr addrspace(5) %"131", align 4
store float %"135", ptr addrspace(5) %"133", align 4
%"137" = load float, ptr addrspace(5) %"132", align 4
%"138" = load float, ptr addrspace(5) %"133", align 4
%"136" = fadd float %"137", %"138"
store float %"136", ptr addrspace(5) %"132", align 4
%"139" = load float, ptr addrspace(5) %"132", align 4
store float %"139", ptr addrspace(5) %"129", align 4
%"140" = load float, ptr addrspace(5) %"129", align 4
store float %"140", ptr addrspace(5) %"128", align 4
%2 = load float, ptr addrspace(5) %"128", align 4
"90": ; preds = %"92"
store float %"82", ptr addrspace(5) %"133", align 4
store float %"83", ptr addrspace(5) %"134", align 4
%"137" = load float, ptr addrspace(5) %"133", align 4
store float %"137", ptr addrspace(5) %"135", align 4
%"138" = load float, ptr addrspace(5) %"134", align 4
store float %"138", ptr addrspace(5) %"136", align 4
%"140" = load float, ptr addrspace(5) %"135", align 4
%"141" = load float, ptr addrspace(5) %"136", align 4
%"139" = fadd float %"140", %"141"
store float %"139", ptr addrspace(5) %"135", align 4
%"142" = load float, ptr addrspace(5) %"135", align 4
store float %"142", ptr addrspace(5) %"132", align 4
%"143" = load float, ptr addrspace(5) %"132", align 4
store float %"143", ptr addrspace(5) %"131", align 4
%2 = load float, ptr addrspace(5) %"131", align 4
ret float %2
}
define hidden float @add_rp(float %"82", float %"83") #0 {
%"141" = alloca float, align 4, addrspace(5)
%"142" = alloca float, align 4, addrspace(5)
%"143" = alloca float, align 4, addrspace(5)
define hidden float @add_rp(float %"85", float %"86") #0 {
%"144" = alloca float, align 4, addrspace(5)
%"145" = alloca float, align 4, addrspace(5)
%"146" = alloca float, align 4, addrspace(5)
%"147" = alloca float, align 4, addrspace(5)
%"148" = alloca float, align 4, addrspace(5)
%"149" = alloca float, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"88"
br label %"91"
"88": ; preds = %1
store float %"82", ptr addrspace(5) %"143", align 4
store float %"83", ptr addrspace(5) %"144", align 4
%"147" = load float, ptr addrspace(5) %"143", align 4
store float %"147", ptr addrspace(5) %"145", align 4
%"148" = load float, ptr addrspace(5) %"144", align 4
store float %"148", ptr addrspace(5) %"146", align 4
%"150" = load float, ptr addrspace(5) %"145", align 4
%"151" = load float, ptr addrspace(5) %"146", align 4
%"149" = fadd float %"150", %"151"
store float %"149", ptr addrspace(5) %"145", align 4
%"152" = load float, ptr addrspace(5) %"145", align 4
store float %"152", ptr addrspace(5) %"142", align 4
%"153" = load float, ptr addrspace(5) %"142", align 4
store float %"153", ptr addrspace(5) %"141", align 4
%2 = load float, ptr addrspace(5) %"141", align 4
"91": ; preds = %1
store float %"85", ptr addrspace(5) %"146", align 4
store float %"86", ptr addrspace(5) %"147", align 4
%"150" = load float, ptr addrspace(5) %"146", align 4
store float %"150", ptr addrspace(5) %"148", align 4
%"151" = load float, ptr addrspace(5) %"147", align 4
store float %"151", ptr addrspace(5) %"149", align 4
%"153" = load float, ptr addrspace(5) %"148", align 4
%"154" = load float, ptr addrspace(5) %"149", align 4
%"152" = fadd float %"153", %"154"
store float %"152", ptr addrspace(5) %"148", align 4
%"155" = load float, ptr addrspace(5) %"148", align 4
store float %"155", ptr addrspace(5) %"145", align 4
%"156" = load float, ptr addrspace(5) %"145", align 4
store float %"156", ptr addrspace(5) %"144", align 4
%2 = load float, ptr addrspace(5) %"144", align 4
ret float %2
}
define amdgpu_kernel void @call_rnd(ptr addrspace(4) byref(i64) %"92", ptr addrspace(4) byref(i64) %"93") #1 {
%"94" = alloca i64, align 8, addrspace(5)
%"95" = alloca i64, align 8, addrspace(5)
%"96" = alloca float, align 4, addrspace(5)
%"97" = alloca float, align 4, addrspace(5)
%"98" = alloca float, align 4, addrspace(5)
define amdgpu_kernel void @call_rnd(ptr addrspace(4) byref(i64) %"95", ptr addrspace(4) byref(i64) %"96") #1 {
%"97" = alloca i64, align 8, addrspace(5)
%"98" = alloca i64, align 8, addrspace(5)
%"99" = alloca float, align 4, addrspace(5)
%"100" = alloca float, align 4, addrspace(5)
%"101" = alloca float, align 4, addrspace(5)
@ -79,71 +76,74 @@ define amdgpu_kernel void @call_rnd(ptr addrspace(4) byref(i64) %"92", ptr addrs
%"105" = alloca float, align 4, addrspace(5)
%"106" = alloca float, align 4, addrspace(5)
%"107" = alloca float, align 4, addrspace(5)
%"108" = alloca float, align 4, addrspace(5)
%"109" = alloca float, align 4, addrspace(5)
%"110" = alloca float, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"84"
br label %"87"
"84": ; preds = %1
"87": ; preds = %1
call void @llvm.amdgcn.s.setreg(i32 6145, i32 1)
%"108" = load i64, ptr addrspace(4) %"92", align 8
store i64 %"108", ptr addrspace(5) %"94", align 8
%"109" = load i64, ptr addrspace(4) %"93", align 8
store i64 %"109", ptr addrspace(5) %"95", align 8
%"111" = load i64, ptr addrspace(5) %"94", align 8
%"154" = inttoptr i64 %"111" to ptr
%"110" = load float, ptr %"154", align 4
store float %"110", ptr addrspace(5) %"96", align 4
%"112" = load i64, ptr addrspace(5) %"94", align 8
%"155" = inttoptr i64 %"112" to ptr
%"59" = getelementptr inbounds i8, ptr %"155", i64 4
%"113" = load float, ptr %"59", align 4
store float %"113", ptr addrspace(5) %"97", align 4
%"114" = load i64, ptr addrspace(5) %"94", align 8
%"156" = inttoptr i64 %"114" to ptr
%"61" = getelementptr inbounds i8, ptr %"156", i64 8
%"115" = load float, ptr %"61", align 4
store float %"115", ptr addrspace(5) %"98", align 4
%"116" = load i64, ptr addrspace(5) %"94", align 8
%"157" = inttoptr i64 %"116" to ptr
%"63" = getelementptr inbounds i8, ptr %"157", i64 12
%"117" = load float, ptr %"63", align 4
store float %"117", ptr addrspace(5) %"99", align 4
%"118" = load float, ptr addrspace(5) %"96", align 4
store float %"118", ptr addrspace(5) %"102", align 4
%"119" = load float, ptr addrspace(5) %"97", align 4
store float %"119", ptr addrspace(5) %"103", align 4
%"72" = load float, ptr addrspace(5) %"102", align 4
%"73" = load float, ptr addrspace(5) %"103", align 4
%"74" = call float @add_rp(float %"72", float %"73")
br label %"85"
"85": ; preds = %"84"
store float %"74", ptr addrspace(5) %"104", align 4
%"120" = load float, ptr addrspace(5) %"104", align 4
store float %"120", ptr addrspace(5) %"100", align 4
%"121" = load i64, ptr addrspace(5) %"95", align 8
%"111" = load i64, ptr addrspace(4) %"95", align 8
store i64 %"111", ptr addrspace(5) %"97", align 8
%"112" = load i64, ptr addrspace(4) %"96", align 8
store i64 %"112", ptr addrspace(5) %"98", align 8
%"114" = load i64, ptr addrspace(5) %"97", align 8
%"157" = inttoptr i64 %"114" to ptr
%"113" = load float, ptr %"157", align 4
store float %"113", ptr addrspace(5) %"99", align 4
%"115" = load i64, ptr addrspace(5) %"97", align 8
%"158" = inttoptr i64 %"115" to ptr
%"62" = getelementptr inbounds i8, ptr %"158", i64 4
%"116" = load float, ptr %"62", align 4
store float %"116", ptr addrspace(5) %"100", align 4
%"117" = load i64, ptr addrspace(5) %"97", align 8
%"159" = inttoptr i64 %"117" to ptr
%"64" = getelementptr inbounds i8, ptr %"159", i64 8
%"118" = load float, ptr %"64", align 4
store float %"118", ptr addrspace(5) %"101", align 4
%"119" = load i64, ptr addrspace(5) %"97", align 8
%"160" = inttoptr i64 %"119" to ptr
%"66" = getelementptr inbounds i8, ptr %"160", i64 12
%"120" = load float, ptr %"66", align 4
store float %"120", ptr addrspace(5) %"102", align 4
%"121" = load float, ptr addrspace(5) %"99", align 4
store float %"121", ptr addrspace(5) %"105", align 4
%"122" = load float, ptr addrspace(5) %"100", align 4
%"158" = inttoptr i64 %"121" to ptr
store float %"122", ptr %"158", align 4
%"123" = load float, ptr addrspace(5) %"98", align 4
store float %"123", ptr addrspace(5) %"105", align 4
%"124" = load float, ptr addrspace(5) %"99", align 4
store float %"124", ptr addrspace(5) %"106", align 4
store float %"122", ptr addrspace(5) %"106", align 4
%"75" = load float, ptr addrspace(5) %"105", align 4
%"76" = load float, ptr addrspace(5) %"106", align 4
%"77" = call float @add_rm(float %"75", float %"76")
br label %"86"
%"77" = call float @add_rp(float %"75", float %"76")
br label %"88"
"86": ; preds = %"85"
"88": ; preds = %"87"
store float %"77", ptr addrspace(5) %"107", align 4
%"125" = load float, ptr addrspace(5) %"107", align 4
store float %"125", ptr addrspace(5) %"101", align 4
%"126" = load i64, ptr addrspace(5) %"95", align 8
%"159" = inttoptr i64 %"126" to ptr
%"65" = getelementptr inbounds i8, ptr %"159", i64 4
%"127" = load float, ptr addrspace(5) %"101", align 4
store float %"127", ptr %"65", align 4
%"123" = load float, ptr addrspace(5) %"107", align 4
store float %"123", ptr addrspace(5) %"103", align 4
%"124" = load i64, ptr addrspace(5) %"98", align 8
%"125" = load float, ptr addrspace(5) %"103", align 4
%"161" = inttoptr i64 %"124" to ptr
store float %"125", ptr %"161", align 4
%"126" = load float, ptr addrspace(5) %"101", align 4
store float %"126", ptr addrspace(5) %"108", align 4
%"127" = load float, ptr addrspace(5) %"102", align 4
store float %"127", ptr addrspace(5) %"109", align 4
%"78" = load float, ptr addrspace(5) %"108", align 4
%"79" = load float, ptr addrspace(5) %"109", align 4
%"80" = call float @add_rm(float %"78", float %"79")
br label %"89"
"89": ; preds = %"88"
store float %"80", ptr addrspace(5) %"110", align 4
%"128" = load float, ptr addrspace(5) %"110", align 4
store float %"128", ptr addrspace(5) %"104", align 4
%"129" = load i64, ptr addrspace(5) %"98", align 8
%"162" = inttoptr i64 %"129" to ptr
%"68" = getelementptr inbounds i8, ptr %"162", i64 4
%"130" = load float, ptr addrspace(5) %"104", align 4
store float %"130", ptr %"68", align 4
ret void
}

42
ptx/src/test/ll/clz.ll
View file

@ -1,28 +1,28 @@
define amdgpu_kernel void @clz(ptr addrspace(4) byref(i64) %"30", ptr addrspace(4) byref(i64) %"31") #0 {
%"32" = alloca i64, align 8, addrspace(5)
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @clz(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"29"
br label %"32"
"29": ; preds = %1
%"35" = load i64, ptr addrspace(4) %"30", align 8
store i64 %"35", ptr addrspace(5) %"32", align 8
%"36" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"36", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(5) %"32", align 8
%"43" = inttoptr i64 %"38" to ptr
%"37" = load i32, ptr %"43", align 4
store i32 %"37", ptr addrspace(5) %"34", align 4
%"40" = load i32, ptr addrspace(5) %"34", align 4
%"44" = call i32 @llvm.ctlz.i32(i32 %"40", i1 false)
store i32 %"44", ptr addrspace(5) %"34", align 4
%"41" = load i64, ptr addrspace(5) %"33", align 8
%"42" = load i32, ptr addrspace(5) %"34", align 4
%"45" = inttoptr i64 %"41" to ptr
store i32 %"42", ptr %"45", align 4
"32": ; preds = %1
%"38" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"38", ptr addrspace(5) %"35", align 8
%"39" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"39", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(5) %"35", align 8
%"46" = inttoptr i64 %"41" to ptr
%"40" = load i32, ptr %"46", align 4
store i32 %"40", ptr addrspace(5) %"37", align 4
%"43" = load i32, ptr addrspace(5) %"37", align 4
%"47" = call i32 @llvm.ctlz.i32(i32 %"43", i1 false)
store i32 %"47", ptr addrspace(5) %"37", align 4
%"44" = load i64, ptr addrspace(5) %"36", align 8
%"45" = load i32, ptr addrspace(5) %"37", align 4
%"48" = inttoptr i64 %"44" to ptr
store i32 %"45", ptr %"48", align 4
ret void
}

78
ptx/src/test/ll/const.ll
View file

@ -1,50 +1,50 @@
@constparams = addrspace(4) global [4 x i16] [i16 10, i16 20, i16 30, i16 40], align 8
define amdgpu_kernel void @const(ptr addrspace(4) byref(i64) %"46", ptr addrspace(4) byref(i64) %"47") #0 {
%"48" = alloca i64, align 8, addrspace(5)
%"49" = alloca i64, align 8, addrspace(5)
%"50" = alloca i16, align 2, addrspace(5)
%"51" = alloca i16, align 2, addrspace(5)
%"52" = alloca i16, align 2, addrspace(5)
define amdgpu_kernel void @const(ptr addrspace(4) byref(i64) %"49", ptr addrspace(4) byref(i64) %"50") #0 {
%"51" = alloca i64, align 8, addrspace(5)
%"52" = alloca i64, align 8, addrspace(5)
%"53" = alloca i16, align 2, addrspace(5)
%"54" = alloca i16, align 2, addrspace(5)
%"55" = alloca i16, align 2, addrspace(5)
%"56" = alloca i16, align 2, addrspace(5)
br label %1
1: ; preds = %0
br label %"45"
br label %"48"
"45": ; preds = %1
%"54" = load i64, ptr addrspace(4) %"46", align 8
store i64 %"54", ptr addrspace(5) %"48", align 8
%"55" = load i64, ptr addrspace(4) %"47", align 8
store i64 %"55", ptr addrspace(5) %"49", align 8
%"56" = load i16, ptr addrspace(4) @constparams, align 2
store i16 %"56", ptr addrspace(5) %"50", align 2
%"57" = load i16, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) @constparams, i64 2), align 2
store i16 %"57", ptr addrspace(5) %"51", align 2
%"58" = load i16, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) @constparams, i64 4), align 2
store i16 %"58", ptr addrspace(5) %"52", align 2
%"59" = load i16, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) @constparams, i64 6), align 2
"48": ; preds = %1
%"57" = load i64, ptr addrspace(4) %"49", align 8
store i64 %"57", ptr addrspace(5) %"51", align 8
%"58" = load i64, ptr addrspace(4) %"50", align 8
store i64 %"58", ptr addrspace(5) %"52", align 8
%"59" = load i16, ptr addrspace(4) @constparams, align 2
store i16 %"59", ptr addrspace(5) %"53", align 2
%"60" = load i64, ptr addrspace(5) %"49", align 8
%"61" = load i16, ptr addrspace(5) %"50", align 2
%"72" = inttoptr i64 %"60" to ptr
store i16 %"61", ptr %"72", align 2
%"62" = load i64, ptr addrspace(5) %"49", align 8
%"74" = inttoptr i64 %"62" to ptr
%"40" = getelementptr inbounds i8, ptr %"74", i64 2
%"63" = load i16, ptr addrspace(5) %"51", align 2
store i16 %"63", ptr %"40", align 2
%"64" = load i64, ptr addrspace(5) %"49", align 8
%"76" = inttoptr i64 %"64" to ptr
%"42" = getelementptr inbounds i8, ptr %"76", i64 4
%"65" = load i16, ptr addrspace(5) %"52", align 2
store i16 %"65", ptr %"42", align 2
%"66" = load i64, ptr addrspace(5) %"49", align 8
%"78" = inttoptr i64 %"66" to ptr
%"44" = getelementptr inbounds i8, ptr %"78", i64 6
%"67" = load i16, ptr addrspace(5) %"53", align 2
store i16 %"67", ptr %"44", align 2
%"60" = load i16, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) @constparams, i64 2), align 2
store i16 %"60", ptr addrspace(5) %"54", align 2
%"61" = load i16, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) @constparams, i64 4), align 2
store i16 %"61", ptr addrspace(5) %"55", align 2
%"62" = load i16, ptr addrspace(4) getelementptr inbounds (i8, ptr addrspace(4) @constparams, i64 6), align 2
store i16 %"62", ptr addrspace(5) %"56", align 2
%"63" = load i64, ptr addrspace(5) %"52", align 8
%"64" = load i16, ptr addrspace(5) %"53", align 2
%"75" = inttoptr i64 %"63" to ptr
store i16 %"64", ptr %"75", align 2
%"65" = load i64, ptr addrspace(5) %"52", align 8
%"77" = inttoptr i64 %"65" to ptr
%"43" = getelementptr inbounds i8, ptr %"77", i64 2
%"66" = load i16, ptr addrspace(5) %"54", align 2
store i16 %"66", ptr %"43", align 2
%"67" = load i64, ptr addrspace(5) %"52", align 8
%"79" = inttoptr i64 %"67" to ptr
%"45" = getelementptr inbounds i8, ptr %"79", i64 4
%"68" = load i16, ptr addrspace(5) %"55", align 2
store i16 %"68", ptr %"45", align 2
%"69" = load i64, ptr addrspace(5) %"52", align 8
%"81" = inttoptr i64 %"69" to ptr
%"47" = getelementptr inbounds i8, ptr %"81", i64 6
%"70" = load i16, ptr addrspace(5) %"56", align 2
store i16 %"70", ptr %"47", align 2
ret void
}
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="preserve-sign" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="preserve-sign" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }

42
ptx/src/test/ll/constant_f32.ll
View file

@ -1,28 +1,28 @@
define amdgpu_kernel void @constant_f32(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #0 {
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca float, align 4, addrspace(5)
define amdgpu_kernel void @constant_f32(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca float, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"30"
br label %"33"
"30": ; preds = %1
%"36" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"36", ptr addrspace(5) %"33", align 8
%"37" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"37", ptr addrspace(5) %"34", align 8
%"39" = load i64, ptr addrspace(5) %"33", align 8
%"44" = inttoptr i64 %"39" to ptr
%"38" = load float, ptr %"44", align 4
store float %"38", ptr addrspace(5) %"35", align 4
%"41" = load float, ptr addrspace(5) %"35", align 4
%"40" = fmul float %"41", 5.000000e-01
store float %"40", ptr addrspace(5) %"35", align 4
%"42" = load i64, ptr addrspace(5) %"34", align 8
%"43" = load float, ptr addrspace(5) %"35", align 4
%"45" = inttoptr i64 %"42" to ptr
store float %"43", ptr %"45", align 4
"33": ; preds = %1
%"39" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"39", ptr addrspace(5) %"36", align 8
%"40" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"40", ptr addrspace(5) %"37", align 8
%"42" = load i64, ptr addrspace(5) %"36", align 8
%"47" = inttoptr i64 %"42" to ptr
%"41" = load float, ptr %"47", align 4
store float %"41", ptr addrspace(5) %"38", align 4
%"44" = load float, ptr addrspace(5) %"38", align 4
%"43" = fmul float %"44", 5.000000e-01
store float %"43", ptr addrspace(5) %"38", align 4
%"45" = load i64, ptr addrspace(5) %"37", align 8
%"46" = load float, ptr addrspace(5) %"38", align 4
%"48" = inttoptr i64 %"45" to ptr
store float %"46", ptr %"48", align 4
ret void
}

42
ptx/src/test/ll/constant_negative.ll
View file

@ -1,28 +1,28 @@
define amdgpu_kernel void @constant_negative(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #0 {
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @constant_negative(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"30"
br label %"33"
"30": ; preds = %1
%"36" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"36", ptr addrspace(5) %"33", align 8
%"37" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"37", ptr addrspace(5) %"34", align 8
%"39" = load i64, ptr addrspace(5) %"33", align 8
%"44" = inttoptr i64 %"39" to ptr
%"38" = load i32, ptr %"44", align 4
store i32 %"38", ptr addrspace(5) %"35", align 4
%"41" = load i32, ptr addrspace(5) %"35", align 4
%"40" = mul i32 %"41", -1
store i32 %"40", ptr addrspace(5) %"35", align 4
%"42" = load i64, ptr addrspace(5) %"34", align 8
%"43" = load i32, ptr addrspace(5) %"35", align 4
%"45" = inttoptr i64 %"42" to ptr
store i32 %"43", ptr %"45", align 4
"33": ; preds = %1
%"39" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"39", ptr addrspace(5) %"36", align 8
%"40" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"40", ptr addrspace(5) %"37", align 8
%"42" = load i64, ptr addrspace(5) %"36", align 8
%"47" = inttoptr i64 %"42" to ptr
%"41" = load i32, ptr %"47", align 4
store i32 %"41", ptr addrspace(5) %"38", align 4
%"44" = load i32, ptr addrspace(5) %"38", align 4
%"43" = mul i32 %"44", -1
store i32 %"43", ptr addrspace(5) %"38", align 4
%"45" = load i64, ptr addrspace(5) %"37", align 8
%"46" = load i32, ptr addrspace(5) %"38", align 4
%"48" = inttoptr i64 %"45" to ptr
store i32 %"46", ptr %"48", align 4
ret void
}

42
ptx/src/test/ll/cos.ll
View file

@ -1,28 +1,28 @@
define amdgpu_kernel void @cos(ptr addrspace(4) byref(i64) %"30", ptr addrspace(4) byref(i64) %"31") #0 {
%"32" = alloca i64, align 8, addrspace(5)
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca float, align 4, addrspace(5)
define amdgpu_kernel void @cos(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca float, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"29"
br label %"32"
"29": ; preds = %1
%"35" = load i64, ptr addrspace(4) %"30", align 8
store i64 %"35", ptr addrspace(5) %"32", align 8
%"36" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"36", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(5) %"32", align 8
%"43" = inttoptr i64 %"38" to ptr
%"37" = load float, ptr %"43", align 4
store float %"37", ptr addrspace(5) %"34", align 4
%"40" = load float, ptr addrspace(5) %"34", align 4
%"39" = call afn float @llvm.cos.f32(float %"40")
store float %"39", ptr addrspace(5) %"34", align 4
%"41" = load i64, ptr addrspace(5) %"33", align 8
%"42" = load float, ptr addrspace(5) %"34", align 4
%"44" = inttoptr i64 %"41" to ptr
store float %"42", ptr %"44", align 4
"32": ; preds = %1
%"38" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"38", ptr addrspace(5) %"35", align 8
%"39" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"39", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(5) %"35", align 8
%"46" = inttoptr i64 %"41" to ptr
%"40" = load float, ptr %"46", align 4
store float %"40", ptr addrspace(5) %"37", align 4
%"43" = load float, ptr addrspace(5) %"37", align 4
%"42" = call afn float @llvm.cos.f32(float %"43")
store float %"42", ptr addrspace(5) %"37", align 4
%"44" = load i64, ptr addrspace(5) %"36", align 8
%"45" = load float, ptr addrspace(5) %"37", align 4
%"47" = inttoptr i64 %"44" to ptr
store float %"45", ptr %"47", align 4
ret void
}

76
ptx/src/test/ll/cp_async.ll
View file

@ -1,53 +1,53 @@
@from = addrspace(1) global [4 x i32] [i32 1, i32 2, i32 3, i32 4]
@to = external addrspace(3) global [4 x i32]
define amdgpu_kernel void @cp_async(ptr addrspace(4) byref(i64) %"48", ptr addrspace(4) byref(i64) %"49") #0 {
%"50" = alloca i64, align 8, addrspace(5)
%"51" = alloca i64, align 8, addrspace(5)
%"52" = alloca i32, align 4, addrspace(5)
%"53" = alloca i32, align 4, addrspace(5)
%"54" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @cp_async(ptr addrspace(4) byref(i64) %"51", ptr addrspace(4) byref(i64) %"52") #0 {
%"53" = alloca i64, align 8, addrspace(5)
%"54" = alloca i64, align 8, addrspace(5)
%"55" = alloca i32, align 4, addrspace(5)
%"56" = alloca i32, align 4, addrspace(5)
%"57" = alloca i32, align 4, addrspace(5)
%"58" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"47"
br label %"50"
"47": ; preds = %1
%"56" = load i64, ptr addrspace(4) %"48", align 8
store i64 %"56", ptr addrspace(5) %"50", align 8
%"57" = load i64, ptr addrspace(4) %"49", align 8
store i64 %"57", ptr addrspace(5) %"51", align 8
"50": ; preds = %1
%"59" = load i64, ptr addrspace(4) %"51", align 8
store i64 %"59", ptr addrspace(5) %"53", align 8
%"60" = load i64, ptr addrspace(4) %"52", align 8
store i64 %"60", ptr addrspace(5) %"54", align 8
%2 = load i96, ptr addrspace(1) @from, align 128
%3 = zext i96 %2 to i128
store i128 %3, ptr addrspace(3) @to, align 4
%"58" = load i32, ptr addrspacecast (ptr addrspace(3) @to to ptr), align 4
store i32 %"58", ptr addrspace(5) %"52", align 4
%"59" = load i32, ptr getelementptr inbounds (i8, ptr addrspacecast (ptr addrspace(3) @to to ptr), i64 4), align 4
store i32 %"59", ptr addrspace(5) %"53", align 4
%"60" = load i32, ptr getelementptr inbounds (i8, ptr addrspacecast (ptr addrspace(3) @to to ptr), i64 8), align 4
store i32 %"60", ptr addrspace(5) %"54", align 4
%"61" = load i32, ptr getelementptr inbounds (i8, ptr addrspacecast (ptr addrspace(3) @to to ptr), i64 12), align 4
%"61" = load i32, ptr addrspacecast (ptr addrspace(3) @to to ptr), align 4
store i32 %"61", ptr addrspace(5) %"55", align 4
%"62" = load i64, ptr addrspace(5) %"51", align 8
%"63" = load i32, ptr addrspace(5) %"52", align 4
%"76" = inttoptr i64 %"62" to ptr
store i32 %"63", ptr %"76", align 4
%"64" = load i64, ptr addrspace(5) %"51", align 8
%"77" = inttoptr i64 %"64" to ptr
%"42" = getelementptr inbounds i8, ptr %"77", i64 4
%"65" = load i32, ptr addrspace(5) %"53", align 4
store i32 %"65", ptr %"42", align 4
%"66" = load i64, ptr addrspace(5) %"51", align 8
%"78" = inttoptr i64 %"66" to ptr
%"44" = getelementptr inbounds i8, ptr %"78", i64 8
%"67" = load i32, ptr addrspace(5) %"54", align 4
store i32 %"67", ptr %"44", align 4
%"68" = load i64, ptr addrspace(5) %"51", align 8
%"79" = inttoptr i64 %"68" to ptr
%"46" = getelementptr inbounds i8, ptr %"79", i64 12
%"69" = load i32, ptr addrspace(5) %"55", align 4
store i32 %"69", ptr %"46", align 4
%"62" = load i32, ptr getelementptr inbounds (i8, ptr addrspacecast (ptr addrspace(3) @to to ptr), i64 4), align 4
store i32 %"62", ptr addrspace(5) %"56", align 4
%"63" = load i32, ptr getelementptr inbounds (i8, ptr addrspacecast (ptr addrspace(3) @to to ptr), i64 8), align 4
store i32 %"63", ptr addrspace(5) %"57", align 4
%"64" = load i32, ptr getelementptr inbounds (i8, ptr addrspacecast (ptr addrspace(3) @to to ptr), i64 12), align 4
store i32 %"64", ptr addrspace(5) %"58", align 4
%"65" = load i64, ptr addrspace(5) %"54", align 8
%"66" = load i32, ptr addrspace(5) %"55", align 4
%"79" = inttoptr i64 %"65" to ptr
store i32 %"66", ptr %"79", align 4
%"67" = load i64, ptr addrspace(5) %"54", align 8
%"80" = inttoptr i64 %"67" to ptr
%"45" = getelementptr inbounds i8, ptr %"80", i64 4
%"68" = load i32, ptr addrspace(5) %"56", align 4
store i32 %"68", ptr %"45", align 4
%"69" = load i64, ptr addrspace(5) %"54", align 8
%"81" = inttoptr i64 %"69" to ptr
%"47" = getelementptr inbounds i8, ptr %"81", i64 8
%"70" = load i32, ptr addrspace(5) %"57", align 4
store i32 %"70", ptr %"47", align 4
%"71" = load i64, ptr addrspace(5) %"54", align 8
%"82" = inttoptr i64 %"71" to ptr
%"49" = getelementptr inbounds i8, ptr %"82", i64 12
%"72" = load i32, ptr addrspace(5) %"58", align 4
store i32 %"72", ptr %"49", align 4
ret void
}

44
ptx/src/test/ll/cvt_f64_f32.ll
View file

@ -1,29 +1,29 @@
define amdgpu_kernel void @cvt_f64_f32(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #0 {
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca float, align 4, addrspace(5)
%"36" = alloca double, align 8, addrspace(5)
define amdgpu_kernel void @cvt_f64_f32(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca float, align 4, addrspace(5)
%"39" = alloca double, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"30"
br label %"33"
"30": ; preds = %1
%"37" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"37", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"38", ptr addrspace(5) %"34", align 8
%"40" = load i64, ptr addrspace(5) %"33", align 8
%"45" = inttoptr i64 %"40" to ptr addrspace(1)
%"39" = load float, ptr addrspace(1) %"45", align 4
store float %"39", ptr addrspace(5) %"35", align 4
%"42" = load float, ptr addrspace(5) %"35", align 4
%"41" = fpext float %"42" to double
store double %"41", ptr addrspace(5) %"36", align 8
%"43" = load i64, ptr addrspace(5) %"34", align 8
%"44" = load double, ptr addrspace(5) %"36", align 8
%"46" = inttoptr i64 %"43" to ptr
store double %"44", ptr %"46", align 8
"33": ; preds = %1
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"48" = inttoptr i64 %"43" to ptr addrspace(1)
%"42" = load float, ptr addrspace(1) %"48", align 4
store float %"42", ptr addrspace(5) %"38", align 4
%"45" = load float, ptr addrspace(5) %"38", align 4
%"44" = fpext float %"45" to double
store double %"44", ptr addrspace(5) %"39", align 8
%"46" = load i64, ptr addrspace(5) %"37", align 8
%"47" = load double, ptr addrspace(5) %"39", align 8
%"49" = inttoptr i64 %"46" to ptr
store double %"47", ptr %"49", align 8
ret void
}

48
ptx/src/test/ll/cvt_rn_f16x2_e4m3x2.ll
View file

@ -1,35 +1,35 @@
declare hidden i32 @__zluda_ptx_impl_cvt_rn_f16x2_e4m3x2(i16) #0
define amdgpu_kernel void @cvt_rn_f16x2_e4m3x2(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #1 {
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i16, align 2, addrspace(5)
%"36" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @cvt_rn_f16x2_e4m3x2(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #1 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i16, align 2, addrspace(5)
%"39" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"30"
br label %"33"
"30": ; preds = %1
%"37" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"37", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"38", ptr addrspace(5) %"34", align 8
%"40" = load i64, ptr addrspace(5) %"33", align 8
%"45" = inttoptr i64 %"40" to ptr
%"39" = load i16, ptr %"45", align 2
store i16 %"39", ptr addrspace(5) %"35", align 2
%"42" = load i16, ptr addrspace(5) %"35", align 2
%"49" = call i32 @__zluda_ptx_impl_cvt_rn_f16x2_e4m3x2(i16 %"42")
%"46" = bitcast i32 %"49" to <2 x half>
%"41" = bitcast <2 x half> %"46" to i32
store i32 %"41", ptr addrspace(5) %"36", align 4
%"43" = load i64, ptr addrspace(5) %"34", align 8
%"44" = load i32, ptr addrspace(5) %"36", align 4
"33": ; preds = %1
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"48" = inttoptr i64 %"43" to ptr
store i32 %"44", ptr %"48", align 4
%"42" = load i16, ptr %"48", align 2
store i16 %"42", ptr addrspace(5) %"38", align 2
%"45" = load i16, ptr addrspace(5) %"38", align 2
%"52" = call i32 @__zluda_ptx_impl_cvt_rn_f16x2_e4m3x2(i16 %"45")
%"49" = bitcast i32 %"52" to <2 x half>
%"44" = bitcast <2 x half> %"49" to i32
store i32 %"44", ptr addrspace(5) %"39", align 4
%"46" = load i64, ptr addrspace(5) %"37", align 8
%"47" = load i32, ptr addrspace(5) %"39", align 4
%"51" = inttoptr i64 %"46" to ptr
store i32 %"47", ptr %"51", align 4
ret void
}
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="dynamic" "denormal-fp-math-f32"="dynamic" "no-trapping-math"="true" "uniform-work-group-size"="true" }
attributes #1 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="ieee" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }
attributes #1 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="ieee" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }

48
ptx/src/test/ll/cvt_rn_f16x2_e5m2x2.ll
View file

@ -1,35 +1,35 @@
declare hidden i32 @__zluda_ptx_impl_cvt_rn_f16x2_e5m2x2(i16) #0
define amdgpu_kernel void @cvt_rn_f16x2_e5m2x2(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #1 {
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i16, align 2, addrspace(5)
%"36" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @cvt_rn_f16x2_e5m2x2(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #1 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i16, align 2, addrspace(5)
%"39" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"30"
br label %"33"
"30": ; preds = %1
%"37" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"37", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"38", ptr addrspace(5) %"34", align 8
%"40" = load i64, ptr addrspace(5) %"33", align 8
%"45" = inttoptr i64 %"40" to ptr
%"39" = load i16, ptr %"45", align 2
store i16 %"39", ptr addrspace(5) %"35", align 2
%"42" = load i16, ptr addrspace(5) %"35", align 2
%"49" = call i32 @__zluda_ptx_impl_cvt_rn_f16x2_e5m2x2(i16 %"42")
%"46" = bitcast i32 %"49" to <2 x half>
%"41" = bitcast <2 x half> %"46" to i32
store i32 %"41", ptr addrspace(5) %"36", align 4
%"43" = load i64, ptr addrspace(5) %"34", align 8
%"44" = load i32, ptr addrspace(5) %"36", align 4
"33": ; preds = %1
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"48" = inttoptr i64 %"43" to ptr
store i32 %"44", ptr %"48", align 4
%"42" = load i16, ptr %"48", align 2
store i16 %"42", ptr addrspace(5) %"38", align 2
%"45" = load i16, ptr addrspace(5) %"38", align 2
%"52" = call i32 @__zluda_ptx_impl_cvt_rn_f16x2_e5m2x2(i16 %"45")
%"49" = bitcast i32 %"52" to <2 x half>
%"44" = bitcast <2 x half> %"49" to i32
store i32 %"44", ptr addrspace(5) %"39", align 4
%"46" = load i64, ptr addrspace(5) %"37", align 8
%"47" = load i32, ptr addrspace(5) %"39", align 4
%"51" = inttoptr i64 %"46" to ptr
store i32 %"47", ptr %"51", align 4
ret void
}
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="dynamic" "denormal-fp-math-f32"="dynamic" "no-trapping-math"="true" "uniform-work-group-size"="true" }
attributes #1 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="ieee" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }
attributes #1 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="ieee" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }

60
ptx/src/test/ll/cvt_rn_satfinite_e4m3x2_f32.ll
View file

@ -1,40 +1,40 @@
declare hidden i16 @__zluda_ptx_impl_cvt_rn_satfinite_e4m3x2_f32(float, float) #0
define amdgpu_kernel void @cvt_rn_satfinite_e4m3x2_f32(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #1 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca float, align 4, addrspace(5)
%"39" = alloca float, align 4, addrspace(5)
%"40" = alloca i16, align 2, addrspace(5)
define amdgpu_kernel void @cvt_rn_satfinite_e4m3x2_f32(ptr addrspace(4) byref(i64) %"37", ptr addrspace(4) byref(i64) %"38") #1 {
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca float, align 4, addrspace(5)
%"42" = alloca float, align 4, addrspace(5)
%"43" = alloca i16, align 2, addrspace(5)
br label %1
1: ; preds = %0
br label %"33"
br label %"36"
"33": ; preds = %1
%"41" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"41", ptr addrspace(5) %"36", align 8
%"42" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"42", ptr addrspace(5) %"37", align 8
%"44" = load i64, ptr addrspace(5) %"36", align 8
%"52" = inttoptr i64 %"44" to ptr
%"43" = load float, ptr %"52", align 4
store float %"43", ptr addrspace(5) %"38", align 4
%"45" = load i64, ptr addrspace(5) %"36", align 8
%"53" = inttoptr i64 %"45" to ptr
%"32" = getelementptr inbounds i8, ptr %"53", i64 4
%"46" = load float, ptr %"32", align 4
store float %"46", ptr addrspace(5) %"39", align 4
%"48" = load float, ptr addrspace(5) %"38", align 4
%"49" = load float, ptr addrspace(5) %"39", align 4
%"54" = call i16 @__zluda_ptx_impl_cvt_rn_satfinite_e4m3x2_f32(float %"48", float %"49")
store i16 %"54", ptr addrspace(5) %"40", align 2
%"50" = load i64, ptr addrspace(5) %"37", align 8
%"51" = load i16, ptr addrspace(5) %"40", align 2
%"55" = inttoptr i64 %"50" to ptr
store i16 %"51", ptr %"55", align 2
"36": ; preds = %1
%"44" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"44", ptr addrspace(5) %"39", align 8
%"45" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"45", ptr addrspace(5) %"40", align 8
%"47" = load i64, ptr addrspace(5) %"39", align 8
%"55" = inttoptr i64 %"47" to ptr
%"46" = load float, ptr %"55", align 4
store float %"46", ptr addrspace(5) %"41", align 4
%"48" = load i64, ptr addrspace(5) %"39", align 8
%"56" = inttoptr i64 %"48" to ptr
%"35" = getelementptr inbounds i8, ptr %"56", i64 4
%"49" = load float, ptr %"35", align 4
store float %"49", ptr addrspace(5) %"42", align 4
%"51" = load float, ptr addrspace(5) %"41", align 4
%"52" = load float, ptr addrspace(5) %"42", align 4
%"57" = call i16 @__zluda_ptx_impl_cvt_rn_satfinite_e4m3x2_f32(float %"51", float %"52")
store i16 %"57", ptr addrspace(5) %"43", align 2
%"53" = load i64, ptr addrspace(5) %"40", align 8
%"54" = load i16, ptr addrspace(5) %"43", align 2
%"58" = inttoptr i64 %"53" to ptr
store i16 %"54", ptr %"58", align 2
ret void
}
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="dynamic" "denormal-fp-math-f32"="dynamic" "no-trapping-math"="true" "uniform-work-group-size"="true" }
attributes #1 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="ieee" "denormal-fp-math-f32"="ieee" "no-trapping-math"="true" "uniform-work-group-size"="true" }
attributes #1 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="ieee" "denormal-fp-math-f32"="ieee" "no-trapping-math"="true" "uniform-work-group-size"="true" }

60
ptx/src/test/ll/cvt_rn_satfinite_e5m2x2_f32.ll
View file

@ -1,40 +1,40 @@
declare hidden i16 @__zluda_ptx_impl_cvt_rn_satfinite_e5m2x2_f32(float, float) #0
define amdgpu_kernel void @cvt_rn_satfinite_e5m2x2_f32(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #1 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca float, align 4, addrspace(5)
%"39" = alloca float, align 4, addrspace(5)
%"40" = alloca i16, align 2, addrspace(5)
define amdgpu_kernel void @cvt_rn_satfinite_e5m2x2_f32(ptr addrspace(4) byref(i64) %"37", ptr addrspace(4) byref(i64) %"38") #1 {
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca float, align 4, addrspace(5)
%"42" = alloca float, align 4, addrspace(5)
%"43" = alloca i16, align 2, addrspace(5)
br label %1
1: ; preds = %0
br label %"33"
br label %"36"
"33": ; preds = %1
%"41" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"41", ptr addrspace(5) %"36", align 8
%"42" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"42", ptr addrspace(5) %"37", align 8
%"44" = load i64, ptr addrspace(5) %"36", align 8
%"52" = inttoptr i64 %"44" to ptr
%"43" = load float, ptr %"52", align 4
store float %"43", ptr addrspace(5) %"38", align 4
%"45" = load i64, ptr addrspace(5) %"36", align 8
%"53" = inttoptr i64 %"45" to ptr
%"32" = getelementptr inbounds i8, ptr %"53", i64 4
%"46" = load float, ptr %"32", align 4
store float %"46", ptr addrspace(5) %"39", align 4
%"48" = load float, ptr addrspace(5) %"38", align 4
%"49" = load float, ptr addrspace(5) %"39", align 4
%"54" = call i16 @__zluda_ptx_impl_cvt_rn_satfinite_e5m2x2_f32(float %"48", float %"49")
store i16 %"54", ptr addrspace(5) %"40", align 2
%"50" = load i64, ptr addrspace(5) %"37", align 8
%"51" = load i16, ptr addrspace(5) %"40", align 2
%"55" = inttoptr i64 %"50" to ptr
store i16 %"51", ptr %"55", align 2
"36": ; preds = %1
%"44" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"44", ptr addrspace(5) %"39", align 8
%"45" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"45", ptr addrspace(5) %"40", align 8
%"47" = load i64, ptr addrspace(5) %"39", align 8
%"55" = inttoptr i64 %"47" to ptr
%"46" = load float, ptr %"55", align 4
store float %"46", ptr addrspace(5) %"41", align 4
%"48" = load i64, ptr addrspace(5) %"39", align 8
%"56" = inttoptr i64 %"48" to ptr
%"35" = getelementptr inbounds i8, ptr %"56", i64 4
%"49" = load float, ptr %"35", align 4
store float %"49", ptr addrspace(5) %"42", align 4
%"51" = load float, ptr addrspace(5) %"41", align 4
%"52" = load float, ptr addrspace(5) %"42", align 4
%"57" = call i16 @__zluda_ptx_impl_cvt_rn_satfinite_e5m2x2_f32(float %"51", float %"52")
store i16 %"57", ptr addrspace(5) %"43", align 2
%"53" = load i64, ptr addrspace(5) %"40", align 8
%"54" = load i16, ptr addrspace(5) %"43", align 2
%"58" = inttoptr i64 %"53" to ptr
store i16 %"54", ptr %"58", align 2
ret void
}
attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="dynamic" "denormal-fp-math-f32"="dynamic" "no-trapping-math"="true" "uniform-work-group-size"="true" }
attributes #1 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="ieee" "denormal-fp-math-f32"="ieee" "no-trapping-math"="true" "uniform-work-group-size"="true" }
attributes #1 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="ieee" "denormal-fp-math-f32"="ieee" "no-trapping-math"="true" "uniform-work-group-size"="true" }

70
ptx/src/test/ll/cvt_rni.ll
View file

@ -1,42 +1,42 @@
define amdgpu_kernel void @cvt_rni(ptr addrspace(4) byref(i64) %"35", ptr addrspace(4) byref(i64) %"36") #0 {
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca float, align 4, addrspace(5)
%"40" = alloca float, align 4, addrspace(5)
define amdgpu_kernel void @cvt_rni(ptr addrspace(4) byref(i64) %"38", ptr addrspace(4) byref(i64) %"39") #0 {
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca float, align 4, addrspace(5)
%"43" = alloca float, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"34"
br label %"37"
"34": ; preds = %1
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"44" = load i64, ptr addrspace(5) %"37", align 8
%"55" = inttoptr i64 %"44" to ptr
%"43" = load float, ptr %"55", align 4
store float %"43", ptr addrspace(5) %"39", align 4
%"45" = load i64, ptr addrspace(5) %"37", align 8
%"56" = inttoptr i64 %"45" to ptr
%"31" = getelementptr inbounds i8, ptr %"56", i64 4
%"46" = load float, ptr %"31", align 4
store float %"46", ptr addrspace(5) %"40", align 4
%"48" = load float, ptr addrspace(5) %"39", align 4
%2 = call float @llvm.roundeven.f32(float %"48")
store float %2, ptr addrspace(5) %"39", align 4
%"50" = load float, ptr addrspace(5) %"40", align 4
%3 = call float @llvm.roundeven.f32(float %"50")
store float %3, ptr addrspace(5) %"40", align 4
%"51" = load i64, ptr addrspace(5) %"38", align 8
%"52" = load float, ptr addrspace(5) %"39", align 4
%"57" = inttoptr i64 %"51" to ptr
store float %"52", ptr %"57", align 4
%"53" = load i64, ptr addrspace(5) %"38", align 8
%"58" = inttoptr i64 %"53" to ptr
%"33" = getelementptr inbounds i8, ptr %"58", i64 4
%"54" = load float, ptr addrspace(5) %"40", align 4
store float %"54", ptr %"33", align 4
"37": ; preds = %1
%"44" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"44", ptr addrspace(5) %"40", align 8
%"45" = load i64, ptr addrspace(4) %"39", align 8
store i64 %"45", ptr addrspace(5) %"41", align 8
%"47" = load i64, ptr addrspace(5) %"40", align 8
%"58" = inttoptr i64 %"47" to ptr
%"46" = load float, ptr %"58", align 4
store float %"46", ptr addrspace(5) %"42", align 4
%"48" = load i64, ptr addrspace(5) %"40", align 8
%"59" = inttoptr i64 %"48" to ptr
%"34" = getelementptr inbounds i8, ptr %"59", i64 4
%"49" = load float, ptr %"34", align 4
store float %"49", ptr addrspace(5) %"43", align 4
%"51" = load float, ptr addrspace(5) %"42", align 4
%2 = call float @llvm.roundeven.f32(float %"51")
store float %2, ptr addrspace(5) %"42", align 4
%"53" = load float, ptr addrspace(5) %"43", align 4
%3 = call float @llvm.roundeven.f32(float %"53")
store float %3, ptr addrspace(5) %"43", align 4
%"54" = load i64, ptr addrspace(5) %"41", align 8
%"55" = load float, ptr addrspace(5) %"42", align 4
%"60" = inttoptr i64 %"54" to ptr
store float %"55", ptr %"60", align 4
%"56" = load i64, ptr addrspace(5) %"41", align 8
%"61" = inttoptr i64 %"56" to ptr
%"36" = getelementptr inbounds i8, ptr %"61", i64 4
%"57" = load float, ptr addrspace(5) %"43", align 4
store float %"57", ptr %"36", align 4
ret void
}

46
ptx/src/test/ll/cvt_rni_u16_f32.ll
View file

@ -1,30 +1,30 @@
define amdgpu_kernel void @cvt_rni_u16_f32(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #0 {
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca float, align 4, addrspace(5)
%"36" = alloca i16, align 2, addrspace(5)
define amdgpu_kernel void @cvt_rni_u16_f32(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca float, align 4, addrspace(5)
%"39" = alloca i16, align 2, addrspace(5)
br label %1
1: ; preds = %0
br label %"30"
br label %"33"
"30": ; preds = %1
%"37" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"37", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"38", ptr addrspace(5) %"34", align 8
%"40" = load i64, ptr addrspace(5) %"33", align 8
%"45" = inttoptr i64 %"40" to ptr addrspace(1)
%"39" = load float, ptr addrspace(1) %"45", align 4
store float %"39", ptr addrspace(5) %"35", align 4
%"42" = load float, ptr addrspace(5) %"35", align 4
%2 = call float @llvm.roundeven.f32(float %"42")
%"41" = call i16 @llvm.fptoui.sat.i16.f32(float %2)
store i16 %"41", ptr addrspace(5) %"36", align 2
%"43" = load i64, ptr addrspace(5) %"34", align 8
%"44" = load i16, ptr addrspace(5) %"36", align 2
%"46" = inttoptr i64 %"43" to ptr
store i16 %"44", ptr %"46", align 2
"33": ; preds = %1
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"48" = inttoptr i64 %"43" to ptr addrspace(1)
%"42" = load float, ptr addrspace(1) %"48", align 4
store float %"42", ptr addrspace(5) %"38", align 4
%"45" = load float, ptr addrspace(5) %"38", align 4
%2 = call float @llvm.roundeven.f32(float %"45")
%"44" = call i16 @llvm.fptoui.sat.i16.f32(float %2)
store i16 %"44", ptr addrspace(5) %"39", align 2
%"46" = load i64, ptr addrspace(5) %"37", align 8
%"47" = load i16, ptr addrspace(5) %"39", align 2
%"49" = inttoptr i64 %"46" to ptr
store i16 %"47", ptr %"49", align 2
ret void
}

70
ptx/src/test/ll/cvt_rzi.ll
View file

@ -1,42 +1,42 @@
define amdgpu_kernel void @cvt_rzi(ptr addrspace(4) byref(i64) %"35", ptr addrspace(4) byref(i64) %"36") #0 {
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca float, align 4, addrspace(5)
%"40" = alloca float, align 4, addrspace(5)
define amdgpu_kernel void @cvt_rzi(ptr addrspace(4) byref(i64) %"38", ptr addrspace(4) byref(i64) %"39") #0 {
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca float, align 4, addrspace(5)
%"43" = alloca float, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"34"
br label %"37"
"34": ; preds = %1
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"44" = load i64, ptr addrspace(5) %"37", align 8
%"55" = inttoptr i64 %"44" to ptr
%"43" = load float, ptr %"55", align 4
store float %"43", ptr addrspace(5) %"39", align 4
%"45" = load i64, ptr addrspace(5) %"37", align 8
%"56" = inttoptr i64 %"45" to ptr
%"31" = getelementptr inbounds i8, ptr %"56", i64 4
%"46" = load float, ptr %"31", align 4
store float %"46", ptr addrspace(5) %"40", align 4
%"48" = load float, ptr addrspace(5) %"39", align 4
%2 = call float @llvm.trunc.f32(float %"48")
store float %2, ptr addrspace(5) %"39", align 4
%"50" = load float, ptr addrspace(5) %"40", align 4
%3 = call float @llvm.trunc.f32(float %"50")
store float %3, ptr addrspace(5) %"40", align 4
%"51" = load i64, ptr addrspace(5) %"38", align 8
%"52" = load float, ptr addrspace(5) %"39", align 4
%"57" = inttoptr i64 %"51" to ptr
store float %"52", ptr %"57", align 4
%"53" = load i64, ptr addrspace(5) %"38", align 8
%"58" = inttoptr i64 %"53" to ptr
%"33" = getelementptr inbounds i8, ptr %"58", i64 4
%"54" = load float, ptr addrspace(5) %"40", align 4
store float %"54", ptr %"33", align 4
"37": ; preds = %1
%"44" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"44", ptr addrspace(5) %"40", align 8
%"45" = load i64, ptr addrspace(4) %"39", align 8
store i64 %"45", ptr addrspace(5) %"41", align 8
%"47" = load i64, ptr addrspace(5) %"40", align 8
%"58" = inttoptr i64 %"47" to ptr
%"46" = load float, ptr %"58", align 4
store float %"46", ptr addrspace(5) %"42", align 4
%"48" = load i64, ptr addrspace(5) %"40", align 8
%"59" = inttoptr i64 %"48" to ptr
%"34" = getelementptr inbounds i8, ptr %"59", i64 4
%"49" = load float, ptr %"34", align 4
store float %"49", ptr addrspace(5) %"43", align 4
%"51" = load float, ptr addrspace(5) %"42", align 4
%2 = call float @llvm.trunc.f32(float %"51")
store float %2, ptr addrspace(5) %"42", align 4
%"53" = load float, ptr addrspace(5) %"43", align 4
%3 = call float @llvm.trunc.f32(float %"53")
store float %3, ptr addrspace(5) %"43", align 4
%"54" = load i64, ptr addrspace(5) %"41", align 8
%"55" = load float, ptr addrspace(5) %"42", align 4
%"60" = inttoptr i64 %"54" to ptr
store float %"55", ptr %"60", align 4
%"56" = load i64, ptr addrspace(5) %"41", align 8
%"61" = inttoptr i64 %"56" to ptr
%"36" = getelementptr inbounds i8, ptr %"61", i64 4
%"57" = load float, ptr addrspace(5) %"43", align 4
store float %"57", ptr %"36", align 4
ret void
}

48
ptx/src/test/ll/cvt_s16_s8.ll
View file

@ -1,31 +1,31 @@
define amdgpu_kernel void @cvt_s16_s8(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #0 {
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i32, align 4, addrspace(5)
%"36" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @cvt_s16_s8(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i32, align 4, addrspace(5)
%"39" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"30"
br label %"33"
"30": ; preds = %1
%"37" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"37", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"38", ptr addrspace(5) %"34", align 8
%"40" = load i64, ptr addrspace(5) %"33", align 8
%"45" = inttoptr i64 %"40" to ptr addrspace(1)
%"39" = load i32, ptr addrspace(1) %"45", align 4
store i32 %"39", ptr addrspace(5) %"36", align 4
%"42" = load i32, ptr addrspace(5) %"36", align 4
%2 = trunc i32 %"42" to i8
%"46" = sext i8 %2 to i16
%"41" = sext i16 %"46" to i32
store i32 %"41", ptr addrspace(5) %"35", align 4
%"43" = load i64, ptr addrspace(5) %"34", align 8
%"44" = load i32, ptr addrspace(5) %"35", align 4
%"48" = inttoptr i64 %"43" to ptr
store i32 %"44", ptr %"48", align 4
"33": ; preds = %1
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"48" = inttoptr i64 %"43" to ptr addrspace(1)
%"42" = load i32, ptr addrspace(1) %"48", align 4
store i32 %"42", ptr addrspace(5) %"39", align 4
%"45" = load i32, ptr addrspace(5) %"39", align 4
%2 = trunc i32 %"45" to i8
%"49" = sext i8 %2 to i16
%"44" = sext i16 %"49" to i32
store i32 %"44", ptr addrspace(5) %"38", align 4
%"46" = load i64, ptr addrspace(5) %"37", align 8
%"47" = load i32, ptr addrspace(5) %"38", align 4
%"51" = inttoptr i64 %"46" to ptr
store i32 %"47", ptr %"51", align 4
ret void
}

80
ptx/src/test/ll/cvt_s32_f32.ll
View file

@ -1,50 +1,50 @@
define amdgpu_kernel void @cvt_s32_f32(ptr addrspace(4) byref(i64) %"35", ptr addrspace(4) byref(i64) %"36") #0 {
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i32, align 4, addrspace(5)
%"40" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @cvt_s32_f32(ptr addrspace(4) byref(i64) %"38", ptr addrspace(4) byref(i64) %"39") #0 {
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i32, align 4, addrspace(5)
%"43" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"34"
br label %"37"
"34": ; preds = %1
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"44" = load i64, ptr addrspace(5) %"37", align 8
%"56" = inttoptr i64 %"44" to ptr
%"55" = load float, ptr %"56", align 4
%"43" = bitcast float %"55" to i32
store i32 %"43", ptr addrspace(5) %"39", align 4
%"45" = load i64, ptr addrspace(5) %"37", align 8
%"57" = inttoptr i64 %"45" to ptr
%"31" = getelementptr inbounds i8, ptr %"57", i64 4
%"58" = load float, ptr %"31", align 4
"37": ; preds = %1
%"44" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"44", ptr addrspace(5) %"40", align 8
%"45" = load i64, ptr addrspace(4) %"39", align 8
store i64 %"45", ptr addrspace(5) %"41", align 8
%"47" = load i64, ptr addrspace(5) %"40", align 8
%"59" = inttoptr i64 %"47" to ptr
%"58" = load float, ptr %"59", align 4
%"46" = bitcast float %"58" to i32
store i32 %"46", ptr addrspace(5) %"40", align 4
%"48" = load i32, ptr addrspace(5) %"39", align 4
%"60" = bitcast i32 %"48" to float
%2 = call float @llvm.ceil.f32(float %"60")
store i32 %"46", ptr addrspace(5) %"42", align 4
%"48" = load i64, ptr addrspace(5) %"40", align 8
%"60" = inttoptr i64 %"48" to ptr
%"34" = getelementptr inbounds i8, ptr %"60", i64 4
%"61" = load float, ptr %"34", align 4
%"49" = bitcast float %"61" to i32
store i32 %"49", ptr addrspace(5) %"43", align 4
%"51" = load i32, ptr addrspace(5) %"42", align 4
%"63" = bitcast i32 %"51" to float
%2 = call float @llvm.ceil.f32(float %"63")
%3 = fptosi float %2 to i32
%"59" = freeze i32 %3
store i32 %"59", ptr addrspace(5) %"39", align 4
%"50" = load i32, ptr addrspace(5) %"40", align 4
%"62" = bitcast i32 %"50" to float
%4 = call float @llvm.ceil.f32(float %"62")
%"62" = freeze i32 %3
store i32 %"62", ptr addrspace(5) %"42", align 4
%"53" = load i32, ptr addrspace(5) %"43", align 4
%"65" = bitcast i32 %"53" to float
%4 = call float @llvm.ceil.f32(float %"65")
%5 = fptosi float %4 to i32
%"61" = freeze i32 %5
store i32 %"61", ptr addrspace(5) %"40", align 4
%"51" = load i64, ptr addrspace(5) %"38", align 8
%"52" = load i32, ptr addrspace(5) %"39", align 4
%"63" = inttoptr i64 %"51" to ptr addrspace(1)
store i32 %"52", ptr addrspace(1) %"63", align 4
%"53" = load i64, ptr addrspace(5) %"38", align 8
%"65" = inttoptr i64 %"53" to ptr addrspace(1)
%"33" = getelementptr inbounds i8, ptr addrspace(1) %"65", i64 4
%"54" = load i32, ptr addrspace(5) %"40", align 4
store i32 %"54", ptr addrspace(1) %"33", align 4
%"64" = freeze i32 %5
store i32 %"64", ptr addrspace(5) %"43", align 4
%"54" = load i64, ptr addrspace(5) %"41", align 8
%"55" = load i32, ptr addrspace(5) %"42", align 4
%"66" = inttoptr i64 %"54" to ptr addrspace(1)
store i32 %"55", ptr addrspace(1) %"66", align 4
%"56" = load i64, ptr addrspace(5) %"41", align 8
%"68" = inttoptr i64 %"56" to ptr addrspace(1)
%"36" = getelementptr inbounds i8, ptr addrspace(1) %"68", i64 4
%"57" = load i32, ptr addrspace(5) %"43", align 4
store i32 %"57", ptr addrspace(1) %"36", align 4
ret void
}

42
ptx/src/test/ll/cvt_s64_s32.ll
View file

@ -1,29 +1,29 @@
define amdgpu_kernel void @cvt_s64_s32(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #0 {
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @cvt_s64_s32(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i32, align 4, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"30"
br label %"33"
"30": ; preds = %1
%"37" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"37", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"38", ptr addrspace(5) %"34", align 8
%"40" = load i64, ptr addrspace(5) %"33", align 8
%"46" = inttoptr i64 %"40" to ptr
%"45" = load i32, ptr %"46", align 4
store i32 %"45", ptr addrspace(5) %"35", align 4
%"42" = load i32, ptr addrspace(5) %"35", align 4
%"41" = sext i32 %"42" to i64
store i64 %"41", ptr addrspace(5) %"36", align 8
%"43" = load i64, ptr addrspace(5) %"34", align 8
%"44" = load i64, ptr addrspace(5) %"36", align 8
%"47" = inttoptr i64 %"43" to ptr
store i64 %"44", ptr %"47", align 8
"33": ; preds = %1
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"49" = inttoptr i64 %"43" to ptr
%"48" = load i32, ptr %"49", align 4
store i32 %"48", ptr addrspace(5) %"38", align 4
%"45" = load i32, ptr addrspace(5) %"38", align 4
%"44" = sext i32 %"45" to i64
store i64 %"44", ptr addrspace(5) %"39", align 8
%"46" = load i64, ptr addrspace(5) %"37", align 8
%"47" = load i64, ptr addrspace(5) %"39", align 8
%"50" = inttoptr i64 %"46" to ptr
store i64 %"47", ptr %"50", align 8
ret void
}

50
ptx/src/test/ll/cvt_sat_s_u.ll
View file

@ -1,33 +1,33 @@
define amdgpu_kernel void @cvt_sat_s_u(ptr addrspace(4) byref(i64) %"32", ptr addrspace(4) byref(i64) %"33") #0 {
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i32, align 4, addrspace(5)
%"37" = alloca i32, align 4, addrspace(5)
%"38" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @cvt_sat_s_u(ptr addrspace(4) byref(i64) %"35", ptr addrspace(4) byref(i64) %"36") #0 {
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i32, align 4, addrspace(5)
%"40" = alloca i32, align 4, addrspace(5)
%"41" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"31"
br label %"34"
"31": ; preds = %1
%"39" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"39", ptr addrspace(5) %"34", align 8
%"40" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"40", ptr addrspace(5) %"35", align 8
%"42" = load i64, ptr addrspace(5) %"34", align 8
%"49" = inttoptr i64 %"42" to ptr
%"41" = load i32, ptr %"49", align 4
store i32 %"41", ptr addrspace(5) %"36", align 4
%"44" = load i32, ptr addrspace(5) %"36", align 4
%2 = call i32 @llvm.smax.i32(i32 %"44", i32 0)
"34": ; preds = %1
%"42" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"42", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"43", ptr addrspace(5) %"38", align 8
%"45" = load i64, ptr addrspace(5) %"37", align 8
%"52" = inttoptr i64 %"45" to ptr
%"44" = load i32, ptr %"52", align 4
store i32 %"44", ptr addrspace(5) %"39", align 4
%"47" = load i32, ptr addrspace(5) %"39", align 4
%2 = call i32 @llvm.smax.i32(i32 %"47", i32 0)
%3 = call i32 @llvm.smin.i32(i32 %2, i32 2147483647)
store i32 %3, ptr addrspace(5) %"37", align 4
%"46" = load i32, ptr addrspace(5) %"37", align 4
store i32 %"46", ptr addrspace(5) %"38", align 4
%"47" = load i64, ptr addrspace(5) %"35", align 8
%"48" = load i32, ptr addrspace(5) %"38", align 4
%"50" = inttoptr i64 %"47" to ptr
store i32 %"48", ptr %"50", align 4
store i32 %3, ptr addrspace(5) %"40", align 4
%"49" = load i32, ptr addrspace(5) %"40", align 4
store i32 %"49", ptr addrspace(5) %"41", align 4
%"50" = load i64, ptr addrspace(5) %"38", align 8
%"51" = load i32, ptr addrspace(5) %"41", align 4
%"53" = inttoptr i64 %"50" to ptr
store i32 %"51", ptr %"53", align 4
ret void
}

52
ptx/src/test/ll/cvta.ll
View file

@ -1,33 +1,33 @@
define amdgpu_kernel void @cvta(ptr addrspace(4) byref(i64) %"30", ptr addrspace(4) byref(i64) %"31") #0 {
%"32" = alloca i64, align 8, addrspace(5)
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca float, align 4, addrspace(5)
define amdgpu_kernel void @cvta(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca float, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"29"
br label %"32"
"29": ; preds = %1
%"35" = load i64, ptr addrspace(4) %"30", align 8
store i64 %"35", ptr addrspace(5) %"32", align 8
%"36" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"36", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(5) %"32", align 8
%2 = inttoptr i64 %"38" to ptr
%"45" = addrspacecast ptr %2 to ptr addrspace(1)
store ptr addrspace(1) %"45", ptr addrspace(5) %"32", align 8
%"40" = load i64, ptr addrspace(5) %"33", align 8
%3 = inttoptr i64 %"40" to ptr
%"47" = addrspacecast ptr %3 to ptr addrspace(1)
store ptr addrspace(1) %"47", ptr addrspace(5) %"33", align 8
%"42" = load i64, ptr addrspace(5) %"32", align 8
%"49" = inttoptr i64 %"42" to ptr addrspace(1)
%"41" = load float, ptr addrspace(1) %"49", align 4
store float %"41", ptr addrspace(5) %"34", align 4
%"43" = load i64, ptr addrspace(5) %"33", align 8
%"44" = load float, ptr addrspace(5) %"34", align 4
%"50" = inttoptr i64 %"43" to ptr addrspace(1)
store float %"44", ptr addrspace(1) %"50", align 4
"32": ; preds = %1
%"38" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"38", ptr addrspace(5) %"35", align 8
%"39" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"39", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(5) %"35", align 8
%2 = inttoptr i64 %"41" to ptr
%"48" = addrspacecast ptr %2 to ptr addrspace(1)
store ptr addrspace(1) %"48", ptr addrspace(5) %"35", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%3 = inttoptr i64 %"43" to ptr
%"50" = addrspacecast ptr %3 to ptr addrspace(1)
store ptr addrspace(1) %"50", ptr addrspace(5) %"36", align 8
%"45" = load i64, ptr addrspace(5) %"35", align 8
%"52" = inttoptr i64 %"45" to ptr addrspace(1)
%"44" = load float, ptr addrspace(1) %"52", align 4
store float %"44", ptr addrspace(5) %"37", align 4
%"46" = load i64, ptr addrspace(5) %"36", align 8
%"47" = load float, ptr addrspace(5) %"37", align 4
%"53" = inttoptr i64 %"46" to ptr addrspace(1)
store float %"47", ptr addrspace(1) %"53", align 4
ret void
}

56
ptx/src/test/ll/div_approx.ll
View file

@ -1,35 +1,35 @@
define amdgpu_kernel void @div_approx(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca float, align 4, addrspace(5)
%"38" = alloca float, align 4, addrspace(5)
define amdgpu_kernel void @div_approx(ptr addrspace(4) byref(i64) %"36", ptr addrspace(4) byref(i64) %"37") #0 {
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca float, align 4, addrspace(5)
%"41" = alloca float, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"32"
br label %"35"
"32": ; preds = %1
%"39" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"39", ptr addrspace(5) %"35", align 8
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"42" = load i64, ptr addrspace(5) %"35", align 8
%"50" = inttoptr i64 %"42" to ptr
%"41" = load float, ptr %"50", align 4
store float %"41", ptr addrspace(5) %"37", align 4
%"43" = load i64, ptr addrspace(5) %"35", align 8
%"51" = inttoptr i64 %"43" to ptr
%"31" = getelementptr inbounds i8, ptr %"51", i64 4
%"44" = load float, ptr %"31", align 4
store float %"44", ptr addrspace(5) %"38", align 4
%"46" = load float, ptr addrspace(5) %"37", align 4
%"47" = load float, ptr addrspace(5) %"38", align 4
%"45" = fdiv arcp afn float %"46", %"47"
store float %"45", ptr addrspace(5) %"37", align 4
%"48" = load i64, ptr addrspace(5) %"36", align 8
%"49" = load float, ptr addrspace(5) %"37", align 4
%"52" = inttoptr i64 %"48" to ptr
store float %"49", ptr %"52", align 4
"35": ; preds = %1
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"43" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"45" = load i64, ptr addrspace(5) %"38", align 8
%"53" = inttoptr i64 %"45" to ptr
%"44" = load float, ptr %"53", align 4
store float %"44", ptr addrspace(5) %"40", align 4
%"46" = load i64, ptr addrspace(5) %"38", align 8
%"54" = inttoptr i64 %"46" to ptr
%"34" = getelementptr inbounds i8, ptr %"54", i64 4
%"47" = load float, ptr %"34", align 4
store float %"47", ptr addrspace(5) %"41", align 4
%"49" = load float, ptr addrspace(5) %"40", align 4
%"50" = load float, ptr addrspace(5) %"41", align 4
%"48" = fdiv arcp afn float %"49", %"50"
store float %"48", ptr addrspace(5) %"40", align 4
%"51" = load i64, ptr addrspace(5) %"39", align 8
%"52" = load float, ptr addrspace(5) %"40", align 4
%"55" = inttoptr i64 %"51" to ptr
store float %"52", ptr %"55", align 4
ret void
}

102
ptx/src/test/ll/div_ftz.ll
View file

@ -4,65 +4,65 @@ declare hidden %struct.f32.f32.f32.i8 @__zluda_ptx_impl_div_f32_part1(float, flo
declare hidden float @__zluda_ptx_impl_div_f32_part2(float, float, float, float, float, i8) #0
define amdgpu_kernel void @div_ftz(ptr addrspace(4) byref(i64) %"63", ptr addrspace(4) byref(i64) %"64") #1 {
%"65" = alloca i64, align 8, addrspace(5)
%"66" = alloca i64, align 8, addrspace(5)
%"67" = alloca float, align 4, addrspace(5)
%"68" = alloca float, align 4, addrspace(5)
%"69" = alloca float, align 4, addrspace(5)
define amdgpu_kernel void @div_ftz(ptr addrspace(4) byref(i64) %"66", ptr addrspace(4) byref(i64) %"67") #1 {
%"68" = alloca i64, align 8, addrspace(5)
%"69" = alloca i64, align 8, addrspace(5)
%"70" = alloca float, align 4, addrspace(5)
%"71" = alloca float, align 4, addrspace(5)
%"72" = alloca float, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"54"
"54": ; preds = %1
%"70" = load i64, ptr addrspace(4) %"63", align 8
store i64 %"70", ptr addrspace(5) %"65", align 8
%"71" = load i64, ptr addrspace(4) %"64", align 8
store i64 %"71", ptr addrspace(5) %"66", align 8
%"73" = load i64, ptr addrspace(5) %"65", align 8
%"88" = inttoptr i64 %"73" to ptr
%"72" = load float, ptr %"88", align 4
store float %"72", ptr addrspace(5) %"67", align 4
%"74" = load i64, ptr addrspace(5) %"65", align 8
%"89" = inttoptr i64 %"74" to ptr
%"32" = getelementptr inbounds i8, ptr %"89", i64 4
%"75" = load float, ptr %"32", align 4
store float %"75", ptr addrspace(5) %"68", align 4
%"77" = load float, ptr addrspace(5) %"67", align 4
%"78" = load float, ptr addrspace(5) %"68", align 4
%"76" = fmul float %"77", %"78"
store float %"76", ptr addrspace(5) %"69", align 4
%"79" = load float, ptr addrspace(5) %"67", align 4
%"80" = load float, ptr addrspace(5) %"68", align 4
%2 = call %struct.f32.f32.f32.i8 @__zluda_ptx_impl_div_f32_part1(float %"79", float %"80")
%"37" = extractvalue %struct.f32.f32.f32.i8 %2, 0
%"38" = extractvalue %struct.f32.f32.f32.i8 %2, 1
%"39" = extractvalue %struct.f32.f32.f32.i8 %2, 2
%"40" = extractvalue %struct.f32.f32.f32.i8 %2, 3
br label %"57"
"57": ; preds = %"54"
"57": ; preds = %1
%"73" = load i64, ptr addrspace(4) %"66", align 8
store i64 %"73", ptr addrspace(5) %"68", align 8
%"74" = load i64, ptr addrspace(4) %"67", align 8
store i64 %"74", ptr addrspace(5) %"69", align 8
%"76" = load i64, ptr addrspace(5) %"68", align 8
%"91" = inttoptr i64 %"76" to ptr
%"75" = load float, ptr %"91", align 4
store float %"75", ptr addrspace(5) %"70", align 4
%"77" = load i64, ptr addrspace(5) %"68", align 8
%"92" = inttoptr i64 %"77" to ptr
%"35" = getelementptr inbounds i8, ptr %"92", i64 4
%"78" = load float, ptr %"35", align 4
store float %"78", ptr addrspace(5) %"71", align 4
%"80" = load float, ptr addrspace(5) %"70", align 4
%"81" = load float, ptr addrspace(5) %"71", align 4
%"79" = fmul float %"80", %"81"
store float %"79", ptr addrspace(5) %"72", align 4
%"82" = load float, ptr addrspace(5) %"70", align 4
%"83" = load float, ptr addrspace(5) %"71", align 4
%2 = call %struct.f32.f32.f32.i8 @__zluda_ptx_impl_div_f32_part1(float %"82", float %"83")
%"40" = extractvalue %struct.f32.f32.f32.i8 %2, 0
%"41" = extractvalue %struct.f32.f32.f32.i8 %2, 1
%"42" = extractvalue %struct.f32.f32.f32.i8 %2, 2
%"43" = extractvalue %struct.f32.f32.f32.i8 %2, 3
br label %"60"
"60": ; preds = %"57"
call void @llvm.amdgcn.s.setreg(i32 6401, i32 0)
br label %"55"
br label %"58"
"55": ; preds = %"57"
%"82" = load float, ptr addrspace(5) %"67", align 4
%"83" = load float, ptr addrspace(5) %"68", align 4
%"81" = call float @__zluda_ptx_impl_div_f32_part2(float %"82", float %"83", float %"37", float %"38", float %"39", i8 %"40")
store float %"81", ptr addrspace(5) %"67", align 4
br label %"56"
"58": ; preds = %"60"
%"85" = load float, ptr addrspace(5) %"70", align 4
%"86" = load float, ptr addrspace(5) %"71", align 4
%"84" = call float @__zluda_ptx_impl_div_f32_part2(float %"85", float %"86", float %"40", float %"41", float %"42", i8 %"43")
store float %"84", ptr addrspace(5) %"70", align 4
br label %"59"
"56": ; preds = %"55"
%"84" = load i64, ptr addrspace(5) %"66", align 8
%"85" = load float, ptr addrspace(5) %"67", align 4
%"90" = inttoptr i64 %"84" to ptr
store float %"85", ptr %"90", align 4
%"86" = load i64, ptr addrspace(5) %"66", align 8
%"91" = inttoptr i64 %"86" to ptr
%"34" = getelementptr inbounds i8, ptr %"91", i64 4
%"87" = load float, ptr addrspace(5) %"69", align 4
store float %"87", ptr %"34", align 4
"59": ; preds = %"58"
%"87" = load i64, ptr addrspace(5) %"69", align 8
%"88" = load float, ptr addrspace(5) %"70", align 4
%"93" = inttoptr i64 %"87" to ptr
store float %"88", ptr %"93", align 4
%"89" = load i64, ptr addrspace(5) %"69", align 8
%"94" = inttoptr i64 %"89" to ptr
%"37" = getelementptr inbounds i8, ptr %"94", i64 4
%"90" = load float, ptr addrspace(5) %"72", align 4
store float %"90", ptr %"37", align 4
ret void
}

98
ptx/src/test/ll/div_noftz.ll
View file

@ -4,62 +4,62 @@ declare hidden %struct.f32.f32.f32.i8 @__zluda_ptx_impl_div_f32_part1(float, flo
declare hidden float @__zluda_ptx_impl_div_f32_part2(float, float, float, float, float, i8) #0
define amdgpu_kernel void @div_noftz(ptr addrspace(4) byref(i64) %"62", ptr addrspace(4) byref(i64) %"63") #1 {
%"64" = alloca i64, align 8, addrspace(5)
%"65" = alloca i64, align 8, addrspace(5)
%"66" = alloca float, align 4, addrspace(5)
%"67" = alloca float, align 4, addrspace(5)
%"68" = alloca float, align 4, addrspace(5)
define amdgpu_kernel void @div_noftz(ptr addrspace(4) byref(i64) %"65", ptr addrspace(4) byref(i64) %"66") #1 {
%"67" = alloca i64, align 8, addrspace(5)
%"68" = alloca i64, align 8, addrspace(5)
%"69" = alloca float, align 4, addrspace(5)
%"70" = alloca float, align 4, addrspace(5)
%"71" = alloca float, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"54"
br label %"57"
"54": ; preds = %1
%"69" = load i64, ptr addrspace(4) %"62", align 8
store i64 %"69", ptr addrspace(5) %"64", align 8
%"70" = load i64, ptr addrspace(4) %"63", align 8
store i64 %"70", ptr addrspace(5) %"65", align 8
%"72" = load i64, ptr addrspace(5) %"64", align 8
%"87" = inttoptr i64 %"72" to ptr
%"71" = load float, ptr %"87", align 4
store float %"71", ptr addrspace(5) %"66", align 4
%"73" = load i64, ptr addrspace(5) %"64", align 8
%"88" = inttoptr i64 %"73" to ptr
%"32" = getelementptr inbounds i8, ptr %"88", i64 4
%"74" = load float, ptr %"32", align 4
store float %"74", ptr addrspace(5) %"67", align 4
%"76" = load float, ptr addrspace(5) %"66", align 4
%"77" = load float, ptr addrspace(5) %"67", align 4
%"75" = fmul float %"76", %"77"
store float %"75", ptr addrspace(5) %"68", align 4
"57": ; preds = %1
%"72" = load i64, ptr addrspace(4) %"65", align 8
store i64 %"72", ptr addrspace(5) %"67", align 8
%"73" = load i64, ptr addrspace(4) %"66", align 8
store i64 %"73", ptr addrspace(5) %"68", align 8
%"75" = load i64, ptr addrspace(5) %"67", align 8
%"90" = inttoptr i64 %"75" to ptr
%"74" = load float, ptr %"90", align 4
store float %"74", ptr addrspace(5) %"69", align 4
%"76" = load i64, ptr addrspace(5) %"67", align 8
%"91" = inttoptr i64 %"76" to ptr
%"35" = getelementptr inbounds i8, ptr %"91", i64 4
%"77" = load float, ptr %"35", align 4
store float %"77", ptr addrspace(5) %"70", align 4
%"79" = load float, ptr addrspace(5) %"69", align 4
%"80" = load float, ptr addrspace(5) %"70", align 4
%"78" = fmul float %"79", %"80"
store float %"78", ptr addrspace(5) %"71", align 4
call void @llvm.amdgcn.s.setreg(i32 6401, i32 3)
%"78" = load float, ptr addrspace(5) %"66", align 4
%"79" = load float, ptr addrspace(5) %"67", align 4
%2 = call %struct.f32.f32.f32.i8 @__zluda_ptx_impl_div_f32_part1(float %"78", float %"79")
%"37" = extractvalue %struct.f32.f32.f32.i8 %2, 0
%"38" = extractvalue %struct.f32.f32.f32.i8 %2, 1
%"39" = extractvalue %struct.f32.f32.f32.i8 %2, 2
%"40" = extractvalue %struct.f32.f32.f32.i8 %2, 3
br label %"55"
%"81" = load float, ptr addrspace(5) %"69", align 4
%"82" = load float, ptr addrspace(5) %"70", align 4
%2 = call %struct.f32.f32.f32.i8 @__zluda_ptx_impl_div_f32_part1(float %"81", float %"82")
%"40" = extractvalue %struct.f32.f32.f32.i8 %2, 0
%"41" = extractvalue %struct.f32.f32.f32.i8 %2, 1
%"42" = extractvalue %struct.f32.f32.f32.i8 %2, 2
%"43" = extractvalue %struct.f32.f32.f32.i8 %2, 3
br label %"58"
"55": ; preds = %"54"
%"81" = load float, ptr addrspace(5) %"66", align 4
%"82" = load float, ptr addrspace(5) %"67", align 4
%"80" = call float @__zluda_ptx_impl_div_f32_part2(float %"81", float %"82", float %"37", float %"38", float %"39", i8 %"40")
store float %"80", ptr addrspace(5) %"66", align 4
br label %"56"
"58": ; preds = %"57"
%"84" = load float, ptr addrspace(5) %"69", align 4
%"85" = load float, ptr addrspace(5) %"70", align 4
%"83" = call float @__zluda_ptx_impl_div_f32_part2(float %"84", float %"85", float %"40", float %"41", float %"42", i8 %"43")
store float %"83", ptr addrspace(5) %"69", align 4
br label %"59"
"56": ; preds = %"55"
%"83" = load i64, ptr addrspace(5) %"65", align 8
%"84" = load float, ptr addrspace(5) %"66", align 4
%"89" = inttoptr i64 %"83" to ptr
store float %"84", ptr %"89", align 4
%"85" = load i64, ptr addrspace(5) %"65", align 8
%"90" = inttoptr i64 %"85" to ptr
%"34" = getelementptr inbounds i8, ptr %"90", i64 4
%"86" = load float, ptr addrspace(5) %"68", align 4
store float %"86", ptr %"34", align 4
"59": ; preds = %"58"
%"86" = load i64, ptr addrspace(5) %"68", align 8
%"87" = load float, ptr addrspace(5) %"69", align 4
%"92" = inttoptr i64 %"86" to ptr
store float %"87", ptr %"92", align 4
%"88" = load i64, ptr addrspace(5) %"68", align 8
%"93" = inttoptr i64 %"88" to ptr
%"37" = getelementptr inbounds i8, ptr %"93", i64 4
%"89" = load float, ptr addrspace(5) %"71", align 4
store float %"89", ptr %"37", align 4
ret void
}

70
ptx/src/test/ll/dp4a.ll
View file

@ -1,43 +1,43 @@
define amdgpu_kernel void @dp4a(ptr addrspace(4) byref(i64) %"37", ptr addrspace(4) byref(i64) %"38") #0 {
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i32, align 4, addrspace(5)
%"42" = alloca i32, align 4, addrspace(5)
%"43" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @dp4a(ptr addrspace(4) byref(i64) %"40", ptr addrspace(4) byref(i64) %"41") #0 {
%"42" = alloca i64, align 8, addrspace(5)
%"43" = alloca i64, align 8, addrspace(5)
%"44" = alloca i32, align 4, addrspace(5)
%"45" = alloca i32, align 4, addrspace(5)
%"46" = alloca i32, align 4, addrspace(5)
%"47" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"36"
br label %"39"
"36": ; preds = %1
%"45" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"45", ptr addrspace(5) %"39", align 8
%"46" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"46", ptr addrspace(5) %"40", align 8
%"48" = load i64, ptr addrspace(5) %"39", align 8
%"59" = inttoptr i64 %"48" to ptr
%"47" = load i32, ptr %"59", align 4
store i32 %"47", ptr addrspace(5) %"41", align 4
%"49" = load i64, ptr addrspace(5) %"39", align 8
%"60" = inttoptr i64 %"49" to ptr
%"33" = getelementptr inbounds i8, ptr %"60", i64 4
%"50" = load i32, ptr %"33", align 4
store i32 %"50", ptr addrspace(5) %"42", align 4
%"51" = load i64, ptr addrspace(5) %"39", align 8
%"61" = inttoptr i64 %"51" to ptr
%"35" = getelementptr inbounds i8, ptr %"61", i64 8
%"52" = load i32, ptr %"35", align 4
store i32 %"52", ptr addrspace(5) %"43", align 4
%"54" = load i32, ptr addrspace(5) %"41", align 4
%"55" = load i32, ptr addrspace(5) %"42", align 4
%"56" = load i32, ptr addrspace(5) %"43", align 4
%"53" = call i32 @llvm.amdgcn.sdot4(i32 %"54", i32 %"55", i32 %"56", i1 false)
store i32 %"53", ptr addrspace(5) %"44", align 4
%"57" = load i64, ptr addrspace(5) %"40", align 8
%"58" = load i32, ptr addrspace(5) %"44", align 4
%"65" = inttoptr i64 %"57" to ptr
store i32 %"58", ptr %"65", align 4
"39": ; preds = %1
%"48" = load i64, ptr addrspace(4) %"40", align 8
store i64 %"48", ptr addrspace(5) %"42", align 8
%"49" = load i64, ptr addrspace(4) %"41", align 8
store i64 %"49", ptr addrspace(5) %"43", align 8
%"51" = load i64, ptr addrspace(5) %"42", align 8
%"62" = inttoptr i64 %"51" to ptr
%"50" = load i32, ptr %"62", align 4
store i32 %"50", ptr addrspace(5) %"44", align 4
%"52" = load i64, ptr addrspace(5) %"42", align 8
%"63" = inttoptr i64 %"52" to ptr
%"36" = getelementptr inbounds i8, ptr %"63", i64 4
%"53" = load i32, ptr %"36", align 4
store i32 %"53", ptr addrspace(5) %"45", align 4
%"54" = load i64, ptr addrspace(5) %"42", align 8
%"64" = inttoptr i64 %"54" to ptr
%"38" = getelementptr inbounds i8, ptr %"64", i64 8
%"55" = load i32, ptr %"38", align 4
store i32 %"55", ptr addrspace(5) %"46", align 4
%"57" = load i32, ptr addrspace(5) %"44", align 4
%"58" = load i32, ptr addrspace(5) %"45", align 4
%"59" = load i32, ptr addrspace(5) %"46", align 4
%"56" = call i32 @llvm.amdgcn.sdot4(i32 %"57", i32 %"58", i32 %"59", i1 false)
store i32 %"56", ptr addrspace(5) %"47", align 4
%"60" = load i64, ptr addrspace(5) %"43", align 8
%"61" = load i32, ptr addrspace(5) %"47", align 4
%"68" = inttoptr i64 %"60" to ptr
store i32 %"61", ptr %"68", align 4
ret void
}

42
ptx/src/test/ll/ex2.ll
View file

@ -1,30 +1,30 @@
declare hidden float @__zluda_ptx_impl_ex2_approx_f32(float) #0
define amdgpu_kernel void @ex2(ptr addrspace(4) byref(i64) %"30", ptr addrspace(4) byref(i64) %"31") #1 {
%"32" = alloca i64, align 8, addrspace(5)
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca float, align 4, addrspace(5)
define amdgpu_kernel void @ex2(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #1 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca float, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"29"
br label %"32"
"29": ; preds = %1
%"35" = load i64, ptr addrspace(4) %"30", align 8
store i64 %"35", ptr addrspace(5) %"32", align 8
%"36" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"36", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(5) %"32", align 8
%"43" = inttoptr i64 %"38" to ptr
%"37" = load float, ptr %"43", align 4
store float %"37", ptr addrspace(5) %"34", align 4
%"40" = load float, ptr addrspace(5) %"34", align 4
%"39" = call float @__zluda_ptx_impl_ex2_approx_f32(float %"40")
store float %"39", ptr addrspace(5) %"34", align 4
%"41" = load i64, ptr addrspace(5) %"33", align 8
%"42" = load float, ptr addrspace(5) %"34", align 4
%"44" = inttoptr i64 %"41" to ptr
store float %"42", ptr %"44", align 4
"32": ; preds = %1
%"38" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"38", ptr addrspace(5) %"35", align 8
%"39" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"39", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(5) %"35", align 8
%"46" = inttoptr i64 %"41" to ptr
%"40" = load float, ptr %"46", align 4
store float %"40", ptr addrspace(5) %"37", align 4
%"43" = load float, ptr addrspace(5) %"37", align 4
%"42" = call float @__zluda_ptx_impl_ex2_approx_f32(float %"43")
store float %"42", ptr addrspace(5) %"37", align 4
%"44" = load i64, ptr addrspace(5) %"36", align 8
%"45" = load float, ptr addrspace(5) %"37", align 4
%"47" = inttoptr i64 %"44" to ptr
store float %"45", ptr %"47", align 4
ret void
}

60
ptx/src/test/ll/extern_func.ll
View file

@ -1,41 +1,41 @@
declare hidden [16 x i8] @foobar(i64) #0
define amdgpu_kernel void @extern_func(ptr addrspace(4) byref(i64) %"44", ptr addrspace(4) byref(i64) %"45") #1 {
%"46" = alloca i64, align 8, addrspace(5)
%"47" = alloca i64, align 8, addrspace(5)
%"48" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @extern_func(ptr addrspace(4) byref(i64) %"47", ptr addrspace(4) byref(i64) %"48") #1 {
%"49" = alloca i64, align 8, addrspace(5)
%"54" = alloca i64, align 8, addrspace(5)
%"57" = alloca [16 x i8], align 16, addrspace(5)
%"50" = alloca i64, align 8, addrspace(5)
%"51" = alloca i64, align 8, addrspace(5)
%"52" = alloca i64, align 8, addrspace(5)
%"57" = alloca i64, align 8, addrspace(5)
%"60" = alloca [16 x i8], align 16, addrspace(5)
br label %1
1: ; preds = %0
br label %"41"
br label %"44"
"41": ; preds = %1
%"50" = load i64, ptr addrspace(4) %"44", align 8
store i64 %"50", ptr addrspace(5) %"46", align 8
%"51" = load i64, ptr addrspace(4) %"45", align 8
store i64 %"51", ptr addrspace(5) %"47", align 8
%"53" = load i64, ptr addrspace(5) %"46", align 8
%"61" = inttoptr i64 %"53" to ptr addrspace(1)
%"52" = load i64, ptr addrspace(1) %"61", align 8
store i64 %"52", ptr addrspace(5) %"48", align 8
%"55" = getelementptr inbounds i8, ptr addrspace(5) %"54", i64 0
%"56" = load i64, ptr addrspace(5) %"48", align 8
store i64 %"56", ptr addrspace(5) %"55", align 8
%"39" = load i64, ptr addrspace(5) %"54", align 8
%"40" = call [16 x i8] @foobar(i64 %"39")
br label %"42"
"44": ; preds = %1
%"53" = load i64, ptr addrspace(4) %"47", align 8
store i64 %"53", ptr addrspace(5) %"49", align 8
%"54" = load i64, ptr addrspace(4) %"48", align 8
store i64 %"54", ptr addrspace(5) %"50", align 8
%"56" = load i64, ptr addrspace(5) %"49", align 8
%"64" = inttoptr i64 %"56" to ptr addrspace(1)
%"55" = load i64, ptr addrspace(1) %"64", align 8
store i64 %"55", ptr addrspace(5) %"51", align 8
%"58" = getelementptr inbounds i8, ptr addrspace(5) %"57", i64 0
%"59" = load i64, ptr addrspace(5) %"51", align 8
store i64 %"59", ptr addrspace(5) %"58", align 8
%"42" = load i64, ptr addrspace(5) %"57", align 8
%"43" = call [16 x i8] @foobar(i64 %"42")
br label %"45"
"42": ; preds = %"41"
store [16 x i8] %"40", ptr addrspace(5) %"57", align 1
%"58" = load i64, ptr addrspace(5) %"57", align 8
store i64 %"58", ptr addrspace(5) %"49", align 8
%"59" = load i64, ptr addrspace(5) %"47", align 8
%"60" = load i64, ptr addrspace(5) %"49", align 8
%"64" = inttoptr i64 %"59" to ptr
store i64 %"60", ptr %"64", align 8
"45": ; preds = %"44"
store [16 x i8] %"43", ptr addrspace(5) %"60", align 1
%"61" = load i64, ptr addrspace(5) %"60", align 8
store i64 %"61", ptr addrspace(5) %"52", align 8
%"62" = load i64, ptr addrspace(5) %"50", align 8
%"63" = load i64, ptr addrspace(5) %"52", align 8
%"67" = inttoptr i64 %"62" to ptr
store i64 %"63", ptr %"67", align 8
ret void
}

42
ptx/src/test/ll/extern_shared.ll
View file

@ -1,31 +1,31 @@
@shared_mem = external addrspace(3) global [0 x i32]
define amdgpu_kernel void @extern_shared(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #0 {
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @extern_shared(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"30"
br label %"33"
"30": ; preds = %1
%"36" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"36", ptr addrspace(5) %"33", align 8
%"37" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"37", ptr addrspace(5) %"34", align 8
%"39" = load i64, ptr addrspace(5) %"33", align 8
%"44" = inttoptr i64 %"39" to ptr addrspace(1)
%"38" = load i64, ptr addrspace(1) %"44", align 8
store i64 %"38", ptr addrspace(5) %"35", align 8
%"40" = load i64, ptr addrspace(5) %"35", align 8
store i64 %"40", ptr addrspace(3) @shared_mem, align 8
%"41" = load i64, ptr addrspace(3) @shared_mem, align 8
store i64 %"41", ptr addrspace(5) %"35", align 8
%"42" = load i64, ptr addrspace(5) %"34", align 8
%"43" = load i64, ptr addrspace(5) %"35", align 8
"33": ; preds = %1
%"39" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"39", ptr addrspace(5) %"36", align 8
%"40" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"40", ptr addrspace(5) %"37", align 8
%"42" = load i64, ptr addrspace(5) %"36", align 8
%"47" = inttoptr i64 %"42" to ptr addrspace(1)
store i64 %"43", ptr addrspace(1) %"47", align 8
%"41" = load i64, ptr addrspace(1) %"47", align 8
store i64 %"41", ptr addrspace(5) %"38", align 8
%"43" = load i64, ptr addrspace(5) %"38", align 8
store i64 %"43", ptr addrspace(3) @shared_mem, align 8
%"44" = load i64, ptr addrspace(3) @shared_mem, align 8
store i64 %"44", ptr addrspace(5) %"38", align 8
%"45" = load i64, ptr addrspace(5) %"37", align 8
%"46" = load i64, ptr addrspace(5) %"38", align 8
%"50" = inttoptr i64 %"45" to ptr addrspace(1)
store i64 %"46", ptr addrspace(1) %"50", align 8
ret void
}

70
ptx/src/test/ll/extern_shared_call.ll
View file

@ -1,53 +1,53 @@
@shared_mem = external addrspace(3) global [0 x i32], align 4
define hidden void @incr_shared_2_global() #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"33"
br label %"36"
"33": ; preds = %1
%"37" = load i64, ptr addrspace(3) @shared_mem, align 8
store i64 %"37", ptr addrspace(5) %"36", align 8
%"39" = load i64, ptr addrspace(5) %"36", align 8
%"38" = add i64 %"39", 2
store i64 %"38", ptr addrspace(5) %"36", align 8
%"40" = load i64, ptr addrspace(5) %"36", align 8
store i64 %"40", ptr addrspace(3) @shared_mem, align 8
"36": ; preds = %1
%"40" = load i64, ptr addrspace(3) @shared_mem, align 8
store i64 %"40", ptr addrspace(5) %"39", align 8
%"42" = load i64, ptr addrspace(5) %"39", align 8
%"41" = add i64 %"42", 2
store i64 %"41", ptr addrspace(5) %"39", align 8
%"43" = load i64, ptr addrspace(5) %"39", align 8
store i64 %"43", ptr addrspace(3) @shared_mem, align 8
ret void
}
define amdgpu_kernel void @extern_shared_call(ptr addrspace(4) byref(i64) %"41", ptr addrspace(4) byref(i64) %"42") #1 {
%"43" = alloca i64, align 8, addrspace(5)
%"44" = alloca i64, align 8, addrspace(5)
%"45" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @extern_shared_call(ptr addrspace(4) byref(i64) %"44", ptr addrspace(4) byref(i64) %"45") #1 {
%"46" = alloca i64, align 8, addrspace(5)
%"47" = alloca i64, align 8, addrspace(5)
%"48" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"34"
br label %"37"
"34": ; preds = %1
%"46" = load i64, ptr addrspace(4) %"41", align 8
store i64 %"46", ptr addrspace(5) %"43", align 8
%"47" = load i64, ptr addrspace(4) %"42", align 8
store i64 %"47", ptr addrspace(5) %"44", align 8
%"49" = load i64, ptr addrspace(5) %"43", align 8
%"56" = inttoptr i64 %"49" to ptr addrspace(1)
%"48" = load i64, ptr addrspace(1) %"56", align 8
store i64 %"48", ptr addrspace(5) %"45", align 8
%"50" = load i64, ptr addrspace(5) %"45", align 8
store i64 %"50", ptr addrspace(3) @shared_mem, align 8
call void @incr_shared_2_global()
br label %"35"
"35": ; preds = %"34"
%"51" = load i64, ptr addrspace(3) @shared_mem, align 8
store i64 %"51", ptr addrspace(5) %"45", align 8
%"52" = load i64, ptr addrspace(5) %"44", align 8
%"53" = load i64, ptr addrspace(5) %"45", align 8
"37": ; preds = %1
%"49" = load i64, ptr addrspace(4) %"44", align 8
store i64 %"49", ptr addrspace(5) %"46", align 8
%"50" = load i64, ptr addrspace(4) %"45", align 8
store i64 %"50", ptr addrspace(5) %"47", align 8
%"52" = load i64, ptr addrspace(5) %"46", align 8
%"59" = inttoptr i64 %"52" to ptr addrspace(1)
store i64 %"53", ptr addrspace(1) %"59", align 8
%"51" = load i64, ptr addrspace(1) %"59", align 8
store i64 %"51", ptr addrspace(5) %"48", align 8
%"53" = load i64, ptr addrspace(5) %"48", align 8
store i64 %"53", ptr addrspace(3) @shared_mem, align 8
call void @incr_shared_2_global()
br label %"38"
"38": ; preds = %"37"
%"54" = load i64, ptr addrspace(3) @shared_mem, align 8
store i64 %"54", ptr addrspace(5) %"48", align 8
%"55" = load i64, ptr addrspace(5) %"47", align 8
%"56" = load i64, ptr addrspace(5) %"48", align 8
%"62" = inttoptr i64 %"55" to ptr addrspace(1)
store i64 %"56", ptr addrspace(1) %"62", align 8
ret void
}

70
ptx/src/test/ll/fma.ll
View file

@ -1,42 +1,42 @@
define amdgpu_kernel void @fma(ptr addrspace(4) byref(i64) %"36", ptr addrspace(4) byref(i64) %"37") #0 {
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca float, align 4, addrspace(5)
%"41" = alloca float, align 4, addrspace(5)
%"42" = alloca float, align 4, addrspace(5)
define amdgpu_kernel void @fma(ptr addrspace(4) byref(i64) %"39", ptr addrspace(4) byref(i64) %"40") #0 {
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i64, align 8, addrspace(5)
%"43" = alloca float, align 4, addrspace(5)
%"44" = alloca float, align 4, addrspace(5)
%"45" = alloca float, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"35"
br label %"38"
"35": ; preds = %1
%"43" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"43", ptr addrspace(5) %"38", align 8
%"44" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"44", ptr addrspace(5) %"39", align 8
%"46" = load i64, ptr addrspace(5) %"38", align 8
%"57" = inttoptr i64 %"46" to ptr
%"45" = load float, ptr %"57", align 4
store float %"45", ptr addrspace(5) %"40", align 4
%"47" = load i64, ptr addrspace(5) %"38", align 8
%"58" = inttoptr i64 %"47" to ptr
%"32" = getelementptr inbounds i8, ptr %"58", i64 4
%"48" = load float, ptr %"32", align 4
store float %"48", ptr addrspace(5) %"41", align 4
%"49" = load i64, ptr addrspace(5) %"38", align 8
%"59" = inttoptr i64 %"49" to ptr
%"34" = getelementptr inbounds i8, ptr %"59", i64 8
%"50" = load float, ptr %"34", align 4
store float %"50", ptr addrspace(5) %"42", align 4
%"52" = load float, ptr addrspace(5) %"40", align 4
%"53" = load float, ptr addrspace(5) %"41", align 4
%"54" = load float, ptr addrspace(5) %"42", align 4
%"51" = call float @llvm.fma.f32(float %"52", float %"53", float %"54")
store float %"51", ptr addrspace(5) %"40", align 4
%"55" = load i64, ptr addrspace(5) %"39", align 8
%"56" = load float, ptr addrspace(5) %"40", align 4
%"60" = inttoptr i64 %"55" to ptr
store float %"56", ptr %"60", align 4
"38": ; preds = %1
%"46" = load i64, ptr addrspace(4) %"39", align 8
store i64 %"46", ptr addrspace(5) %"41", align 8
%"47" = load i64, ptr addrspace(4) %"40", align 8
store i64 %"47", ptr addrspace(5) %"42", align 8
%"49" = load i64, ptr addrspace(5) %"41", align 8
%"60" = inttoptr i64 %"49" to ptr
%"48" = load float, ptr %"60", align 4
store float %"48", ptr addrspace(5) %"43", align 4
%"50" = load i64, ptr addrspace(5) %"41", align 8
%"61" = inttoptr i64 %"50" to ptr
%"35" = getelementptr inbounds i8, ptr %"61", i64 4
%"51" = load float, ptr %"35", align 4
store float %"51", ptr addrspace(5) %"44", align 4
%"52" = load i64, ptr addrspace(5) %"41", align 8
%"62" = inttoptr i64 %"52" to ptr
%"37" = getelementptr inbounds i8, ptr %"62", i64 8
%"53" = load float, ptr %"37", align 4
store float %"53", ptr addrspace(5) %"45", align 4
%"55" = load float, ptr addrspace(5) %"43", align 4
%"56" = load float, ptr addrspace(5) %"44", align 4
%"57" = load float, ptr addrspace(5) %"45", align 4
%"54" = call float @llvm.fma.f32(float %"55", float %"56", float %"57")
store float %"54", ptr addrspace(5) %"43", align 4
%"58" = load i64, ptr addrspace(5) %"42", align 8
%"59" = load float, ptr addrspace(5) %"43", align 4
%"63" = inttoptr i64 %"58" to ptr
store float %"59", ptr %"63", align 4
ret void
}

62
ptx/src/test/ll/fmax.ll
View file

@ -1,40 +1,40 @@
define amdgpu_kernel void @fmax(ptr addrspace(4) byref(i64) %"35", ptr addrspace(4) byref(i64) %"36") #0 {
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca half, align 2, addrspace(5)
%"40" = alloca half, align 2, addrspace(5)
%"41" = alloca half, align 2, addrspace(5)
define amdgpu_kernel void @fmax(ptr addrspace(4) byref(i64) %"38", ptr addrspace(4) byref(i64) %"39") #0 {
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca half, align 2, addrspace(5)
%"43" = alloca half, align 2, addrspace(5)
%"44" = alloca half, align 2, addrspace(5)
%"45" = alloca half, align 2, addrspace(5)
br label %1
1: ; preds = %0
br label %"34"
br label %"37"
"34": ; preds = %1
%"43" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"43", ptr addrspace(5) %"37", align 8
%"44" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"44", ptr addrspace(5) %"38", align 8
%"46" = load i64, ptr addrspace(5) %"37", align 8
%"55" = inttoptr i64 %"46" to ptr
%"54" = load i16, ptr %"55", align 2
%"45" = bitcast i16 %"54" to half
store half %"45", ptr addrspace(5) %"39", align 2
%"47" = load i64, ptr addrspace(5) %"37", align 8
%"56" = inttoptr i64 %"47" to ptr
%"33" = getelementptr inbounds i8, ptr %"56", i64 2
%"57" = load i16, ptr %"33", align 2
"37": ; preds = %1
%"46" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"46", ptr addrspace(5) %"40", align 8
%"47" = load i64, ptr addrspace(4) %"39", align 8
store i64 %"47", ptr addrspace(5) %"41", align 8
%"49" = load i64, ptr addrspace(5) %"40", align 8
%"58" = inttoptr i64 %"49" to ptr
%"57" = load i16, ptr %"58", align 2
%"48" = bitcast i16 %"57" to half
store half %"48", ptr addrspace(5) %"40", align 2
%"50" = load half, ptr addrspace(5) %"40", align 2
%"51" = load half, ptr addrspace(5) %"39", align 2
%"49" = call half @llvm.maxnum.f16(half %"50", half %"51")
store half %"49", ptr addrspace(5) %"41", align 2
%"52" = load i64, ptr addrspace(5) %"38", align 8
%"53" = load half, ptr addrspace(5) %"41", align 2
%"58" = inttoptr i64 %"52" to ptr
%"59" = bitcast half %"53" to i16
store i16 %"59", ptr %"58", align 2
store half %"48", ptr addrspace(5) %"42", align 2
%"50" = load i64, ptr addrspace(5) %"40", align 8
%"59" = inttoptr i64 %"50" to ptr
%"36" = getelementptr inbounds i8, ptr %"59", i64 2
%"60" = load i16, ptr %"36", align 2
%"51" = bitcast i16 %"60" to half
store half %"51", ptr addrspace(5) %"43", align 2
%"53" = load half, ptr addrspace(5) %"43", align 2
%"54" = load half, ptr addrspace(5) %"42", align 2
%"52" = call half @llvm.maxnum.f16(half %"53", half %"54")
store half %"52", ptr addrspace(5) %"44", align 2
%"55" = load i64, ptr addrspace(5) %"41", align 8
%"56" = load half, ptr addrspace(5) %"44", align 2
%"61" = inttoptr i64 %"55" to ptr
%"62" = bitcast half %"56" to i16
store i16 %"62", ptr %"61", align 2
ret void
}

34
ptx/src/test/ll/global_array.ll
View file

@ -1,26 +1,26 @@
@foobar = addrspace(1) global [4 x i32] [i32 1, i32 0, i32 0, i32 0]
define amdgpu_kernel void @global_array(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #0 {
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @global_array(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"30"
br label %"33"
"30": ; preds = %1
store i64 ptrtoint (ptr addrspace(1) @foobar to i64), ptr addrspace(5) %"33", align 8
%"37" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"37", ptr addrspace(5) %"34", align 8
%"39" = load i64, ptr addrspace(5) %"33", align 8
%"43" = inttoptr i64 %"39" to ptr addrspace(1)
%"38" = load i32, ptr addrspace(1) %"43", align 4
store i32 %"38", ptr addrspace(5) %"35", align 4
%"40" = load i64, ptr addrspace(5) %"34", align 8
%"41" = load i32, ptr addrspace(5) %"35", align 4
%"44" = inttoptr i64 %"40" to ptr addrspace(1)
store i32 %"41", ptr addrspace(1) %"44", align 4
"33": ; preds = %1
store i64 ptrtoint (ptr addrspace(1) @foobar to i64), ptr addrspace(5) %"36", align 8
%"40" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"40", ptr addrspace(5) %"37", align 8
%"42" = load i64, ptr addrspace(5) %"36", align 8
%"46" = inttoptr i64 %"42" to ptr addrspace(1)
%"41" = load i32, ptr addrspace(1) %"46", align 4
store i32 %"41", ptr addrspace(5) %"38", align 4
%"43" = load i64, ptr addrspace(5) %"37", align 8
%"44" = load i32, ptr addrspace(5) %"38", align 4
%"47" = inttoptr i64 %"43" to ptr addrspace(1)
store i32 %"44", ptr addrspace(1) %"47", align 4
ret void
}

62
ptx/src/test/ll/lanemask_lt.ll
View file

@ -1,41 +1,41 @@
declare hidden i32 @__zluda_ptx_impl_sreg_lanemask_lt() #0
define amdgpu_kernel void @lanemask_lt(ptr addrspace(4) byref(i64) %"36", ptr addrspace(4) byref(i64) %"37") #1 {
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i32, align 4, addrspace(5)
%"41" = alloca i32, align 4, addrspace(5)
%"42" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @lanemask_lt(ptr addrspace(4) byref(i64) %"39", ptr addrspace(4) byref(i64) %"40") #1 {
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i64, align 8, addrspace(5)
%"43" = alloca i32, align 4, addrspace(5)
%"44" = alloca i32, align 4, addrspace(5)
%"45" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"33"
br label %"36"
"33": ; preds = %1
%"43" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"43", ptr addrspace(5) %"38", align 8
%"44" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"44", ptr addrspace(5) %"39", align 8
%"46" = load i64, ptr addrspace(5) %"38", align 8
%"56" = inttoptr i64 %"46" to ptr
%"55" = load i32, ptr %"56", align 4
store i32 %"55", ptr addrspace(5) %"40", align 4
%"48" = load i32, ptr addrspace(5) %"40", align 4
%"57" = add i32 %"48", 1
store i32 %"57", ptr addrspace(5) %"41", align 4
%"31" = call i32 @__zluda_ptx_impl_sreg_lanemask_lt()
br label %"34"
"36": ; preds = %1
%"46" = load i64, ptr addrspace(4) %"39", align 8
store i64 %"46", ptr addrspace(5) %"41", align 8
%"47" = load i64, ptr addrspace(4) %"40", align 8
store i64 %"47", ptr addrspace(5) %"42", align 8
%"49" = load i64, ptr addrspace(5) %"41", align 8
%"59" = inttoptr i64 %"49" to ptr
%"58" = load i32, ptr %"59", align 4
store i32 %"58", ptr addrspace(5) %"43", align 4
%"51" = load i32, ptr addrspace(5) %"43", align 4
%"60" = add i32 %"51", 1
store i32 %"60", ptr addrspace(5) %"44", align 4
%"34" = call i32 @__zluda_ptx_impl_sreg_lanemask_lt()
br label %"37"
"34": ; preds = %"33"
store i32 %"31", ptr addrspace(5) %"42", align 4
%"51" = load i32, ptr addrspace(5) %"41", align 4
%"52" = load i32, ptr addrspace(5) %"42", align 4
%"60" = add i32 %"51", %"52"
store i32 %"60", ptr addrspace(5) %"41", align 4
%"53" = load i64, ptr addrspace(5) %"39", align 8
%"54" = load i32, ptr addrspace(5) %"41", align 4
%"63" = inttoptr i64 %"53" to ptr
store i32 %"54", ptr %"63", align 4
"37": ; preds = %"36"
store i32 %"34", ptr addrspace(5) %"45", align 4
%"54" = load i32, ptr addrspace(5) %"44", align 4
%"55" = load i32, ptr addrspace(5) %"45", align 4
%"63" = add i32 %"54", %"55"
store i32 %"63", ptr addrspace(5) %"44", align 4
%"56" = load i64, ptr addrspace(5) %"42", align 8
%"57" = load i32, ptr addrspace(5) %"44", align 4
%"66" = inttoptr i64 %"56" to ptr
store i32 %"57", ptr %"66", align 4
ret void
}

36
ptx/src/test/ll/ld_st.ll
View file

@ -1,25 +1,25 @@
define amdgpu_kernel void @ld_st(ptr addrspace(4) byref(i64) %"30", ptr addrspace(4) byref(i64) %"31") #0 {
%"32" = alloca i64, align 8, addrspace(5)
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @ld_st(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"29"
br label %"32"
"29": ; preds = %1
%"35" = load i64, ptr addrspace(4) %"30", align 8
store i64 %"35", ptr addrspace(5) %"32", align 8
%"36" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"36", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(5) %"32", align 8
%"41" = inttoptr i64 %"38" to ptr
%"37" = load i64, ptr %"41", align 8
store i64 %"37", ptr addrspace(5) %"34", align 8
%"39" = load i64, ptr addrspace(5) %"33", align 8
%"40" = load i64, ptr addrspace(5) %"34", align 8
%"42" = inttoptr i64 %"39" to ptr
store i64 %"40", ptr %"42", align 8
"32": ; preds = %1
%"38" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"38", ptr addrspace(5) %"35", align 8
%"39" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"39", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(5) %"35", align 8
%"44" = inttoptr i64 %"41" to ptr
%"40" = load i64, ptr %"44", align 8
store i64 %"40", ptr addrspace(5) %"37", align 8
%"42" = load i64, ptr addrspace(5) %"36", align 8
%"43" = load i64, ptr addrspace(5) %"37", align 8
%"45" = inttoptr i64 %"42" to ptr
store i64 %"43", ptr %"45", align 8
ret void
}

46
ptx/src/test/ll/ld_st_implicit.ll
View file

@ -1,30 +1,30 @@
define amdgpu_kernel void @ld_st_implicit(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #0 {
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @ld_st_implicit(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"30"
br label %"33"
"30": ; preds = %1
%"36" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"36", ptr addrspace(5) %"33", align 8
%"37" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"37", ptr addrspace(5) %"34", align 8
store i64 81985529216486895, ptr addrspace(5) %"35", align 8
%"40" = load i64, ptr addrspace(5) %"33", align 8
%"44" = inttoptr i64 %"40" to ptr addrspace(1)
%"43" = load float, ptr addrspace(1) %"44", align 4
%2 = bitcast float %"43" to i32
%"39" = zext i32 %2 to i64
store i64 %"39", ptr addrspace(5) %"35", align 8
%"41" = load i64, ptr addrspace(5) %"34", align 8
%"42" = load i64, ptr addrspace(5) %"35", align 8
%"45" = inttoptr i64 %"41" to ptr addrspace(1)
%3 = trunc i64 %"42" to i32
%"46" = bitcast i32 %3 to float
store float %"46", ptr addrspace(1) %"45", align 4
"33": ; preds = %1
%"39" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"39", ptr addrspace(5) %"36", align 8
%"40" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"40", ptr addrspace(5) %"37", align 8
store i64 81985529216486895, ptr addrspace(5) %"38", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"47" = inttoptr i64 %"43" to ptr addrspace(1)
%"46" = load float, ptr addrspace(1) %"47", align 4
%2 = bitcast float %"46" to i32
%"42" = zext i32 %2 to i64
store i64 %"42", ptr addrspace(5) %"38", align 8
%"44" = load i64, ptr addrspace(5) %"37", align 8
%"45" = load i64, ptr addrspace(5) %"38", align 8
%"48" = inttoptr i64 %"44" to ptr addrspace(1)
%3 = trunc i64 %"45" to i32
%"49" = bitcast i32 %3 to float
store float %"49", ptr addrspace(1) %"48", align 4
ret void
}

58
ptx/src/test/ll/ld_st_offset.ll
View file

@ -1,36 +1,36 @@
define amdgpu_kernel void @ld_st_offset(ptr addrspace(4) byref(i64) %"35", ptr addrspace(4) byref(i64) %"36") #0 {
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i32, align 4, addrspace(5)
%"40" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @ld_st_offset(ptr addrspace(4) byref(i64) %"38", ptr addrspace(4) byref(i64) %"39") #0 {
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i32, align 4, addrspace(5)
%"43" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"34"
br label %"37"
"34": ; preds = %1
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"44" = load i64, ptr addrspace(5) %"37", align 8
%"51" = inttoptr i64 %"44" to ptr
%"43" = load i32, ptr %"51", align 4
store i32 %"43", ptr addrspace(5) %"39", align 4
%"45" = load i64, ptr addrspace(5) %"37", align 8
%"52" = inttoptr i64 %"45" to ptr
%"31" = getelementptr inbounds i8, ptr %"52", i64 4
%"46" = load i32, ptr %"31", align 4
store i32 %"46", ptr addrspace(5) %"40", align 4
%"47" = load i64, ptr addrspace(5) %"38", align 8
%"48" = load i32, ptr addrspace(5) %"40", align 4
%"53" = inttoptr i64 %"47" to ptr
store i32 %"48", ptr %"53", align 4
%"49" = load i64, ptr addrspace(5) %"38", align 8
%"54" = inttoptr i64 %"49" to ptr
%"33" = getelementptr inbounds i8, ptr %"54", i64 4
%"50" = load i32, ptr addrspace(5) %"39", align 4
store i32 %"50", ptr %"33", align 4
"37": ; preds = %1
%"44" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"44", ptr addrspace(5) %"40", align 8
%"45" = load i64, ptr addrspace(4) %"39", align 8
store i64 %"45", ptr addrspace(5) %"41", align 8
%"47" = load i64, ptr addrspace(5) %"40", align 8
%"54" = inttoptr i64 %"47" to ptr
%"46" = load i32, ptr %"54", align 4
store i32 %"46", ptr addrspace(5) %"42", align 4
%"48" = load i64, ptr addrspace(5) %"40", align 8
%"55" = inttoptr i64 %"48" to ptr
%"34" = getelementptr inbounds i8, ptr %"55", i64 4
%"49" = load i32, ptr %"34", align 4
store i32 %"49", ptr addrspace(5) %"43", align 4
%"50" = load i64, ptr addrspace(5) %"41", align 8
%"51" = load i32, ptr addrspace(5) %"43", align 4
%"56" = inttoptr i64 %"50" to ptr
store i32 %"51", ptr %"56", align 4
%"52" = load i64, ptr addrspace(5) %"41", align 8
%"57" = inttoptr i64 %"52" to ptr
%"36" = getelementptr inbounds i8, ptr %"57", i64 4
%"53" = load i32, ptr addrspace(5) %"42", align 4
store i32 %"53", ptr %"36", align 4
ret void
}

42
ptx/src/test/ll/lg2.ll
View file

@ -1,30 +1,30 @@
declare hidden float @__zluda_ptx_impl_lg2_approx_f32(float) #0
define amdgpu_kernel void @lg2(ptr addrspace(4) byref(i64) %"30", ptr addrspace(4) byref(i64) %"31") #1 {
%"32" = alloca i64, align 8, addrspace(5)
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca float, align 4, addrspace(5)
define amdgpu_kernel void @lg2(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #1 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca float, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"29"
br label %"32"
"29": ; preds = %1
%"35" = load i64, ptr addrspace(4) %"30", align 8
store i64 %"35", ptr addrspace(5) %"32", align 8
%"36" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"36", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(5) %"32", align 8
%"43" = inttoptr i64 %"38" to ptr
%"37" = load float, ptr %"43", align 4
store float %"37", ptr addrspace(5) %"34", align 4
%"40" = load float, ptr addrspace(5) %"34", align 4
%"39" = call float @__zluda_ptx_impl_lg2_approx_f32(float %"40")
store float %"39", ptr addrspace(5) %"34", align 4
%"41" = load i64, ptr addrspace(5) %"33", align 8
%"42" = load float, ptr addrspace(5) %"34", align 4
%"44" = inttoptr i64 %"41" to ptr
store float %"42", ptr %"44", align 4
"32": ; preds = %1
%"38" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"38", ptr addrspace(5) %"35", align 8
%"39" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"39", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(5) %"35", align 8
%"46" = inttoptr i64 %"41" to ptr
%"40" = load float, ptr %"46", align 4
store float %"40", ptr addrspace(5) %"37", align 4
%"43" = load float, ptr addrspace(5) %"37", align 4
%"42" = call float @__zluda_ptx_impl_lg2_approx_f32(float %"43")
store float %"42", ptr addrspace(5) %"37", align 4
%"44" = load i64, ptr addrspace(5) %"36", align 8
%"45" = load float, ptr addrspace(5) %"37", align 4
%"47" = inttoptr i64 %"44" to ptr
store float %"45", ptr %"47", align 4
ret void
}

38
ptx/src/test/ll/local_align.ll
View file

@ -1,26 +1,26 @@
define amdgpu_kernel void @local_align(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #0 {
%"10" = alloca [8 x i8], align 8, addrspace(5)
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @local_align(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"11" = alloca [8 x i8], align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"30"
br label %"33"
"30": ; preds = %1
%"36" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"36", ptr addrspace(5) %"33", align 8
%"37" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"37", ptr addrspace(5) %"34", align 8
%"39" = load i64, ptr addrspace(5) %"33", align 8
%"42" = inttoptr i64 %"39" to ptr
%"38" = load i64, ptr %"42", align 8
store i64 %"38", ptr addrspace(5) %"35", align 8
%"40" = load i64, ptr addrspace(5) %"34", align 8
%"41" = load i64, ptr addrspace(5) %"35", align 8
%"43" = inttoptr i64 %"40" to ptr
store i64 %"41", ptr %"43", align 8
"33": ; preds = %1
%"39" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"39", ptr addrspace(5) %"36", align 8
%"40" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"40", ptr addrspace(5) %"37", align 8
%"42" = load i64, ptr addrspace(5) %"36", align 8
%"45" = inttoptr i64 %"42" to ptr
%"41" = load i64, ptr %"45", align 8
store i64 %"41", ptr addrspace(5) %"38", align 8
%"43" = load i64, ptr addrspace(5) %"37", align 8
%"44" = load i64, ptr addrspace(5) %"38", align 8
%"46" = inttoptr i64 %"43" to ptr
store i64 %"44", ptr %"46", align 8
ret void
}

72
ptx/src/test/ll/mad_s32.ll
View file

@ -1,44 +1,44 @@
define amdgpu_kernel void @mad_s32(ptr addrspace(4) byref(i64) %"37", ptr addrspace(4) byref(i64) %"38") #0 {
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i32, align 4, addrspace(5)
%"42" = alloca i32, align 4, addrspace(5)
%"43" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @mad_s32(ptr addrspace(4) byref(i64) %"40", ptr addrspace(4) byref(i64) %"41") #0 {
%"42" = alloca i64, align 8, addrspace(5)
%"43" = alloca i64, align 8, addrspace(5)
%"44" = alloca i32, align 4, addrspace(5)
%"45" = alloca i32, align 4, addrspace(5)
%"46" = alloca i32, align 4, addrspace(5)
%"47" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"36"
br label %"39"
"36": ; preds = %1
%"45" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"45", ptr addrspace(5) %"39", align 8
%"46" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"46", ptr addrspace(5) %"40", align 8
%"48" = load i64, ptr addrspace(5) %"39", align 8
%"59" = inttoptr i64 %"48" to ptr
%"47" = load i32, ptr %"59", align 4
store i32 %"47", ptr addrspace(5) %"42", align 4
%"49" = load i64, ptr addrspace(5) %"39", align 8
%"60" = inttoptr i64 %"49" to ptr
%"33" = getelementptr inbounds i8, ptr %"60", i64 4
%"50" = load i32, ptr %"33", align 4
store i32 %"50", ptr addrspace(5) %"43", align 4
%"51" = load i64, ptr addrspace(5) %"39", align 8
%"61" = inttoptr i64 %"51" to ptr
%"35" = getelementptr inbounds i8, ptr %"61", i64 8
%"52" = load i32, ptr %"35", align 4
store i32 %"52", ptr addrspace(5) %"44", align 4
%"54" = load i32, ptr addrspace(5) %"42", align 4
%"55" = load i32, ptr addrspace(5) %"43", align 4
%"56" = load i32, ptr addrspace(5) %"44", align 4
%2 = mul i32 %"54", %"55"
%"53" = add i32 %2, %"56"
store i32 %"53", ptr addrspace(5) %"41", align 4
%"57" = load i64, ptr addrspace(5) %"40", align 8
%"58" = load i32, ptr addrspace(5) %"41", align 4
%"62" = inttoptr i64 %"57" to ptr
store i32 %"58", ptr %"62", align 4
"39": ; preds = %1
%"48" = load i64, ptr addrspace(4) %"40", align 8
store i64 %"48", ptr addrspace(5) %"42", align 8
%"49" = load i64, ptr addrspace(4) %"41", align 8
store i64 %"49", ptr addrspace(5) %"43", align 8
%"51" = load i64, ptr addrspace(5) %"42", align 8
%"62" = inttoptr i64 %"51" to ptr
%"50" = load i32, ptr %"62", align 4
store i32 %"50", ptr addrspace(5) %"45", align 4
%"52" = load i64, ptr addrspace(5) %"42", align 8
%"63" = inttoptr i64 %"52" to ptr
%"36" = getelementptr inbounds i8, ptr %"63", i64 4
%"53" = load i32, ptr %"36", align 4
store i32 %"53", ptr addrspace(5) %"46", align 4
%"54" = load i64, ptr addrspace(5) %"42", align 8
%"64" = inttoptr i64 %"54" to ptr
%"38" = getelementptr inbounds i8, ptr %"64", i64 8
%"55" = load i32, ptr %"38", align 4
store i32 %"55", ptr addrspace(5) %"47", align 4
%"57" = load i32, ptr addrspace(5) %"45", align 4
%"58" = load i32, ptr addrspace(5) %"46", align 4
%"59" = load i32, ptr addrspace(5) %"47", align 4
%2 = mul i32 %"57", %"58"
%"56" = add i32 %2, %"59"
store i32 %"56", ptr addrspace(5) %"44", align 4
%"60" = load i64, ptr addrspace(5) %"43", align 8
%"61" = load i32, ptr addrspace(5) %"44", align 4
%"65" = inttoptr i64 %"60" to ptr
store i32 %"61", ptr %"65", align 4
ret void
}

74
ptx/src/test/ll/mad_wide.ll
View file

@ -1,46 +1,46 @@
define amdgpu_kernel void @mad_wide(ptr addrspace(4) byref(i64) %"37", ptr addrspace(4) byref(i64) %"38") #0 {
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i32, align 4, addrspace(5)
%"43" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @mad_wide(ptr addrspace(4) byref(i64) %"40", ptr addrspace(4) byref(i64) %"41") #0 {
%"42" = alloca i64, align 8, addrspace(5)
%"43" = alloca i64, align 8, addrspace(5)
%"44" = alloca i64, align 8, addrspace(5)
%"45" = alloca i32, align 4, addrspace(5)
%"46" = alloca i32, align 4, addrspace(5)
%"47" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"36"
br label %"39"
"36": ; preds = %1
%"45" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"45", ptr addrspace(5) %"39", align 8
%"46" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"46", ptr addrspace(5) %"40", align 8
%"48" = load i64, ptr addrspace(5) %"39", align 8
%"59" = inttoptr i64 %"48" to ptr
%"47" = load i32, ptr %"59", align 4
store i32 %"47", ptr addrspace(5) %"42", align 4
%"49" = load i64, ptr addrspace(5) %"39", align 8
%"60" = inttoptr i64 %"49" to ptr
%"33" = getelementptr inbounds i8, ptr %"60", i64 4
%"50" = load i32, ptr %"33", align 4
store i32 %"50", ptr addrspace(5) %"43", align 4
%"51" = load i64, ptr addrspace(5) %"39", align 8
%"61" = inttoptr i64 %"51" to ptr
%"35" = getelementptr inbounds i8, ptr %"61", i64 8
%"52" = load i64, ptr %"35", align 8
store i64 %"52", ptr addrspace(5) %"44", align 8
%"54" = load i32, ptr addrspace(5) %"42", align 4
%"55" = load i32, ptr addrspace(5) %"43", align 4
%"56" = load i64, ptr addrspace(5) %"44", align 8
%2 = sext i32 %"54" to i64
%3 = sext i32 %"55" to i64
"39": ; preds = %1
%"48" = load i64, ptr addrspace(4) %"40", align 8
store i64 %"48", ptr addrspace(5) %"42", align 8
%"49" = load i64, ptr addrspace(4) %"41", align 8
store i64 %"49", ptr addrspace(5) %"43", align 8
%"51" = load i64, ptr addrspace(5) %"42", align 8
%"62" = inttoptr i64 %"51" to ptr
%"50" = load i32, ptr %"62", align 4
store i32 %"50", ptr addrspace(5) %"45", align 4
%"52" = load i64, ptr addrspace(5) %"42", align 8
%"63" = inttoptr i64 %"52" to ptr
%"36" = getelementptr inbounds i8, ptr %"63", i64 4
%"53" = load i32, ptr %"36", align 4
store i32 %"53", ptr addrspace(5) %"46", align 4
%"54" = load i64, ptr addrspace(5) %"42", align 8
%"64" = inttoptr i64 %"54" to ptr
%"38" = getelementptr inbounds i8, ptr %"64", i64 8
%"55" = load i64, ptr %"38", align 8
store i64 %"55", ptr addrspace(5) %"47", align 8
%"57" = load i32, ptr addrspace(5) %"45", align 4
%"58" = load i32, ptr addrspace(5) %"46", align 4
%"59" = load i64, ptr addrspace(5) %"47", align 8
%2 = sext i32 %"57" to i64
%3 = sext i32 %"58" to i64
%4 = mul i64 %2, %3
%"53" = add i64 %4, %"56"
store i64 %"53", ptr addrspace(5) %"41", align 8
%"57" = load i64, ptr addrspace(5) %"40", align 8
%"58" = load i64, ptr addrspace(5) %"41", align 8
%"62" = inttoptr i64 %"57" to ptr
store i64 %"58", ptr %"62", align 8
%"56" = add i64 %4, %"59"
store i64 %"56", ptr addrspace(5) %"44", align 8
%"60" = load i64, ptr addrspace(5) %"43", align 8
%"61" = load i64, ptr addrspace(5) %"44", align 8
%"65" = inttoptr i64 %"60" to ptr
store i64 %"61", ptr %"65", align 8
ret void
}

46
ptx/src/test/ll/malformed_label.ll
View file

@ -1,32 +1,32 @@
define amdgpu_kernel void @malformed_label(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @malformed_label(ptr addrspace(4) byref(i64) %"37", ptr addrspace(4) byref(i64) %"38") #0 {
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"32"
br label %"35"
"32": ; preds = %1
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
br label %"10"
"35": ; preds = %1
%"43" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"44" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"44", ptr addrspace(5) %"40", align 8
br label %"11"
"10": ; preds = %"32"
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"48" = inttoptr i64 %"43" to ptr
%"42" = load i64, ptr %"48", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"45" = load i64, ptr addrspace(5) %"38", align 8
%"44" = add i64 %"45", 1
store i64 %"44", ptr addrspace(5) %"39", align 8
%"46" = load i64, ptr addrspace(5) %"37", align 8
%"47" = load i64, ptr addrspace(5) %"39", align 8
%"49" = inttoptr i64 %"46" to ptr
store i64 %"47", ptr %"49", align 8
"11": ; preds = %"35"
%"46" = load i64, ptr addrspace(5) %"39", align 8
%"51" = inttoptr i64 %"46" to ptr
%"45" = load i64, ptr %"51", align 8
store i64 %"45", ptr addrspace(5) %"41", align 8
%"48" = load i64, ptr addrspace(5) %"41", align 8
%"47" = add i64 %"48", 1
store i64 %"47", ptr addrspace(5) %"42", align 8
%"49" = load i64, ptr addrspace(5) %"40", align 8
%"50" = load i64, ptr addrspace(5) %"42", align 8
%"52" = inttoptr i64 %"49" to ptr
store i64 %"50", ptr %"52", align 8
ret void
}

56
ptx/src/test/ll/max.ll
View file

@ -1,35 +1,35 @@
define amdgpu_kernel void @max(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i32, align 4, addrspace(5)
%"38" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @max(ptr addrspace(4) byref(i64) %"36", ptr addrspace(4) byref(i64) %"37") #0 {
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i32, align 4, addrspace(5)
%"41" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"32"
br label %"35"
"32": ; preds = %1
%"39" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"39", ptr addrspace(5) %"35", align 8
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"42" = load i64, ptr addrspace(5) %"35", align 8
%"50" = inttoptr i64 %"42" to ptr
%"41" = load i32, ptr %"50", align 4
store i32 %"41", ptr addrspace(5) %"37", align 4
%"43" = load i64, ptr addrspace(5) %"35", align 8
%"51" = inttoptr i64 %"43" to ptr
%"31" = getelementptr inbounds i8, ptr %"51", i64 4
%"44" = load i32, ptr %"31", align 4
store i32 %"44", ptr addrspace(5) %"38", align 4
%"46" = load i32, ptr addrspace(5) %"37", align 4
%"47" = load i32, ptr addrspace(5) %"38", align 4
%"45" = call i32 @llvm.smax.i32(i32 %"46", i32 %"47")
store i32 %"45", ptr addrspace(5) %"37", align 4
%"48" = load i64, ptr addrspace(5) %"36", align 8
%"49" = load i32, ptr addrspace(5) %"37", align 4
%"52" = inttoptr i64 %"48" to ptr
store i32 %"49", ptr %"52", align 4
"35": ; preds = %1
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"43" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"45" = load i64, ptr addrspace(5) %"38", align 8
%"53" = inttoptr i64 %"45" to ptr
%"44" = load i32, ptr %"53", align 4
store i32 %"44", ptr addrspace(5) %"40", align 4
%"46" = load i64, ptr addrspace(5) %"38", align 8
%"54" = inttoptr i64 %"46" to ptr
%"34" = getelementptr inbounds i8, ptr %"54", i64 4
%"47" = load i32, ptr %"34", align 4
store i32 %"47", ptr addrspace(5) %"41", align 4
%"49" = load i32, ptr addrspace(5) %"40", align 4
%"50" = load i32, ptr addrspace(5) %"41", align 4
%"48" = call i32 @llvm.smax.i32(i32 %"49", i32 %"50")
store i32 %"48", ptr addrspace(5) %"40", align 4
%"51" = load i64, ptr addrspace(5) %"39", align 8
%"52" = load i32, ptr addrspace(5) %"40", align 4
%"55" = inttoptr i64 %"51" to ptr
store i32 %"52", ptr %"55", align 4
ret void
}

36
ptx/src/test/ll/membar.ll
View file

@ -1,26 +1,26 @@
define amdgpu_kernel void @membar(ptr addrspace(4) byref(i64) %"30", ptr addrspace(4) byref(i64) %"31") #0 {
%"32" = alloca i64, align 8, addrspace(5)
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @membar(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"29"
br label %"32"
"29": ; preds = %1
%"35" = load i64, ptr addrspace(4) %"30", align 8
store i64 %"35", ptr addrspace(5) %"32", align 8
%"36" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"36", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(5) %"32", align 8
%"42" = inttoptr i64 %"38" to ptr
%"41" = load i32, ptr %"42", align 4
store i32 %"41", ptr addrspace(5) %"34", align 4
"32": ; preds = %1
%"38" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"38", ptr addrspace(5) %"35", align 8
%"39" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"39", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(5) %"35", align 8
%"45" = inttoptr i64 %"41" to ptr
%"44" = load i32, ptr %"45", align 4
store i32 %"44", ptr addrspace(5) %"37", align 4
fence seq_cst
%"39" = load i64, ptr addrspace(5) %"33", align 8
%"40" = load i32, ptr addrspace(5) %"34", align 4
%"43" = inttoptr i64 %"39" to ptr
store i32 %"40", ptr %"43", align 4
%"42" = load i64, ptr addrspace(5) %"36", align 8
%"43" = load i32, ptr addrspace(5) %"37", align 4
%"46" = inttoptr i64 %"42" to ptr
store i32 %"43", ptr %"46", align 4
ret void
}

56
ptx/src/test/ll/min.ll
View file

@ -1,35 +1,35 @@
define amdgpu_kernel void @min(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i32, align 4, addrspace(5)
%"38" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @min(ptr addrspace(4) byref(i64) %"36", ptr addrspace(4) byref(i64) %"37") #0 {
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i32, align 4, addrspace(5)
%"41" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"32"
br label %"35"
"32": ; preds = %1
%"39" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"39", ptr addrspace(5) %"35", align 8
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"42" = load i64, ptr addrspace(5) %"35", align 8
%"50" = inttoptr i64 %"42" to ptr
%"41" = load i32, ptr %"50", align 4
store i32 %"41", ptr addrspace(5) %"37", align 4
%"43" = load i64, ptr addrspace(5) %"35", align 8
%"51" = inttoptr i64 %"43" to ptr
%"31" = getelementptr inbounds i8, ptr %"51", i64 4
%"44" = load i32, ptr %"31", align 4
store i32 %"44", ptr addrspace(5) %"38", align 4
%"46" = load i32, ptr addrspace(5) %"37", align 4
%"47" = load i32, ptr addrspace(5) %"38", align 4
%"45" = call i32 @llvm.smin.i32(i32 %"46", i32 %"47")
store i32 %"45", ptr addrspace(5) %"37", align 4
%"48" = load i64, ptr addrspace(5) %"36", align 8
%"49" = load i32, ptr addrspace(5) %"37", align 4
%"52" = inttoptr i64 %"48" to ptr
store i32 %"49", ptr %"52", align 4
"35": ; preds = %1
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"43" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"45" = load i64, ptr addrspace(5) %"38", align 8
%"53" = inttoptr i64 %"45" to ptr
%"44" = load i32, ptr %"53", align 4
store i32 %"44", ptr addrspace(5) %"40", align 4
%"46" = load i64, ptr addrspace(5) %"38", align 8
%"54" = inttoptr i64 %"46" to ptr
%"34" = getelementptr inbounds i8, ptr %"54", i64 4
%"47" = load i32, ptr %"34", align 4
store i32 %"47", ptr addrspace(5) %"41", align 4
%"49" = load i32, ptr addrspace(5) %"40", align 4
%"50" = load i32, ptr addrspace(5) %"41", align 4
%"48" = call i32 @llvm.smin.i32(i32 %"49", i32 %"50")
store i32 %"48", ptr addrspace(5) %"40", align 4
%"51" = load i64, ptr addrspace(5) %"39", align 8
%"52" = load i32, ptr addrspace(5) %"40", align 4
%"55" = inttoptr i64 %"51" to ptr
store i32 %"52", ptr %"55", align 4
ret void
}

40
ptx/src/test/ll/mov.ll
View file

@ -1,28 +1,28 @@
define amdgpu_kernel void @mov(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #0 {
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @mov(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"30"
br label %"33"
"30": ; preds = %1
%"37" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"37", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"38", ptr addrspace(5) %"34", align 8
%"40" = load i64, ptr addrspace(5) %"33", align 8
%"45" = inttoptr i64 %"40" to ptr
%"39" = load i64, ptr %"45", align 8
store i64 %"39", ptr addrspace(5) %"35", align 8
%"42" = load i64, ptr addrspace(5) %"35", align 8
store i64 %"42", ptr addrspace(5) %"36", align 8
%"43" = load i64, ptr addrspace(5) %"34", align 8
%"44" = load i64, ptr addrspace(5) %"36", align 8
%"46" = inttoptr i64 %"43" to ptr
store i64 %"44", ptr %"46", align 8
"33": ; preds = %1
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"48" = inttoptr i64 %"43" to ptr
%"42" = load i64, ptr %"48", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"45" = load i64, ptr addrspace(5) %"38", align 8
store i64 %"45", ptr addrspace(5) %"39", align 8
%"46" = load i64, ptr addrspace(5) %"37", align 8
%"47" = load i64, ptr addrspace(5) %"39", align 8
%"49" = inttoptr i64 %"46" to ptr
store i64 %"47", ptr %"49", align 8
ret void
}

14
ptx/src/test/ll/mov_address.ll
View file

@ -1,14 +1,14 @@
define amdgpu_kernel void @mov_address(ptr addrspace(4) byref(i64) %"29", ptr addrspace(4) byref(i64) %"30") #0 {
%"10" = alloca [8 x i8], align 1, addrspace(5)
%"31" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @mov_address(ptr addrspace(4) byref(i64) %"32", ptr addrspace(4) byref(i64) %"33") #0 {
%"11" = alloca [8 x i8], align 1, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"28"
br label %"31"
"28": ; preds = %1
%"33" = ptrtoint ptr addrspace(5) %"10" to i64
store i64 %"33", ptr addrspace(5) %"31", align 8
"31": ; preds = %1
%"36" = ptrtoint ptr addrspace(5) %"11" to i64
store i64 %"36", ptr addrspace(5) %"34", align 8
ret void
}

58
ptx/src/test/ll/mul24_hi_s32.ll
View file

@ -1,38 +1,38 @@
define amdgpu_kernel void @mul24_hi_s32(ptr addrspace(4) byref(i64) %"32", ptr addrspace(4) byref(i64) %"33") #0 {
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i32, align 4, addrspace(5)
%"37" = alloca i32, align 4, addrspace(5)
%"38" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @mul24_hi_s32(ptr addrspace(4) byref(i64) %"35", ptr addrspace(4) byref(i64) %"36") #0 {
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i32, align 4, addrspace(5)
%"40" = alloca i32, align 4, addrspace(5)
%"41" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"31"
br label %"34"
"31": ; preds = %1
%"39" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"39", ptr addrspace(5) %"34", align 8
%"40" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"40", ptr addrspace(5) %"35", align 8
%"42" = load i64, ptr addrspace(5) %"34", align 8
%"50" = inttoptr i64 %"42" to ptr
%"41" = load i32, ptr %"50", align 4
store i32 %"41", ptr addrspace(5) %"36", align 4
%"44" = load i32, ptr addrspace(5) %"36", align 4
%"43" = sub i32 0, %"44"
store i32 %"43", ptr addrspace(5) %"37", align 4
%"46" = load i32, ptr addrspace(5) %"37", align 4
%"47" = load i32, ptr addrspace(5) %"36", align 4
%2 = call i32 @llvm.amdgcn.mul.i24(i32 %"46", i32 %"47")
%3 = call i32 @llvm.amdgcn.mulhi.i24(i32 %"46", i32 %"47")
"34": ; preds = %1
%"42" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"42", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"43", ptr addrspace(5) %"38", align 8
%"45" = load i64, ptr addrspace(5) %"37", align 8
%"53" = inttoptr i64 %"45" to ptr
%"44" = load i32, ptr %"53", align 4
store i32 %"44", ptr addrspace(5) %"39", align 4
%"47" = load i32, ptr addrspace(5) %"39", align 4
%"46" = sub i32 0, %"47"
store i32 %"46", ptr addrspace(5) %"40", align 4
%"49" = load i32, ptr addrspace(5) %"40", align 4
%"50" = load i32, ptr addrspace(5) %"39", align 4
%2 = call i32 @llvm.amdgcn.mul.i24(i32 %"49", i32 %"50")
%3 = call i32 @llvm.amdgcn.mulhi.i24(i32 %"49", i32 %"50")
%4 = lshr i32 %2, 16
%5 = shl i32 %3, 16
%"45" = or i32 %4, %5
store i32 %"45", ptr addrspace(5) %"38", align 4
%"48" = load i64, ptr addrspace(5) %"35", align 8
%"49" = load i32, ptr addrspace(5) %"38", align 4
%"51" = inttoptr i64 %"48" to ptr
store i32 %"49", ptr %"51", align 4
%"48" = or i32 %4, %5
store i32 %"48", ptr addrspace(5) %"41", align 4
%"51" = load i64, ptr addrspace(5) %"38", align 8
%"52" = load i32, ptr addrspace(5) %"41", align 4
%"54" = inttoptr i64 %"51" to ptr
store i32 %"52", ptr %"54", align 4
ret void
}

50
ptx/src/test/ll/mul24_hi_u32.ll
View file

@ -1,34 +1,34 @@
define amdgpu_kernel void @mul24_hi_u32(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #0 {
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i32, align 4, addrspace(5)
%"36" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @mul24_hi_u32(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i32, align 4, addrspace(5)
%"39" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"30"
br label %"33"
"30": ; preds = %1
%"37" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"37", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"38", ptr addrspace(5) %"34", align 8
%"40" = load i64, ptr addrspace(5) %"33", align 8
%"46" = inttoptr i64 %"40" to ptr
%"39" = load i32, ptr %"46", align 4
store i32 %"39", ptr addrspace(5) %"35", align 4
%"42" = load i32, ptr addrspace(5) %"35", align 4
%"43" = load i32, ptr addrspace(5) %"35", align 4
%2 = call i32 @llvm.amdgcn.mul.u24(i32 %"42", i32 %"43")
%3 = call i32 @llvm.amdgcn.mulhi.u24(i32 %"42", i32 %"43")
"33": ; preds = %1
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"49" = inttoptr i64 %"43" to ptr
%"42" = load i32, ptr %"49", align 4
store i32 %"42", ptr addrspace(5) %"38", align 4
%"45" = load i32, ptr addrspace(5) %"38", align 4
%"46" = load i32, ptr addrspace(5) %"38", align 4
%2 = call i32 @llvm.amdgcn.mul.u24(i32 %"45", i32 %"46")
%3 = call i32 @llvm.amdgcn.mulhi.u24(i32 %"45", i32 %"46")
%4 = lshr i32 %2, 16
%5 = shl i32 %3, 16
%"41" = or i32 %4, %5
store i32 %"41", ptr addrspace(5) %"36", align 4
%"44" = load i64, ptr addrspace(5) %"34", align 8
%"45" = load i32, ptr addrspace(5) %"36", align 4
%"47" = inttoptr i64 %"44" to ptr
store i32 %"45", ptr %"47", align 4
%"44" = or i32 %4, %5
store i32 %"44", ptr addrspace(5) %"39", align 4
%"47" = load i64, ptr addrspace(5) %"37", align 8
%"48" = load i32, ptr addrspace(5) %"39", align 4
%"50" = inttoptr i64 %"47" to ptr
store i32 %"48", ptr %"50", align 4
ret void
}

54
ptx/src/test/ll/mul24_lo_s32.ll
View file

@ -1,34 +1,34 @@
define amdgpu_kernel void @mul24_lo_s32(ptr addrspace(4) byref(i64) %"32", ptr addrspace(4) byref(i64) %"33") #0 {
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i32, align 4, addrspace(5)
%"37" = alloca i32, align 4, addrspace(5)
%"38" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @mul24_lo_s32(ptr addrspace(4) byref(i64) %"35", ptr addrspace(4) byref(i64) %"36") #0 {
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i32, align 4, addrspace(5)
%"40" = alloca i32, align 4, addrspace(5)
%"41" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"31"
br label %"34"
"31": ; preds = %1
%"39" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"39", ptr addrspace(5) %"34", align 8
%"40" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"40", ptr addrspace(5) %"35", align 8
%"42" = load i64, ptr addrspace(5) %"34", align 8
%"50" = inttoptr i64 %"42" to ptr
%"41" = load i32, ptr %"50", align 4
store i32 %"41", ptr addrspace(5) %"36", align 4
%"44" = load i32, ptr addrspace(5) %"36", align 4
%"43" = sub i32 0, %"44"
store i32 %"43", ptr addrspace(5) %"37", align 4
%"46" = load i32, ptr addrspace(5) %"37", align 4
%"47" = load i32, ptr addrspace(5) %"36", align 4
%"45" = call i32 @llvm.amdgcn.mul.i24(i32 %"46", i32 %"47")
store i32 %"45", ptr addrspace(5) %"38", align 4
%"48" = load i64, ptr addrspace(5) %"35", align 8
%"49" = load i32, ptr addrspace(5) %"38", align 4
%"51" = inttoptr i64 %"48" to ptr
store i32 %"49", ptr %"51", align 4
"34": ; preds = %1
%"42" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"42", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"43", ptr addrspace(5) %"38", align 8
%"45" = load i64, ptr addrspace(5) %"37", align 8
%"53" = inttoptr i64 %"45" to ptr
%"44" = load i32, ptr %"53", align 4
store i32 %"44", ptr addrspace(5) %"39", align 4
%"47" = load i32, ptr addrspace(5) %"39", align 4
%"46" = sub i32 0, %"47"
store i32 %"46", ptr addrspace(5) %"40", align 4
%"49" = load i32, ptr addrspace(5) %"40", align 4
%"50" = load i32, ptr addrspace(5) %"39", align 4
%"48" = call i32 @llvm.amdgcn.mul.i24(i32 %"49", i32 %"50")
store i32 %"48", ptr addrspace(5) %"41", align 4
%"51" = load i64, ptr addrspace(5) %"38", align 8
%"52" = load i32, ptr addrspace(5) %"41", align 4
%"54" = inttoptr i64 %"51" to ptr
store i32 %"52", ptr %"54", align 4
ret void
}

46
ptx/src/test/ll/mul24_lo_u32.ll
View file

@ -1,30 +1,30 @@
define amdgpu_kernel void @mul24_lo_u32(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #0 {
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i32, align 4, addrspace(5)
%"36" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @mul24_lo_u32(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i32, align 4, addrspace(5)
%"39" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"30"
br label %"33"
"30": ; preds = %1
%"37" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"37", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"38", ptr addrspace(5) %"34", align 8
%"40" = load i64, ptr addrspace(5) %"33", align 8
%"46" = inttoptr i64 %"40" to ptr
%"39" = load i32, ptr %"46", align 4
store i32 %"39", ptr addrspace(5) %"35", align 4
%"42" = load i32, ptr addrspace(5) %"35", align 4
%"43" = load i32, ptr addrspace(5) %"35", align 4
%"41" = call i32 @llvm.amdgcn.mul.u24(i32 %"42", i32 %"43")
store i32 %"41", ptr addrspace(5) %"36", align 4
%"44" = load i64, ptr addrspace(5) %"34", align 8
%"45" = load i32, ptr addrspace(5) %"36", align 4
%"47" = inttoptr i64 %"44" to ptr
store i32 %"45", ptr %"47", align 4
"33": ; preds = %1
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"49" = inttoptr i64 %"43" to ptr
%"42" = load i32, ptr %"49", align 4
store i32 %"42", ptr addrspace(5) %"38", align 4
%"45" = load i32, ptr addrspace(5) %"38", align 4
%"46" = load i32, ptr addrspace(5) %"38", align 4
%"44" = call i32 @llvm.amdgcn.mul.u24(i32 %"45", i32 %"46")
store i32 %"44", ptr addrspace(5) %"39", align 4
%"47" = load i64, ptr addrspace(5) %"37", align 8
%"48" = load i32, ptr addrspace(5) %"39", align 4
%"50" = inttoptr i64 %"47" to ptr
store i32 %"48", ptr %"50", align 4
ret void
}

56
ptx/src/test/ll/mul_ftz.ll
View file

@ -1,35 +1,35 @@
define amdgpu_kernel void @mul_ftz(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca float, align 4, addrspace(5)
%"38" = alloca float, align 4, addrspace(5)
define amdgpu_kernel void @mul_ftz(ptr addrspace(4) byref(i64) %"36", ptr addrspace(4) byref(i64) %"37") #0 {
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca float, align 4, addrspace(5)
%"41" = alloca float, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"32"
br label %"35"
"32": ; preds = %1
%"39" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"39", ptr addrspace(5) %"35", align 8
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"42" = load i64, ptr addrspace(5) %"35", align 8
%"50" = inttoptr i64 %"42" to ptr
%"41" = load float, ptr %"50", align 4
store float %"41", ptr addrspace(5) %"37", align 4
%"43" = load i64, ptr addrspace(5) %"35", align 8
%"51" = inttoptr i64 %"43" to ptr
%"31" = getelementptr inbounds i8, ptr %"51", i64 4
%"44" = load float, ptr %"31", align 4
store float %"44", ptr addrspace(5) %"38", align 4
%"46" = load float, ptr addrspace(5) %"37", align 4
%"47" = load float, ptr addrspace(5) %"38", align 4
%"45" = fmul float %"46", %"47"
store float %"45", ptr addrspace(5) %"37", align 4
%"48" = load i64, ptr addrspace(5) %"36", align 8
%"49" = load float, ptr addrspace(5) %"37", align 4
%"52" = inttoptr i64 %"48" to ptr
store float %"49", ptr %"52", align 4
"35": ; preds = %1
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"43" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"45" = load i64, ptr addrspace(5) %"38", align 8
%"53" = inttoptr i64 %"45" to ptr
%"44" = load float, ptr %"53", align 4
store float %"44", ptr addrspace(5) %"40", align 4
%"46" = load i64, ptr addrspace(5) %"38", align 8
%"54" = inttoptr i64 %"46" to ptr
%"34" = getelementptr inbounds i8, ptr %"54", i64 4
%"47" = load float, ptr %"34", align 4
store float %"47", ptr addrspace(5) %"41", align 4
%"49" = load float, ptr addrspace(5) %"40", align 4
%"50" = load float, ptr addrspace(5) %"41", align 4
%"48" = fmul float %"49", %"50"
store float %"48", ptr addrspace(5) %"40", align 4
%"51" = load i64, ptr addrspace(5) %"39", align 8
%"52" = load float, ptr addrspace(5) %"40", align 4
%"55" = inttoptr i64 %"51" to ptr
store float %"52", ptr %"55", align 4
ret void
}

44
ptx/src/test/ll/mul_hi.ll
View file

@ -1,32 +1,32 @@
define amdgpu_kernel void @mul_hi(ptr addrspace(4) byref(i64) %"32", ptr addrspace(4) byref(i64) %"33") #0 {
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @mul_hi(ptr addrspace(4) byref(i64) %"35", ptr addrspace(4) byref(i64) %"36") #0 {
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"31"
br label %"34"
"31": ; preds = %1
%"38" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"38", ptr addrspace(5) %"34", align 8
%"39" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"39", ptr addrspace(5) %"35", align 8
%"41" = load i64, ptr addrspace(5) %"34", align 8
%"46" = inttoptr i64 %"41" to ptr
%"40" = load i64, ptr %"46", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%2 = zext i64 %"43" to i128
"34": ; preds = %1
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"44" = load i64, ptr addrspace(5) %"37", align 8
%"49" = inttoptr i64 %"44" to ptr
%"43" = load i64, ptr %"49", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"46" = load i64, ptr addrspace(5) %"39", align 8
%2 = zext i64 %"46" to i128
%3 = mul i128 %2, 2
%4 = lshr i128 %3, 64
%"42" = trunc i128 %4 to i64
store i64 %"42", ptr addrspace(5) %"37", align 8
%"44" = load i64, ptr addrspace(5) %"35", align 8
%"45" = load i64, ptr addrspace(5) %"37", align 8
%"47" = inttoptr i64 %"44" to ptr
store i64 %"45", ptr %"47", align 8
%"45" = trunc i128 %4 to i64
store i64 %"45", ptr addrspace(5) %"40", align 8
%"47" = load i64, ptr addrspace(5) %"38", align 8
%"48" = load i64, ptr addrspace(5) %"40", align 8
%"50" = inttoptr i64 %"47" to ptr
store i64 %"48", ptr %"50", align 8
ret void
}

42
ptx/src/test/ll/mul_lo.ll
View file

@ -1,29 +1,29 @@
define amdgpu_kernel void @mul_lo(ptr addrspace(4) byref(i64) %"32", ptr addrspace(4) byref(i64) %"33") #0 {
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @mul_lo(ptr addrspace(4) byref(i64) %"35", ptr addrspace(4) byref(i64) %"36") #0 {
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"31"
br label %"34"
"31": ; preds = %1
%"38" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"38", ptr addrspace(5) %"34", align 8
%"39" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"39", ptr addrspace(5) %"35", align 8
%"41" = load i64, ptr addrspace(5) %"34", align 8
%"46" = inttoptr i64 %"41" to ptr
%"40" = load i64, ptr %"46", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"42" = mul i64 %"43", 2
store i64 %"42", ptr addrspace(5) %"37", align 8
%"44" = load i64, ptr addrspace(5) %"35", align 8
%"45" = load i64, ptr addrspace(5) %"37", align 8
%"47" = inttoptr i64 %"44" to ptr
store i64 %"45", ptr %"47", align 8
"34": ; preds = %1
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"44" = load i64, ptr addrspace(5) %"37", align 8
%"49" = inttoptr i64 %"44" to ptr
%"43" = load i64, ptr %"49", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"46" = load i64, ptr addrspace(5) %"39", align 8
%"45" = mul i64 %"46", 2
store i64 %"45", ptr addrspace(5) %"40", align 8
%"47" = load i64, ptr addrspace(5) %"38", align 8
%"48" = load i64, ptr addrspace(5) %"40", align 8
%"50" = inttoptr i64 %"47" to ptr
store i64 %"48", ptr %"50", align 8
ret void
}

56
ptx/src/test/ll/mul_non_ftz.ll
View file

@ -1,35 +1,35 @@
define amdgpu_kernel void @mul_non_ftz(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca float, align 4, addrspace(5)
%"38" = alloca float, align 4, addrspace(5)
define amdgpu_kernel void @mul_non_ftz(ptr addrspace(4) byref(i64) %"36", ptr addrspace(4) byref(i64) %"37") #0 {
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca float, align 4, addrspace(5)
%"41" = alloca float, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"32"
br label %"35"
"32": ; preds = %1
%"39" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"39", ptr addrspace(5) %"35", align 8
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"42" = load i64, ptr addrspace(5) %"35", align 8
%"50" = inttoptr i64 %"42" to ptr
%"41" = load float, ptr %"50", align 4
store float %"41", ptr addrspace(5) %"37", align 4
%"43" = load i64, ptr addrspace(5) %"35", align 8
%"51" = inttoptr i64 %"43" to ptr
%"31" = getelementptr inbounds i8, ptr %"51", i64 4
%"44" = load float, ptr %"31", align 4
store float %"44", ptr addrspace(5) %"38", align 4
%"46" = load float, ptr addrspace(5) %"37", align 4
%"47" = load float, ptr addrspace(5) %"38", align 4
%"45" = fmul float %"46", %"47"
store float %"45", ptr addrspace(5) %"37", align 4
%"48" = load i64, ptr addrspace(5) %"36", align 8
%"49" = load float, ptr addrspace(5) %"37", align 4
%"52" = inttoptr i64 %"48" to ptr
store float %"49", ptr %"52", align 4
"35": ; preds = %1
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"43" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"45" = load i64, ptr addrspace(5) %"38", align 8
%"53" = inttoptr i64 %"45" to ptr
%"44" = load float, ptr %"53", align 4
store float %"44", ptr addrspace(5) %"40", align 4
%"46" = load i64, ptr addrspace(5) %"38", align 8
%"54" = inttoptr i64 %"46" to ptr
%"34" = getelementptr inbounds i8, ptr %"54", i64 4
%"47" = load float, ptr %"34", align 4
store float %"47", ptr addrspace(5) %"41", align 4
%"49" = load float, ptr addrspace(5) %"40", align 4
%"50" = load float, ptr addrspace(5) %"41", align 4
%"48" = fmul float %"49", %"50"
store float %"48", ptr addrspace(5) %"40", align 4
%"51" = load i64, ptr addrspace(5) %"39", align 8
%"52" = load float, ptr addrspace(5) %"40", align 4
%"55" = inttoptr i64 %"51" to ptr
store float %"52", ptr %"55", align 4
ret void
}

60
ptx/src/test/ll/mul_wide.ll
View file

@ -1,38 +1,38 @@
define amdgpu_kernel void @mul_wide(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i32, align 4, addrspace(5)
%"39" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @mul_wide(ptr addrspace(4) byref(i64) %"37", ptr addrspace(4) byref(i64) %"38") #0 {
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i32, align 4, addrspace(5)
%"42" = alloca i32, align 4, addrspace(5)
%"43" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"33"
br label %"36"
"33": ; preds = %1
%"41" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"41", ptr addrspace(5) %"36", align 8
%"42" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"42", ptr addrspace(5) %"37", align 8
%"44" = load i64, ptr addrspace(5) %"36", align 8
%"52" = inttoptr i64 %"44" to ptr addrspace(1)
%"43" = load i32, ptr addrspace(1) %"52", align 4
store i32 %"43", ptr addrspace(5) %"38", align 4
%"45" = load i64, ptr addrspace(5) %"36", align 8
%"53" = inttoptr i64 %"45" to ptr addrspace(1)
%"32" = getelementptr inbounds i8, ptr addrspace(1) %"53", i64 4
%"46" = load i32, ptr addrspace(1) %"32", align 4
store i32 %"46", ptr addrspace(5) %"39", align 4
%"48" = load i32, ptr addrspace(5) %"38", align 4
%"49" = load i32, ptr addrspace(5) %"39", align 4
%2 = sext i32 %"48" to i64
%3 = sext i32 %"49" to i64
%"47" = mul i64 %2, %3
store i64 %"47", ptr addrspace(5) %"40", align 8
%"50" = load i64, ptr addrspace(5) %"37", align 8
%"51" = load i64, ptr addrspace(5) %"40", align 8
%"54" = inttoptr i64 %"50" to ptr
store i64 %"51", ptr %"54", align 8
"36": ; preds = %1
%"44" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"44", ptr addrspace(5) %"39", align 8
%"45" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"45", ptr addrspace(5) %"40", align 8
%"47" = load i64, ptr addrspace(5) %"39", align 8
%"55" = inttoptr i64 %"47" to ptr addrspace(1)
%"46" = load i32, ptr addrspace(1) %"55", align 4
store i32 %"46", ptr addrspace(5) %"41", align 4
%"48" = load i64, ptr addrspace(5) %"39", align 8
%"56" = inttoptr i64 %"48" to ptr addrspace(1)
%"35" = getelementptr inbounds i8, ptr addrspace(1) %"56", i64 4
%"49" = load i32, ptr addrspace(1) %"35", align 4
store i32 %"49", ptr addrspace(5) %"42", align 4
%"51" = load i32, ptr addrspace(5) %"41", align 4
%"52" = load i32, ptr addrspace(5) %"42", align 4
%2 = sext i32 %"51" to i64
%3 = sext i32 %"52" to i64
%"50" = mul i64 %2, %3
store i64 %"50", ptr addrspace(5) %"43", align 8
%"53" = load i64, ptr addrspace(5) %"40", align 8
%"54" = load i64, ptr addrspace(5) %"43", align 8
%"57" = inttoptr i64 %"53" to ptr
store i64 %"54", ptr %"57", align 8
ret void
}

94
ptx/src/test/ll/multiple_return.ll
View file

@ -1,68 +1,68 @@
%struct.i32.i1 = type { i32, i1 }
define hidden %struct.i32.i1 @do_something(i32 %"10") #0 {
%"46" = alloca i32, align 4, addrspace(5)
%"47" = alloca i1, align 1, addrspace(5)
define hidden %struct.i32.i1 @do_something(i32 %"11") #0 {
%"49" = alloca i32, align 4, addrspace(5)
%"50" = alloca i1, align 1, addrspace(5)
br label %1
1: ; preds = %0
br label %"43"
br label %"46"
"43": ; preds = %1
%"48" = add i32 %"10", 1
store i32 %"48", ptr addrspace(5) %"46", align 4
store i1 true, ptr addrspace(5) %"47", align 1
%2 = load i32, ptr addrspace(5) %"46", align 4
%3 = load i1, ptr addrspace(5) %"47", align 1
"46": ; preds = %1
%"51" = add i32 %"11", 1
store i32 %"51", ptr addrspace(5) %"49", align 4
store i1 true, ptr addrspace(5) %"50", align 1
%2 = load i32, ptr addrspace(5) %"49", align 4
%3 = load i1, ptr addrspace(5) %"50", align 1
%4 = insertvalue %struct.i32.i1 undef, i32 %2, 0
%5 = insertvalue %struct.i32.i1 %4, i1 %3, 1
ret %struct.i32.i1 %5
}
define amdgpu_kernel void @multiple_return(ptr addrspace(4) byref(i64) %"50", ptr addrspace(4) byref(i64) %"51") #1 {
%"52" = alloca i64, align 8, addrspace(5)
%"53" = alloca i64, align 8, addrspace(5)
%"54" = alloca i32, align 4, addrspace(5)
%"55" = alloca i32, align 4, addrspace(5)
%"56" = alloca i1, align 1, addrspace(5)
define amdgpu_kernel void @multiple_return(ptr addrspace(4) byref(i64) %"53", ptr addrspace(4) byref(i64) %"54") #1 {
%"55" = alloca i64, align 8, addrspace(5)
%"56" = alloca i64, align 8, addrspace(5)
%"57" = alloca i32, align 4, addrspace(5)
%"58" = alloca i32, align 4, addrspace(5)
%"59" = alloca i1, align 1, addrspace(5)
br label %1
1: ; preds = %0
br label %"44"
br label %"47"
"44": ; preds = %1
%"57" = load i64, ptr addrspace(4) %"50", align 8
store i64 %"57", ptr addrspace(5) %"52", align 8
%"58" = load i64, ptr addrspace(4) %"51", align 8
store i64 %"58", ptr addrspace(5) %"53", align 8
%"60" = load i64, ptr addrspace(5) %"52", align 8
%"68" = inttoptr i64 %"60" to ptr
%"59" = load i32, ptr %"68", align 4
store i32 %"59", ptr addrspace(5) %"54", align 4
%"63" = load i32, ptr addrspace(5) %"54", align 4
%2 = call %struct.i32.i1 @do_something(i32 %"63")
%"61" = extractvalue %struct.i32.i1 %2, 0
%"62" = extractvalue %struct.i32.i1 %2, 1
store i32 %"61", ptr addrspace(5) %"55", align 4
store i1 %"62", ptr addrspace(5) %"56", align 1
br label %"45"
"47": ; preds = %1
%"60" = load i64, ptr addrspace(4) %"53", align 8
store i64 %"60", ptr addrspace(5) %"55", align 8
%"61" = load i64, ptr addrspace(4) %"54", align 8
store i64 %"61", ptr addrspace(5) %"56", align 8
%"63" = load i64, ptr addrspace(5) %"55", align 8
%"71" = inttoptr i64 %"63" to ptr
%"62" = load i32, ptr %"71", align 4
store i32 %"62", ptr addrspace(5) %"57", align 4
%"66" = load i32, ptr addrspace(5) %"57", align 4
%2 = call %struct.i32.i1 @do_something(i32 %"66")
%"64" = extractvalue %struct.i32.i1 %2, 0
%"65" = extractvalue %struct.i32.i1 %2, 1
store i32 %"64", ptr addrspace(5) %"58", align 4
store i1 %"65", ptr addrspace(5) %"59", align 1
br label %"48"
"45": ; preds = %"44"
%"64" = load i64, ptr addrspace(5) %"53", align 8
%"65" = load i32, ptr addrspace(5) %"55", align 4
%"69" = inttoptr i64 %"64" to ptr
store i32 %"65", ptr %"69", align 4
%"66" = load i1, ptr addrspace(5) %"56", align 1
br i1 %"66", label %"19", label %"20"
"48": ; preds = %"47"
%"67" = load i64, ptr addrspace(5) %"56", align 8
%"68" = load i32, ptr addrspace(5) %"58", align 4
%"72" = inttoptr i64 %"67" to ptr
store i32 %"68", ptr %"72", align 4
%"69" = load i1, ptr addrspace(5) %"59", align 1
br i1 %"69", label %"20", label %"21"
"19": ; preds = %"45"
%"67" = load i64, ptr addrspace(5) %"53", align 8
%"70" = inttoptr i64 %"67" to ptr
%"41" = getelementptr inbounds i8, ptr %"70", i64 4
store i32 123, ptr %"41", align 4
br label %"20"
"20": ; preds = %"48"
%"70" = load i64, ptr addrspace(5) %"56", align 8
%"73" = inttoptr i64 %"70" to ptr
%"44" = getelementptr inbounds i8, ptr %"73", i64 4
store i32 123, ptr %"44", align 4
br label %"21"
"20": ; preds = %"19", %"45"
"21": ; preds = %"20", %"48"
ret void
}

6
ptx/src/test/ll/nanosleep.ll
View file

@ -1,12 +1,12 @@
declare hidden void @__zluda_ptx_impl_nanosleep_u32(i32) #0
define amdgpu_kernel void @nanosleep(ptr addrspace(4) byref(i64) %"28", ptr addrspace(4) byref(i64) %"29") #1 {
define amdgpu_kernel void @nanosleep(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #1 {
br label %1
1: ; preds = %0
br label %"27"
br label %"30"
"27": ; preds = %1
"30": ; preds = %1
call void @__zluda_ptx_impl_nanosleep_u32(i32 1)
ret void
}

42
ptx/src/test/ll/neg.ll
View file

@ -1,28 +1,28 @@
define amdgpu_kernel void @neg(ptr addrspace(4) byref(i64) %"30", ptr addrspace(4) byref(i64) %"31") #0 {
%"32" = alloca i64, align 8, addrspace(5)
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @neg(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"29"
br label %"32"
"29": ; preds = %1
%"35" = load i64, ptr addrspace(4) %"30", align 8
store i64 %"35", ptr addrspace(5) %"32", align 8
%"36" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"36", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(5) %"32", align 8
%"43" = inttoptr i64 %"38" to ptr
%"37" = load i32, ptr %"43", align 4
store i32 %"37", ptr addrspace(5) %"34", align 4
%"40" = load i32, ptr addrspace(5) %"34", align 4
%"39" = sub i32 0, %"40"
store i32 %"39", ptr addrspace(5) %"34", align 4
%"41" = load i64, ptr addrspace(5) %"33", align 8
%"42" = load i32, ptr addrspace(5) %"34", align 4
%"44" = inttoptr i64 %"41" to ptr
store i32 %"42", ptr %"44", align 4
"32": ; preds = %1
%"38" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"38", ptr addrspace(5) %"35", align 8
%"39" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"39", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(5) %"35", align 8
%"46" = inttoptr i64 %"41" to ptr
%"40" = load i32, ptr %"46", align 4
store i32 %"40", ptr addrspace(5) %"37", align 4
%"43" = load i32, ptr addrspace(5) %"37", align 4
%"42" = sub i32 0, %"43"
store i32 %"42", ptr addrspace(5) %"37", align 4
%"44" = load i64, ptr addrspace(5) %"36", align 8
%"45" = load i32, ptr addrspace(5) %"37", align 4
%"47" = inttoptr i64 %"44" to ptr
store i32 %"45", ptr %"47", align 4
ret void
}

54
ptx/src/test/ll/non_scalar_ptr_offset.ll
View file

@ -1,34 +1,34 @@
define amdgpu_kernel void @non_scalar_ptr_offset(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i32, align 4, addrspace(5)
%"39" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @non_scalar_ptr_offset(ptr addrspace(4) byref(i64) %"37", ptr addrspace(4) byref(i64) %"38") #0 {
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i32, align 4, addrspace(5)
%"42" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"33"
br label %"36"
"33": ; preds = %1
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"42" = load i64, ptr addrspace(5) %"36", align 8
%"50" = inttoptr i64 %"42" to ptr addrspace(1)
%"32" = getelementptr inbounds i8, ptr addrspace(1) %"50", i64 8
%"30" = load <2 x i32>, ptr addrspace(1) %"32", align 8
%"43" = extractelement <2 x i32> %"30", i8 0
%"44" = extractelement <2 x i32> %"30", i8 1
store i32 %"43", ptr addrspace(5) %"38", align 4
store i32 %"44", ptr addrspace(5) %"39", align 4
%"46" = load i32, ptr addrspace(5) %"38", align 4
%"47" = load i32, ptr addrspace(5) %"39", align 4
%"45" = add i32 %"46", %"47"
store i32 %"45", ptr addrspace(5) %"38", align 4
%"48" = load i64, ptr addrspace(5) %"37", align 8
%"49" = load i32, ptr addrspace(5) %"38", align 4
%"51" = inttoptr i64 %"48" to ptr addrspace(1)
store i32 %"49", ptr addrspace(1) %"51", align 4
"36": ; preds = %1
%"43" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"44" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"44", ptr addrspace(5) %"40", align 8
%"45" = load i64, ptr addrspace(5) %"39", align 8
%"53" = inttoptr i64 %"45" to ptr addrspace(1)
%"35" = getelementptr inbounds i8, ptr addrspace(1) %"53", i64 8
%"33" = load <2 x i32>, ptr addrspace(1) %"35", align 8
%"46" = extractelement <2 x i32> %"33", i8 0
%"47" = extractelement <2 x i32> %"33", i8 1
store i32 %"46", ptr addrspace(5) %"41", align 4
store i32 %"47", ptr addrspace(5) %"42", align 4
%"49" = load i32, ptr addrspace(5) %"41", align 4
%"50" = load i32, ptr addrspace(5) %"42", align 4
%"48" = add i32 %"49", %"50"
store i32 %"48", ptr addrspace(5) %"41", align 4
%"51" = load i64, ptr addrspace(5) %"40", align 8
%"52" = load i32, ptr addrspace(5) %"41", align 4
%"54" = inttoptr i64 %"51" to ptr addrspace(1)
store i32 %"52", ptr addrspace(1) %"54", align 4
ret void
}

40
ptx/src/test/ll/not.ll
View file

@ -1,29 +1,29 @@
define amdgpu_kernel void @not(ptr addrspace(4) byref(i64) %"31", ptr addrspace(4) byref(i64) %"32") #0 {
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @not(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"30"
br label %"33"
"30": ; preds = %1
%"37" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"37", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"38", ptr addrspace(5) %"34", align 8
%"40" = load i64, ptr addrspace(5) %"33", align 8
%"45" = inttoptr i64 %"40" to ptr
%"39" = load i64, ptr %"45", align 8
store i64 %"39", ptr addrspace(5) %"35", align 8
%"42" = load i64, ptr addrspace(5) %"35", align 8
%"46" = xor i64 %"42", -1
store i64 %"46", ptr addrspace(5) %"36", align 8
%"43" = load i64, ptr addrspace(5) %"34", align 8
%"44" = load i64, ptr addrspace(5) %"36", align 8
"33": ; preds = %1
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"48" = inttoptr i64 %"43" to ptr
store i64 %"44", ptr %"48", align 8
%"42" = load i64, ptr %"48", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"45" = load i64, ptr addrspace(5) %"38", align 8
%"49" = xor i64 %"45", -1
store i64 %"49", ptr addrspace(5) %"39", align 8
%"46" = load i64, ptr addrspace(5) %"37", align 8
%"47" = load i64, ptr addrspace(5) %"39", align 8
%"51" = inttoptr i64 %"46" to ptr
store i64 %"47", ptr %"51", align 8
ret void
}

54
ptx/src/test/ll/ntid.ll
View file

@ -1,37 +1,37 @@
declare hidden i32 @__zluda_ptx_impl_sreg_ntid(i8) #0
define amdgpu_kernel void @ntid(ptr addrspace(4) byref(i64) %"35", ptr addrspace(4) byref(i64) %"36") #1 {
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i32, align 4, addrspace(5)
%"40" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @ntid(ptr addrspace(4) byref(i64) %"38", ptr addrspace(4) byref(i64) %"39") #1 {
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i32, align 4, addrspace(5)
%"43" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"32"
br label %"35"
"32": ; preds = %1
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"44" = load i64, ptr addrspace(5) %"37", align 8
%"51" = inttoptr i64 %"44" to ptr
%"43" = load i32, ptr %"51", align 4
store i32 %"43", ptr addrspace(5) %"39", align 4
%"31" = call i32 @__zluda_ptx_impl_sreg_ntid(i8 0)
br label %"33"
"35": ; preds = %1
%"44" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"44", ptr addrspace(5) %"40", align 8
%"45" = load i64, ptr addrspace(4) %"39", align 8
store i64 %"45", ptr addrspace(5) %"41", align 8
%"47" = load i64, ptr addrspace(5) %"40", align 8
%"54" = inttoptr i64 %"47" to ptr
%"46" = load i32, ptr %"54", align 4
store i32 %"46", ptr addrspace(5) %"42", align 4
%"34" = call i32 @__zluda_ptx_impl_sreg_ntid(i8 0)
br label %"36"
"33": ; preds = %"32"
store i32 %"31", ptr addrspace(5) %"40", align 4
%"47" = load i32, ptr addrspace(5) %"39", align 4
%"48" = load i32, ptr addrspace(5) %"40", align 4
%"46" = add i32 %"47", %"48"
store i32 %"46", ptr addrspace(5) %"39", align 4
%"49" = load i64, ptr addrspace(5) %"38", align 8
%"50" = load i32, ptr addrspace(5) %"39", align 4
%"52" = inttoptr i64 %"49" to ptr
store i32 %"50", ptr %"52", align 4
"36": ; preds = %"35"
store i32 %"34", ptr addrspace(5) %"43", align 4
%"50" = load i32, ptr addrspace(5) %"42", align 4
%"51" = load i32, ptr addrspace(5) %"43", align 4
%"49" = add i32 %"50", %"51"
store i32 %"49", ptr addrspace(5) %"42", align 4
%"52" = load i64, ptr addrspace(5) %"41", align 8
%"53" = load i32, ptr addrspace(5) %"42", align 4
%"55" = inttoptr i64 %"52" to ptr
store i32 %"53", ptr %"55", align 4
ret void
}

54
ptx/src/test/ll/or.ll
View file

@ -1,35 +1,35 @@
define amdgpu_kernel void @or(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @or(ptr addrspace(4) byref(i64) %"36", ptr addrspace(4) byref(i64) %"37") #0 {
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"32"
br label %"35"
"32": ; preds = %1
%"39" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"39", ptr addrspace(5) %"35", align 8
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"42" = load i64, ptr addrspace(5) %"35", align 8
%"50" = inttoptr i64 %"42" to ptr
%"41" = load i64, ptr %"50", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(5) %"35", align 8
%"51" = inttoptr i64 %"43" to ptr
%"31" = getelementptr inbounds i8, ptr %"51", i64 8
%"44" = load i64, ptr %"31", align 8
store i64 %"44", ptr addrspace(5) %"38", align 8
%"46" = load i64, ptr addrspace(5) %"37", align 8
%"47" = load i64, ptr addrspace(5) %"38", align 8
%"52" = or i64 %"46", %"47"
store i64 %"52", ptr addrspace(5) %"37", align 8
%"48" = load i64, ptr addrspace(5) %"36", align 8
%"49" = load i64, ptr addrspace(5) %"37", align 8
%"55" = inttoptr i64 %"48" to ptr
store i64 %"49", ptr %"55", align 8
"35": ; preds = %1
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"43" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"45" = load i64, ptr addrspace(5) %"38", align 8
%"53" = inttoptr i64 %"45" to ptr
%"44" = load i64, ptr %"53", align 8
store i64 %"44", ptr addrspace(5) %"40", align 8
%"46" = load i64, ptr addrspace(5) %"38", align 8
%"54" = inttoptr i64 %"46" to ptr
%"34" = getelementptr inbounds i8, ptr %"54", i64 8
%"47" = load i64, ptr %"34", align 8
store i64 %"47", ptr addrspace(5) %"41", align 8
%"49" = load i64, ptr addrspace(5) %"40", align 8
%"50" = load i64, ptr addrspace(5) %"41", align 8
%"55" = or i64 %"49", %"50"
store i64 %"55", ptr addrspace(5) %"40", align 8
%"51" = load i64, ptr addrspace(5) %"39", align 8
%"52" = load i64, ptr addrspace(5) %"40", align 8
%"58" = inttoptr i64 %"51" to ptr
store i64 %"52", ptr %"58", align 8
ret void
}

42
ptx/src/test/ll/popc.ll
View file

@ -1,28 +1,28 @@
define amdgpu_kernel void @popc(ptr addrspace(4) byref(i64) %"30", ptr addrspace(4) byref(i64) %"31") #0 {
%"32" = alloca i64, align 8, addrspace(5)
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @popc(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"29"
br label %"32"
"29": ; preds = %1
%"35" = load i64, ptr addrspace(4) %"30", align 8
store i64 %"35", ptr addrspace(5) %"32", align 8
%"36" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"36", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(5) %"32", align 8
%"43" = inttoptr i64 %"38" to ptr
%"37" = load i32, ptr %"43", align 4
store i32 %"37", ptr addrspace(5) %"34", align 4
%"40" = load i32, ptr addrspace(5) %"34", align 4
%"44" = call i32 @llvm.ctpop.i32(i32 %"40")
store i32 %"44", ptr addrspace(5) %"34", align 4
%"41" = load i64, ptr addrspace(5) %"33", align 8
%"42" = load i32, ptr addrspace(5) %"34", align 4
%"45" = inttoptr i64 %"41" to ptr
store i32 %"42", ptr %"45", align 4
"32": ; preds = %1
%"38" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"38", ptr addrspace(5) %"35", align 8
%"39" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"39", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(5) %"35", align 8
%"46" = inttoptr i64 %"41" to ptr
%"40" = load i32, ptr %"46", align 4
store i32 %"40", ptr addrspace(5) %"37", align 4
%"43" = load i32, ptr addrspace(5) %"37", align 4
%"47" = call i32 @llvm.ctpop.i32(i32 %"43")
store i32 %"47", ptr addrspace(5) %"37", align 4
%"44" = load i64, ptr addrspace(5) %"36", align 8
%"45" = load i32, ptr addrspace(5) %"37", align 4
%"48" = inttoptr i64 %"44" to ptr
store i32 %"45", ptr %"48", align 4
ret void
}

86
ptx/src/test/ll/pred_not.ll
View file

@ -1,56 +1,56 @@
define amdgpu_kernel void @pred_not(ptr addrspace(4) byref(i64) %"41", ptr addrspace(4) byref(i64) %"42") #0 {
%"43" = alloca i64, align 8, addrspace(5)
%"44" = alloca i64, align 8, addrspace(5)
%"45" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @pred_not(ptr addrspace(4) byref(i64) %"44", ptr addrspace(4) byref(i64) %"45") #0 {
%"46" = alloca i64, align 8, addrspace(5)
%"47" = alloca i64, align 8, addrspace(5)
%"48" = alloca i1, align 1, addrspace(5)
%"48" = alloca i64, align 8, addrspace(5)
%"49" = alloca i64, align 8, addrspace(5)
%"50" = alloca i64, align 8, addrspace(5)
%"51" = alloca i1, align 1, addrspace(5)
br label %1
1: ; preds = %0
br label %"40"
br label %"43"
"40": ; preds = %1
%"49" = load i64, ptr addrspace(4) %"41", align 8
store i64 %"49", ptr addrspace(5) %"43", align 8
%"50" = load i64, ptr addrspace(4) %"42", align 8
store i64 %"50", ptr addrspace(5) %"44", align 8
%"52" = load i64, ptr addrspace(5) %"43", align 8
%"66" = inttoptr i64 %"52" to ptr
%"51" = load i64, ptr %"66", align 8
store i64 %"51", ptr addrspace(5) %"45", align 8
%"53" = load i64, ptr addrspace(5) %"43", align 8
%"67" = inttoptr i64 %"53" to ptr
%"37" = getelementptr inbounds i8, ptr %"67", i64 8
%"54" = load i64, ptr %"37", align 8
store i64 %"54", ptr addrspace(5) %"46", align 8
%"56" = load i64, ptr addrspace(5) %"45", align 8
%"57" = load i64, ptr addrspace(5) %"46", align 8
%2 = icmp ult i64 %"56", %"57"
store i1 %2, ptr addrspace(5) %"48", align 1
%"59" = load i1, ptr addrspace(5) %"48", align 1
%"58" = xor i1 %"59", true
store i1 %"58", ptr addrspace(5) %"48", align 1
%"60" = load i1, ptr addrspace(5) %"48", align 1
br i1 %"60", label %"16", label %"17"
"43": ; preds = %1
%"52" = load i64, ptr addrspace(4) %"44", align 8
store i64 %"52", ptr addrspace(5) %"46", align 8
%"53" = load i64, ptr addrspace(4) %"45", align 8
store i64 %"53", ptr addrspace(5) %"47", align 8
%"55" = load i64, ptr addrspace(5) %"46", align 8
%"69" = inttoptr i64 %"55" to ptr
%"54" = load i64, ptr %"69", align 8
store i64 %"54", ptr addrspace(5) %"48", align 8
%"56" = load i64, ptr addrspace(5) %"46", align 8
%"70" = inttoptr i64 %"56" to ptr
%"40" = getelementptr inbounds i8, ptr %"70", i64 8
%"57" = load i64, ptr %"40", align 8
store i64 %"57", ptr addrspace(5) %"49", align 8
%"59" = load i64, ptr addrspace(5) %"48", align 8
%"60" = load i64, ptr addrspace(5) %"49", align 8
%2 = icmp ult i64 %"59", %"60"
store i1 %2, ptr addrspace(5) %"51", align 1
%"62" = load i1, ptr addrspace(5) %"51", align 1
%"61" = xor i1 %"62", true
store i1 %"61", ptr addrspace(5) %"51", align 1
%"63" = load i1, ptr addrspace(5) %"51", align 1
br i1 %"63", label %"17", label %"18"
"16": ; preds = %"40"
store i64 1, ptr addrspace(5) %"47", align 8
br label %"17"
"17": ; preds = %"43"
store i64 1, ptr addrspace(5) %"50", align 8
br label %"18"
"17": ; preds = %"16", %"40"
%"62" = load i1, ptr addrspace(5) %"48", align 1
br i1 %"62", label %"19", label %"18"
"18": ; preds = %"17", %"43"
%"65" = load i1, ptr addrspace(5) %"51", align 1
br i1 %"65", label %"20", label %"19"
"18": ; preds = %"17"
store i64 2, ptr addrspace(5) %"47", align 8
br label %"19"
"19": ; preds = %"18"
store i64 2, ptr addrspace(5) %"50", align 8
br label %"20"
"19": ; preds = %"18", %"17"
%"64" = load i64, ptr addrspace(5) %"44", align 8
%"65" = load i64, ptr addrspace(5) %"47", align 8
%"68" = inttoptr i64 %"64" to ptr
store i64 %"65", ptr %"68", align 8
"20": ; preds = %"19", %"18"
%"67" = load i64, ptr addrspace(5) %"47", align 8
%"68" = load i64, ptr addrspace(5) %"50", align 8
%"71" = inttoptr i64 %"67" to ptr
store i64 %"68", ptr %"71", align 8
ret void
}

60
ptx/src/test/ll/prmt.ll
View file

@ -1,37 +1,37 @@
define amdgpu_kernel void @prmt(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i32, align 4, addrspace(5)
%"38" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @prmt(ptr addrspace(4) byref(i64) %"36", ptr addrspace(4) byref(i64) %"37") #0 {
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i32, align 4, addrspace(5)
%"41" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"32"
br label %"35"
"32": ; preds = %1
%"39" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"39", ptr addrspace(5) %"35", align 8
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"42" = load i64, ptr addrspace(5) %"35", align 8
%"50" = inttoptr i64 %"42" to ptr
%"41" = load i32, ptr %"50", align 4
store i32 %"41", ptr addrspace(5) %"37", align 4
%"43" = load i64, ptr addrspace(5) %"35", align 8
%"51" = inttoptr i64 %"43" to ptr
%"31" = getelementptr inbounds i8, ptr %"51", i64 4
%"44" = load i32, ptr %"31", align 4
store i32 %"44", ptr addrspace(5) %"38", align 4
%"46" = load i32, ptr addrspace(5) %"37", align 4
%"47" = load i32, ptr addrspace(5) %"38", align 4
%2 = bitcast i32 %"46" to <4 x i8>
%3 = bitcast i32 %"47" to <4 x i8>
%"52" = shufflevector <4 x i8> %2, <4 x i8> %3, <4 x i32> <i32 4, i32 0, i32 6, i32 7>
store <4 x i8> %"52", ptr addrspace(5) %"38", align 4
%"48" = load i64, ptr addrspace(5) %"36", align 8
%"49" = load i32, ptr addrspace(5) %"38", align 4
%"55" = inttoptr i64 %"48" to ptr
store i32 %"49", ptr %"55", align 4
"35": ; preds = %1
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"43" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"45" = load i64, ptr addrspace(5) %"38", align 8
%"53" = inttoptr i64 %"45" to ptr
%"44" = load i32, ptr %"53", align 4
store i32 %"44", ptr addrspace(5) %"40", align 4
%"46" = load i64, ptr addrspace(5) %"38", align 8
%"54" = inttoptr i64 %"46" to ptr
%"34" = getelementptr inbounds i8, ptr %"54", i64 4
%"47" = load i32, ptr %"34", align 4
store i32 %"47", ptr addrspace(5) %"41", align 4
%"49" = load i32, ptr addrspace(5) %"40", align 4
%"50" = load i32, ptr addrspace(5) %"41", align 4
%2 = bitcast i32 %"49" to <4 x i8>
%3 = bitcast i32 %"50" to <4 x i8>
%"55" = shufflevector <4 x i8> %2, <4 x i8> %3, <4 x i32> <i32 4, i32 0, i32 6, i32 7>
store <4 x i8> %"55", ptr addrspace(5) %"41", align 4
%"51" = load i64, ptr addrspace(5) %"39", align 8
%"52" = load i32, ptr addrspace(5) %"41", align 4
%"58" = inttoptr i64 %"51" to ptr
store i32 %"52", ptr %"58", align 4
ret void
}

42
ptx/src/test/ll/rcp.ll
View file

@ -1,30 +1,30 @@
declare hidden float @__zluda_ptx_impl_rcp_approx_f32(float) #0
define amdgpu_kernel void @rcp(ptr addrspace(4) byref(i64) %"30", ptr addrspace(4) byref(i64) %"31") #1 {
%"32" = alloca i64, align 8, addrspace(5)
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca float, align 4, addrspace(5)
define amdgpu_kernel void @rcp(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #1 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca float, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"29"
br label %"32"
"29": ; preds = %1
%"35" = load i64, ptr addrspace(4) %"30", align 8
store i64 %"35", ptr addrspace(5) %"32", align 8
%"36" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"36", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(5) %"32", align 8
%"43" = inttoptr i64 %"38" to ptr
%"37" = load float, ptr %"43", align 4
store float %"37", ptr addrspace(5) %"34", align 4
%"40" = load float, ptr addrspace(5) %"34", align 4
%"39" = call float @__zluda_ptx_impl_rcp_approx_f32(float %"40")
store float %"39", ptr addrspace(5) %"34", align 4
%"41" = load i64, ptr addrspace(5) %"33", align 8
%"42" = load float, ptr addrspace(5) %"34", align 4
%"44" = inttoptr i64 %"41" to ptr
store float %"42", ptr %"44", align 4
"32": ; preds = %1
%"38" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"38", ptr addrspace(5) %"35", align 8
%"39" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"39", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(5) %"35", align 8
%"46" = inttoptr i64 %"41" to ptr
%"40" = load float, ptr %"46", align 4
store float %"40", ptr addrspace(5) %"37", align 4
%"43" = load float, ptr addrspace(5) %"37", align 4
%"42" = call float @__zluda_ptx_impl_rcp_approx_f32(float %"43")
store float %"42", ptr addrspace(5) %"37", align 4
%"44" = load i64, ptr addrspace(5) %"36", align 8
%"45" = load float, ptr addrspace(5) %"37", align 4
%"47" = inttoptr i64 %"44" to ptr
store float %"45", ptr %"47", align 4
ret void
}

56
ptx/src/test/ll/reg_local.ll
View file

@ -1,35 +1,35 @@
define amdgpu_kernel void @reg_local(ptr addrspace(4) byref(i64) %"37", ptr addrspace(4) byref(i64) %"38") #0 {
%"10" = alloca [8 x i8], align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @reg_local(ptr addrspace(4) byref(i64) %"40", ptr addrspace(4) byref(i64) %"41") #0 {
%"11" = alloca [8 x i8], align 8, addrspace(5)
%"42" = alloca i64, align 8, addrspace(5)
%"43" = alloca i64, align 8, addrspace(5)
%"44" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"36"
br label %"39"
"36": ; preds = %1
%"42" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"42", ptr addrspace(5) %"39", align 8
%"43" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"43", ptr addrspace(5) %"40", align 8
%"45" = load i64, ptr addrspace(5) %"39", align 8
%"51" = inttoptr i64 %"45" to ptr addrspace(1)
%"50" = load i64, ptr addrspace(1) %"51", align 8
store i64 %"50", ptr addrspace(5) %"41", align 8
%"46" = load i64, ptr addrspace(5) %"41", align 8
%"31" = add i64 %"46", 1
%"52" = addrspacecast ptr addrspace(5) %"10" to ptr
store i64 %"31", ptr %"52", align 8
%"54" = addrspacecast ptr addrspace(5) %"10" to ptr
%"33" = getelementptr inbounds i8, ptr %"54", i64 0
%"55" = load i64, ptr %"33", align 8
store i64 %"55", ptr addrspace(5) %"41", align 8
%"48" = load i64, ptr addrspace(5) %"40", align 8
%"56" = inttoptr i64 %"48" to ptr addrspace(1)
%"35" = getelementptr inbounds i8, ptr addrspace(1) %"56", i64 0
%"49" = load i64, ptr addrspace(5) %"41", align 8
store i64 %"49", ptr addrspace(1) %"35", align 8
"39": ; preds = %1
%"45" = load i64, ptr addrspace(4) %"40", align 8
store i64 %"45", ptr addrspace(5) %"42", align 8
%"46" = load i64, ptr addrspace(4) %"41", align 8
store i64 %"46", ptr addrspace(5) %"43", align 8
%"48" = load i64, ptr addrspace(5) %"42", align 8
%"54" = inttoptr i64 %"48" to ptr addrspace(1)
%"53" = load i64, ptr addrspace(1) %"54", align 8
store i64 %"53", ptr addrspace(5) %"44", align 8
%"49" = load i64, ptr addrspace(5) %"44", align 8
%"34" = add i64 %"49", 1
%"55" = addrspacecast ptr addrspace(5) %"11" to ptr
store i64 %"34", ptr %"55", align 8
%"57" = addrspacecast ptr addrspace(5) %"11" to ptr
%"36" = getelementptr inbounds i8, ptr %"57", i64 0
%"58" = load i64, ptr %"36", align 8
store i64 %"58", ptr addrspace(5) %"44", align 8
%"51" = load i64, ptr addrspace(5) %"43", align 8
%"59" = inttoptr i64 %"51" to ptr addrspace(1)
%"38" = getelementptr inbounds i8, ptr addrspace(1) %"59", i64 0
%"52" = load i64, ptr addrspace(5) %"44", align 8
store i64 %"52", ptr addrspace(1) %"38", align 8
ret void
}

56
ptx/src/test/ll/rem.ll
View file

@ -1,35 +1,35 @@
define amdgpu_kernel void @rem(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i32, align 4, addrspace(5)
%"38" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @rem(ptr addrspace(4) byref(i64) %"36", ptr addrspace(4) byref(i64) %"37") #0 {
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i32, align 4, addrspace(5)
%"41" = alloca i32, align 4, addrspace(5)
br label %1
1: ; preds = %0
br label %"32"
br label %"35"
"32": ; preds = %1
%"39" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"39", ptr addrspace(5) %"35", align 8
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"42" = load i64, ptr addrspace(5) %"35", align 8
%"50" = inttoptr i64 %"42" to ptr
%"41" = load i32, ptr %"50", align 4
store i32 %"41", ptr addrspace(5) %"37", align 4
%"43" = load i64, ptr addrspace(5) %"35", align 8
%"51" = inttoptr i64 %"43" to ptr
%"31" = getelementptr inbounds i8, ptr %"51", i64 4
%"44" = load i32, ptr %"31", align 4
store i32 %"44", ptr addrspace(5) %"38", align 4
%"46" = load i32, ptr addrspace(5) %"37", align 4
%"47" = load i32, ptr addrspace(5) %"38", align 4
%"45" = srem i32 %"46", %"47"
store i32 %"45", ptr addrspace(5) %"37", align 4
%"48" = load i64, ptr addrspace(5) %"36", align 8
%"49" = load i32, ptr addrspace(5) %"37", align 4
%"52" = inttoptr i64 %"48" to ptr
store i32 %"49", ptr %"52", align 4
"35": ; preds = %1
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"43" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"45" = load i64, ptr addrspace(5) %"38", align 8
%"53" = inttoptr i64 %"45" to ptr
%"44" = load i32, ptr %"53", align 4
store i32 %"44", ptr addrspace(5) %"40", align 4
%"46" = load i64, ptr addrspace(5) %"38", align 8
%"54" = inttoptr i64 %"46" to ptr
%"34" = getelementptr inbounds i8, ptr %"54", i64 4
%"47" = load i32, ptr %"34", align 4
store i32 %"47", ptr addrspace(5) %"41", align 4
%"49" = load i32, ptr addrspace(5) %"40", align 4
%"50" = load i32, ptr addrspace(5) %"41", align 4
%"48" = srem i32 %"49", %"50"
store i32 %"48", ptr addrspace(5) %"40", align 4
%"51" = load i64, ptr addrspace(5) %"39", align 8
%"52" = load i32, ptr addrspace(5) %"40", align 4
%"55" = inttoptr i64 %"51" to ptr
store i32 %"52", ptr %"55", align 4
ret void
}

42
ptx/src/test/ll/rsqrt.ll
View file

@ -1,28 +1,28 @@
define amdgpu_kernel void @rsqrt(ptr addrspace(4) byref(i64) %"30", ptr addrspace(4) byref(i64) %"31") #0 {
%"32" = alloca i64, align 8, addrspace(5)
%"33" = alloca i64, align 8, addrspace(5)
%"34" = alloca double, align 8, addrspace(5)
define amdgpu_kernel void @rsqrt(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca double, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"29"
br label %"32"
"29": ; preds = %1
%"35" = load i64, ptr addrspace(4) %"30", align 8
store i64 %"35", ptr addrspace(5) %"32", align 8
%"36" = load i64, ptr addrspace(4) %"31", align 8
store i64 %"36", ptr addrspace(5) %"33", align 8
%"38" = load i64, ptr addrspace(5) %"32", align 8
%"43" = inttoptr i64 %"38" to ptr
%"37" = load double, ptr %"43", align 8
store double %"37", ptr addrspace(5) %"34", align 8
%"40" = load double, ptr addrspace(5) %"34", align 8
%"39" = call double @llvm.amdgcn.rsq.f64(double %"40")
store double %"39", ptr addrspace(5) %"34", align 8
%"41" = load i64, ptr addrspace(5) %"33", align 8
%"42" = load double, ptr addrspace(5) %"34", align 8
%"44" = inttoptr i64 %"41" to ptr
store double %"42", ptr %"44", align 8
"32": ; preds = %1
%"38" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"38", ptr addrspace(5) %"35", align 8
%"39" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"39", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(5) %"35", align 8
%"46" = inttoptr i64 %"41" to ptr
%"40" = load double, ptr %"46", align 8
store double %"40", ptr addrspace(5) %"37", align 8
%"43" = load double, ptr addrspace(5) %"37", align 8
%"42" = call double @llvm.amdgcn.rsq.f64(double %"43")
store double %"42", ptr addrspace(5) %"37", align 8
%"44" = load i64, ptr addrspace(5) %"36", align 8
%"45" = load double, ptr addrspace(5) %"37", align 8
%"47" = inttoptr i64 %"44" to ptr
store double %"45", ptr %"47", align 8
ret void
}

56
ptx/src/test/ll/selp.ll
View file

@ -1,35 +1,35 @@
define amdgpu_kernel void @selp(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i16, align 2, addrspace(5)
%"39" = alloca i16, align 2, addrspace(5)
define amdgpu_kernel void @selp(ptr addrspace(4) byref(i64) %"37", ptr addrspace(4) byref(i64) %"38") #0 {
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i16, align 2, addrspace(5)
%"42" = alloca i16, align 2, addrspace(5)
br label %1
1: ; preds = %0
br label %"33"
br label %"36"
"33": ; preds = %1
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"51" = inttoptr i64 %"43" to ptr
%"42" = load i16, ptr %"51", align 2
store i16 %"42", ptr addrspace(5) %"38", align 2
%"44" = load i64, ptr addrspace(5) %"36", align 8
%"52" = inttoptr i64 %"44" to ptr
%"31" = getelementptr inbounds i8, ptr %"52", i64 2
%"45" = load i16, ptr %"31", align 2
store i16 %"45", ptr addrspace(5) %"39", align 2
%"47" = load i16, ptr addrspace(5) %"38", align 2
%"48" = load i16, ptr addrspace(5) %"39", align 2
%"46" = select i1 false, i16 %"47", i16 %"48"
store i16 %"46", ptr addrspace(5) %"38", align 2
%"49" = load i64, ptr addrspace(5) %"37", align 8
%"50" = load i16, ptr addrspace(5) %"38", align 2
%"53" = inttoptr i64 %"49" to ptr
store i16 %"50", ptr %"53", align 2
"36": ; preds = %1
%"43" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"44" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"44", ptr addrspace(5) %"40", align 8
%"46" = load i64, ptr addrspace(5) %"39", align 8
%"54" = inttoptr i64 %"46" to ptr
%"45" = load i16, ptr %"54", align 2
store i16 %"45", ptr addrspace(5) %"41", align 2
%"47" = load i64, ptr addrspace(5) %"39", align 8
%"55" = inttoptr i64 %"47" to ptr
%"34" = getelementptr inbounds i8, ptr %"55", i64 2
%"48" = load i16, ptr %"34", align 2
store i16 %"48", ptr addrspace(5) %"42", align 2
%"50" = load i16, ptr addrspace(5) %"41", align 2
%"51" = load i16, ptr addrspace(5) %"42", align 2
%"49" = select i1 false, i16 %"50", i16 %"51"
store i16 %"49", ptr addrspace(5) %"41", align 2
%"52" = load i64, ptr addrspace(5) %"40", align 8
%"53" = load i16, ptr addrspace(5) %"41", align 2
%"56" = inttoptr i64 %"52" to ptr
store i16 %"53", ptr %"56", align 2
ret void
}

56
ptx/src/test/ll/selp_true.ll
View file

@ -1,35 +1,35 @@
define amdgpu_kernel void @selp_true(ptr addrspace(4) byref(i64) %"34", ptr addrspace(4) byref(i64) %"35") #0 {
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i16, align 2, addrspace(5)
%"39" = alloca i16, align 2, addrspace(5)
define amdgpu_kernel void @selp_true(ptr addrspace(4) byref(i64) %"37", ptr addrspace(4) byref(i64) %"38") #0 {
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i16, align 2, addrspace(5)
%"42" = alloca i16, align 2, addrspace(5)
br label %1
1: ; preds = %0
br label %"33"
br label %"36"
"33": ; preds = %1
%"40" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(5) %"36", align 8
%"51" = inttoptr i64 %"43" to ptr
%"42" = load i16, ptr %"51", align 2
store i16 %"42", ptr addrspace(5) %"38", align 2
%"44" = load i64, ptr addrspace(5) %"36", align 8
%"52" = inttoptr i64 %"44" to ptr
%"31" = getelementptr inbounds i8, ptr %"52", i64 2
%"45" = load i16, ptr %"31", align 2
store i16 %"45", ptr addrspace(5) %"39", align 2
%"47" = load i16, ptr addrspace(5) %"38", align 2
%"48" = load i16, ptr addrspace(5) %"39", align 2
%"46" = select i1 true, i16 %"47", i16 %"48"
store i16 %"46", ptr addrspace(5) %"38", align 2
%"49" = load i64, ptr addrspace(5) %"37", align 8
%"50" = load i16, ptr addrspace(5) %"38", align 2
%"53" = inttoptr i64 %"49" to ptr
store i16 %"50", ptr %"53", align 2
"36": ; preds = %1
%"43" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"44" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"44", ptr addrspace(5) %"40", align 8
%"46" = load i64, ptr addrspace(5) %"39", align 8
%"54" = inttoptr i64 %"46" to ptr
%"45" = load i16, ptr %"54", align 2
store i16 %"45", ptr addrspace(5) %"41", align 2
%"47" = load i64, ptr addrspace(5) %"39", align 8
%"55" = inttoptr i64 %"47" to ptr
%"34" = getelementptr inbounds i8, ptr %"55", i64 2
%"48" = load i16, ptr %"34", align 2
store i16 %"48", ptr addrspace(5) %"42", align 2
%"50" = load i16, ptr addrspace(5) %"41", align 2
%"51" = load i16, ptr addrspace(5) %"42", align 2
%"49" = select i1 true, i16 %"50", i16 %"51"
store i16 %"49", ptr addrspace(5) %"41", align 2
%"52" = load i64, ptr addrspace(5) %"40", align 8
%"53" = load i16, ptr addrspace(5) %"41", align 2
%"56" = inttoptr i64 %"52" to ptr
store i16 %"53", ptr %"56", align 2
ret void
}

80
ptx/src/test/ll/setp.ll
View file

@ -1,53 +1,53 @@
define amdgpu_kernel void @setp(ptr addrspace(4) byref(i64) %"41", ptr addrspace(4) byref(i64) %"42") #0 {
%"43" = alloca i64, align 8, addrspace(5)
%"44" = alloca i64, align 8, addrspace(5)
%"45" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @setp(ptr addrspace(4) byref(i64) %"44", ptr addrspace(4) byref(i64) %"45") #0 {
%"46" = alloca i64, align 8, addrspace(5)
%"47" = alloca i64, align 8, addrspace(5)
%"48" = alloca i1, align 1, addrspace(5)
%"48" = alloca i64, align 8, addrspace(5)
%"49" = alloca i64, align 8, addrspace(5)
%"50" = alloca i64, align 8, addrspace(5)
%"51" = alloca i1, align 1, addrspace(5)
br label %1
1: ; preds = %0
br label %"40"
br label %"43"
"40": ; preds = %1
%"49" = load i64, ptr addrspace(4) %"41", align 8
store i64 %"49", ptr addrspace(5) %"43", align 8
%"50" = load i64, ptr addrspace(4) %"42", align 8
store i64 %"50", ptr addrspace(5) %"44", align 8
%"52" = load i64, ptr addrspace(5) %"43", align 8
%"64" = inttoptr i64 %"52" to ptr
%"51" = load i64, ptr %"64", align 8
store i64 %"51", ptr addrspace(5) %"45", align 8
%"53" = load i64, ptr addrspace(5) %"43", align 8
%"65" = inttoptr i64 %"53" to ptr
%"37" = getelementptr inbounds i8, ptr %"65", i64 8
%"54" = load i64, ptr %"37", align 8
store i64 %"54", ptr addrspace(5) %"46", align 8
%"56" = load i64, ptr addrspace(5) %"45", align 8
%"57" = load i64, ptr addrspace(5) %"46", align 8
%2 = icmp ult i64 %"56", %"57"
store i1 %2, ptr addrspace(5) %"48", align 1
%"58" = load i1, ptr addrspace(5) %"48", align 1
br i1 %"58", label %"16", label %"17"
"43": ; preds = %1
%"52" = load i64, ptr addrspace(4) %"44", align 8
store i64 %"52", ptr addrspace(5) %"46", align 8
%"53" = load i64, ptr addrspace(4) %"45", align 8
store i64 %"53", ptr addrspace(5) %"47", align 8
%"55" = load i64, ptr addrspace(5) %"46", align 8
%"67" = inttoptr i64 %"55" to ptr
%"54" = load i64, ptr %"67", align 8
store i64 %"54", ptr addrspace(5) %"48", align 8
%"56" = load i64, ptr addrspace(5) %"46", align 8
%"68" = inttoptr i64 %"56" to ptr
%"40" = getelementptr inbounds i8, ptr %"68", i64 8
%"57" = load i64, ptr %"40", align 8
store i64 %"57", ptr addrspace(5) %"49", align 8
%"59" = load i64, ptr addrspace(5) %"48", align 8
%"60" = load i64, ptr addrspace(5) %"49", align 8
%2 = icmp ult i64 %"59", %"60"
store i1 %2, ptr addrspace(5) %"51", align 1
%"61" = load i1, ptr addrspace(5) %"51", align 1
br i1 %"61", label %"17", label %"18"
"16": ; preds = %"40"
store i64 1, ptr addrspace(5) %"47", align 8
br label %"17"
"17": ; preds = %"43"
store i64 1, ptr addrspace(5) %"50", align 8
br label %"18"
"17": ; preds = %"16", %"40"
%"60" = load i1, ptr addrspace(5) %"48", align 1
br i1 %"60", label %"19", label %"18"
"18": ; preds = %"17", %"43"
%"63" = load i1, ptr addrspace(5) %"51", align 1
br i1 %"63", label %"20", label %"19"
"18": ; preds = %"17"
store i64 2, ptr addrspace(5) %"47", align 8
br label %"19"
"19": ; preds = %"18"
store i64 2, ptr addrspace(5) %"50", align 8
br label %"20"
"19": ; preds = %"18", %"17"
%"62" = load i64, ptr addrspace(5) %"44", align 8
%"63" = load i64, ptr addrspace(5) %"47", align 8
%"66" = inttoptr i64 %"62" to ptr
store i64 %"63", ptr %"66", align 8
"20": ; preds = %"19", %"18"
%"65" = load i64, ptr addrspace(5) %"47", align 8
%"66" = load i64, ptr addrspace(5) %"50", align 8
%"69" = inttoptr i64 %"65" to ptr
store i64 %"66", ptr %"69", align 8
ret void
}

88
ptx/src/test/ll/setp_gt.ll
View file

@ -1,55 +1,55 @@
define amdgpu_kernel void @setp_gt(ptr addrspace(4) byref(i64) %"39", ptr addrspace(4) byref(i64) %"40") #0 {
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i64, align 8, addrspace(5)
%"43" = alloca float, align 4, addrspace(5)
%"44" = alloca float, align 4, addrspace(5)
%"45" = alloca float, align 4, addrspace(5)
%"46" = alloca i1, align 1, addrspace(5)
define amdgpu_kernel void @setp_gt(ptr addrspace(4) byref(i64) %"42", ptr addrspace(4) byref(i64) %"43") #0 {
%"44" = alloca i64, align 8, addrspace(5)
%"45" = alloca i64, align 8, addrspace(5)
%"46" = alloca float, align 4, addrspace(5)
%"47" = alloca float, align 4, addrspace(5)
%"48" = alloca float, align 4, addrspace(5)
%"49" = alloca i1, align 1, addrspace(5)
br label %1
1: ; preds = %0
br label %"38"
br label %"41"
"38": ; preds = %1
%"47" = load i64, ptr addrspace(4) %"39", align 8
store i64 %"47", ptr addrspace(5) %"41", align 8
%"48" = load i64, ptr addrspace(4) %"40", align 8
store i64 %"48", ptr addrspace(5) %"42", align 8
%"50" = load i64, ptr addrspace(5) %"41", align 8
%"64" = inttoptr i64 %"50" to ptr
%"49" = load float, ptr %"64", align 4
store float %"49", ptr addrspace(5) %"43", align 4
%"51" = load i64, ptr addrspace(5) %"41", align 8
%"65" = inttoptr i64 %"51" to ptr
%"37" = getelementptr inbounds i8, ptr %"65", i64 4
%"52" = load float, ptr %"37", align 4
store float %"52", ptr addrspace(5) %"44", align 4
%"54" = load float, ptr addrspace(5) %"43", align 4
%"55" = load float, ptr addrspace(5) %"44", align 4
%2 = fcmp ogt float %"54", %"55"
store i1 %2, ptr addrspace(5) %"46", align 1
%"56" = load i1, ptr addrspace(5) %"46", align 1
br i1 %"56", label %"16", label %"17"
"41": ; preds = %1
%"50" = load i64, ptr addrspace(4) %"42", align 8
store i64 %"50", ptr addrspace(5) %"44", align 8
%"51" = load i64, ptr addrspace(4) %"43", align 8
store i64 %"51", ptr addrspace(5) %"45", align 8
%"53" = load i64, ptr addrspace(5) %"44", align 8
%"67" = inttoptr i64 %"53" to ptr
%"52" = load float, ptr %"67", align 4
store float %"52", ptr addrspace(5) %"46", align 4
%"54" = load i64, ptr addrspace(5) %"44", align 8
%"68" = inttoptr i64 %"54" to ptr
%"40" = getelementptr inbounds i8, ptr %"68", i64 4
%"55" = load float, ptr %"40", align 4
store float %"55", ptr addrspace(5) %"47", align 4
%"57" = load float, ptr addrspace(5) %"46", align 4
%"58" = load float, ptr addrspace(5) %"47", align 4
%2 = fcmp ogt float %"57", %"58"
store i1 %2, ptr addrspace(5) %"49", align 1
%"59" = load i1, ptr addrspace(5) %"49", align 1
br i1 %"59", label %"17", label %"18"
"16": ; preds = %"38"
%"58" = load float, ptr addrspace(5) %"43", align 4
store float %"58", ptr addrspace(5) %"45", align 4
br label %"17"
"17": ; preds = %"41"
%"61" = load float, ptr addrspace(5) %"46", align 4
store float %"61", ptr addrspace(5) %"48", align 4
br label %"18"
"17": ; preds = %"16", %"38"
%"59" = load i1, ptr addrspace(5) %"46", align 1
br i1 %"59", label %"19", label %"18"
"18": ; preds = %"17", %"41"
%"62" = load i1, ptr addrspace(5) %"49", align 1
br i1 %"62", label %"20", label %"19"
"18": ; preds = %"17"
%"61" = load float, ptr addrspace(5) %"44", align 4
store float %"61", ptr addrspace(5) %"45", align 4
br label %"19"
"19": ; preds = %"18"
%"64" = load float, ptr addrspace(5) %"47", align 4
store float %"64", ptr addrspace(5) %"48", align 4
br label %"20"
"19": ; preds = %"18", %"17"
%"62" = load i64, ptr addrspace(5) %"42", align 8
%"63" = load float, ptr addrspace(5) %"45", align 4
%"66" = inttoptr i64 %"62" to ptr
store float %"63", ptr %"66", align 4
"20": ; preds = %"19", %"18"
%"65" = load i64, ptr addrspace(5) %"45", align 8
%"66" = load float, ptr addrspace(5) %"48", align 4
%"69" = inttoptr i64 %"65" to ptr
store float %"66", ptr %"69", align 4
ret void
}

88
ptx/src/test/ll/setp_leu.ll
View file

@ -1,55 +1,55 @@
define amdgpu_kernel void @setp_leu(ptr addrspace(4) byref(i64) %"39", ptr addrspace(4) byref(i64) %"40") #0 {
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i64, align 8, addrspace(5)
%"43" = alloca float, align 4, addrspace(5)
%"44" = alloca float, align 4, addrspace(5)
%"45" = alloca float, align 4, addrspace(5)
%"46" = alloca i1, align 1, addrspace(5)
define amdgpu_kernel void @setp_leu(ptr addrspace(4) byref(i64) %"42", ptr addrspace(4) byref(i64) %"43") #0 {
%"44" = alloca i64, align 8, addrspace(5)
%"45" = alloca i64, align 8, addrspace(5)
%"46" = alloca float, align 4, addrspace(5)
%"47" = alloca float, align 4, addrspace(5)
%"48" = alloca float, align 4, addrspace(5)
%"49" = alloca i1, align 1, addrspace(5)
br label %1
1: ; preds = %0
br label %"38"
br label %"41"
"38": ; preds = %1
%"47" = load i64, ptr addrspace(4) %"39", align 8
store i64 %"47", ptr addrspace(5) %"41", align 8
%"48" = load i64, ptr addrspace(4) %"40", align 8
store i64 %"48", ptr addrspace(5) %"42", align 8
%"50" = load i64, ptr addrspace(5) %"41", align 8
%"64" = inttoptr i64 %"50" to ptr
%"49" = load float, ptr %"64", align 4
store float %"49", ptr addrspace(5) %"43", align 4
%"51" = load i64, ptr addrspace(5) %"41", align 8
%"65" = inttoptr i64 %"51" to ptr
%"37" = getelementptr inbounds i8, ptr %"65", i64 4
%"52" = load float, ptr %"37", align 4
store float %"52", ptr addrspace(5) %"44", align 4
%"54" = load float, ptr addrspace(5) %"43", align 4
%"55" = load float, ptr addrspace(5) %"44", align 4
%2 = fcmp ule float %"54", %"55"
store i1 %2, ptr addrspace(5) %"46", align 1
%"56" = load i1, ptr addrspace(5) %"46", align 1
br i1 %"56", label %"16", label %"17"
"41": ; preds = %1
%"50" = load i64, ptr addrspace(4) %"42", align 8
store i64 %"50", ptr addrspace(5) %"44", align 8
%"51" = load i64, ptr addrspace(4) %"43", align 8
store i64 %"51", ptr addrspace(5) %"45", align 8
%"53" = load i64, ptr addrspace(5) %"44", align 8
%"67" = inttoptr i64 %"53" to ptr
%"52" = load float, ptr %"67", align 4
store float %"52", ptr addrspace(5) %"46", align 4
%"54" = load i64, ptr addrspace(5) %"44", align 8
%"68" = inttoptr i64 %"54" to ptr
%"40" = getelementptr inbounds i8, ptr %"68", i64 4
%"55" = load float, ptr %"40", align 4
store float %"55", ptr addrspace(5) %"47", align 4
%"57" = load float, ptr addrspace(5) %"46", align 4
%"58" = load float, ptr addrspace(5) %"47", align 4
%2 = fcmp ule float %"57", %"58"
store i1 %2, ptr addrspace(5) %"49", align 1
%"59" = load i1, ptr addrspace(5) %"49", align 1
br i1 %"59", label %"17", label %"18"
"16": ; preds = %"38"
%"58" = load float, ptr addrspace(5) %"43", align 4
store float %"58", ptr addrspace(5) %"45", align 4
br label %"17"
"17": ; preds = %"41"
%"61" = load float, ptr addrspace(5) %"46", align 4
store float %"61", ptr addrspace(5) %"48", align 4
br label %"18"
"17": ; preds = %"16", %"38"
%"59" = load i1, ptr addrspace(5) %"46", align 1
br i1 %"59", label %"19", label %"18"
"18": ; preds = %"17", %"41"
%"62" = load i1, ptr addrspace(5) %"49", align 1
br i1 %"62", label %"20", label %"19"
"18": ; preds = %"17"
%"61" = load float, ptr addrspace(5) %"44", align 4
store float %"61", ptr addrspace(5) %"45", align 4
br label %"19"
"19": ; preds = %"18"
%"64" = load float, ptr addrspace(5) %"47", align 4
store float %"64", ptr addrspace(5) %"48", align 4
br label %"20"
"19": ; preds = %"18", %"17"
%"62" = load i64, ptr addrspace(5) %"42", align 8
%"63" = load float, ptr addrspace(5) %"45", align 4
%"66" = inttoptr i64 %"62" to ptr
store float %"63", ptr %"66", align 4
"20": ; preds = %"19", %"18"
%"65" = load i64, ptr addrspace(5) %"45", align 8
%"66" = load float, ptr addrspace(5) %"48", align 4
%"69" = inttoptr i64 %"65" to ptr
store float %"66", ptr %"69", align 4
ret void
}

272
ptx/src/test/ll/setp_nan.ll
View file

@ -1,164 +1,164 @@
define amdgpu_kernel void @setp_nan(ptr addrspace(4) byref(i64) %"83", ptr addrspace(4) byref(i64) %"84") #0 {
%"85" = alloca i64, align 8, addrspace(5)
%"86" = alloca i64, align 8, addrspace(5)
%"87" = alloca float, align 4, addrspace(5)
%"88" = alloca float, align 4, addrspace(5)
%"89" = alloca float, align 4, addrspace(5)
define amdgpu_kernel void @setp_nan(ptr addrspace(4) byref(i64) %"86", ptr addrspace(4) byref(i64) %"87") #0 {
%"88" = alloca i64, align 8, addrspace(5)
%"89" = alloca i64, align 8, addrspace(5)
%"90" = alloca float, align 4, addrspace(5)
%"91" = alloca float, align 4, addrspace(5)
%"92" = alloca float, align 4, addrspace(5)
%"93" = alloca float, align 4, addrspace(5)
%"94" = alloca float, align 4, addrspace(5)
%"95" = alloca i32, align 4, addrspace(5)
%"96" = alloca i1, align 1, addrspace(5)
%"95" = alloca float, align 4, addrspace(5)
%"96" = alloca float, align 4, addrspace(5)
%"97" = alloca float, align 4, addrspace(5)
%"98" = alloca i32, align 4, addrspace(5)
%"99" = alloca i1, align 1, addrspace(5)
br label %1
1: ; preds = %0
br label %"82"
br label %"85"
"82": ; preds = %1
%"97" = load i64, ptr addrspace(4) %"83", align 8
store i64 %"97", ptr addrspace(5) %"85", align 8
%"98" = load i64, ptr addrspace(4) %"84", align 8
store i64 %"98", ptr addrspace(5) %"86", align 8
%"100" = load i64, ptr addrspace(5) %"85", align 8
%"151" = inttoptr i64 %"100" to ptr
%"99" = load float, ptr %"151", align 4
store float %"99", ptr addrspace(5) %"87", align 4
%"101" = load i64, ptr addrspace(5) %"85", align 8
%"152" = inttoptr i64 %"101" to ptr
%"55" = getelementptr inbounds i8, ptr %"152", i64 4
%"102" = load float, ptr %"55", align 4
store float %"102", ptr addrspace(5) %"88", align 4
%"103" = load i64, ptr addrspace(5) %"85", align 8
%"153" = inttoptr i64 %"103" to ptr
%"57" = getelementptr inbounds i8, ptr %"153", i64 8
%"104" = load float, ptr %"57", align 4
store float %"104", ptr addrspace(5) %"89", align 4
%"105" = load i64, ptr addrspace(5) %"85", align 8
%"154" = inttoptr i64 %"105" to ptr
%"59" = getelementptr inbounds i8, ptr %"154", i64 12
%"106" = load float, ptr %"59", align 4
store float %"106", ptr addrspace(5) %"90", align 4
%"107" = load i64, ptr addrspace(5) %"85", align 8
%"155" = inttoptr i64 %"107" to ptr
%"61" = getelementptr inbounds i8, ptr %"155", i64 16
%"108" = load float, ptr %"61", align 4
store float %"108", ptr addrspace(5) %"91", align 4
%"109" = load i64, ptr addrspace(5) %"85", align 8
%"156" = inttoptr i64 %"109" to ptr
%"63" = getelementptr inbounds i8, ptr %"156", i64 20
%"110" = load float, ptr %"63", align 4
store float %"110", ptr addrspace(5) %"92", align 4
%"111" = load i64, ptr addrspace(5) %"85", align 8
%"157" = inttoptr i64 %"111" to ptr
%"65" = getelementptr inbounds i8, ptr %"157", i64 24
%"112" = load float, ptr %"65", align 4
store float %"112", ptr addrspace(5) %"93", align 4
%"113" = load i64, ptr addrspace(5) %"85", align 8
%"158" = inttoptr i64 %"113" to ptr
%"67" = getelementptr inbounds i8, ptr %"158", i64 28
%"114" = load float, ptr %"67", align 4
store float %"114", ptr addrspace(5) %"94", align 4
%"116" = load float, ptr addrspace(5) %"87", align 4
%"117" = load float, ptr addrspace(5) %"88", align 4
%2 = fcmp uno float %"116", %"117"
store i1 %2, ptr addrspace(5) %"96", align 1
%"118" = load i1, ptr addrspace(5) %"96", align 1
br i1 %"118", label %"22", label %"23"
"85": ; preds = %1
%"100" = load i64, ptr addrspace(4) %"86", align 8
store i64 %"100", ptr addrspace(5) %"88", align 8
%"101" = load i64, ptr addrspace(4) %"87", align 8
store i64 %"101", ptr addrspace(5) %"89", align 8
%"103" = load i64, ptr addrspace(5) %"88", align 8
%"154" = inttoptr i64 %"103" to ptr
%"102" = load float, ptr %"154", align 4
store float %"102", ptr addrspace(5) %"90", align 4
%"104" = load i64, ptr addrspace(5) %"88", align 8
%"155" = inttoptr i64 %"104" to ptr
%"58" = getelementptr inbounds i8, ptr %"155", i64 4
%"105" = load float, ptr %"58", align 4
store float %"105", ptr addrspace(5) %"91", align 4
%"106" = load i64, ptr addrspace(5) %"88", align 8
%"156" = inttoptr i64 %"106" to ptr
%"60" = getelementptr inbounds i8, ptr %"156", i64 8
%"107" = load float, ptr %"60", align 4
store float %"107", ptr addrspace(5) %"92", align 4
%"108" = load i64, ptr addrspace(5) %"88", align 8
%"157" = inttoptr i64 %"108" to ptr
%"62" = getelementptr inbounds i8, ptr %"157", i64 12
%"109" = load float, ptr %"62", align 4
store float %"109", ptr addrspace(5) %"93", align 4
%"110" = load i64, ptr addrspace(5) %"88", align 8
%"158" = inttoptr i64 %"110" to ptr
%"64" = getelementptr inbounds i8, ptr %"158", i64 16
%"111" = load float, ptr %"64", align 4
store float %"111", ptr addrspace(5) %"94", align 4
%"112" = load i64, ptr addrspace(5) %"88", align 8
%"159" = inttoptr i64 %"112" to ptr
%"66" = getelementptr inbounds i8, ptr %"159", i64 20
%"113" = load float, ptr %"66", align 4
store float %"113", ptr addrspace(5) %"95", align 4
%"114" = load i64, ptr addrspace(5) %"88", align 8
%"160" = inttoptr i64 %"114" to ptr
%"68" = getelementptr inbounds i8, ptr %"160", i64 24
%"115" = load float, ptr %"68", align 4
store float %"115", ptr addrspace(5) %"96", align 4
%"116" = load i64, ptr addrspace(5) %"88", align 8
%"161" = inttoptr i64 %"116" to ptr
%"70" = getelementptr inbounds i8, ptr %"161", i64 28
%"117" = load float, ptr %"70", align 4
store float %"117", ptr addrspace(5) %"97", align 4
%"119" = load float, ptr addrspace(5) %"90", align 4
%"120" = load float, ptr addrspace(5) %"91", align 4
%2 = fcmp uno float %"119", %"120"
store i1 %2, ptr addrspace(5) %"99", align 1
%"121" = load i1, ptr addrspace(5) %"99", align 1
br i1 %"121", label %"23", label %"24"
"22": ; preds = %"82"
store i32 1, ptr addrspace(5) %"95", align 4
br label %"23"
"23": ; preds = %"85"
store i32 1, ptr addrspace(5) %"98", align 4
br label %"24"
"23": ; preds = %"22", %"82"
%"120" = load i1, ptr addrspace(5) %"96", align 1
br i1 %"120", label %"25", label %"24"
"24": ; preds = %"23", %"85"
%"123" = load i1, ptr addrspace(5) %"99", align 1
br i1 %"123", label %"26", label %"25"
"24": ; preds = %"23"
store i32 0, ptr addrspace(5) %"95", align 4
br label %"25"
"25": ; preds = %"24"
store i32 0, ptr addrspace(5) %"98", align 4
br label %"26"
"25": ; preds = %"24", %"23"
%"122" = load i64, ptr addrspace(5) %"86", align 8
%"123" = load i32, ptr addrspace(5) %"95", align 4
%"159" = inttoptr i64 %"122" to ptr
store i32 %"123", ptr %"159", align 4
%"125" = load float, ptr addrspace(5) %"89", align 4
%"126" = load float, ptr addrspace(5) %"90", align 4
%3 = fcmp uno float %"125", %"126"
store i1 %3, ptr addrspace(5) %"96", align 1
%"127" = load i1, ptr addrspace(5) %"96", align 1
br i1 %"127", label %"26", label %"27"
"26": ; preds = %"25", %"24"
%"125" = load i64, ptr addrspace(5) %"89", align 8
%"126" = load i32, ptr addrspace(5) %"98", align 4
%"162" = inttoptr i64 %"125" to ptr
store i32 %"126", ptr %"162", align 4
%"128" = load float, ptr addrspace(5) %"92", align 4
%"129" = load float, ptr addrspace(5) %"93", align 4
%3 = fcmp uno float %"128", %"129"
store i1 %3, ptr addrspace(5) %"99", align 1
%"130" = load i1, ptr addrspace(5) %"99", align 1
br i1 %"130", label %"27", label %"28"
"26": ; preds = %"25"
store i32 1, ptr addrspace(5) %"95", align 4
br label %"27"
"27": ; preds = %"26"
store i32 1, ptr addrspace(5) %"98", align 4
br label %"28"
"27": ; preds = %"26", %"25"
%"129" = load i1, ptr addrspace(5) %"96", align 1
br i1 %"129", label %"29", label %"28"
"28": ; preds = %"27", %"26"
%"132" = load i1, ptr addrspace(5) %"99", align 1
br i1 %"132", label %"30", label %"29"
"28": ; preds = %"27"
store i32 0, ptr addrspace(5) %"95", align 4
br label %"29"
"29": ; preds = %"28"
store i32 0, ptr addrspace(5) %"98", align 4
br label %"30"
"29": ; preds = %"28", %"27"
%"131" = load i64, ptr addrspace(5) %"86", align 8
%"160" = inttoptr i64 %"131" to ptr
%"73" = getelementptr inbounds i8, ptr %"160", i64 4
%"132" = load i32, ptr addrspace(5) %"95", align 4
store i32 %"132", ptr %"73", align 4
%"134" = load float, ptr addrspace(5) %"91", align 4
%"135" = load float, ptr addrspace(5) %"92", align 4
%4 = fcmp uno float %"134", %"135"
store i1 %4, ptr addrspace(5) %"96", align 1
%"136" = load i1, ptr addrspace(5) %"96", align 1
br i1 %"136", label %"30", label %"31"
"30": ; preds = %"29", %"28"
%"134" = load i64, ptr addrspace(5) %"89", align 8
%"163" = inttoptr i64 %"134" to ptr
%"76" = getelementptr inbounds i8, ptr %"163", i64 4
%"135" = load i32, ptr addrspace(5) %"98", align 4
store i32 %"135", ptr %"76", align 4
%"137" = load float, ptr addrspace(5) %"94", align 4
%"138" = load float, ptr addrspace(5) %"95", align 4
%4 = fcmp uno float %"137", %"138"
store i1 %4, ptr addrspace(5) %"99", align 1
%"139" = load i1, ptr addrspace(5) %"99", align 1
br i1 %"139", label %"31", label %"32"
"30": ; preds = %"29"
store i32 1, ptr addrspace(5) %"95", align 4
br label %"31"
"31": ; preds = %"30"
store i32 1, ptr addrspace(5) %"98", align 4
br label %"32"
"31": ; preds = %"30", %"29"
%"138" = load i1, ptr addrspace(5) %"96", align 1
br i1 %"138", label %"33", label %"32"
"32": ; preds = %"31", %"30"
%"141" = load i1, ptr addrspace(5) %"99", align 1
br i1 %"141", label %"34", label %"33"
"32": ; preds = %"31"
store i32 0, ptr addrspace(5) %"95", align 4
br label %"33"
"33": ; preds = %"32"
store i32 0, ptr addrspace(5) %"98", align 4
br label %"34"
"33": ; preds = %"32", %"31"
%"140" = load i64, ptr addrspace(5) %"86", align 8
%"161" = inttoptr i64 %"140" to ptr
%"77" = getelementptr inbounds i8, ptr %"161", i64 8
%"141" = load i32, ptr addrspace(5) %"95", align 4
store i32 %"141", ptr %"77", align 4
%"143" = load float, ptr addrspace(5) %"93", align 4
%"144" = load float, ptr addrspace(5) %"94", align 4
%5 = fcmp uno float %"143", %"144"
store i1 %5, ptr addrspace(5) %"96", align 1
%"145" = load i1, ptr addrspace(5) %"96", align 1
br i1 %"145", label %"34", label %"35"
"34": ; preds = %"33", %"32"
%"143" = load i64, ptr addrspace(5) %"89", align 8
%"164" = inttoptr i64 %"143" to ptr
%"80" = getelementptr inbounds i8, ptr %"164", i64 8
%"144" = load i32, ptr addrspace(5) %"98", align 4
store i32 %"144", ptr %"80", align 4
%"146" = load float, ptr addrspace(5) %"96", align 4
%"147" = load float, ptr addrspace(5) %"97", align 4
%5 = fcmp uno float %"146", %"147"
store i1 %5, ptr addrspace(5) %"99", align 1
%"148" = load i1, ptr addrspace(5) %"99", align 1
br i1 %"148", label %"35", label %"36"
"34": ; preds = %"33"
store i32 1, ptr addrspace(5) %"95", align 4
br label %"35"
"35": ; preds = %"34"
store i32 1, ptr addrspace(5) %"98", align 4
br label %"36"
"35": ; preds = %"34", %"33"
%"147" = load i1, ptr addrspace(5) %"96", align 1
br i1 %"147", label %"37", label %"36"
"36": ; preds = %"35", %"34"
%"150" = load i1, ptr addrspace(5) %"99", align 1
br i1 %"150", label %"38", label %"37"
"36": ; preds = %"35"
store i32 0, ptr addrspace(5) %"95", align 4
br label %"37"
"37": ; preds = %"36"
store i32 0, ptr addrspace(5) %"98", align 4
br label %"38"
"37": ; preds = %"36", %"35"
%"149" = load i64, ptr addrspace(5) %"86", align 8
%"162" = inttoptr i64 %"149" to ptr
%"81" = getelementptr inbounds i8, ptr %"162", i64 12
%"150" = load i32, ptr addrspace(5) %"95", align 4
store i32 %"150", ptr %"81", align 4
"38": ; preds = %"37", %"36"
%"152" = load i64, ptr addrspace(5) %"89", align 8
%"165" = inttoptr i64 %"152" to ptr
%"84" = getelementptr inbounds i8, ptr %"165", i64 12
%"153" = load i32, ptr addrspace(5) %"98", align 4
store i32 %"153", ptr %"84", align 4
ret void
}

272
ptx/src/test/ll/setp_num.ll
View file

@ -1,164 +1,164 @@
define amdgpu_kernel void @setp_num(ptr addrspace(4) byref(i64) %"83", ptr addrspace(4) byref(i64) %"84") #0 {
%"85" = alloca i64, align 8, addrspace(5)
%"86" = alloca i64, align 8, addrspace(5)
%"87" = alloca float, align 4, addrspace(5)
%"88" = alloca float, align 4, addrspace(5)
%"89" = alloca float, align 4, addrspace(5)
define amdgpu_kernel void @setp_num(ptr addrspace(4) byref(i64) %"86", ptr addrspace(4) byref(i64) %"87") #0 {
%"88" = alloca i64, align 8, addrspace(5)
%"89" = alloca i64, align 8, addrspace(5)
%"90" = alloca float, align 4, addrspace(5)
%"91" = alloca float, align 4, addrspace(5)
%"92" = alloca float, align 4, addrspace(5)
%"93" = alloca float, align 4, addrspace(5)
%"94" = alloca float, align 4, addrspace(5)
%"95" = alloca i32, align 4, addrspace(5)
%"96" = alloca i1, align 1, addrspace(5)
%"95" = alloca float, align 4, addrspace(5)
%"96" = alloca float, align 4, addrspace(5)
%"97" = alloca float, align 4, addrspace(5)
%"98" = alloca i32, align 4, addrspace(5)
%"99" = alloca i1, align 1, addrspace(5)
br label %1
1: ; preds = %0
br label %"82"
br label %"85"
"82": ; preds = %1
%"97" = load i64, ptr addrspace(4) %"83", align 8
store i64 %"97", ptr addrspace(5) %"85", align 8
%"98" = load i64, ptr addrspace(4) %"84", align 8
store i64 %"98", ptr addrspace(5) %"86", align 8
%"100" = load i64, ptr addrspace(5) %"85", align 8
%"151" = inttoptr i64 %"100" to ptr
%"99" = load float, ptr %"151", align 4
store float %"99", ptr addrspace(5) %"87", align 4
%"101" = load i64, ptr addrspace(5) %"85", align 8
%"152" = inttoptr i64 %"101" to ptr
%"55" = getelementptr inbounds i8, ptr %"152", i64 4
%"102" = load float, ptr %"55", align 4
store float %"102", ptr addrspace(5) %"88", align 4
%"103" = load i64, ptr addrspace(5) %"85", align 8
%"153" = inttoptr i64 %"103" to ptr
%"57" = getelementptr inbounds i8, ptr %"153", i64 8
%"104" = load float, ptr %"57", align 4
store float %"104", ptr addrspace(5) %"89", align 4
%"105" = load i64, ptr addrspace(5) %"85", align 8
%"154" = inttoptr i64 %"105" to ptr
%"59" = getelementptr inbounds i8, ptr %"154", i64 12
%"106" = load float, ptr %"59", align 4
store float %"106", ptr addrspace(5) %"90", align 4
%"107" = load i64, ptr addrspace(5) %"85", align 8
%"155" = inttoptr i64 %"107" to ptr
%"61" = getelementptr inbounds i8, ptr %"155", i64 16
%"108" = load float, ptr %"61", align 4
store float %"108", ptr addrspace(5) %"91", align 4
%"109" = load i64, ptr addrspace(5) %"85", align 8
%"156" = inttoptr i64 %"109" to ptr
%"63" = getelementptr inbounds i8, ptr %"156", i64 20
%"110" = load float, ptr %"63", align 4
store float %"110", ptr addrspace(5) %"92", align 4
%"111" = load i64, ptr addrspace(5) %"85", align 8
%"157" = inttoptr i64 %"111" to ptr
%"65" = getelementptr inbounds i8, ptr %"157", i64 24
%"112" = load float, ptr %"65", align 4
store float %"112", ptr addrspace(5) %"93", align 4
%"113" = load i64, ptr addrspace(5) %"85", align 8
%"158" = inttoptr i64 %"113" to ptr
%"67" = getelementptr inbounds i8, ptr %"158", i64 28
%"114" = load float, ptr %"67", align 4
store float %"114", ptr addrspace(5) %"94", align 4
%"116" = load float, ptr addrspace(5) %"87", align 4
%"117" = load float, ptr addrspace(5) %"88", align 4
%2 = fcmp ord float %"116", %"117"
store i1 %2, ptr addrspace(5) %"96", align 1
%"118" = load i1, ptr addrspace(5) %"96", align 1
br i1 %"118", label %"22", label %"23"
"85": ; preds = %1
%"100" = load i64, ptr addrspace(4) %"86", align 8
store i64 %"100", ptr addrspace(5) %"88", align 8
%"101" = load i64, ptr addrspace(4) %"87", align 8
store i64 %"101", ptr addrspace(5) %"89", align 8
%"103" = load i64, ptr addrspace(5) %"88", align 8
%"154" = inttoptr i64 %"103" to ptr
%"102" = load float, ptr %"154", align 4
store float %"102", ptr addrspace(5) %"90", align 4
%"104" = load i64, ptr addrspace(5) %"88", align 8
%"155" = inttoptr i64 %"104" to ptr
%"58" = getelementptr inbounds i8, ptr %"155", i64 4
%"105" = load float, ptr %"58", align 4
store float %"105", ptr addrspace(5) %"91", align 4
%"106" = load i64, ptr addrspace(5) %"88", align 8
%"156" = inttoptr i64 %"106" to ptr
%"60" = getelementptr inbounds i8, ptr %"156", i64 8
%"107" = load float, ptr %"60", align 4
store float %"107", ptr addrspace(5) %"92", align 4
%"108" = load i64, ptr addrspace(5) %"88", align 8
%"157" = inttoptr i64 %"108" to ptr
%"62" = getelementptr inbounds i8, ptr %"157", i64 12
%"109" = load float, ptr %"62", align 4
store float %"109", ptr addrspace(5) %"93", align 4
%"110" = load i64, ptr addrspace(5) %"88", align 8
%"158" = inttoptr i64 %"110" to ptr
%"64" = getelementptr inbounds i8, ptr %"158", i64 16
%"111" = load float, ptr %"64", align 4
store float %"111", ptr addrspace(5) %"94", align 4
%"112" = load i64, ptr addrspace(5) %"88", align 8
%"159" = inttoptr i64 %"112" to ptr
%"66" = getelementptr inbounds i8, ptr %"159", i64 20
%"113" = load float, ptr %"66", align 4
store float %"113", ptr addrspace(5) %"95", align 4
%"114" = load i64, ptr addrspace(5) %"88", align 8
%"160" = inttoptr i64 %"114" to ptr
%"68" = getelementptr inbounds i8, ptr %"160", i64 24
%"115" = load float, ptr %"68", align 4
store float %"115", ptr addrspace(5) %"96", align 4
%"116" = load i64, ptr addrspace(5) %"88", align 8
%"161" = inttoptr i64 %"116" to ptr
%"70" = getelementptr inbounds i8, ptr %"161", i64 28
%"117" = load float, ptr %"70", align 4
store float %"117", ptr addrspace(5) %"97", align 4
%"119" = load float, ptr addrspace(5) %"90", align 4
%"120" = load float, ptr addrspace(5) %"91", align 4
%2 = fcmp ord float %"119", %"120"
store i1 %2, ptr addrspace(5) %"99", align 1
%"121" = load i1, ptr addrspace(5) %"99", align 1
br i1 %"121", label %"23", label %"24"
"22": ; preds = %"82"
store i32 2, ptr addrspace(5) %"95", align 4
br label %"23"
"23": ; preds = %"85"
store i32 2, ptr addrspace(5) %"98", align 4
br label %"24"
"23": ; preds = %"22", %"82"
%"120" = load i1, ptr addrspace(5) %"96", align 1
br i1 %"120", label %"25", label %"24"
"24": ; preds = %"23", %"85"
%"123" = load i1, ptr addrspace(5) %"99", align 1
br i1 %"123", label %"26", label %"25"
"24": ; preds = %"23"
store i32 0, ptr addrspace(5) %"95", align 4
br label %"25"
"25": ; preds = %"24"
store i32 0, ptr addrspace(5) %"98", align 4
br label %"26"
"25": ; preds = %"24", %"23"
%"122" = load i64, ptr addrspace(5) %"86", align 8
%"123" = load i32, ptr addrspace(5) %"95", align 4
%"159" = inttoptr i64 %"122" to ptr
store i32 %"123", ptr %"159", align 4
%"125" = load float, ptr addrspace(5) %"89", align 4
%"126" = load float, ptr addrspace(5) %"90", align 4
%3 = fcmp ord float %"125", %"126"
store i1 %3, ptr addrspace(5) %"96", align 1
%"127" = load i1, ptr addrspace(5) %"96", align 1
br i1 %"127", label %"26", label %"27"
"26": ; preds = %"25", %"24"
%"125" = load i64, ptr addrspace(5) %"89", align 8
%"126" = load i32, ptr addrspace(5) %"98", align 4
%"162" = inttoptr i64 %"125" to ptr
store i32 %"126", ptr %"162", align 4
%"128" = load float, ptr addrspace(5) %"92", align 4
%"129" = load float, ptr addrspace(5) %"93", align 4
%3 = fcmp ord float %"128", %"129"
store i1 %3, ptr addrspace(5) %"99", align 1
%"130" = load i1, ptr addrspace(5) %"99", align 1
br i1 %"130", label %"27", label %"28"
"26": ; preds = %"25"
store i32 2, ptr addrspace(5) %"95", align 4
br label %"27"
"27": ; preds = %"26"
store i32 2, ptr addrspace(5) %"98", align 4
br label %"28"
"27": ; preds = %"26", %"25"
%"129" = load i1, ptr addrspace(5) %"96", align 1
br i1 %"129", label %"29", label %"28"
"28": ; preds = %"27", %"26"
%"132" = load i1, ptr addrspace(5) %"99", align 1
br i1 %"132", label %"30", label %"29"
"28": ; preds = %"27"
store i32 0, ptr addrspace(5) %"95", align 4
br label %"29"
"29": ; preds = %"28"
store i32 0, ptr addrspace(5) %"98", align 4
br label %"30"
"29": ; preds = %"28", %"27"
%"131" = load i64, ptr addrspace(5) %"86", align 8
%"160" = inttoptr i64 %"131" to ptr
%"73" = getelementptr inbounds i8, ptr %"160", i64 4
%"132" = load i32, ptr addrspace(5) %"95", align 4
store i32 %"132", ptr %"73", align 4
%"134" = load float, ptr addrspace(5) %"91", align 4
%"135" = load float, ptr addrspace(5) %"92", align 4
%4 = fcmp ord float %"134", %"135"
store i1 %4, ptr addrspace(5) %"96", align 1
%"136" = load i1, ptr addrspace(5) %"96", align 1
br i1 %"136", label %"30", label %"31"
"30": ; preds = %"29", %"28"
%"134" = load i64, ptr addrspace(5) %"89", align 8
%"163" = inttoptr i64 %"134" to ptr
%"76" = getelementptr inbounds i8, ptr %"163", i64 4
%"135" = load i32, ptr addrspace(5) %"98", align 4
store i32 %"135", ptr %"76", align 4
%"137" = load float, ptr addrspace(5) %"94", align 4
%"138" = load float, ptr addrspace(5) %"95", align 4
%4 = fcmp ord float %"137", %"138"
store i1 %4, ptr addrspace(5) %"99", align 1
%"139" = load i1, ptr addrspace(5) %"99", align 1
br i1 %"139", label %"31", label %"32"
"30": ; preds = %"29"
store i32 2, ptr addrspace(5) %"95", align 4
br label %"31"
"31": ; preds = %"30"
store i32 2, ptr addrspace(5) %"98", align 4
br label %"32"
"31": ; preds = %"30", %"29"
%"138" = load i1, ptr addrspace(5) %"96", align 1
br i1 %"138", label %"33", label %"32"
"32": ; preds = %"31", %"30"
%"141" = load i1, ptr addrspace(5) %"99", align 1
br i1 %"141", label %"34", label %"33"
"32": ; preds = %"31"
store i32 0, ptr addrspace(5) %"95", align 4
br label %"33"
"33": ; preds = %"32"
store i32 0, ptr addrspace(5) %"98", align 4
br label %"34"
"33": ; preds = %"32", %"31"
%"140" = load i64, ptr addrspace(5) %"86", align 8
%"161" = inttoptr i64 %"140" to ptr
%"77" = getelementptr inbounds i8, ptr %"161", i64 8
%"141" = load i32, ptr addrspace(5) %"95", align 4
store i32 %"141", ptr %"77", align 4
%"143" = load float, ptr addrspace(5) %"93", align 4
%"144" = load float, ptr addrspace(5) %"94", align 4
%5 = fcmp ord float %"143", %"144"
store i1 %5, ptr addrspace(5) %"96", align 1
%"145" = load i1, ptr addrspace(5) %"96", align 1
br i1 %"145", label %"34", label %"35"
"34": ; preds = %"33", %"32"
%"143" = load i64, ptr addrspace(5) %"89", align 8
%"164" = inttoptr i64 %"143" to ptr
%"80" = getelementptr inbounds i8, ptr %"164", i64 8
%"144" = load i32, ptr addrspace(5) %"98", align 4
store i32 %"144", ptr %"80", align 4
%"146" = load float, ptr addrspace(5) %"96", align 4
%"147" = load float, ptr addrspace(5) %"97", align 4
%5 = fcmp ord float %"146", %"147"
store i1 %5, ptr addrspace(5) %"99", align 1
%"148" = load i1, ptr addrspace(5) %"99", align 1
br i1 %"148", label %"35", label %"36"
"34": ; preds = %"33"
store i32 2, ptr addrspace(5) %"95", align 4
br label %"35"
"35": ; preds = %"34"
store i32 2, ptr addrspace(5) %"98", align 4
br label %"36"
"35": ; preds = %"34", %"33"
%"147" = load i1, ptr addrspace(5) %"96", align 1
br i1 %"147", label %"37", label %"36"
"36": ; preds = %"35", %"34"
%"150" = load i1, ptr addrspace(5) %"99", align 1
br i1 %"150", label %"38", label %"37"
"36": ; preds = %"35"
store i32 0, ptr addrspace(5) %"95", align 4
br label %"37"
"37": ; preds = %"36"
store i32 0, ptr addrspace(5) %"98", align 4
br label %"38"
"37": ; preds = %"36", %"35"
%"149" = load i64, ptr addrspace(5) %"86", align 8
%"162" = inttoptr i64 %"149" to ptr
%"81" = getelementptr inbounds i8, ptr %"162", i64 12
%"150" = load i32, ptr addrspace(5) %"95", align 4
store i32 %"150", ptr %"81", align 4
"38": ; preds = %"37", %"36"
%"152" = load i64, ptr addrspace(5) %"89", align 8
%"165" = inttoptr i64 %"152" to ptr
%"84" = getelementptr inbounds i8, ptr %"165", i64 12
%"153" = load i32, ptr addrspace(5) %"98", align 4
store i32 %"153", ptr %"84", align 4
ret void
}

54
ptx/src/test/ll/shared_ptr_32.ll
View file

@ -1,39 +1,39 @@
@shared_mem1 = external addrspace(3) global [128 x i8], align 4
define amdgpu_kernel void @shared_ptr_32(ptr addrspace(4) byref(i64) %"35", ptr addrspace(4) byref(i64) %"36") #0 {
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i32, align 4, addrspace(5)
define amdgpu_kernel void @shared_ptr_32(ptr addrspace(4) byref(i64) %"38", ptr addrspace(4) byref(i64) %"39") #0 {
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i32, align 4, addrspace(5)
%"43" = alloca i64, align 8, addrspace(5)
%"44" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"34"
br label %"37"
"34": ; preds = %1
%"42" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"42", ptr addrspace(5) %"37", align 8
%"43" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"43", ptr addrspace(5) %"38", align 8
store i32 ptrtoint (ptr addrspace(3) @shared_mem1 to i32), ptr addrspace(5) %"39", align 4
%"46" = load i64, ptr addrspace(5) %"37", align 8
%"54" = inttoptr i64 %"46" to ptr addrspace(1)
%"45" = load i64, ptr addrspace(1) %"54", align 8
"37": ; preds = %1
%"45" = load i64, ptr addrspace(4) %"38", align 8
store i64 %"45", ptr addrspace(5) %"40", align 8
%"47" = load i32, ptr addrspace(5) %"39", align 4
%"48" = load i64, ptr addrspace(5) %"40", align 8
%"55" = inttoptr i32 %"47" to ptr addrspace(3)
store i64 %"48", ptr addrspace(3) %"55", align 8
%"49" = load i32, ptr addrspace(5) %"39", align 4
%"56" = inttoptr i32 %"49" to ptr addrspace(3)
%"33" = getelementptr inbounds i8, ptr addrspace(3) %"56", i64 0
%"50" = load i64, ptr addrspace(3) %"33", align 8
store i64 %"50", ptr addrspace(5) %"41", align 8
%"51" = load i64, ptr addrspace(5) %"38", align 8
%"52" = load i64, ptr addrspace(5) %"41", align 8
%"57" = inttoptr i64 %"51" to ptr addrspace(1)
store i64 %"52", ptr addrspace(1) %"57", align 8
%"46" = load i64, ptr addrspace(4) %"39", align 8
store i64 %"46", ptr addrspace(5) %"41", align 8
store i32 ptrtoint (ptr addrspace(3) @shared_mem1 to i32), ptr addrspace(5) %"42", align 4
%"49" = load i64, ptr addrspace(5) %"40", align 8
%"57" = inttoptr i64 %"49" to ptr addrspace(1)
%"48" = load i64, ptr addrspace(1) %"57", align 8
store i64 %"48", ptr addrspace(5) %"43", align 8
%"50" = load i32, ptr addrspace(5) %"42", align 4
%"51" = load i64, ptr addrspace(5) %"43", align 8
%"58" = inttoptr i32 %"50" to ptr addrspace(3)
store i64 %"51", ptr addrspace(3) %"58", align 8
%"52" = load i32, ptr addrspace(5) %"42", align 4
%"59" = inttoptr i32 %"52" to ptr addrspace(3)
%"36" = getelementptr inbounds i8, ptr addrspace(3) %"59", i64 0
%"53" = load i64, ptr addrspace(3) %"36", align 8
store i64 %"53", ptr addrspace(5) %"44", align 8
%"54" = load i64, ptr addrspace(5) %"41", align 8
%"55" = load i64, ptr addrspace(5) %"44", align 8
%"60" = inttoptr i64 %"54" to ptr addrspace(1)
store i64 %"55", ptr addrspace(1) %"60", align 8
ret void
}

52
ptx/src/test/ll/shared_ptr_take_address.ll
View file

@ -1,38 +1,38 @@
@shared_mem = external addrspace(3) global [0 x i8], align 4
define amdgpu_kernel void @shared_ptr_take_address(ptr addrspace(4) byref(i64) %"33", ptr addrspace(4) byref(i64) %"34") #0 {
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
%"37" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @shared_ptr_take_address(ptr addrspace(4) byref(i64) %"36", ptr addrspace(4) byref(i64) %"37") #0 {
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
%"41" = alloca i64, align 8, addrspace(5)
%"42" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"32"
br label %"35"
"32": ; preds = %1
%"40" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"40", ptr addrspace(5) %"35", align 8
%"41" = load i64, ptr addrspace(4) %"34", align 8
store i64 %"41", ptr addrspace(5) %"36", align 8
store i64 ptrtoint (ptr addrspace(3) @shared_mem to i64), ptr addrspace(5) %"37", align 8
%"44" = load i64, ptr addrspace(5) %"35", align 8
%"52" = inttoptr i64 %"44" to ptr addrspace(1)
%"43" = load i64, ptr addrspace(1) %"52", align 8
"35": ; preds = %1
%"43" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"43", ptr addrspace(5) %"38", align 8
%"45" = load i64, ptr addrspace(5) %"37", align 8
%"46" = load i64, ptr addrspace(5) %"38", align 8
%"53" = inttoptr i64 %"45" to ptr addrspace(3)
store i64 %"46", ptr addrspace(3) %"53", align 8
%"48" = load i64, ptr addrspace(5) %"37", align 8
%"54" = inttoptr i64 %"48" to ptr addrspace(3)
%"47" = load i64, ptr addrspace(3) %"54", align 8
store i64 %"47", ptr addrspace(5) %"39", align 8
%"49" = load i64, ptr addrspace(5) %"36", align 8
%"50" = load i64, ptr addrspace(5) %"39", align 8
%"55" = inttoptr i64 %"49" to ptr addrspace(1)
store i64 %"50", ptr addrspace(1) %"55", align 8
%"44" = load i64, ptr addrspace(4) %"37", align 8
store i64 %"44", ptr addrspace(5) %"39", align 8
store i64 ptrtoint (ptr addrspace(3) @shared_mem to i64), ptr addrspace(5) %"40", align 8
%"47" = load i64, ptr addrspace(5) %"38", align 8
%"55" = inttoptr i64 %"47" to ptr addrspace(1)
%"46" = load i64, ptr addrspace(1) %"55", align 8
store i64 %"46", ptr addrspace(5) %"41", align 8
%"48" = load i64, ptr addrspace(5) %"40", align 8
%"49" = load i64, ptr addrspace(5) %"41", align 8
%"56" = inttoptr i64 %"48" to ptr addrspace(3)
store i64 %"49", ptr addrspace(3) %"56", align 8
%"51" = load i64, ptr addrspace(5) %"40", align 8
%"57" = inttoptr i64 %"51" to ptr addrspace(3)
%"50" = load i64, ptr addrspace(3) %"57", align 8
store i64 %"50", ptr addrspace(5) %"42", align 8
%"52" = load i64, ptr addrspace(5) %"39", align 8
%"53" = load i64, ptr addrspace(5) %"42", align 8
%"58" = inttoptr i64 %"52" to ptr addrspace(1)
store i64 %"53", ptr addrspace(1) %"58", align 8
ret void
}

134
ptx/src/test/ll/shared_unify_extern.ll
View file

@ -2,81 +2,81 @@
@shared_mod = external addrspace(3) global [4 x i32]
define hidden i64 @add() #0 {
%"46" = alloca i64, align 8, addrspace(5)
%"47" = alloca i64, align 8, addrspace(5)
%"48" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"41"
"41": ; preds = %1
%"49" = load i64, ptr addrspace(3) @shared_mod, align 8
store i64 %"49", ptr addrspace(5) %"47", align 8
%"50" = load i64, ptr addrspace(3) @shared_ex, align 8
store i64 %"50", ptr addrspace(5) %"48", align 8
%"52" = load i64, ptr addrspace(5) %"48", align 8
%"53" = load i64, ptr addrspace(5) %"47", align 8
%"75" = add i64 %"52", %"53"
store i64 %"75", ptr addrspace(5) %"46", align 8
%2 = load i64, ptr addrspace(5) %"46", align 8
ret i64 %2
}
define hidden i64 @set_shared_temp1(i64 %"15") #0 {
%"54" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"42"
"42": ; preds = %1
store i64 %"15", ptr addrspace(3) @shared_ex, align 8
%"55" = call i64 @add()
store i64 %"55", ptr addrspace(5) %"54", align 8
br label %"43"
"43": ; preds = %"42"
%2 = load i64, ptr addrspace(5) %"54", align 8
ret i64 %2
}
define amdgpu_kernel void @shared_unify_extern(ptr addrspace(4) byref(i64) %"56", ptr addrspace(4) byref(i64) %"57") #1 {
%"58" = alloca i64, align 8, addrspace(5)
%"59" = alloca i64, align 8, addrspace(5)
%"60" = alloca i64, align 8, addrspace(5)
%"61" = alloca i64, align 8, addrspace(5)
%"49" = alloca i64, align 8, addrspace(5)
%"50" = alloca i64, align 8, addrspace(5)
%"51" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"44"
"44": ; preds = %1
%"62" = load i64, ptr addrspace(4) %"56", align 8
store i64 %"62", ptr addrspace(5) %"58", align 8
%"63" = load i64, ptr addrspace(4) %"57", align 8
store i64 %"63", ptr addrspace(5) %"59", align 8
%"65" = load i64, ptr addrspace(5) %"58", align 8
%"78" = inttoptr i64 %"65" to ptr addrspace(1)
%"64" = load i64, ptr addrspace(1) %"78", align 8
store i64 %"64", ptr addrspace(5) %"60", align 8
%"66" = load i64, ptr addrspace(5) %"58", align 8
%"79" = inttoptr i64 %"66" to ptr addrspace(1)
%"40" = getelementptr inbounds i8, ptr addrspace(1) %"79", i64 8
%"67" = load i64, ptr addrspace(1) %"40", align 8
store i64 %"67", ptr addrspace(5) %"61", align 8
%"68" = load i64, ptr addrspace(5) %"61", align 8
store i64 %"68", ptr addrspace(3) @shared_mod, align 8
%"70" = load i64, ptr addrspace(5) %"60", align 8
%"81" = call i64 @set_shared_temp1(i64 %"70")
store i64 %"81", ptr addrspace(5) %"61", align 8
%"52" = load i64, ptr addrspace(3) @shared_mod, align 8
store i64 %"52", ptr addrspace(5) %"50", align 8
%"53" = load i64, ptr addrspace(3) @shared_ex, align 8
store i64 %"53", ptr addrspace(5) %"51", align 8
%"55" = load i64, ptr addrspace(5) %"51", align 8
%"56" = load i64, ptr addrspace(5) %"50", align 8
%"78" = add i64 %"55", %"56"
store i64 %"78", ptr addrspace(5) %"49", align 8
%2 = load i64, ptr addrspace(5) %"49", align 8
ret i64 %2
}
define hidden i64 @set_shared_temp1(i64 %"16") #0 {
%"57" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"45"
"45": ; preds = %"44"
%"71" = load i64, ptr addrspace(5) %"59", align 8
%"72" = load i64, ptr addrspace(5) %"61", align 8
%"83" = inttoptr i64 %"71" to ptr
store i64 %"72", ptr %"83", align 8
"45": ; preds = %1
store i64 %"16", ptr addrspace(3) @shared_ex, align 8
%"58" = call i64 @add()
store i64 %"58", ptr addrspace(5) %"57", align 8
br label %"46"
"46": ; preds = %"45"
%2 = load i64, ptr addrspace(5) %"57", align 8
ret i64 %2
}
define amdgpu_kernel void @shared_unify_extern(ptr addrspace(4) byref(i64) %"59", ptr addrspace(4) byref(i64) %"60") #1 {
%"61" = alloca i64, align 8, addrspace(5)
%"62" = alloca i64, align 8, addrspace(5)
%"63" = alloca i64, align 8, addrspace(5)
%"64" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"47"
"47": ; preds = %1
%"65" = load i64, ptr addrspace(4) %"59", align 8
store i64 %"65", ptr addrspace(5) %"61", align 8
%"66" = load i64, ptr addrspace(4) %"60", align 8
store i64 %"66", ptr addrspace(5) %"62", align 8
%"68" = load i64, ptr addrspace(5) %"61", align 8
%"81" = inttoptr i64 %"68" to ptr addrspace(1)
%"67" = load i64, ptr addrspace(1) %"81", align 8
store i64 %"67", ptr addrspace(5) %"63", align 8
%"69" = load i64, ptr addrspace(5) %"61", align 8
%"82" = inttoptr i64 %"69" to ptr addrspace(1)
%"43" = getelementptr inbounds i8, ptr addrspace(1) %"82", i64 8
%"70" = load i64, ptr addrspace(1) %"43", align 8
store i64 %"70", ptr addrspace(5) %"64", align 8
%"71" = load i64, ptr addrspace(5) %"64", align 8
store i64 %"71", ptr addrspace(3) @shared_mod, align 8
%"73" = load i64, ptr addrspace(5) %"63", align 8
%"84" = call i64 @set_shared_temp1(i64 %"73")
store i64 %"84", ptr addrspace(5) %"64", align 8
br label %"48"
"48": ; preds = %"47"
%"74" = load i64, ptr addrspace(5) %"62", align 8
%"75" = load i64, ptr addrspace(5) %"64", align 8
%"86" = inttoptr i64 %"74" to ptr
store i64 %"75", ptr %"86", align 8
ret void
}

130
ptx/src/test/ll/shared_unify_local.ll
View file

@ -1,79 +1,79 @@
@shared_ex = external addrspace(3) global [0 x i32]
@shared_mod = external addrspace(3) global i64, align 4
define hidden i64 @add(i64 %"10") #0 {
%"47" = alloca i64, align 8, addrspace(5)
%"48" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"42"
"42": ; preds = %1
store i64 %"10", ptr addrspace(3) @shared_mod, align 8
%"49" = load i64, ptr addrspace(3) @shared_mod, align 8
store i64 %"49", ptr addrspace(5) %"48", align 8
%"101" = load i64, ptr addrspace(3) @shared_ex, align 8
%"51" = load i64, ptr addrspace(5) %"48", align 8
%"72" = add i64 %"101", %"51"
store i64 %"72", ptr addrspace(5) %"47", align 8
%2 = load i64, ptr addrspace(5) %"47", align 8
ret i64 %2
}
define hidden i64 @set_shared_temp1(i64 %"15", i64 %"16") #0 {
%"52" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"43"
"43": ; preds = %1
store i64 %"15", ptr addrspace(3) @shared_ex, align 8
%"53" = call i64 @add(i64 %"16")
store i64 %"53", ptr addrspace(5) %"52", align 8
br label %"44"
"44": ; preds = %"43"
%2 = load i64, ptr addrspace(5) %"52", align 8
ret i64 %2
}
define amdgpu_kernel void @shared_unify_local(ptr addrspace(4) byref(i64) %"54", ptr addrspace(4) byref(i64) %"55") #1 {
%"56" = alloca i64, align 8, addrspace(5)
%"57" = alloca i64, align 8, addrspace(5)
%"58" = alloca i64, align 8, addrspace(5)
%"59" = alloca i64, align 8, addrspace(5)
define hidden i64 @add(i64 %"11") #0 {
%"50" = alloca i64, align 8, addrspace(5)
%"51" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"45"
"45": ; preds = %1
%"60" = load i64, ptr addrspace(4) %"54", align 8
store i64 %"60", ptr addrspace(5) %"56", align 8
%"61" = load i64, ptr addrspace(4) %"55", align 8
store i64 %"61", ptr addrspace(5) %"57", align 8
%"63" = load i64, ptr addrspace(5) %"56", align 8
%"75" = inttoptr i64 %"63" to ptr addrspace(1)
%"62" = load i64, ptr addrspace(1) %"75", align 8
store i64 %"62", ptr addrspace(5) %"58", align 8
%"64" = load i64, ptr addrspace(5) %"56", align 8
%"76" = inttoptr i64 %"64" to ptr addrspace(1)
%"41" = getelementptr inbounds i8, ptr addrspace(1) %"76", i64 8
%"65" = load i64, ptr addrspace(1) %"41", align 8
store i64 %"65", ptr addrspace(5) %"59", align 8
%"67" = load i64, ptr addrspace(5) %"58", align 8
%"68" = load i64, ptr addrspace(5) %"59", align 8
%"77" = call i64 @set_shared_temp1(i64 %"67", i64 %"68")
store i64 %"77", ptr addrspace(5) %"59", align 8
store i64 %"11", ptr addrspace(3) @shared_mod, align 8
%"52" = load i64, ptr addrspace(3) @shared_mod, align 8
store i64 %"52", ptr addrspace(5) %"51", align 8
%"111" = load i64, ptr addrspace(3) @shared_ex, align 8
%"54" = load i64, ptr addrspace(5) %"51", align 8
%"75" = add i64 %"111", %"54"
store i64 %"75", ptr addrspace(5) %"50", align 8
%2 = load i64, ptr addrspace(5) %"50", align 8
ret i64 %2
}
define hidden i64 @set_shared_temp1(i64 %"16", i64 %"17") #0 {
%"55" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"46"
"46": ; preds = %"45"
%"69" = load i64, ptr addrspace(5) %"57", align 8
%"70" = load i64, ptr addrspace(5) %"59", align 8
%"79" = inttoptr i64 %"69" to ptr
store i64 %"70", ptr %"79", align 8
"46": ; preds = %1
store i64 %"16", ptr addrspace(3) @shared_ex, align 8
%"56" = call i64 @add(i64 %"17")
store i64 %"56", ptr addrspace(5) %"55", align 8
br label %"47"
"47": ; preds = %"46"
%2 = load i64, ptr addrspace(5) %"55", align 8
ret i64 %2
}
define amdgpu_kernel void @shared_unify_local(ptr addrspace(4) byref(i64) %"57", ptr addrspace(4) byref(i64) %"58") #1 {
%"59" = alloca i64, align 8, addrspace(5)
%"60" = alloca i64, align 8, addrspace(5)
%"61" = alloca i64, align 8, addrspace(5)
%"62" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"48"
"48": ; preds = %1
%"63" = load i64, ptr addrspace(4) %"57", align 8
store i64 %"63", ptr addrspace(5) %"59", align 8
%"64" = load i64, ptr addrspace(4) %"58", align 8
store i64 %"64", ptr addrspace(5) %"60", align 8
%"66" = load i64, ptr addrspace(5) %"59", align 8
%"78" = inttoptr i64 %"66" to ptr addrspace(1)
%"65" = load i64, ptr addrspace(1) %"78", align 8
store i64 %"65", ptr addrspace(5) %"61", align 8
%"67" = load i64, ptr addrspace(5) %"59", align 8
%"79" = inttoptr i64 %"67" to ptr addrspace(1)
%"44" = getelementptr inbounds i8, ptr addrspace(1) %"79", i64 8
%"68" = load i64, ptr addrspace(1) %"44", align 8
store i64 %"68", ptr addrspace(5) %"62", align 8
%"70" = load i64, ptr addrspace(5) %"61", align 8
%"71" = load i64, ptr addrspace(5) %"62", align 8
%"80" = call i64 @set_shared_temp1(i64 %"70", i64 %"71")
store i64 %"80", ptr addrspace(5) %"62", align 8
br label %"49"
"49": ; preds = %"48"
%"72" = load i64, ptr addrspace(5) %"60", align 8
%"73" = load i64, ptr addrspace(5) %"62", align 8
%"82" = inttoptr i64 %"72" to ptr
store i64 %"73", ptr %"82", align 8
ret void
}

42
ptx/src/test/ll/shared_variable.ll
View file

@ -1,32 +1,32 @@
@shared_mem1 = external addrspace(3) global [128 x i8], align 4
define amdgpu_kernel void @shared_variable(ptr addrspace(4) byref(i64) %"32", ptr addrspace(4) byref(i64) %"33") #0 {
%"34" = alloca i64, align 8, addrspace(5)
%"35" = alloca i64, align 8, addrspace(5)
%"36" = alloca i64, align 8, addrspace(5)
define amdgpu_kernel void @shared_variable(ptr addrspace(4) byref(i64) %"35", ptr addrspace(4) byref(i64) %"36") #0 {
%"37" = alloca i64, align 8, addrspace(5)
%"38" = alloca i64, align 8, addrspace(5)
%"39" = alloca i64, align 8, addrspace(5)
%"40" = alloca i64, align 8, addrspace(5)
br label %1
1: ; preds = %0
br label %"31"
br label %"34"
"31": ; preds = %1
%"38" = load i64, ptr addrspace(4) %"32", align 8
store i64 %"38", ptr addrspace(5) %"34", align 8
%"39" = load i64, ptr addrspace(4) %"33", align 8
store i64 %"39", ptr addrspace(5) %"35", align 8
%"41" = load i64, ptr addrspace(5) %"34", align 8
%"46" = inttoptr i64 %"41" to ptr addrspace(1)
%"40" = load i64, ptr addrspace(1) %"46", align 8
store i64 %"40", ptr addrspace(5) %"36", align 8
%"42" = load i64, ptr addrspace(5) %"36", align 8
store i64 %"42", ptr addrspace(3) @shared_mem1, align 8
%"43" = load i64, ptr addrspace(3) @shared_mem1, align 8
store i64 %"43", ptr addrspace(5) %"37", align 8
%"44" = load i64, ptr addrspace(5) %"35", align 8
%"45" = load i64, ptr addrspace(5) %"37", align 8
"34": ; preds = %1
%"41" = load i64, ptr addrspace(4) %"35", align 8
store i64 %"41", ptr addrspace(5) %"37", align 8
%"42" = load i64, ptr addrspace(4) %"36", align 8
store i64 %"42", ptr addrspace(5) %"38", align 8
%"44" = load i64, ptr addrspace(5) %"37", align 8
%"49" = inttoptr i64 %"44" to ptr addrspace(1)
store i64 %"45", ptr addrspace(1) %"49", align 8
%"43" = load i64, ptr addrspace(1) %"49", align 8
store i64 %"43", ptr addrspace(5) %"39", align 8
%"45" = load i64, ptr addrspace(5) %"39", align 8
store i64 %"45", ptr addrspace(3) @shared_mem1, align 8
%"46" = load i64, ptr addrspace(3) @shared_mem1, align 8
store i64 %"46", ptr addrspace(5) %"40", align 8
%"47" = load i64, ptr addrspace(5) %"38", align 8
%"48" = load i64, ptr addrspace(5) %"40", align 8
%"52" = inttoptr i64 %"47" to ptr addrspace(1)
store i64 %"48", ptr addrspace(1) %"52", align 8
ret void
}

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