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https://github.com/vosen/ZLUDA.git
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Remove PrmtSlow
This commit is contained in:
Violet
parent
ddc00895a7
commit
12a5f14837
8 changed files with 36 additions and 97 deletions
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@ -164,7 +164,6 @@ fn run_instruction<'input>(
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| ast::Instruction::Or { .. }
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| ast::Instruction::Or { .. }
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| ast::Instruction::Popc { .. }
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| ast::Instruction::Popc { .. }
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| ast::Instruction::Prmt { .. }
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| ast::Instruction::Prmt { .. }
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| ast::Instruction::PrmtSlow { .. }
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| ast::Instruction::Rcp { .. }
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| ast::Instruction::Rcp { .. }
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| ast::Instruction::Rem { .. }
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| ast::Instruction::Rem { .. }
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| ast::Instruction::Ret { .. }
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| ast::Instruction::Ret { .. }
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@ -1818,7 +1818,6 @@ fn get_modes<T: ast::Operand>(inst: &ast::Instruction<T>) -> InstructionModes {
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| ast::Instruction::Mov { .. }
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| ast::Instruction::Mov { .. }
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| ast::Instruction::Ld { .. }
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| ast::Instruction::Ld { .. }
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| ast::Instruction::St { .. }
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| ast::Instruction::St { .. }
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| ast::Instruction::PrmtSlow { .. }
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| ast::Instruction::Prmt { .. }
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| ast::Instruction::Prmt { .. }
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| ast::Instruction::Activemask { .. }
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| ast::Instruction::Activemask { .. }
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| ast::Instruction::Membar { .. }
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| ast::Instruction::Membar { .. }
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@ -511,7 +511,6 @@ impl<'a> MethodEmitContext<'a> {
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ast::Instruction::Xor { data, arguments } => self.emit_xor(data, arguments),
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ast::Instruction::Xor { data, arguments } => self.emit_xor(data, arguments),
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ast::Instruction::Rem { data, arguments } => self.emit_rem(data, arguments),
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ast::Instruction::Rem { data, arguments } => self.emit_rem(data, arguments),
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ast::Instruction::BarWarp { .. } => self.emit_bar_warp(),
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ast::Instruction::BarWarp { .. } => self.emit_bar_warp(),
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ast::Instruction::Prmt { data, arguments } => self.emit_prmt(data, arguments),
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ast::Instruction::Membar { data } => self.emit_membar(data),
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ast::Instruction::Membar { data } => self.emit_membar(data),
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ast::Instruction::Trap {} => self.emit_trap(),
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ast::Instruction::Trap {} => self.emit_trap(),
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ast::Instruction::Tanh { data, arguments } => self.emit_tanh(data, arguments),
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ast::Instruction::Tanh { data, arguments } => self.emit_tanh(data, arguments),
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@ -532,7 +531,7 @@ impl<'a> MethodEmitContext<'a> {
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| ast::Instruction::ReduxSync { .. }
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| ast::Instruction::ReduxSync { .. }
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| ast::Instruction::LdMatrix { .. }
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| ast::Instruction::LdMatrix { .. }
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| ast::Instruction::Mma { .. }
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| ast::Instruction::Mma { .. }
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| ast::Instruction::PrmtSlow { .. } => return Err(error_unreachable()),
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| ast::Instruction::Prmt { .. } => return Err(error_unreachable()),
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}
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}
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}
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}
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@ -2446,48 +2445,6 @@ impl<'a> MethodEmitContext<'a> {
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Ok(())
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Ok(())
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}
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}
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fn emit_prmt(
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&mut self,
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control: u16,
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arguments: ptx_parser::PrmtArgs<SpirvWord>,
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) -> Result<(), TranslateError> {
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let components = [
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(control >> 0) & 0b1111,
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(control >> 4) & 0b1111,
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(control >> 8) & 0b1111,
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(control >> 12) & 0b1111,
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];
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if components.iter().any(|&c| c > 7) {
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return Err(error_todo());
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}
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let u32_type = get_scalar_type(self.context, ast::ScalarType::U32);
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let v4u8_type = get_type(self.context, &ast::Type::Vector(4, ast::ScalarType::U8))?;
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let mut components = [
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unsafe { LLVMConstInt(u32_type, components[0] as _, 0) },
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unsafe { LLVMConstInt(u32_type, components[1] as _, 0) },
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unsafe { LLVMConstInt(u32_type, components[2] as _, 0) },
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unsafe { LLVMConstInt(u32_type, components[3] as _, 0) },
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];
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let components_indices =
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unsafe { LLVMConstVector(components.as_mut_ptr(), components.len() as u32) };
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let src1 = self.resolver.value(arguments.src1)?;
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let src1_vector =
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unsafe { LLVMBuildBitCast(self.builder, src1, v4u8_type, LLVM_UNNAMED.as_ptr()) };
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let src2 = self.resolver.value(arguments.src2)?;
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let src2_vector =
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unsafe { LLVMBuildBitCast(self.builder, src2, v4u8_type, LLVM_UNNAMED.as_ptr()) };
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self.resolver.with_result(arguments.dst, |dst| unsafe {
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LLVMBuildShuffleVector(
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self.builder,
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src1_vector,
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src2_vector,
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components_indices,
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dst,
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)
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});
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Ok(())
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}
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fn emit_abs(
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fn emit_abs(
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&mut self,
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&mut self,
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data: ast::TypeFtz,
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data: ast::TypeFtz,
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@ -519,7 +519,7 @@ fn run_instruction<'input>(
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i,
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i,
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)?
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)?
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}
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}
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i @ ptx_parser::Instruction::PrmtSlow { .. } => {
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i @ ptx_parser::Instruction::Prmt { .. } => {
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to_call(resolver, fn_declarations, "prmt_b32".into(), i)?
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to_call(resolver, fn_declarations, "prmt_b32".into(), i)?
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}
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}
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i => i,
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i => i,
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@ -1,38 +1,39 @@
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define amdgpu_kernel void @prmt(ptr addrspace(4) byref(i64) %"36", ptr addrspace(4) byref(i64) %"37") #0 {
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declare hidden i32 @__zluda_ptx_impl_prmt_b32(i32, i32, i32) #0
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%"38" = alloca i64, align 8, addrspace(5)
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define amdgpu_kernel void @prmt(ptr addrspace(4) byref(i64) %"37", ptr addrspace(4) byref(i64) %"38") #1 {
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%"39" = alloca i64, align 8, addrspace(5)
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%"39" = alloca i64, align 8, addrspace(5)
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%"40" = alloca i32, align 4, addrspace(5)
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%"40" = alloca i64, align 8, addrspace(5)
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%"41" = alloca i32, align 4, addrspace(5)
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%"41" = alloca i32, align 4, addrspace(5)
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%"42" = alloca i32, align 4, addrspace(5)
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br label %1
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br label %1
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1: ; preds = %0
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1: ; preds = %0
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br label %"35"
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br label %"36"
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"35": ; preds = %1
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"36": ; preds = %1
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%"42" = load i64, ptr addrspace(4) %"36", align 8
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store i64 %"42", ptr addrspace(5) %"38", align 8
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%"43" = load i64, ptr addrspace(4) %"37", align 8
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%"43" = load i64, ptr addrspace(4) %"37", align 8
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store i64 %"43", ptr addrspace(5) %"39", align 8
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store i64 %"43", ptr addrspace(5) %"39", align 8
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%"45" = load i64, ptr addrspace(5) %"38", align 8
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%"44" = load i64, ptr addrspace(4) %"38", align 8
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%"53" = inttoptr i64 %"45" to ptr
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store i64 %"44", ptr addrspace(5) %"40", align 8
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%"44" = load i32, ptr %"53", align 4
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%"46" = load i64, ptr addrspace(5) %"39", align 8
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store i32 %"44", ptr addrspace(5) %"40", align 4
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%"46" = load i64, ptr addrspace(5) %"38", align 8
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%"54" = inttoptr i64 %"46" to ptr
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%"54" = inttoptr i64 %"46" to ptr
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%"34" = getelementptr inbounds i8, ptr %"54", i64 4
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%"45" = load i32, ptr %"54", align 4
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%"47" = load i32, ptr %"34", align 4
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store i32 %"45", ptr addrspace(5) %"41", align 4
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store i32 %"47", ptr addrspace(5) %"41", align 4
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%"47" = load i64, ptr addrspace(5) %"39", align 8
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%"49" = load i32, ptr addrspace(5) %"40", align 4
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%"55" = inttoptr i64 %"47" to ptr
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%"34" = getelementptr inbounds i8, ptr %"55", i64 4
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%"48" = load i32, ptr %"34", align 4
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store i32 %"48", ptr addrspace(5) %"42", align 4
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%"50" = load i32, ptr addrspace(5) %"41", align 4
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%"50" = load i32, ptr addrspace(5) %"41", align 4
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%2 = bitcast i32 %"49" to <4 x i8>
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%"51" = load i32, ptr addrspace(5) %"42", align 4
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%3 = bitcast i32 %"50" to <4 x i8>
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%"56" = call i32 @__zluda_ptx_impl_prmt_b32(i32 %"50", i32 %"51", i32 30212)
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%"55" = shufflevector <4 x i8> %2, <4 x i8> %3, <4 x i32> <i32 4, i32 0, i32 6, i32 7>
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store i32 %"56", ptr addrspace(5) %"42", align 4
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store <4 x i8> %"55", ptr addrspace(5) %"41", align 4
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%"52" = load i64, ptr addrspace(5) %"40", align 8
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%"51" = load i64, ptr addrspace(5) %"39", align 8
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%"53" = load i32, ptr addrspace(5) %"42", align 4
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%"52" = load i32, ptr addrspace(5) %"41", align 4
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%"59" = inttoptr i64 %"52" to ptr
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%"58" = inttoptr i64 %"51" to ptr
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store i32 %"53", ptr %"59", align 4
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store i32 %"52", ptr %"58", align 4
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ret void
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ret void
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}
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}
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attributes #0 = { "amdgpu-ieee"="false" "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="preserve-sign" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }
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attributes #0 = { "amdgpu-ieee"="false" "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="dynamic" "denormal-fp-math-f32"="dynamic" "no-trapping-math"="true" "uniform-work-group-size"="true" }
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attributes #1 = { "amdgpu-ieee"="false" "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="preserve-sign" "denormal-fp-math-f32"="preserve-sign" "no-trapping-math"="true" "uniform-work-group-size"="true" }
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@ -33,12 +33,12 @@ define amdgpu_kernel void @prmt_slow(ptr addrspace(4) byref(i64) %"39", ptr addr
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%"55" = load i32, ptr addrspace(5) %"43", align 4
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%"55" = load i32, ptr addrspace(5) %"43", align 4
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%"56" = load i32, ptr addrspace(5) %"44", align 4
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%"56" = load i32, ptr addrspace(5) %"44", align 4
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%"57" = load i32, ptr addrspace(5) %"45", align 4
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%"57" = load i32, ptr addrspace(5) %"45", align 4
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%"54" = call i32 @__zluda_ptx_impl_prmt_b32(i32 %"55", i32 %"56", i32 %"57")
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%"63" = call i32 @__zluda_ptx_impl_prmt_b32(i32 %"55", i32 %"56", i32 %"57")
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store i32 %"54", ptr addrspace(5) %"44", align 4
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store i32 %"63", ptr addrspace(5) %"44", align 4
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%"58" = load i64, ptr addrspace(5) %"42", align 8
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%"58" = load i64, ptr addrspace(5) %"42", align 8
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%"59" = load i32, ptr addrspace(5) %"44", align 4
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%"59" = load i32, ptr addrspace(5) %"44", align 4
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%"63" = inttoptr i64 %"58" to ptr
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%"67" = inttoptr i64 %"58" to ptr
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store i32 %"59", ptr %"63", align 4
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store i32 %"59", ptr %"67", align 4
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ret void
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ret void
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}
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}
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@ -432,15 +432,6 @@ ptx_parser_macros::generate_instruction_type!(
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},
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},
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Prmt {
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Prmt {
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type: Type::Scalar(ScalarType::B32),
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type: Type::Scalar(ScalarType::B32),
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data: u16,
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arguments<T>: {
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dst: T,
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src1: T,
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src2: T
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}
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},
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PrmtSlow {
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type: Type::Scalar(ScalarType::U32),
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arguments<T>: {
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arguments<T>: {
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dst: T,
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dst: T,
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src1: T,
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src1: T,
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@ -3659,20 +3659,12 @@ derive_parser!(
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// prmt.b32{.mode} d, a, b, c;
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// prmt.b32{.mode} d, a, b, c;
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// .mode = { .f4e, .b4e, .rc8, .ecl, .ecr, .rc16 };
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// .mode = { .f4e, .b4e, .rc8, .ecl, .ecr, .rc16 };
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prmt.b32 d, a, b, c => {
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prmt.b32 d, a, b, c => {
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match c {
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ast::Instruction::Prmt {
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ast::ParsedOperand::Imm(ImmediateValue::S64(control)) => ast::Instruction::Prmt {
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data: control as u16,
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arguments: PrmtArgs {
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arguments: PrmtArgs {
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dst: d, src1: a, src2: b
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}
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},
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_ => ast::Instruction::PrmtSlow {
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arguments: PrmtSlowArgs {
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dst: d, src1: a, src2: b, src3: c
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dst: d, src1: a, src2: b, src3: c
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}
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}
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}
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}
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}
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}
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}
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-activemask
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#parallel-synchronization-and-communication-instructions-activemask
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activemask.b32 d => {
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activemask.b32 d => {
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