mirror of
https://github.com/vosen/ZLUDA.git
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Refactor how instructions are parsed
This commit is contained in:
Andrzej Janik
parent
6f4530fe83
commit
12e0509b09
5 changed files with 264 additions and 64 deletions
105
ptx/src/ast.rs
105
ptx/src/ast.rs
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@ -105,7 +105,7 @@ impl Default for ScalarType {
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pub enum Statement<'a> {
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Label(&'a str),
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Variable(Variable<'a>),
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Instruction(Instruction),
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Instruction(Option<PredAt<'a>>, Instruction<'a>),
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}
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pub struct Variable<'a> {
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@ -124,16 +124,95 @@ pub enum StateSpace {
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Shared,
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}
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pub enum Instruction {
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Ld,
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Mov,
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Mul,
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Add,
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Setp,
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Not,
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Bra,
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Cvt,
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Shl,
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At,
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Ret,
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pub struct PredAt<'a> {
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pub not: bool,
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pub label: &'a str,
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}
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pub enum Instruction<'a> {
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Ld(LdData, Arg2<'a>),
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Mov(MovData, Arg2Mov<'a>),
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Mul(MulData, Arg3<'a>),
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Add(AddData, Arg3<'a>),
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Setp(SetpData, Arg4<'a>),
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SetpBool(SetpBoolData, Arg5<'a>),
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Not(NotData, Arg2<'a>),
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Bra(BraData, Arg1<'a>),
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Cvt(CvtData, Arg2<'a>),
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Shl(ShlData, Arg3<'a>),
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St(StData, Arg2<'a>),
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At(AtData, Arg1<'a>),
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Ret(RetData),
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}
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pub struct Arg1<'a> {
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pub dst: &'a str,
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}
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pub struct Arg2<'a> {
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pub dst: &'a str,
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pub src: Operand<'a>,
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}
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pub struct Arg2Mov<'a> {
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pub dst: &'a str,
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pub src: MovOperand<'a>,
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}
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pub struct Arg3<'a> {
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pub dst: &'a str,
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pub src1: Operand<'a>,
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pub src2: Operand<'a>,
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}
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pub struct Arg4<'a> {
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pub dst1: &'a str,
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pub dst2: Option<&'a str>,
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pub src1: Operand<'a>,
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pub src2: Operand<'a>,
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}
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pub struct Arg5<'a> {
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pub dst1: &'a str,
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pub dst2: Option<&'a str>,
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pub src1: Operand<'a>,
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pub src2: Operand<'a>,
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pub src3: Operand<'a>,
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}
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pub enum Operand<'a> {
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Reg(&'a str),
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RegOffset(&'a str, i32),
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Imm(i128),
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}
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pub enum MovOperand<'a> {
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Op(Operand<'a>),
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Vec(&'a str, &'a str),
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}
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pub struct LdData {}
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pub struct MovData {}
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pub struct MulData {}
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pub struct AddData {}
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pub struct SetpData {}
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pub struct SetpBoolData {}
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pub struct NotData {}
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pub struct BraData {}
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pub struct CvtData {}
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pub struct ShlData {}
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pub struct StData {}
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pub struct AtData {}
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pub struct RetData {}
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@ -139,7 +139,7 @@ Statement: Option<ast::Statement<'input>> = {
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<l:Label> => Some(ast::Statement::Label(l)),
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DebugDirective => None,
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<v:Variable> ";" => Some(ast::Statement::Variable(v)),
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<i:Instruction> ";" => Some(ast::Statement::Instruction(i))
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<p:PredAt?> <i:Instruction> ";" => Some(ast::Statement::Instruction(p, i))
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};
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DebugDirective: () = {
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@ -175,7 +175,7 @@ VariableName: (&'input str, Option<u32>) = {
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}
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};
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Instruction = {
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Instruction: ast::Instruction<'input> = {
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InstLd,
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InstMov,
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InstMul,
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@ -190,8 +190,10 @@ Instruction = {
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};
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld
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InstLd: ast::Instruction = {
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"ld" LdQualifier? LdStateSpace? LdCacheOperator? Vector? BaseType ID "," "[" ID "]" => ast::Instruction::Ld
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InstLd: ast::Instruction<'input> = {
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"ld" LdQualifier? LdStateSpace? LdCacheOperator? Vector? BaseType <dst:ID> "," "[" <src:Operand> "]" => {
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ast::Instruction::Ld(ast::LdData{}, ast::Arg2{dst:dst, src:src})
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}
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};
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LdQualifier: () = {
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@ -222,8 +224,10 @@ LdCacheOperator = {
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};
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-mov
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InstMov: ast::Instruction = {
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"mov" MovType ID "," Operand => ast::Instruction::Mov
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InstMov: ast::Instruction<'input> = {
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"mov" MovType <a:Arg2Mov> => {
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ast::Instruction::Mov(ast::MovData{}, a)
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}
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};
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MovType = {
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@ -237,12 +241,16 @@ MovType = {
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-mul
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#floating-point-instructions-mul
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#half-precision-floating-point-instructions-mul
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InstMul: ast::Instruction = {
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"mul" MulIntControl? IntType ID "," Operand "," Operand => ast::Instruction::Mul,
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"mul" RoundingMode? ".ftz"? ".sat"? ".f32" ID "," Operand "," Operand => ast::Instruction::Mul,
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"mul" RoundingMode? ".f64" ID "," Operand "," Operand => ast::Instruction::Mul,
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"mul" ".rn"? ".ftz"? ".sat"? ".f16" ID "," Operand "," Operand => ast::Instruction::Mul,
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"mul" ".rn"? ".ftz"? ".sat"? ".f16x2" ID "," Operand "," Operand => ast::Instruction::Mul,
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InstMul: ast::Instruction<'input> = {
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"mul" <d:InstMulMode> <a:Arg3> => ast::Instruction::Mul(d, a)
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};
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InstMulMode: ast::MulData = {
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MulIntControl? IntType => ast::MulData{},
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RoundingMode? ".ftz"? ".sat"? ".f32" => ast::MulData{},
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RoundingMode? ".f64" => ast::MulData{},
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".rn"? ".ftz"? ".sat"? ".f16" => ast::MulData{},
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".rn"? ".ftz"? ".sat"? ".f16x2" => ast::MulData{}
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};
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MulIntControl = {
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@ -262,19 +270,33 @@ IntType = {
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-add
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#floating-point-instructions-add
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#half-precision-floating-point-instructions-add
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InstAdd: ast::Instruction = {
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"add" IntType ID "," Operand "," Operand => ast::Instruction::Add,
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"add" ".sat" ".s32" ID "," Operand "," Operand => ast::Instruction::Add,
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"add" RoundingMode? ".ftz"? ".sat"? ".f32" ID "," Operand "," Operand => ast::Instruction::Add,
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"add" RoundingMode? ".f64" ID "," Operand "," Operand => ast::Instruction::Add,
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"add" ".rn"? ".ftz"? ".sat"? ".f16" ID "," Operand "," Operand => ast::Instruction::Add,
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"add" ".rn"? ".ftz"? ".sat"? ".f16x2" ID "," Operand "," Operand => ast::Instruction::Add,
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InstAdd: ast::Instruction<'input> = {
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"add" <d:InstAddMode> <a:Arg3> => ast::Instruction::Add(d, a)
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};
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InstAddMode: ast::AddData = {
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IntType => ast::AddData{},
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".sat" ".s32" => ast::AddData{},
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RoundingMode? ".ftz"? ".sat"? ".f32" => ast::AddData{},
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RoundingMode? ".f64" => ast::AddData{},
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".rn"? ".ftz"? ".sat"? ".f16" => ast::AddData{},
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".rn"? ".ftz"? ".sat"? ".f16x2" => ast::AddData{}
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};
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#comparison-and-selection-instructions-setp
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InstSetp: ast::Instruction = {
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"setp" SetpCmpOp ".ftz"? SetpType ID ("|" ID)? "," Operand "," Operand => ast::Instruction::Setp,
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"setp" SetpCmpOp SetpBoolOp ".ftz"? SetpType ID ("|" ID)? "," Operand "," Operand "," "!"? ID => ast::Instruction::Setp
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#half-precision-comparison-instructions-setp
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// TODO: support f16 setp
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InstSetp: ast::Instruction<'input> = {
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"setp" <d:SetpMode> <a:Arg4> => ast::Instruction::Setp(d, a),
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"setp" <d:SetpBoolMode> <a:Arg5> => ast::Instruction::SetpBool(d, a),
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};
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SetpMode: ast::SetpData = {
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SetpCmpOp ".ftz"? SetpType => ast::SetpData{}
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};
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SetpBoolMode: ast::SetpBoolData = {
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SetpCmpOp SetpBoolOp ".ftz"? SetpType => ast::SetpBoolData{}
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};
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SetpCmpOp = {
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@ -294,8 +316,8 @@ SetpType = {
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};
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#logic-and-shift-instructions-not
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InstNot: ast::Instruction = {
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"not" NotType ID "," Operand => ast::Instruction::Not
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InstNot: ast::Instruction<'input> = {
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"not" NotType <a:Arg2> => ast::Instruction::Not(ast::NotData{}, a)
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};
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NotType = {
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@ -303,18 +325,21 @@ NotType = {
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};
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#control-flow-instructions-at
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InstAt: ast::Instruction = {
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"@" "!"? ID => ast::Instruction::At
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PredAt: ast::PredAt<'input> = {
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"@" <label:ID> => ast::PredAt { not: false, label:label },
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"@" "!" <label:ID> => ast::PredAt { not: true, label:label }
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};
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#control-flow-instructions-bra
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InstBra: ast::Instruction = {
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InstAt? "bra" ".uni"? ID => ast::Instruction::Bra
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InstBra: ast::Instruction<'input> = {
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"bra" ".uni"? <a:Arg1> => ast::Instruction::Bra(ast::BraData{}, a)
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};
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt
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InstCvt: ast::Instruction = {
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"cvt" CvtRnd? ".ftz"? ".sat"? CvtType CvtType ID "," Operand => ast::Instruction::Cvt
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InstCvt: ast::Instruction<'input> = {
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"cvt" CvtRnd? ".ftz"? ".sat"? CvtType CvtType <a:Arg2> => {
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ast::Instruction::Cvt(ast::CvtData{}, a)
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}
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};
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CvtRnd = {
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@ -337,8 +362,8 @@ CvtType = {
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};
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#logic-and-shift-instructions-shl
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InstShl: ast::Instruction = {
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"shl" ShlType ID "," Operand "," Operand => ast::Instruction::Shl
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InstShl: ast::Instruction<'input> = {
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"shl" ShlType <a:Arg3> => ast::Instruction::Shl(ast::ShlData{}, a)
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};
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ShlType = {
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@ -346,8 +371,10 @@ ShlType = {
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};
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-st
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InstSt: ast::Instruction = {
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"st" LdQualifier? StStateSpace? StCacheOperator? Vector? BaseType "[" ID "]" "," Operand => ast::Instruction::Shl
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InstSt: ast::Instruction<'input> = {
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"st" LdQualifier? StStateSpace? StCacheOperator? Vector? BaseType "[" <dst:ID> "]" "," <src:Operand> => {
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ast::Instruction::St(ast::StData{}, ast::Arg2{dst:dst, src:src})
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}
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};
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StStateSpace = {
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@ -365,31 +392,66 @@ StCacheOperator = {
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};
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#control-flow-instructions-ret
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InstRet: ast::Instruction = {
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"ret" ".uni"? => ast::Instruction::Ret
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InstRet: ast::Instruction<'input> = {
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"ret" ".uni"? => ast::Instruction::Ret(ast::RetData{})
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};
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Operand: () = {
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ID,
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Num,
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OffsetOperand,
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ArrayOperand,
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VectorOperand,
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Operand: ast::Operand<'input> = {
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<r:ID> => ast::Operand::Reg(r),
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<r:ID> "+" <o:Num> => {
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let offset = o.parse::<i32>();
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let offset = offset.unwrap_with(errors);
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ast::Operand::RegOffset(r, offset)
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},
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<o:Num> => {
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let offset = o.parse::<i128>();
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let offset = offset.unwrap_with(errors);
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ast::Operand::Imm(offset)
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}
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};
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OffsetOperand = {
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ID "+" Num,
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MovOperand: ast::MovOperand<'input> = {
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<o:Operand> => ast::MovOperand::Op(o),
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<o:VectorOperand> => {
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let (pref, suf) = o;
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ast::MovOperand::Vec(pref, suf)
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}
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};
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ArrayOperand = {
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ID "[" Num "]",
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VectorOperand: (&'input str, &'input str) = {
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<pref:ID> "." <suf:ID> => (pref, suf),
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<pref:ID> <suf:DotID> => (pref, &suf[1..]),
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};
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VectorOperand: () = {
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ID "." ID,
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ID DotID,
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Arg1: ast::Arg1<'input> = {
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<dst:ID> => ast::Arg1{<>}
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};
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Arg2: ast::Arg2<'input> = {
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<dst:ID> "," <src:Operand> => ast::Arg2{<>}
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};
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Arg2Mov: ast::Arg2Mov<'input> = {
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<dst:ID> "," <src:MovOperand> => ast::Arg2Mov{<>}
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};
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Arg3: ast::Arg3<'input> = {
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<dst:ID> "," <src1:Operand> "," <src2:Operand> => ast::Arg3{<>}
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};
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Arg4: ast::Arg4<'input> = {
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<dst1:ID> <dst2:OptionalDst?> "," <src1:Operand> "," <src2:Operand> => ast::Arg4{<>}
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};
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// TODO: pass src3 negation somewhere
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Arg5: ast::Arg5<'input> = {
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<dst1:ID> <dst2:OptionalDst?> "," <src1:Operand> "," <src2:Operand> "," "!"? <src3:Operand> => ast::Arg5{<>}
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};
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OptionalDst: &'input str = {
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"|" <dst2:ID> => dst2
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}
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Vector = {
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".v2",
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".v4"
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|
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@ -12,7 +12,13 @@ fn empty() {
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}
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#[test]
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fn vector_add() {
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fn vectorAdd_kernel64_ptx() {
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let vector_add = include_str!("vectorAdd_kernel64.ptx");
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parse_and_assert(vector_add);
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}
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#[test]
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fn operands_ptx() {
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let vector_add = include_str!("operands.ptx");
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parse_and_assert(vector_add);
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}
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33
ptx/src/test/operands.ptx
Normal file
33
ptx/src/test/operands.ptx
Normal file
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@ -0,0 +1,33 @@
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.version 6.5
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.target sm_30
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.address_size 64
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.visible .entry foobar(
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.param .u32 foobar_param_0
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)
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{
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.reg .u32 %reg<10>;
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.reg .u64 %reg_64;
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.reg .pred p;
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.reg .pred q;
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// reg
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ld.param.u32 %reg0, [foobar_param_0];
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// reg with offset
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ld.param.u32 %reg1, [foobar_param_0+1];
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ld.param.u32 %reg2, [foobar_param_0+-1];
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// immediate - only in local
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ld.local.u32 %reg3, [1];
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// ids
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add.u32 %reg0, %reg1, %reg2;
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// immediate
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add.u32 %reg0, 1, %reg2;
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// reg with offset
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add.u32 %reg0, %reg1+1, %reg2+-1;
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// suprisingly, setp accepts all forms
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setp.eq.and.u32 p, %reg1+1, %reg2+-1, 2;
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// vector index - only supported by mov (maybe: ld, st, tex)
|
||||
mov.u32 %reg0, %ntid.x;
|
||||
}
|
||||
|
|
@ -128,10 +128,30 @@ fn emit_function<'a>(
|
|||
builder.begin_block(Some(id))?;
|
||||
}
|
||||
ast::Statement::Variable(var) => panic!(),
|
||||
ast::Statement::Instruction(i) => panic!(),
|
||||
ast::Statement::Instruction(_,_) => panic!(),
|
||||
}
|
||||
}
|
||||
builder.ret()?;
|
||||
builder.end_function()?;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
enum Statement {
|
||||
Label,
|
||||
Instruction(Instruction),
|
||||
Phi(Vec<spirv::Word>)
|
||||
}
|
||||
|
||||
enum Instruction {
|
||||
Ld,
|
||||
Mov,
|
||||
Mul,
|
||||
Add,
|
||||
Setp,
|
||||
Not,
|
||||
Bra,
|
||||
Cvt,
|
||||
Shl,
|
||||
At,
|
||||
Ret,
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue