diff --git a/ptx/src/ast.rs b/ptx/src/ast.rs
index d308479..f1323be 100644
--- a/ptx/src/ast.rs
+++ b/ptx/src/ast.rs
@@ -16,6 +16,8 @@ pub enum PtxError {
         source: ParseFloatError,
     },
     #[error("")]
+    Unsupported32Bit,
+    #[error("")]
     SyntaxError,
     #[error("")]
     NonF32Ftz,
diff --git a/ptx_parser/src/ast.rs b/ptx_parser/src/ast.rs
index 7755c7f..98583a8 100644
--- a/ptx_parser/src/ast.rs
+++ b/ptx_parser/src/ast.rs
@@ -192,6 +192,14 @@ gen::generate_instruction_type!(
         Ret {
             data: RetData
         },
+        Cvta {
+            data: CvtaDetails,
+            type: { Type::Scalar(ScalarType::B64) },
+            arguments<T>: {
+                dst: T,
+                src: T,
+            }
+        },
         Trap { }
     }
 );
@@ -824,9 +832,9 @@ impl<T: Operand> CallArgs<T> {
 }
 
 pub struct CvtDetails {
-    from: ScalarType,
-    to: ScalarType,
-    mode: CvtMode,
+    pub from: ScalarType,
+    pub to: ScalarType,
+    pub mode: CvtMode,
 }
 
 pub enum CvtMode {
@@ -977,3 +985,13 @@ pub enum RightShiftKind {
     Arithmetic,
     Logical,
 }
+
+pub struct CvtaDetails {
+    pub state_space: StateSpace,
+    pub direction: CvtaDirection,
+}
+
+pub enum CvtaDirection {
+    GenericToExplicit,
+    ExplicitToGeneric,
+}
diff --git a/ptx_parser/src/main.rs b/ptx_parser/src/main.rs
index 6055c1d..03360f3 100644
--- a/ptx_parser/src/main.rs
+++ b/ptx_parser/src/main.rs
@@ -814,6 +814,8 @@ pub enum PtxError {
     #[error("")]
     NonF32Ftz,
     #[error("")]
+    Unsupported32Bit,
+    #[error("")]
     WrongType,
     #[error("")]
     UnknownFunction,
@@ -1653,7 +1655,7 @@ derive_parser!(
                                   .s8,   .s16, .s32, .s64,
                                   .bf16, .f16, .f32, .f64 };
     // https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#logic-and-shift-instructions-shl
-    shl.type d, a, b => { 
+    shl.type d, a, b => {
         ast::Instruction::Shl { data: type_, arguments: ShlArgs { dst: d, src1: a, src2: b } }
     }
     .type: ScalarType = { .b16, .b32, .b64 };
@@ -1666,11 +1668,44 @@ derive_parser!(
             arguments: ShrArgs { dst: d, src1: a, src2: b }
         }
     }
-
     .type: ScalarType = { .b16, .b32, .b64,
                           .u16, .u32, .u64,
                           .s16, .s32, .s64 };
 
+    // https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvta
+    cvta.space.size     p, a => {
+        if size != ScalarType::U64 {
+            state.errors.push(PtxError::Unsupported32Bit);
+        }
+        let data = ast::CvtaDetails {
+            state_space: space,
+            direction: ast::CvtaDirection::ExplicitToGeneric
+        };
+        let arguments = ast::CvtaArgs {
+            dst: p, src: a
+        };
+        ast::Instruction::Cvta {
+            data, arguments
+        }
+    }
+    cvta.to.space.size  p, a => {
+        if size != ScalarType::U64 {
+            state.errors.push(PtxError::Unsupported32Bit);
+        }
+        let data = ast::CvtaDetails {
+            state_space: space,
+            direction: ast::CvtaDirection::GenericToExplicit
+        };
+        let arguments = ast::CvtaArgs {
+            dst: p, src: a
+        };
+        ast::Instruction::Cvta {
+            data, arguments
+        }
+    }
+    .space: StateSpace = { .const, .global, .local, .shared{::cta, ::cluster}, .param{::entry} };
+    .size: ScalarType  = { .u32, .u64 };
+
     // https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#control-flow-instructions-ret
     ret{.uni} => {
         Instruction::Ret { data: RetData { uniform: uni } }