mirror of
https://github.com/vosen/ZLUDA.git
synced 2025-10-04 07:09:55 +00:00
Progress compilation despite parsing errors (#495)
Previously if we ran into a broken instruction we'd fail whole compilation. This PR changes it so (only in Release mode) we try and progress at all cost. Meaning that if we had trouble parsing an instruction we just remove function form the output and continue. For some workloads we can still compile a semi-broken, but meaningful subset of a module
This commit is contained in:
Andrzej Janik
GitHub
parent
00ca92167d
commit
869d291099
23 changed files with 1043 additions and 391 deletions
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@ -10,12 +10,11 @@ name = "zoc"
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path = "src/main.rs"
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[dependencies]
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amd_comgr-sys = { path = "../ext/amd_comgr-sys" }
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bpaf = { version = "0.9.19", features = ["derive"] }
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comgr = { path = "../comgr" }
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hip_runtime-sys = { path = "../ext/hip_runtime-sys" }
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ptx = { path = "../ptx" }
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ptx_parser = { path = "../ptx_parser" }
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libloading = "0.8"
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thiserror = "2.0.12"
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[package.metadata.zluda]
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@ -1,15 +1,15 @@
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use ptx::TranslateError;
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use ptx_parser::PtxError;
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use std::ffi::FromBytesUntilNulError;
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use std::io;
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use std::str::Utf8Error;
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use hip_runtime_sys::hipErrorCode_t;
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use ptx::TranslateError;
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use ptx_parser::PtxError;
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#[derive(Debug, thiserror::Error)]
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pub enum CompilerError {
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#[error("HIP error code: {0:?}")]
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HipError(hipErrorCode_t),
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HipError(u32),
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#[error(transparent)]
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Libloading(#[from] libloading::Error),
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#[error(transparent)]
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ComgrError(#[from] comgr::Error),
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#[error(transparent)]
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@ -26,12 +26,6 @@ pub enum CompilerError {
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},
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}
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impl From<hipErrorCode_t> for CompilerError {
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fn from(error_code: hipErrorCode_t) -> Self {
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CompilerError::HipError(error_code)
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}
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}
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impl From<Vec<PtxError<'_>>> for CompilerError {
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fn from(causes: Vec<PtxError>) -> Self {
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let errors: Vec<String> = causes
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@ -1,3 +1,5 @@
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use bpaf::Bpaf;
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use error::CompilerError;
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use std::ffi::CStr;
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use std::fs::{self, File};
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use std::io::{self, Write};
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@ -6,11 +8,7 @@ use std::process::ExitCode;
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use std::str;
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use std::{env, mem};
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use bpaf::Bpaf;
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mod error;
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use error::CompilerError;
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use hip_runtime_sys::{hipDeviceProp_tR0600, hipGetDevicePropertiesR0600, hipInit};
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const DEFAULT_ARCH: &'static str = "gfx1100";
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@ -60,12 +58,17 @@ fn main_core() -> Result<(), CompilerError> {
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let arch: String = match opts.arch {
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Some(s) => s,
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None => {
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unsafe { hipInit(0) }?;
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let mut dev_props: hipDeviceProp_tR0600 = unsafe { mem::zeroed() };
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unsafe { hipGetDevicePropertiesR0600(&mut dev_props, 0) }?;
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(|| {
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let runtime = hip::Runtime::load()?;
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runtime.init()?;
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get_gpu_arch(&runtime)
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})()
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.unwrap_or_else(|_| DEFAULT_ARCH.to_owned())
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/*
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get_gpu_arch(&mut dev_props)
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.map(String::from)
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.unwrap_or(DEFAULT_ARCH.to_owned())
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*/
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}
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};
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@ -122,12 +125,13 @@ struct LLVMArtifacts {
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llvm_ir: Vec<u8>,
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}
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fn get_gpu_arch<'a>(dev_props: &'a mut hipDeviceProp_tR0600) -> Result<&'a str, CompilerError> {
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unsafe { hipGetDevicePropertiesR0600(dev_props, 0) }?;
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fn get_gpu_arch(runtime: &hip::Runtime) -> Result<String, CompilerError> {
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let mut dev_props = unsafe { mem::zeroed() };
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runtime.device_get_properties(&mut dev_props, 0)?;
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let gcn_arch_name = &dev_props.gcnArchName;
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let gcn_arch_name = unsafe { CStr::from_ptr(gcn_arch_name.as_ptr()) };
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let gcn_arch_name = gcn_arch_name.to_str();
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gcn_arch_name.map_err(CompilerError::from)
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let gcn_arch_name = gcn_arch_name.to_str()?;
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Ok(gcn_arch_name.to_string())
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}
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fn write_to_file(content: &[u8], path: &Path) -> io::Result<()> {
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@ -137,3 +141,316 @@ fn write_to_file(content: &[u8], path: &Path) -> io::Result<()> {
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println!("Wrote to {}", path.to_str().unwrap());
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Ok(())
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}
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mod hip {
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use crate::error::CompilerError;
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// We lazy load HIP runtime because we want to work on systems with no
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// HIP driver installed
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pub struct Runtime(libloading::Library);
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impl Runtime {
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fn hip_check(err: u32) -> Result<(), CompilerError> {
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match err {
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0 => Ok(()),
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err_code => Err(CompilerError::HipError(err_code)),
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}
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}
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pub fn load() -> Result<Self, CompilerError> {
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#[cfg(windows)]
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let lib_name = "amdhip64_6.dll\0";
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#[cfg(unix)]
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let lib_name = "libamdhip64.so.6\0";
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let library = unsafe { libloading::Library::new(lib_name)? };
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Ok(Self(library))
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}
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pub fn init(&self) -> Result<(), CompilerError> {
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unsafe {
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let hip_init: libloading::Symbol<unsafe extern "C" fn(u32) -> u32> =
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self.0.get(b"hipInit\0")?;
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Self::hip_check(hip_init(0))
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}
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}
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pub fn device_get_properties(
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&self,
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prop: &mut hipDeviceProp_tR0600,
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device: i32,
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) -> Result<(), CompilerError> {
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unsafe {
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let hip_get_device_properties: libloading::Symbol<
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unsafe extern "C" fn(*mut hipDeviceProp_tR0600, i32) -> u32,
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> = self.0.get(b"hipGetDevicePropertiesR0600\0")?;
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Self::hip_check(hip_get_device_properties(prop, device))
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}
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}
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}
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#[allow(non_snake_case, non_camel_case_types)]
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#[repr(C)]
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#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
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pub struct hipDeviceProp_tR0600 {
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///< Device name.
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pub name: [::core::ffi::c_char; 256usize],
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///< UUID of a device
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pub uuid: hipUUID,
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///< 8-byte unique identifier. Only valid on windows
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pub luid: [::core::ffi::c_char; 8usize],
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///< LUID node mask
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pub luidDeviceNodeMask: ::core::ffi::c_uint,
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///< Size of global memory region (in bytes).
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pub totalGlobalMem: usize,
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///< Size of shared memory per block (in bytes).
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pub sharedMemPerBlock: usize,
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///< Registers per block.
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pub regsPerBlock: ::core::ffi::c_int,
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///< Warp size.
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pub warpSize: ::core::ffi::c_int,
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/**< Maximum pitch in bytes allowed by memory copies
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< pitched memory*/
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pub memPitch: usize,
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///< Max work items per work group or workgroup max size.
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pub maxThreadsPerBlock: ::core::ffi::c_int,
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///< Max number of threads in each dimension (XYZ) of a block.
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pub maxThreadsDim: [::core::ffi::c_int; 3usize],
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///< Max grid dimensions (XYZ).
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pub maxGridSize: [::core::ffi::c_int; 3usize],
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///< Max clock frequency of the multiProcessors in khz.
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pub clockRate: ::core::ffi::c_int,
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/**< Size of shared constant memory region on the device
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< (in bytes).*/
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pub totalConstMem: usize,
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/**< Major compute capability. On HCC, this is an approximation and features may
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< differ from CUDA CC. See the arch feature flags for portable ways to query
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< feature caps.*/
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pub major: ::core::ffi::c_int,
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/**< Minor compute capability. On HCC, this is an approximation and features may
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< differ from CUDA CC. See the arch feature flags for portable ways to query
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< feature caps.*/
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pub minor: ::core::ffi::c_int,
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///< Alignment requirement for textures
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pub textureAlignment: usize,
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///< Pitch alignment requirement for texture references bound to
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pub texturePitchAlignment: usize,
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///< Deprecated. Use asyncEngineCount instead
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pub deviceOverlap: ::core::ffi::c_int,
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///< Number of multi-processors (compute units).
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pub multiProcessorCount: ::core::ffi::c_int,
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///< Run time limit for kernels executed on the device
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pub kernelExecTimeoutEnabled: ::core::ffi::c_int,
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///< APU vs dGPU
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pub integrated: ::core::ffi::c_int,
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///< Check whether HIP can map host memory
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pub canMapHostMemory: ::core::ffi::c_int,
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///< Compute mode.
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pub computeMode: ::core::ffi::c_int,
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///< Maximum number of elements in 1D images
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pub maxTexture1D: ::core::ffi::c_int,
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///< Maximum 1D mipmap texture size
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pub maxTexture1DMipmap: ::core::ffi::c_int,
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///< Maximum size for 1D textures bound to linear memory
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pub maxTexture1DLinear: ::core::ffi::c_int,
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///< Maximum dimensions (width, height) of 2D images, in image elements
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pub maxTexture2D: [::core::ffi::c_int; 2usize],
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///< Maximum number of elements in 2D array mipmap of images
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pub maxTexture2DMipmap: [::core::ffi::c_int; 2usize],
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///< Maximum 2D tex dimensions if tex are bound to pitched memory
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pub maxTexture2DLinear: [::core::ffi::c_int; 3usize],
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///< Maximum 2D tex dimensions if gather has to be performed
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pub maxTexture2DGather: [::core::ffi::c_int; 2usize],
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/**< Maximum dimensions (width, height, depth) of 3D images, in image
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< elements*/
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pub maxTexture3D: [::core::ffi::c_int; 3usize],
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///< Maximum alternate 3D texture dims
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pub maxTexture3DAlt: [::core::ffi::c_int; 3usize],
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///< Maximum cubemap texture dims
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pub maxTextureCubemap: ::core::ffi::c_int,
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///< Maximum number of elements in 1D array images
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pub maxTexture1DLayered: [::core::ffi::c_int; 2usize],
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///< Maximum number of elements in 2D array images
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pub maxTexture2DLayered: [::core::ffi::c_int; 3usize],
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///< Maximum cubemaps layered texture dims
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pub maxTextureCubemapLayered: [::core::ffi::c_int; 2usize],
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///< Maximum 1D surface size
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pub maxSurface1D: ::core::ffi::c_int,
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///< Maximum 2D surface size
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pub maxSurface2D: [::core::ffi::c_int; 2usize],
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///< Maximum 3D surface size
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pub maxSurface3D: [::core::ffi::c_int; 3usize],
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///< Maximum 1D layered surface size
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pub maxSurface1DLayered: [::core::ffi::c_int; 2usize],
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///< Maximum 2D layared surface size
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pub maxSurface2DLayered: [::core::ffi::c_int; 3usize],
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///< Maximum cubemap surface size
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pub maxSurfaceCubemap: ::core::ffi::c_int,
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///< Maximum cubemap layered surface size
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pub maxSurfaceCubemapLayered: [::core::ffi::c_int; 2usize],
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///< Alignment requirement for surface
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pub surfaceAlignment: usize,
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///< Device can possibly execute multiple kernels concurrently.
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pub concurrentKernels: ::core::ffi::c_int,
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///< Device has ECC support enabled
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pub ECCEnabled: ::core::ffi::c_int,
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///< PCI Bus ID.
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pub pciBusID: ::core::ffi::c_int,
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///< PCI Device ID.
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pub pciDeviceID: ::core::ffi::c_int,
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///< PCI Domain ID
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pub pciDomainID: ::core::ffi::c_int,
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///< 1:If device is Tesla device using TCC driver, else 0
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pub tccDriver: ::core::ffi::c_int,
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///< Number of async engines
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pub asyncEngineCount: ::core::ffi::c_int,
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///< Does device and host share unified address space
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pub unifiedAddressing: ::core::ffi::c_int,
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///< Max global memory clock frequency in khz.
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pub memoryClockRate: ::core::ffi::c_int,
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///< Global memory bus width in bits.
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pub memoryBusWidth: ::core::ffi::c_int,
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///< L2 cache size.
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pub l2CacheSize: ::core::ffi::c_int,
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///< Device's max L2 persisting lines in bytes
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pub persistingL2CacheMaxSize: ::core::ffi::c_int,
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///< Maximum resident threads per multi-processor.
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pub maxThreadsPerMultiProcessor: ::core::ffi::c_int,
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///< Device supports stream priority
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pub streamPrioritiesSupported: ::core::ffi::c_int,
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///< Indicates globals are cached in L1
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pub globalL1CacheSupported: ::core::ffi::c_int,
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///< Locals are cahced in L1
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pub localL1CacheSupported: ::core::ffi::c_int,
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///< Amount of shared memory available per multiprocessor.
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pub sharedMemPerMultiprocessor: usize,
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///< registers available per multiprocessor
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pub regsPerMultiprocessor: ::core::ffi::c_int,
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///< Device supports allocating managed memory on this system
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pub managedMemory: ::core::ffi::c_int,
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///< 1 if device is on a multi-GPU board, 0 if not.
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pub isMultiGpuBoard: ::core::ffi::c_int,
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///< Unique identifier for a group of devices on same multiboard GPU
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pub multiGpuBoardGroupID: ::core::ffi::c_int,
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///< Link between host and device supports native atomics
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pub hostNativeAtomicSupported: ::core::ffi::c_int,
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///< Deprecated. CUDA only.
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pub singleToDoublePrecisionPerfRatio: ::core::ffi::c_int,
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/**< Device supports coherently accessing pageable memory
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< without calling hipHostRegister on it*/
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pub pageableMemoryAccess: ::core::ffi::c_int,
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/**< Device can coherently access managed memory concurrently with
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< the CPU*/
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pub concurrentManagedAccess: ::core::ffi::c_int,
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///< Is compute preemption supported on the device
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pub computePreemptionSupported: ::core::ffi::c_int,
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/**< Device can access host registered memory with same
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< address as the host*/
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pub canUseHostPointerForRegisteredMem: ::core::ffi::c_int,
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///< HIP device supports cooperative launch
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pub cooperativeLaunch: ::core::ffi::c_int,
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/**< HIP device supports cooperative launch on multiple
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< devices*/
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pub cooperativeMultiDeviceLaunch: ::core::ffi::c_int,
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///< Per device m ax shared mem per block usable by special opt in
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pub sharedMemPerBlockOptin: usize,
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/**< Device accesses pageable memory via the host's
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< page tables*/
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pub pageableMemoryAccessUsesHostPageTables: ::core::ffi::c_int,
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/**< Host can directly access managed memory on the device
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< without migration*/
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pub directManagedMemAccessFromHost: ::core::ffi::c_int,
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///< Max number of blocks on CU
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pub maxBlocksPerMultiProcessor: ::core::ffi::c_int,
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///< Max value of access policy window
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pub accessPolicyMaxWindowSize: ::core::ffi::c_int,
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///< Shared memory reserved by driver per block
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pub reservedSharedMemPerBlock: usize,
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///< Device supports hipHostRegister
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pub hostRegisterSupported: ::core::ffi::c_int,
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///< Indicates if device supports sparse hip arrays
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pub sparseHipArraySupported: ::core::ffi::c_int,
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/**< Device supports using the hipHostRegisterReadOnly flag
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< with hipHostRegistger*/
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pub hostRegisterReadOnlySupported: ::core::ffi::c_int,
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///< Indicates external timeline semaphore support
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pub timelineSemaphoreInteropSupported: ::core::ffi::c_int,
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///< Indicates if device supports hipMallocAsync and hipMemPool APIs
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pub memoryPoolsSupported: ::core::ffi::c_int,
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///< Indicates device support of RDMA APIs
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pub gpuDirectRDMASupported: ::core::ffi::c_int,
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/**< Bitmask to be interpreted according to
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< hipFlushGPUDirectRDMAWritesOptions*/
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pub gpuDirectRDMAFlushWritesOptions: ::core::ffi::c_uint,
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///< value of hipGPUDirectRDMAWritesOrdering
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pub gpuDirectRDMAWritesOrdering: ::core::ffi::c_int,
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///< Bitmask of handle types support with mempool based IPC
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pub memoryPoolSupportedHandleTypes: ::core::ffi::c_uint,
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/**< Device supports deferred mapping HIP arrays and HIP
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< mipmapped arrays*/
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pub deferredMappingHipArraySupported: ::core::ffi::c_int,
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///< Device supports IPC events
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pub ipcEventSupported: ::core::ffi::c_int,
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///< Device supports cluster launch
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pub clusterLaunch: ::core::ffi::c_int,
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///< Indicates device supports unified function pointers
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pub unifiedFunctionPointers: ::core::ffi::c_int,
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///< CUDA Reserved.
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pub reserved: [::core::ffi::c_int; 63usize],
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///< Reserved for adding new entries for HIP/CUDA.
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pub hipReserved: [::core::ffi::c_int; 32usize],
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///< AMD GCN Arch Name. HIP Only.
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pub gcnArchName: [::core::ffi::c_char; 256usize],
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///< Maximum Shared Memory Per CU. HIP Only.
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pub maxSharedMemoryPerMultiProcessor: usize,
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/**< Frequency in khz of the timer used by the device-side "clock*"
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< instructions. New for HIP.*/
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pub clockInstructionRate: ::core::ffi::c_int,
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///< Architectural feature flags. New for HIP.
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pub arch: hipDeviceArch_t,
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///< Addres of HDP_MEM_COHERENCY_FLUSH_CNTL register
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pub hdpMemFlushCntl: *mut ::core::ffi::c_uint,
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///< Addres of HDP_REG_COHERENCY_FLUSH_CNTL register
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pub hdpRegFlushCntl: *mut ::core::ffi::c_uint,
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/**< HIP device supports cooperative launch on
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< multiple*/
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pub cooperativeMultiDeviceUnmatchedFunc: ::core::ffi::c_int,
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/**< HIP device supports cooperative launch on
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< multiple*/
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pub cooperativeMultiDeviceUnmatchedGridDim: ::core::ffi::c_int,
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/**< HIP device supports cooperative launch on
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< multiple*/
|
||||
pub cooperativeMultiDeviceUnmatchedBlockDim: ::core::ffi::c_int,
|
||||
/**< HIP device supports cooperative launch on
|
||||
< multiple*/
|
||||
pub cooperativeMultiDeviceUnmatchedSharedMem: ::core::ffi::c_int,
|
||||
///< 1: if it is a large PCI bar device, else 0
|
||||
pub isLargeBar: ::core::ffi::c_int,
|
||||
///< Revision of the GPU in this device
|
||||
pub asicRevision: ::core::ffi::c_int,
|
||||
}
|
||||
|
||||
#[allow(non_snake_case, non_camel_case_types)]
|
||||
#[repr(C)]
|
||||
#[repr(align(4))]
|
||||
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
|
||||
pub struct hipDeviceArch_t {
|
||||
pub _bitfield_align_1: [u8; 0],
|
||||
pub _bitfield_1: __BindgenBitfieldUnit<[u8; 3usize]>,
|
||||
pub __bindgen_padding_0: u8,
|
||||
}
|
||||
|
||||
#[repr(C)]
|
||||
#[derive(Copy, Clone, Debug, Default, Eq, Hash, Ord, PartialEq, PartialOrd)]
|
||||
pub struct __BindgenBitfieldUnit<Storage> {
|
||||
storage: Storage,
|
||||
}
|
||||
|
||||
#[allow(non_camel_case_types)]
|
||||
#[repr(C)]
|
||||
#[derive(Debug, Copy, Clone, Hash, PartialEq, Eq)]
|
||||
pub struct hipUUID_t {
|
||||
pub bytes: [::core::ffi::c_char; 16usize],
|
||||
}
|
||||
#[allow(non_camel_case_types)]
|
||||
pub type hipUUID = hipUUID_t;
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue