mirror of
https://github.com/vosen/ZLUDA.git
synced 2025-04-20 00:14:45 +00:00
Implement device host functions
This commit is contained in:
Andrzej Janik
parent
6c2a8576c2
commit
94e8e13425
3 changed files with 335 additions and 313 deletions
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@ -1,29 +1,25 @@
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use super::{transmute_lifetime, transmute_lifetime_mut, CUresult};
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use crate::{
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cuda::{self, CUdevice, CUdevprop},
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hip_call,
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};
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use cuda::{CUdevice_attribute, CUuuid_st};
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use hip_runtime_sys::{
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hipDeviceAttribute_t, hipDeviceGetAttribute, hipError_t, hipGetDeviceProperties,
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};
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use ocl_core::{ClDeviceIdPtr, ContextProperties, DeviceType};
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use paste::paste;
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use std::{
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cmp,
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collections::HashSet,
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ffi::c_void,
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mem,
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os::raw::{c_char, c_int, c_uint},
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ptr,
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sync::atomic::{AtomicU32, Ordering},
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};
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use cuda_types::*;
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use hip_runtime_sys::*;
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use std::{mem, ptr};
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const PROJECT_URL_SUFFIX_SHORT: &'static str = " [ZLUDA]";
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const PROJECT_URL_SUFFIX_LONG: &'static str = " [github.com/vosen/ZLUDA]";
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const PROJECT_SUFFIX: &[u8] = b" [ZLUDA]\0";
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pub const COMPUTE_CAPABILITY_MAJOR: i32 = 8;
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pub const COMPUTE_CAPABILITY_MINOR: i32 = 8;
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pub(crate) fn compute_capability(major: &mut i32, minor: &mut i32, _dev: hipDevice_t) -> CUresult {
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*major = COMPUTE_CAPABILITY_MAJOR;
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*minor = COMPUTE_CAPABILITY_MINOR;
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Ok(())
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}
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pub(crate) fn get(device: *mut hipDevice_t, ordinal: i32) -> hipError_t {
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unsafe { hipDeviceGet(device, ordinal) }
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}
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#[allow(warnings)]
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trait hipDeviceAttribute_t_ext {
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trait DeviceAttributeNames {
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const hipDeviceAttributeGpuOverlap: hipDeviceAttribute_t =
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hipDeviceAttribute_t::hipDeviceAttributeDeviceOverlap;
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const hipDeviceAttributeMaximumTexture1DWidth: hipDeviceAttribute_t =
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hipDeviceAttribute_t::hipDeviceAttributeMaxTexture1DWidth;
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const hipDeviceAttributeMaximumTexture2DWidth: hipDeviceAttribute_t =
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@ -42,307 +38,268 @@ trait hipDeviceAttribute_t_ext {
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hipDeviceAttribute_t::hipDeviceAttributeMaxThreadsPerMultiProcessor;
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const hipDeviceAttributeAsyncEngineCount: hipDeviceAttribute_t =
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hipDeviceAttribute_t::hipDeviceAttributeConcurrentKernels;
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const hipDeviceAttributePciDomainId: hipDeviceAttribute_t =
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hipDeviceAttribute_t::hipDeviceAttributePciDomainID;
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const hipDeviceAttributeMultiGpuBoard: hipDeviceAttribute_t =
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hipDeviceAttribute_t::hipDeviceAttributeIsMultiGpuBoard;
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const hipDeviceAttributeMultiGpuBoardGroupId: hipDeviceAttribute_t =
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hipDeviceAttribute_t::hipDeviceAttributeMultiGpuBoardGroupID;
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const hipDeviceAttributeMaxSharedMemoryPerBlockOptin: hipDeviceAttribute_t =
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hipDeviceAttribute_t::hipDeviceAttributeSharedMemPerBlockOptin;
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}
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impl hipDeviceAttribute_t_ext for hipDeviceAttribute_t {}
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impl DeviceAttributeNames for hipDeviceAttribute_t {}
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macro_rules! remap_attribute {
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($attrib:expr => $([ $($word:expr)* ]),*,) => {
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match $attrib {
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$(
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paste! { CUdevice_attribute:: [< CU_DEVICE_ATTRIBUTE $(_ $word:upper)* >] } => {
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paste! { hipDeviceAttribute_t:: [< hipDeviceAttribute $($word:camel)* >] }
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paste::paste! { CUdevice_attribute:: [< CU_DEVICE_ATTRIBUTE $(_ $word:upper)* >] } => {
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paste::paste! { hipDeviceAttribute_t:: [< hipDeviceAttribute $($word:camel)* >] }
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}
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)*
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_ => return hipError_t::hipErrorInvalidValue
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_ => return Err(hipErrorCode_t::hipErrorNotSupported)
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}
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}
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}
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pub fn get_attribute(pi: *mut i32, attrib: CUdevice_attribute, dev_idx: c_int) -> hipError_t {
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if pi == ptr::null_mut() {
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return hipError_t::hipErrorInvalidValue;
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}
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//let mut props = unsafe { mem::zeroed() };
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let hip_attrib = match attrib {
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_ASYNC_ENGINE_COUNT => {
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unsafe { *pi = 1 };
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return hipError_t::hipSuccess;
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pub(crate) fn get_attribute(
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pi: &mut i32,
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attrib: CUdevice_attribute,
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dev_idx: hipDevice_t,
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) -> hipError_t {
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match attrib {
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_WARP_SIZE => {
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*pi = 32;
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return Ok(());
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_GPU_OVERLAP
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_UNIFIED_ADDRESSING
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_STREAM_PRIORITIES_SUPPORTED
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_GLOBAL_L1_CACHE_SUPPORTED
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_LOCAL_L1_CACHE_SUPPORTED => {
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unsafe { *pi = 1 };
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return hipError_t::hipSuccess;
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_TCC_DRIVER
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_WIDTH
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_GATHER_HEIGHT
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_WIDTH_ALTERNATE
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_HEIGHT_ALTERNATE
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE3D_DEPTH_ALTERNATE
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_WIDTH
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_WIDTH
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURECUBEMAP_LAYERED_LAYERS
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_WIDTH
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_WIDTH
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACECUBEMAP_LAYERED_LAYERS
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_WIDTH
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_HEIGHT
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_LINEAR_PITCH
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAX_REGISTERS_PER_MULTIPROCESSOR
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MULTI_GPU_BOARD_GROUP_ID => {
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unsafe { *pi = 0 };
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return hipError_t::hipSuccess;
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_TCC_DRIVER => {
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*pi = 0;
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return Ok(());
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MAJOR => {
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unsafe { *pi = 8 };
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return hipError_t::hipSuccess;
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*pi = COMPUTE_CAPABILITY_MAJOR;
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return Ok(());
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_COMPUTE_CAPABILITY_MINOR => {
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unsafe { *pi = 0 };
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return hipError_t::hipSuccess;
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*pi = COMPUTE_CAPABILITY_MINOR;
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return Ok(());
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}
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// we assume that arrayed texts have the same limits
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_WIDTH => {
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hipDeviceAttribute_t::hipDeviceAttributeMaxTexture2DWidth
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_HEIGHT => {
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hipDeviceAttribute_t::hipDeviceAttributeMaxTexture2DHeight
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_WIDTH => {
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hipDeviceAttribute_t::hipDeviceAttributeMaxTexture1DWidth
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_WIDTH => {
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hipDeviceAttribute_t::hipDeviceAttributeMaxTexture1DWidth
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_WIDTH => {
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hipDeviceAttribute_t::hipDeviceAttributeMaxTexture2DWidth
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_HEIGHT => {
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hipDeviceAttribute_t::hipDeviceAttributeMaxTexture2DHeight
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}
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// we treat surface the same as texture
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_SURFACE_ALIGNMENT => {
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hipDeviceAttribute_t::hipDeviceAttributeTextureAlignment
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_WIDTH => {
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hipDeviceAttribute_t::hipDeviceAttributeMaxTexture1DWidth
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_WIDTH => {
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hipDeviceAttribute_t::hipDeviceAttributeMaxTexture2DWidth
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_HEIGHT => {
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hipDeviceAttribute_t::hipDeviceAttributeMaxTexture2DHeight
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_WIDTH => {
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hipDeviceAttribute_t::hipDeviceAttributeMaxTexture3DWidth
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_HEIGHT => {
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hipDeviceAttribute_t::hipDeviceAttributeMaxTexture3DHeight
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE3D_DEPTH => {
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hipDeviceAttribute_t::hipDeviceAttributeMaxTexture3DDepth
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_WIDTH => {
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hipDeviceAttribute_t::hipDeviceAttributeMaxTexture2DWidth
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_MIPMAPPED_HEIGHT => {
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hipDeviceAttribute_t::hipDeviceAttributeMaxTexture2DHeight
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_MIPMAPPED_WIDTH => {
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hipDeviceAttribute_t::hipDeviceAttributeMaxTexture1DWidth
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}
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// Totally made up
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE2D_ARRAY_NUMSLICES
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LAYERED_LAYERS
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE1D_LAYERED_LAYERS
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| CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_SURFACE2D_LAYERED_LAYERS => {
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unsafe { *pi = u16::MAX as i32 };
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return hipError_t::hipSuccess;
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}
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// linear sizes
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_MAXIMUM_TEXTURE1D_LINEAR_WIDTH => {
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let mut prop = unsafe { mem::zeroed() };
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let err = unsafe { hipGetDeviceProperties(&mut prop, dev_idx) };
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if err != hipError_t::hipSuccess {
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return err;
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}
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unsafe { *pi = prop.maxTexture1DLinear };
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return hipError_t::hipSuccess;
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}
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CUdevice_attribute::CU_DEVICE_ATTRIBUTE_PCI_DOMAIN_ID => {
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let mut prop = unsafe { mem::zeroed() };
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let err = unsafe { hipGetDeviceProperties(&mut prop, dev_idx) };
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if err != hipError_t::hipSuccess {
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return err;
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}
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unsafe { *pi = prop.pciDomainID };
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return hipError_t::hipSuccess;
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}
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attrib => remap_attribute! {
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attrib =>
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[MAX THREADS PER BLOCK],
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[MAX BLOCK DIM X],
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[MAX BLOCK DIM Y],
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[MAX BLOCK DIM Z],
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[MAX GRID DIM X],
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[MAX GRID DIM Y],
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[MAX GRID DIM Z],
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[MAX SHARED MEMORY PER BLOCK],
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[TOTAL CONSTANT MEMORY],
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[WARP SIZE],
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[MAX PITCH],
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[MAX REGISTERS PER BLOCK],
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[CLOCK RATE],
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[TEXTURE ALIGNMENT],
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//[GPU OVERLAP],
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[MULTIPROCESSOR COUNT],
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[KERNEL EXEC TIMEOUT],
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[INTEGRATED],
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[CAN MAP HOST MEMORY],
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[COMPUTE MODE],
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[MAXIMUM TEXTURE1D WIDTH],
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[MAXIMUM TEXTURE2D WIDTH],
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[MAXIMUM TEXTURE2D HEIGHT],
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[MAXIMUM TEXTURE3D WIDTH],
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[MAXIMUM TEXTURE3D HEIGHT],
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[MAXIMUM TEXTURE3D DEPTH],
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//[MAXIMUM TEXTURE2D LAYERED WIDTH],
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//[MAXIMUM TEXTURE2D LAYERED HEIGHT],
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//[MAXIMUM TEXTURE2D LAYERED LAYERS],
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//[MAXIMUM TEXTURE2D ARRAY WIDTH],
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//[MAXIMUM TEXTURE2D ARRAY HEIGHT],
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//[MAXIMUM TEXTURE2D ARRAY NUMSLICES],
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//[SURFACE ALIGNMENT],
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[CONCURRENT KERNELS],
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[ECC ENABLED],
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[PCI BUS ID],
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[PCI DEVICE ID],
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//[TCC DRIVER],
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[MEMORY CLOCK RATE],
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[GLOBAL MEMORY BUS WIDTH],
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[L2 CACHE SIZE],
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[MAX THREADS PER MULTIPROCESSOR],
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[ASYNC ENGINE COUNT],
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//[UNIFIED ADDRESSING],
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//[MAXIMUM TEXTURE1D LAYERED WIDTH],
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//[MAXIMUM TEXTURE1D LAYERED LAYERS],
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//[CAN TEX2D GATHER],
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//[MAXIMUM TEXTURE2D GATHER WIDTH],
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//[MAXIMUM TEXTURE2D GATHER HEIGHT],
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//[MAXIMUM TEXTURE3D WIDTH ALTERNATE],
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//[MAXIMUM TEXTURE3D HEIGHT ALTERNATE],
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//[MAXIMUM TEXTURE3D DEPTH ALTERNATE],
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//[PCI DOMAIN ID],
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[TEXTURE PITCH ALIGNMENT],
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//[MAXIMUM TEXTURECUBEMAP WIDTH],
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//[MAXIMUM TEXTURECUBEMAP LAYERED WIDTH],
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//[MAXIMUM TEXTURECUBEMAP LAYERED LAYERS],
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//[MAXIMUM SURFACE1D WIDTH],
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//[MAXIMUM SURFACE2D WIDTH],
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//[MAXIMUM SURFACE2D HEIGHT],
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//[MAXIMUM SURFACE3D WIDTH],
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//[MAXIMUM SURFACE3D HEIGHT],
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//[MAXIMUM SURFACE3D DEPTH],
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//[MAXIMUM SURFACE1D LAYERED WIDTH],
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//[MAXIMUM SURFACE1D LAYERED LAYERS],
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//[MAXIMUM SURFACE2D LAYERED WIDTH],
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//[MAXIMUM SURFACE2D LAYERED HEIGHT],
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//[MAXIMUM SURFACE2D LAYERED LAYERS],
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//[MAXIMUM SURFACECUBEMAP WIDTH],
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//[MAXIMUM SURFACECUBEMAP LAYERED WIDTH],
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//[MAXIMUM SURFACECUBEMAP LAYERED LAYERS],
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//[MAXIMUM TEXTURE1D LINEAR WIDTH],
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//[MAXIMUM TEXTURE2D LINEAR WIDTH],
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//[MAXIMUM TEXTURE2D LINEAR HEIGHT],
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//[MAXIMUM TEXTURE2D LINEAR PITCH],
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//[MAXIMUM TEXTURE2D MIPMAPPED WIDTH],
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//[MAXIMUM TEXTURE2D MIPMAPPED HEIGHT],
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//[COMPUTE CAPABILITY MAJOR],
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//[COMPUTE CAPABILITY MINOR],
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//[MAXIMUM TEXTURE1D MIPMAPPED WIDTH],
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//[STREAM PRIORITIES SUPPORTED],
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//[GLOBAL L1 CACHE SUPPORTED],
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//[LOCAL L1 CACHE SUPPORTED],
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[MAX SHARED MEMORY PER MULTIPROCESSOR],
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//[MAX REGISTERS PER MULTIPROCESSOR],
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[MANAGED MEMORY],
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//[MULTI GPU BOARD],
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//[MULTI GPU BOARD GROUP ID],
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//[HOST NATIVE ATOMIC SUPPORTED],
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//[SINGLE TO DOUBLE PRECISION PERF RATIO],
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[PAGEABLE MEMORY ACCESS],
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[CONCURRENT MANAGED ACCESS],
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//[COMPUTE PREEMPTION SUPPORTED],
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//[CAN USE HOST POINTER FOR REGISTERED MEM],
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//[CAN USE STREAM MEM OPS],
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//[CAN USE 64 BIT STREAM MEM OPS],
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//[CAN USE STREAM WAIT VALUE NOR],
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[COOPERATIVE LAUNCH],
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[COOPERATIVE MULTI DEVICE LAUNCH],
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//[MAX SHARED MEMORY PER BLOCK OPTIN],
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//[CAN FLUSH REMOTE WRITES],
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//[HOST REGISTER SUPPORTED],
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[PAGEABLE MEMORY ACCESS USES HOST PAGE TABLES],
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[DIRECT MANAGED MEM ACCESS FROM HOST],
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//[VIRTUAL ADDRESS MANAGEMENT SUPPORTED],
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//[VIRTUAL MEMORY MANAGEMENT SUPPORTED],
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//[HANDLE TYPE POSIX FILE DESCRIPTOR SUPPORTED],
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//[HANDLE TYPE WIN32 HANDLE SUPPORTED],
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//[HANDLE TYPE WIN32 KMT HANDLE SUPPORTED],
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//[MAX BLOCKS PER MULTIPROCESSOR],
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//[GENERIC COMPRESSION SUPPORTED],
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//[MAX PERSISTING L2 CACHE SIZE],
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//[MAX ACCESS POLICY WINDOW SIZE],
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//[GPU DIRECT RDMA WITH CUDA VMM SUPPORTED],
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//[RESERVED SHARED MEMORY PER BLOCK],
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//[SPARSE CUDA ARRAY SUPPORTED],
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//[READ ONLY HOST REGISTER SUPPORTED],
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//[TIMELINE SEMAPHORE INTEROP SUPPORTED],
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//[MEMORY POOLS SUPPORTED],
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},
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};
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unsafe { hipDeviceGetAttribute(pi, hip_attrib, dev_idx) }
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}
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pub fn get_uuid(uuid: *mut CUuuid_st, _dev_idx: c_int) -> Result<(), CUresult> {
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unsafe {
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*uuid = CUuuid_st {
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bytes: mem::zeroed(),
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}
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};
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Ok(())
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}
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// TODO: add support if Level 0 exposes it
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pub fn get_luid(
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luid: *mut c_char,
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dev_node_mask: *mut c_uint,
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_dev_idx: c_int,
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) -> Result<(), CUresult> {
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unsafe { ptr::write_bytes(luid, 0u8, 8) };
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unsafe { *dev_node_mask = 0 };
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Ok(())
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}
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pub(crate) unsafe fn get_properties(prop: *mut CUdevprop, dev: CUdevice) -> Result<(), hipError_t> {
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if prop == ptr::null_mut() {
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return Err(hipError_t::hipErrorInvalidValue);
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_ => {}
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}
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let mut hip_props = mem::zeroed();
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hip_call! { hipGetDeviceProperties(&mut hip_props, dev.0) };
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(*prop).maxThreadsPerBlock = hip_props.maxThreadsPerBlock;
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(*prop).maxThreadsDim = hip_props.maxThreadsDim;
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(*prop).maxGridSize = hip_props.maxGridSize;
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(*prop).totalConstantMemory = usize::min(hip_props.totalConstMem, i32::MAX as usize) as i32;
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(*prop).SIMDWidth = hip_props.warpSize;
|
||||
(*prop).memPitch = usize::min(hip_props.memPitch, i32::MAX as usize) as i32;
|
||||
(*prop).regsPerBlock = hip_props.regsPerBlock;
|
||||
(*prop).clockRate = hip_props.clockRate;
|
||||
(*prop).textureAlign = usize::min(hip_props.textureAlignment, i32::MAX as usize) as i32;
|
||||
let attrib = remap_attribute! {
|
||||
attrib =>
|
||||
[MAX THREADS PER BLOCK],
|
||||
[MAX BLOCK DIM X],
|
||||
[MAX BLOCK DIM Y],
|
||||
[MAX BLOCK DIM Z],
|
||||
[MAX GRID DIM X],
|
||||
[MAX GRID DIM Y],
|
||||
[MAX GRID DIM Z],
|
||||
[MAX SHARED MEMORY PER BLOCK],
|
||||
[TOTAL CONSTANT MEMORY],
|
||||
//[WARP SIZE],
|
||||
[MAX PITCH],
|
||||
[MAX REGISTERS PER BLOCK],
|
||||
[CLOCK RATE],
|
||||
[TEXTURE ALIGNMENT],
|
||||
[GPU OVERLAP],
|
||||
[MULTIPROCESSOR COUNT],
|
||||
[KERNEL EXEC TIMEOUT],
|
||||
[INTEGRATED],
|
||||
[CAN MAP HOST MEMORY],
|
||||
[COMPUTE MODE],
|
||||
[MAXIMUM TEXTURE1D WIDTH],
|
||||
[MAXIMUM TEXTURE2D WIDTH],
|
||||
[MAXIMUM TEXTURE2D HEIGHT],
|
||||
[MAXIMUM TEXTURE3D WIDTH],
|
||||
[MAXIMUM TEXTURE3D HEIGHT],
|
||||
[MAXIMUM TEXTURE3D DEPTH],
|
||||
//[MAXIMUM TEXTURE2D LAYERED WIDTH],
|
||||
//[MAXIMUM TEXTURE2D LAYERED HEIGHT],
|
||||
//[MAXIMUM TEXTURE2D LAYERED LAYERS],
|
||||
//[MAXIMUM TEXTURE2D ARRAY WIDTH],
|
||||
//[MAXIMUM TEXTURE2D ARRAY HEIGHT],
|
||||
//[MAXIMUM TEXTURE2D ARRAY NUMSLICES],
|
||||
[SURFACE ALIGNMENT],
|
||||
[CONCURRENT KERNELS],
|
||||
[ECC ENABLED],
|
||||
[PCI BUS ID],
|
||||
[PCI DEVICE ID],
|
||||
//[TCC DRIVER],
|
||||
[MEMORY CLOCK RATE],
|
||||
[GLOBAL MEMORY BUS WIDTH],
|
||||
[L2 CACHE SIZE],
|
||||
[MAX THREADS PER MULTIPROCESSOR],
|
||||
[ASYNC ENGINE COUNT],
|
||||
[UNIFIED ADDRESSING],
|
||||
//[MAXIMUM TEXTURE1D LAYERED WIDTH],
|
||||
//[MAXIMUM TEXTURE1D LAYERED LAYERS],
|
||||
//[CAN TEX2D GATHER],
|
||||
//[MAXIMUM TEXTURE2D GATHER WIDTH],
|
||||
//[MAXIMUM TEXTURE2D GATHER HEIGHT],
|
||||
//[MAXIMUM TEXTURE3D WIDTH ALTERNATE],
|
||||
//[MAXIMUM TEXTURE3D HEIGHT ALTERNATE],
|
||||
//[MAXIMUM TEXTURE3D DEPTH ALTERNATE],
|
||||
[PCI DOMAIN ID],
|
||||
[TEXTURE PITCH ALIGNMENT],
|
||||
//[MAXIMUM TEXTURECUBEMAP WIDTH],
|
||||
//[MAXIMUM TEXTURECUBEMAP LAYERED WIDTH],
|
||||
//[MAXIMUM TEXTURECUBEMAP LAYERED LAYERS],
|
||||
//[MAXIMUM SURFACE1D WIDTH],
|
||||
//[MAXIMUM SURFACE2D WIDTH],
|
||||
//[MAXIMUM SURFACE2D HEIGHT],
|
||||
//[MAXIMUM SURFACE3D WIDTH],
|
||||
//[MAXIMUM SURFACE3D HEIGHT],
|
||||
//[MAXIMUM SURFACE3D DEPTH],
|
||||
//[MAXIMUM SURFACE1D LAYERED WIDTH],
|
||||
//[MAXIMUM SURFACE1D LAYERED LAYERS],
|
||||
//[MAXIMUM SURFACE2D LAYERED WIDTH],
|
||||
//[MAXIMUM SURFACE2D LAYERED HEIGHT],
|
||||
//[MAXIMUM SURFACE2D LAYERED LAYERS],
|
||||
//[MAXIMUM SURFACECUBEMAP WIDTH],
|
||||
//[MAXIMUM SURFACECUBEMAP LAYERED WIDTH],
|
||||
//[MAXIMUM SURFACECUBEMAP LAYERED LAYERS],
|
||||
//[MAXIMUM TEXTURE1D LINEAR WIDTH],
|
||||
//[MAXIMUM TEXTURE2D LINEAR WIDTH],
|
||||
//[MAXIMUM TEXTURE2D LINEAR HEIGHT],
|
||||
//[MAXIMUM TEXTURE2D LINEAR PITCH],
|
||||
//[MAXIMUM TEXTURE2D MIPMAPPED WIDTH],
|
||||
//[MAXIMUM TEXTURE2D MIPMAPPED HEIGHT],
|
||||
//[COMPUTE CAPABILITY MAJOR],
|
||||
//[COMPUTE CAPABILITY MINOR],
|
||||
//[MAXIMUM TEXTURE1D MIPMAPPED WIDTH],
|
||||
[STREAM PRIORITIES SUPPORTED],
|
||||
[GLOBAL L1 CACHE SUPPORTED],
|
||||
[LOCAL L1 CACHE SUPPORTED],
|
||||
[MAX SHARED MEMORY PER MULTIPROCESSOR],
|
||||
[MAX REGISTERS PER MULTIPROCESSOR],
|
||||
[MANAGED MEMORY],
|
||||
[MULTI GPU BOARD],
|
||||
[MULTI GPU BOARD GROUP ID],
|
||||
[HOST NATIVE ATOMIC SUPPORTED],
|
||||
[SINGLE TO DOUBLE PRECISION PERF RATIO],
|
||||
[PAGEABLE MEMORY ACCESS],
|
||||
[CONCURRENT MANAGED ACCESS],
|
||||
[COMPUTE PREEMPTION SUPPORTED],
|
||||
[CAN USE HOST POINTER FOR REGISTERED MEM],
|
||||
//[CAN USE STREAM MEM OPS],
|
||||
[COOPERATIVE LAUNCH],
|
||||
[COOPERATIVE MULTI DEVICE LAUNCH],
|
||||
[MAX SHARED MEMORY PER BLOCK OPTIN],
|
||||
//[CAN FLUSH REMOTE WRITES],
|
||||
[HOST REGISTER SUPPORTED],
|
||||
[PAGEABLE MEMORY ACCESS USES HOST PAGE TABLES],
|
||||
[DIRECT MANAGED MEM ACCESS FROM HOST],
|
||||
//[VIRTUAL ADDRESS MANAGEMENT SUPPORTED],
|
||||
[VIRTUAL MEMORY MANAGEMENT SUPPORTED],
|
||||
//[HANDLE TYPE POSIX FILE DESCRIPTOR SUPPORTED],
|
||||
//[HANDLE TYPE WIN32 HANDLE SUPPORTED],
|
||||
//[HANDLE TYPE WIN32 KMT HANDLE SUPPORTED],
|
||||
//[MAX BLOCKS PER MULTIPROCESSOR],
|
||||
//[GENERIC COMPRESSION SUPPORTED],
|
||||
//[MAX PERSISTING L2 CACHE SIZE],
|
||||
//[MAX ACCESS POLICY WINDOW SIZE],
|
||||
//[GPU DIRECT RDMA WITH CUDA VMM SUPPORTED],
|
||||
//[RESERVED SHARED MEMORY PER BLOCK],
|
||||
//[SPARSE CUDA ARRAY SUPPORTED],
|
||||
//[READ ONLY HOST REGISTER SUPPORTED],
|
||||
//[TIMELINE SEMAPHORE INTEROP SUPPORTED],
|
||||
[MEMORY POOLS SUPPORTED],
|
||||
//[GPU DIRECT RDMA SUPPORTED],
|
||||
//[GPU DIRECT RDMA FLUSH WRITES OPTIONS],
|
||||
//[GPU DIRECT RDMA WRITES ORDERING],
|
||||
//[MEMPOOL SUPPORTED HANDLE TYPES],
|
||||
//[CLUSTER LAUNCH],
|
||||
//[DEFERRED MAPPING CUDA ARRAY SUPPORTED],
|
||||
//[CAN USE 64 BIT STREAM MEM OPS],
|
||||
//[CAN USE STREAM WAIT VALUE NOR],
|
||||
//[DMA BUF SUPPORTED],
|
||||
//[IPC EVENT SUPPORTED],
|
||||
//[MEM SYNC DOMAIN COUNT],
|
||||
//[TENSOR MAP ACCESS SUPPORTED],
|
||||
//[HANDLE TYPE FABRIC SUPPORTED],
|
||||
//[UNIFIED FUNCTION POINTERS],
|
||||
//[NUMA CONFIG],
|
||||
//[NUMA ID],
|
||||
//[MULTICAST SUPPORTED],
|
||||
//[MPS ENABLED],
|
||||
//[HOST NUMA ID],
|
||||
};
|
||||
unsafe { hipDeviceGetAttribute(pi, attrib, dev_idx) }
|
||||
}
|
||||
|
||||
pub(crate) fn get_uuid(uuid: *mut hipUUID, device: hipDevice_t) -> hipError_t {
|
||||
unsafe { hipDeviceGetUuid(uuid, device) }
|
||||
}
|
||||
|
||||
pub(crate) fn get_uuid_v2(uuid: *mut hipUUID, device: hipDevice_t) -> hipError_t {
|
||||
get_uuid(uuid, device)
|
||||
}
|
||||
|
||||
pub(crate) fn get_luid(
|
||||
luid: *mut ::core::ffi::c_char,
|
||||
device_node_mask: &mut ::core::ffi::c_uint,
|
||||
dev: hipDevice_t,
|
||||
) -> hipError_t {
|
||||
let luid = unsafe {
|
||||
luid.cast::<[i8; 8]>()
|
||||
.as_mut()
|
||||
.ok_or(hipErrorCode_t::hipErrorInvalidValue)
|
||||
}?;
|
||||
let mut properties = unsafe { mem::zeroed() };
|
||||
unsafe { hipGetDevicePropertiesR0600(&mut properties, dev) }?;
|
||||
*luid = properties.luid;
|
||||
*device_node_mask = properties.luidDeviceNodeMask;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub(crate) fn get_name(
|
||||
name: *mut ::core::ffi::c_char,
|
||||
len: ::core::ffi::c_int,
|
||||
dev: hipDevice_t,
|
||||
) -> cuda_types::CUresult {
|
||||
unsafe { hipDeviceGetName(name, len, dev) }?;
|
||||
let len = len as usize;
|
||||
let buffer = unsafe { std::slice::from_raw_parts(name, len) };
|
||||
let first_zero = buffer.iter().position(|c| *c == 0);
|
||||
let first_zero = if let Some(x) = first_zero {
|
||||
x
|
||||
} else {
|
||||
return Ok(());
|
||||
};
|
||||
if (first_zero + PROJECT_SUFFIX.len()) > len {
|
||||
return Ok(());
|
||||
}
|
||||
unsafe {
|
||||
ptr::copy_nonoverlapping(
|
||||
PROJECT_SUFFIX.as_ptr() as _,
|
||||
name.add(first_zero),
|
||||
PROJECT_SUFFIX.len(),
|
||||
)
|
||||
};
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub(crate) fn total_mem_v2(bytes: *mut usize, dev: hipDevice_t) -> hipError_t {
|
||||
unsafe { hipDeviceTotalMem(bytes, dev) }
|
||||
}
|
||||
|
||||
pub(crate) fn get_properties(prop: &mut cuda_types::CUdevprop, dev: hipDevice_t) -> hipError_t {
|
||||
let mut hip_props = unsafe { mem::zeroed() };
|
||||
unsafe { hipGetDevicePropertiesR0600(&mut hip_props, dev) }?;
|
||||
prop.maxThreadsPerBlock = hip_props.maxThreadsPerBlock;
|
||||
prop.maxThreadsDim = hip_props.maxThreadsDim;
|
||||
prop.maxGridSize = hip_props.maxGridSize;
|
||||
prop.totalConstantMemory = clamp_usize(hip_props.totalConstMem);
|
||||
prop.SIMDWidth = 32;
|
||||
prop.memPitch = clamp_usize(hip_props.memPitch);
|
||||
prop.regsPerBlock = hip_props.regsPerBlock;
|
||||
prop.clockRate = hip_props.clockRate;
|
||||
prop.textureAlign = clamp_usize(hip_props.textureAlignment);
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn clamp_usize(x: usize) -> i32 {
|
||||
usize::min(x, i32::MAX as usize) as i32
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,6 +1,8 @@
|
|||
use cuda_types::*;
|
||||
use hip_runtime_sys::*;
|
||||
|
||||
pub(super) mod device;
|
||||
|
||||
#[cfg(debug_assertions)]
|
||||
pub(crate) fn unimplemented() -> CUresult {
|
||||
unimplemented!()
|
||||
|
|
@ -11,16 +13,70 @@ pub(crate) fn unimplemented() -> CUresult {
|
|||
CUresult::ERROR_NOT_SUPPORTED
|
||||
}
|
||||
|
||||
pub(crate) trait FromCuda<T>: Sized {
|
||||
fn from_cuda(t: T) -> Result<Self, CUerror>;
|
||||
pub(crate) trait FromCuda<'a, T>: Sized {
|
||||
fn from_cuda(t: &'a T) -> Result<Self, CUerror>;
|
||||
}
|
||||
|
||||
impl FromCuda<u32> for u32 {
|
||||
fn from_cuda(x: u32) -> Result<Self, CUerror> {
|
||||
Ok(x)
|
||||
}
|
||||
macro_rules! from_cuda_noop {
|
||||
($($type_:ty),*) => {
|
||||
$(
|
||||
impl<'a> FromCuda<'a, $type_> for $type_ {
|
||||
fn from_cuda(x: &'a $type_) -> Result<Self, CUerror> {
|
||||
Ok(*x)
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a> FromCuda<'a, *mut $type_> for &'a mut $type_ {
|
||||
fn from_cuda(x: &'a *mut $type_) -> Result<Self, CUerror> {
|
||||
match unsafe { x.as_mut() } {
|
||||
Some(x) => Ok(x),
|
||||
None => Err(CUerror::INVALID_VALUE),
|
||||
}
|
||||
}
|
||||
}
|
||||
)*
|
||||
};
|
||||
}
|
||||
|
||||
macro_rules! from_cuda_transmute {
|
||||
($($from:ty => $to:ty),*) => {
|
||||
$(
|
||||
impl<'a> FromCuda<'a, $from> for $to {
|
||||
fn from_cuda(x: &'a $from) -> Result<Self, CUerror> {
|
||||
Ok(unsafe { std::mem::transmute(*x) })
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a> FromCuda<'a, *mut $from> for &'a mut $to {
|
||||
fn from_cuda(x: &'a *mut $from) -> Result<Self, CUerror> {
|
||||
match unsafe { x.cast::<$to>().as_mut() } {
|
||||
Some(x) => Ok(x),
|
||||
None => Err(CUerror::INVALID_VALUE),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a> FromCuda<'a, *mut $from> for * mut $to {
|
||||
fn from_cuda(x: &'a *mut $from) -> Result<Self, CUerror> {
|
||||
Ok(x.cast::<$to>())
|
||||
}
|
||||
}
|
||||
)*
|
||||
};
|
||||
}
|
||||
|
||||
from_cuda_noop!(
|
||||
*mut i8,
|
||||
*mut usize,
|
||||
i32,
|
||||
u32,
|
||||
cuda_types::CUdevprop, CUdevice_attribute
|
||||
);
|
||||
from_cuda_transmute!(
|
||||
CUdevice => hipDevice_t,
|
||||
CUuuid => hipUUID
|
||||
);
|
||||
|
||||
pub(crate) fn init(flags: ::core::ffi::c_uint) -> hipError_t {
|
||||
unsafe { hipInit(flags) }
|
||||
}
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@ macro_rules! implemented {
|
|||
#[allow(improper_ctypes)]
|
||||
#[allow(improper_ctypes_definitions)]
|
||||
pub unsafe extern $abi fn $fn_name ( $( $arg_id : $arg_type),* ) -> $ret_type {
|
||||
cuda_base::cuda_normalize_fn!( crate::r#impl::$fn_name ) ($(crate::r#impl::FromCuda::from_cuda($arg_id)?),*)?;
|
||||
cuda_base::cuda_normalize_fn!( crate::r#impl::$fn_name ) ($(crate::r#impl::FromCuda::from_cuda(&$arg_id)?),*)?;
|
||||
Ok(())
|
||||
}
|
||||
)*
|
||||
|
|
@ -32,6 +32,15 @@ use cuda_base::cuda_function_declarations;
|
|||
cuda_function_declarations!(
|
||||
unimplemented,
|
||||
implemented <= [
|
||||
cuInit
|
||||
cuDeviceComputeCapability,
|
||||
cuDeviceGet,
|
||||
cuDeviceGetAttribute,
|
||||
cuDeviceGetLuid,
|
||||
cuDeviceGetName,
|
||||
cuDeviceGetProperties,
|
||||
cuDeviceGetUuid,
|
||||
cuDeviceGetUuid_v2,
|
||||
cuDeviceTotalMem_v2,
|
||||
cuInit,
|
||||
]
|
||||
);
|
||||
Loading…
Add table
Reference in a new issue