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Add mad_hi_cc.ptx test
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NyanCatTW1
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3 changed files with 162 additions and 0 deletions
111
ptx/src/test/spirv_run/mad_hi_cc.ll
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111
ptx/src/test/spirv_run/mad_hi_cc.ll
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@ -0,0 +1,111 @@
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target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7"
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target triple = "amdgcn-amd-amdhsa"
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define protected amdgpu_kernel void @mad_hi_cc(ptr addrspace(4) byref(i64) %"76", ptr addrspace(4) byref(i64) %"77") #0 {
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"99":
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%"15" = alloca i1, align 1, addrspace(5)
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store i1 false, ptr addrspace(5) %"15", align 1
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%"16" = alloca i1, align 1, addrspace(5)
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store i1 false, ptr addrspace(5) %"16", align 1
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%"4" = alloca i64, align 8, addrspace(5)
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%"5" = alloca i64, align 8, addrspace(5)
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%"6" = alloca i32, align 4, addrspace(5)
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%"7" = alloca i32, align 4, addrspace(5)
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%"8" = alloca i32, align 4, addrspace(5)
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%"9" = alloca i32, align 4, addrspace(5)
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%"10" = alloca i32, align 4, addrspace(5)
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%"11" = alloca i32, align 4, addrspace(5)
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%"12" = alloca i32, align 4, addrspace(5)
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%"13" = alloca i32, align 4, addrspace(5)
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%"14" = alloca i32, align 4, addrspace(5)
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%"17" = load i64, ptr addrspace(4) %"76", align 8
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store i64 %"17", ptr addrspace(5) %"4", align 8
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%"18" = load i64, ptr addrspace(4) %"77", align 8
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store i64 %"18", ptr addrspace(5) %"5", align 8
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%"20" = load i64, ptr addrspace(5) %"4", align 8
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%"79" = inttoptr i64 %"20" to ptr
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%"78" = load i32, ptr %"79", align 4
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store i32 %"78", ptr addrspace(5) %"8", align 4
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%"22" = load i64, ptr addrspace(5) %"4", align 8
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%"80" = inttoptr i64 %"22" to ptr
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%"101" = getelementptr inbounds i8, ptr %"80", i64 4
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%"81" = load i32, ptr %"101", align 4
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store i32 %"81", ptr addrspace(5) %"9", align 4
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%"24" = load i64, ptr addrspace(5) %"4", align 8
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%"82" = inttoptr i64 %"24" to ptr
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%"103" = getelementptr inbounds i8, ptr %"82", i64 8
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%"23" = load i32, ptr %"103", align 4
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store i32 %"23", ptr addrspace(5) %"10", align 4
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%"27" = load i32, ptr addrspace(5) %"8", align 4
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%"28" = load i32, ptr addrspace(5) %"9", align 4
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%"29" = load i32, ptr addrspace(5) %"10", align 4
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%0 = sext i32 %"27" to i64
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%1 = sext i32 %"28" to i64
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%2 = mul nsw i64 %0, %1
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%3 = lshr i64 %2, 32
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%4 = trunc i64 %3 to i32
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%5 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %4, i32 %"29")
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%"25" = extractvalue { i32, i1 } %5, 0
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%"26" = extractvalue { i32, i1 } %5, 1
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store i32 %"25", ptr addrspace(5) %"7", align 4
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store i1 %"26", ptr addrspace(5) %"15", align 1
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%"30" = load i64, ptr addrspace(5) %"5", align 8
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%"31" = load i32, ptr addrspace(5) %"7", align 4
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%"86" = inttoptr i64 %"30" to ptr
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store i32 %"31", ptr %"86", align 4
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%6 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 0, i32 -1)
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%"32" = extractvalue { i32, i1 } %6, 0
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%"33" = extractvalue { i32, i1 } %6, 1
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store i32 %"32", ptr addrspace(5) %"6", align 4
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store i1 %"33", ptr addrspace(5) %"15", align 1
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%"36" = load i1, ptr addrspace(5) %"15", align 1
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%7 = zext i1 %"36" to i32
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%8 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 1, i32 -1)
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%9 = extractvalue { i32, i1 } %8, 0
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%10 = extractvalue { i32, i1 } %8, 1
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%11 = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %9, i32 %7)
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%"87" = extractvalue { i32, i1 } %11, 0
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%12 = extractvalue { i32, i1 } %11, 1
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%"35" = xor i1 %10, %12
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store i32 %"87", ptr addrspace(5) %"11", align 4
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store i1 %"35", ptr addrspace(5) %"15", align 1
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%"38" = load i1, ptr addrspace(5) %"15", align 1
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%13 = zext i1 %"38" to i32
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%"88" = add i32 0, %13
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store i32 %"88", ptr addrspace(5) %"12", align 4
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%"40" = load i1, ptr addrspace(5) %"15", align 1
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%14 = zext i1 %"40" to i32
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%"89" = add i32 0, %14
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store i32 %"89", ptr addrspace(5) %"13", align 4
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%"42" = load i1, ptr addrspace(5) %"16", align 1
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%15 = zext i1 %"42" to i32
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%"90" = sub i32 2, %15
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store i32 %"90", ptr addrspace(5) %"14", align 4
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%"43" = load i64, ptr addrspace(5) %"5", align 8
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%"44" = load i32, ptr addrspace(5) %"11", align 4
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%"91" = inttoptr i64 %"43" to ptr
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%"105" = getelementptr inbounds i8, ptr %"91", i64 4
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store i32 %"44", ptr %"105", align 4
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%"45" = load i64, ptr addrspace(5) %"5", align 8
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%"46" = load i32, ptr addrspace(5) %"12", align 4
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%"93" = inttoptr i64 %"45" to ptr
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%"107" = getelementptr inbounds i8, ptr %"93", i64 8
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store i32 %"46", ptr %"107", align 4
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%"47" = load i64, ptr addrspace(5) %"5", align 8
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%"48" = load i32, ptr addrspace(5) %"13", align 4
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%"95" = inttoptr i64 %"47" to ptr
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%"109" = getelementptr inbounds i8, ptr %"95", i64 12
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store i32 %"48", ptr %"109", align 4
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%"49" = load i64, ptr addrspace(5) %"5", align 8
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%"50" = load i32, ptr addrspace(5) %"14", align 4
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%"97" = inttoptr i64 %"49" to ptr
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%"111" = getelementptr inbounds i8, ptr %"97", i64 16
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store i32 %"50", ptr %"111", align 4
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ret void
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}
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; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn
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declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1
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attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "no-trapping-math"="true" "uniform-work-group-size"="true" }
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attributes #1 = { nocallback nofree nosync nounwind readnone speculatable willreturn }
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50
ptx/src/test/spirv_run/mad_hi_cc.ptx
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50
ptx/src/test/spirv_run/mad_hi_cc.ptx
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@ -0,0 +1,50 @@
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.version 6.5
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.target sm_30
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.address_size 64
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.visible .entry mad_hi_cc(
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.param .u64 input,
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.param .u64 output
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)
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{
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.reg .u64 in_addr;
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.reg .u64 out_addr;
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.reg .u32 unused;
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.reg .s32 dst1;
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.reg .b32 src1;
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.reg .b32 src2;
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.reg .b32 src3;
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.reg .b32 result_1;
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.reg .b32 carry_out_1_1;
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.reg .b32 carry_out_1_2;
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.reg .b32 carry_out_1_3;
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ld.param.u64 in_addr, [input];
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ld.param.u64 out_addr, [output];
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// test valid computational results
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ld.s32 src1, [in_addr];
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ld.s32 src2, [in_addr+4];
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ld.b32 src3, [in_addr+8];
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mad.hi.cc.s32 dst1, src1, src2, src3;
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st.s32 [out_addr], dst1;
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// set carry=1
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mad.lo.cc.u32 unused, 0, 0, 4294967295;
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// overflow addition
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madc.hi.cc.u32 result_1, 65536, 65536, 4294967295;
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// write carry
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madc.lo.u32 carry_out_1_1, 0, 0, 0;
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// overflow is also detected by addc
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addc.u32 carry_out_1_2, 0, 0;
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// but not subc
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subc.u32 carry_out_1_3, 2, 0;
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st.s32 [out_addr+4], result_1;
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st.s32 [out_addr+8], carry_out_1_1;
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st.s32 [out_addr+12], carry_out_1_2;
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st.s32 [out_addr+16], carry_out_1_3;
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ret;
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}
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@ -290,6 +290,7 @@ test_ptx!(
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[2147487519u32, 4294934539]
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);
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test_ptx!(madc_cc2, [0xDEADu32], [0u32, 1, 1, 2]);
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test_ptx!(mad_hi_cc, [0x26223377u32, 0x70777766u32, 0x60666633u32], [0x71272866u32, 0u32, 1, 1, 2]); // Multi-tap :)
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test_ptx!(mov_vector_cast, [0x200000001u64], [2u32, 1u32]);
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test_ptx!(
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cvt_clamp,
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