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https://github.com/vosen/ZLUDA.git
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Implement sad instruction
This commit is contained in:
Andrzej Janik
parent
0d9ace2475
commit
fca92e31e4
7 changed files with 139 additions and 0 deletions
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@ -476,6 +476,7 @@ pub enum Instruction<P: ArgParams> {
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MatchAny(Arg3<P>),
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Red(AtomDetails, Arg2St<P>),
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Nanosleep(Arg1<P>),
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Sad(ScalarType, Arg4<P>),
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}
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#[derive(Copy, Clone)]
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@ -13,6 +13,7 @@ use zluda_llvm::prelude::*;
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use zluda_llvm::zluda::*;
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use zluda_llvm::*;
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use crate::ast::SetpData;
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use crate::translate::{
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self, Arg4CarryOut, ConstType, ConversionKind, DenormSummary, ExpandedArgParams, FPDenormMode,
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MadCCDetails, MadCDetails, TranslationModule, TypeKind, TypeParts,
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@ -1137,6 +1138,7 @@ fn emit_instruction(
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ast::Instruction::Vshr(arg) => emit_inst_vshr(ctx, arg)?,
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ast::Instruction::Set(details, arg) => emit_inst_set(ctx, details, arg)?,
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ast::Instruction::Red(details, arg) => emit_inst_red(ctx, details, arg)?,
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ast::Instruction::Sad(type_, arg) => emit_inst_sad(ctx, *type_, arg)?,
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// replaced by function calls or Statement variants
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ast::Instruction::Activemask { .. }
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| ast::Instruction::Bar(..)
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@ -1161,6 +1163,35 @@ fn emit_instruction(
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})
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}
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fn emit_inst_sad(
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ctx: &mut EmitContext,
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type_: ast::ScalarType,
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arg: &ast::Arg4<ExpandedArgParams>,
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) -> Result<(), TranslateError> {
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let builder = ctx.builder.get();
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let less_than = emit_inst_setp_int(
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ctx,
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&SetpData {
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typ: type_,
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flush_to_zero: None,
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cmp_op: ast::SetpCompareOp::Less,
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},
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None,
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arg.src1,
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arg.src2,
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)?;
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let a = ctx.names.value(arg.src1)?;
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let b = ctx.names.value(arg.src2)?;
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let b_minus_a = unsafe { LLVMBuildSub(builder, b, a, LLVM_UNNAMED) };
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let a_minus_b = unsafe { LLVMBuildSub(builder, a, b, LLVM_UNNAMED) };
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let a_or_b = unsafe { LLVMBuildSelect(builder, less_than, b_minus_a, a_minus_b, LLVM_UNNAMED) };
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let src3 = ctx.names.value(arg.src3)?;
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ctx.names.register_result(arg.dst, |dst_name| unsafe {
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LLVMBuildAdd(builder, src3, a_or_b, dst_name)
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});
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Ok(())
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}
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fn emit_inst_red(
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ctx: &mut EmitContext,
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details: &ast::AtomDetails,
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@ -224,6 +224,7 @@ match {
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"rem",
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"ret",
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"rsqrt",
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"sad",
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"selp",
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"set",
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"setp",
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@ -305,6 +306,7 @@ ExtendedID : &'input str = {
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"rem",
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"ret",
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"rsqrt",
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"sad",
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"selp",
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"set",
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"setp",
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@ -839,6 +841,7 @@ Instruction: ast::Instruction<ast::ParsedArgParams<'input>> = {
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InstMatch,
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InstRed,
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InstNanosleep,
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InstSad
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};
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-ld
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@ -2377,6 +2380,13 @@ InstNanosleep: ast::Instruction<ast::ParsedArgParams<'input>> = {
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}
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}
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// https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#integer-arithmetic-instructions-sad
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InstSad: ast::Instruction<ast::ParsedArgParams<'input>> = {
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"sad" <type_:IntType> <a:Arg4> => {
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ast::Instruction::Sad(type_, a)
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}
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}
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NegTypeFtz: ast::ScalarType = {
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".f16" => ast::ScalarType::F16,
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".f16x2" => ast::ScalarType::F16x2,
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@ -364,6 +364,7 @@ test_ptx!(
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[1923569713u64, 1923569712],
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[1923569713u64, 1923569712]
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);
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test_ptx!(sad, [2147483648u32, 2, 13], [2147483659u32, 2147483663]);
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test_ptx_warp!(
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shfl,
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63
ptx/src/test/spirv_run/sad.ll
Normal file
63
ptx/src/test/spirv_run/sad.ll
Normal file
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@ -0,0 +1,63 @@
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target datalayout = "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32-p6:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-S32-A5-G1-ni:7"
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target triple = "amdgcn-amd-amdhsa"
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define protected amdgpu_kernel void @sad(ptr addrspace(4) byref(i64) %"38", ptr addrspace(4) byref(i64) %"39") #0 {
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"56":
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%"11" = alloca i1, align 1, addrspace(5)
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store i1 false, ptr addrspace(5) %"11", align 1
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%"4" = alloca i64, align 8, addrspace(5)
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%"5" = alloca i64, align 8, addrspace(5)
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%"6" = alloca i32, align 4, addrspace(5)
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%"7" = alloca i32, align 4, addrspace(5)
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%"8" = alloca i32, align 4, addrspace(5)
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%"9" = alloca i32, align 4, addrspace(5)
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%"10" = alloca i32, align 4, addrspace(5)
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%"12" = load i64, ptr addrspace(4) %"38", align 8
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store i64 %"12", ptr addrspace(5) %"4", align 8
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%"13" = load i64, ptr addrspace(4) %"39", align 8
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store i64 %"13", ptr addrspace(5) %"5", align 8
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%"15" = load i64, ptr addrspace(5) %"4", align 8
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%"41" = inttoptr i64 %"15" to ptr
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%"40" = load i32, ptr %"41", align 4
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store i32 %"40", ptr addrspace(5) %"6", align 4
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%"17" = load i64, ptr addrspace(5) %"4", align 8
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%"42" = inttoptr i64 %"17" to ptr
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%"58" = getelementptr inbounds i8, ptr %"42", i64 4
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%"43" = load i32, ptr %"58", align 4
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store i32 %"43", ptr addrspace(5) %"7", align 4
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%"19" = load i64, ptr addrspace(5) %"4", align 8
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%"44" = inttoptr i64 %"19" to ptr
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%"60" = getelementptr inbounds i8, ptr %"44", i64 8
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%"45" = load i32, ptr %"60", align 4
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store i32 %"45", ptr addrspace(5) %"8", align 4
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%"21" = load i32, ptr addrspace(5) %"6", align 4
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%"22" = load i32, ptr addrspace(5) %"7", align 4
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%"23" = load i32, ptr addrspace(5) %"8", align 4
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%0 = icmp ult i32 %"21", %"22"
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%1 = sub i32 %"22", %"21"
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%2 = sub i32 %"21", %"22"
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%3 = select i1 %0, i32 %1, i32 %2
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%"46" = add i32 %"23", %3
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store i32 %"46", ptr addrspace(5) %"9", align 4
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%"25" = load i32, ptr addrspace(5) %"6", align 4
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%"26" = load i32, ptr addrspace(5) %"7", align 4
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%"27" = load i32, ptr addrspace(5) %"8", align 4
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%4 = icmp slt i32 %"25", %"26"
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%5 = sub i32 %"26", %"25"
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%6 = sub i32 %"25", %"26"
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%7 = select i1 %4, i32 %5, i32 %6
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%"50" = add i32 %"27", %7
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store i32 %"50", ptr addrspace(5) %"10", align 4
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%"28" = load i64, ptr addrspace(5) %"5", align 8
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%"29" = load i32, ptr addrspace(5) %"9", align 4
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%"54" = inttoptr i64 %"28" to ptr
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store i32 %"29", ptr %"54", align 4
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%"30" = load i64, ptr addrspace(5) %"5", align 8
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%"31" = load i32, ptr addrspace(5) %"10", align 4
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%"55" = inttoptr i64 %"30" to ptr
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%"62" = getelementptr inbounds i8, ptr %"55", i64 4
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store i32 %"31", ptr %"62", align 4
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ret void
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}
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attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" "denormal-fp-math"="ieee,ieee" "denormal-fp-math-f32"="ieee,ieee" "no-trapping-math"="true" "uniform-work-group-size"="true" }
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29
ptx/src/test/spirv_run/sad.ptx
Normal file
29
ptx/src/test/spirv_run/sad.ptx
Normal file
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@ -0,0 +1,29 @@
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.version 6.5
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.target sm_30
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.address_size 64
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.entry sad(
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.param .u64 input,
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.param .u64 output
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)
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{
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.reg .u64 in_addr;
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.reg .u64 out_addr;
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.reg .b32 a;
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.reg .b32 b;
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.reg .b32 c;
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.reg .b32 result_u32;
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.reg .b32 result_s32;
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ld.param.u64 in_addr, [input];
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ld.param.u64 out_addr, [output];
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ld.u32 a, [in_addr];
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ld.u32 b, [in_addr+4];
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ld.u32 c, [in_addr+8];
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sad.u32 result_u32, a, b, c;
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sad.s32 result_s32, a, b, c;
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st.b32 [out_addr], result_u32;
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st.b32 [out_addr+4], result_s32;
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ret;
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}
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@ -6644,6 +6644,9 @@ impl<T: ArgParamsEx> ast::Instruction<T> {
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ast::StateSpace::Reg,
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)),
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)?),
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ast::Instruction::Sad(type_, a) => {
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ast::Instruction::Sad(type_, a.map(visitor, &ast::Type::Scalar(type_), false)?)
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}
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})
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}
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}
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@ -7000,6 +7003,7 @@ impl<T: ast::ArgParams> ast::Instruction<T> {
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ast::Instruction::Shf(..) => None,
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ast::Instruction::Vote(..) => None,
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ast::Instruction::Nanosleep(..) => None,
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ast::Instruction::Sad(_, _) => None,
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ast::Instruction::Sub(ast::ArithDetails::Float(float_control), _)
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| ast::Instruction::Add(ast::ArithDetails::Float(float_control), _)
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| ast::Instruction::Mul(ast::MulDetails::Float(float_control), _)
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