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Cast to int for enums that are not formattable

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This commit is contained in:
Pokechu22 2022-01-12 16:47:26 -08:00
commit 1a92699455
19 changed files with 60 additions and 42 deletions
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3
Source/Core/Core/PowerPC/CachedInterpreter/CachedInterpreter.cpp
View file

@ -100,7 +100,8 @@ void CachedInterpreter::ExecuteOneBlock()
break;
default:
ERROR_LOG_FMT(POWERPC, "Unknown CachedInterpreter Instruction: {}", code->type);
ERROR_LOG_FMT(POWERPC, "Unknown CachedInterpreter Instruction: {}",
static_cast<int>(code->type));
break;
}
}

9
Source/Core/Core/PowerPC/GDBStub.cpp
View file

@ -848,7 +848,8 @@ static bool AddBreakpoint(BreakpointType type, u32 addr, u32 len)
if (type == BreakpointType::ExecuteHard || type == BreakpointType::ExecuteSoft)
{
PowerPC::breakpoints.Add(addr);
INFO_LOG_FMT(GDB_STUB, "gdb: added {} breakpoint: {:08x} bytes at {:08x}", type, len, addr);
INFO_LOG_FMT(GDB_STUB, "gdb: added {} breakpoint: {:08x} bytes at {:08x}",
static_cast<int>(type), len, addr);
}
else
{
@ -864,7 +865,8 @@ static bool AddBreakpoint(BreakpointType type, u32 addr, u32 len)
new_memcheck.log_on_hit = false;
new_memcheck.is_enabled = true;
PowerPC::memchecks.Add(new_memcheck);
INFO_LOG_FMT(GDB_STUB, "gdb: added {} memcheck: {:08x} bytes at {:08x}", type, len, addr);
INFO_LOG_FMT(GDB_STUB, "gdb: added {} memcheck: {:08x} bytes at {:08x}", static_cast<int>(type),
len, addr);
}
return true;
}
@ -1111,7 +1113,8 @@ bool JustConnected()
void SendSignal(Signal signal)
{
char bfr[128] = {};
fmt::format_to(bfr, "T{:02x}{:02x}:{:08x};{:02x}:{:08x};", signal, 64, PC, 1, GPR(1));
fmt::format_to(bfr, "T{:02x}{:02x}:{:08x};{:02x}:{:08x};", static_cast<u8>(signal), 64, PC, 1,
GPR(1));
SendReply(bfr);
}
} // namespace GDBStub

6
Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.cpp
View file

@ -90,7 +90,8 @@ void Arm64RegCache::LockRegister(ARM64Reg host_reg)
{
auto reg = std::find(m_host_registers.begin(), m_host_registers.end(), host_reg);
ASSERT_MSG(DYNA_REC, reg != m_host_registers.end(),
"Don't try locking a register that isn't in the cache. Reg {}", host_reg);
"Don't try locking a register that isn't in the cache. Reg {}",
static_cast<int>(host_reg));
reg->Lock();
}
@ -98,7 +99,8 @@ void Arm64RegCache::UnlockRegister(ARM64Reg host_reg)
{
auto reg = std::find(m_host_registers.begin(), m_host_registers.end(), host_reg);
ASSERT_MSG(DYNA_REC, reg != m_host_registers.end(),
"Don't try unlocking a register that isn't in the cache. Reg {}", host_reg);
"Don't try unlocking a register that isn't in the cache. Reg {}",
static_cast<int>(host_reg));
reg->Unlock();
}

3
Source/Core/Core/PowerPC/PowerPC.cpp
View file

@ -220,7 +220,8 @@ static void InitializeCPUCore(CPUCore cpu_core)
s_cpu_core_base = JitInterface::InitJitCore(cpu_core);
if (!s_cpu_core_base) // Handle Situations where JIT core isn't available
{
WARN_LOG_FMT(POWERPC, "CPU core {} not available. Falling back to default.", cpu_core);
WARN_LOG_FMT(POWERPC, "CPU core {} not available. Falling back to default.",
static_cast<int>(cpu_core));
s_cpu_core_base = JitInterface::InitJitCore(DefaultCPUCore());
}
break;