diff --git a/Source/DSPSpy/main_spy.cpp b/Source/DSPSpy/main_spy.cpp
index 492632ba5f..3d21ed4e70 100644
--- a/Source/DSPSpy/main_spy.cpp
+++ b/Source/DSPSpy/main_spy.cpp
@@ -424,7 +424,7 @@ void handle_dsp_mail(void)
     }
 
     // Request for an interrupt
-    else if (mail == 0x88881111)
+    else if (mail == 0x88885371)
     {
       if (real_dsp.CheckInterrupt())
       {
diff --git a/Source/DSPSpy/tests/external_interrupt.ds b/Source/DSPSpy/tests/external_interrupt.ds
index df53cc8688..e6951f96e5 100644
--- a/Source/DSPSpy/tests/external_interrupt.ds
+++ b/Source/DSPSpy/tests/external_interrupt.ds
@@ -13,38 +13,23 @@ include "dsp_base_noirq.inc"
 
 test_main:
 	CLR $ACC0
+	CLR $ACC1
 	SBCLR #2
 	SBCLR #3
 	SBCLR #4
-	SBCLR #5
-	SBCLR #6
-
-	LRI $AR0, #0
+	SBSET #5
+	SBSET #6
 
 	LRIS $AX0.H, #1
 	CALL send_back
 
 	SI @DMBH, #0x8888
-	SI @DMBL, #0x1111
+	SI @DMBL, #0x5371
 
-wait_cpu_read:
-	LRS $AC1.M, @DMBH
-	ANDCF $AC1.M, #0x8000
-	JLZ wait_cpu_read
-
-	CLR $ACC1
-second_loop:
+wait_external_irq:
 	INC $ACC1
-	CMPIS $AC1.M, #1
-	JNZ second_loop
-
-	SBSET #6
-	SBSET #5
-	LRI $AR0, #2
-	LRI $AR0, #3
-	LRI $AR0, #4
-	LRI $AR0, #5
-	LRI $AR0, #6
+	TST $ACC0
+	JZ wait_external_irq
 
 	LRIS $AX0.H, #2
 	CALL send_back
@@ -52,6 +37,14 @@ second_loop:
 	JMP end_of_test
 
 external_irq:
+	INC $ACC0
 	LRIS $AX0.H, #3
 	CALL send_back
 	RTI
+
+; Expected output ($AX0.H (send_back num), $AC0.L (interrupt count), and $SR):
+; 1, 0, 3824 (start)
+; 3, 1, 2820 (in interrupt handler)
+; 2, 1, 3820 (back out of interrupt handler)
+; DSPSpy shows "interrupt after 20 ticks / 0 tries" (exact number of ticks varies)
+; ACC1 is 7bb40 or so (also varies, and can vary between steps 2 and 3 if the interrupt happens on the JZ)
diff --git a/Source/DSPSpy/tests/external_interrupt_delay.ds b/Source/DSPSpy/tests/external_interrupt_delay.ds
index 9f440273a1..f227ca60b0 100644
--- a/Source/DSPSpy/tests/external_interrupt_delay.ds
+++ b/Source/DSPSpy/tests/external_interrupt_delay.ds
@@ -13,6 +13,10 @@ include "dsp_base_noirq.inc"
 
 test_main:
 	CLR $ACC0
+	CLR $ACC1
+	SBCLR #2
+	SBCLR #3
+	SBCLR #4
 	SBCLR #5
 	SBCLR #6
 
@@ -22,7 +26,7 @@ test_main:
 	CALL send_back
 
 	SI @DMBH, #0x8888
-	SI @DMBL, #0x1111
+	SI @DMBL, #0x5371
 
 wait_cpu_read:
 	LRS $AC1.M, @DMBH
@@ -53,3 +57,9 @@ external_irq:
 	LRIS $AX0.H, #3
 	CALL send_back
 	RTI
+
+; Expected result ($AX0.H (send_back num), $AR0, and $SR):
+; 1, 0, 2024 (start)
+; 3, 2, 2025 (in interrupt handler - note that the interrupt happens after the first LRI)
+; 2, 6, 3825 (the remaining LRIs execute)
+; DSPSpy shows "interrupt after 131054 ticks / 37414 tries" (exact numbers vary but are close)
diff --git a/Source/DSPSpy/tests/external_interrupt_nested.ds b/Source/DSPSpy/tests/external_interrupt_nested_rti.ds
similarity index 70%
rename from Source/DSPSpy/tests/external_interrupt_nested.ds
rename to Source/DSPSpy/tests/external_interrupt_nested_rti.ds
index e0e8a7d15f..1d3ea12ee2 100644
--- a/Source/DSPSpy/tests/external_interrupt_nested.ds
+++ b/Source/DSPSpy/tests/external_interrupt_nested_rti.ds
@@ -13,6 +13,7 @@ include "dsp_base_noirq.inc"
 
 test_main:
 	CLR $ACC0
+	CLR $ACC1
 	SBCLR #2
 	SBCLR #3
 	SBCLR #4
@@ -25,7 +26,7 @@ test_main:
 	CALL send_back
 
 	SI @DMBH, #0x8888
-	SI @DMBL, #0x1111
+	SI @DMBL, #0x5371
 
 wait_cpu_read:
 	LRS $AC1.M, @DMBH
@@ -38,8 +39,8 @@ second_loop:
 	CMPIS $AC1.M, #1
 	JNZ second_loop
 
-	SBSET #6
 	SBSET #5
+	SBSET #6
 	LRI $AR0, #2
 	LRI $AR0, #3
 	LRI $AR0, #4
@@ -52,16 +53,17 @@ second_loop:
 	JMP end_of_test
 
 external_irq:
+	INC $ACC0
 	INCM $AC0.M
 	LRIS $AX0.H, #3
 	CALL send_back
 
-	; Only trigger a nested interrupt the first time through
-	CMPIS $AC0.M, #1
-	RTINZ
+	; Only trigger a nested interrupt the first time through.
+	CMPIS $AC0.M, #2
+	JGE exit_irq
 
 	SI @DMBH, #0x8888
-	SI @DMBL, #0x1111
+	SI @DMBL, #0x5371
 
 wait_cpu_read_irq:
 	LRS $AC1.M, @DMBH
@@ -74,4 +76,12 @@ second_loop_irq:
 	CMPIS $AC1.M, #1
 	JNZ second_loop_irq
 
+exit_irq:
+	DEC $ACC0
 	RTI
+
+; Expected result ($AX0.H (send_back num), $AC0.L (interrupt depth), $AC0.M (interrupt count), $AR0, and $SR):
+; 1, 0, 0, 0, 2024
+; 3, 1, 1, 2, 2020
+; 3, 1, 2, 3, 2020
+; 2, 0, 2, 6, 3825
diff --git a/Source/DSPSpy/tests/external_interrupt_nested_sbset.ds b/Source/DSPSpy/tests/external_interrupt_nested_sbset.ds
new file mode 100644
index 0000000000..47c325be1f
--- /dev/null
+++ b/Source/DSPSpy/tests/external_interrupt_nested_sbset.ds
@@ -0,0 +1,89 @@
+; This test needs to manually specify IRQs
+	jmp		irq0
+	jmp		irq1
+	jmp		irq2
+	jmp		irq3
+	jmp		irq4
+	jmp		irq5
+	jmp		irq6
+	jmp		external_irq
+
+incdir  "tests"
+include "dsp_base_noirq.inc"
+
+test_main:
+	CLR $ACC0
+	CLR $ACC1
+	SBCLR #2
+	SBCLR #3
+	SBCLR #4
+	SBCLR #5
+	SBCLR #6
+
+	LRI $AR0, #0
+
+	LRIS $AX0.H, #1
+	CALL send_back
+
+	SI @DMBH, #0x8888
+	SI @DMBL, #0x5371
+
+wait_cpu_read:
+	LRS $AC1.M, @DMBH
+	ANDCF $AC1.M, #0x8000
+	JLZ wait_cpu_read
+
+	CLR $ACC1
+second_loop:
+	INC $ACC1
+	CMPIS $AC1.M, #1
+	JNZ second_loop
+
+	SBSET #5
+	SBSET #6
+	LRI $AR0, #2
+	LRI $AR0, #3
+	LRI $AR0, #4
+	LRI $AR0, #5
+	LRI $AR0, #6
+
+	LRIS $AX0.H, #2
+	CALL send_back
+
+	JMP end_of_test
+
+external_irq:
+	INC $ACC0
+	INCM $AC0.M
+	LRIS $AX0.H, #3
+	CALL send_back
+
+	; Only trigger a nested interrupt the first time through.
+	CMPIS $AC0.M, #2
+	JGE exit_irq
+
+	SI @DMBH, #0x8888
+	SI @DMBL, #0x5371
+
+wait_cpu_read_irq:
+	LRS $AC1.M, @DMBH
+	ANDCF $AC1.M, #0x8000
+	JLZ wait_cpu_read_irq
+
+	CLR $ACC1
+	SBSET #6
+
+second_loop_irq:
+	INC $ACC1
+	CMPIS $AC1.M, #1
+	JNZ second_loop_irq
+
+exit_irq:
+	DEC $ACC0
+	RTI
+
+; Expected result ($AX0.H (send_back num), $AC0.L (interrupt depth), $AC0.M (interrupt count), $AR0, and $SR):
+; 1, 0, 0, 0, 2024
+; 3, 1, 1, 2, 2020
+; 3, 2, 2, 2, 2020
+; 2, 0, 2, 6, 3825
diff --git a/Source/DSPSpy/tests/external_interrupt_no_delay.ds b/Source/DSPSpy/tests/external_interrupt_no_delay.ds
index 549b499fe3..49239f4974 100644
--- a/Source/DSPSpy/tests/external_interrupt_no_delay.ds
+++ b/Source/DSPSpy/tests/external_interrupt_no_delay.ds
@@ -13,6 +13,10 @@ include "dsp_base_noirq.inc"
 
 test_main:
 	CLR $ACC0
+	CLR $ACC1
+	SBCLR #2
+	SBCLR #3
+	SBCLR #4
 	SBCLR #5
 	SBCLR #6
 
@@ -22,7 +26,7 @@ test_main:
 	CALL send_back
 
 	SI @DMBH, #0x8888
-	SI @DMBL, #0x1111
+	SI @DMBL, #0x5371
 
 wait_cpu_read:
 	LRS $AC1.M, @DMBH
@@ -55,3 +59,11 @@ external_irq:
 	LRIS $AX0.H, #3
 	CALL send_back
 	RTI
+
+; Expected result ($AX0.H (send_back num), $AR0, and $SR):
+; 1, 0, 2024 (start)
+; 3, 0, 2020 (in interrupt handler)
+; 2, 6, 3825 (end)
+; DSPSpy shows "interrupt after 21 ticks / 0 tries" (exact numbers vary)
+; $ACC1 in the interrupt handler is approximately 15 (so it loops 15 times
+; after the CPU receives the mail before the interrupt fires)
diff --git a/Source/DSPSpy/tests/external_interrupt_other_interrupt_on_return.ds b/Source/DSPSpy/tests/external_interrupt_other_interrupt_on_return.ds
index 4de8a91ade..f4bcad3ebc 100644
--- a/Source/DSPSpy/tests/external_interrupt_other_interrupt_on_return.ds
+++ b/Source/DSPSpy/tests/external_interrupt_other_interrupt_on_return.ds
@@ -38,7 +38,7 @@ test_main:
 	CALL send_back
 
 	SI @DMBH, #0x8888
-	SI @DMBL, #0x1111
+	SI @DMBL, #0x5371
 
 wait_cpu_read:
 	LRS $AC1.M, @DMBH
@@ -66,6 +66,7 @@ second_loop:
 	JMP end_of_test
 
 accov_irq:
+	INC $ACC0
 	INCM $AC0.M
 
 	; Restore registers, otherwise no new interrupt will be generated
@@ -76,10 +77,21 @@ accov_irq:
 	LRIS $AX0.H, #3
 	CALL send_back
 
+	DECM $AC0.M
 	RTI
 
 external_irq:
+	INC $ACC0
 	INCM $AC0.M
+
 	LRIS $AX0.H, #4
 	CALL send_back
+
+	DECM $AC0.M
 	RTI
+
+; Expected result ($AX0.H (send_back num), $AC0.L (interrupt count), $AC0.M (interrupt depth), $AR0, and $SR):
+; 1, 0, 0, 0, 2224 (start)
+; 3, 1, 1, 0, 2a20 (overflow interrupt)
+; 4, 2, 1, 3, 2a20 (external interrupt
+; 2, 2, 0, 6, 3a25 (end)
diff --git a/Source/DSPSpy/tests/external_interrupt_toggle.ds b/Source/DSPSpy/tests/external_interrupt_toggle.ds
index eec640bb0a..8fc255e126 100644
--- a/Source/DSPSpy/tests/external_interrupt_toggle.ds
+++ b/Source/DSPSpy/tests/external_interrupt_toggle.ds
@@ -13,6 +13,7 @@ include "dsp_base_noirq.inc"
 
 test_main:
 	CLR $ACC0
+	CLR $ACC1
 	SBCLR #5
 	SBCLR #6
 
@@ -22,7 +23,7 @@ test_main:
 	CALL send_back
 
 	SI @DMBH, #0x8888
-	SI @DMBL, #0x1111
+	SI @DMBL, #0x5371
 
 wait_cpu_read:
 	LRS $AC1.M, @DMBH
@@ -59,3 +60,8 @@ external_irq:
 	LRIS $AX0.H, #3
 	CALL send_back
 	RTI
+
+; Expected result ($AX0.H (send_back num), $AR0, and $SR):
+; 1, 0, 2224
+; 3, 2, 2a25
+; 2, 4, 3a25
diff --git a/Source/DSPSpy/tests/external_interrupt_toggle_2.ds b/Source/DSPSpy/tests/external_interrupt_toggle_2.ds
index cf91fa73f4..8a85f75ce5 100644
--- a/Source/DSPSpy/tests/external_interrupt_toggle_2.ds
+++ b/Source/DSPSpy/tests/external_interrupt_toggle_2.ds
@@ -13,6 +13,7 @@ include "dsp_base_noirq.inc"
 
 test_main:
 	CLR $ACC0
+	CLR $ACC1
 	SBCLR #5
 	SBCLR #6
 
@@ -22,7 +23,7 @@ test_main:
 	CALL send_back
 
 	SI @DMBH, #0x8888
-	SI @DMBL, #0x1111
+	SI @DMBL, #0x5371
 
 wait_cpu_read:
 	LRS $AC1.M, @DMBH
@@ -62,3 +63,8 @@ external_irq:
 	LRIS $AX0.H, #3
 	CALL send_back
 	RTI
+
+; Expected result ($AX0.H (send_back num), $AR0, and $SR):
+; 1, 0, 2224
+; 3, 6, 2a25
+; 2, 7, 3a25
diff --git a/Source/DSPSpy/tests/interrupt_nested.ds b/Source/DSPSpy/tests/interrupt_nested.ds
index 389ea7b96d..30975a7a11 100644
--- a/Source/DSPSpy/tests/interrupt_nested.ds
+++ b/Source/DSPSpy/tests/interrupt_nested.ds
@@ -25,6 +25,12 @@ test_main:
 	SI @ACEAH, #0
 	SI @ACEAL, #0
 
+	SBSET #2
+	SBSET #3
+	SBCLR #4
+	SBSET #5
+	SBSET #6
+
 	CLR $ACC0
 	CLR $ACC1
 	LRIS $AX0.H, #1
@@ -69,9 +75,9 @@ accov_irq:
 
 ; Expected output ($AX0.H (send_back number), $AX1.H (changed on lines after an exception fires,
 ; to make sure it happens immediately), $AC0.M (interrupt count), $AC1.M (interrupt depth), and $SR):
-; 1, 0, 0, 0, 2224 (first line)
-; 3, 0, 1, 1, 2220 (start of interrupt handler)
-; 3, 0, 2, 2, 2220 (nested start of interrupt handler)
-; 4, 2, 2, 2, 2221 (nested interrupt handler exits)
-; 4, 2, 2, 1, 2225 (interrupt handler exits)
-; 2, 1, 2, 0, 2224 (before end_of_test)
\ No newline at end of file
+; 1, 0, 0, 0, 3a24 (first line)
+; 3, 0, 1, 1, 2a20 (start of interrupt handler)
+; 3, 0, 2, 2, 2a20 (nested start of interrupt handler)
+; 4, 2, 2, 2, 2a21 (nested interrupt handler exits)
+; 4, 2, 2, 1, 2a25 (interrupt handler exits)
+; 2, 1, 2, 0, 3a24 (before end_of_test)
diff --git a/Source/DSPSpy/tests/interrupt_suppressed.ds b/Source/DSPSpy/tests/interrupt_suppressed.ds
index 6f80b3fe44..76fbe84477 100644
--- a/Source/DSPSpy/tests/interrupt_suppressed.ds
+++ b/Source/DSPSpy/tests/interrupt_suppressed.ds
@@ -25,6 +25,12 @@ test_main:
 	SI @ACEAH, #0
 	SI @ACEAL, #0
 
+	SBSET #2
+	SBSET #3
+	SBCLR #4
+	SBSET #5
+	SBSET #6
+
 	CLR $ACC0
 	CLR $ACC1
 
@@ -66,9 +72,9 @@ accov_irq:
 	RTI
 
 ; Expected output ($AC0.M (num interrupts), $AC1.M (send_back number), and $SR):
-; 0, 1, 2224 (start)
-; 1, 6, 2220 (in interrupt handler)
-; 1, 2, 2224 (out of interrupt handler)
-; 1, 3, 2024 (interrupts disabled)
-; 1, 4, 2024 (no interrupt triggered)
-; 1, 5, 2224 (interrupts enabled, still no interrupt triggered)
+; 0, 1, 3a24 (start)
+; 1, 6, 2a20 (in interrupt handler)
+; 1, 2, 3a24 (out of interrupt handler)
+; 1, 3, 3824 (interrupts disabled)
+; 1, 4, 3824 (no interrupt triggered)
+; 1, 5, 3a24 (interrupts enabled, still no interrupt triggered)
diff --git a/Source/DSPSpy/tests/interrupt_suppressed_nested_rti.ds b/Source/DSPSpy/tests/interrupt_suppressed_nested_rti.ds
index 9c5e31d572..b8d48a44e2 100644
--- a/Source/DSPSpy/tests/interrupt_suppressed_nested_rti.ds
+++ b/Source/DSPSpy/tests/interrupt_suppressed_nested_rti.ds
@@ -25,6 +25,12 @@ test_main:
 	SI @ACEAH, #0
 	SI @ACEAL, #0
 
+	SBSET #2
+	SBSET #3
+	SBCLR #4
+	SBSET #5
+	SBSET #6
+
 	CLR $ACC0
 	CLR $ACC1
 	LRIS $AX0.H, #1
@@ -67,7 +73,7 @@ accov_irq:
 
 ; Expected output ($AX0.H (send_back number), $AX1.H (changed on lines after an exception fires,
 ; to make sure it happens immediately), $AC0.M (interrupt count), $AC1.M (interrupt depth), and $SR):
-; 1, 0, 0, 0, 2224 (first line)
-; 3, 0, 1, 1, 2020 (start of interrupt handler)
-; 4, 2, 1, 1, 2020 (end of interrupt handler)
-; 2, 1, 1, 0, 2224 (before end_of_test)
+; 1, 0, 0, 0, 3a24 (first line)
+; 3, 0, 1, 1, 2820 (start of interrupt handler)
+; 4, 2, 1, 1, 2820 (end of interrupt handler)
+; 2, 1, 1, 0, 3a24 (before end_of_test)
diff --git a/Source/DSPSpy/tests/interrupt_suppressed_nested_sbset.ds b/Source/DSPSpy/tests/interrupt_suppressed_nested_sbset.ds
index 9db3080d57..d98e64089e 100644
--- a/Source/DSPSpy/tests/interrupt_suppressed_nested_sbset.ds
+++ b/Source/DSPSpy/tests/interrupt_suppressed_nested_sbset.ds
@@ -25,6 +25,12 @@ test_main:
 	SI @ACEAH, #0
 	SI @ACEAL, #0
 
+	SBSET #2
+	SBSET #3
+	SBCLR #4
+	SBSET #5
+	SBSET #6
+
 	CLR $ACC0
 	CLR $ACC1
 	LRIS $AX0.H, #1
@@ -74,8 +80,8 @@ accov_irq:
 
 ; Expected output ($AX0.H (send_back number), $AX1.H (changed on lines after an exception fires,
 ; to make sure it happens immediately), $AC0.M (interrupt count), $AC1.M (interrupt depth), and $SR):
-; 1, 0, 0, 0, 2224 (first line)
-; 3, 0, 1, 1, 2020 (start of interrupt handler)
-; 4, 2, 1, 1, 2020 (middle of interrupt handler)
-; 5, 3, 1, 1, 2220 (end of interrupt handler)
-; 2, 1, 1, 0, 2224 (before end_of_test)
+; 1, 0, 0, 0, 3a24 (first line)
+; 3, 0, 1, 1, 2820 (start of interrupt handler)
+; 4, 2, 1, 1, 2820 (middle of interrupt handler)
+; 5, 3, 1, 1, 2a20 (end of interrupt handler)
+; 2, 1, 1, 0, 3a24 (before end_of_test)