diff --git a/Source/Core/Common/Src/ArmEmitter.cpp b/Source/Core/Common/Src/ArmEmitter.cpp
index 2788760c6d..e9102f20cf 100644
--- a/Source/Core/Common/Src/ArmEmitter.cpp
+++ b/Source/Core/Common/Src/ArmEmitter.cpp
@@ -1154,7 +1154,10 @@ void ARMXEmitter::VMOV(ARMReg Dest, ARMReg Src)
 			else
 			{
 				// Move 64bit from Arm reg
-				_dbg_assert_msg_(DYNA_REC, false, "This VMOV doesn't support moving 64bit ARM to NEON");
+				ARMReg Src2 = (ARMReg)(Src + 1);
+				Dest = (ARMReg)(Dest - S0); 
+				Write32(condition | (0xC4 << 20) | (Src2 << 16) | (Src << 12) \
+						| (0xB << 8) | ((Dest & 0x10) << 1) | (1 << 4) | ((Dest & 0xF) >> 1)); 
 				return;
 			}
 		}
diff --git a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStoreFloating.cpp b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStoreFloating.cpp
index 14a9786cc2..178007f5b3 100644
--- a/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStoreFloating.cpp
+++ b/Source/Core/Core/Src/PowerPC/JitArm32/JitArm_LoadStoreFloating.cpp
@@ -61,6 +61,9 @@ void JitArm::lfs(UGeckoInstruction inst)
 
 	ARMReg v0 = fpr.R0(inst.FD);
 	ARMReg v1 = fpr.R1(inst.FD);
+#if !defined(__ARM_PCS_VFP) // SoftFP returns in R0
+	VMOV(S0, R0);	
+#endif
 
 	VCVT(v0, S0, 0);
 	VCVT(v1, S0, 0);
@@ -98,8 +101,12 @@ void JitArm::lfd(UGeckoInstruction inst)
 	BL(rA);
 
 	ARMReg v0 = fpr.R0(inst.FD);
-
+#if !defined(__ARM_PCS_VFP) // SoftFP returns in R0 and R1
+	VMOV(v0, R0);
+#else
 	VMOV(v0, D0);
+#endif
+
 	POP(4, R0, R1, R2, R3);
 
 	gpr.Unlock(rA, rB);