diff --git a/Source/DSPSpy/main_spy.cpp b/Source/DSPSpy/main_spy.cpp
index ed97055d4d..a154997f49 100644
--- a/Source/DSPSpy/main_spy.cpp
+++ b/Source/DSPSpy/main_spy.cpp
@@ -455,8 +455,8 @@ void handle_dsp_mail(void)
     {
       real_dsp.SetInterrupt(false);
       real_dsp.SendMailTo(real_dsp.CheckInterrupt() ? 0x99995372 : 0x99995370);
-      while (real_dsp.CheckMailTo())
-        ;
+      //while (real_dsp.CheckMailTo())
+      //  ;
     }
     else if (mail == 0x88885372)
     {
diff --git a/Source/DSPSpy/tests/external_interrupt_status_bits.ds b/Source/DSPSpy/tests/external_interrupt_status_bits.ds
index 3871cd0827..58aa2cbd57 100644
--- a/Source/DSPSpy/tests/external_interrupt_status_bits.ds
+++ b/Source/DSPSpy/tests/external_interrupt_status_bits.ds
@@ -1,19 +1,87 @@
+; This test needs to manually specify IRQs
+	jmp		irq0
+	jmp		irq1
+	jmp		irq2
+	jmp		irq3
+	jmp		irq4
+	jmp		irq5
+	jmp		irq6
+	jmp		external_irq
+
 incdir  "tests"
-include "dsp_base.inc"
+include "dsp_base_noirq.inc"
 
 test_main:
 	CLR $ACC0
 	CLR $ACC1
 
+	;SBCLR #2
+	;SBCLR #3
+	;SBCLR #4
+	;SBCLR #5
+	;SBCLR #6
+
+	; We store a copy of $SR in $AR0.
+	;MRR $AR0, $SR
+	; $IX0 is set to SR_100, so we can add it to $AR0 repeatedly to cycle through $SR bits.
+	;LRI $IX0, #0x0100
+	; Subtract $IX0 from $AR0, so that we can add it the first time to get $SR
+	; (and have $AR0 always match $SR instead of overflowing)
+	;SUBARN $AR0
+
 	LRIS $AX0.H, #1
 	CALL send_back
 
+	; We're checking 5 bits in $sr, so 1 << 5 or 0x20 times.
+	;BLOOPI #0x20, main_loop_last_ins
+		CLR $ACC0
+		ADDARN $AR0, $IX0
+		MRR $SR, $AR0
+
+		; Tell the CPU to set the external interrupt
+		SI @DMBH, #0x8888
+		SI @DMBL, #0x5372
+		SI @DIRQ, #0x0001
+
+		; Wait for CPU
+wait_cpu_read_1a:
+		LRS $AC1.M, @DMBH
+		ANDCF $AC1.M, #0x8000
+		JLZ wait_cpu_read_1a
+wait_cpu_read_1b:
+		LRS $AC1.M, @CMBH
+		ANDCF $AC1.M, #0x8000
+		JLZ wait_cpu_read_1b
+
+		LRIS $AX0.H, #2
+		;CALL send_back
+
+		; Tell the CPU to un-set the external interrupt
+		SI @DMBH, #0x8888
+		SI @DMBL, #0x5370
+		SI @DIRQ, #0x0001
+
+wait_cpu_read_2a:
+		LRS $AC1.M, @DMBH
+		ANDCF $AC1.M, #0x8000
+		JLZ wait_cpu_read_2a
+wait_cpu_read_2b:
+		LRS $AC1.M, @CMBH
+		ANDCF $AC1.M, #0x8000
+		JLZ wait_cpu_read_2b
+
+		LRIS $AX0.H, #3
+		;CALL send_back
+
+		NOP
+main_loop_last_ins:
+		NOP
 
 	JMP end_of_test
 
 external_irq:
 	INC $ACC0
-	; LRIS $AX0.H, #3
+	; LRIS $AX0.H, #4
 	; CALL send_back
 	RTI