mirrors/dolphin
0
0
Fork 0
mirror of https://github.com/dolphin-emu/dolphin.git synced 2025-08-19 16:59:13 +00:00
Code Issues Projects Releases Packages Wiki Activity Actions

Common/Assert: Switch to fmt

Browse source
This commit is contained in:
Pokechu22 2021-11-10 14:42:49 -08:00
commit 44e93e91d7
27 changed files with 234 additions and 237 deletions
Download patch file Download diff file Expand all files Collapse all files

2
Source/Core/Core/PowerPC/Interpreter/Interpreter.cpp
View file

@ -340,7 +340,7 @@ void Interpreter::unknown_instruction(UGeckoInstruction inst)
i + 1, rGPR[i + 1], i + 2, rGPR[i + 2], i + 3, rGPR[i + 3]);
}
ASSERT_MSG(POWERPC, 0,
"\nIntCPU: Unknown instruction %08x at PC = %08x last_PC = %08x LR = %08x\n",
"\nIntCPU: Unknown instruction {:08x} at PC = {:08x} last_PC = {:08x} LR = {:08x}\n",
inst.hex, PC, last_pc, LR);
}

2
Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp
View file

@ -341,7 +341,7 @@ void Interpreter::mtspr(UGeckoInstruction inst)
break;
case SPR_WPAR:
ASSERT_MSG(POWERPC, rGPR[inst.RD] == 0x0C008000, "Gather pipe @ %08x", PC);
ASSERT_MSG(POWERPC, rGPR[inst.RD] == 0x0C008000, "Gather pipe @ {:08x}", PC);
GPFifo::ResetGatherPipe();
break;

2
Source/Core/Core/PowerPC/Jit64/Jit.cpp
View file

@ -1142,7 +1142,7 @@ bool Jit64::DoJit(u32 em_address, JitBlock* b, u32 nextPC)
// it.
FixupBranch memException;
ASSERT_MSG(DYNA_REC, !(js.fastmemLoadStore && js.fixupExceptionHandler),
"Fastmem loadstores shouldn't have exception handler fixups (PC=%x)!",
"Fastmem loadstores shouldn't have exception handler fixups (PC={:x})!",
op.address);
if (!js.fastmemLoadStore && !js.fixupExceptionHandler)
{

4
Source/Core/Core/PowerPC/Jit64/RegCache/FPURegCache.cpp
View file

@ -15,13 +15,13 @@ FPURegCache::FPURegCache(Jit64& jit) : RegCache{jit}
void FPURegCache::StoreRegister(preg_t preg, const OpArg& new_loc)
{
ASSERT_MSG(DYNA_REC, m_regs[preg].IsBound(), "Unbound register - %zu", preg);
ASSERT_MSG(DYNA_REC, m_regs[preg].IsBound(), "Unbound register - {}", preg);
m_emitter->MOVAPD(new_loc, m_regs[preg].Location()->GetSimpleReg());
}
void FPURegCache::LoadRegister(preg_t preg, X64Reg new_loc)
{
ASSERT_MSG(DYNA_REC, !m_regs[preg].IsDiscarded(), "Discarded register - %zu", preg);
ASSERT_MSG(DYNA_REC, !m_regs[preg].IsDiscarded(), "Discarded register - {}", preg);
m_emitter->MOVAPD(new_loc, m_regs[preg].Location().value());
}

4
Source/Core/Core/PowerPC/Jit64/RegCache/GPRRegCache.cpp
View file

@ -15,13 +15,13 @@ GPRRegCache::GPRRegCache(Jit64& jit) : RegCache{jit}
void GPRRegCache::StoreRegister(preg_t preg, const OpArg& new_loc)
{
ASSERT_MSG(DYNA_REC, !m_regs[preg].IsDiscarded(), "Discarded register - %zu", preg);
ASSERT_MSG(DYNA_REC, !m_regs[preg].IsDiscarded(), "Discarded register - {}", preg);
m_emitter->MOV(32, new_loc, m_regs[preg].Location().value());
}
void GPRRegCache::LoadRegister(preg_t preg, X64Reg new_loc)
{
ASSERT_MSG(DYNA_REC, !m_regs[preg].IsDiscarded(), "Discarded register - %zu", preg);
ASSERT_MSG(DYNA_REC, !m_regs[preg].IsDiscarded(), "Discarded register - {}", preg);
m_emitter->MOV(32, ::Gen::R(new_loc), m_regs[preg].Location().value());
}

29
Source/Core/Core/PowerPC/Jit64/RegCache/JitRegCache.cpp
View file

@ -389,9 +389,10 @@ void RegCache::Discard(BitSet32 pregs)
for (preg_t i : pregs)
{
ASSERT_MSG(DYNA_REC, !m_regs[i].IsLocked(),
"Someone forgot to unlock PPC reg %zu (X64 reg %i).", i, RX(i));
ASSERT_MSG(DYNA_REC, !m_regs[i].IsRevertable(), "Register transaction is in progress!");
ASSERT_MSG(DYNA_REC, !m_regs[i].IsLocked(), "Someone forgot to unlock PPC reg {} (X64 reg {}).",
i, RX(i));
ASSERT_MSG(DYNA_REC, !m_regs[i].IsRevertable(), "Register transaction is in progress for {}!",
i);
if (m_regs[i].IsBound())
{
@ -412,9 +413,10 @@ void RegCache::Flush(BitSet32 pregs)
for (preg_t i : pregs)
{
ASSERT_MSG(DYNA_REC, !m_regs[i].IsLocked(),
"Someone forgot to unlock PPC reg %zu (X64 reg %i).", i, RX(i));
ASSERT_MSG(DYNA_REC, !m_regs[i].IsRevertable(), "Register transaction is in progress!");
ASSERT_MSG(DYNA_REC, !m_regs[i].IsLocked(), "Someone forgot to unlock PPC reg {} (X64 reg {}).",
i, RX(i));
ASSERT_MSG(DYNA_REC, !m_regs[i].IsRevertable(), "Register transaction is in progress for {}!",
i);
switch (m_regs[i].GetLocationType())
{
@ -496,7 +498,7 @@ BitSet32 RegCache::RegistersInUse() const
void RegCache::FlushX(X64Reg reg)
{
ASSERT_MSG(DYNA_REC, reg < m_xregs.size(), "Flushing non-existent reg %i", reg);
ASSERT_MSG(DYNA_REC, reg < m_xregs.size(), "Flushing non-existent reg {}", reg);
ASSERT(!m_xregs[reg].IsLocked());
if (!m_xregs[reg].IsFree())
{
@ -520,7 +522,7 @@ void RegCache::BindToRegister(preg_t i, bool doLoad, bool makeDirty)
{
X64Reg xr = GetFreeXReg();
ASSERT_MSG(DYNA_REC, !m_xregs[xr].IsDirty(), "Xreg %i already dirty", xr);
ASSERT_MSG(DYNA_REC, !m_xregs[xr].IsDirty(), "Xreg {} already dirty", xr);
ASSERT_MSG(DYNA_REC, !m_xregs[xr].IsLocked(), "GetFreeXReg returned locked register");
ASSERT_MSG(DYNA_REC, !m_regs[i].IsRevertable(), "Invalid transaction state");
@ -537,7 +539,7 @@ void RegCache::BindToRegister(preg_t i, bool doLoad, bool makeDirty)
[xr](const auto& r) {
return r.Location().has_value() && r.Location()->IsSimpleReg(xr);
}),
"Xreg %i already bound", xr);
"Xreg {} already bound", xr);
m_regs[i].SetBoundTo(xr);
}
@ -549,13 +551,14 @@ void RegCache::BindToRegister(preg_t i, bool doLoad, bool makeDirty)
m_xregs[RX(i)].MakeDirty();
}
ASSERT_MSG(DYNA_REC, !m_xregs[RX(i)].IsLocked(), "WTF, this reg should have been flushed");
ASSERT_MSG(DYNA_REC, !m_xregs[RX(i)].IsLocked(),
"WTF, this reg ({} -> {}) should have been flushed", i, RX(i));
}
void RegCache::StoreFromRegister(preg_t i, FlushMode mode)
{
// When a transaction is in progress, allowing the store would overwrite the old value.
ASSERT_MSG(DYNA_REC, !m_regs[i].IsRevertable(), "Register transaction is in progress!");
ASSERT_MSG(DYNA_REC, !m_regs[i].IsRevertable(), "Register transaction on {} is in progress!", i);
bool doStore = false;
@ -673,13 +676,13 @@ float RegCache::ScoreRegister(X64Reg xreg) const
const OpArg& RegCache::R(preg_t preg) const
{
ASSERT_MSG(DYNA_REC, !m_regs[preg].IsDiscarded(), "Discarded register - %zu", preg);
ASSERT_MSG(DYNA_REC, !m_regs[preg].IsDiscarded(), "Discarded register - {}", preg);
return m_regs[preg].Location().value();
}
X64Reg RegCache::RX(preg_t preg) const
{
ASSERT_MSG(DYNA_REC, m_regs[preg].IsBound(), "Unbound register - %zu", preg);
ASSERT_MSG(DYNA_REC, m_regs[preg].IsBound(), "Unbound register - {}", preg);
return m_regs[preg].Location()->GetSimpleReg();
}

6
Source/Core/Core/PowerPC/JitArm64/JitArm64_RegCache.cpp
View file

@ -90,8 +90,7 @@ void Arm64RegCache::LockRegister(ARM64Reg host_reg)
{
auto reg = std::find(m_host_registers.begin(), m_host_registers.end(), host_reg);
ASSERT_MSG(DYNA_REC, reg != m_host_registers.end(),
"Don't try locking a register that isn't in the cache. Reg %d",
static_cast<int>(host_reg));
"Don't try locking a register that isn't in the cache. Reg {}", host_reg);
reg->Lock();
}
@ -99,8 +98,7 @@ void Arm64RegCache::UnlockRegister(ARM64Reg host_reg)
{
auto reg = std::find(m_host_registers.begin(), m_host_registers.end(), host_reg);
ASSERT_MSG(DYNA_REC, reg != m_host_registers.end(),
"Don't try unlocking a register that isn't in the cache. Reg %d",
static_cast<int>(host_reg));
"Don't try unlocking a register that isn't in the cache. Reg {}", host_reg);
reg->Unlock();
}

4
Source/Core/Core/PowerPC/JitArm64/Jit_Util.cpp
View file

@ -48,7 +48,7 @@ private:
m_emit->STR(IndexType::Unsigned, reg, ARM64Reg::X0, 0);
break;
default:
ASSERT_MSG(DYNA_REC, false, "Unknown size %d passed to MMIOWriteCodeGenerator!", sbits);
ASSERT_MSG(DYNA_REC, false, "Unknown size {} passed to MMIOWriteCodeGenerator!", sbits);
break;
}
}
@ -141,7 +141,7 @@ private:
m_emit->LDR(IndexType::Unsigned, m_dst_reg, ARM64Reg::X0, 0);
break;
default:
ASSERT_MSG(DYNA_REC, false, "Unknown size %d passed to MMIOReadCodeGenerator!", sbits);
ASSERT_MSG(DYNA_REC, false, "Unknown size {} passed to MMIOReadCodeGenerator!", sbits);
break;
}
}

9
Source/Core/Core/PowerPC/PPCTables.cpp
View file

@ -52,7 +52,7 @@ GekkoOPInfo* GetOpInfo(UGeckoInstruction inst)
case 63:
return m_infoTable63[inst.SUBOP10];
default:
ASSERT_MSG(POWERPC, 0, "GetOpInfo - invalid subtable op %08x @ %08x", inst.hex, PC);
ASSERT_MSG(POWERPC, 0, "GetOpInfo - invalid subtable op {:08x} @ {:08x}", inst.hex, PC);
return nullptr;
}
}
@ -60,7 +60,7 @@ GekkoOPInfo* GetOpInfo(UGeckoInstruction inst)
{
if (info->type == OpType::Invalid)
{
ASSERT_MSG(POWERPC, 0, "GetOpInfo - invalid op %08x @ %08x", inst.hex, PC);
ASSERT_MSG(POWERPC, 0, "GetOpInfo - invalid op {:08x} @ {:08x}", inst.hex, PC);
return nullptr;
}
return m_infoTable[inst.OPCD];
@ -85,7 +85,8 @@ Interpreter::Instruction GetInterpreterOp(UGeckoInstruction inst)
case 63:
return Interpreter::m_op_table63[inst.SUBOP10];
default:
ASSERT_MSG(POWERPC, 0, "GetInterpreterOp - invalid subtable op %08x @ %08x", inst.hex, PC);
ASSERT_MSG(POWERPC, 0, "GetInterpreterOp - invalid subtable op {:08x} @ {:08x}", inst.hex,
PC);
return nullptr;
}
}
@ -93,7 +94,7 @@ Interpreter::Instruction GetInterpreterOp(UGeckoInstruction inst)
{
if (info->type == OpType::Invalid)
{
ASSERT_MSG(POWERPC, 0, "GetInterpreterOp - invalid op %08x @ %08x", inst.hex, PC);
ASSERT_MSG(POWERPC, 0, "GetInterpreterOp - invalid op {:08x} @ {:08x}", inst.hex, PC);
return nullptr;
}
return Interpreter::m_op_table[inst.OPCD];

2
Source/Core/Core/PowerPC/PowerPC.cpp
View file

@ -600,7 +600,7 @@ void CheckExternalExceptions()
}
else
{
DEBUG_ASSERT_MSG(POWERPC, 0, "Unknown EXT interrupt: Exceptions == %08x", exceptions);
DEBUG_ASSERT_MSG(POWERPC, 0, "Unknown EXT interrupt: Exceptions == {:08x}", exceptions);
ERROR_LOG_FMT(POWERPC, "Unknown EXTERNAL INTERRUPT exception: Exceptions == {:08x}",
exceptions);
}