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https://github.com/dolphin-emu/dolphin.git
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Arm64Emitter: Add CSSC instruction emitters
This commit is contained in:
Sintendo
parent
4835e620c3
commit
47bc36d319
2 changed files with 143 additions and 35 deletions
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@ -16,6 +16,7 @@
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#include "Common/Align.h"
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#include "Common/Assert.h"
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#include "Common/CPUDetect.h"
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#include "Common/CommonTypes.h"
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#include "Common/MathUtil.h"
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#include "Common/SmallVector.h"
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@ -204,24 +205,9 @@ static const u32 Data1SrcEnc[][2] = {
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{0, 3}, // REV64
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{0, 4}, // CLZ
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{0, 5}, // CLS
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};
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// Data-Processing (2 source)
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static const u32 Data2SrcEnc[] = {
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0x02, // UDIV
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0x03, // SDIV
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0x08, // LSLV
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0x09, // LSRV
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0x0A, // ASRV
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0x0B, // RORV
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0x10, // CRC32B
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0x11, // CRC32H
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0x12, // CRC32W
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0x14, // CRC32CB
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0x15, // CRC32CH
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0x16, // CRC32CW
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0x13, // CRC32X (64bit Only)
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0x17, // XRC32CX (64bit Only)
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{0, 6}, // CTZ
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{0, 7}, // CNT
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{0, 8}, // ABS
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};
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// Data-Processing (3 source)
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@ -409,14 +395,22 @@ void ARM64XEmitter::EncodeData1SrcInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn)
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(Data1SrcEnc[instenc][1] << 10) | (DecodeReg(Rn) << 5) | DecodeReg(Rd));
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}
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void ARM64XEmitter::EncodeData2SrcInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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void ARM64XEmitter::EncodeData2SrcInst(Data2SrcEnc instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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bool b64Bit = Is64Bit(Rd);
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Write32((b64Bit << 31) | (0x0D6 << 21) | (DecodeReg(Rm) << 16) | (Data2SrcEnc[instenc] << 10) |
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Write32((b64Bit << 31) | (0x0D6 << 21) | (DecodeReg(Rm) << 16) | (u32(instenc) << 10) |
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(DecodeReg(Rn) << 5) | DecodeReg(Rd));
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}
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void ARM64XEmitter::EncodeDataCSSCImmInst(DataCSSCImm8Enc opc, ARM64Reg Rd, ARM64Reg Rn, u8 imm)
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{
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bool b64Bit = Is64Bit(Rd);
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Write32((b64Bit << 31) | (0x47 << 22) | (u32(opc) << 18) | (imm << 10) | (DecodeReg(Rn) << 5) |
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DecodeReg(Rd));
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}
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void ARM64XEmitter::EncodeData3SrcInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm,
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ARM64Reg Ra)
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{
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@ -1180,59 +1174,59 @@ void ARM64XEmitter::CLS(ARM64Reg Rd, ARM64Reg Rn)
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// Data-Processing 2 source
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void ARM64XEmitter::UDIV(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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EncodeData2SrcInst(0, Rd, Rn, Rm);
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EncodeData2SrcInst(Data2SrcEnc::UDIV, Rd, Rn, Rm);
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}
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void ARM64XEmitter::SDIV(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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EncodeData2SrcInst(1, Rd, Rn, Rm);
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EncodeData2SrcInst(Data2SrcEnc::SDIV, Rd, Rn, Rm);
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}
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void ARM64XEmitter::LSLV(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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EncodeData2SrcInst(2, Rd, Rn, Rm);
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EncodeData2SrcInst(Data2SrcEnc::LSLV, Rd, Rn, Rm);
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}
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void ARM64XEmitter::LSRV(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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EncodeData2SrcInst(3, Rd, Rn, Rm);
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EncodeData2SrcInst(Data2SrcEnc::LSRV, Rd, Rn, Rm);
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}
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void ARM64XEmitter::ASRV(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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EncodeData2SrcInst(4, Rd, Rn, Rm);
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EncodeData2SrcInst(Data2SrcEnc::ASRV, Rd, Rn, Rm);
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}
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void ARM64XEmitter::RORV(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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EncodeData2SrcInst(5, Rd, Rn, Rm);
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EncodeData2SrcInst(Data2SrcEnc::RORV, Rd, Rn, Rm);
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}
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void ARM64XEmitter::CRC32B(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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EncodeData2SrcInst(6, Rd, Rn, Rm);
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EncodeData2SrcInst(Data2SrcEnc::CRC32B, Rd, Rn, Rm);
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}
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void ARM64XEmitter::CRC32H(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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EncodeData2SrcInst(7, Rd, Rn, Rm);
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EncodeData2SrcInst(Data2SrcEnc::CRC32H, Rd, Rn, Rm);
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}
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void ARM64XEmitter::CRC32W(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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EncodeData2SrcInst(8, Rd, Rn, Rm);
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EncodeData2SrcInst(Data2SrcEnc::CRC32W, Rd, Rn, Rm);
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}
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void ARM64XEmitter::CRC32CB(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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EncodeData2SrcInst(9, Rd, Rn, Rm);
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EncodeData2SrcInst(Data2SrcEnc::CRC32CB, Rd, Rn, Rm);
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}
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void ARM64XEmitter::CRC32CH(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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EncodeData2SrcInst(10, Rd, Rn, Rm);
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EncodeData2SrcInst(Data2SrcEnc::CRC32CH, Rd, Rn, Rm);
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}
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void ARM64XEmitter::CRC32CW(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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EncodeData2SrcInst(11, Rd, Rn, Rm);
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EncodeData2SrcInst(Data2SrcEnc::CRC32CW, Rd, Rn, Rm);
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}
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void ARM64XEmitter::CRC32X(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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EncodeData2SrcInst(12, Rd, Rn, Rm);
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EncodeData2SrcInst(Data2SrcEnc::CRC32X, Rd, Rn, Rm);
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}
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void ARM64XEmitter::CRC32CX(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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EncodeData2SrcInst(13, Rd, Rn, Rm);
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EncodeData2SrcInst(Data2SrcEnc::CRC32CX, Rd, Rn, Rm);
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}
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// Data-Processing 3 source
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@ -1775,6 +1769,74 @@ void ARM64XEmitter::ADRP(ARM64Reg Rd, s64 imm)
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EncodeAddressInst(1, Rd, static_cast<s32>(imm >> 12));
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}
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// Common Short Sequence Compression (CSSC) instructions
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void ARM64XEmitter::ABS(ARM64Reg Rd, ARM64Reg Rn)
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{
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if (!cpu_info.bCSSC)
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PanicAlertFmt("Trying to use CSSC on a system that doesn't support it. Bad programmer.");
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EncodeData1SrcInst(8, Rd, Rn);
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}
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void ARM64XEmitter::CNT(ARM64Reg Rd, ARM64Reg Rn)
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{
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if (!cpu_info.bCSSC)
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PanicAlertFmt("Trying to use CSSC on a system that doesn't support it. Bad programmer.");
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EncodeData1SrcInst(7, Rd, Rn);
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}
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void ARM64XEmitter::CTZ(ARM64Reg Rd, ARM64Reg Rn)
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{
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if (!cpu_info.bCSSC)
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PanicAlertFmt("Trying to use CSSC on a system that doesn't support it. Bad programmer.");
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EncodeData1SrcInst(6, Rd, Rn);
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}
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void ARM64XEmitter::SMIN(ARM64Reg Rd, ARM64Reg Rn, s8 imm)
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{
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if (!cpu_info.bCSSC)
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PanicAlertFmt("Trying to use CSSC on a system that doesn't support it. Bad programmer.");
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EncodeDataCSSCImmInst(DataCSSCImm8Enc::SMIN, Rd, Rn, static_cast<u8>(imm));
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}
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void ARM64XEmitter::SMIN(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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if (!cpu_info.bCSSC)
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PanicAlertFmt("Trying to use CSSC on a system that doesn't support it. Bad programmer.");
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EncodeData2SrcInst(Data2SrcEnc::SMIN, Rd, Rn, Rm);
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}
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void ARM64XEmitter::SMAX(ARM64Reg Rd, ARM64Reg Rn, s8 imm)
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{
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if (!cpu_info.bCSSC)
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PanicAlertFmt("Trying to use CSSC on a system that doesn't support it. Bad programmer.");
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EncodeDataCSSCImmInst(DataCSSCImm8Enc::SMAX, Rd, Rn, static_cast<u8>(imm));
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}
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void ARM64XEmitter::SMAX(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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if (!cpu_info.bCSSC)
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PanicAlertFmt("Trying to use CSSC on a system that doesn't support it. Bad programmer.");
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EncodeData2SrcInst(Data2SrcEnc::SMAX, Rd, Rn, Rm);
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}
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void ARM64XEmitter::UMIN(ARM64Reg Rd, ARM64Reg Rn, u8 imm)
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{
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if (!cpu_info.bCSSC)
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PanicAlertFmt("Trying to use CSSC on a system that doesn't support it. Bad programmer.");
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EncodeDataCSSCImmInst(DataCSSCImm8Enc::UMIN, Rd, Rn, static_cast<u8>(imm));
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}
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void ARM64XEmitter::UMIN(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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if (!cpu_info.bCSSC)
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PanicAlertFmt("Trying to use CSSC on a system that doesn't support it. Bad programmer.");
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EncodeData2SrcInst(Data2SrcEnc::UMIN, Rd, Rn, Rm);
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}
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void ARM64XEmitter::UMAX(ARM64Reg Rd, ARM64Reg Rn, u8 imm)
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{
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if (!cpu_info.bCSSC)
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PanicAlertFmt("Trying to use CSSC on a system that doesn't support it. Bad programmer.");
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EncodeDataCSSCImmInst(DataCSSCImm8Enc::UMAX, Rd, Rn, static_cast<u8>(imm));
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}
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void ARM64XEmitter::UMAX(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm)
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{
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if (!cpu_info.bCSSC)
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PanicAlertFmt("Trying to use CSSC on a system that doesn't support it. Bad programmer.");
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EncodeData2SrcInst(Data2SrcEnc::UMAX, Rd, Rn, Rm);
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}
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// This is using a hand-rolled algorithm. The goal is zero memory allocations, not necessarily
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// the best JIT-time time complexity. (The number of moves is usually very small.)
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void ARM64XEmitter::ParallelMoves(RegisterMove* begin, RegisterMove* end,
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@ -624,6 +624,38 @@ private:
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// Must be cleared with SetCodePtr() afterwards.
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bool m_write_failed = false;
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// Data-Processing (2 source)
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enum class Data2SrcEnc : u32
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{
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UDIV = 0x02,
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SDIV = 0x03,
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LSLV = 0x08,
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LSRV = 0x09,
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ASRV = 0x0A,
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RORV = 0x0B,
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CRC32B = 0x10,
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CRC32H = 0x11,
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CRC32W = 0x12,
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CRC32CB = 0x14,
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CRC32CH = 0x15,
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CRC32CW = 0x16,
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CRC32X = 0x13, // 64-bit only
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CRC32CX = 0x17, // 64-bit only
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// CSSC
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SMAX = 0x18,
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UMAX = 0x19,
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SMIN = 0x1A,
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UMIN = 0x1B,
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};
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enum class DataCSSCImm8Enc : u8
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{
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SMAX = 0b0000,
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UMAX = 0b0001,
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SMIN = 0b0010,
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UMIN = 0b0011,
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};
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void AddImmediate(ARM64Reg Rd, ARM64Reg Rn, u64 imm, bool shift, bool negative, bool flags);
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void EncodeCompareBranchInst(u32 op, ARM64Reg Rt, const void* ptr);
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void EncodeTestBranchInst(u32 op, ARM64Reg Rt, u8 bits, const void* ptr);
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@ -638,7 +670,7 @@ private:
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void EncodeCondCompareRegInst(u32 op, ARM64Reg Rn, ARM64Reg Rm, u32 nzcv, CCFlags cond);
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void EncodeCondSelectInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, CCFlags cond);
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void EncodeData1SrcInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn);
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void EncodeData2SrcInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void EncodeData2SrcInst(Data2SrcEnc instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void EncodeData3SrcInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ARM64Reg Ra);
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void EncodeLogicalInst(u32 instenc, ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm, ArithOption Shift);
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void EncodeLoadRegisterInst(u32 bitop, ARM64Reg Rt, u32 imm);
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@ -655,6 +687,7 @@ private:
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s32 imm);
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void EncodeAddressInst(u32 op, ARM64Reg Rd, s32 imm);
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void EncodeLoadStoreUnscaled(u32 size, u32 op, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
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void EncodeDataCSSCImmInst(DataCSSCImm8Enc opc, ARM64Reg Rd, ARM64Reg Rn, u8 imm);
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[[nodiscard]] FixupBranch WriteFixupBranch();
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@ -1021,6 +1054,19 @@ public:
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void ADR(ARM64Reg Rd, s32 imm);
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void ADRP(ARM64Reg Rd, s64 imm);
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// Common Short Sequence Compression (CSSC) instructions
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void ABS(ARM64Reg Rd, ARM64Reg Rn);
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void CNT(ARM64Reg Rd, ARM64Reg Rn);
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void CTZ(ARM64Reg Rd, ARM64Reg Rn);
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void SMIN(ARM64Reg Rd, ARM64Reg Rn, s8 imm);
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void SMIN(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void SMAX(ARM64Reg Rd, ARM64Reg Rn, s8 imm);
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void SMAX(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void UMIN(ARM64Reg Rd, ARM64Reg Rn, u8 imm);
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void UMIN(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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void UMAX(ARM64Reg Rd, ARM64Reg Rn, u8 imm);
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void UMAX(ARM64Reg Rd, ARM64Reg Rn, ARM64Reg Rm);
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// Wrapper around ADR/ADRP/MOVZ/MOVN/MOVK
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void MOVI2R(ARM64Reg Rd, u64 imm);
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bool MOVI2R2(ARM64Reg Rd, u64 imm1, u64 imm2);
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