From 7bf50663b20e2a0307476a071c7bdb1797abc4e9 Mon Sep 17 00:00:00 2001 From: JosJuice Date: Sun, 29 Dec 2024 21:18:09 +0100 Subject: [PATCH] JitArm64: Stop encoding EmitBackpatchRoutine addr as 64-bit There's no reason why this register should be 64-bit. It always contains a 32-bit value, since guest addresses are 32-bit. --- Source/Core/Core/PowerPC/JitArm64/Jit.h | 10 +++---- .../PowerPC/JitArm64/JitArm64_LoadStore.cpp | 28 ++++++++----------- .../JitArm64/JitArm64_LoadStoreFloating.cpp | 18 +++++------- .../JitArm64/JitArm64_LoadStorePaired.cpp | 6 ++-- Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp | 4 +-- 5 files changed, 28 insertions(+), 38 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/Jit.h b/Source/Core/Core/PowerPC/JitArm64/Jit.h index f1eb73e160..67ef2ff621 100644 --- a/Source/Core/Core/PowerPC/JitArm64/Jit.h +++ b/Source/Core/Core/PowerPC/JitArm64/Jit.h @@ -253,11 +253,11 @@ protected: // Registers used: // // addr - // Store: X2 - // Load: X1 - // Zero 256: X1 - // Store float: X2 - // Load float: X1 + // Store: W2 + // Load: W1 + // Zero 256: W1 + // Store float: W2 + // Load float: W1 // // If mode == AlwaysFastAccess, the addr argument can be any register. // Otherwise it must be the register listed in the table above. diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp index 815174db63..e5dda05dcd 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp @@ -107,12 +107,10 @@ void JitArm64::SafeLoadToReg(u32 dest, s32 addr, s32 offsetReg, u32 flags, s32 o } } - ARM64Reg XA = EncodeRegTo64(addr_reg); - bool addr_reg_set = !is_immediate; const auto set_addr_reg_if_needed = [&] { if (!addr_reg_set) - MOVI2R(XA, imm_addr); + MOVI2R(addr_reg, imm_addr); }; const bool early_update = !jo.memcheck && dest != static_cast(addr); @@ -138,7 +136,7 @@ void JitArm64::SafeLoadToReg(u32 dest, s32 addr, s32 offsetReg, u32 flags, s32 o if (is_immediate && m_mmu.IsOptimizableRAMAddress(imm_addr, access_size)) { set_addr_reg_if_needed(); - EmitBackpatchRoutine(flags, MemAccessMode::AlwaysFastAccess, dest_reg, XA, scratch_gprs, + EmitBackpatchRoutine(flags, MemAccessMode::AlwaysFastAccess, dest_reg, addr_reg, scratch_gprs, scratch_fprs); } else if (mmio_address) @@ -154,7 +152,8 @@ void JitArm64::SafeLoadToReg(u32 dest, s32 addr, s32 offsetReg, u32 flags, s32 o else { set_addr_reg_if_needed(); - EmitBackpatchRoutine(flags, MemAccessMode::Auto, dest_reg, XA, scratch_gprs, scratch_fprs); + EmitBackpatchRoutine(flags, MemAccessMode::Auto, dest_reg, addr_reg, scratch_gprs, + scratch_fprs); } gpr.BindToRegister(dest, false, true); @@ -252,12 +251,10 @@ void JitArm64::SafeStoreFromReg(s32 dest, u32 value, s32 regOffset, u32 flags, s } } - ARM64Reg XA = EncodeRegTo64(addr_reg); - bool addr_reg_set = !is_immediate; const auto set_addr_reg_if_needed = [&] { if (!addr_reg_set) - MOVI2R(XA, imm_addr); + MOVI2R(addr_reg, imm_addr); }; const bool early_update = !jo.memcheck && value != static_cast(dest); @@ -307,7 +304,7 @@ void JitArm64::SafeStoreFromReg(s32 dest, u32 value, s32 regOffset, u32 flags, s else if (is_immediate && m_mmu.IsOptimizableRAMAddress(imm_addr, access_size)) { set_addr_reg_if_needed(); - EmitBackpatchRoutine(flags, MemAccessMode::AlwaysFastAccess, RS, XA, scratch_gprs, + EmitBackpatchRoutine(flags, MemAccessMode::AlwaysFastAccess, RS, addr_reg, scratch_gprs, scratch_fprs); } else if (mmio_address) @@ -323,7 +320,7 @@ void JitArm64::SafeStoreFromReg(s32 dest, u32 value, s32 regOffset, u32 flags, s else { set_addr_reg_if_needed(); - EmitBackpatchRoutine(flags, MemAccessMode::Auto, RS, XA, scratch_gprs, scratch_fprs); + EmitBackpatchRoutine(flags, MemAccessMode::Auto, RS, addr_reg, scratch_gprs, scratch_fprs); } if (update && !early_update) @@ -591,8 +588,8 @@ void JitArm64::lmw(UGeckoInstruction inst) if (jo.memcheck) scratch_gprs[DecodeReg(ARM64Reg::W0)] = true; - EmitBackpatchRoutine(flags, MemAccessMode::Auto, dest_reg, EncodeRegTo64(addr_reg), - scratch_gprs, scratch_fprs); + EmitBackpatchRoutine(flags, MemAccessMode::Auto, dest_reg, addr_reg, scratch_gprs, + scratch_fprs); gpr.BindToRegister(i, false, true); ASSERT(dest_reg == gpr.R(i)); @@ -703,8 +700,7 @@ void JitArm64::stmw(UGeckoInstruction inst) BitSet32 scratch_fprs; scratch_gprs[DecodeReg(addr_reg)] = true; - EmitBackpatchRoutine(flags, MemAccessMode::Auto, src_reg, EncodeRegTo64(addr_reg), scratch_gprs, - scratch_fprs); + EmitBackpatchRoutine(flags, MemAccessMode::Auto, src_reg, addr_reg, scratch_gprs, scratch_fprs); // To reduce register pressure and to avoid getting a pipeline-unfriendly long run of stores // after this instruction, flush registers that would be flushed after this instruction anyway. @@ -1025,8 +1021,8 @@ void JitArm64::dcbz(UGeckoInstruction inst) BitSet32 scratch_fprs; scratch_gprs[DecodeReg(ARM64Reg::W1)] = true; - EmitBackpatchRoutine(BackPatchInfo::FLAG_ZERO_256, MemAccessMode::Auto, ARM64Reg::W1, - EncodeRegTo64(addr_reg), scratch_gprs, scratch_fprs); + EmitBackpatchRoutine(BackPatchInfo::FLAG_ZERO_256, MemAccessMode::Auto, ARM64Reg::W1, addr_reg, + scratch_gprs, scratch_fprs); if (using_dcbz_hack) SetJumpTarget(end_dcbz_hack); diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp index 5deeaf3724..ff7d37df96 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStoreFloating.cpp @@ -151,10 +151,8 @@ void JitArm64::lfXX(UGeckoInstruction inst) } } - ARM64Reg XA = EncodeRegTo64(addr_reg); - if (is_immediate) - MOVI2R(XA, imm_addr); + MOVI2R(addr_reg, imm_addr); const bool early_update = !jo.memcheck; if (update && early_update) @@ -172,12 +170,12 @@ void JitArm64::lfXX(UGeckoInstruction inst) if (is_immediate && m_mmu.IsOptimizableRAMAddress(imm_addr, BackPatchInfo::GetFlagSize(flags))) { - EmitBackpatchRoutine(flags, MemAccessMode::AlwaysFastAccess, VD, XA, scratch_gprs, + EmitBackpatchRoutine(flags, MemAccessMode::AlwaysFastAccess, VD, addr_reg, scratch_gprs, scratch_fprs); } else { - EmitBackpatchRoutine(flags, MemAccessMode::Auto, VD, XA, scratch_gprs, scratch_fprs); + EmitBackpatchRoutine(flags, MemAccessMode::Auto, VD, addr_reg, scratch_gprs, scratch_fprs); } const ARM64Reg VD_again = fpr.RW(inst.FD, type, true); @@ -343,12 +341,10 @@ void JitArm64::stfXX(UGeckoInstruction inst) } } - ARM64Reg XA = EncodeRegTo64(addr_reg); - bool addr_reg_set = !is_immediate; const auto set_addr_reg_if_needed = [&] { if (!addr_reg_set) - MOVI2R(XA, imm_addr); + MOVI2R(addr_reg, imm_addr); }; const bool early_update = !jo.memcheck; @@ -390,20 +386,20 @@ void JitArm64::stfXX(UGeckoInstruction inst) else if (m_mmu.IsOptimizableRAMAddress(imm_addr, BackPatchInfo::GetFlagSize(flags))) { set_addr_reg_if_needed(); - EmitBackpatchRoutine(flags, MemAccessMode::AlwaysFastAccess, V0, XA, scratch_gprs, + EmitBackpatchRoutine(flags, MemAccessMode::AlwaysFastAccess, V0, addr_reg, scratch_gprs, scratch_fprs); } else { set_addr_reg_if_needed(); - EmitBackpatchRoutine(flags, MemAccessMode::AlwaysSlowAccess, V0, XA, scratch_gprs, + EmitBackpatchRoutine(flags, MemAccessMode::AlwaysSlowAccess, V0, addr_reg, scratch_gprs, scratch_fprs); } } else { set_addr_reg_if_needed(); - EmitBackpatchRoutine(flags, MemAccessMode::Auto, V0, XA, scratch_gprs, scratch_fprs); + EmitBackpatchRoutine(flags, MemAccessMode::Auto, V0, addr_reg, scratch_gprs, scratch_fprs); } if (update && !early_update) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp index b5731a2157..b225c83eab 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStorePaired.cpp @@ -90,8 +90,7 @@ void JitArm64::psq_lXX(UGeckoInstruction inst) if (!w) flags |= BackPatchInfo::FLAG_PAIR; - EmitBackpatchRoutine(flags, MemAccessMode::Auto, VS, EncodeRegTo64(addr_reg), scratch_gprs, - scratch_fprs); + EmitBackpatchRoutine(flags, MemAccessMode::Auto, VS, addr_reg, scratch_gprs, scratch_fprs); } else { @@ -244,8 +243,7 @@ void JitArm64::psq_stXX(UGeckoInstruction inst) if (!w) flags |= BackPatchInfo::FLAG_PAIR; - EmitBackpatchRoutine(flags, MemAccessMode::Auto, VS, EncodeRegTo64(addr_reg), scratch_gprs, - scratch_fprs); + EmitBackpatchRoutine(flags, MemAccessMode::Auto, VS, addr_reg, scratch_gprs, scratch_fprs); } else { diff --git a/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp b/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp index aefec65cad..bb28b9052b 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitAsm.cpp @@ -524,7 +524,7 @@ void JitArm64::GenerateQuantizedLoads() // Q0 is the return // Q1 is a temporary ARM64Reg temp_reg = ARM64Reg::X0; - ARM64Reg addr_reg = ARM64Reg::X1; + ARM64Reg addr_reg = ARM64Reg::W1; ARM64Reg scale_reg = ARM64Reg::X2; BitSet32 scratch_gprs{0, 3}; if (!jo.memcheck) @@ -735,7 +735,7 @@ void JitArm64::GenerateQuantizedStores() // Q1 is a temporary ARM64Reg temp_reg = ARM64Reg::X0; ARM64Reg scale_reg = ARM64Reg::X1; - ARM64Reg addr_reg = ARM64Reg::X2; + ARM64Reg addr_reg = ARM64Reg::W2; BitSet32 scratch_gprs{0, 1}; if (!jo.memcheck) scratch_gprs[2] = true;