From 94169b3c7d3249bbc824e7c7e226fbdc257d9ee8 Mon Sep 17 00:00:00 2001 From: Pokechu22 Date: Sat, 10 Dec 2022 17:24:31 -0800 Subject: [PATCH] Add (failing) interrupt-related tests --- Source/DSPSpy/tests/interrupt_nested.ds | 77 ++++++++++++++++++ Source/DSPSpy/tests/interrupt_suppressed.ds | 74 +++++++++++++++++ .../tests/interrupt_suppressed_nested_rti.ds | 73 +++++++++++++++++ .../interrupt_suppressed_nested_sbset.ds | 81 +++++++++++++++++++ 4 files changed, 305 insertions(+) create mode 100644 Source/DSPSpy/tests/interrupt_nested.ds create mode 100644 Source/DSPSpy/tests/interrupt_suppressed.ds create mode 100644 Source/DSPSpy/tests/interrupt_suppressed_nested_rti.ds create mode 100644 Source/DSPSpy/tests/interrupt_suppressed_nested_sbset.ds diff --git a/Source/DSPSpy/tests/interrupt_nested.ds b/Source/DSPSpy/tests/interrupt_nested.ds new file mode 100644 index 0000000000..389ea7b96d --- /dev/null +++ b/Source/DSPSpy/tests/interrupt_nested.ds @@ -0,0 +1,77 @@ +; This test needs to manually specify IRQs + jmp irq0 + jmp irq1 + jmp irq2 + jmp irq3 + jmp irq4 + jmp accov_irq + jmp irq6 + jmp irq7 + +incdir "tests" +include "dsp_base_noirq.inc" + +test_main: + ; Use the accelerator to generate an IRQ by setting the start and end address to 0 + ; This will result in an interrupt on every read + SI @0xffda, #0 ; pred_scale + SI @0xffdb, #0 ; yn1 + SI @0xffdc, #0 ; yn2 + SI @0xffd1, #0 ; SampleFormat + SI @ACSAH, #0 + SI @ACCAH, #0 + SI @ACSAL, #0 + SI @ACCAL, #0 + SI @ACEAH, #0 + SI @ACEAL, #0 + + CLR $ACC0 + CLR $ACC1 + LRIS $AX0.H, #1 + LRIS $AX1.H, #0 + CALL send_back + + LRS $AX0.L, @ARAM ; Trigger interrupt + LRIS $AX1.H, #1 + + LRIS $AX0.H, #2 + CALL send_back + + jmp end_of_test + +accov_irq: + ; NOTE: interrupts are NOT automatically disabled here + + ; Restore registers, otherwise no new interrupt will be generated + SI @0xffda, #0 ; pred_scale + SI @0xffdb, #0 ; yn1 + SI @0xffdc, #0 ; yn2 + + INCM $AC0.M + INCM $AC1.M + + LRIS $AX0.H, #3 + CALL send_back + + CMPIS $AC0.M, #1 + IFZ + ; Trigger second interrupt, which will happen immediately + LRS $AX0.L, @ARAM + + LRIS $AX1.H, #2 + + LRIS $AX0.H, #4 + CALL send_back + + DECM $AC1.M + + RTI + +; Expected output ($AX0.H (send_back number), $AX1.H (changed on lines after an exception fires, +; to make sure it happens immediately), $AC0.M (interrupt count), $AC1.M (interrupt depth), and $SR): +; 1, 0, 0, 0, 2224 (first line) +; 3, 0, 1, 1, 2220 (start of interrupt handler) +; 3, 0, 2, 2, 2220 (nested start of interrupt handler) +; 4, 2, 2, 2, 2221 (nested interrupt handler exits) +; 4, 2, 2, 1, 2225 (interrupt handler exits) +; 2, 1, 2, 0, 2224 (before end_of_test) \ No newline at end of file diff --git a/Source/DSPSpy/tests/interrupt_suppressed.ds b/Source/DSPSpy/tests/interrupt_suppressed.ds new file mode 100644 index 0000000000..6f80b3fe44 --- /dev/null +++ b/Source/DSPSpy/tests/interrupt_suppressed.ds @@ -0,0 +1,74 @@ +; This test needs to manually specify IRQs + jmp irq0 + jmp irq1 + jmp irq2 + jmp irq3 + jmp irq4 + jmp accov_irq + jmp irq6 + jmp irq7 + +incdir "tests" +include "dsp_base_noirq.inc" + +test_main: + ; Use the accelerator to generate an IRQ by setting the start and end address to 0 + ; This will result in an interrupt on every read + SI @0xffda, #0 ; pred_scale + SI @0xffdb, #0 ; yn1 + SI @0xffdc, #0 ; yn2 + SI @0xffd1, #0 ; SampleFormat + SI @ACSAH, #0 + SI @ACCAH, #0 + SI @ACSAL, #0 + SI @ACCAL, #0 + SI @ACEAH, #0 + SI @ACEAL, #0 + + CLR $ACC0 + CLR $ACC1 + + LRIS $AC1.M, #1 + CALL send_back + + LRS $AX0.L, @ARAM ; Trigger interrupt + + LRIS $AC1.M, #2 + CALL send_back + + SBCLR #3 ; Disable interrupts + + LRIS $AC1.M, #3 + CALL send_back + + LRS $AX0.L, @ARAM ; Trigger interrupt while disabled + + LRIS $AC1.M, #4 + CALL send_back + + SBSET #3 ; Re-enable interrupts + + LRIS $AC1.M, #5 + CALL send_back + + jmp end_of_test + +accov_irq: + ; Restore registers, otherwise no new interrupt will be generated + SI @0xffda, #0 ; pred_scale + SI @0xffdb, #0 ; yn1 + SI @0xffdc, #0 ; yn2 + + INCM $AC0.M + LRIS $AC1.M, #6 + CALL send_back + + RTI + +; Expected output ($AC0.M (num interrupts), $AC1.M (send_back number), and $SR): +; 0, 1, 2224 (start) +; 1, 6, 2220 (in interrupt handler) +; 1, 2, 2224 (out of interrupt handler) +; 1, 3, 2024 (interrupts disabled) +; 1, 4, 2024 (no interrupt triggered) +; 1, 5, 2224 (interrupts enabled, still no interrupt triggered) diff --git a/Source/DSPSpy/tests/interrupt_suppressed_nested_rti.ds b/Source/DSPSpy/tests/interrupt_suppressed_nested_rti.ds new file mode 100644 index 0000000000..9c5e31d572 --- /dev/null +++ b/Source/DSPSpy/tests/interrupt_suppressed_nested_rti.ds @@ -0,0 +1,73 @@ +; This test needs to manually specify IRQs + jmp irq0 + jmp irq1 + jmp irq2 + jmp irq3 + jmp irq4 + jmp accov_irq + jmp irq6 + jmp irq7 + +incdir "tests" +include "dsp_base_noirq.inc" + +test_main: + ; Use the accelerator to generate an IRQ by setting the start and end address to 0 + ; This will result in an interrupt on every read + SI @0xffda, #0 ; pred_scale + SI @0xffdb, #0 ; yn1 + SI @0xffdc, #0 ; yn2 + SI @0xffd1, #0 ; SampleFormat + SI @ACSAH, #0 + SI @ACCAH, #0 + SI @ACSAL, #0 + SI @ACCAL, #0 + SI @ACEAH, #0 + SI @ACEAL, #0 + + CLR $ACC0 + CLR $ACC1 + LRIS $AX0.H, #1 + LRIS $AX1.H, #0 + CALL send_back + + LRS $AX0.L, @ARAM ; Trigger interrupt + LRIS $AX1.H, #1 + + LRIS $AX0.H, #2 + CALL send_back + + jmp end_of_test + +accov_irq: + ; Disable interrupts + SBCLR #3 + + ; Restore registers, otherwise no new interrupt will be generated + SI @0xffda, #0 ; pred_scale + SI @0xffdb, #0 ; yn1 + SI @0xffdc, #0 ; yn2 + + INCM $AC0.M + INCM $AC1.M + + LRIS $AX0.H, #3 + CALL send_back + + ; Trigger second interrupt, which will be ignored(!) + LRS $AX0.L, @ARAM + LRIS $AX1.H, #2 + + LRIS $AX0.H, #4 + CALL send_back + + DECM $AC1.M + + RTI + +; Expected output ($AX0.H (send_back number), $AX1.H (changed on lines after an exception fires, +; to make sure it happens immediately), $AC0.M (interrupt count), $AC1.M (interrupt depth), and $SR): +; 1, 0, 0, 0, 2224 (first line) +; 3, 0, 1, 1, 2020 (start of interrupt handler) +; 4, 2, 1, 1, 2020 (end of interrupt handler) +; 2, 1, 1, 0, 2224 (before end_of_test) diff --git a/Source/DSPSpy/tests/interrupt_suppressed_nested_sbset.ds b/Source/DSPSpy/tests/interrupt_suppressed_nested_sbset.ds new file mode 100644 index 0000000000..9db3080d57 --- /dev/null +++ b/Source/DSPSpy/tests/interrupt_suppressed_nested_sbset.ds @@ -0,0 +1,81 @@ +; This test needs to manually specify IRQs + jmp irq0 + jmp irq1 + jmp irq2 + jmp irq3 + jmp irq4 + jmp accov_irq + jmp irq6 + jmp irq7 + +incdir "tests" +include "dsp_base_noirq.inc" + +test_main: + ; Use the accelerator to generate an IRQ by setting the start and end address to 0 + ; This will result in an interrupt on every read + SI @0xffda, #0 ; pred_scale + SI @0xffdb, #0 ; yn1 + SI @0xffdc, #0 ; yn2 + SI @0xffd1, #0 ; SampleFormat + SI @ACSAH, #0 + SI @ACCAH, #0 + SI @ACSAL, #0 + SI @ACCAL, #0 + SI @ACEAH, #0 + SI @ACEAL, #0 + + CLR $ACC0 + CLR $ACC1 + LRIS $AX0.H, #1 + LRIS $AX1.H, #0 + CALL send_back + + LRS $AX0.L, @ARAM ; Trigger interrupt + LRIS $AX1.H, #1 + + LRIS $AX0.H, #2 + CALL send_back + + jmp end_of_test + +accov_irq: + ; Disable interrupts + SBCLR #3 + + ; Restore registers, otherwise no new interrupt will be generated + SI @0xffda, #0 ; pred_scale + SI @0xffdb, #0 ; yn1 + SI @0xffdc, #0 ; yn2 + + INCM $AC0.M + INCM $AC1.M + + LRIS $AX0.H, #3 + CALL send_back + + ; Trigger second interrupt, which will be ignored(!) + LRS $AX0.L, @ARAM + LRIS $AX1.H, #2 + + LRIS $AX0.H, #4 + CALL send_back + + ; Re-enable interrupts - we don't get the previously triggered interrupt here. + SBSET #3 + LRIS $AX1.H, #3 + + LRIS $AX0.H, #5 + CALL send_back + + DECM $AC1.M + + RTI + +; Expected output ($AX0.H (send_back number), $AX1.H (changed on lines after an exception fires, +; to make sure it happens immediately), $AC0.M (interrupt count), $AC1.M (interrupt depth), and $SR): +; 1, 0, 0, 0, 2224 (first line) +; 3, 0, 1, 1, 2020 (start of interrupt handler) +; 4, 2, 1, 1, 2020 (middle of interrupt handler) +; 5, 3, 1, 1, 2220 (end of interrupt handler) +; 2, 1, 1, 0, 2224 (before end_of_test)