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Core: Detect SR updates

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This commit is contained in:
JosJuice 2025-06-20 08:56:15 +02:00
commit ab19d714d2
10 changed files with 28 additions and 51 deletions
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2
Source/Core/Core/PowerPC/GDBStub.cpp
View file

@ -36,6 +36,7 @@ typedef SSIZE_T ssize_t;
#include "Core/Host.h"
#include "Core/PowerPC/BreakPoints.h"
#include "Core/PowerPC/Gekko.h"
#include "Core/PowerPC/MMU.h"
#include "Core/PowerPC/PPCCache.h"
#include "Core/PowerPC/PowerPC.h"
#include "Core/System.h"
@ -648,6 +649,7 @@ static void WriteRegister()
else if (id >= 71 && id < 87)
{
ppc_state.sr[id - 71] = re32hex(bufptr);
system.GetMMU().SRUpdated();
}
else if (id >= 88 && id < 104)
{

6
Source/Core/Core/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp
View file

@ -203,7 +203,8 @@ void Interpreter::mtsr(Interpreter& interpreter, UGeckoInstruction inst)
const u32 index = inst.SR;
const u32 value = ppc_state.gpr[inst.RS];
ppc_state.SetSR(index, value);
ppc_state.sr[index] = value;
interpreter.m_system.GetMMU().SRUpdated();
}
void Interpreter::mtsrin(Interpreter& interpreter, UGeckoInstruction inst)
@ -217,7 +218,8 @@ void Interpreter::mtsrin(Interpreter& interpreter, UGeckoInstruction inst)
const u32 index = (ppc_state.gpr[inst.RB] >> 28) & 0xF;
const u32 value = ppc_state.gpr[inst.RS];
ppc_state.SetSR(index, value);
ppc_state.sr[index] = value;
interpreter.m_system.GetMMU().SRUpdated();
}
void Interpreter::mftb(Interpreter& interpreter, UGeckoInstruction inst)

2
Source/Core/Core/PowerPC/JitArm64/Jit.h
View file

@ -122,9 +122,7 @@ public:
void mcrf(UGeckoInstruction inst);
void mcrxr(UGeckoInstruction inst);
void mfsr(UGeckoInstruction inst);
void mtsr(UGeckoInstruction inst);
void mfsrin(UGeckoInstruction inst);
void mtsrin(UGeckoInstruction inst);
void twx(UGeckoInstruction inst);
void mfspr(UGeckoInstruction inst);
void mftb(UGeckoInstruction inst);

26
Source/Core/Core/PowerPC/JitArm64/JitArm64_SystemRegisters.cpp
View file

@ -291,14 +291,6 @@ void JitArm64::mfsr(UGeckoInstruction inst)
LDR(IndexType::Unsigned, gpr.R(inst.RD), PPC_REG, PPCSTATE_OFF_SR(inst.SR));
}
void JitArm64::mtsr(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITSystemRegistersOff);
STR(IndexType::Unsigned, gpr.R(inst.RS), PPC_REG, PPCSTATE_OFF_SR(inst.SR));
}
void JitArm64::mfsrin(UGeckoInstruction inst)
{
INSTRUCTION_START
@ -317,24 +309,6 @@ void JitArm64::mfsrin(UGeckoInstruction inst)
LDR(RD, addr, ArithOption(EncodeRegTo64(index), true));
}
void JitArm64::mtsrin(UGeckoInstruction inst)
{
INSTRUCTION_START
JITDISABLE(bJITSystemRegistersOff);
u32 b = inst.RB, d = inst.RD;
gpr.BindToRegister(d, d == b);
ARM64Reg RB = gpr.R(b);
ARM64Reg RD = gpr.R(d);
auto index = gpr.GetScopedReg();
auto addr = gpr.GetScopedReg();
UBFM(index, RB, 28, 31);
ADDI2R(EncodeRegTo64(addr), PPC_REG, PPCSTATE_OFF_SR(0), EncodeRegTo64(addr));
STR(RD, EncodeRegTo64(addr), ArithOption(EncodeRegTo64(index), true));
}
void JitArm64::twx(UGeckoInstruction inst)
{
INSTRUCTION_START

24
Source/Core/Core/PowerPC/JitArm64/JitArm64_Tables.cpp
View file

@ -266,18 +266,18 @@ constexpr std::array<JitArm64OpTemplate, 107> s_table31{{
{759, &JitArm64::stfXX}, // stfdux
{983, &JitArm64::stfXX}, // stfiwx
{19, &JitArm64::mfcr}, // mfcr
{83, &JitArm64::mfmsr}, // mfmsr
{144, &JitArm64::mtcrf}, // mtcrf
{146, &JitArm64::mtmsr}, // mtmsr
{210, &JitArm64::mtsr}, // mtsr
{242, &JitArm64::mtsrin}, // mtsrin
{339, &JitArm64::mfspr}, // mfspr
{467, &JitArm64::mtspr}, // mtspr
{371, &JitArm64::mftb}, // mftb
{512, &JitArm64::mcrxr}, // mcrxr
{595, &JitArm64::mfsr}, // mfsr
{659, &JitArm64::mfsrin}, // mfsrin
{19, &JitArm64::mfcr}, // mfcr
{83, &JitArm64::mfmsr}, // mfmsr
{144, &JitArm64::mtcrf}, // mtcrf
{146, &JitArm64::mtmsr}, // mtmsr
{210, &JitArm64::FallBackToInterpreter}, // mtsr
{242, &JitArm64::FallBackToInterpreter}, // mtsrin
{339, &JitArm64::mfspr}, // mfspr
{467, &JitArm64::mtspr}, // mtspr
{371, &JitArm64::mftb}, // mftb
{512, &JitArm64::mcrxr}, // mcrxr
{595, &JitArm64::mfsr}, // mfsr
{659, &JitArm64::mfsrin}, // mfsrin
{4, &JitArm64::twx}, // tw
{598, &JitArm64::DoNothing}, // sync

4
Source/Core/Core/PowerPC/MMU.cpp
View file

@ -1325,6 +1325,10 @@ void MMU::SDRUpdated()
m_ppc_state.pagetable_hashmask = ((htabmask << 10) | 0x3ff);
}
void MMU::SRUpdated()
{
}
enum class TLBLookupResult
{
Found,

1
Source/Core/Core/PowerPC/MMU.h
View file

@ -238,6 +238,7 @@ public:
// TLB functions
void SDRUpdated();
void SRUpdated();
void InvalidateTLBEntry(u32 address);
void DBATUpdated();
void IBATUpdated();

6
Source/Core/Core/PowerPC/PowerPC.cpp
View file

@ -662,12 +662,6 @@ bool PowerPCManager::CheckAndHandleBreakPoints()
return false;
}
void PowerPCState::SetSR(u32 index, u32 value)
{
DEBUG_LOG_FMT(POWERPC, "{:08x}: MMU: Segment register {} set to {:08x}", pc, index, value);
sr[index] = value;
}
// FPSCR update functions
void PowerPCState::UpdateFPRFDouble(double dvalue)

2
Source/Core/Core/PowerPC/PowerPC.h
View file

@ -193,8 +193,6 @@ struct PowerPCState
cr.SetField(1, (fpscr.FX << 3) | (fpscr.FEX << 2) | (fpscr.VX << 1) | fpscr.OX);
}
void SetSR(u32 index, u32 value);
void SetCarry(u32 ca) { xer_ca = ca; }
u32 GetCarry() const { return xer_ca; }

6
Source/Core/DolphinQt/Debugger/RegisterWidget.cpp
View file

@ -15,6 +15,7 @@
#include "Core/Core.h"
#include "Core/Debugger/CodeTrace.h"
#include "Core/HW/ProcessorInterface.h"
#include "Core/PowerPC/MMU.h"
#include "Core/PowerPC/PowerPC.h"
#include "Core/System.h"
#include "DolphinQt/Host.h"
@ -405,7 +406,10 @@ void RegisterWidget::PopulateTable()
AddRegister(
i, 7, RegisterType::sr, "SR" + std::to_string(i),
[this, i] { return m_system.GetPPCState().sr[i]; },
[this, i](u64 value) { m_system.GetPPCState().sr[i] = value; });
[this, i](u64 value) {
m_system.GetPPCState().sr[i] = value;
m_system.GetMMU().SRUpdated();
});
}
// Special registers