mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2025-06-18 16:21:39 +00:00
update Cheat files
This commit is contained in:
Nayla Hanegan
parent
9ab8c1e433
commit
cbfd634a4b
217 changed files with 2263 additions and 1880 deletions
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@ -20,7 +20,8 @@
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#include "DolphinQt/Host.h"
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#include "DolphinQt/Settings.h"
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RegisterWidget::RegisterWidget(QWidget* parent) : QDockWidget(parent)
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RegisterWidget::RegisterWidget(QWidget* parent)
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: QDockWidget(parent), m_system(Core::System::GetInstance())
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{
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setWindowTitle(tr("Registers"));
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setObjectName(QStringLiteral("registers"));
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@ -295,8 +296,8 @@ void RegisterWidget::AutoStep(const std::string& reg) const
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while (true)
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{
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const AutoStepResults results = [&trace] {
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Core::CPUThreadGuard guard(Core::System::GetInstance());
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const AutoStepResults results = [this, &trace] {
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Core::CPUThreadGuard guard(m_system);
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return trace.AutoStepping(guard, true);
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}();
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@ -318,18 +319,19 @@ void RegisterWidget::PopulateTable()
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{
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// General purpose registers (int)
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AddRegister(
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i, 0, RegisterType::gpr, "r" + std::to_string(i), [i] { return PowerPC::ppcState.gpr[i]; },
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[i](u64 value) { PowerPC::ppcState.gpr[i] = value; });
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i, 0, RegisterType::gpr, "r" + std::to_string(i),
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[this, i] { return m_system.GetPPCState().gpr[i]; },
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[this, i](u64 value) { m_system.GetPPCState().gpr[i] = value; });
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// Floating point registers (double)
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AddRegister(
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i, 2, RegisterType::fpr, "f" + std::to_string(i),
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[i] { return PowerPC::ppcState.ps[i].PS0AsU64(); },
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[i](u64 value) { PowerPC::ppcState.ps[i].SetPS0(value); });
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[this, i] { return m_system.GetPPCState().ps[i].PS0AsU64(); },
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[this, i](u64 value) { m_system.GetPPCState().ps[i].SetPS0(value); });
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AddRegister(
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i, 4, RegisterType::fpr, "", [i] { return PowerPC::ppcState.ps[i].PS1AsU64(); },
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[i](u64 value) { PowerPC::ppcState.ps[i].SetPS1(value); });
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i, 4, RegisterType::fpr, "", [this, i] { return m_system.GetPPCState().ps[i].PS1AsU64(); },
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[this, i](u64 value) { m_system.GetPPCState().ps[i].SetPS1(value); });
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}
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// The IBAT and DBAT registers have a large gap between
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@ -340,32 +342,36 @@ void RegisterWidget::PopulateTable()
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// IBAT registers
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AddRegister(
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i, 5, RegisterType::ibat, "IBAT" + std::to_string(i),
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[i] {
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return (static_cast<u64>(PowerPC::ppcState.spr[SPR_IBAT0U + i * 2]) << 32) +
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PowerPC::ppcState.spr[SPR_IBAT0L + i * 2];
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[this, i] {
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const auto& ppc_state = m_system.GetPPCState();
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return (static_cast<u64>(ppc_state.spr[SPR_IBAT0U + i * 2]) << 32) +
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ppc_state.spr[SPR_IBAT0L + i * 2];
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},
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nullptr);
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AddRegister(
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i + 4, 5, RegisterType::ibat, "IBAT" + std::to_string(4 + i),
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[i] {
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return (static_cast<u64>(PowerPC::ppcState.spr[SPR_IBAT4U + i * 2]) << 32) +
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PowerPC::ppcState.spr[SPR_IBAT4L + i * 2];
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[this, i] {
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const auto& ppc_state = m_system.GetPPCState();
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return (static_cast<u64>(ppc_state.spr[SPR_IBAT4U + i * 2]) << 32) +
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ppc_state.spr[SPR_IBAT4L + i * 2];
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},
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nullptr);
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// DBAT registers
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AddRegister(
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i + 8, 5, RegisterType::dbat, "DBAT" + std::to_string(i),
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[i] {
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return (static_cast<u64>(PowerPC::ppcState.spr[SPR_DBAT0U + i * 2]) << 32) +
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PowerPC::ppcState.spr[SPR_DBAT0L + i * 2];
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[this, i] {
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const auto& ppc_state = m_system.GetPPCState();
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return (static_cast<u64>(ppc_state.spr[SPR_DBAT0U + i * 2]) << 32) +
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ppc_state.spr[SPR_DBAT0L + i * 2];
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},
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nullptr);
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AddRegister(
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i + 12, 5, RegisterType::dbat, "DBAT" + std::to_string(4 + i),
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[i] {
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return (static_cast<u64>(PowerPC::ppcState.spr[SPR_DBAT4U + i * 2]) << 32) +
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PowerPC::ppcState.spr[SPR_DBAT4L + i * 2];
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[this, i] {
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const auto& ppc_state = m_system.GetPPCState();
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return (static_cast<u64>(ppc_state.spr[SPR_DBAT4U + i * 2]) << 32) +
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ppc_state.spr[SPR_DBAT4L + i * 2];
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},
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nullptr);
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}
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@ -375,114 +381,113 @@ void RegisterWidget::PopulateTable()
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// Graphics quantization registers
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AddRegister(
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i + 16, 7, RegisterType::gqr, "GQR" + std::to_string(i),
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[i] { return PowerPC::ppcState.spr[SPR_GQR0 + i]; }, nullptr);
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[this, i] { return m_system.GetPPCState().spr[SPR_GQR0 + i]; }, nullptr);
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}
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// HID registers
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AddRegister(
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24, 7, RegisterType::hid, "HID0", [] { return PowerPC::ppcState.spr[SPR_HID0]; },
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[](u64 value) { PowerPC::ppcState.spr[SPR_HID0] = static_cast<u32>(value); });
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24, 7, RegisterType::hid, "HID0", [this] { return m_system.GetPPCState().spr[SPR_HID0]; },
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[this](u64 value) { m_system.GetPPCState().spr[SPR_HID0] = static_cast<u32>(value); });
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AddRegister(
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25, 7, RegisterType::hid, "HID1", [] { return PowerPC::ppcState.spr[SPR_HID1]; },
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[](u64 value) { PowerPC::ppcState.spr[SPR_HID1] = static_cast<u32>(value); });
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25, 7, RegisterType::hid, "HID1", [this] { return m_system.GetPPCState().spr[SPR_HID1]; },
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[this](u64 value) { m_system.GetPPCState().spr[SPR_HID1] = static_cast<u32>(value); });
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AddRegister(
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26, 7, RegisterType::hid, "HID2", [] { return PowerPC::ppcState.spr[SPR_HID2]; },
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[](u64 value) { PowerPC::ppcState.spr[SPR_HID2] = static_cast<u32>(value); });
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26, 7, RegisterType::hid, "HID2", [this] { return m_system.GetPPCState().spr[SPR_HID2]; },
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[this](u64 value) { m_system.GetPPCState().spr[SPR_HID2] = static_cast<u32>(value); });
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AddRegister(
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27, 7, RegisterType::hid, "HID4", [] { return PowerPC::ppcState.spr[SPR_HID4]; },
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[](u64 value) { PowerPC::ppcState.spr[SPR_HID4] = static_cast<u32>(value); });
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27, 7, RegisterType::hid, "HID4", [this] { return m_system.GetPPCState().spr[SPR_HID4]; },
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[this](u64 value) { m_system.GetPPCState().spr[SPR_HID4] = static_cast<u32>(value); });
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for (int i = 0; i < 16; i++)
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{
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// SR registers
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AddRegister(
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i, 7, RegisterType::sr, "SR" + std::to_string(i), [i] { return PowerPC::ppcState.sr[i]; },
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[i](u64 value) { PowerPC::ppcState.sr[i] = value; });
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i, 7, RegisterType::sr, "SR" + std::to_string(i),
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[this, i] { return m_system.GetPPCState().sr[i]; },
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[this, i](u64 value) { m_system.GetPPCState().sr[i] = value; });
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}
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// Special registers
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// TB
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AddRegister(16, 5, RegisterType::tb, "TB", PowerPC::ReadFullTimeBaseValue, nullptr);
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AddRegister(
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16, 5, RegisterType::tb, "TB",
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[this] { return m_system.GetPowerPC().ReadFullTimeBaseValue(); }, nullptr);
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// PC
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AddRegister(
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17, 5, RegisterType::pc, "PC", [] { return PowerPC::ppcState.pc; },
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[](u64 value) { PowerPC::ppcState.pc = value; });
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17, 5, RegisterType::pc, "PC", [this] { return m_system.GetPPCState().pc; },
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[this](u64 value) { m_system.GetPPCState().pc = value; });
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// LR
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AddRegister(
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18, 5, RegisterType::lr, "LR", [] { return PowerPC::ppcState.spr[SPR_LR]; },
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[](u64 value) { PowerPC::ppcState.spr[SPR_LR] = value; });
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18, 5, RegisterType::lr, "LR", [this] { return m_system.GetPPCState().spr[SPR_LR]; },
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[this](u64 value) { m_system.GetPPCState().spr[SPR_LR] = value; });
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// CTR
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AddRegister(
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19, 5, RegisterType::ctr, "CTR", [] { return PowerPC::ppcState.spr[SPR_CTR]; },
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[](u64 value) { PowerPC::ppcState.spr[SPR_CTR] = value; });
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19, 5, RegisterType::ctr, "CTR", [this] { return m_system.GetPPCState().spr[SPR_CTR]; },
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[this](u64 value) { m_system.GetPPCState().spr[SPR_CTR] = value; });
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// CR
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AddRegister(
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20, 5, RegisterType::cr, "CR", [] { return PowerPC::ppcState.cr.Get(); },
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[](u64 value) { PowerPC::ppcState.cr.Set(value); });
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20, 5, RegisterType::cr, "CR", [this] { return m_system.GetPPCState().cr.Get(); },
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[this](u64 value) { m_system.GetPPCState().cr.Set(value); });
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// XER
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AddRegister(
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21, 5, RegisterType::xer, "XER", [] { return PowerPC::ppcState.GetXER().Hex; },
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[](u64 value) { PowerPC::ppcState.SetXER(UReg_XER(value)); });
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21, 5, RegisterType::xer, "XER", [this] { return m_system.GetPPCState().GetXER().Hex; },
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[this](u64 value) { m_system.GetPPCState().SetXER(UReg_XER(value)); });
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// FPSCR
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AddRegister(
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22, 5, RegisterType::fpscr, "FPSCR", [] { return PowerPC::ppcState.fpscr.Hex; },
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[](u64 value) { PowerPC::ppcState.fpscr = static_cast<u32>(value); });
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22, 5, RegisterType::fpscr, "FPSCR", [this] { return m_system.GetPPCState().fpscr.Hex; },
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[this](u64 value) { m_system.GetPPCState().fpscr = static_cast<u32>(value); });
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// MSR
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AddRegister(
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23, 5, RegisterType::msr, "MSR", [] { return PowerPC::ppcState.msr.Hex; },
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[](u64 value) { PowerPC::ppcState.msr.Hex = value; });
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23, 5, RegisterType::msr, "MSR", [this] { return m_system.GetPPCState().msr.Hex; },
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[this](u64 value) { m_system.GetPPCState().msr.Hex = value; });
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// SRR 0-1
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AddRegister(
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24, 5, RegisterType::srr, "SRR0", [] { return PowerPC::ppcState.spr[SPR_SRR0]; },
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[](u64 value) { PowerPC::ppcState.spr[SPR_SRR0] = value; });
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24, 5, RegisterType::srr, "SRR0", [this] { return m_system.GetPPCState().spr[SPR_SRR0]; },
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[this](u64 value) { m_system.GetPPCState().spr[SPR_SRR0] = value; });
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AddRegister(
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25, 5, RegisterType::srr, "SRR1", [] { return PowerPC::ppcState.spr[SPR_SRR1]; },
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[](u64 value) { PowerPC::ppcState.spr[SPR_SRR1] = value; });
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25, 5, RegisterType::srr, "SRR1", [this] { return m_system.GetPPCState().spr[SPR_SRR1]; },
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[this](u64 value) { m_system.GetPPCState().spr[SPR_SRR1] = value; });
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// Exceptions
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AddRegister(
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26, 5, RegisterType::exceptions, "Exceptions", [] { return PowerPC::ppcState.Exceptions; },
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[](u64 value) { PowerPC::ppcState.Exceptions = value; });
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26, 5, RegisterType::exceptions, "Exceptions",
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[this] { return m_system.GetPPCState().Exceptions; },
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[this](u64 value) { m_system.GetPPCState().Exceptions = value; });
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// Int Mask
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AddRegister(
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27, 5, RegisterType::int_mask, "Int Mask",
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[] {
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auto& system = Core::System::GetInstance();
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return system.GetProcessorInterface().GetMask();
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},
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nullptr);
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[this] { return m_system.GetProcessorInterface().GetMask(); }, nullptr);
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// Int Cause
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AddRegister(
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28, 5, RegisterType::int_cause, "Int Cause",
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[] {
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auto& system = Core::System::GetInstance();
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return system.GetProcessorInterface().GetCause();
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},
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nullptr);
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[this] { return m_system.GetProcessorInterface().GetCause(); }, nullptr);
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// DSISR
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AddRegister(
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29, 5, RegisterType::dsisr, "DSISR", [] { return PowerPC::ppcState.spr[SPR_DSISR]; },
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[](u64 value) { PowerPC::ppcState.spr[SPR_DSISR] = value; });
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29, 5, RegisterType::dsisr, "DSISR", [this] { return m_system.GetPPCState().spr[SPR_DSISR]; },
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[this](u64 value) { m_system.GetPPCState().spr[SPR_DSISR] = value; });
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// DAR
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AddRegister(
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30, 5, RegisterType::dar, "DAR", [] { return PowerPC::ppcState.spr[SPR_DAR]; },
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[](u64 value) { PowerPC::ppcState.spr[SPR_DAR] = value; });
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30, 5, RegisterType::dar, "DAR", [this] { return m_system.GetPPCState().spr[SPR_DAR]; },
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[this](u64 value) { m_system.GetPPCState().spr[SPR_DAR] = value; });
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// Hash Mask
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AddRegister(
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31, 5, RegisterType::pt_hashmask, "Hash Mask",
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[] { return (PowerPC::ppcState.pagetable_hashmask << 6) | PowerPC::ppcState.pagetable_base; },
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[this] {
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const auto& ppc_state = m_system.GetPPCState();
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return (ppc_state.pagetable_hashmask << 6) | ppc_state.pagetable_base;
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},
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nullptr);
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emit RequestTableUpdate();
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