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Core: Update page table mappings incrementally
Removing and readding every page table mapping every time something changes in the page table is very slow. Instead, let's generate a diff and ask Memmap to update only the diff.
This commit is contained in:
JosJuice
parent
dac13baade
commit
d3cfa293e9
7 changed files with 439 additions and 106 deletions
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@ -13,6 +13,7 @@
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#include <cstring>
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#include <map>
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#include <memory>
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#include <set>
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#include <span>
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#include <tuple>
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@ -244,11 +245,7 @@ void MemoryManager::UpdateDBATMappings(const PowerPC::BatTable& dbat_table)
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}
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m_dbat_mapped_entries.clear();
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for (auto& entry : m_page_table_mapped_entries)
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{
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m_arena.UnmapFromMemoryRegion(entry.mapped_pointer, entry.mapped_size);
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}
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m_page_table_mapped_entries.clear();
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RemoveAllPageTableMappings();
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m_logical_page_mappings.fill(nullptr);
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@ -302,7 +299,7 @@ void MemoryManager::UpdateDBATMappings(const PowerPC::BatTable& dbat_table)
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intersection_start, mapped_size, logical_address);
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continue;
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}
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m_dbat_mapped_entries.push_back({mapped_pointer, mapped_size});
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m_dbat_mapped_entries.push_back({mapped_pointer, mapped_size, logical_address});
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}
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m_logical_page_mappings[i] =
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@ -313,18 +310,12 @@ void MemoryManager::UpdateDBATMappings(const PowerPC::BatTable& dbat_table)
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}
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}
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void MemoryManager::UpdatePageTableMappings(const std::map<u32, u32>& page_mappings)
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void MemoryManager::AddPageTableMappings(const std::map<u32, u32>& mappings)
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{
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if (m_page_size > PowerPC::HW_PAGE_SIZE)
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return;
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for (auto& entry : m_page_table_mapped_entries)
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{
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m_arena.UnmapFromMemoryRegion(entry.mapped_pointer, entry.mapped_size);
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}
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m_page_table_mapped_entries.clear();
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for (const auto [logical_address, translated_address] : page_mappings)
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for (const auto [logical_address, translated_address] : mappings)
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{
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if (logical_address % m_page_alignment != 0)
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continue;
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@ -357,13 +348,38 @@ void MemoryManager::UpdatePageTableMappings(const std::map<u32, u32>& page_mappi
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intersection_start, mapped_size, logical_address);
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continue;
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}
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m_page_table_mapped_entries.push_back({mapped_pointer, mapped_size});
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m_page_table_mapped_entries.push_back({mapped_pointer, mapped_size, logical_address});
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}
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}
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}
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}
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}
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void MemoryManager::RemovePageTableMappings(const std::set<u32>& mappings)
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{
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if (m_page_size > PowerPC::HW_PAGE_SIZE)
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return;
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if (mappings.empty())
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return;
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std::erase_if(m_page_table_mapped_entries, [this, &mappings](const LogicalMemoryView& entry) {
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const bool remove = mappings.contains(entry.logical_address);
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if (remove)
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m_arena.UnmapFromMemoryRegion(entry.mapped_pointer, entry.mapped_size);
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return remove;
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});
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}
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void MemoryManager::RemoveAllPageTableMappings()
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{
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for (auto& entry : m_page_table_mapped_entries)
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{
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m_arena.UnmapFromMemoryRegion(entry.mapped_pointer, entry.mapped_size);
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}
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m_page_table_mapped_entries.clear();
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}
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void MemoryManager::DoState(PointerWrap& p)
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{
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const u32 current_ram_size = GetRamSize();
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@ -6,6 +6,7 @@
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#include <array>
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#include <map>
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#include <memory>
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#include <set>
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#include <span>
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#include <string>
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#include <vector>
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@ -55,6 +56,7 @@ struct LogicalMemoryView
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{
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void* mapped_pointer;
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u32 mapped_size;
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u32 logical_address;
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};
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class MemoryManager
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@ -101,7 +103,9 @@ public:
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void DoState(PointerWrap& p);
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void UpdateDBATMappings(const PowerPC::BatTable& dbat_table);
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void UpdatePageTableMappings(const std::map<u32, u32>& page_mappings);
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void AddPageTableMappings(const std::map<u32, u32>& mappings);
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void RemovePageTableMappings(const std::set<u32>& mappings);
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void RemoveAllPageTableMappings();
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void Clear();
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@ -33,19 +33,19 @@ constexpr Arm64Gen::ARM64Reg DISPATCHER_PC = Arm64Gen::ARM64Reg::W26;
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PowerPC::PowerPCState, elem); \
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_Pragma("GCC diagnostic pop") \
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}())
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#else
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#define PPCSTATE_OFF(elem) (offsetof(PowerPC::PowerPCState, elem))
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#endif
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#define PPCSTATE_OFF_ARRAY(elem, i) \
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(PPCSTATE_OFF(elem[0]) + sizeof(PowerPC::PowerPCState::elem[0]) * (i))
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#else
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#define PPCSTATE_OFF(elem) (offsetof(PowerPC::PowerPCState, elem))
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#define PPCSTATE_OFF_ARRAY(elem, i) \
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(offsetof(PowerPC::PowerPCState, elem[0]) + sizeof(PowerPC::PowerPCState::elem[0]) * (i))
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#endif
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#define PPCSTATE_OFF_STD_ARRAY(elem, i) \
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(PPCSTATE_OFF(elem) + sizeof(PowerPC::PowerPCState::elem[0]) * (i))
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#define PPCSTATE_OFF_GPR(i) PPCSTATE_OFF_ARRAY(gpr, i)
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#define PPCSTATE_OFF_CR(i) PPCSTATE_OFF_ARRAY(cr.fields, i)
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#define PPCSTATE_OFF_SR(i) PPCSTATE_OFF_ARRAY(sr, i)
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#define PPCSTATE_OFF_SR(i) PPCSTATE_OFF_STD_ARRAY(sr, i)
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#define PPCSTATE_OFF_SPR(i) PPCSTATE_OFF_ARRAY(spr, i)
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static_assert(std::is_same_v<decltype(PowerPC::PowerPCState::ps[0]), PowerPC::PairedSingle&>);
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@ -25,10 +25,17 @@
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#include "Core/PowerPC/MMU.h"
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#include <algorithm>
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#include <bit>
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#include <cstddef>
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#include <cstring>
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#include <memory>
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#include <string>
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#include <utility>
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#ifdef _M_X86_64
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#include <emmintrin.h>
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#endif
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#include "Common/Align.h"
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#include "Common/Assert.h"
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@ -61,18 +68,37 @@ MMU::~MMU() = default;
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void MMU::Reset()
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{
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m_page_table.clear();
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m_page_mappings.clear();
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#ifndef _ARCH_32
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m_memory.UpdatePageTableMappings(m_page_mappings);
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m_memory.RemoveAllPageTableMappings();
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#endif
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}
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void MMU::DoState(PointerWrap& p)
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void MMU::DoState(PointerWrap& p, bool sr_changed)
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{
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// Instead of storing m_page_mappings in savestates, we *could* recalculate it based on memory
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// Instead of storing m_page_table in savestates, we *could* refetch it from memory
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// here in DoState, but this could lead to us getting a more up-to-date set of page mappings
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// than we had when the savestate was created, which could be a problem for TAS determinism.
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p.Do(m_page_mappings);
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if (p.IsReadMode())
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{
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if (sr_changed)
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{
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// Non-incremental update of page table mappings.
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p.Do(m_page_table);
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SRUpdated();
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}
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else
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{
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// Incremental update of page table mappings.
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p.Do(m_temp_page_table);
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PageTableUpdated(m_temp_page_table);
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}
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}
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else
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{
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p.Do(m_page_table);
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}
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}
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// Overloaded byteswap functions, for use within the templated functions below.
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@ -1346,10 +1372,12 @@ void MMU::SDRUpdated()
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void MMU::SRUpdated()
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{
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if (m_ppc_state.msr.DR)
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PageTableUpdated();
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else
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m_ppc_state.pagetable_update_pending = true;
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#ifndef _ARCH_32
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// Our incremental handling of page table updates can't handle SR changing, so throw away all
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// existing mappings and then reparse the whole page table.
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m_memory.RemoveAllPageTableMappings();
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ReloadPageTable();
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#endif
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}
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enum class TLBLookupResult
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@ -1449,9 +1477,13 @@ void MMU::InvalidateTLBEntry(u32 address)
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void MMU::PageTableUpdated()
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{
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m_ppc_state.pagetable_update_pending = false;
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#ifndef _ARCH_32
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m_page_mappings.clear();
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#ifdef _ARCH_32
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// If a savestate is brought from a 64-bit system to a 32-bit system, clear m_page_table.
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// Not doing this means a stale m_page_table would stick around, which could be a problem
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// if the savestate is then brought to a 64-bit system again.
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m_page_table.clear();
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#else
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if (m_ppc_state.m_enable_dcache)
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{
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// Because fastmem isn't in use when accurate dcache emulation is enabled, setting up mappings
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@ -1460,9 +1492,8 @@ void MMU::PageTableUpdated()
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return;
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}
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const u32 page_table_mask = m_ppc_state.pagetable_hashmask;
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const u32 page_table_base = m_ppc_state.pagetable_base;
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const u32 page_table_end = (page_table_base | (page_table_mask << 6)) + (1 << 6);
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const u32 page_table_end = (page_table_base | (m_ppc_state.pagetable_hashmask << 6)) + (1 << 6);
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const u32 page_table_size = page_table_end - page_table_base;
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u8* page_table_view = m_system.GetMemory().GetPointerForRange(page_table_base, page_table_size);
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@ -1470,98 +1501,332 @@ void MMU::PageTableUpdated()
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{
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WARN_LOG_FMT(POWERPC, "Failed to read page table at {:#010x}-{:#010x}", page_table_base,
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page_table_end);
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m_memory.UpdatePageTableMappings(m_page_mappings);
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// Remove host mappings, because we no longer know if they're up to date.
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m_memory.RemoveAllPageTableMappings();
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// Because we removed host mappings, incremental updates won't work correctly.
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// Start over from scratch.
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m_page_table.clear();
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m_page_mappings.clear();
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return;
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}
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const auto read_page_table = [&](u32 H) {
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for (u32 i = 0; i <= page_table_mask; ++i)
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PageTableUpdated(std::span(page_table_view, page_table_size));
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#endif
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}
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#ifndef _ARCH_32
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void MMU::ReloadPageTable()
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{
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m_page_mappings.clear();
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m_temp_page_table.clear();
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std::swap(m_page_table, m_temp_page_table);
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PageTableUpdated(m_temp_page_table);
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}
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void MMU::PageTableUpdated(std::span<u8> page_table)
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{
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// PowerPC's priority order for PTEs that have the same logical adress is as follows:
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//
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// * Primary PTEs (H=0) take priority over secondary PTEs (H=1).
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// * If two PTEs have equal H values, they must be in the same PTEG due to how the hash
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// incorporates the logical address and H. The PTE located first in the PTEG takes priority.
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m_removed_mappings.clear();
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m_added_mappings.clear();
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if (m_page_table.size() != page_table.size())
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{
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m_page_table.clear();
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m_page_table.resize(page_table.size());
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}
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u8* old_page_table = m_page_table.data();
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u8* new_page_table = page_table.data();
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constexpr auto compare_64_bytes = [](const u8* a, const u8* b) -> bool {
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#ifdef _M_X86_64
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// MSVC (x64) doesn't want to optimize the memcmp call. This 64-byte compare is performance
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// critical in certain games like Spider-Man 2, so let's use our own vectorized version
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// instead.
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const __m128i a1 = _mm_load_si128(reinterpret_cast<const __m128i*>(a));
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const __m128i b1 = _mm_load_si128(reinterpret_cast<const __m128i*>(b));
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const __m128i cmp1 = _mm_cmpeq_epi8(a1, b1);
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const __m128i a2 = _mm_load_si128(reinterpret_cast<const __m128i*>(a + 0x10));
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const __m128i b2 = _mm_load_si128(reinterpret_cast<const __m128i*>(b + 0x10));
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const __m128i cmp2 = _mm_cmpeq_epi8(a2, b2);
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const __m128i cmp12 = _mm_and_si128(cmp1, cmp2);
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const __m128i a3 = _mm_load_si128(reinterpret_cast<const __m128i*>(a + 0x20));
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const __m128i b3 = _mm_load_si128(reinterpret_cast<const __m128i*>(b + 0x20));
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const __m128i cmp3 = _mm_cmpeq_epi8(a3, b3);
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const __m128i a4 = _mm_load_si128(reinterpret_cast<const __m128i*>(a + 0x30));
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const __m128i b4 = _mm_load_si128(reinterpret_cast<const __m128i*>(b + 0x30));
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const __m128i cmp4 = _mm_cmpeq_epi8(a4, b4);
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const __m128i cmp34 = _mm_and_si128(cmp3, cmp4);
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const __m128i cmp1234 = _mm_and_si128(cmp12, cmp34);
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return _mm_movemask_epi8(cmp1234) == 0xFFFF;
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#else
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return std::memcmp(std::assume_aligned<16>(a), std::assume_aligned<16>(b), 64) == 0;
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#endif
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};
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constexpr auto get_page_index = [](UPTE_Lo pte1, u32 hash) {
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u32 page_index_from_hash = hash ^ pte1.VSID;
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if (pte1.H)
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page_index_from_hash = ~page_index_from_hash;
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// Due to hash masking, the upper bits of page_index_from_hash might not match the actual
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// page index. But these bits fully overlap with the API (abbreviated page index), so we can
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// overwrite these bits with the API from pte1 and thereby get the correct page index.
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//
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// In other words: logical_address.API must be written to after logical_address.page_index!
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EffectiveAddress logical_address;
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logical_address.offset = 0;
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logical_address.page_index = page_index_from_hash;
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logical_address.API = pte1.API;
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return logical_address;
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};
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const auto fixup_shadowed_mappings = [this, &get_page_index, old_page_table, new_page_table](
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UPTE_Lo pte1, u32 page_table_offset, bool* run_pass_2) {
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DEBUG_ASSERT(pte1.V == 1);
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bool switched_to_secondary = false;
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while (true)
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{
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for (u32 j = 0; j < 8; ++j)
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const u32 big_endian_pte1 = Common::swap32(pte1.Hex);
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const u32 pteg_end = Common::AlignUp(page_table_offset, 64);
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for (u32 i = page_table_offset; i < pteg_end; i += 8)
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{
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const u32 pte_addr = (page_table_base | ((i & page_table_mask) << 6)) + j * 8;
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if (std::memcmp(new_page_table + i, &big_endian_pte1, sizeof(big_endian_pte1)) == 0)
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{
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// We've found a PTE that has V set and has the same logical address as the passed-in PTE.
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// The found PTE was previously skipped over because the passed-in PTE had priority, but
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// the passed-in PTE is being changed, so now we need to re-check the found PTE. This will
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// happen naturally later in the loop that's calling this function, but only if the 8-byte
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// memcmp reports that the PTE has changed. Therefore, if the PTE currently compares
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// equal, change an unused bit in the PTE.
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if (std::memcmp(old_page_table + i, new_page_table + i, 8) == 0)
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{
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UPTE_Hi pte2(Common::swap32(old_page_table + i + 4));
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pte2.reserved_1 = pte2.reserved_1 ^ 1;
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const u32 value = Common::swap32(pte2.Hex);
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std::memcpy(old_page_table + i + 4, &value, sizeof(value));
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UPTE_Lo pte1(Common::swap32(page_table_view + pte_addr - page_table_base));
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UPTE_Hi pte2(Common::swap32(page_table_view + pte_addr - page_table_base + 4));
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if (switched_to_secondary)
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*run_pass_2 = true;
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}
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return;
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}
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}
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if (!pte1.V)
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continue;
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if (pte1.H == 1)
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{
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// We've scanned the secondary PTEG. Nothing left to do.
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return;
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}
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else
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{
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// We've scanned the primary PTEG. Now let's scan the secondary PTEG.
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const EffectiveAddress ea = get_page_index(pte1, page_table_offset / 64);
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const u32 hash = ~(pte1.VSID ^ ea.page_index);
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pte1.H = 1;
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page_table_offset =
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(((hash & m_ppc_state.pagetable_hashmask) << 6) | m_ppc_state.pagetable_base) -
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m_ppc_state.pagetable_base;
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switched_to_secondary = true;
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}
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}
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};
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if (pte1.H != H)
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continue;
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const auto try_add_mapping = [this, &get_page_index, page_table](UPTE_Lo pte1, UPTE_Hi pte2,
|
||||
u32 page_table_offset) {
|
||||
EffectiveAddress logical_address = get_page_index(pte1, page_table_offset / 64);
|
||||
|
||||
for (u32 i = 0; i < std::size(m_ppc_state.sr); ++i)
|
||||
{
|
||||
const auto sr = UReg_SR{m_ppc_state.sr[i]};
|
||||
if (sr.VSID != pte1.VSID || sr.T != 0)
|
||||
continue;
|
||||
|
||||
logical_address.SR = i;
|
||||
|
||||
bool host_mapping = true;
|
||||
|
||||
const bool wi = (pte2.WIMG & 0b1100) != 0;
|
||||
if (wi)
|
||||
{
|
||||
// There are quirks related to uncached memory that can't be correctly emulated by fast
|
||||
// accesses, so we don't map uncached memory. (However, no software at all is known to
|
||||
// trigger these quirks through page address translation, only through block address
|
||||
// translation.)
|
||||
const bool wi = (pte2.WIMG & 0b1100) != 0;
|
||||
if (wi)
|
||||
continue;
|
||||
host_mapping = false;
|
||||
}
|
||||
else if (m_dbat_table[logical_address.Hex >> PowerPC::BAT_INDEX_SHIFT] &
|
||||
PowerPC::BAT_MAPPED_BIT)
|
||||
{
|
||||
// Block address translation takes priority over page address translation.
|
||||
host_mapping = false;
|
||||
}
|
||||
else if (m_power_pc.GetMemChecks().OverlapsMemcheck(logical_address.Hex,
|
||||
PowerPC::HW_PAGE_SIZE))
|
||||
{
|
||||
// Fast accesses don't support memchecks, so force slow accesses by removing fastmem
|
||||
// mappings for all overlapping virtual pages.
|
||||
host_mapping = false;
|
||||
}
|
||||
|
||||
// Due to hash masking, the upper bits of page_index_from_hash might not match the actual
|
||||
// page index. But these bits fully overlap with the API (abbreviated page index), so we can
|
||||
// overwrite these bits with the API from pte1 and thereby get the correct page index.
|
||||
//
|
||||
// In other words: logical_address.API must be written to after logical_address.page_index!
|
||||
u32 page_index_from_hash = i ^ pte1.VSID;
|
||||
if (pte1.H)
|
||||
page_index_from_hash = ~page_index_from_hash;
|
||||
EffectiveAddress logical_address;
|
||||
logical_address.offset = 0;
|
||||
logical_address.page_index = page_index_from_hash;
|
||||
logical_address.API = pte1.API;
|
||||
const u32 priority = (page_table_offset % 64 / 8) | (pte1.H << 3);
|
||||
const PageMapping page_mapping(pte2.RPN, host_mapping, priority);
|
||||
|
||||
for (u32 k = 0; k < std::size(m_ppc_state.sr); ++k)
|
||||
const auto it = m_page_mappings.find(logical_address.Hex);
|
||||
if (it != m_page_mappings.end()) [[unlikely]]
|
||||
{
|
||||
if (priority > it->second.priority)
|
||||
{
|
||||
const auto sr = UReg_SR{m_ppc_state.sr[k]};
|
||||
if (sr.VSID != pte1.VSID || sr.T != 0)
|
||||
continue;
|
||||
// An existing mapping has priority.
|
||||
continue;
|
||||
}
|
||||
else
|
||||
{
|
||||
// The new mapping has priority over an existing mapping. Replace the existing mapping.
|
||||
if (it->second.host_mapping)
|
||||
m_removed_mappings.emplace(it->first);
|
||||
it->second.Hex = page_mapping.Hex;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// There's no existing mapping for this logical address. Add a new mapping.
|
||||
m_page_mappings.emplace(logical_address.Hex, page_mapping);
|
||||
}
|
||||
|
||||
logical_address.SR = k;
|
||||
if (host_mapping)
|
||||
{
|
||||
const u32 physical_address = pte2.RPN << 12;
|
||||
m_added_mappings.emplace(logical_address.Hex, physical_address);
|
||||
|
||||
// Block address translation takes priority over page address translation.
|
||||
if (m_dbat_table[logical_address.Hex >> PowerPC::BAT_INDEX_SHIFT] &
|
||||
PowerPC::BAT_MAPPED_BIT)
|
||||
{
|
||||
continue;
|
||||
}
|
||||
// HACK: We set R and C, which indicate whether a page have been read from and written to
|
||||
// respectively, when a page is mapped rather than when it's actually accessed. The latter
|
||||
// is probably possible using some fault handling logic, but for now it seems like more
|
||||
// work than it's worth.
|
||||
if (!pte2.R || !pte2.C)
|
||||
{
|
||||
pte2.R = 1;
|
||||
pte2.C = 1;
|
||||
|
||||
// Fast accesses don't support memchecks, so force slow accesses by removing fastmem
|
||||
// mappings for all overlapping virtual pages.
|
||||
constexpr u32 logical_size = PowerPC::HW_PAGE_SIZE;
|
||||
if (m_power_pc.GetMemChecks().OverlapsMemcheck(logical_address.Hex, logical_size))
|
||||
continue;
|
||||
|
||||
const u32 physical_address = pte2.RPN << 12;
|
||||
|
||||
// Important: This doesn't overwrite anything already present in m_page_mappings.
|
||||
m_page_mappings.emplace(logical_address.Hex, physical_address);
|
||||
|
||||
// HACK: We set R and C, which indicate whether a page have been read from and written to
|
||||
// respectively, when a page is mapped rather than when it's actually accessed. The latter
|
||||
// is probably possible using some fault handling logic, but for now it seems like more
|
||||
// work than it's worth.
|
||||
if (!pte2.R || !pte2.C)
|
||||
{
|
||||
pte2.R = 1;
|
||||
pte2.C = 1;
|
||||
|
||||
const u32 pte2_swapped = Common::swap32(pte2.Hex);
|
||||
std::memcpy(page_table_view + pte_addr - page_table_base + 4, &pte2_swapped,
|
||||
sizeof(pte2_swapped));
|
||||
}
|
||||
const u32 pte2_swapped = Common::swap32(pte2.Hex);
|
||||
std::memcpy(page_table.data() + page_table_offset + 4, &pte2_swapped,
|
||||
sizeof(pte2_swapped));
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
// We need to read all H=0 PTEs first, because H=0 takes priority over H=1.
|
||||
read_page_table(0);
|
||||
read_page_table(1);
|
||||
bool run_pass_2 = false;
|
||||
|
||||
m_memory.UpdatePageTableMappings(m_page_mappings);
|
||||
#endif
|
||||
// Pass 1: Remove old mappings and add new primary (H=0) mappings.
|
||||
for (u32 i = 0; i < page_table.size(); i += 64)
|
||||
{
|
||||
if (compare_64_bytes(old_page_table + i, new_page_table + i)) [[likely]]
|
||||
continue;
|
||||
|
||||
for (u32 j = 0; j < 64; j += 8)
|
||||
{
|
||||
if (std::memcmp(old_page_table + i + j, new_page_table + i + j, 8) == 0) [[likely]]
|
||||
continue;
|
||||
|
||||
// Remove old mappings.
|
||||
UPTE_Lo old_pte1(Common::swap32(old_page_table + i + j));
|
||||
if (old_pte1.V)
|
||||
{
|
||||
const u32 priority = (j / 8) | (old_pte1.H << 3);
|
||||
EffectiveAddress logical_address = get_page_index(old_pte1, i / 64);
|
||||
|
||||
for (u32 k = 0; k < std::size(m_ppc_state.sr); ++k)
|
||||
{
|
||||
const auto sr = UReg_SR{m_ppc_state.sr[k]};
|
||||
if (sr.VSID != old_pte1.VSID || sr.T != 0)
|
||||
continue;
|
||||
|
||||
logical_address.SR = k;
|
||||
|
||||
const auto it = m_page_mappings.find(logical_address.Hex);
|
||||
if (it != m_page_mappings.end() && priority == it->second.priority)
|
||||
{
|
||||
if (it->second.host_mapping)
|
||||
m_removed_mappings.emplace(logical_address.Hex);
|
||||
m_page_mappings.erase(it);
|
||||
|
||||
// It's unlikely but theoretically possible that this was shadowing another PTE that's
|
||||
// using the same logical address but has a lower priority. If this happens, we must
|
||||
// make sure that we don't skip over that other PTE because of the 8-byte memcmp.
|
||||
fixup_shadowed_mappings(old_pte1, i + j, &run_pass_2);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Add new primary (H=0) mappings.
|
||||
UPTE_Lo new_pte1(Common::swap32(new_page_table + i + j));
|
||||
UPTE_Hi new_pte2(Common::swap32(new_page_table + i + j + 4));
|
||||
if (new_pte1.V)
|
||||
{
|
||||
if (new_pte1.H)
|
||||
{
|
||||
run_pass_2 = true;
|
||||
continue;
|
||||
}
|
||||
|
||||
try_add_mapping(new_pte1, new_pte2, i + j);
|
||||
}
|
||||
|
||||
// Update our copy of the page table.
|
||||
std::memcpy(old_page_table + i + j, new_page_table + i + j, 8);
|
||||
}
|
||||
}
|
||||
|
||||
// Pass 2: Add new secondary (H=1) mappings. This is a separate pass because before we can process
|
||||
// whether a mapping should be added, we first need to check all PTEs that have equal or higher
|
||||
// priority to see if their mappings should be removed. For adding primary mappings, this ordering
|
||||
// comes naturally from doing a linear scan of the page table from start to finish. But for adding
|
||||
// secondary mappings, the primary PTEG that has priority over a given secondary PTEG is in the
|
||||
// other half of the page table, so we need more than one pass through the page table. But most of
|
||||
// the time, there are no secondary mappings, letting us skip the second pass.
|
||||
if (run_pass_2) [[unlikely]]
|
||||
{
|
||||
for (u32 i = 0; i < page_table.size(); i += 64)
|
||||
{
|
||||
if (compare_64_bytes(old_page_table + i, new_page_table + i)) [[likely]]
|
||||
continue;
|
||||
|
||||
for (u32 j = 0; j < 64; j += 8)
|
||||
{
|
||||
if (std::memcmp(old_page_table + i + j, new_page_table + i + j, 8) == 0) [[likely]]
|
||||
continue;
|
||||
|
||||
UPTE_Lo new_pte1(Common::swap32(new_page_table + i + j));
|
||||
UPTE_Hi new_pte2(Common::swap32(new_page_table + i + j + 4));
|
||||
|
||||
// We don't need to check new_pte1.V and new_pte1.H. If the memcmp above returned nonzero,
|
||||
// pass 1 must have skipped running memcpy, which only happens if V and H are both set.
|
||||
try_add_mapping(new_pte1, new_pte2, i + j);
|
||||
|
||||
std::memcpy(old_page_table + i + j, new_page_table + i + j, 8);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (!m_removed_mappings.empty())
|
||||
m_memory.RemovePageTableMappings(m_removed_mappings);
|
||||
|
||||
if (!m_added_mappings.empty())
|
||||
m_memory.AddPageTableMappings(m_added_mappings);
|
||||
}
|
||||
#endif
|
||||
|
||||
void MMU::PageTableUpdatedFromJit(MMU* mmu)
|
||||
{
|
||||
|
|
@ -1794,7 +2059,11 @@ void MMU::DBATUpdated()
|
|||
|
||||
#ifndef _ARCH_32
|
||||
m_memory.UpdateDBATMappings(m_dbat_table);
|
||||
m_memory.UpdatePageTableMappings(m_page_mappings);
|
||||
|
||||
// Calling UpdateDBATMappings removes all fastmem page table mappings,
|
||||
// so we have to recreate them.
|
||||
if (!m_page_table.empty())
|
||||
ReloadPageTable();
|
||||
#endif
|
||||
|
||||
// IsOptimizable*Address and dcbz depends on the BAT mapping, so we need a flush here.
|
||||
|
|
|
|||
|
|
@ -7,7 +7,10 @@
|
|||
#include <cstddef>
|
||||
#include <map>
|
||||
#include <optional>
|
||||
#include <set>
|
||||
#include <span>
|
||||
#include <string>
|
||||
#include <vector>
|
||||
|
||||
#include "Common/BitField.h"
|
||||
#include "Common/CommonTypes.h"
|
||||
|
|
@ -120,7 +123,7 @@ public:
|
|||
~MMU();
|
||||
|
||||
void Reset();
|
||||
void DoState(PointerWrap& p);
|
||||
void DoState(PointerWrap& p, bool sr_changed);
|
||||
|
||||
// Routines for debugger UI, cheats, etc. to access emulated memory from the
|
||||
// perspective of the CPU. Not for use by core emulation routines.
|
||||
|
|
@ -300,6 +303,26 @@ private:
|
|||
explicit EffectiveAddress(u32 address) : Hex{address} {}
|
||||
};
|
||||
|
||||
union PageMapping
|
||||
{
|
||||
// A small priority number wins over a larger priority number.
|
||||
BitField<0, 11, u32> priority;
|
||||
// Whether we're allowed to create a host mapping for this mapping.
|
||||
BitField<11, 1, u32> host_mapping;
|
||||
// The physical address of the page.
|
||||
BitField<12, 20, u32> RPN;
|
||||
|
||||
u32 Hex = 0;
|
||||
|
||||
PageMapping() = default;
|
||||
PageMapping(u32 RPN_, bool host_mapping_, u32 priority_)
|
||||
{
|
||||
RPN = RPN_;
|
||||
host_mapping = host_mapping_;
|
||||
priority = priority_;
|
||||
}
|
||||
};
|
||||
|
||||
template <const XCheckTLBFlag flag>
|
||||
TranslateAddressResult TranslateAddress(u32 address);
|
||||
|
||||
|
|
@ -311,6 +334,11 @@ private:
|
|||
|
||||
void Memcheck(u32 address, u64 var, bool write, size_t size);
|
||||
|
||||
#ifndef _ARCH_32
|
||||
void ReloadPageTable();
|
||||
void PageTableUpdated(std::span<u8> page_table);
|
||||
#endif
|
||||
|
||||
void UpdateBATs(BatTable& bat_table, u32 base_spr);
|
||||
void UpdateFakeMMUBat(BatTable& bat_table, u32 start_addr);
|
||||
|
||||
|
|
@ -335,9 +363,18 @@ private:
|
|||
PowerPC::PowerPCState& m_ppc_state;
|
||||
|
||||
// STATE_TO_SAVE
|
||||
std::map<u32, u32> m_page_mappings;
|
||||
std::vector<u8> m_page_table;
|
||||
// END STATE_TO_SAVE
|
||||
|
||||
// This keeps track of all valid page table mappings in m_page_table.
|
||||
// The key is the logical address.
|
||||
std::map<u32, PageMapping> m_page_mappings;
|
||||
|
||||
// These are kept around just for their memory allocations. They are always cleared before use.
|
||||
std::vector<u8> m_temp_page_table;
|
||||
std::set<u32> m_removed_mappings;
|
||||
std::map<u32, u32> m_added_mappings;
|
||||
|
||||
BatTable m_ibat_table;
|
||||
BatTable m_dbat_table;
|
||||
};
|
||||
|
|
|
|||
|
|
@ -4,6 +4,7 @@
|
|||
#include "Core/PowerPC/PowerPC.h"
|
||||
|
||||
#include <algorithm>
|
||||
#include <array>
|
||||
#include <bit>
|
||||
#include <cstring>
|
||||
#include <type_traits>
|
||||
|
|
@ -80,6 +81,8 @@ void PowerPCManager::DoState(PointerWrap& p)
|
|||
// *((u64 *)&TL(m_ppc_state)) = SystemTimers::GetFakeTimeBase(); //works since we are little
|
||||
// endian and TL comes first :)
|
||||
|
||||
const std::array<u32, 16> old_sr = m_ppc_state.sr;
|
||||
|
||||
p.DoArray(m_ppc_state.gpr);
|
||||
p.Do(m_ppc_state.pc);
|
||||
p.Do(m_ppc_state.npc);
|
||||
|
|
@ -107,10 +110,10 @@ void PowerPCManager::DoState(PointerWrap& p)
|
|||
m_ppc_state.dCache.DoState(memory, p);
|
||||
|
||||
auto& mmu = m_system.GetMMU();
|
||||
mmu.DoState(p);
|
||||
|
||||
if (p.IsReadMode())
|
||||
{
|
||||
mmu.DoState(p, old_sr != m_ppc_state.sr);
|
||||
|
||||
if (!m_ppc_state.m_enable_dcache)
|
||||
{
|
||||
INFO_LOG_FMT(POWERPC, "Flushing data cache");
|
||||
|
|
@ -123,6 +126,10 @@ void PowerPCManager::DoState(PointerWrap& p)
|
|||
mmu.IBATUpdated();
|
||||
mmu.DBATUpdated();
|
||||
}
|
||||
else
|
||||
{
|
||||
mmu.DoState(p, false);
|
||||
}
|
||||
|
||||
// SystemTimers::DecrementerSet();
|
||||
// SystemTimers::TimeBaseSet();
|
||||
|
|
|
|||
|
|
@ -175,7 +175,7 @@ struct PowerPCState
|
|||
alignas(16) PairedSingle ps[32];
|
||||
#endif
|
||||
|
||||
u32 sr[16]{}; // Segment registers.
|
||||
std::array<u32, 16> sr{}; // Segment registers.
|
||||
|
||||
// special purpose registers - controls quantizers, DMA, and lots of other misc extensions.
|
||||
// also for power management, but we don't care about that.
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue