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Merge pull request #122 from lioncash/rename-default

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Rename the JIT function Default() to FallBackToInterpreter(). Communicates intent way better in terms of telling the reader what's going on.
This commit is contained in:
Matthew Parlane 2014-03-06 12:13:54 +13:00
commit e5b250fa79
40 changed files with 1700 additions and 1264 deletions
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4
Source/Core/Core/PowerPC/Jit64/Jit.cpp
View file

@ -199,7 +199,7 @@ void Jit64::Shutdown()
asm_routines.Shutdown(); asm_routines.Shutdown();
} }
// This is only called by Default() in this file. It will execute an instruction with the interpreter functions. // This is only called by FallBackToInterpreter() in this file. It will execute an instruction with the interpreter functions.
void Jit64::WriteCallInterpreter(UGeckoInstruction inst) void Jit64::WriteCallInterpreter(UGeckoInstruction inst)
{ {
gpr.Flush(FLUSH_ALL); gpr.Flush(FLUSH_ALL);
@ -218,7 +218,7 @@ void Jit64::unknown_instruction(UGeckoInstruction inst)
PanicAlert("unknown_instruction %08x - Fix me ;)", inst.hex); PanicAlert("unknown_instruction %08x - Fix me ;)", inst.hex);
} }
void Jit64::Default(UGeckoInstruction _inst) void Jit64::FallBackToInterpreter(UGeckoInstruction _inst)
{ {
WriteCallInterpreter(_inst.hex); WriteCallInterpreter(_inst.hex);
} }

2
Source/Core/Core/PowerPC/Jit64/Jit.h
View file

@ -113,7 +113,7 @@ public:
// OPCODES // OPCODES
void unknown_instruction(UGeckoInstruction _inst); void unknown_instruction(UGeckoInstruction _inst);
void Default(UGeckoInstruction _inst); void FallBackToInterpreter(UGeckoInstruction _inst);
void DoNothing(UGeckoInstruction _inst); void DoNothing(UGeckoInstruction _inst);
void HLEFunction(UGeckoInstruction _inst); void HLEFunction(UGeckoInstruction _inst);

488
Source/Core/Core/PowerPC/Jit64/Jit64_Tables.cpp
View file

@ -29,118 +29,118 @@ struct GekkoOPTemplate
static GekkoOPTemplate primarytable[] = static GekkoOPTemplate primarytable[] =
{ {
{4, &Jit64::DynaRunTable4}, //"RunTable4", OPTYPE_SUBTABLE | (4<<24), 0}}, {4, &Jit64::DynaRunTable4}, //"RunTable4", OPTYPE_SUBTABLE | (4<<24), 0}},
{19, &Jit64::DynaRunTable19}, //"RunTable19", OPTYPE_SUBTABLE | (19<<24), 0}}, {19, &Jit64::DynaRunTable19}, //"RunTable19", OPTYPE_SUBTABLE | (19<<24), 0}},
{31, &Jit64::DynaRunTable31}, //"RunTable31", OPTYPE_SUBTABLE | (31<<24), 0}}, {31, &Jit64::DynaRunTable31}, //"RunTable31", OPTYPE_SUBTABLE | (31<<24), 0}},
{59, &Jit64::DynaRunTable59}, //"RunTable59", OPTYPE_SUBTABLE | (59<<24), 0}}, {59, &Jit64::DynaRunTable59}, //"RunTable59", OPTYPE_SUBTABLE | (59<<24), 0}},
{63, &Jit64::DynaRunTable63}, //"RunTable63", OPTYPE_SUBTABLE | (63<<24), 0}}, {63, &Jit64::DynaRunTable63}, //"RunTable63", OPTYPE_SUBTABLE | (63<<24), 0}},
{16, &Jit64::bcx}, //"bcx", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {16, &Jit64::bcx}, //"bcx", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{18, &Jit64::bx}, //"bx", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {18, &Jit64::bx}, //"bx", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{1, &Jit64::HLEFunction}, //"HLEFunction", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {1, &Jit64::HLEFunction}, //"HLEFunction", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{2, &Jit64::Default}, //"DynaBlock", OPTYPE_SYSTEM, 0}}, {2, &Jit64::FallBackToInterpreter}, //"DynaBlock", OPTYPE_SYSTEM, 0}},
{3, &Jit64::twx}, //"twi", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {3, &Jit64::twx}, //"twi", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{17, &Jit64::sc}, //"sc", OPTYPE_SYSTEM, FL_ENDBLOCK, 1}}, {17, &Jit64::sc}, //"sc", OPTYPE_SYSTEM, FL_ENDBLOCK, 1}},
{7, &Jit64::mulli}, //"mulli", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_RC_BIT, 2}}, {7, &Jit64::mulli}, //"mulli", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_RC_BIT, 2}},
{8, &Jit64::subfic}, //"subfic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}}, {8, &Jit64::subfic}, //"subfic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}},
{10, &Jit64::cmpXX}, //"cmpli", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}}, {10, &Jit64::cmpXX}, //"cmpli", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}},
{11, &Jit64::cmpXX}, //"cmpi", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}}, {11, &Jit64::cmpXX}, //"cmpi", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}},
{12, &Jit64::reg_imm}, //"addic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}}, {12, &Jit64::reg_imm}, //"addic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}},
{13, &Jit64::reg_imm}, //"addic_rc", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CR0}}, {13, &Jit64::reg_imm}, //"addic_rc", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CR0}},
{14, &Jit64::reg_imm}, //"addi", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}}, {14, &Jit64::reg_imm}, //"addi", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}},
{15, &Jit64::reg_imm}, //"addis", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}}, {15, &Jit64::reg_imm}, //"addis", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}},
{20, &Jit64::rlwimix}, //"rlwimix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_A | FL_IN_S | FL_RC_BIT}}, {20, &Jit64::rlwimix}, //"rlwimix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_A | FL_IN_S | FL_RC_BIT}},
{21, &Jit64::rlwinmx}, //"rlwinmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, {21, &Jit64::rlwinmx}, //"rlwinmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
{23, &Jit64::rlwnmx}, //"rlwnmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_IN_B | FL_RC_BIT}}, {23, &Jit64::rlwnmx}, //"rlwnmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_IN_B | FL_RC_BIT}},
{24, &Jit64::reg_imm}, //"ori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, {24, &Jit64::reg_imm}, //"ori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
{25, &Jit64::reg_imm}, //"oris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, {25, &Jit64::reg_imm}, //"oris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
{26, &Jit64::reg_imm}, //"xori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, {26, &Jit64::reg_imm}, //"xori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
{27, &Jit64::reg_imm}, //"xoris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, {27, &Jit64::reg_imm}, //"xoris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
{28, &Jit64::reg_imm}, //"andi_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}}, {28, &Jit64::reg_imm}, //"andi_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}},
{29, &Jit64::reg_imm}, //"andis_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}}, {29, &Jit64::reg_imm}, //"andis_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}},
{32, &Jit64::lXXx}, //"lwz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, {32, &Jit64::lXXx}, //"lwz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
{33, &Jit64::lXXx}, //"lwzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {33, &Jit64::lXXx}, //"lwzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
{34, &Jit64::lXXx}, //"lbz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, {34, &Jit64::lXXx}, //"lbz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
{35, &Jit64::lXXx}, //"lbzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {35, &Jit64::lXXx}, //"lbzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
{40, &Jit64::lXXx}, //"lhz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, {40, &Jit64::lXXx}, //"lhz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
{41, &Jit64::lXXx}, //"lhzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {41, &Jit64::lXXx}, //"lhzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
{42, &Jit64::lXXx}, //"lha", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, {42, &Jit64::lXXx}, //"lha", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
{43, &Jit64::lXXx}, //"lhau", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {43, &Jit64::lXXx}, //"lhau", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
{44, &Jit64::stX}, //"sth", OPTYPE_STORE, FL_IN_A | FL_IN_S}}, {44, &Jit64::stX}, //"sth", OPTYPE_STORE, FL_IN_A | FL_IN_S}},
{45, &Jit64::stX}, //"sthu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}}, {45, &Jit64::stX}, //"sthu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
{36, &Jit64::stX}, //"stw", OPTYPE_STORE, FL_IN_A | FL_IN_S}}, {36, &Jit64::stX}, //"stw", OPTYPE_STORE, FL_IN_A | FL_IN_S}},
{37, &Jit64::stX}, //"stwu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}}, {37, &Jit64::stX}, //"stwu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
{38, &Jit64::stX}, //"stb", OPTYPE_STORE, FL_IN_A | FL_IN_S}}, {38, &Jit64::stX}, //"stb", OPTYPE_STORE, FL_IN_A | FL_IN_S}},
{39, &Jit64::stX}, //"stbu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}}, {39, &Jit64::stX}, //"stbu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
{46, &Jit64::lmw}, //"lmw", OPTYPE_SYSTEM, FL_EVIL, 10}}, {46, &Jit64::lmw}, //"lmw", OPTYPE_SYSTEM, FL_EVIL, 10}},
{47, &Jit64::stmw}, //"stmw", OPTYPE_SYSTEM, FL_EVIL, 10}}, {47, &Jit64::stmw}, //"stmw", OPTYPE_SYSTEM, FL_EVIL, 10}},
{48, &Jit64::lfs}, //"lfs", OPTYPE_LOADFP, FL_IN_A}}, {48, &Jit64::lfs}, //"lfs", OPTYPE_LOADFP, FL_IN_A}},
{49, &Jit64::Default}, //"lfsu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}}, {49, &Jit64::FallBackToInterpreter}, //"lfsu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}},
{50, &Jit64::lfd}, //"lfd", OPTYPE_LOADFP, FL_IN_A}}, {50, &Jit64::lfd}, //"lfd", OPTYPE_LOADFP, FL_IN_A}},
{51, &Jit64::Default}, //"lfdu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}}, {51, &Jit64::FallBackToInterpreter}, //"lfdu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}},
{52, &Jit64::stfs}, //"stfs", OPTYPE_STOREFP, FL_IN_A}}, {52, &Jit64::stfs}, //"stfs", OPTYPE_STOREFP, FL_IN_A}},
{53, &Jit64::stfs}, //"stfsu", OPTYPE_STOREFP, FL_OUT_A | FL_IN_A}}, {53, &Jit64::stfs}, //"stfsu", OPTYPE_STOREFP, FL_OUT_A | FL_IN_A}},
{54, &Jit64::stfd}, //"stfd", OPTYPE_STOREFP, FL_IN_A}}, {54, &Jit64::stfd}, //"stfd", OPTYPE_STOREFP, FL_IN_A}},
{55, &Jit64::Default}, //"stfdu", OPTYPE_STOREFP, FL_OUT_A | FL_IN_A}}, {55, &Jit64::FallBackToInterpreter}, //"stfdu", OPTYPE_STOREFP, FL_OUT_A | FL_IN_A}},
{56, &Jit64::psq_l}, //"psq_l", OPTYPE_PS, FL_IN_A}}, {56, &Jit64::psq_l}, //"psq_l", OPTYPE_PS, FL_IN_A}},
{57, &Jit64::psq_l}, //"psq_lu", OPTYPE_PS, FL_OUT_A | FL_IN_A}}, {57, &Jit64::psq_l}, //"psq_lu", OPTYPE_PS, FL_OUT_A | FL_IN_A}},
{60, &Jit64::psq_st}, //"psq_st", OPTYPE_PS, FL_IN_A}}, {60, &Jit64::psq_st}, //"psq_st", OPTYPE_PS, FL_IN_A}},
{61, &Jit64::psq_st}, //"psq_stu", OPTYPE_PS, FL_OUT_A | FL_IN_A}}, {61, &Jit64::psq_st}, //"psq_stu", OPTYPE_PS, FL_OUT_A | FL_IN_A}},
//missing: 0, 5, 6, 9, 22, 30, 62, 58 //missing: 0, 5, 6, 9, 22, 30, 62, 58
{0, &Jit64::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {0, &Jit64::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{5, &Jit64::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {5, &Jit64::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{6, &Jit64::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {6, &Jit64::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{9, &Jit64::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {9, &Jit64::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{22, &Jit64::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {22, &Jit64::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{30, &Jit64::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {30, &Jit64::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{62, &Jit64::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {62, &Jit64::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{58, &Jit64::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {58, &Jit64::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
}; };
static GekkoOPTemplate table4[] = static GekkoOPTemplate table4[] =
{ //SUBOP10 { //SUBOP10
{0, &Jit64::Default}, //"ps_cmpu0", OPTYPE_PS, FL_SET_CRn}}, {0, &Jit64::FallBackToInterpreter}, //"ps_cmpu0", OPTYPE_PS, FL_SET_CRn}},
{32, &Jit64::Default}, //"ps_cmpo0", OPTYPE_PS, FL_SET_CRn}}, {32, &Jit64::FallBackToInterpreter}, //"ps_cmpo0", OPTYPE_PS, FL_SET_CRn}},
{40, &Jit64::ps_sign}, //"ps_neg", OPTYPE_PS, FL_RC_BIT}}, {40, &Jit64::ps_sign}, //"ps_neg", OPTYPE_PS, FL_RC_BIT}},
{136, &Jit64::ps_sign}, //"ps_nabs", OPTYPE_PS, FL_RC_BIT}}, {136, &Jit64::ps_sign}, //"ps_nabs", OPTYPE_PS, FL_RC_BIT}},
{264, &Jit64::ps_sign}, //"ps_abs", OPTYPE_PS, FL_RC_BIT}}, {264, &Jit64::ps_sign}, //"ps_abs", OPTYPE_PS, FL_RC_BIT}},
{64, &Jit64::Default}, //"ps_cmpu1", OPTYPE_PS, FL_RC_BIT}}, {64, &Jit64::FallBackToInterpreter}, //"ps_cmpu1", OPTYPE_PS, FL_RC_BIT}},
{72, &Jit64::ps_mr}, //"ps_mr", OPTYPE_PS, FL_RC_BIT}}, {72, &Jit64::ps_mr}, //"ps_mr", OPTYPE_PS, FL_RC_BIT}},
{96, &Jit64::Default}, //"ps_cmpo1", OPTYPE_PS, FL_RC_BIT}}, {96, &Jit64::FallBackToInterpreter}, //"ps_cmpo1", OPTYPE_PS, FL_RC_BIT}},
{528, &Jit64::ps_mergeXX}, //"ps_merge00", OPTYPE_PS, FL_RC_BIT}}, {528, &Jit64::ps_mergeXX}, //"ps_merge00", OPTYPE_PS, FL_RC_BIT}},
{560, &Jit64::ps_mergeXX}, //"ps_merge01", OPTYPE_PS, FL_RC_BIT}}, {560, &Jit64::ps_mergeXX}, //"ps_merge01", OPTYPE_PS, FL_RC_BIT}},
{592, &Jit64::ps_mergeXX}, //"ps_merge10", OPTYPE_PS, FL_RC_BIT}}, {592, &Jit64::ps_mergeXX}, //"ps_merge10", OPTYPE_PS, FL_RC_BIT}},
{624, &Jit64::ps_mergeXX}, //"ps_merge11", OPTYPE_PS, FL_RC_BIT}}, {624, &Jit64::ps_mergeXX}, //"ps_merge11", OPTYPE_PS, FL_RC_BIT}},
{1014, &Jit64::Default}, //"dcbz_l", OPTYPE_SYSTEM, 0}}, {1014, &Jit64::FallBackToInterpreter}, //"dcbz_l", OPTYPE_SYSTEM, 0}},
}; };
static GekkoOPTemplate table4_2[] = static GekkoOPTemplate table4_2[] =
{ {
{10, &Jit64::ps_sum}, //"ps_sum0", OPTYPE_PS, 0}}, {10, &Jit64::ps_sum}, //"ps_sum0", OPTYPE_PS, 0}},
{11, &Jit64::ps_sum}, //"ps_sum1", OPTYPE_PS, 0}}, {11, &Jit64::ps_sum}, //"ps_sum1", OPTYPE_PS, 0}},
{12, &Jit64::ps_muls}, //"ps_muls0", OPTYPE_PS, 0}}, {12, &Jit64::ps_muls}, //"ps_muls0", OPTYPE_PS, 0}},
{13, &Jit64::ps_muls}, //"ps_muls1", OPTYPE_PS, 0}}, {13, &Jit64::ps_muls}, //"ps_muls1", OPTYPE_PS, 0}},
{14, &Jit64::ps_maddXX}, //"ps_madds0", OPTYPE_PS, 0}}, {14, &Jit64::ps_maddXX}, //"ps_madds0", OPTYPE_PS, 0}},
{15, &Jit64::ps_maddXX}, //"ps_madds1", OPTYPE_PS, 0}}, {15, &Jit64::ps_maddXX}, //"ps_madds1", OPTYPE_PS, 0}},
{18, &Jit64::ps_arith}, //"ps_div", OPTYPE_PS, 0, 16}}, {18, &Jit64::ps_arith}, //"ps_div", OPTYPE_PS, 0, 16}},
{20, &Jit64::ps_arith}, //"ps_sub", OPTYPE_PS, 0}}, {20, &Jit64::ps_arith}, //"ps_sub", OPTYPE_PS, 0}},
{21, &Jit64::ps_arith}, //"ps_add", OPTYPE_PS, 0}}, {21, &Jit64::ps_arith}, //"ps_add", OPTYPE_PS, 0}},
{23, &Jit64::ps_sel}, //"ps_sel", OPTYPE_PS, 0}}, {23, &Jit64::ps_sel}, //"ps_sel", OPTYPE_PS, 0}},
{24, &Jit64::ps_recip}, //"ps_res", OPTYPE_PS, 0}}, {24, &Jit64::ps_recip}, //"ps_res", OPTYPE_PS, 0}},
{25, &Jit64::ps_arith}, //"ps_mul", OPTYPE_PS, 0}}, {25, &Jit64::ps_arith}, //"ps_mul", OPTYPE_PS, 0}},
{26, &Jit64::ps_recip}, //"ps_rsqrte", OPTYPE_PS, 0, 1}}, {26, &Jit64::ps_recip}, //"ps_rsqrte", OPTYPE_PS, 0, 1}},
{28, &Jit64::ps_maddXX}, //"ps_msub", OPTYPE_PS, 0}}, {28, &Jit64::ps_maddXX}, //"ps_msub", OPTYPE_PS, 0}},
{29, &Jit64::ps_maddXX}, //"ps_madd", OPTYPE_PS, 0}}, {29, &Jit64::ps_maddXX}, //"ps_madd", OPTYPE_PS, 0}},
{30, &Jit64::ps_maddXX}, //"ps_nmsub", OPTYPE_PS, 0}}, {30, &Jit64::ps_maddXX}, //"ps_nmsub", OPTYPE_PS, 0}},
@ -150,221 +150,221 @@ static GekkoOPTemplate table4_2[] =
static GekkoOPTemplate table4_3[] = static GekkoOPTemplate table4_3[] =
{ {
{6, &Jit64::Default}, //"psq_lx", OPTYPE_PS, 0}}, {6, &Jit64::FallBackToInterpreter}, //"psq_lx", OPTYPE_PS, 0}},
{7, &Jit64::Default}, //"psq_stx", OPTYPE_PS, 0}}, {7, &Jit64::FallBackToInterpreter}, //"psq_stx", OPTYPE_PS, 0}},
{38, &Jit64::Default}, //"psq_lux", OPTYPE_PS, 0}}, {38, &Jit64::FallBackToInterpreter}, //"psq_lux", OPTYPE_PS, 0}},
{39, &Jit64::Default}, //"psq_stux", OPTYPE_PS, 0}}, {39, &Jit64::FallBackToInterpreter}, //"psq_stux", OPTYPE_PS, 0}},
}; };
static GekkoOPTemplate table19[] = static GekkoOPTemplate table19[] =
{ {
{528, &Jit64::bcctrx}, //"bcctrx", OPTYPE_BRANCH, FL_ENDBLOCK}}, {528, &Jit64::bcctrx}, //"bcctrx", OPTYPE_BRANCH, FL_ENDBLOCK}},
{16, &Jit64::bclrx}, //"bclrx", OPTYPE_BRANCH, FL_ENDBLOCK}}, {16, &Jit64::bclrx}, //"bclrx", OPTYPE_BRANCH, FL_ENDBLOCK}},
{257, &Jit64::crXXX}, //"crand", OPTYPE_CR, FL_EVIL}}, {257, &Jit64::crXXX}, //"crand", OPTYPE_CR, FL_EVIL}},
{129, &Jit64::crXXX}, //"crandc", OPTYPE_CR, FL_EVIL}}, {129, &Jit64::crXXX}, //"crandc", OPTYPE_CR, FL_EVIL}},
{289, &Jit64::crXXX}, //"creqv", OPTYPE_CR, FL_EVIL}}, {289, &Jit64::crXXX}, //"creqv", OPTYPE_CR, FL_EVIL}},
{225, &Jit64::crXXX}, //"crnand", OPTYPE_CR, FL_EVIL}}, {225, &Jit64::crXXX}, //"crnand", OPTYPE_CR, FL_EVIL}},
{33, &Jit64::crXXX}, //"crnor", OPTYPE_CR, FL_EVIL}}, {33, &Jit64::crXXX}, //"crnor", OPTYPE_CR, FL_EVIL}},
{449, &Jit64::crXXX}, //"cror", OPTYPE_CR, FL_EVIL}}, {449, &Jit64::crXXX}, //"cror", OPTYPE_CR, FL_EVIL}},
{417, &Jit64::crXXX}, //"crorc", OPTYPE_CR, FL_EVIL}}, {417, &Jit64::crXXX}, //"crorc", OPTYPE_CR, FL_EVIL}},
{193, &Jit64::crXXX}, //"crxor", OPTYPE_CR, FL_EVIL}}, {193, &Jit64::crXXX}, //"crxor", OPTYPE_CR, FL_EVIL}},
{150, &Jit64::DoNothing}, //"isync", OPTYPE_ICACHE, FL_EVIL}}, {150, &Jit64::DoNothing}, //"isync", OPTYPE_ICACHE, FL_EVIL}},
{0, &Jit64::mcrf}, //"mcrf", OPTYPE_SYSTEM, FL_EVIL}}, {0, &Jit64::mcrf}, //"mcrf", OPTYPE_SYSTEM, FL_EVIL}},
{50, &Jit64::rfi}, //"rfi", OPTYPE_SYSTEM, FL_ENDBLOCK | FL_CHECKEXCEPTIONS, 1}}, {50, &Jit64::rfi}, //"rfi", OPTYPE_SYSTEM, FL_ENDBLOCK | FL_CHECKEXCEPTIONS, 1}},
{18, &Jit64::Default}, //"rfid", OPTYPE_SYSTEM, FL_ENDBLOCK | FL_CHECKEXCEPTIONS}} {18, &Jit64::FallBackToInterpreter}, //"rfid", OPTYPE_SYSTEM, FL_ENDBLOCK | FL_CHECKEXCEPTIONS}}
}; };
static GekkoOPTemplate table31[] = static GekkoOPTemplate table31[] =
{ {
{28, &Jit64::boolX}, //"andx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {28, &Jit64::boolX}, //"andx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{60, &Jit64::boolX}, //"andcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {60, &Jit64::boolX}, //"andcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{444, &Jit64::boolX}, //"orx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {444, &Jit64::boolX}, //"orx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{124, &Jit64::boolX}, //"norx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {124, &Jit64::boolX}, //"norx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{316, &Jit64::boolX}, //"xorx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {316, &Jit64::boolX}, //"xorx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{412, &Jit64::boolX}, //"orcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {412, &Jit64::boolX}, //"orcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{476, &Jit64::boolX}, //"nandx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {476, &Jit64::boolX}, //"nandx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{284, &Jit64::boolX}, //"eqvx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {284, &Jit64::boolX}, //"eqvx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{0, &Jit64::cmpXX}, //"cmp", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}}, {0, &Jit64::cmpXX}, //"cmp", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}},
{32, &Jit64::cmpXX}, //"cmpl", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}}, {32, &Jit64::cmpXX}, //"cmpl", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}},
{26, &Jit64::cntlzwx}, //"cntlzwx",OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, {26, &Jit64::cntlzwx}, //"cntlzwx",OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
{922, &Jit64::extshx}, //"extshx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, {922, &Jit64::extshx}, //"extshx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
{954, &Jit64::extsbx}, //"extsbx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, {954, &Jit64::extsbx}, //"extsbx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
{536, &Jit64::srwx}, //"srwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, {536, &Jit64::srwx}, //"srwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
{792, &Jit64::srawx}, //"srawx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, {792, &Jit64::srawx}, //"srawx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
{824, &Jit64::srawix}, //"srawix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, {824, &Jit64::srawix}, //"srawix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
{24, &Jit64::slwx}, //"slwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, {24, &Jit64::slwx}, //"slwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
{54, &Jit64::dcbst}, //"dcbst", OPTYPE_DCACHE, 0, 4}}, {54, &Jit64::dcbst}, //"dcbst", OPTYPE_DCACHE, 0, 4}},
{86, &Jit64::Default}, //"dcbf", OPTYPE_DCACHE, 0, 4}}, {86, &Jit64::FallBackToInterpreter}, //"dcbf", OPTYPE_DCACHE, 0, 4}},
{246, &Jit64::DoNothing}, //"dcbtst", OPTYPE_DCACHE, 0, 1}}, {246, &Jit64::DoNothing}, //"dcbtst", OPTYPE_DCACHE, 0, 1}},
{278, &Jit64::DoNothing}, //"dcbt", OPTYPE_DCACHE, 0, 1}}, {278, &Jit64::DoNothing}, //"dcbt", OPTYPE_DCACHE, 0, 1}},
{470, &Jit64::Default}, //"dcbi", OPTYPE_DCACHE, 0, 4}}, {470, &Jit64::FallBackToInterpreter}, //"dcbi", OPTYPE_DCACHE, 0, 4}},
{758, &Jit64::DoNothing}, //"dcba", OPTYPE_DCACHE, 0, 4}}, {758, &Jit64::DoNothing}, //"dcba", OPTYPE_DCACHE, 0, 4}},
{1014, &Jit64::dcbz}, //"dcbz", OPTYPE_DCACHE, 0, 4}}, {1014, &Jit64::dcbz}, //"dcbz", OPTYPE_DCACHE, 0, 4}},
//load word //load word
{23, &Jit64::lXXx}, //"lwzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {23, &Jit64::lXXx}, //"lwzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{55, &Jit64::lXXx}, //"lwzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, {55, &Jit64::lXXx}, //"lwzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
//load halfword //load halfword
{279, &Jit64::lXXx}, //"lhzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {279, &Jit64::lXXx}, //"lhzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{311, &Jit64::lXXx}, //"lhzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, {311, &Jit64::lXXx}, //"lhzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
//load halfword signextend //load halfword signextend
{343, &Jit64::lXXx}, //"lhax", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {343, &Jit64::lXXx}, //"lhax", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{375, &Jit64::lXXx}, //"lhaux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, {375, &Jit64::lXXx}, //"lhaux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
//load byte //load byte
{87, &Jit64::lXXx}, //"lbzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {87, &Jit64::lXXx}, //"lbzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{119, &Jit64::lXXx}, //"lbzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, {119, &Jit64::lXXx}, //"lbzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
//load byte reverse //load byte reverse
{534, &Jit64::Default}, //"lwbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {534, &Jit64::FallBackToInterpreter}, //"lwbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{790, &Jit64::Default}, //"lhbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {790, &Jit64::FallBackToInterpreter}, //"lhbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
// Conditional load/store (Wii SMP) // Conditional load/store (Wii SMP)
{150, &Jit64::Default}, //"stwcxd", OPTYPE_STORE, FL_EVIL | FL_SET_CR0}}, {150, &Jit64::FallBackToInterpreter}, //"stwcxd", OPTYPE_STORE, FL_EVIL | FL_SET_CR0}},
{20, &Jit64::Default}, //"lwarx", OPTYPE_LOAD, FL_EVIL | FL_OUT_D | FL_IN_A0B | FL_SET_CR0}}, {20, &Jit64::FallBackToInterpreter}, //"lwarx", OPTYPE_LOAD, FL_EVIL | FL_OUT_D | FL_IN_A0B | FL_SET_CR0}},
//load string (interpret these) //load string (interpret these)
{533, &Jit64::Default}, //"lswx", OPTYPE_LOAD, FL_EVIL | FL_IN_A | FL_OUT_D}}, {533, &Jit64::FallBackToInterpreter}, //"lswx", OPTYPE_LOAD, FL_EVIL | FL_IN_A | FL_OUT_D}},
{597, &Jit64::Default}, //"lswi", OPTYPE_LOAD, FL_EVIL | FL_IN_AB | FL_OUT_D}}, {597, &Jit64::FallBackToInterpreter}, //"lswi", OPTYPE_LOAD, FL_EVIL | FL_IN_AB | FL_OUT_D}},
//store word //store word
{151, &Jit64::stXx}, //"stwx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, {151, &Jit64::stXx}, //"stwx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}},
{183, &Jit64::stXx}, //"stwux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}}, {183, &Jit64::stXx}, //"stwux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}},
//store halfword //store halfword
{407, &Jit64::stXx}, //"sthx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, {407, &Jit64::stXx}, //"sthx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}},
{439, &Jit64::stXx}, //"sthux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}}, {439, &Jit64::stXx}, //"sthux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}},
//store byte //store byte
{215, &Jit64::stXx}, //"stbx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, {215, &Jit64::stXx}, //"stbx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}},
{247, &Jit64::stXx}, //"stbux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}}, {247, &Jit64::stXx}, //"stbux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}},
//store bytereverse //store bytereverse
{662, &Jit64::Default}, //"stwbrx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, {662, &Jit64::FallBackToInterpreter}, //"stwbrx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}},
{918, &Jit64::Default}, //"sthbrx", OPTYPE_STORE, FL_IN_A | FL_IN_B}}, {918, &Jit64::FallBackToInterpreter}, //"sthbrx", OPTYPE_STORE, FL_IN_A | FL_IN_B}},
{661, &Jit64::Default}, //"stswx", OPTYPE_STORE, FL_EVIL}}, {661, &Jit64::FallBackToInterpreter}, //"stswx", OPTYPE_STORE, FL_EVIL}},
{725, &Jit64::Default}, //"stswi", OPTYPE_STORE, FL_EVIL}}, {725, &Jit64::FallBackToInterpreter}, //"stswi", OPTYPE_STORE, FL_EVIL}},
// fp load/store // fp load/store
{535, &Jit64::lfsx}, //"lfsx", OPTYPE_LOADFP, FL_IN_A0 | FL_IN_B}}, {535, &Jit64::lfsx}, //"lfsx", OPTYPE_LOADFP, FL_IN_A0 | FL_IN_B}},
{567, &Jit64::Default}, //"lfsux", OPTYPE_LOADFP, FL_IN_A | FL_IN_B}}, {567, &Jit64::FallBackToInterpreter}, //"lfsux", OPTYPE_LOADFP, FL_IN_A | FL_IN_B}},
{599, &Jit64::Default}, //"lfdx", OPTYPE_LOADFP, FL_IN_A0 | FL_IN_B}}, {599, &Jit64::FallBackToInterpreter}, //"lfdx", OPTYPE_LOADFP, FL_IN_A0 | FL_IN_B}},
{631, &Jit64::Default}, //"lfdux", OPTYPE_LOADFP, FL_IN_A | FL_IN_B}}, {631, &Jit64::FallBackToInterpreter}, //"lfdux", OPTYPE_LOADFP, FL_IN_A | FL_IN_B}},
{663, &Jit64::stfsx}, //"stfsx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}}, {663, &Jit64::stfsx}, //"stfsx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}},
{695, &Jit64::Default}, //"stfsux", OPTYPE_STOREFP, FL_IN_A | FL_IN_B}}, {695, &Jit64::FallBackToInterpreter}, //"stfsux", OPTYPE_STOREFP, FL_IN_A | FL_IN_B}},
{727, &Jit64::Default}, //"stfdx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}}, {727, &Jit64::FallBackToInterpreter}, //"stfdx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}},
{759, &Jit64::Default}, //"stfdux", OPTYPE_STOREFP, FL_IN_A | FL_IN_B}}, {759, &Jit64::FallBackToInterpreter}, //"stfdux", OPTYPE_STOREFP, FL_IN_A | FL_IN_B}},
{983, &Jit64::Default}, //"stfiwx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}}, {983, &Jit64::FallBackToInterpreter}, //"stfiwx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}},
{19, &Jit64::mfcr}, //"mfcr", OPTYPE_SYSTEM, FL_OUT_D}}, {19, &Jit64::mfcr}, //"mfcr", OPTYPE_SYSTEM, FL_OUT_D}},
{83, &Jit64::mfmsr}, //"mfmsr", OPTYPE_SYSTEM, FL_OUT_D}}, {83, &Jit64::mfmsr}, //"mfmsr", OPTYPE_SYSTEM, FL_OUT_D}},
{144, &Jit64::mtcrf}, //"mtcrf", OPTYPE_SYSTEM, 0}}, {144, &Jit64::mtcrf}, //"mtcrf", OPTYPE_SYSTEM, 0}},
{146, &Jit64::mtmsr}, //"mtmsr", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {146, &Jit64::mtmsr}, //"mtmsr", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{210, &Jit64::Default}, //"mtsr", OPTYPE_SYSTEM, 0}}, {210, &Jit64::FallBackToInterpreter}, //"mtsr", OPTYPE_SYSTEM, 0}},
{242, &Jit64::Default}, //"mtsrin", OPTYPE_SYSTEM, 0}}, {242, &Jit64::FallBackToInterpreter}, //"mtsrin", OPTYPE_SYSTEM, 0}},
{339, &Jit64::mfspr}, //"mfspr", OPTYPE_SPR, FL_OUT_D}}, {339, &Jit64::mfspr}, //"mfspr", OPTYPE_SPR, FL_OUT_D}},
{467, &Jit64::mtspr}, //"mtspr", OPTYPE_SPR, 0, 2}}, {467, &Jit64::mtspr}, //"mtspr", OPTYPE_SPR, 0, 2}},
{371, &Jit64::mftb}, //"mftb", OPTYPE_SYSTEM, FL_OUT_D | FL_TIMER}}, {371, &Jit64::mftb}, //"mftb", OPTYPE_SYSTEM, FL_OUT_D | FL_TIMER}},
{512, &Jit64::mcrxr}, //"mcrxr", OPTYPE_SYSTEM, 0}}, {512, &Jit64::mcrxr}, //"mcrxr", OPTYPE_SYSTEM, 0}},
{595, &Jit64::Default}, //"mfsr", OPTYPE_SYSTEM, FL_OUT_D, 2}}, {595, &Jit64::FallBackToInterpreter}, //"mfsr", OPTYPE_SYSTEM, FL_OUT_D, 2}},
{659, &Jit64::Default}, //"mfsrin", OPTYPE_SYSTEM, FL_OUT_D, 2}}, {659, &Jit64::FallBackToInterpreter}, //"mfsrin", OPTYPE_SYSTEM, FL_OUT_D, 2}},
{4, &Jit64::twx}, //"tw", OPTYPE_SYSTEM, FL_ENDBLOCK, 1}}, {4, &Jit64::twx}, //"tw", OPTYPE_SYSTEM, FL_ENDBLOCK, 1}},
{598, &Jit64::DoNothing}, //"sync", OPTYPE_SYSTEM, 0, 2}}, {598, &Jit64::DoNothing}, //"sync", OPTYPE_SYSTEM, 0, 2}},
{982, &Jit64::icbi}, //"icbi", OPTYPE_SYSTEM, FL_ENDBLOCK, 3}}, {982, &Jit64::icbi}, //"icbi", OPTYPE_SYSTEM, FL_ENDBLOCK, 3}},
// Unused instructions on GC // Unused instructions on GC
{310, &Jit64::Default}, //"eciwx", OPTYPE_INTEGER, FL_RC_BIT}}, {310, &Jit64::FallBackToInterpreter}, //"eciwx", OPTYPE_INTEGER, FL_RC_BIT}},
{438, &Jit64::Default}, //"ecowx", OPTYPE_INTEGER, FL_RC_BIT}}, {438, &Jit64::FallBackToInterpreter}, //"ecowx", OPTYPE_INTEGER, FL_RC_BIT}},
{854, &Jit64::Default}, //"eieio", OPTYPE_INTEGER, FL_RC_BIT}}, {854, &Jit64::FallBackToInterpreter}, //"eieio", OPTYPE_INTEGER, FL_RC_BIT}},
{306, &Jit64::Default}, //"tlbie", OPTYPE_SYSTEM, 0}}, {306, &Jit64::FallBackToInterpreter}, //"tlbie", OPTYPE_SYSTEM, 0}},
{370, &Jit64::Default}, //"tlbia", OPTYPE_SYSTEM, 0}}, {370, &Jit64::FallBackToInterpreter}, //"tlbia", OPTYPE_SYSTEM, 0}},
{566, &Jit64::Default}, //"tlbsync", OPTYPE_SYSTEM, 0}}, {566, &Jit64::FallBackToInterpreter}, //"tlbsync", OPTYPE_SYSTEM, 0}},
}; };
static GekkoOPTemplate table31_2[] = static GekkoOPTemplate table31_2[] =
{ {
{266, &Jit64::addx}, //"addx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {266, &Jit64::addx}, //"addx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{778, &Jit64::addx}, //"addx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {778, &Jit64::addx}, //"addx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{10, &Jit64::addcx}, //"addcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}}, {10, &Jit64::addcx}, //"addcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}},
{522, &Jit64::addcx}, //"addcox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}}, {522, &Jit64::addcx}, //"addcox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}},
{138, &Jit64::addex}, //"addex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {138, &Jit64::addex}, //"addex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{650, &Jit64::addex}, //"addeox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {650, &Jit64::addex}, //"addeox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{234, &Jit64::addmex}, //"addmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {234, &Jit64::addmex}, //"addmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{202, &Jit64::addzex}, //"addzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {202, &Jit64::addzex}, //"addzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{491, &Jit64::divwx}, //"divwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}}, {491, &Jit64::divwx}, //"divwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}},
{1003, &Jit64::divwx}, //"divwox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}}, {1003, &Jit64::divwx}, //"divwox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}},
{459, &Jit64::divwux}, //"divwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}}, {459, &Jit64::divwux}, //"divwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}},
{971, &Jit64::divwux}, //"divwuox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}}, {971, &Jit64::divwux}, //"divwuox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}},
{75, &Jit64::Default}, //"mulhwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, {75, &Jit64::FallBackToInterpreter}, //"mulhwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
{11, &Jit64::mulhwux}, //"mulhwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, {11, &Jit64::mulhwux}, //"mulhwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
{235, &Jit64::mullwx}, //"mullwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, {235, &Jit64::mullwx}, //"mullwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
{747, &Jit64::mullwx}, //"mullwox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, {747, &Jit64::mullwx}, //"mullwox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
{104, &Jit64::negx}, //"negx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {104, &Jit64::negx}, //"negx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{40, &Jit64::subfx}, //"subfx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {40, &Jit64::subfx}, //"subfx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{552, &Jit64::subfx}, //"subox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {552, &Jit64::subfx}, //"subox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{8, &Jit64::subfcx}, //"subfcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}}, {8, &Jit64::subfcx}, //"subfcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}},
{520, &Jit64::subfcx}, //"subfcox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}}, {520, &Jit64::subfcx}, //"subfcox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}},
{136, &Jit64::subfex}, //"subfex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {136, &Jit64::subfex}, //"subfex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{232, &Jit64::subfmex}, //"subfmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {232, &Jit64::subfmex}, //"subfmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{200, &Jit64::subfzex}, //"subfzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {200, &Jit64::subfzex}, //"subfzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
}; };
static GekkoOPTemplate table59[] = static GekkoOPTemplate table59[] =
{ {
{18, &Jit64::fp_arith}, //{"fdivsx", OPTYPE_FPU, FL_RC_BIT_F, 16}}, {18, &Jit64::fp_arith}, //{"fdivsx", OPTYPE_FPU, FL_RC_BIT_F, 16}},
{20, &Jit64::fp_arith}, //"fsubsx", OPTYPE_FPU, FL_RC_BIT_F}}, {20, &Jit64::fp_arith}, //"fsubsx", OPTYPE_FPU, FL_RC_BIT_F}},
{21, &Jit64::fp_arith}, //"faddsx", OPTYPE_FPU, FL_RC_BIT_F}}, {21, &Jit64::fp_arith}, //"faddsx", OPTYPE_FPU, FL_RC_BIT_F}},
// {22, &Jit64::Default}, //"fsqrtsx", OPTYPE_FPU, FL_RC_BIT_F}}, // Not implemented on gekko // {22, &Jit64::FallBackToInterpreter}, //"fsqrtsx", OPTYPE_FPU, FL_RC_BIT_F}}, // Not implemented on gekko
{24, &Jit64::Default}, //"fresx", OPTYPE_FPU, FL_RC_BIT_F}}, {24, &Jit64::FallBackToInterpreter}, //"fresx", OPTYPE_FPU, FL_RC_BIT_F}},
{25, &Jit64::fp_arith}, //"fmulsx", OPTYPE_FPU, FL_RC_BIT_F}}, {25, &Jit64::fp_arith}, //"fmulsx", OPTYPE_FPU, FL_RC_BIT_F}},
{28, &Jit64::fmaddXX}, //"fmsubsx", OPTYPE_FPU, FL_RC_BIT_F}}, {28, &Jit64::fmaddXX}, //"fmsubsx", OPTYPE_FPU, FL_RC_BIT_F}},
{29, &Jit64::fmaddXX}, //"fmaddsx", OPTYPE_FPU, FL_RC_BIT_F}}, {29, &Jit64::fmaddXX}, //"fmaddsx", OPTYPE_FPU, FL_RC_BIT_F}},
{30, &Jit64::fmaddXX}, //"fnmsubsx", OPTYPE_FPU, FL_RC_BIT_F}}, {30, &Jit64::fmaddXX}, //"fnmsubsx", OPTYPE_FPU, FL_RC_BIT_F}},
{31, &Jit64::fmaddXX}, //"fnmaddsx", OPTYPE_FPU, FL_RC_BIT_F}}, {31, &Jit64::fmaddXX}, //"fnmaddsx", OPTYPE_FPU, FL_RC_BIT_F}},
}; };
static GekkoOPTemplate table63[] = static GekkoOPTemplate table63[] =
{ {
{264, &Jit64::fsign}, //"fabsx", OPTYPE_FPU, FL_RC_BIT_F}}, {264, &Jit64::fsign}, //"fabsx", OPTYPE_FPU, FL_RC_BIT_F}},
{32, &Jit64::fcmpx}, //"fcmpo", OPTYPE_FPU, FL_RC_BIT_F}}, {32, &Jit64::fcmpx}, //"fcmpo", OPTYPE_FPU, FL_RC_BIT_F}},
{0, &Jit64::fcmpx}, //"fcmpu", OPTYPE_FPU, FL_RC_BIT_F}}, {0, &Jit64::fcmpx}, //"fcmpu", OPTYPE_FPU, FL_RC_BIT_F}},
{14, &Jit64::Default}, //"fctiwx", OPTYPE_FPU, FL_RC_BIT_F}}, {14, &Jit64::FallBackToInterpreter}, //"fctiwx", OPTYPE_FPU, FL_RC_BIT_F}},
{15, &Jit64::Default}, //"fctiwzx", OPTYPE_FPU, FL_RC_BIT_F}}, {15, &Jit64::FallBackToInterpreter}, //"fctiwzx", OPTYPE_FPU, FL_RC_BIT_F}},
{72, &Jit64::fmrx}, //"fmrx", OPTYPE_FPU, FL_RC_BIT_F}}, {72, &Jit64::fmrx}, //"fmrx", OPTYPE_FPU, FL_RC_BIT_F}},
{136, &Jit64::fsign}, //"fnabsx", OPTYPE_FPU, FL_RC_BIT_F}}, {136, &Jit64::fsign}, //"fnabsx", OPTYPE_FPU, FL_RC_BIT_F}},
{40, &Jit64::fsign}, //"fnegx", OPTYPE_FPU, FL_RC_BIT_F}}, {40, &Jit64::fsign}, //"fnegx", OPTYPE_FPU, FL_RC_BIT_F}},
{12, &Jit64::Default}, //"frspx", OPTYPE_FPU, FL_RC_BIT_F}}, {12, &Jit64::FallBackToInterpreter}, //"frspx", OPTYPE_FPU, FL_RC_BIT_F}},
{64, &Jit64::Default}, //"mcrfs", OPTYPE_SYSTEMFP, 0}}, {64, &Jit64::FallBackToInterpreter}, //"mcrfs", OPTYPE_SYSTEMFP, 0}},
{583, &Jit64::Default}, //"mffsx", OPTYPE_SYSTEMFP, 0}}, {583, &Jit64::FallBackToInterpreter}, //"mffsx", OPTYPE_SYSTEMFP, 0}},
{70, &Jit64::Default}, //"mtfsb0x", OPTYPE_SYSTEMFP, 0, 2}}, {70, &Jit64::FallBackToInterpreter}, //"mtfsb0x", OPTYPE_SYSTEMFP, 0, 2}},
{38, &Jit64::Default}, //"mtfsb1x", OPTYPE_SYSTEMFP, 0, 2}}, {38, &Jit64::FallBackToInterpreter}, //"mtfsb1x", OPTYPE_SYSTEMFP, 0, 2}},
{134, &Jit64::Default}, //"mtfsfix", OPTYPE_SYSTEMFP, 0, 2}}, {134, &Jit64::FallBackToInterpreter}, //"mtfsfix", OPTYPE_SYSTEMFP, 0, 2}},
{711, &Jit64::Default}, //"mtfsfx", OPTYPE_SYSTEMFP, 0, 2}}, {711, &Jit64::FallBackToInterpreter}, //"mtfsfx", OPTYPE_SYSTEMFP, 0, 2}},
}; };
static GekkoOPTemplate table63_2[] = static GekkoOPTemplate table63_2[] =
{ {
{18, &Jit64::fp_arith}, //"fdivx", OPTYPE_FPU, FL_RC_BIT_F, 30}}, {18, &Jit64::fp_arith}, //"fdivx", OPTYPE_FPU, FL_RC_BIT_F, 30}},
{20, &Jit64::fp_arith}, //"fsubx", OPTYPE_FPU, FL_RC_BIT_F}}, {20, &Jit64::fp_arith}, //"fsubx", OPTYPE_FPU, FL_RC_BIT_F}},
{21, &Jit64::fp_arith}, //"faddx", OPTYPE_FPU, FL_RC_BIT_F}}, {21, &Jit64::fp_arith}, //"faddx", OPTYPE_FPU, FL_RC_BIT_F}},
{22, &Jit64::Default}, //"fsqrtx", OPTYPE_FPU, FL_RC_BIT_F}}, {22, &Jit64::FallBackToInterpreter}, //"fsqrtx", OPTYPE_FPU, FL_RC_BIT_F}},
{23, &Jit64::Default}, //"fselx", OPTYPE_FPU, FL_RC_BIT_F}}, {23, &Jit64::FallBackToInterpreter}, //"fselx", OPTYPE_FPU, FL_RC_BIT_F}},
{25, &Jit64::fp_arith}, //"fmulx", OPTYPE_FPU, FL_RC_BIT_F}}, {25, &Jit64::fp_arith}, //"fmulx", OPTYPE_FPU, FL_RC_BIT_F}},
{26, &Jit64::frsqrtex}, //"frsqrtex", OPTYPE_FPU, FL_RC_BIT_F}}, {26, &Jit64::frsqrtex}, //"frsqrtex", OPTYPE_FPU, FL_RC_BIT_F}},
{28, &Jit64::fmaddXX}, //"fmsubx", OPTYPE_FPU, FL_RC_BIT_F}}, {28, &Jit64::fmaddXX}, //"fmsubx", OPTYPE_FPU, FL_RC_BIT_F}},
{29, &Jit64::fmaddXX}, //"fmaddx", OPTYPE_FPU, FL_RC_BIT_F}}, {29, &Jit64::fmaddXX}, //"fmaddx", OPTYPE_FPU, FL_RC_BIT_F}},
{30, &Jit64::fmaddXX}, //"fnmsubx", OPTYPE_FPU, FL_RC_BIT_F}}, {30, &Jit64::fmaddXX}, //"fnmsubx", OPTYPE_FPU, FL_RC_BIT_F}},
{31, &Jit64::fmaddXX}, //"fnmaddx", OPTYPE_FPU, FL_RC_BIT_F}}, {31, &Jit64::fmaddXX}, //"fnmaddx", OPTYPE_FPU, FL_RC_BIT_F}},
}; };
namespace Jit64Tables namespace Jit64Tables

71
Source/Core/Core/PowerPC/Jit64/Jit_FloatingPoint.cpp
View file

@ -75,13 +75,18 @@ void Jit64::fp_arith(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc) {
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
// Only the interpreter has "proper" support for (some) FP flags // Only the interpreter has "proper" support for (some) FP flags
if (inst.SUBOP5 == 25 && Core::g_CoreStartupParameter.bEnableFPRF) { if (inst.SUBOP5 == 25 && Core::g_CoreStartupParameter.bEnableFPRF)
Default(inst); return; {
FallBackToInterpreter(inst);
return;
} }
bool single = inst.OPCD == 59; bool single = inst.OPCD == 59;
@ -98,29 +103,35 @@ void Jit64::fp_arith(UGeckoInstruction inst)
void Jit64::frsqrtex(UGeckoInstruction inst) void Jit64::frsqrtex(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
int d = inst.FD; int d = inst.FD;
int b = inst.FB; int b = inst.FB;
fpr.Lock(b, d); fpr.Lock(b, d);
fpr.BindToRegister(d, true, true); fpr.BindToRegister(d, true, true);
MOVSD(XMM0, M((void *)&one_const)); MOVSD(XMM0, M((void *)&one_const));
SQRTSD(XMM1, fpr.R(b)); SQRTSD(XMM1, fpr.R(b));
DIVSD(XMM0, R(XMM1)); DIVSD(XMM0, R(XMM1));
MOVSD(fpr.R(d), XMM0); MOVSD(fpr.R(d), XMM0);
fpr.UnlockAll(); fpr.UnlockAll();
} }
void Jit64::fmaddXX(UGeckoInstruction inst) void Jit64::fmaddXX(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc) {
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
// Only the interpreter has "proper" support for (some) FP flags // Only the interpreter has "proper" support for (some) FP flags
if (inst.SUBOP5 == 29 && Core::g_CoreStartupParameter.bEnableFPRF) { if (inst.SUBOP5 == 29 && Core::g_CoreStartupParameter.bEnableFPRF)
Default(inst); return; {
FallBackToInterpreter(inst);
return;
} }
bool single_precision = inst.OPCD == 59; bool single_precision = inst.OPCD == 59;
@ -172,8 +183,11 @@ void Jit64::fsign(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc) {
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
int d = inst.FD; int d = inst.FD;
@ -203,9 +217,13 @@ void Jit64::fmrx(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc) {
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
int d = inst.FD; int d = inst.FD;
int b = inst.FB; int b = inst.FB;
fpr.Lock(b, d); fpr.Lock(b, d);
@ -219,8 +237,11 @@ void Jit64::fcmpx(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (jo.fpAccurateFcmp) {
Default(inst); return; // turn off from debugger if (jo.fpAccurateFcmp)
{
FallBackToInterpreter(inst); // turn off from debugger
return;
} }
//bool ordered = inst.SUBOP10 == 32; //bool ordered = inst.SUBOP10 == 32;

12
Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
View file

@ -296,7 +296,7 @@ void Jit64::reg_imm(UGeckoInstruction inst)
case 12: regimmop(d, a, false, (u32)(s32)inst.SIMM_16, Add, &XEmitter::ADD, false, true); break; //addic case 12: regimmop(d, a, false, (u32)(s32)inst.SIMM_16, Add, &XEmitter::ADD, false, true); break; //addic
case 13: regimmop(d, a, true, (u32)(s32)inst.SIMM_16, Add, &XEmitter::ADD, true, true); break; //addic_rc case 13: regimmop(d, a, true, (u32)(s32)inst.SIMM_16, Add, &XEmitter::ADD, true, true); break; //addic_rc
default: default:
Default(inst); FallBackToInterpreter(inst);
break; break;
} }
} }
@ -2111,15 +2111,21 @@ void Jit64::srawix(UGeckoInstruction inst)
} }
else else
{ {
Default(inst); return; // FIXME // FIXME
FallBackToInterpreter(inst);
return;
gpr.Lock(a, s); gpr.Lock(a, s);
JitClearCA(); JitClearCA();
gpr.BindToRegister(a, a == s, true); gpr.BindToRegister(a, a == s, true);
if (a != s) if (a != s)
{ {
MOV(32, gpr.R(a), gpr.R(s)); MOV(32, gpr.R(a), gpr.R(s));
} }
if (inst.Rc) {
if (inst.Rc)
{
ComputeRC(gpr.R(a)); ComputeRC(gpr.R(a));
} }
gpr.UnlockAll(); gpr.UnlockAll();

32
Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp
View file

@ -20,11 +20,20 @@ void Jit64::lXXx(UGeckoInstruction inst)
// Skip disabled JIT instructions // Skip disabled JIT instructions
if (Core::g_CoreStartupParameter.bJITLoadStorelbzxOff && (inst.OPCD == 31) && (inst.SUBOP10 == 87)) if (Core::g_CoreStartupParameter.bJITLoadStorelbzxOff && (inst.OPCD == 31) && (inst.SUBOP10 == 87))
{ Default(inst); return; } {
FallBackToInterpreter(inst);
return;
}
if (Core::g_CoreStartupParameter.bJITLoadStorelXzOff && ((inst.OPCD == 34) || (inst.OPCD == 40) || (inst.OPCD == 32))) if (Core::g_CoreStartupParameter.bJITLoadStorelXzOff && ((inst.OPCD == 34) || (inst.OPCD == 40) || (inst.OPCD == 32)))
{ Default(inst); return; } {
FallBackToInterpreter(inst);
return;
}
if (Core::g_CoreStartupParameter.bJITLoadStorelwzOff && (inst.OPCD == 32)) if (Core::g_CoreStartupParameter.bJITLoadStorelwzOff && (inst.OPCD == 32))
{ Default(inst); return; } {
FallBackToInterpreter(inst);
return;
}
// Determine memory access size and sign extend // Determine memory access size and sign extend
int accessSize = 0; int accessSize = 0;
@ -225,7 +234,8 @@ void Jit64::dcbst(UGeckoInstruction inst)
// dcbt = 0x7c00022c // dcbt = 0x7c00022c
if ((Memory::ReadUnchecked_U32(js.compilerPC - 4) & 0x7c00022c) != 0x7c00022c) if ((Memory::ReadUnchecked_U32(js.compilerPC - 4) & 0x7c00022c) != 0x7c00022c)
{ {
Default(inst); return; FallBackToInterpreter(inst);
return;
} }
} }
@ -235,7 +245,9 @@ void Jit64::dcbz(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff) JITDISABLE(bJITLoadStoreOff)
Default(inst); return; // FIXME
FallBackToInterpreter(inst);
return;
MOV(32, R(EAX), gpr.R(inst.RB)); MOV(32, R(EAX), gpr.R(inst.RB));
if (inst.RA) if (inst.RA)
@ -398,7 +410,7 @@ void Jit64::stXx(UGeckoInstruction inst)
int a = inst.RA, b = inst.RB, s = inst.RS; int a = inst.RA, b = inst.RB, s = inst.RS;
if (!a || a == s || a == b) if (!a || a == s || a == b)
{ {
Default(inst); FallBackToInterpreter(inst);
return; return;
} }
gpr.Lock(a, b, s); gpr.Lock(a, b, s);
@ -451,7 +463,8 @@ void Jit64::lmw(UGeckoInstruction inst)
} }
gpr.UnlockAllX(); gpr.UnlockAllX();
#else #else
Default(inst); return; FallBackToInterpreter(inst);
return;
#endif #endif
} }
@ -473,12 +486,13 @@ void Jit64::stmw(UGeckoInstruction inst)
} }
gpr.UnlockAllX(); gpr.UnlockAllX();
#else #else
Default(inst); return; FallBackToInterpreter(inst);
return;
#endif #endif
} }
void Jit64::icbi(UGeckoInstruction inst) void Jit64::icbi(UGeckoInstruction inst)
{ {
Default(inst); FallBackToInterpreter(inst);
WriteExit(js.compilerPC + 4); WriteExit(js.compilerPC + 4);
} }

26
Source/Core/Core/PowerPC/Jit64/Jit_LoadStoreFloating.cpp
View file

@ -36,9 +36,10 @@ void Jit64::lfs(UGeckoInstruction inst)
int a = inst.RA; int a = inst.RA;
if (!a) if (!a)
{ {
Default(inst); FallBackToInterpreter(inst);
return; return;
} }
s32 offset = (s32)(s16)inst.SIMM_16; s32 offset = (s32)(s16)inst.SIMM_16;
SafeLoadToReg(EAX, gpr.R(a), 32, offset, RegistersInUse(), false); SafeLoadToReg(EAX, gpr.R(a), 32, offset, RegistersInUse(), false);
@ -60,15 +61,20 @@ void Jit64::lfd(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreFloatingOff) JITDISABLE(bJITLoadStoreFloatingOff)
if (js.memcheck) { Default(inst); return; } if (js.memcheck)
{
FallBackToInterpreter(inst);
return;
}
int d = inst.RD; int d = inst.RD;
int a = inst.RA; int a = inst.RA;
if (!a) if (!a)
{ {
Default(inst); FallBackToInterpreter(inst);
return; return;
} }
s32 offset = (s32)(s16)inst.SIMM_16; s32 offset = (s32)(s16)inst.SIMM_16;
gpr.FlushLockX(ABI_PARAM1); gpr.FlushLockX(ABI_PARAM1);
gpr.Lock(a); gpr.Lock(a);
@ -129,13 +135,17 @@ void Jit64::stfd(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreFloatingOff) JITDISABLE(bJITLoadStoreFloatingOff)
if (js.memcheck) { Default(inst); return; } if (js.memcheck)
{
FallBackToInterpreter(inst);
return;
}
int s = inst.RS; int s = inst.RS;
int a = inst.RA; int a = inst.RA;
if (!a) if (!a)
{ {
Default(inst); FallBackToInterpreter(inst);
return; return;
} }
@ -218,8 +228,10 @@ void Jit64::stfs(UGeckoInstruction inst)
int s = inst.RS; int s = inst.RS;
int a = inst.RA; int a = inst.RA;
s32 offset = (s32)(s16)inst.SIMM_16; s32 offset = (s32)(s16)inst.SIMM_16;
if (!a || update) {
Default(inst); if (!a || update)
{
FallBackToInterpreter(inst);
return; return;
} }

16
Source/Core/Core/PowerPC/Jit64/Jit_LoadStorePaired.cpp
View file

@ -19,12 +19,16 @@ void Jit64::psq_st(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStorePairedOff) JITDISABLE(bJITLoadStorePairedOff)
if (js.memcheck) { Default(inst); return; } if (js.memcheck)
{
FallBackToInterpreter(inst);
return;
}
if (!inst.RA) if (!inst.RA)
{ {
// TODO: Support these cases if it becomes necessary. // TODO: Support these cases if it becomes necessary.
Default(inst); FallBackToInterpreter(inst);
return; return;
} }
@ -71,11 +75,15 @@ void Jit64::psq_l(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStorePairedOff) JITDISABLE(bJITLoadStorePairedOff)
if (js.memcheck) { Default(inst); return; } if (js.memcheck)
{
FallBackToInterpreter(inst);
return;
}
if (!inst.RA) if (!inst.RA)
{ {
Default(inst); FallBackToInterpreter(inst);
return; return;
} }

74
Source/Core/Core/PowerPC/Jit64/Jit_Paired.cpp
View file

@ -22,13 +22,18 @@ void Jit64::ps_mr(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
if (inst.Rc) {
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
int d = inst.FD; int d = inst.FD;
int b = inst.FB; int b = inst.FB;
if (d == b) if (d == b)
return; return;
fpr.BindToRegister(d, false); fpr.BindToRegister(d, false);
MOVAPD(fpr.RX(d), fpr.R(b)); MOVAPD(fpr.RX(d), fpr.R(b));
} }
@ -41,9 +46,12 @@ void Jit64::ps_sel(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
if (inst.Rc) { if (inst.Rc)
Default(inst); return; {
FallBackToInterpreter(inst);
return;
} }
int d = inst.FD; int d = inst.FD;
int a = inst.FA; int a = inst.FA;
int b = inst.FB; int b = inst.FB;
@ -67,9 +75,13 @@ void Jit64::ps_sign(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
if (inst.Rc) {
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
int d = inst.FD; int d = inst.FD;
int b = inst.FB; int b = inst.FB;
@ -105,9 +117,13 @@ void Jit64::ps_recip(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
if (inst.Rc) {
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
OpArg divisor; OpArg divisor;
int d = inst.FD; int d = inst.FD;
int b = inst.FB; int b = inst.FB;
@ -185,9 +201,13 @@ void Jit64::ps_arith(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
if (inst.Rc) {
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
switch (inst.SUBOP5) switch (inst.SUBOP5)
{ {
case 18: tri_op(inst.FD, inst.FA, inst.FB, false, &XEmitter::DIVPD); break; //div case 18: tri_op(inst.FD, inst.FA, inst.FB, false, &XEmitter::DIVPD); break; //div
@ -203,10 +223,14 @@ void Jit64::ps_sum(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
// TODO: (inst.SUBOP5 == 10) breaks Sonic Colours (black screen) // TODO: (inst.SUBOP5 == 10) breaks Sonic Colours (black screen)
if (inst.Rc || (inst.SUBOP5 == 10)) { if (inst.Rc || (inst.SUBOP5 == 10))
Default(inst); return; {
FallBackToInterpreter(inst);
return;
} }
int d = inst.FD; int d = inst.FD;
int a = inst.FA; int a = inst.FA;
int b = inst.FB; int b = inst.FB;
@ -245,9 +269,13 @@ void Jit64::ps_muls(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
if (inst.Rc) {
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
int d = inst.FD; int d = inst.FD;
int a = inst.FA; int a = inst.FA;
int c = inst.FC; int c = inst.FC;
@ -284,9 +312,13 @@ void Jit64::ps_mergeXX(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
if (inst.Rc) {
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
int d = inst.FD; int d = inst.FD;
int a = inst.FA; int a = inst.FA;
int b = inst.FB; int b = inst.FB;
@ -321,9 +353,13 @@ void Jit64::ps_maddXX(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
if (inst.Rc) {
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
int a = inst.FA; int a = inst.FA;
int b = inst.FB; int b = inst.FB;
int c = inst.FC; int c = inst.FC;
@ -364,7 +400,7 @@ void Jit64::ps_maddXX(UGeckoInstruction inst)
break; break;
default: default:
_assert_msg_(DYNA_REC, 0, "ps_maddXX WTF!!!"); _assert_msg_(DYNA_REC, 0, "ps_maddXX WTF!!!");
//Default(inst); //FallBackToInterpreter(inst);
//fpr.UnlockAll(); //fpr.UnlockAll();
return; return;
} }

4
Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp
View file

@ -49,7 +49,7 @@ void Jit64::mtspr(UGeckoInstruction inst)
break; break;
default: default:
Default(inst); FallBackToInterpreter(inst);
return; return;
} }
@ -79,7 +79,7 @@ void Jit64::mfspr(UGeckoInstruction inst)
case SPR_PMC2: case SPR_PMC2:
case SPR_PMC3: case SPR_PMC3:
case SPR_PMC4: case SPR_PMC4:
Default(inst); FallBackToInterpreter(inst);
return; return;
default: default:
gpr.Lock(d); gpr.Lock(d);

4
Source/Core/Core/PowerPC/Jit64IL/IR_X86.cpp
View file

@ -595,7 +595,7 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress) {
case LoadGQR: case LoadGQR:
case BlockEnd: case BlockEnd:
case BlockStart: case BlockStart:
case InterpreterFallback: case FallBackToInterpreter:
case SystemCall: case SystemCall:
case RFIExit: case RFIExit:
case InterpreterBranch: case InterpreterBranch:
@ -742,7 +742,7 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress) {
} }
switch (getOpcode(*I)) { switch (getOpcode(*I)) {
case InterpreterFallback: { case FallBackToInterpreter: {
unsigned InstCode = ibuild->GetImmValue(getOp1(I)); unsigned InstCode = ibuild->GetImmValue(getOp1(I));
unsigned InstLoc = ibuild->GetImmValue(getOp2(I)); unsigned InstLoc = ibuild->GetImmValue(getOp2(I));
// There really shouldn't be anything live across an // There really shouldn't be anything live across an

4
Source/Core/Core/PowerPC/Jit64IL/JitIL.cpp
View file

@ -316,9 +316,9 @@ void JitIL::unknown_instruction(UGeckoInstruction inst)
PanicAlert("unknown_instruction %08x - Fix me ;)", inst.hex); PanicAlert("unknown_instruction %08x - Fix me ;)", inst.hex);
} }
void JitIL::Default(UGeckoInstruction _inst) void JitIL::FallBackToInterpreter(UGeckoInstruction _inst)
{ {
ibuild.EmitInterpreterFallback( ibuild.EmitFallBackToInterpreter(
ibuild.EmitIntConst(_inst.hex), ibuild.EmitIntConst(_inst.hex),
ibuild.EmitIntConst(js.compilerPC)); ibuild.EmitIntConst(js.compilerPC));
} }

4
Source/Core/Core/PowerPC/Jit64IL/JitIL.h
View file

@ -38,7 +38,7 @@
#if _M_X86_64 #if _M_X86_64
#define DISABLE64 \ #define DISABLE64 \
{Default(inst); return;} {FallBackToInterpreter(inst); return;}
#else #else
#define DISABLE64 #define DISABLE64
#endif #endif
@ -116,7 +116,7 @@ public:
// OPCODES // OPCODES
void unknown_instruction(UGeckoInstruction _inst) override; void unknown_instruction(UGeckoInstruction _inst) override;
void Default(UGeckoInstruction _inst) override; void FallBackToInterpreter(UGeckoInstruction _inst) override;
void DoNothing(UGeckoInstruction _inst) override; void DoNothing(UGeckoInstruction _inst) override;
void HLEFunction(UGeckoInstruction _inst) override; void HLEFunction(UGeckoInstruction _inst) override;

501
Source/Core/Core/PowerPC/Jit64IL/JitIL_Tables.cpp
View file

@ -31,341 +31,342 @@ struct GekkoOPTemplate
static GekkoOPTemplate primarytable[] = static GekkoOPTemplate primarytable[] =
{ {
{4, &JitIL::DynaRunTable4}, //"RunTable4", OPTYPE_SUBTABLE | (4<<24), 0}}, {4, &JitIL::DynaRunTable4}, //"RunTable4", OPTYPE_SUBTABLE | (4<<24), 0}},
{19, &JitIL::DynaRunTable19}, //"RunTable19", OPTYPE_SUBTABLE | (19<<24), 0}}, {19, &JitIL::DynaRunTable19}, //"RunTable19", OPTYPE_SUBTABLE | (19<<24), 0}},
{31, &JitIL::DynaRunTable31}, //"RunTable31", OPTYPE_SUBTABLE | (31<<24), 0}}, {31, &JitIL::DynaRunTable31}, //"RunTable31", OPTYPE_SUBTABLE | (31<<24), 0}},
{59, &JitIL::DynaRunTable59}, //"RunTable59", OPTYPE_SUBTABLE | (59<<24), 0}}, {59, &JitIL::DynaRunTable59}, //"RunTable59", OPTYPE_SUBTABLE | (59<<24), 0}},
{63, &JitIL::DynaRunTable63}, //"RunTable63", OPTYPE_SUBTABLE | (63<<24), 0}}, {63, &JitIL::DynaRunTable63}, //"RunTable63", OPTYPE_SUBTABLE | (63<<24), 0}},
{16, &JitIL::bcx}, //"bcx", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {16, &JitIL::bcx}, //"bcx", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{18, &JitIL::bx}, //"bx", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {18, &JitIL::bx}, //"bx", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{1, &JitIL::HLEFunction}, //"HLEFunction", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {1, &JitIL::HLEFunction}, //"HLEFunction", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{2, &JitIL::Default}, //"DynaBlock", OPTYPE_SYSTEM, 0}}, {2, &JitIL::FallBackToInterpreter}, //"DynaBlock", OPTYPE_SYSTEM, 0}},
{3, &JitIL::Default}, //"twi", OPTYPE_SYSTEM, 0}}, {3, &JitIL::FallBackToInterpreter}, //"twi", OPTYPE_SYSTEM, 0}},
{17, &JitIL::sc}, //"sc", OPTYPE_SYSTEM, FL_ENDBLOCK, 1}}, {17, &JitIL::sc}, //"sc", OPTYPE_SYSTEM, FL_ENDBLOCK, 1}},
{7, &JitIL::mulli}, //"mulli", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_RC_BIT, 2}}, {7, &JitIL::mulli}, //"mulli", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_RC_BIT, 2}},
{8, &JitIL::subfic}, //"subfic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}}, {8, &JitIL::subfic}, //"subfic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}},
{10, &JitIL::cmpXX}, //"cmpli", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}}, {10, &JitIL::cmpXX}, //"cmpli", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}},
{11, &JitIL::cmpXX}, //"cmpi", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}}, {11, &JitIL::cmpXX}, //"cmpi", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}},
{12, &JitIL::reg_imm}, //"addic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}}, {12, &JitIL::reg_imm}, //"addic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}},
{13, &JitIL::reg_imm}, //"addic_rc", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CR0}}, {13, &JitIL::reg_imm}, //"addic_rc", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CR0}},
{14, &JitIL::reg_imm}, //"addi", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}}, {14, &JitIL::reg_imm}, //"addi", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}},
{15, &JitIL::reg_imm}, //"addis", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}}, {15, &JitIL::reg_imm}, //"addis", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}},
{20, &JitIL::rlwimix}, //"rlwimix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_A | FL_IN_S | FL_RC_BIT}}, {20, &JitIL::rlwimix}, //"rlwimix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_A | FL_IN_S | FL_RC_BIT}},
{21, &JitIL::rlwinmx}, //"rlwinmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, {21, &JitIL::rlwinmx}, //"rlwinmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
{23, &JitIL::rlwnmx}, //"rlwnmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_IN_B | FL_RC_BIT}}, {23, &JitIL::rlwnmx}, //"rlwnmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_IN_B | FL_RC_BIT}},
{24, &JitIL::reg_imm}, //"ori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, {24, &JitIL::reg_imm}, //"ori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
{25, &JitIL::reg_imm}, //"oris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, {25, &JitIL::reg_imm}, //"oris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
{26, &JitIL::reg_imm}, //"xori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, {26, &JitIL::reg_imm}, //"xori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
{27, &JitIL::reg_imm}, //"xoris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, {27, &JitIL::reg_imm}, //"xoris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
{28, &JitIL::reg_imm}, //"andi_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}}, {28, &JitIL::reg_imm}, //"andi_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}},
{29, &JitIL::reg_imm}, //"andis_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}}, {29, &JitIL::reg_imm}, //"andis_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}},
{32, &JitIL::lXz}, //"lwz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, {32, &JitIL::lXz}, //"lwz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
{33, &JitIL::lXz}, //"lwzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {33, &JitIL::lXz}, //"lwzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
{34, &JitIL::lXz}, //"lbz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, {34, &JitIL::lXz}, //"lbz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
{35, &JitIL::lbzu}, //"lbzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {35, &JitIL::lbzu}, //"lbzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
{40, &JitIL::lXz}, //"lhz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, {40, &JitIL::lXz}, //"lhz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
{41, &JitIL::lXz}, //"lhzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {41, &JitIL::lXz}, //"lhzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
{42, &JitIL::lha}, //"lha", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, {42, &JitIL::lha}, //"lha", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
{43, &JitIL::Default}, //"lhau", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {43, &JitIL::FallBackToInterpreter}, //"lhau", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
{44, &JitIL::stX}, //"sth", OPTYPE_STORE, FL_IN_A | FL_IN_S}}, {44, &JitIL::stX}, //"sth", OPTYPE_STORE, FL_IN_A | FL_IN_S}},
{45, &JitIL::stX}, //"sthu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}}, {45, &JitIL::stX}, //"sthu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
{36, &JitIL::stX}, //"stw", OPTYPE_STORE, FL_IN_A | FL_IN_S}}, {36, &JitIL::stX}, //"stw", OPTYPE_STORE, FL_IN_A | FL_IN_S}},
{37, &JitIL::stX}, //"stwu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}}, {37, &JitIL::stX}, //"stwu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
{38, &JitIL::stX}, //"stb", OPTYPE_STORE, FL_IN_A | FL_IN_S}}, {38, &JitIL::stX}, //"stb", OPTYPE_STORE, FL_IN_A | FL_IN_S}},
{39, &JitIL::stX}, //"stbu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}}, {39, &JitIL::stX}, //"stbu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
{46, &JitIL::lmw}, //"lmw", OPTYPE_SYSTEM, FL_EVIL, 10}}, {46, &JitIL::lmw}, //"lmw", OPTYPE_SYSTEM, FL_EVIL, 10}},
{47, &JitIL::stmw}, //"stmw", OPTYPE_SYSTEM, FL_EVIL, 10}}, {47, &JitIL::stmw}, //"stmw", OPTYPE_SYSTEM, FL_EVIL, 10}},
{48, &JitIL::lfs}, //"lfs", OPTYPE_LOADFP, FL_IN_A}}, {48, &JitIL::lfs}, //"lfs", OPTYPE_LOADFP, FL_IN_A}},
{49, &JitIL::Default}, //"lfsu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}}, {49, &JitIL::FallBackToInterpreter}, //"lfsu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}},
{50, &JitIL::lfd}, //"lfd", OPTYPE_LOADFP, FL_IN_A}}, {50, &JitIL::lfd}, //"lfd", OPTYPE_LOADFP, FL_IN_A}},
{51, &JitIL::Default}, //"lfdu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}}, {51, &JitIL::FallBackToInterpreter}, //"lfdu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}},
{52, &JitIL::stfs}, //"stfs", OPTYPE_STOREFP, FL_IN_A}}, {52, &JitIL::stfs}, //"stfs", OPTYPE_STOREFP, FL_IN_A}},
{53, &JitIL::stfs}, //"stfsu", OPTYPE_STOREFP, FL_OUT_A | FL_IN_A}}, {53, &JitIL::stfs}, //"stfsu", OPTYPE_STOREFP, FL_OUT_A | FL_IN_A}},
{54, &JitIL::stfd}, //"stfd", OPTYPE_STOREFP, FL_IN_A}}, {54, &JitIL::stfd}, //"stfd", OPTYPE_STOREFP, FL_IN_A}},
{55, &JitIL::Default}, //"stfdu", OPTYPE_STOREFP, FL_OUT_A | FL_IN_A}}, {55, &JitIL::FallBackToInterpreter}, //"stfdu", OPTYPE_STOREFP, FL_OUT_A | FL_IN_A}},
{56, &JitIL::psq_l}, //"psq_l", OPTYPE_PS, FL_IN_A}}, {56, &JitIL::psq_l}, //"psq_l", OPTYPE_PS, FL_IN_A}},
{57, &JitIL::psq_l}, //"psq_lu", OPTYPE_PS, FL_OUT_A | FL_IN_A}}, {57, &JitIL::psq_l}, //"psq_lu", OPTYPE_PS, FL_OUT_A | FL_IN_A}},
{60, &JitIL::psq_st}, //"psq_st", OPTYPE_PS, FL_IN_A}}, {60, &JitIL::psq_st}, //"psq_st", OPTYPE_PS, FL_IN_A}},
{61, &JitIL::psq_st}, //"psq_stu", OPTYPE_PS, FL_OUT_A | FL_IN_A}}, {61, &JitIL::psq_st}, //"psq_stu", OPTYPE_PS, FL_OUT_A | FL_IN_A}},
//missing: 0, 5, 6, 9, 22, 30, 62, 58 //missing: 0, 5, 6, 9, 22, 30, 62, 58
{0, &JitIL::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {0, &JitIL::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{5, &JitIL::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {5, &JitIL::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{6, &JitIL::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {6, &JitIL::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{9, &JitIL::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {9, &JitIL::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{22, &JitIL::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {22, &JitIL::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{30, &JitIL::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {30, &JitIL::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{62, &JitIL::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {62, &JitIL::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{58, &JitIL::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {58, &JitIL::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
}; };
static GekkoOPTemplate table4[] = static GekkoOPTemplate table4[] =
{ //SUBOP10 { //SUBOP10
{0, &JitIL::Default}, //"ps_cmpu0", OPTYPE_PS, FL_SET_CRn}}, {0, &JitIL::FallBackToInterpreter}, //"ps_cmpu0", OPTYPE_PS, FL_SET_CRn}},
{32, &JitIL::Default}, //"ps_cmpo0", OPTYPE_PS, FL_SET_CRn}}, {32, &JitIL::FallBackToInterpreter}, //"ps_cmpo0", OPTYPE_PS, FL_SET_CRn}},
{40, &JitIL::ps_sign}, //"ps_neg", OPTYPE_PS, FL_RC_BIT}}, {40, &JitIL::ps_sign}, //"ps_neg", OPTYPE_PS, FL_RC_BIT}},
{136, &JitIL::ps_sign}, //"ps_nabs", OPTYPE_PS, FL_RC_BIT}}, {136, &JitIL::ps_sign}, //"ps_nabs", OPTYPE_PS, FL_RC_BIT}},
{264, &JitIL::ps_sign}, //"ps_abs", OPTYPE_PS, FL_RC_BIT}}, {264, &JitIL::ps_sign}, //"ps_abs", OPTYPE_PS, FL_RC_BIT}},
{64, &JitIL::Default}, //"ps_cmpu1", OPTYPE_PS, FL_RC_BIT}}, {64, &JitIL::FallBackToInterpreter}, //"ps_cmpu1", OPTYPE_PS, FL_RC_BIT}},
{72, &JitIL::ps_mr}, //"ps_mr", OPTYPE_PS, FL_RC_BIT}}, {72, &JitIL::ps_mr}, //"ps_mr", OPTYPE_PS, FL_RC_BIT}},
{96, &JitIL::Default}, //"ps_cmpo1", OPTYPE_PS, FL_RC_BIT}}, {96, &JitIL::FallBackToInterpreter}, //"ps_cmpo1", OPTYPE_PS, FL_RC_BIT}},
{528, &JitIL::ps_mergeXX}, //"ps_merge00", OPTYPE_PS, FL_RC_BIT}}, {528, &JitIL::ps_mergeXX}, //"ps_merge00", OPTYPE_PS, FL_RC_BIT}},
{560, &JitIL::ps_mergeXX}, //"ps_merge01", OPTYPE_PS, FL_RC_BIT}}, {560, &JitIL::ps_mergeXX}, //"ps_merge01", OPTYPE_PS, FL_RC_BIT}},
{592, &JitIL::ps_mergeXX}, //"ps_merge10", OPTYPE_PS, FL_RC_BIT}}, {592, &JitIL::ps_mergeXX}, //"ps_merge10", OPTYPE_PS, FL_RC_BIT}},
{624, &JitIL::ps_mergeXX}, //"ps_merge11", OPTYPE_PS, FL_RC_BIT}}, {624, &JitIL::ps_mergeXX}, //"ps_merge11", OPTYPE_PS, FL_RC_BIT}},
{1014, &JitIL::Default}, //"dcbz_l", OPTYPE_SYSTEM, 0}}, {1014, &JitIL::FallBackToInterpreter}, //"dcbz_l", OPTYPE_SYSTEM, 0}},
}; };
static GekkoOPTemplate table4_2[] = static GekkoOPTemplate table4_2[] =
{ {
{10, &JitIL::ps_sum}, //"ps_sum0", OPTYPE_PS, 0}}, {10, &JitIL::ps_sum}, //"ps_sum0", OPTYPE_PS, 0}},
{11, &JitIL::ps_sum}, //"ps_sum1", OPTYPE_PS, 0}}, {11, &JitIL::ps_sum}, //"ps_sum1", OPTYPE_PS, 0}},
{12, &JitIL::ps_muls}, //"ps_muls0", OPTYPE_PS, 0}}, {12, &JitIL::ps_muls}, //"ps_muls0", OPTYPE_PS, 0}},
{13, &JitIL::ps_muls}, //"ps_muls1", OPTYPE_PS, 0}}, {13, &JitIL::ps_muls}, //"ps_muls1", OPTYPE_PS, 0}},
{14, &JitIL::ps_maddXX}, //"ps_madds0", OPTYPE_PS, 0}}, {14, &JitIL::ps_maddXX}, //"ps_madds0", OPTYPE_PS, 0}},
{15, &JitIL::ps_maddXX}, //"ps_madds1", OPTYPE_PS, 0}}, {15, &JitIL::ps_maddXX}, //"ps_madds1", OPTYPE_PS, 0}},
{18, &JitIL::ps_arith}, //"ps_div", OPTYPE_PS, 0, 16}}, {18, &JitIL::ps_arith}, //"ps_div", OPTYPE_PS, 0, 16}},
{20, &JitIL::ps_arith}, //"ps_sub", OPTYPE_PS, 0}}, {20, &JitIL::ps_arith}, //"ps_sub", OPTYPE_PS, 0}},
{21, &JitIL::ps_arith}, //"ps_add", OPTYPE_PS, 0}}, {21, &JitIL::ps_arith}, //"ps_add", OPTYPE_PS, 0}},
{23, &JitIL::ps_sel}, //"ps_sel", OPTYPE_PS, 0}}, {23, &JitIL::ps_sel}, //"ps_sel", OPTYPE_PS, 0}},
{24, &JitIL::Default}, //"ps_res", OPTYPE_PS, 0}}, {24, &JitIL::FallBackToInterpreter}, //"ps_res", OPTYPE_PS, 0}},
{25, &JitIL::ps_arith}, //"ps_mul", OPTYPE_PS, 0}}, {25, &JitIL::ps_arith}, //"ps_mul", OPTYPE_PS, 0}},
{26, &JitIL::ps_rsqrte}, //"ps_rsqrte", OPTYPE_PS, 0, 1}}, {26, &JitIL::ps_rsqrte}, //"ps_rsqrte", OPTYPE_PS, 0, 1}},
{28, &JitIL::ps_maddXX}, //"ps_msub", OPTYPE_PS, 0}}, {28, &JitIL::ps_maddXX}, //"ps_msub", OPTYPE_PS, 0}},
{29, &JitIL::ps_maddXX}, //"ps_madd", OPTYPE_PS, 0}}, {29, &JitIL::ps_maddXX}, //"ps_madd", OPTYPE_PS, 0}},
{30, &JitIL::ps_maddXX}, //"ps_nmsub", OPTYPE_PS, 0}}, {30, &JitIL::ps_maddXX}, //"ps_nmsub", OPTYPE_PS, 0}},
{31, &JitIL::ps_maddXX}, //"ps_nmadd", OPTYPE_PS, 0}}, {31, &JitIL::ps_maddXX}, //"ps_nmadd", OPTYPE_PS, 0}},
}; };
static GekkoOPTemplate table4_3[] = static GekkoOPTemplate table4_3[] =
{ {
{6, &JitIL::Default}, //"psq_lx", OPTYPE_PS, 0}}, {6, &JitIL::FallBackToInterpreter}, //"psq_lx", OPTYPE_PS, 0}},
{7, &JitIL::Default}, //"psq_stx", OPTYPE_PS, 0}}, {7, &JitIL::FallBackToInterpreter}, //"psq_stx", OPTYPE_PS, 0}},
{38, &JitIL::Default}, //"psq_lux", OPTYPE_PS, 0}}, {38, &JitIL::FallBackToInterpreter}, //"psq_lux", OPTYPE_PS, 0}},
{39, &JitIL::Default}, //"psq_stux", OPTYPE_PS, 0}}, {39, &JitIL::FallBackToInterpreter}, //"psq_stux", OPTYPE_PS, 0}},
}; };
static GekkoOPTemplate table19[] = static GekkoOPTemplate table19[] =
{ {
{528, &JitIL::bcctrx}, //"bcctrx", OPTYPE_BRANCH, FL_ENDBLOCK}}, {528, &JitIL::bcctrx}, //"bcctrx", OPTYPE_BRANCH, FL_ENDBLOCK}},
{16, &JitIL::bclrx}, //"bclrx", OPTYPE_BRANCH, FL_ENDBLOCK}}, {16, &JitIL::bclrx}, //"bclrx", OPTYPE_BRANCH, FL_ENDBLOCK}},
{257, &JitIL::crXX}, //"crand", OPTYPE_CR, FL_EVIL}}, {257, &JitIL::crXX}, //"crand", OPTYPE_CR, FL_EVIL}},
{129, &JitIL::crXX}, //"crandc", OPTYPE_CR, FL_EVIL}}, {129, &JitIL::crXX}, //"crandc", OPTYPE_CR, FL_EVIL}},
{289, &JitIL::crXX}, //"creqv", OPTYPE_CR, FL_EVIL}}, {289, &JitIL::crXX}, //"creqv", OPTYPE_CR, FL_EVIL}},
{225, &JitIL::crXX}, //"crnand", OPTYPE_CR, FL_EVIL}}, {225, &JitIL::crXX}, //"crnand", OPTYPE_CR, FL_EVIL}},
{33, &JitIL::crXX}, //"crnor", OPTYPE_CR, FL_EVIL}}, {33, &JitIL::crXX}, //"crnor", OPTYPE_CR, FL_EVIL}},
{449, &JitIL::crXX}, //"cror", OPTYPE_CR, FL_EVIL}}, {449, &JitIL::crXX}, //"cror", OPTYPE_CR, FL_EVIL}},
{417, &JitIL::crXX}, //"crorc", OPTYPE_CR, FL_EVIL}}, {417, &JitIL::crXX}, //"crorc", OPTYPE_CR, FL_EVIL}},
{193, &JitIL::crXX}, //"crxor", OPTYPE_CR, FL_EVIL}}, {193, &JitIL::crXX}, //"crxor", OPTYPE_CR, FL_EVIL}},
{150, &JitIL::DoNothing}, //"isync", OPTYPE_ICACHE, FL_EVIL}}, {150, &JitIL::DoNothing}, //"isync", OPTYPE_ICACHE, FL_EVIL}},
{0, &JitIL::mcrf}, //"mcrf", OPTYPE_SYSTEM, FL_EVIL}}, {0, &JitIL::mcrf}, //"mcrf", OPTYPE_SYSTEM, FL_EVIL}},
{50, &JitIL::rfi}, //"rfi", OPTYPE_SYSTEM, FL_ENDBLOCK | FL_CHECKEXCEPTIONS, 1}}, {50, &JitIL::rfi}, //"rfi", OPTYPE_SYSTEM, FL_ENDBLOCK | FL_CHECKEXCEPTIONS, 1}},
{18, &JitIL::Default}, //"rfid", OPTYPE_SYSTEM, FL_ENDBLOCK | FL_CHECKEXCEPTIONS}} {18, &JitIL::FallBackToInterpreter}, //"rfid", OPTYPE_SYSTEM, FL_ENDBLOCK | FL_CHECKEXCEPTIONS}}
}; };
static GekkoOPTemplate table31[] = static GekkoOPTemplate table31[] =
{ {
{28, &JitIL::boolX}, //"andx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {28, &JitIL::boolX}, //"andx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{60, &JitIL::boolX}, //"andcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {60, &JitIL::boolX}, //"andcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{444, &JitIL::boolX}, //"orx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {444, &JitIL::boolX}, //"orx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{124, &JitIL::boolX}, //"norx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {124, &JitIL::boolX}, //"norx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{316, &JitIL::boolX}, //"xorx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {316, &JitIL::boolX}, //"xorx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{412, &JitIL::boolX}, //"orcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {412, &JitIL::boolX}, //"orcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{476, &JitIL::boolX}, //"nandx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {476, &JitIL::boolX}, //"nandx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{284, &JitIL::boolX}, //"eqvx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {284, &JitIL::boolX}, //"eqvx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{0, &JitIL::cmpXX}, //"cmp", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}}, {0, &JitIL::cmpXX}, //"cmp", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}},
{32, &JitIL::cmpXX}, //"cmpl", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}}, {32, &JitIL::cmpXX}, //"cmpl", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}},
{26, &JitIL::cntlzwx}, //"cntlzwx",OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, {26, &JitIL::cntlzwx}, //"cntlzwx",OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
{922, &JitIL::extshx}, //"extshx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, {922, &JitIL::extshx}, //"extshx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
{954, &JitIL::extsbx}, //"extsbx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, {954, &JitIL::extsbx}, //"extsbx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
{536, &JitIL::srwx}, //"srwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, {536, &JitIL::srwx}, //"srwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
{792, &JitIL::srawx}, //"srawx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, {792, &JitIL::srawx}, //"srawx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
{824, &JitIL::srawix}, //"srawix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, {824, &JitIL::srawix}, //"srawix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
{24, &JitIL::slwx}, //"slwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, {24, &JitIL::slwx}, //"slwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
{54, &JitIL::dcbst}, //"dcbst", OPTYPE_DCACHE, 0, 4}},
{86, &JitIL::FallBackToInterpreter}, //"dcbf", OPTYPE_DCACHE, 0, 4}},
{246, &JitIL::DoNothing}, //"dcbtst", OPTYPE_DCACHE, 0, 1}},
{278, &JitIL::DoNothing}, //"dcbt", OPTYPE_DCACHE, 0, 1}},
{470, &JitIL::FallBackToInterpreter}, //"dcbi", OPTYPE_DCACHE, 0, 4}},
{758, &JitIL::DoNothing}, //"dcba", OPTYPE_DCACHE, 0, 4}},
{1014, &JitIL::dcbz}, //"dcbz", OPTYPE_DCACHE, 0, 4}},
{54, &JitIL::dcbst}, //"dcbst", OPTYPE_DCACHE, 0, 4}},
{86, &JitIL::Default}, //"dcbf", OPTYPE_DCACHE, 0, 4}},
{246, &JitIL::DoNothing}, //"dcbtst", OPTYPE_DCACHE, 0, 1}},
{278, &JitIL::DoNothing}, //"dcbt", OPTYPE_DCACHE, 0, 1}},
{470, &JitIL::Default}, //"dcbi", OPTYPE_DCACHE, 0, 4}},
{758, &JitIL::DoNothing}, //"dcba", OPTYPE_DCACHE, 0, 4}},
{1014, &JitIL::dcbz}, //"dcbz", OPTYPE_DCACHE, 0, 4}},
//load word //load word
{23, &JitIL::lXzx}, //"lwzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {23, &JitIL::lXzx}, //"lwzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{55, &JitIL::lXzx}, //"lwzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, {55, &JitIL::lXzx}, //"lwzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
//load halfword //load halfword
{279, &JitIL::lXzx}, //"lhzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {279, &JitIL::lXzx}, //"lhzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{311, &JitIL::lXzx}, //"lhzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, {311, &JitIL::lXzx}, //"lhzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
//load halfword signextend //load halfword signextend
{343, &JitIL::lhax}, //"lhax", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {343, &JitIL::lhax}, //"lhax", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{375, &JitIL::Default}, //"lhaux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, {375, &JitIL::FallBackToInterpreter}, //"lhaux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
//load byte //load byte
{87, &JitIL::lXzx}, //"lbzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {87, &JitIL::lXzx}, //"lbzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{119, &JitIL::lXzx}, //"lbzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, {119, &JitIL::lXzx}, //"lbzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
//load byte reverse //load byte reverse
{534, &JitIL::Default}, //"lwbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {534, &JitIL::FallBackToInterpreter}, //"lwbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{790, &JitIL::Default}, //"lhbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {790, &JitIL::FallBackToInterpreter}, //"lhbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
// Conditional load/store (Wii SMP) // Conditional load/store (Wii SMP)
{150, &JitIL::Default}, //"stwcxd", OPTYPE_STORE, FL_EVIL | FL_SET_CR0}}, {150, &JitIL::FallBackToInterpreter}, //"stwcxd", OPTYPE_STORE, FL_EVIL | FL_SET_CR0}},
{20, &JitIL::Default}, //"lwarx", OPTYPE_LOAD, FL_EVIL | FL_OUT_D | FL_IN_A0B | FL_SET_CR0}}, {20, &JitIL::FallBackToInterpreter}, //"lwarx", OPTYPE_LOAD, FL_EVIL | FL_OUT_D | FL_IN_A0B | FL_SET_CR0}},
//load string (interpret these) //load string (interpret these)
{533, &JitIL::Default}, //"lswx", OPTYPE_LOAD, FL_EVIL | FL_IN_A | FL_OUT_D}}, {533, &JitIL::FallBackToInterpreter}, //"lswx", OPTYPE_LOAD, FL_EVIL | FL_IN_A | FL_OUT_D}},
{597, &JitIL::Default}, //"lswi", OPTYPE_LOAD, FL_EVIL | FL_IN_AB | FL_OUT_D}}, {597, &JitIL::FallBackToInterpreter}, //"lswi", OPTYPE_LOAD, FL_EVIL | FL_IN_AB | FL_OUT_D}},
//store word //store word
{151, &JitIL::stXx}, //"stwx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, {151, &JitIL::stXx}, //"stwx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}},
{183, &JitIL::stXx}, //"stwux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}}, {183, &JitIL::stXx}, //"stwux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}},
//store halfword //store halfword
{407, &JitIL::stXx}, //"sthx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, {407, &JitIL::stXx}, //"sthx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}},
{439, &JitIL::stXx}, //"sthux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}}, {439, &JitIL::stXx}, //"sthux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}},
//store byte //store byte
{215, &JitIL::stXx}, //"stbx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, {215, &JitIL::stXx}, //"stbx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}},
{247, &JitIL::stXx}, //"stbux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}}, {247, &JitIL::stXx}, //"stbux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}},
//store bytereverse //store bytereverse
{662, &JitIL::Default}, //"stwbrx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, {662, &JitIL::FallBackToInterpreter}, //"stwbrx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}},
{918, &JitIL::Default}, //"sthbrx", OPTYPE_STORE, FL_IN_A | FL_IN_B}}, {918, &JitIL::FallBackToInterpreter}, //"sthbrx", OPTYPE_STORE, FL_IN_A | FL_IN_B}},
{661, &JitIL::Default}, //"stswx", OPTYPE_STORE, FL_EVIL}}, {661, &JitIL::FallBackToInterpreter}, //"stswx", OPTYPE_STORE, FL_EVIL}},
{725, &JitIL::Default}, //"stswi", OPTYPE_STORE, FL_EVIL}}, {725, &JitIL::FallBackToInterpreter}, //"stswi", OPTYPE_STORE, FL_EVIL}},
// fp load/store // fp load/store
{535, &JitIL::lfsx}, //"lfsx", OPTYPE_LOADFP, FL_IN_A0 | FL_IN_B}}, {535, &JitIL::lfsx}, //"lfsx", OPTYPE_LOADFP, FL_IN_A0 | FL_IN_B}},
{567, &JitIL::Default}, //"lfsux", OPTYPE_LOADFP, FL_IN_A | FL_IN_B}}, {567, &JitIL::FallBackToInterpreter}, //"lfsux", OPTYPE_LOADFP, FL_IN_A | FL_IN_B}},
{599, &JitIL::Default}, //"lfdx", OPTYPE_LOADFP, FL_IN_A0 | FL_IN_B}}, {599, &JitIL::FallBackToInterpreter}, //"lfdx", OPTYPE_LOADFP, FL_IN_A0 | FL_IN_B}},
{631, &JitIL::Default}, //"lfdux", OPTYPE_LOADFP, FL_IN_A | FL_IN_B}}, {631, &JitIL::FallBackToInterpreter}, //"lfdux", OPTYPE_LOADFP, FL_IN_A | FL_IN_B}},
{663, &JitIL::stfsx}, //"stfsx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}}, {663, &JitIL::stfsx}, //"stfsx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}},
{695, &JitIL::Default}, //"stfsux", OPTYPE_STOREFP, FL_IN_A | FL_IN_B}}, {695, &JitIL::FallBackToInterpreter}, //"stfsux", OPTYPE_STOREFP, FL_IN_A | FL_IN_B}},
{727, &JitIL::Default}, //"stfdx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}}, {727, &JitIL::FallBackToInterpreter}, //"stfdx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}},
{759, &JitIL::Default}, //"stfdux", OPTYPE_STOREFP, FL_IN_A | FL_IN_B}}, {759, &JitIL::FallBackToInterpreter}, //"stfdux", OPTYPE_STOREFP, FL_IN_A | FL_IN_B}},
{983, &JitIL::Default}, //"stfiwx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}}, {983, &JitIL::FallBackToInterpreter}, //"stfiwx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}},
{19, &JitIL::mfcr}, //"mfcr", OPTYPE_SYSTEM, FL_OUT_D}}, {19, &JitIL::mfcr}, //"mfcr", OPTYPE_SYSTEM, FL_OUT_D}},
{83, &JitIL::mfmsr}, //"mfmsr", OPTYPE_SYSTEM, FL_OUT_D}}, {83, &JitIL::mfmsr}, //"mfmsr", OPTYPE_SYSTEM, FL_OUT_D}},
{144, &JitIL::mtcrf}, //"mtcrf", OPTYPE_SYSTEM, 0}}, {144, &JitIL::mtcrf}, //"mtcrf", OPTYPE_SYSTEM, 0}},
{146, &JitIL::mtmsr}, //"mtmsr", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {146, &JitIL::mtmsr}, //"mtmsr", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{210, &JitIL::Default}, //"mtsr", OPTYPE_SYSTEM, 0}}, {210, &JitIL::FallBackToInterpreter}, //"mtsr", OPTYPE_SYSTEM, 0}},
{242, &JitIL::Default}, //"mtsrin", OPTYPE_SYSTEM, 0}}, {242, &JitIL::FallBackToInterpreter}, //"mtsrin", OPTYPE_SYSTEM, 0}},
{339, &JitIL::mfspr}, //"mfspr", OPTYPE_SPR, FL_OUT_D}}, {339, &JitIL::mfspr}, //"mfspr", OPTYPE_SPR, FL_OUT_D}},
{467, &JitIL::mtspr}, //"mtspr", OPTYPE_SPR, 0, 2}}, {467, &JitIL::mtspr}, //"mtspr", OPTYPE_SPR, 0, 2}},
{371, &JitIL::mftb}, //"mftb", OPTYPE_SYSTEM, FL_OUT_D | FL_TIMER}}, {371, &JitIL::mftb}, //"mftb", OPTYPE_SYSTEM, FL_OUT_D | FL_TIMER}},
{512, &JitIL::Default}, //"mcrxr", OPTYPE_SYSTEM, 0}}, {512, &JitIL::FallBackToInterpreter}, //"mcrxr", OPTYPE_SYSTEM, 0}},
{595, &JitIL::Default}, //"mfsr", OPTYPE_SYSTEM, FL_OUT_D, 2}}, {595, &JitIL::FallBackToInterpreter}, //"mfsr", OPTYPE_SYSTEM, FL_OUT_D, 2}},
{659, &JitIL::Default}, //"mfsrin", OPTYPE_SYSTEM, FL_OUT_D, 2}}, {659, &JitIL::FallBackToInterpreter}, //"mfsrin", OPTYPE_SYSTEM, FL_OUT_D, 2}},
{4, &JitIL::Default}, //"tw", OPTYPE_SYSTEM, 0, 1}}, {4, &JitIL::FallBackToInterpreter}, //"tw", OPTYPE_SYSTEM, 0, 1}},
{598, &JitIL::DoNothing}, //"sync", OPTYPE_SYSTEM, 0, 2}}, {598, &JitIL::DoNothing}, //"sync", OPTYPE_SYSTEM, 0, 2}},
{982, &JitIL::icbi}, //"icbi", OPTYPE_SYSTEM, FL_ENDBLOCK, 3}}, {982, &JitIL::icbi}, //"icbi", OPTYPE_SYSTEM, FL_ENDBLOCK, 3}},
// Unused instructions on GC // Unused instructions on GC
{310, &JitIL::Default}, //"eciwx", OPTYPE_INTEGER, FL_RC_BIT}}, {310, &JitIL::FallBackToInterpreter}, //"eciwx", OPTYPE_INTEGER, FL_RC_BIT}},
{438, &JitIL::Default}, //"ecowx", OPTYPE_INTEGER, FL_RC_BIT}}, {438, &JitIL::FallBackToInterpreter}, //"ecowx", OPTYPE_INTEGER, FL_RC_BIT}},
{854, &JitIL::Default}, //"eieio", OPTYPE_INTEGER, FL_RC_BIT}}, {854, &JitIL::FallBackToInterpreter}, //"eieio", OPTYPE_INTEGER, FL_RC_BIT}},
{306, &JitIL::Default}, //"tlbie", OPTYPE_SYSTEM, 0}}, {306, &JitIL::FallBackToInterpreter}, //"tlbie", OPTYPE_SYSTEM, 0}},
{370, &JitIL::Default}, //"tlbia", OPTYPE_SYSTEM, 0}}, {370, &JitIL::FallBackToInterpreter}, //"tlbia", OPTYPE_SYSTEM, 0}},
{566, &JitIL::Default}, //"tlbsync", OPTYPE_SYSTEM, 0}}, {566, &JitIL::FallBackToInterpreter}, //"tlbsync", OPTYPE_SYSTEM, 0}},
}; };
static GekkoOPTemplate table31_2[] = static GekkoOPTemplate table31_2[] =
{ {
{266, &JitIL::addx}, //"addx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {266, &JitIL::addx}, //"addx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{778, &JitIL::addx}, //"addx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {778, &JitIL::addx}, //"addx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{10, &JitIL::Default}, //"addcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}}, {10, &JitIL::FallBackToInterpreter}, //"addcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}},
{522, &JitIL::Default}, //"addcox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}}, {522, &JitIL::FallBackToInterpreter}, //"addcox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}},
{138, &JitIL::addex}, //"addex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {138, &JitIL::addex}, //"addex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{650, &JitIL::addex}, //"addeox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {650, &JitIL::addex}, //"addeox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{234, &JitIL::Default}, //"addmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {234, &JitIL::FallBackToInterpreter}, //"addmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{202, &JitIL::addzex}, //"addzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {202, &JitIL::addzex}, //"addzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{491, &JitIL::Default}, //"divwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}}, {491, &JitIL::FallBackToInterpreter}, //"divwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}},
{1003, &JitIL::Default}, //"divwox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}}, {1003, &JitIL::FallBackToInterpreter}, //"divwox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}},
{459, &JitIL::divwux}, //"divwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}}, {459, &JitIL::divwux}, //"divwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}},
{971, &JitIL::divwux}, //"divwuox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}}, {971, &JitIL::divwux}, //"divwuox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}},
{75, &JitIL::Default}, //"mulhwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, {75, &JitIL::FallBackToInterpreter}, //"mulhwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
{11, &JitIL::mulhwux}, //"mulhwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, {11, &JitIL::mulhwux}, //"mulhwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
{235, &JitIL::mullwx}, //"mullwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, {235, &JitIL::mullwx}, //"mullwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
{747, &JitIL::mullwx}, //"mullwox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, {747, &JitIL::mullwx}, //"mullwox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
{104, &JitIL::negx}, //"negx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {104, &JitIL::negx}, //"negx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{40, &JitIL::subfx}, //"subfx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {40, &JitIL::subfx}, //"subfx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{552, &JitIL::subfx}, //"subox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {552, &JitIL::subfx}, //"subox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{8, &JitIL::subfcx}, //"subfcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}}, {8, &JitIL::subfcx}, //"subfcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}},
{520, &JitIL::subfcx}, //"subfcox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}}, {520, &JitIL::subfcx}, //"subfcox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}},
{136, &JitIL::subfex}, //"subfex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {136, &JitIL::subfex}, //"subfex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{232, &JitIL::Default}, //"subfmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {232, &JitIL::FallBackToInterpreter}, //"subfmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{200, &JitIL::Default}, //"subfzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {200, &JitIL::FallBackToInterpreter}, //"subfzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
}; };
static GekkoOPTemplate table59[] = static GekkoOPTemplate table59[] =
{ {
{18, &JitIL::Default}, //{"fdivsx", OPTYPE_FPU, FL_RC_BIT_F, 16}}, {18, &JitIL::FallBackToInterpreter}, //{"fdivsx", OPTYPE_FPU, FL_RC_BIT_F, 16}},
{20, &JitIL::fp_arith_s}, //"fsubsx", OPTYPE_FPU, FL_RC_BIT_F}}, {20, &JitIL::fp_arith_s}, //"fsubsx", OPTYPE_FPU, FL_RC_BIT_F}},
{21, &JitIL::fp_arith_s}, //"faddsx", OPTYPE_FPU, FL_RC_BIT_F}}, {21, &JitIL::fp_arith_s}, //"faddsx", OPTYPE_FPU, FL_RC_BIT_F}},
// {22, &JitIL::Default}, //"fsqrtsx", OPTYPE_FPU, FL_RC_BIT_F}}, // Not implemented on gekko // {22, &JitIL::FallBackToInterpreter}, //"fsqrtsx", OPTYPE_FPU, FL_RC_BIT_F}}, // Not implemented on gekko
{24, &JitIL::Default}, //"fresx", OPTYPE_FPU, FL_RC_BIT_F}}, {24, &JitIL::FallBackToInterpreter}, //"fresx", OPTYPE_FPU, FL_RC_BIT_F}},
{25, &JitIL::fp_arith_s}, //"fmulsx", OPTYPE_FPU, FL_RC_BIT_F}}, {25, &JitIL::fp_arith_s}, //"fmulsx", OPTYPE_FPU, FL_RC_BIT_F}},
{28, &JitIL::fmaddXX}, //"fmsubsx", OPTYPE_FPU, FL_RC_BIT_F}}, {28, &JitIL::fmaddXX}, //"fmsubsx", OPTYPE_FPU, FL_RC_BIT_F}},
{29, &JitIL::fmaddXX}, //"fmaddsx", OPTYPE_FPU, FL_RC_BIT_F}}, {29, &JitIL::fmaddXX}, //"fmaddsx", OPTYPE_FPU, FL_RC_BIT_F}},
{30, &JitIL::fmaddXX}, //"fnmsubsx", OPTYPE_FPU, FL_RC_BIT_F}}, {30, &JitIL::fmaddXX}, //"fnmsubsx", OPTYPE_FPU, FL_RC_BIT_F}},
{31, &JitIL::fmaddXX}, //"fnmaddsx", OPTYPE_FPU, FL_RC_BIT_F}}, {31, &JitIL::fmaddXX}, //"fnmaddsx", OPTYPE_FPU, FL_RC_BIT_F}},
}; };
static GekkoOPTemplate table63[] = static GekkoOPTemplate table63[] =
{ {
{264, &JitIL::fsign}, //"fabsx", OPTYPE_FPU, FL_RC_BIT_F}}, {264, &JitIL::fsign}, //"fabsx", OPTYPE_FPU, FL_RC_BIT_F}},
{32, &JitIL::fcmpx}, //"fcmpo", OPTYPE_FPU, FL_RC_BIT_F}}, {32, &JitIL::fcmpx}, //"fcmpo", OPTYPE_FPU, FL_RC_BIT_F}},
{0, &JitIL::fcmpx}, //"fcmpu", OPTYPE_FPU, FL_RC_BIT_F}}, {0, &JitIL::fcmpx}, //"fcmpu", OPTYPE_FPU, FL_RC_BIT_F}},
{14, &JitIL::Default}, //"fctiwx", OPTYPE_FPU, FL_RC_BIT_F}}, {14, &JitIL::FallBackToInterpreter}, //"fctiwx", OPTYPE_FPU, FL_RC_BIT_F}},
{15, &JitIL::Default}, //"fctiwzx", OPTYPE_FPU, FL_RC_BIT_F}}, {15, &JitIL::FallBackToInterpreter}, //"fctiwzx", OPTYPE_FPU, FL_RC_BIT_F}},
{72, &JitIL::fmrx}, //"fmrx", OPTYPE_FPU, FL_RC_BIT_F}}, {72, &JitIL::fmrx}, //"fmrx", OPTYPE_FPU, FL_RC_BIT_F}},
{136, &JitIL::fsign}, //"fnabsx", OPTYPE_FPU, FL_RC_BIT_F}}, {136, &JitIL::fsign}, //"fnabsx", OPTYPE_FPU, FL_RC_BIT_F}},
{40, &JitIL::fsign}, //"fnegx", OPTYPE_FPU, FL_RC_BIT_F}}, {40, &JitIL::fsign}, //"fnegx", OPTYPE_FPU, FL_RC_BIT_F}},
{12, &JitIL::Default}, //"frspx", OPTYPE_FPU, FL_RC_BIT_F}}, {12, &JitIL::FallBackToInterpreter}, //"frspx", OPTYPE_FPU, FL_RC_BIT_F}},
{64, &JitIL::Default}, //"mcrfs", OPTYPE_SYSTEMFP, 0}}, {64, &JitIL::FallBackToInterpreter}, //"mcrfs", OPTYPE_SYSTEMFP, 0}},
{583, &JitIL::Default}, //"mffsx", OPTYPE_SYSTEMFP, 0}}, {583, &JitIL::FallBackToInterpreter}, //"mffsx", OPTYPE_SYSTEMFP, 0}},
{70, &JitIL::Default}, //"mtfsb0x", OPTYPE_SYSTEMFP, 0, 2}}, {70, &JitIL::FallBackToInterpreter}, //"mtfsb0x", OPTYPE_SYSTEMFP, 0, 2}},
{38, &JitIL::Default}, //"mtfsb1x", OPTYPE_SYSTEMFP, 0, 2}}, {38, &JitIL::FallBackToInterpreter}, //"mtfsb1x", OPTYPE_SYSTEMFP, 0, 2}},
{134, &JitIL::Default}, //"mtfsfix", OPTYPE_SYSTEMFP, 0, 2}}, {134, &JitIL::FallBackToInterpreter}, //"mtfsfix", OPTYPE_SYSTEMFP, 0, 2}},
{711, &JitIL::Default}, //"mtfsfx", OPTYPE_SYSTEMFP, 0, 2}}, {711, &JitIL::FallBackToInterpreter}, //"mtfsfx", OPTYPE_SYSTEMFP, 0, 2}},
}; };
static GekkoOPTemplate table63_2[] = static GekkoOPTemplate table63_2[] =
{ {
{18, &JitIL::Default}, //"fdivx", OPTYPE_FPU, FL_RC_BIT_F, 30}}, {18, &JitIL::FallBackToInterpreter}, //"fdivx", OPTYPE_FPU, FL_RC_BIT_F, 30}},
{20, &JitIL::Default}, //"fsubx", OPTYPE_FPU, FL_RC_BIT_F}}, {20, &JitIL::FallBackToInterpreter}, //"fsubx", OPTYPE_FPU, FL_RC_BIT_F}},
{21, &JitIL::Default}, //"faddx", OPTYPE_FPU, FL_RC_BIT_F}}, {21, &JitIL::FallBackToInterpreter}, //"faddx", OPTYPE_FPU, FL_RC_BIT_F}},
{22, &JitIL::Default}, //"fsqrtx", OPTYPE_FPU, FL_RC_BIT_F}}, {22, &JitIL::FallBackToInterpreter}, //"fsqrtx", OPTYPE_FPU, FL_RC_BIT_F}},
{23, &JitIL::Default}, //"fselx", OPTYPE_FPU, FL_RC_BIT_F}}, {23, &JitIL::FallBackToInterpreter}, //"fselx", OPTYPE_FPU, FL_RC_BIT_F}},
{25, &JitIL::fp_arith_s}, //"fmulx", OPTYPE_FPU, FL_RC_BIT_F}}, {25, &JitIL::fp_arith_s}, //"fmulx", OPTYPE_FPU, FL_RC_BIT_F}},
{26, &JitIL::fp_arith_s}, //"frsqrtex", OPTYPE_FPU, FL_RC_BIT_F}}, {26, &JitIL::fp_arith_s}, //"frsqrtex", OPTYPE_FPU, FL_RC_BIT_F}},
{28, &JitIL::fmaddXX}, //"fmsubx", OPTYPE_FPU, FL_RC_BIT_F}}, {28, &JitIL::fmaddXX}, //"fmsubx", OPTYPE_FPU, FL_RC_BIT_F}},
{29, &JitIL::fmaddXX}, //"fmaddx", OPTYPE_FPU, FL_RC_BIT_F}}, {29, &JitIL::fmaddXX}, //"fmaddx", OPTYPE_FPU, FL_RC_BIT_F}},
{30, &JitIL::fmaddXX}, //"fnmsubx", OPTYPE_FPU, FL_RC_BIT_F}}, {30, &JitIL::fmaddXX}, //"fnmsubx", OPTYPE_FPU, FL_RC_BIT_F}},
{31, &JitIL::fmaddXX}, //"fnmaddx", OPTYPE_FPU, FL_RC_BIT_F}}, {31, &JitIL::fmaddXX}, //"fnmaddx", OPTYPE_FPU, FL_RC_BIT_F}},
}; };
namespace JitILTables namespace JitILTables

4
Source/Core/Core/PowerPC/JitArm32/Jit.cpp
View file

@ -55,7 +55,7 @@ void JitArm::Shutdown()
asm_routines.Shutdown(); asm_routines.Shutdown();
} }
// This is only called by Default() in this file. It will execute an instruction with the interpreter functions. // This is only called by FallBackToInterpreter() in this file. It will execute an instruction with the interpreter functions.
void JitArm::WriteCallInterpreter(UGeckoInstruction inst) void JitArm::WriteCallInterpreter(UGeckoInstruction inst)
{ {
gpr.Flush(); gpr.Flush();
@ -70,7 +70,7 @@ void JitArm::unknown_instruction(UGeckoInstruction inst)
PanicAlert("unknown_instruction %08x - Fix me ;)", inst.hex); PanicAlert("unknown_instruction %08x - Fix me ;)", inst.hex);
} }
void JitArm::Default(UGeckoInstruction _inst) void JitArm::FallBackToInterpreter(UGeckoInstruction _inst)
{ {
WriteCallInterpreter(_inst.hex); WriteCallInterpreter(_inst.hex);
} }

2
Source/Core/Core/PowerPC/JitArm32/Jit.h
View file

@ -114,7 +114,7 @@ public:
// OPCODES // OPCODES
void unknown_instruction(UGeckoInstruction _inst); void unknown_instruction(UGeckoInstruction _inst);
void Default(UGeckoInstruction _inst); void FallBackToInterpreter(UGeckoInstruction _inst);
void DoNothing(UGeckoInstruction _inst); void DoNothing(UGeckoInstruction _inst);
void HLEFunction(UGeckoInstruction _inst); void HLEFunction(UGeckoInstruction _inst);

93
Source/Core/Core/PowerPC/JitArm32/JitArm_FloatingPoint.cpp
View file

@ -345,8 +345,9 @@ void JitArm::fabsx(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc) { if (inst.Rc)
Default(inst); {
FallBackToInterpreter(inst);
return; return;
} }
@ -361,8 +362,9 @@ void JitArm::fnabsx(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc) { if (inst.Rc)
Default(inst); {
FallBackToInterpreter(inst);
return; return;
} }
@ -378,8 +380,9 @@ void JitArm::fnegx(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc) { if (inst.Rc)
Default(inst); {
FallBackToInterpreter(inst);
return; return;
} }
@ -394,8 +397,9 @@ void JitArm::faddsx(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc) { if (inst.Rc)
Default(inst); {
FallBackToInterpreter(inst);
return; return;
} }
@ -413,8 +417,9 @@ void JitArm::faddx(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc) { if (inst.Rc)
Default(inst); {
FallBackToInterpreter(inst);
return; return;
} }
@ -430,8 +435,9 @@ void JitArm::fsubsx(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc) { if (inst.Rc)
Default(inst); {
FallBackToInterpreter(inst);
return; return;
} }
@ -449,8 +455,9 @@ void JitArm::fsubx(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc) { if (inst.Rc)
Default(inst); {
FallBackToInterpreter(inst);
return; return;
} }
@ -466,8 +473,9 @@ void JitArm::fmulsx(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc) { if (inst.Rc)
Default(inst); {
FallBackToInterpreter(inst);
return; return;
} }
@ -484,8 +492,9 @@ void JitArm::fmulx(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc) { if (inst.Rc)
Default(inst); {
FallBackToInterpreter(inst);
return; return;
} }
@ -500,8 +509,9 @@ void JitArm::fmrx(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc) { if (inst.Rc)
Default(inst); {
FallBackToInterpreter(inst);
return; return;
} }
@ -516,8 +526,9 @@ void JitArm::fmaddsx(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc) { if (inst.Rc)
Default(inst); {
FallBackToInterpreter(inst);
return; return;
} }
@ -546,8 +557,9 @@ void JitArm::fmaddx(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc) { if (inst.Rc)
Default(inst); {
FallBackToInterpreter(inst);
return; return;
} }
@ -576,8 +588,9 @@ void JitArm::fnmaddx(UGeckoInstruction inst)
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD; u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
if (inst.Rc) { if (inst.Rc)
Default(inst); {
FallBackToInterpreter(inst);
return; return;
} }
@ -603,8 +616,9 @@ void JitArm::fnmaddsx(UGeckoInstruction inst)
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD; u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
if (inst.Rc) { if (inst.Rc)
Default(inst); {
FallBackToInterpreter(inst);
return; return;
} }
@ -634,12 +648,14 @@ void JitArm::fresx(UGeckoInstruction inst)
u32 b = inst.FB, d = inst.FD; u32 b = inst.FB, d = inst.FD;
if (inst.Rc) { if (inst.Rc)
Default(inst); {
FallBackToInterpreter(inst);
return; return;
} }
Default(inst); return; FallBackToInterpreter(inst);
return;
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);
ARMReg vD0 = fpr.R0(d, false); ARMReg vD0 = fpr.R0(d, false);
@ -660,9 +676,12 @@ void JitArm::fselx(UGeckoInstruction inst)
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD; u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
if (inst.Rc) { if (inst.Rc)
Default(inst); return; {
FallBackToInterpreter(inst);
return;
} }
ARMReg vA0 = fpr.R0(a); ARMReg vA0 = fpr.R0(a);
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);
ARMReg vC0 = fpr.R0(c); ARMReg vC0 = fpr.R0(c);
@ -685,9 +704,13 @@ void JitArm::frsqrtex(UGeckoInstruction inst)
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
u32 b = inst.FB, d = inst.FD; u32 b = inst.FB, d = inst.FD;
if (inst.Rc){
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);
ARMReg vD0 = fpr.R0(d, false); ARMReg vD0 = fpr.R0(d, false);
ARMReg fpscrReg = gpr.GetReg(); ARMReg fpscrReg = gpr.GetReg();

17
Source/Core/Core/PowerPC/JitArm32/JitArm_Integer.cpp
View file

@ -109,7 +109,11 @@ void JitArm::subfic(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITIntegerOff) JITDISABLE(bJITIntegerOff)
Default(inst); return; // FIXME
// FIXME
FallBackToInterpreter(inst);
return;
int a = inst.RA, d = inst.RD; int a = inst.RA, d = inst.RD;
int imm = inst.SIMM_16; int imm = inst.SIMM_16;
@ -328,8 +332,9 @@ void JitArm::arith(UGeckoInstruction inst)
} }
break; break;
default: default:
WARN_LOG(DYNA_REC, "Unkown OPCD %d with arith function", inst.OPCD); WARN_LOG(DYNA_REC, "Unknown OPCD %d with arith function", inst.OPCD);
Default(inst); return; FallBackToInterpreter(inst);
return;
break; break;
} }
if (isImm[0] && isImm[1]) // Immediate propagation if (isImm[0] && isImm[1]) // Immediate propagation
@ -615,7 +620,11 @@ void JitArm::addex(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITIntegerOff) JITDISABLE(bJITIntegerOff)
u32 a = inst.RA, b = inst.RB, d = inst.RD; u32 a = inst.RA, b = inst.RB, d = inst.RD;
Default(inst); return; // FIXME
// FIXME
FallBackToInterpreter(inst);
return;
ARMReg RA = gpr.R(a); ARMReg RA = gpr.R(a);
ARMReg RB = gpr.R(b); ARMReg RB = gpr.R(b);
ARMReg RD = gpr.R(d); ARMReg RD = gpr.R(d);

21
Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStore.cpp
View file

@ -448,8 +448,11 @@ void JitArm::lmw(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff) JITDISABLE(bJITLoadStoreOff)
if (!Core::g_CoreStartupParameter.bFastmem){
Default(inst); return; if (!Core::g_CoreStartupParameter.bFastmem)
{
FallBackToInterpreter(inst);
return;
} }
u32 a = inst.RA; u32 a = inst.RA;
@ -476,8 +479,11 @@ void JitArm::stmw(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff) JITDISABLE(bJITLoadStoreOff)
if (!Core::g_CoreStartupParameter.bFastmem){
Default(inst); return; if (!Core::g_CoreStartupParameter.bFastmem)
{
FallBackToInterpreter(inst);
return;
} }
u32 a = inst.RA; u32 a = inst.RA;
@ -500,6 +506,7 @@ void JitArm::stmw(UGeckoInstruction inst)
} }
gpr.Unlock(rA, rB, rC); gpr.Unlock(rA, rB, rC);
} }
void JitArm::dcbst(UGeckoInstruction inst) void JitArm::dcbst(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
@ -511,12 +518,14 @@ void JitArm::dcbst(UGeckoInstruction inst)
// dcbt = 0x7c00022c // dcbt = 0x7c00022c
if ((Memory::ReadUnchecked_U32(js.compilerPC - 4) & 0x7c00022c) != 0x7c00022c) if ((Memory::ReadUnchecked_U32(js.compilerPC - 4) & 0x7c00022c) != 0x7c00022c)
{ {
Default(inst); return; FallBackToInterpreter(inst);
return;
} }
} }
void JitArm::icbi(UGeckoInstruction inst) void JitArm::icbi(UGeckoInstruction inst)
{ {
Default(inst); FallBackToInterpreter(inst);
WriteExit(js.compilerPC + 4); WriteExit(js.compilerPC + 4);
} }

24
Source/Core/Core/PowerPC/JitArm32/JitArm_LoadStorePaired.cpp
View file

@ -25,7 +25,11 @@ void JitArm::psq_l(UGeckoInstruction inst)
// R12 contains scale // R12 contains scale
// R11 contains type // R11 contains type
// R10 is the ADDR // R10 is the ADDR
if (js.memcheck || !Core::g_CoreStartupParameter.bFastmem) { Default(inst); return; } if (js.memcheck || !Core::g_CoreStartupParameter.bFastmem)
{
FallBackToInterpreter(inst);
return;
}
LDR(R11, R9, PPCSTATE_OFF(spr[SPR_GQR0 + inst.I])); LDR(R11, R9, PPCSTATE_OFF(spr[SPR_GQR0 + inst.I]));
UBFX(R12, R11, 16, 3); // Type UBFX(R12, R11, 16, 3); // Type
@ -63,7 +67,11 @@ void JitArm::psq_lx(UGeckoInstruction inst)
// R12 contains scale // R12 contains scale
// R11 contains type // R11 contains type
// R10 is the ADDR // R10 is the ADDR
if (js.memcheck || !Core::g_CoreStartupParameter.bFastmem) { Default(inst); return; } if (js.memcheck || !Core::g_CoreStartupParameter.bFastmem)
{
FallBackToInterpreter(inst);
return;
}
LDR(R11, R9, PPCSTATE_OFF(spr[SPR_GQR0 + inst.Ix])); LDR(R11, R9, PPCSTATE_OFF(spr[SPR_GQR0 + inst.Ix]));
UBFX(R12, R11, 16, 3); // Type UBFX(R12, R11, 16, 3); // Type
@ -113,7 +121,11 @@ void JitArm::psq_st(UGeckoInstruction inst)
// R12 contains scale // R12 contains scale
// R11 contains type // R11 contains type
// R10 is the ADDR // R10 is the ADDR
if (js.memcheck || !Core::g_CoreStartupParameter.bFastmem) { Default(inst); return; } if (js.memcheck || !Core::g_CoreStartupParameter.bFastmem)
{
FallBackToInterpreter(inst);
return;
}
LDR(R11, R9, PPCSTATE_OFF(spr[SPR_GQR0 + inst.I])); LDR(R11, R9, PPCSTATE_OFF(spr[SPR_GQR0 + inst.I]));
UBFX(R12, R11, 0, 3); // Type UBFX(R12, R11, 0, 3); // Type
@ -157,7 +169,11 @@ void JitArm::psq_stx(UGeckoInstruction inst)
// R12 contains scale // R12 contains scale
// R11 contains type // R11 contains type
// R10 is the ADDR // R10 is the ADDR
if (js.memcheck || !Core::g_CoreStartupParameter.bFastmem) { Default(inst); return; } if (js.memcheck || !Core::g_CoreStartupParameter.bFastmem)
{
FallBackToInterpreter(inst);
return;
}
LDR(R11, R9, PPCSTATE_OFF(spr[SPR_GQR0 + inst.I])); LDR(R11, R9, PPCSTATE_OFF(spr[SPR_GQR0 + inst.I]));
UBFX(R12, R11, 0, 3); // Type UBFX(R12, R11, 0, 3); // Type

191
Source/Core/Core/PowerPC/JitArm32/JitArm_Paired.cpp
View file

@ -21,9 +21,13 @@ void JitArm::ps_rsqrte(UGeckoInstruction inst)
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
u32 b = inst.FB, d = inst.FD; u32 b = inst.FB, d = inst.FD;
if (inst.Rc){
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);
ARMReg vB1 = fpr.R1(b); ARMReg vB1 = fpr.R1(b);
ARMReg vD0 = fpr.R0(d, false); ARMReg vD0 = fpr.R0(d, false);
@ -84,9 +88,12 @@ void JitArm::ps_sel(UGeckoInstruction inst)
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD; u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
if (inst.Rc) { if (inst.Rc)
Default(inst); return; {
FallBackToInterpreter(inst);
return;
} }
ARMReg vA0 = fpr.R0(a); ARMReg vA0 = fpr.R0(a);
ARMReg vA1 = fpr.R1(a); ARMReg vA1 = fpr.R1(a);
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);
@ -122,9 +129,13 @@ void JitArm::ps_add(UGeckoInstruction inst)
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
u32 a = inst.FA, b = inst.FB, d = inst.FD; u32 a = inst.FA, b = inst.FB, d = inst.FD;
if (inst.Rc){
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
ARMReg vA0 = fpr.R0(a); ARMReg vA0 = fpr.R0(a);
ARMReg vA1 = fpr.R1(a); ARMReg vA1 = fpr.R1(a);
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);
@ -142,9 +153,13 @@ void JitArm::ps_div(UGeckoInstruction inst)
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
u32 a = inst.FA, b = inst.FB, d = inst.FD; u32 a = inst.FA, b = inst.FB, d = inst.FD;
if (inst.Rc){
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
ARMReg vA0 = fpr.R0(a); ARMReg vA0 = fpr.R0(a);
ARMReg vA1 = fpr.R1(a); ARMReg vA1 = fpr.R1(a);
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);
@ -162,9 +177,13 @@ void JitArm::ps_res(UGeckoInstruction inst)
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
u32 b = inst.FB, d = inst.FD; u32 b = inst.FB, d = inst.FD;
if (inst.Rc){
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);
ARMReg vB1 = fpr.R1(b); ARMReg vB1 = fpr.R1(b);
ARMReg vD0 = fpr.R0(d, false); ARMReg vD0 = fpr.R0(d, false);
@ -184,9 +203,12 @@ void JitArm::ps_nmadd(UGeckoInstruction inst)
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD; u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
if (inst.Rc) { if (inst.Rc)
Default(inst); return; {
FallBackToInterpreter(inst);
return;
} }
ARMReg vA0 = fpr.R0(a); ARMReg vA0 = fpr.R0(a);
ARMReg vA1 = fpr.R1(a); ARMReg vA1 = fpr.R1(a);
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);
@ -217,9 +239,12 @@ void JitArm::ps_madd(UGeckoInstruction inst)
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD; u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
if (inst.Rc) { if (inst.Rc)
Default(inst); return; {
FallBackToInterpreter(inst);
return;
} }
ARMReg vA0 = fpr.R0(a); ARMReg vA0 = fpr.R0(a);
ARMReg vA1 = fpr.R1(a); ARMReg vA1 = fpr.R1(a);
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);
@ -248,9 +273,12 @@ void JitArm::ps_nmsub(UGeckoInstruction inst)
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD; u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
if (inst.Rc) { if (inst.Rc)
Default(inst); return; {
FallBackToInterpreter(inst);
return;
} }
ARMReg vA0 = fpr.R0(a); ARMReg vA0 = fpr.R0(a);
ARMReg vA1 = fpr.R1(a); ARMReg vA1 = fpr.R1(a);
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);
@ -281,9 +309,12 @@ void JitArm::ps_msub(UGeckoInstruction inst)
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD; u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
if (inst.Rc) { if (inst.Rc)
Default(inst); return; {
FallBackToInterpreter(inst);
return;
} }
ARMReg vA0 = fpr.R0(a); ARMReg vA0 = fpr.R0(a);
ARMReg vA1 = fpr.R1(a); ARMReg vA1 = fpr.R1(a);
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);
@ -312,9 +343,12 @@ void JitArm::ps_madds0(UGeckoInstruction inst)
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD; u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
if (inst.Rc) { if (inst.Rc)
Default(inst); return; {
FallBackToInterpreter(inst);
return;
} }
ARMReg vA0 = fpr.R0(a); ARMReg vA0 = fpr.R0(a);
ARMReg vA1 = fpr.R1(a); ARMReg vA1 = fpr.R1(a);
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);
@ -343,9 +377,12 @@ void JitArm::ps_madds1(UGeckoInstruction inst)
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD; u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
if (inst.Rc) { if (inst.Rc)
Default(inst); return; {
FallBackToInterpreter(inst);
return;
} }
ARMReg vA0 = fpr.R0(a); ARMReg vA0 = fpr.R0(a);
ARMReg vA1 = fpr.R1(a); ARMReg vA1 = fpr.R1(a);
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);
@ -372,9 +409,12 @@ void JitArm::ps_sum0(UGeckoInstruction inst)
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD; u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
if (inst.Rc) { if (inst.Rc)
Default(inst); return; {
FallBackToInterpreter(inst);
return;
} }
ARMReg vA0 = fpr.R0(a); ARMReg vA0 = fpr.R0(a);
ARMReg vB1 = fpr.R1(b); ARMReg vB1 = fpr.R1(b);
ARMReg vC1 = fpr.R1(c); ARMReg vC1 = fpr.R1(c);
@ -393,9 +433,12 @@ void JitArm::ps_sum1(UGeckoInstruction inst)
u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD; u32 a = inst.FA, b = inst.FB, c = inst.FC, d = inst.FD;
if (inst.Rc) { if (inst.Rc)
Default(inst); return; {
FallBackToInterpreter(inst);
return;
} }
ARMReg vA0 = fpr.R0(a); ARMReg vA0 = fpr.R0(a);
ARMReg vB1 = fpr.R1(b); ARMReg vB1 = fpr.R1(b);
ARMReg vC0 = fpr.R0(c); ARMReg vC0 = fpr.R0(c);
@ -413,9 +456,13 @@ void JitArm::ps_sub(UGeckoInstruction inst)
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
u32 a = inst.FA, b = inst.FB, d = inst.FD; u32 a = inst.FA, b = inst.FB, d = inst.FD;
if (inst.Rc){
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
ARMReg vA0 = fpr.R0(a); ARMReg vA0 = fpr.R0(a);
ARMReg vA1 = fpr.R1(a); ARMReg vA1 = fpr.R1(a);
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);
@ -433,9 +480,13 @@ void JitArm::ps_mul(UGeckoInstruction inst)
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
u32 a = inst.FA, c = inst.FC, d = inst.FD; u32 a = inst.FA, c = inst.FC, d = inst.FD;
if (inst.Rc){
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
ARMReg vA0 = fpr.R0(a); ARMReg vA0 = fpr.R0(a);
ARMReg vA1 = fpr.R1(a); ARMReg vA1 = fpr.R1(a);
ARMReg vC0 = fpr.R0(c); ARMReg vC0 = fpr.R0(c);
@ -453,9 +504,13 @@ void JitArm::ps_muls0(UGeckoInstruction inst)
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
u32 a = inst.FA, c = inst.FC, d = inst.FD; u32 a = inst.FA, c = inst.FC, d = inst.FD;
if (inst.Rc){
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
ARMReg vA0 = fpr.R0(a); ARMReg vA0 = fpr.R0(a);
ARMReg vA1 = fpr.R1(a); ARMReg vA1 = fpr.R1(a);
ARMReg vC0 = fpr.R0(c); ARMReg vC0 = fpr.R0(c);
@ -480,9 +535,13 @@ void JitArm::ps_muls1(UGeckoInstruction inst)
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
u32 a = inst.FA, c = inst.FC, d = inst.FD; u32 a = inst.FA, c = inst.FC, d = inst.FD;
if (inst.Rc){
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
ARMReg vA0 = fpr.R0(a); ARMReg vA0 = fpr.R0(a);
ARMReg vA1 = fpr.R1(a); ARMReg vA1 = fpr.R1(a);
ARMReg vC1 = fpr.R1(c); ARMReg vC1 = fpr.R1(c);
@ -505,9 +564,13 @@ void JitArm::ps_merge00(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
u32 a = inst.FA, b = inst.FB, d = inst.FD; u32 a = inst.FA, b = inst.FB, d = inst.FD;
if (inst.Rc){
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
ARMReg vA0 = fpr.R0(a); ARMReg vA0 = fpr.R0(a);
@ -523,9 +586,13 @@ void JitArm::ps_merge01(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
u32 a = inst.FA, b = inst.FB, d = inst.FD; u32 a = inst.FA, b = inst.FB, d = inst.FD;
if (inst.Rc){
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
ARMReg vA0 = fpr.R0(a); ARMReg vA0 = fpr.R0(a);
@ -540,9 +607,13 @@ void JitArm::ps_merge10(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
u32 a = inst.FA, b = inst.FB, d = inst.FD; u32 a = inst.FA, b = inst.FB, d = inst.FD;
if (inst.Rc){
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
ARMReg vA1 = fpr.R1(a); ARMReg vA1 = fpr.R1(a);
@ -562,9 +633,13 @@ void JitArm::ps_merge11(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
u32 a = inst.FA, b = inst.FB, d = inst.FD; u32 a = inst.FA, b = inst.FB, d = inst.FD;
if (inst.Rc){
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
ARMReg vA1 = fpr.R1(a); ARMReg vA1 = fpr.R1(a);
@ -579,9 +654,13 @@ void JitArm::ps_mr(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
u32 b = inst.FB, d = inst.FD; u32 b = inst.FB, d = inst.FD;
if (inst.Rc){
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);
@ -596,9 +675,13 @@ void JitArm::ps_neg(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
u32 b = inst.FB, d = inst.FD; u32 b = inst.FB, d = inst.FD;
if (inst.Rc){
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);
@ -613,9 +696,13 @@ void JitArm::ps_abs(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
u32 b = inst.FB, d = inst.FD; u32 b = inst.FB, d = inst.FD;
if (inst.Rc){
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);
@ -630,9 +717,13 @@ void JitArm::ps_nabs(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
u32 b = inst.FB, d = inst.FD; u32 b = inst.FB, d = inst.FD;
if (inst.Rc){
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
ARMReg vB0 = fpr.R0(b); ARMReg vB0 = fpr.R0(b);

4
Source/Core/Core/PowerPC/JitArm32/JitArm_SystemRegisters.cpp
View file

@ -51,7 +51,7 @@ void JitArm::mtspr(UGeckoInstruction inst)
break; break;
default: default:
Default(inst); FallBackToInterpreter(inst);
return; return;
} }
@ -77,7 +77,7 @@ void JitArm::mfspr(UGeckoInstruction inst)
case SPR_DEC: case SPR_DEC:
case SPR_TL: case SPR_TL:
case SPR_TU: case SPR_TU:
Default(inst); FallBackToInterpreter(inst);
return; return;
default: default:
ARMReg RD = gpr.R(inst.RD); ARMReg RD = gpr.R(inst.RD);

482
Source/Core/Core/PowerPC/JitArm32/JitArm_Tables.cpp
View file

@ -31,339 +31,339 @@ struct GekkoOPTemplate
static GekkoOPTemplate primarytable[] = static GekkoOPTemplate primarytable[] =
{ {
{4, &JitArm::DynaRunTable4}, //"RunTable4", OPTYPE_SUBTABLE | (4<<24), 0}}, {4, &JitArm::DynaRunTable4}, //"RunTable4", OPTYPE_SUBTABLE | (4<<24), 0}},
{19, &JitArm::DynaRunTable19}, //"RunTable19", OPTYPE_SUBTABLE | (19<<24), 0}}, {19, &JitArm::DynaRunTable19}, //"RunTable19", OPTYPE_SUBTABLE | (19<<24), 0}},
{31, &JitArm::DynaRunTable31}, //"RunTable31", OPTYPE_SUBTABLE | (31<<24), 0}}, {31, &JitArm::DynaRunTable31}, //"RunTable31", OPTYPE_SUBTABLE | (31<<24), 0}},
{59, &JitArm::DynaRunTable59}, //"RunTable59", OPTYPE_SUBTABLE | (59<<24), 0}}, {59, &JitArm::DynaRunTable59}, //"RunTable59", OPTYPE_SUBTABLE | (59<<24), 0}},
{63, &JitArm::DynaRunTable63}, //"RunTable63", OPTYPE_SUBTABLE | (63<<24), 0}}, {63, &JitArm::DynaRunTable63}, //"RunTable63", OPTYPE_SUBTABLE | (63<<24), 0}},
{16, &JitArm::bcx}, //"bcx", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {16, &JitArm::bcx}, //"bcx", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{18, &JitArm::bx}, //"bx", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {18, &JitArm::bx}, //"bx", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{1, &JitArm::HLEFunction}, //"HLEFunction", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {1, &JitArm::HLEFunction}, //"HLEFunction", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{2, &JitArm::Default}, //"DynaBlock", OPTYPE_SYSTEM, 0}}, {2, &JitArm::FallBackToInterpreter}, //"DynaBlock", OPTYPE_SYSTEM, 0}},
{3, &JitArm::twx}, //"twi", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {3, &JitArm::twx}, //"twi", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{17, &JitArm::sc}, //"sc", OPTYPE_SYSTEM, FL_ENDBLOCK, 1}}, {17, &JitArm::sc}, //"sc", OPTYPE_SYSTEM, FL_ENDBLOCK, 1}},
{7, &JitArm::arith}, //"mulli", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_RC_BIT, 2}}, {7, &JitArm::arith}, //"mulli", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_RC_BIT, 2}},
{8, &JitArm::subfic}, //"subfic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}}, {8, &JitArm::subfic}, //"subfic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}},
{10, &JitArm::cmpli}, //"cmpli", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}}, {10, &JitArm::cmpli}, //"cmpli", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}},
{11, &JitArm::cmpi}, //"cmpi", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}}, {11, &JitArm::cmpi}, //"cmpi", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}},
{12, &JitArm::arith}, //"addic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}}, {12, &JitArm::arith}, //"addic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}},
{13, &JitArm::arith}, //"addic_rc", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CR0}}, {13, &JitArm::arith}, //"addic_rc", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CR0}},
{14, &JitArm::arith}, //"addi", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}}, {14, &JitArm::arith}, //"addi", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}},
{15, &JitArm::arith}, //"addis", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}}, {15, &JitArm::arith}, //"addis", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}},
{20, &JitArm::rlwimix}, //"rlwimix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_A | FL_IN_S | FL_RC_BIT}}, {20, &JitArm::rlwimix}, //"rlwimix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_A | FL_IN_S | FL_RC_BIT}},
{21, &JitArm::rlwinmx}, //"rlwinmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, {21, &JitArm::rlwinmx}, //"rlwinmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
{23, &JitArm::rlwnmx}, //"rlwnmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_IN_B | FL_RC_BIT}}, {23, &JitArm::rlwnmx}, //"rlwnmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_IN_B | FL_RC_BIT}},
{24, &JitArm::arith}, //"ori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, {24, &JitArm::arith}, //"ori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
{25, &JitArm::arith}, //"oris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, {25, &JitArm::arith}, //"oris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
{26, &JitArm::arith}, //"xori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, {26, &JitArm::arith}, //"xori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
{27, &JitArm::arith}, //"xoris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, {27, &JitArm::arith}, //"xoris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
{28, &JitArm::arith}, //"andi_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}}, {28, &JitArm::arith}, //"andi_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}},
{29, &JitArm::arith}, //"andis_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}}, {29, &JitArm::arith}, //"andis_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}},
{32, &JitArm::lXX}, //"lwz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, {32, &JitArm::lXX}, //"lwz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
{33, &JitArm::lXX}, //"lwzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {33, &JitArm::lXX}, //"lwzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
{34, &JitArm::lXX}, //"lbz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, {34, &JitArm::lXX}, //"lbz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
{35, &JitArm::lXX}, //"lbzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {35, &JitArm::lXX}, //"lbzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
{40, &JitArm::lXX}, //"lhz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, {40, &JitArm::lXX}, //"lhz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
{41, &JitArm::lXX}, //"lhzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {41, &JitArm::lXX}, //"lhzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
{42, &JitArm::lXX}, //"lha", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, {42, &JitArm::lXX}, //"lha", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
{43, &JitArm::lXX}, //"lhau", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {43, &JitArm::lXX}, //"lhau", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
{44, &JitArm::stX}, //"sth", OPTYPE_STORE, FL_IN_A | FL_IN_S}}, {44, &JitArm::stX}, //"sth", OPTYPE_STORE, FL_IN_A | FL_IN_S}},
{45, &JitArm::stX}, //"sthu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}}, {45, &JitArm::stX}, //"sthu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
{36, &JitArm::stX}, //"stw", OPTYPE_STORE, FL_IN_A | FL_IN_S}}, {36, &JitArm::stX}, //"stw", OPTYPE_STORE, FL_IN_A | FL_IN_S}},
{37, &JitArm::stX}, //"stwu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}}, {37, &JitArm::stX}, //"stwu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
{38, &JitArm::stX}, //"stb", OPTYPE_STORE, FL_IN_A | FL_IN_S}}, {38, &JitArm::stX}, //"stb", OPTYPE_STORE, FL_IN_A | FL_IN_S}},
{39, &JitArm::stX}, //"stbu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}}, {39, &JitArm::stX}, //"stbu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
{46, &JitArm::lmw}, //"lmw", OPTYPE_SYSTEM, FL_EVIL, 10}}, {46, &JitArm::lmw}, //"lmw", OPTYPE_SYSTEM, FL_EVIL, 10}},
{47, &JitArm::stmw}, //"stmw", OPTYPE_SYSTEM, FL_EVIL, 10}}, {47, &JitArm::stmw}, //"stmw", OPTYPE_SYSTEM, FL_EVIL, 10}},
{48, &JitArm::lfXX}, //"lfs", OPTYPE_LOADFP, FL_IN_A}}, {48, &JitArm::lfXX}, //"lfs", OPTYPE_LOADFP, FL_IN_A}},
{49, &JitArm::lfXX}, //"lfsu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}}, {49, &JitArm::lfXX}, //"lfsu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}},
{50, &JitArm::lfXX}, //"lfd", OPTYPE_LOADFP, FL_IN_A}}, {50, &JitArm::lfXX}, //"lfd", OPTYPE_LOADFP, FL_IN_A}},
{51, &JitArm::lfXX}, //"lfdu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}}, {51, &JitArm::lfXX}, //"lfdu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}},
{52, &JitArm::stfs}, //"stfs", OPTYPE_STOREFP, FL_IN_A}}, {52, &JitArm::stfs}, //"stfs", OPTYPE_STOREFP, FL_IN_A}},
{53, &JitArm::stfXX}, //"stfsu", OPTYPE_STOREFP, FL_OUT_A | FL_IN_A}}, {53, &JitArm::stfXX}, //"stfsu", OPTYPE_STOREFP, FL_OUT_A | FL_IN_A}},
{54, &JitArm::stfXX}, //"stfd", OPTYPE_STOREFP, FL_IN_A}}, {54, &JitArm::stfXX}, //"stfd", OPTYPE_STOREFP, FL_IN_A}},
{55, &JitArm::stfXX}, //"stfdu", OPTYPE_STOREFP, FL_OUT_A | FL_IN_A}}, {55, &JitArm::stfXX}, //"stfdu", OPTYPE_STOREFP, FL_OUT_A | FL_IN_A}},
{56, &JitArm::psq_l}, //"psq_l", OPTYPE_PS, FL_IN_A}}, {56, &JitArm::psq_l}, //"psq_l", OPTYPE_PS, FL_IN_A}},
{57, &JitArm::psq_l}, //"psq_lu", OPTYPE_PS, FL_OUT_A | FL_IN_A}}, {57, &JitArm::psq_l}, //"psq_lu", OPTYPE_PS, FL_OUT_A | FL_IN_A}},
{60, &JitArm::psq_st}, //"psq_st", OPTYPE_PS, FL_IN_A}}, {60, &JitArm::psq_st}, //"psq_st", OPTYPE_PS, FL_IN_A}},
{61, &JitArm::psq_st}, //"psq_stu", OPTYPE_PS, FL_OUT_A | FL_IN_A}}, {61, &JitArm::psq_st}, //"psq_stu", OPTYPE_PS, FL_OUT_A | FL_IN_A}},
//missing: 0, 5, 6, 9, 22, 30, 62, 58 //missing: 0, 5, 6, 9, 22, 30, 62, 58
{0, &JitArm::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {0, &JitArm::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{5, &JitArm::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {5, &JitArm::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{6, &JitArm::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {6, &JitArm::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{9, &JitArm::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {9, &JitArm::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{22, &JitArm::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {22, &JitArm::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{30, &JitArm::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {30, &JitArm::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{62, &JitArm::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {62, &JitArm::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{58, &JitArm::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {58, &JitArm::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
}; };
static GekkoOPTemplate table4[] = static GekkoOPTemplate table4[] =
{ //SUBOP10 { //SUBOP10
{0, &JitArm::ps_cmpu0}, //"ps_cmpu0", OPTYPE_PS, FL_SET_CRn}}, {0, &JitArm::ps_cmpu0}, //"ps_cmpu0", OPTYPE_PS, FL_SET_CRn}},
{32, &JitArm::ps_cmpo0}, //"ps_cmpo0", OPTYPE_PS, FL_SET_CRn}}, {32, &JitArm::ps_cmpo0}, //"ps_cmpo0", OPTYPE_PS, FL_SET_CRn}},
{40, &JitArm::ps_neg}, //"ps_neg", OPTYPE_PS, FL_RC_BIT}}, {40, &JitArm::ps_neg}, //"ps_neg", OPTYPE_PS, FL_RC_BIT}},
{136, &JitArm::ps_nabs}, //"ps_nabs", OPTYPE_PS, FL_RC_BIT}}, {136, &JitArm::ps_nabs}, //"ps_nabs", OPTYPE_PS, FL_RC_BIT}},
{264, &JitArm::ps_abs}, //"ps_abs", OPTYPE_PS, FL_RC_BIT}}, {264, &JitArm::ps_abs}, //"ps_abs", OPTYPE_PS, FL_RC_BIT}},
{64, &JitArm::ps_cmpu1}, //"ps_cmpu1", OPTYPE_PS, FL_RC_BIT}}, {64, &JitArm::ps_cmpu1}, //"ps_cmpu1", OPTYPE_PS, FL_RC_BIT}},
{72, &JitArm::ps_mr}, //"ps_mr", OPTYPE_PS, FL_RC_BIT}}, {72, &JitArm::ps_mr}, //"ps_mr", OPTYPE_PS, FL_RC_BIT}},
{96, &JitArm::ps_cmpo1}, //"ps_cmpo1", OPTYPE_PS, FL_RC_BIT}}, {96, &JitArm::ps_cmpo1}, //"ps_cmpo1", OPTYPE_PS, FL_RC_BIT}},
{528, &JitArm::ps_merge00}, //"ps_merge00", OPTYPE_PS, FL_RC_BIT}}, {528, &JitArm::ps_merge00}, //"ps_merge00", OPTYPE_PS, FL_RC_BIT}},
{560, &JitArm::ps_merge01}, //"ps_merge01", OPTYPE_PS, FL_RC_BIT}}, {560, &JitArm::ps_merge01}, //"ps_merge01", OPTYPE_PS, FL_RC_BIT}},
{592, &JitArm::ps_merge10}, //"ps_merge10", OPTYPE_PS, FL_RC_BIT}}, {592, &JitArm::ps_merge10}, //"ps_merge10", OPTYPE_PS, FL_RC_BIT}},
{624, &JitArm::ps_merge11}, //"ps_merge11", OPTYPE_PS, FL_RC_BIT}}, {624, &JitArm::ps_merge11}, //"ps_merge11", OPTYPE_PS, FL_RC_BIT}},
{1014, &JitArm::Default}, //"dcbz_l", OPTYPE_SYSTEM, 0}}, {1014, &JitArm::FallBackToInterpreter}, //"dcbz_l", OPTYPE_SYSTEM, 0}},
}; };
static GekkoOPTemplate table4_2[] = static GekkoOPTemplate table4_2[] =
{ {
{10, &JitArm::ps_sum0}, //"ps_sum0", OPTYPE_PS, 0}}, {10, &JitArm::ps_sum0}, //"ps_sum0", OPTYPE_PS, 0}},
{11, &JitArm::ps_sum1}, //"ps_sum1", OPTYPE_PS, 0}}, {11, &JitArm::ps_sum1}, //"ps_sum1", OPTYPE_PS, 0}},
{12, &JitArm::ps_muls0}, //"ps_muls0", OPTYPE_PS, 0}}, {12, &JitArm::ps_muls0}, //"ps_muls0", OPTYPE_PS, 0}},
{13, &JitArm::ps_muls1}, //"ps_muls1", OPTYPE_PS, 0}}, {13, &JitArm::ps_muls1}, //"ps_muls1", OPTYPE_PS, 0}},
{14, &JitArm::ps_madds0}, //"ps_madds0", OPTYPE_PS, 0}}, {14, &JitArm::ps_madds0}, //"ps_madds0", OPTYPE_PS, 0}},
{15, &JitArm::ps_madds1}, //"ps_madds1", OPTYPE_PS, 0}}, {15, &JitArm::ps_madds1}, //"ps_madds1", OPTYPE_PS, 0}},
{18, &JitArm::ps_div}, //"ps_div", OPTYPE_PS, 0, 16}}, {18, &JitArm::ps_div}, //"ps_div", OPTYPE_PS, 0, 16}},
{20, &JitArm::ps_sub}, //"ps_sub", OPTYPE_PS, 0}}, {20, &JitArm::ps_sub}, //"ps_sub", OPTYPE_PS, 0}},
{21, &JitArm::ps_add}, //"ps_add", OPTYPE_PS, 0}}, {21, &JitArm::ps_add}, //"ps_add", OPTYPE_PS, 0}},
{23, &JitArm::ps_sel}, //"ps_sel", OPTYPE_PS, 0}}, {23, &JitArm::ps_sel}, //"ps_sel", OPTYPE_PS, 0}},
{24, &JitArm::ps_res}, //"ps_res", OPTYPE_PS, 0}}, {24, &JitArm::ps_res}, //"ps_res", OPTYPE_PS, 0}},
{25, &JitArm::ps_mul}, //"ps_mul", OPTYPE_PS, 0}}, {25, &JitArm::ps_mul}, //"ps_mul", OPTYPE_PS, 0}},
{26, &JitArm::ps_rsqrte}, //"ps_rsqrte", OPTYPE_PS, 0, 1}}, {26, &JitArm::ps_rsqrte}, //"ps_rsqrte", OPTYPE_PS, 0, 1}},
{28, &JitArm::ps_msub}, //"ps_msub", OPTYPE_PS, 0}}, {28, &JitArm::ps_msub}, //"ps_msub", OPTYPE_PS, 0}},
{29, &JitArm::ps_madd}, //"ps_madd", OPTYPE_PS, 0}}, {29, &JitArm::ps_madd}, //"ps_madd", OPTYPE_PS, 0}},
{30, &JitArm::ps_nmsub}, //"ps_nmsub", OPTYPE_PS, 0}}, {30, &JitArm::ps_nmsub}, //"ps_nmsub", OPTYPE_PS, 0}},
{31, &JitArm::ps_nmadd}, //"ps_nmadd", OPTYPE_PS, 0}}, {31, &JitArm::ps_nmadd}, //"ps_nmadd", OPTYPE_PS, 0}},
}; };
static GekkoOPTemplate table4_3[] = static GekkoOPTemplate table4_3[] =
{ {
{6, &JitArm::psq_lx}, //"psq_lx", OPTYPE_PS, 0}}, {6, &JitArm::psq_lx}, //"psq_lx", OPTYPE_PS, 0}},
{7, &JitArm::psq_stx}, //"psq_stx", OPTYPE_PS, 0}}, {7, &JitArm::psq_stx}, //"psq_stx", OPTYPE_PS, 0}},
{38, &JitArm::psq_lx}, //"psq_lux", OPTYPE_PS, 0}}, {38, &JitArm::psq_lx}, //"psq_lux", OPTYPE_PS, 0}},
{39, &JitArm::psq_stx}, //"psq_stux", OPTYPE_PS, 0}}, {39, &JitArm::psq_stx}, //"psq_stux", OPTYPE_PS, 0}},
}; };
static GekkoOPTemplate table19[] = static GekkoOPTemplate table19[] =
{ {
{528, &JitArm::bcctrx}, //"bcctrx", OPTYPE_BRANCH, FL_ENDBLOCK}}, {528, &JitArm::bcctrx}, //"bcctrx", OPTYPE_BRANCH, FL_ENDBLOCK}},
{16, &JitArm::bclrx}, //"bclrx", OPTYPE_BRANCH, FL_ENDBLOCK}}, {16, &JitArm::bclrx}, //"bclrx", OPTYPE_BRANCH, FL_ENDBLOCK}},
{257, &JitArm::crXXX}, //"crand", OPTYPE_CR, FL_EVIL}}, {257, &JitArm::crXXX}, //"crand", OPTYPE_CR, FL_EVIL}},
{129, &JitArm::crXXX}, //"crandc", OPTYPE_CR, FL_EVIL}}, {129, &JitArm::crXXX}, //"crandc", OPTYPE_CR, FL_EVIL}},
{289, &JitArm::crXXX}, //"creqv", OPTYPE_CR, FL_EVIL}}, {289, &JitArm::crXXX}, //"creqv", OPTYPE_CR, FL_EVIL}},
{225, &JitArm::crXXX}, //"crnand", OPTYPE_CR, FL_EVIL}}, {225, &JitArm::crXXX}, //"crnand", OPTYPE_CR, FL_EVIL}},
{33, &JitArm::crXXX}, //"crnor", OPTYPE_CR, FL_EVIL}}, {33, &JitArm::crXXX}, //"crnor", OPTYPE_CR, FL_EVIL}},
{449, &JitArm::crXXX}, //"cror", OPTYPE_CR, FL_EVIL}}, {449, &JitArm::crXXX}, //"cror", OPTYPE_CR, FL_EVIL}},
{417, &JitArm::crXXX}, //"crorc", OPTYPE_CR, FL_EVIL}}, {417, &JitArm::crXXX}, //"crorc", OPTYPE_CR, FL_EVIL}},
{193, &JitArm::crXXX}, //"crxor", OPTYPE_CR, FL_EVIL}}, {193, &JitArm::crXXX}, //"crxor", OPTYPE_CR, FL_EVIL}},
{150, &JitArm::DoNothing}, //"isync", OPTYPE_ICACHE, FL_EVIL}}, {150, &JitArm::DoNothing}, //"isync", OPTYPE_ICACHE, FL_EVIL}},
{0, &JitArm::mcrf}, //"mcrf", OPTYPE_SYSTEM, FL_EVIL}}, {0, &JitArm::mcrf}, //"mcrf", OPTYPE_SYSTEM, FL_EVIL}},
{50, &JitArm::rfi}, //"rfi", OPTYPE_SYSTEM, FL_ENDBLOCK | FL_CHECKEXCEPTIONS, 1}}, {50, &JitArm::rfi}, //"rfi", OPTYPE_SYSTEM, FL_ENDBLOCK | FL_CHECKEXCEPTIONS, 1}},
{18, &JitArm::Break}, //"rfid", OPTYPE_SYSTEM, FL_ENDBLOCK | FL_CHECKEXCEPTIONS}} {18, &JitArm::Break}, //"rfid", OPTYPE_SYSTEM, FL_ENDBLOCK | FL_CHECKEXCEPTIONS}}
}; };
static GekkoOPTemplate table31[] = static GekkoOPTemplate table31[] =
{ {
{28, &JitArm::arith}, //"andx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {28, &JitArm::arith}, //"andx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{60, &JitArm::arith}, //"andcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {60, &JitArm::arith}, //"andcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{444, &JitArm::arith}, //"orx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {444, &JitArm::arith}, //"orx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{124, &JitArm::arith}, //"norx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {124, &JitArm::arith}, //"norx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{316, &JitArm::arith}, //"xorx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {316, &JitArm::arith}, //"xorx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{412, &JitArm::arith}, //"orcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {412, &JitArm::arith}, //"orcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{476, &JitArm::arith}, //"nandx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {476, &JitArm::arith}, //"nandx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{284, &JitArm::arith}, //"eqvx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {284, &JitArm::arith}, //"eqvx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{0, &JitArm::cmp}, //"cmp", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}}, {0, &JitArm::cmp}, //"cmp", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}},
{32, &JitArm::cmpl}, //"cmpl", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}}, {32, &JitArm::cmpl}, //"cmpl", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}},
{26, &JitArm::cntlzwx}, //"cntlzwx",OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, {26, &JitArm::cntlzwx}, //"cntlzwx",OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
{922, &JitArm::extshx}, //"extshx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, {922, &JitArm::extshx}, //"extshx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
{954, &JitArm::extsbx}, //"extsbx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, {954, &JitArm::extsbx}, //"extsbx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
{536, &JitArm::arith}, //"srwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, {536, &JitArm::arith}, //"srwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
{792, &JitArm::arith}, //"srawx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, {792, &JitArm::arith}, //"srawx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
{824, &JitArm::srawix}, //"srawix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, {824, &JitArm::srawix}, //"srawix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
{24, &JitArm::arith}, //"slwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, {24, &JitArm::arith}, //"slwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
{54, &JitArm::dcbst}, //"dcbst", OPTYPE_DCACHE, 0, 4}}, {54, &JitArm::dcbst}, //"dcbst", OPTYPE_DCACHE, 0, 4}},
{86, &JitArm::Default}, //"dcbf", OPTYPE_DCACHE, 0, 4}}, {86, &JitArm::FallBackToInterpreter}, //"dcbf", OPTYPE_DCACHE, 0, 4}},
{246, &JitArm::DoNothing}, //"dcbtst", OPTYPE_DCACHE, 0, 1}}, {246, &JitArm::DoNothing}, //"dcbtst", OPTYPE_DCACHE, 0, 1}},
{278, &JitArm::DoNothing}, //"dcbt", OPTYPE_DCACHE, 0, 1}}, {278, &JitArm::DoNothing}, //"dcbt", OPTYPE_DCACHE, 0, 1}},
{470, &JitArm::Default}, //"dcbi", OPTYPE_DCACHE, 0, 4}}, {470, &JitArm::FallBackToInterpreter}, //"dcbi", OPTYPE_DCACHE, 0, 4}},
{758, &JitArm::DoNothing}, //"dcba", OPTYPE_DCACHE, 0, 4}}, {758, &JitArm::DoNothing}, //"dcba", OPTYPE_DCACHE, 0, 4}},
{1014, &JitArm::Default}, //"dcbz", OPTYPE_DCACHE, 0, 4}}, {1014, &JitArm::FallBackToInterpreter}, //"dcbz", OPTYPE_DCACHE, 0, 4}},
//load word //load word
{23, &JitArm::lXX}, //"lwzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {23, &JitArm::lXX}, //"lwzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{55, &JitArm::lXX}, //"lwzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, {55, &JitArm::lXX}, //"lwzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
//load halfword //load halfword
{279, &JitArm::lXX}, //"lhzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {279, &JitArm::lXX}, //"lhzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{311, &JitArm::lXX}, //"lhzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, {311, &JitArm::lXX}, //"lhzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
//load halfword signextend //load halfword signextend
{343, &JitArm::lXX}, //"lhax", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {343, &JitArm::lXX}, //"lhax", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{375, &JitArm::lXX}, //"lhaux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, {375, &JitArm::lXX}, //"lhaux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
//load byte //load byte
{87, &JitArm::lXX}, //"lbzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {87, &JitArm::lXX}, //"lbzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{119, &JitArm::lXX}, //"lbzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, {119, &JitArm::lXX}, //"lbzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
//load byte reverse //load byte reverse
{534, &JitArm::lXX}, //"lwbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {534, &JitArm::lXX}, //"lwbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{790, &JitArm::lXX}, //"lhbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {790, &JitArm::lXX}, //"lhbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
// Conditional load/store (Wii SMP) // Conditional load/store (Wii SMP)
{150, &JitArm::Default}, //"stwcxd", OPTYPE_STORE, FL_EVIL | FL_SET_CR0}}, {150, &JitArm::FallBackToInterpreter}, //"stwcxd", OPTYPE_STORE, FL_EVIL | FL_SET_CR0}},
{20, &JitArm::Default}, //"lwarx", OPTYPE_LOAD, FL_EVIL | FL_OUT_D | FL_IN_A0B | FL_SET_CR0}}, {20, &JitArm::FallBackToInterpreter}, //"lwarx", OPTYPE_LOAD, FL_EVIL | FL_OUT_D | FL_IN_A0B | FL_SET_CR0}},
//load string (interpret these) //load string (interpret these)
{533, &JitArm::Default}, //"lswx", OPTYPE_LOAD, FL_EVIL | FL_IN_A | FL_OUT_D}}, {533, &JitArm::FallBackToInterpreter}, //"lswx", OPTYPE_LOAD, FL_EVIL | FL_IN_A | FL_OUT_D}},
{597, &JitArm::Default}, //"lswi", OPTYPE_LOAD, FL_EVIL | FL_IN_AB | FL_OUT_D}}, {597, &JitArm::FallBackToInterpreter}, //"lswi", OPTYPE_LOAD, FL_EVIL | FL_IN_AB | FL_OUT_D}},
//store word //store word
{151, &JitArm::stX}, //"stwx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, {151, &JitArm::stX}, //"stwx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}},
{183, &JitArm::stX}, //"stwux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}}, {183, &JitArm::stX}, //"stwux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}},
//store halfword //store halfword
{407, &JitArm::stX}, //"sthx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, {407, &JitArm::stX}, //"sthx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}},
{439, &JitArm::stX}, //"sthux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}}, {439, &JitArm::stX}, //"sthux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}},
//store byte //store byte
{215, &JitArm::stX}, //"stbx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, {215, &JitArm::stX}, //"stbx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}},
{247, &JitArm::stX}, //"stbux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}}, {247, &JitArm::stX}, //"stbux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}},
//store bytereverse //store bytereverse
{662, &JitArm::Default}, //"stwbrx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, {662, &JitArm::FallBackToInterpreter}, //"stwbrx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}},
{918, &JitArm::Default}, //"sthbrx", OPTYPE_STORE, FL_IN_A | FL_IN_B}}, {918, &JitArm::FallBackToInterpreter}, //"sthbrx", OPTYPE_STORE, FL_IN_A | FL_IN_B}},
{661, &JitArm::Default}, //"stswx", OPTYPE_STORE, FL_EVIL}}, {661, &JitArm::FallBackToInterpreter}, //"stswx", OPTYPE_STORE, FL_EVIL}},
{725, &JitArm::Default}, //"stswi", OPTYPE_STORE, FL_EVIL}}, {725, &JitArm::FallBackToInterpreter}, //"stswi", OPTYPE_STORE, FL_EVIL}},
// fp load/store // fp load/store
{535, &JitArm::lfXX}, //"lfsx", OPTYPE_LOADFP, FL_IN_A0 | FL_IN_B}}, {535, &JitArm::lfXX}, //"lfsx", OPTYPE_LOADFP, FL_IN_A0 | FL_IN_B}},
{567, &JitArm::lfXX}, //"lfsux", OPTYPE_LOADFP, FL_IN_A | FL_IN_B}}, {567, &JitArm::lfXX}, //"lfsux", OPTYPE_LOADFP, FL_IN_A | FL_IN_B}},
{599, &JitArm::lfXX}, //"lfdx", OPTYPE_LOADFP, FL_IN_A0 | FL_IN_B}}, {599, &JitArm::lfXX}, //"lfdx", OPTYPE_LOADFP, FL_IN_A0 | FL_IN_B}},
{631, &JitArm::lfXX}, //"lfdux", OPTYPE_LOADFP, FL_IN_A | FL_IN_B}}, {631, &JitArm::lfXX}, //"lfdux", OPTYPE_LOADFP, FL_IN_A | FL_IN_B}},
{663, &JitArm::stfXX}, //"stfsx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}}, {663, &JitArm::stfXX}, //"stfsx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}},
{695, &JitArm::stfXX}, //"stfsux", OPTYPE_STOREFP, FL_IN_A | FL_IN_B}}, {695, &JitArm::stfXX}, //"stfsux", OPTYPE_STOREFP, FL_IN_A | FL_IN_B}},
{727, &JitArm::stfXX}, //"stfdx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}}, {727, &JitArm::stfXX}, //"stfdx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}},
{759, &JitArm::stfXX}, //"stfdux", OPTYPE_STOREFP, FL_IN_A | FL_IN_B}}, {759, &JitArm::stfXX}, //"stfdux", OPTYPE_STOREFP, FL_IN_A | FL_IN_B}},
{983, &JitArm::Default}, //"stfiwx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}}, {983, &JitArm::FallBackToInterpreter}, //"stfiwx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}},
{19, &JitArm::mfcr}, //"mfcr", OPTYPE_SYSTEM, FL_OUT_D}}, {19, &JitArm::mfcr}, //"mfcr", OPTYPE_SYSTEM, FL_OUT_D}},
{83, &JitArm::mfmsr}, //"mfmsr", OPTYPE_SYSTEM, FL_OUT_D}}, {83, &JitArm::mfmsr}, //"mfmsr", OPTYPE_SYSTEM, FL_OUT_D}},
{144, &JitArm::mtcrf}, //"mtcrf", OPTYPE_SYSTEM, 0}}, {144, &JitArm::mtcrf}, //"mtcrf", OPTYPE_SYSTEM, 0}},
{146, &JitArm::mtmsr}, //"mtmsr", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {146, &JitArm::mtmsr}, //"mtmsr", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{210, &JitArm::mtsr}, //"mtsr", OPTYPE_SYSTEM, 0}}, {210, &JitArm::mtsr}, //"mtsr", OPTYPE_SYSTEM, 0}},
{242, &JitArm::Default}, //"mtsrin", OPTYPE_SYSTEM, 0}}, {242, &JitArm::FallBackToInterpreter}, //"mtsrin", OPTYPE_SYSTEM, 0}},
{339, &JitArm::mfspr}, //"mfspr", OPTYPE_SPR, FL_OUT_D}}, {339, &JitArm::mfspr}, //"mfspr", OPTYPE_SPR, FL_OUT_D}},
{467, &JitArm::mtspr}, //"mtspr", OPTYPE_SPR, 0, 2}}, {467, &JitArm::mtspr}, //"mtspr", OPTYPE_SPR, 0, 2}},
{371, &JitArm::mftb}, //"mftb", OPTYPE_SYSTEM, FL_OUT_D | FL_TIMER}}, {371, &JitArm::mftb}, //"mftb", OPTYPE_SYSTEM, FL_OUT_D | FL_TIMER}},
{512, &JitArm::mcrxr}, //"mcrxr", OPTYPE_SYSTEM, 0}}, {512, &JitArm::mcrxr}, //"mcrxr", OPTYPE_SYSTEM, 0}},
{595, &JitArm::mfsr}, //"mfsr", OPTYPE_SYSTEM, FL_OUT_D, 2}}, {595, &JitArm::mfsr}, //"mfsr", OPTYPE_SYSTEM, FL_OUT_D, 2}},
{659, &JitArm::Default}, //"mfsrin", OPTYPE_SYSTEM, FL_OUT_D, 2}}, {659, &JitArm::FallBackToInterpreter}, //"mfsrin", OPTYPE_SYSTEM, FL_OUT_D, 2}},
{4, &JitArm::twx}, //"tw", OPTYPE_SYSTEM, FL_ENDBLOCK, 1}}, {4, &JitArm::twx}, //"tw", OPTYPE_SYSTEM, FL_ENDBLOCK, 1}},
{598, &JitArm::DoNothing}, //"sync", OPTYPE_SYSTEM, 0, 2}}, {598, &JitArm::DoNothing}, //"sync", OPTYPE_SYSTEM, 0, 2}},
{982, &JitArm::icbi}, //"icbi", OPTYPE_SYSTEM, FL_ENDBLOCK, 3}}, {982, &JitArm::icbi}, //"icbi", OPTYPE_SYSTEM, FL_ENDBLOCK, 3}},
// Unused instructions on GC // Unused instructions on GC
{310, &JitArm::Default}, //"eciwx", OPTYPE_INTEGER, FL_RC_BIT}}, {310, &JitArm::FallBackToInterpreter}, //"eciwx", OPTYPE_INTEGER, FL_RC_BIT}},
{438, &JitArm::Default}, //"ecowx", OPTYPE_INTEGER, FL_RC_BIT}}, {438, &JitArm::FallBackToInterpreter}, //"ecowx", OPTYPE_INTEGER, FL_RC_BIT}},
{854, &JitArm::Default}, //"eieio", OPTYPE_INTEGER, FL_RC_BIT}}, {854, &JitArm::FallBackToInterpreter}, //"eieio", OPTYPE_INTEGER, FL_RC_BIT}},
{306, &JitArm::Default}, //"tlbie", OPTYPE_SYSTEM, 0}}, {306, &JitArm::FallBackToInterpreter}, //"tlbie", OPTYPE_SYSTEM, 0}},
{370, &JitArm::Default}, //"tlbia", OPTYPE_SYSTEM, 0}}, {370, &JitArm::FallBackToInterpreter}, //"tlbia", OPTYPE_SYSTEM, 0}},
{566, &JitArm::Default}, //"tlbsync", OPTYPE_SYSTEM, 0}}, {566, &JitArm::FallBackToInterpreter}, //"tlbsync", OPTYPE_SYSTEM, 0}},
}; };
static GekkoOPTemplate table31_2[] = static GekkoOPTemplate table31_2[] =
{ {
{266, &JitArm::arith}, //"addx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {266, &JitArm::arith}, //"addx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{778, &JitArm::arith}, //"addx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {778, &JitArm::arith}, //"addx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{10, &JitArm::arith}, //"addcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}}, {10, &JitArm::arith}, //"addcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}},
{138, &JitArm::addex}, //"addex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {138, &JitArm::addex}, //"addex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{234, &JitArm::Default}, //"addmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {234, &JitArm::FallBackToInterpreter}, //"addmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{202, &JitArm::Default}, //"addzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {202, &JitArm::FallBackToInterpreter}, //"addzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{491, &JitArm::Default}, //"divwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}}, {491, &JitArm::FallBackToInterpreter}, //"divwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}},
{1003, &JitArm::Default}, //"divwox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}}, {1003, &JitArm::FallBackToInterpreter}, //"divwox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}},
{459, &JitArm::Default}, //"divwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}}, {459, &JitArm::FallBackToInterpreter}, //"divwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}},
{971, &JitArm::Default}, //"divwuox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}}, {971, &JitArm::FallBackToInterpreter}, //"divwuox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}},
{75, &JitArm::Default}, //"mulhwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, {75, &JitArm::FallBackToInterpreter}, //"mulhwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
{11, &JitArm::mulhwux}, //"mulhwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, {11, &JitArm::mulhwux}, //"mulhwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
{235, &JitArm::arith}, //"mullwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, {235, &JitArm::arith}, //"mullwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
{747, &JitArm::arith}, //"mullwox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, {747, &JitArm::arith}, //"mullwox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
{104, &JitArm::negx}, //"negx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {104, &JitArm::negx}, //"negx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{40, &JitArm::arith}, //"subfx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {40, &JitArm::arith}, //"subfx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{552, &JitArm::arith}, //"subox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {552, &JitArm::arith}, //"subox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{8, &JitArm::Default}, //"subfcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}}, {8, &JitArm::FallBackToInterpreter}, //"subfcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}},
{136, &JitArm::Default}, //"subfex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {136, &JitArm::FallBackToInterpreter}, //"subfex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{232, &JitArm::Default}, //"subfmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {232, &JitArm::FallBackToInterpreter}, //"subfmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{200, &JitArm::Default}, //"subfzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {200, &JitArm::FallBackToInterpreter}, //"subfzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
}; };
static GekkoOPTemplate table59[] = static GekkoOPTemplate table59[] =
{ {
{18, &JitArm::Default}, //{"fdivsx", OPTYPE_FPU, FL_RC_BIT_F, 16}}, {18, &JitArm::FallBackToInterpreter}, //{"fdivsx", OPTYPE_FPU, FL_RC_BIT_F, 16}},
{20, &JitArm::fsubsx}, //"fsubsx", OPTYPE_FPU, FL_RC_BIT_F}}, {20, &JitArm::fsubsx}, //"fsubsx", OPTYPE_FPU, FL_RC_BIT_F}},
{21, &JitArm::faddsx}, //"faddsx", OPTYPE_FPU, FL_RC_BIT_F}}, {21, &JitArm::faddsx}, //"faddsx", OPTYPE_FPU, FL_RC_BIT_F}},
// {22, &JitArm::Default}, //"fsqrtsx", OPTYPE_FPU, FL_RC_BIT_F}}, // Not implemented on gekko // {22, &JitArm::FallBackToInterpreter}, //"fsqrtsx", OPTYPE_FPU, FL_RC_BIT_F}}, // Not implemented on gekko
{24, &JitArm::fresx}, //"fresx", OPTYPE_FPU, FL_RC_BIT_F}}, {24, &JitArm::fresx}, //"fresx", OPTYPE_FPU, FL_RC_BIT_F}},
{25, &JitArm::fmulsx}, //"fmulsx", OPTYPE_FPU, FL_RC_BIT_F}}, {25, &JitArm::fmulsx}, //"fmulsx", OPTYPE_FPU, FL_RC_BIT_F}},
{28, &JitArm::Default}, //"fmsubsx", OPTYPE_FPU, FL_RC_BIT_F}}, {28, &JitArm::FallBackToInterpreter}, //"fmsubsx", OPTYPE_FPU, FL_RC_BIT_F}},
{29, &JitArm::fmaddsx}, //"fmaddsx", OPTYPE_FPU, FL_RC_BIT_F}}, {29, &JitArm::fmaddsx}, //"fmaddsx", OPTYPE_FPU, FL_RC_BIT_F}},
{30, &JitArm::Default}, //"fnmsubsx", OPTYPE_FPU, FL_RC_BIT_F}}, {30, &JitArm::FallBackToInterpreter}, //"fnmsubsx", OPTYPE_FPU, FL_RC_BIT_F}},
{31, &JitArm::fnmaddsx}, //"fnmaddsx", OPTYPE_FPU, FL_RC_BIT_F}}, {31, &JitArm::fnmaddsx}, //"fnmaddsx", OPTYPE_FPU, FL_RC_BIT_F}},
}; };
static GekkoOPTemplate table63[] = static GekkoOPTemplate table63[] =
{ {
{264, &JitArm::fabsx}, //"fabsx", OPTYPE_FPU, FL_RC_BIT_F}}, {264, &JitArm::fabsx}, //"fabsx", OPTYPE_FPU, FL_RC_BIT_F}},
{32, &JitArm::fcmpo}, //"fcmpo", OPTYPE_FPU, FL_RC_BIT_F}}, {32, &JitArm::fcmpo}, //"fcmpo", OPTYPE_FPU, FL_RC_BIT_F}},
{0, &JitArm::fcmpu}, //"fcmpu", OPTYPE_FPU, FL_RC_BIT_F}}, {0, &JitArm::fcmpu}, //"fcmpu", OPTYPE_FPU, FL_RC_BIT_F}},
{14, &JitArm::fctiwx}, //"fctiwx", OPTYPE_FPU, FL_RC_BIT_F}}, {14, &JitArm::fctiwx}, //"fctiwx", OPTYPE_FPU, FL_RC_BIT_F}},
{15, &JitArm::fctiwzx}, //"fctiwzx", OPTYPE_FPU, FL_RC_BIT_F}}, {15, &JitArm::fctiwzx}, //"fctiwzx", OPTYPE_FPU, FL_RC_BIT_F}},
{72, &JitArm::fmrx}, //"fmrx", OPTYPE_FPU, FL_RC_BIT_F}}, {72, &JitArm::fmrx}, //"fmrx", OPTYPE_FPU, FL_RC_BIT_F}},
{136, &JitArm::fnabsx}, //"fnabsx", OPTYPE_FPU, FL_RC_BIT_F}}, {136, &JitArm::fnabsx}, //"fnabsx", OPTYPE_FPU, FL_RC_BIT_F}},
{40, &JitArm::fnegx}, //"fnegx", OPTYPE_FPU, FL_RC_BIT_F}}, {40, &JitArm::fnegx}, //"fnegx", OPTYPE_FPU, FL_RC_BIT_F}},
{12, &JitArm::Default}, //"frspx", OPTYPE_FPU, FL_RC_BIT_F}}, {12, &JitArm::FallBackToInterpreter}, //"frspx", OPTYPE_FPU, FL_RC_BIT_F}},
{64, &JitArm::Default}, //"mcrfs", OPTYPE_SYSTEMFP, 0}}, {64, &JitArm::FallBackToInterpreter}, //"mcrfs", OPTYPE_SYSTEMFP, 0}},
{583, &JitArm::Default}, //"mffsx", OPTYPE_SYSTEMFP, 0}}, {583, &JitArm::FallBackToInterpreter}, //"mffsx", OPTYPE_SYSTEMFP, 0}},
{70, &JitArm::Default}, //"mtfsb0x", OPTYPE_SYSTEMFP, 0, 2}}, {70, &JitArm::FallBackToInterpreter}, //"mtfsb0x", OPTYPE_SYSTEMFP, 0, 2}},
{38, &JitArm::Default}, //"mtfsb1x", OPTYPE_SYSTEMFP, 0, 2}}, {38, &JitArm::FallBackToInterpreter}, //"mtfsb1x", OPTYPE_SYSTEMFP, 0, 2}},
{134, &JitArm::Default}, //"mtfsfix", OPTYPE_SYSTEMFP, 0, 2}}, {134, &JitArm::FallBackToInterpreter}, //"mtfsfix", OPTYPE_SYSTEMFP, 0, 2}},
{711, &JitArm::Default}, //"mtfsfx", OPTYPE_SYSTEMFP, 0, 2}}, {711, &JitArm::FallBackToInterpreter}, //"mtfsfx", OPTYPE_SYSTEMFP, 0, 2}},
}; };
static GekkoOPTemplate table63_2[] = static GekkoOPTemplate table63_2[] =
{ {
{18, &JitArm::Default}, //"fdivx", OPTYPE_FPU, FL_RC_BIT_F, 30}}, {18, &JitArm::FallBackToInterpreter}, //"fdivx", OPTYPE_FPU, FL_RC_BIT_F, 30}},
{20, &JitArm::fsubx}, //"fsubx", OPTYPE_FPU, FL_RC_BIT_F}}, {20, &JitArm::fsubx}, //"fsubx", OPTYPE_FPU, FL_RC_BIT_F}},
{21, &JitArm::faddx}, //"faddx", OPTYPE_FPU, FL_RC_BIT_F}}, {21, &JitArm::faddx}, //"faddx", OPTYPE_FPU, FL_RC_BIT_F}},
{22, &JitArm::Default}, //"fsqrtx", OPTYPE_FPU, FL_RC_BIT_F}}, {22, &JitArm::FallBackToInterpreter}, //"fsqrtx", OPTYPE_FPU, FL_RC_BIT_F}},
{23, &JitArm::fselx}, //"fselx", OPTYPE_FPU, FL_RC_BIT_F}}, {23, &JitArm::fselx}, //"fselx", OPTYPE_FPU, FL_RC_BIT_F}},
{25, &JitArm::fmulx}, //"fmulx", OPTYPE_FPU, FL_RC_BIT_F}}, {25, &JitArm::fmulx}, //"fmulx", OPTYPE_FPU, FL_RC_BIT_F}},
{26, &JitArm::frsqrtex}, //"frsqrtex", OPTYPE_FPU, FL_RC_BIT_F}}, {26, &JitArm::frsqrtex}, //"frsqrtex", OPTYPE_FPU, FL_RC_BIT_F}},
{28, &JitArm::Default}, //"fmsubx", OPTYPE_FPU, FL_RC_BIT_F}}, {28, &JitArm::FallBackToInterpreter}, //"fmsubx", OPTYPE_FPU, FL_RC_BIT_F}},
{29, &JitArm::fmaddx}, //"fmaddx", OPTYPE_FPU, FL_RC_BIT_F}}, {29, &JitArm::fmaddx}, //"fmaddx", OPTYPE_FPU, FL_RC_BIT_F}},
{30, &JitArm::Default}, //"fnmsubx", OPTYPE_FPU, FL_RC_BIT_F}}, {30, &JitArm::FallBackToInterpreter}, //"fnmsubx", OPTYPE_FPU, FL_RC_BIT_F}},
{31, &JitArm::fnmaddx}, //"fnmaddx", OPTYPE_FPU, FL_RC_BIT_F}}, {31, &JitArm::fnmaddx}, //"fnmaddx", OPTYPE_FPU, FL_RC_BIT_F}},
}; };

4
Source/Core/Core/PowerPC/JitArmIL/IR_Arm.cpp
View file

@ -310,7 +310,7 @@ static void DoWriteCode(IRBuilder* ibuild, JitArmIL* Jit, u32 exitAddress) {
case LoadGQR: case LoadGQR:
case BlockEnd: case BlockEnd:
case BlockStart: case BlockStart:
case InterpreterFallback: case FallBackToInterpreter:
case SystemCall: case SystemCall:
case RFIExit: case RFIExit:
case InterpreterBranch: case InterpreterBranch:
@ -571,7 +571,7 @@ static void DoWriteCode(IRBuilder* ibuild, JitArmIL* Jit, u32 exitAddress) {
RI.regs[reg] = I; RI.regs[reg] = I;
break; break;
} }
case InterpreterFallback: { case FallBackToInterpreter: {
unsigned InstCode = ibuild->GetImmValue(getOp1(I)); unsigned InstCode = ibuild->GetImmValue(getOp1(I));
unsigned InstLoc = ibuild->GetImmValue(getOp2(I)); unsigned InstLoc = ibuild->GetImmValue(getOp2(I));
// There really shouldn't be anything live across an // There really shouldn't be anything live across an

4
Source/Core/Core/PowerPC/JitArmIL/JitIL.cpp
View file

@ -54,9 +54,9 @@ void JitArmIL::unknown_instruction(UGeckoInstruction inst)
PanicAlert("unknown_instruction %08x - Fix me ;)", inst.hex); PanicAlert("unknown_instruction %08x - Fix me ;)", inst.hex);
} }
void JitArmIL::Default(UGeckoInstruction _inst) void JitArmIL::FallBackToInterpreter(UGeckoInstruction _inst)
{ {
ibuild.EmitInterpreterFallback( ibuild.EmitFallBackToInterpreter(
ibuild.EmitIntConst(_inst.hex), ibuild.EmitIntConst(_inst.hex),
ibuild.EmitIntConst(js.compilerPC)); ibuild.EmitIntConst(js.compilerPC));
} }

2
Source/Core/Core/PowerPC/JitArmIL/JitIL.h
View file

@ -66,7 +66,7 @@ public:
// OPCODES // OPCODES
void unknown_instruction(UGeckoInstruction inst); void unknown_instruction(UGeckoInstruction inst);
void Default(UGeckoInstruction inst); void FallBackToInterpreter(UGeckoInstruction inst);
void DoNothing(UGeckoInstruction inst); void DoNothing(UGeckoInstruction inst);
void HLEFunction(UGeckoInstruction inst); void HLEFunction(UGeckoInstruction inst);
void Break(UGeckoInstruction inst); void Break(UGeckoInstruction inst);

2
Source/Core/Core/PowerPC/JitArmIL/JitIL_Branch.cpp
View file

@ -11,7 +11,7 @@
#include "Core/PowerPC/JitArmIL/JitIL.h" #include "Core/PowerPC/JitArmIL/JitIL.h"
// FIXME // FIXME
#define NORMALBRANCH_START Default(inst); ibuild.EmitInterpreterBranch(); return; #define NORMALBRANCH_START FallBackToInterpreter(inst); ibuild.EmitInterpreterBranch(); return;
//#define NORMALBRANCH_START //#define NORMALBRANCH_START
void JitArmIL::bx(UGeckoInstruction inst) void JitArmIL::bx(UGeckoInstruction inst)

494
Source/Core/Core/PowerPC/JitArmIL/JitIL_Tables.cpp
View file

@ -31,339 +31,339 @@ struct GekkoOPTemplate
static GekkoOPTemplate primarytable[] = static GekkoOPTemplate primarytable[] =
{ {
{4, &JitArmIL::DynaRunTable4}, //"RunTable4", OPTYPE_SUBTABLE | (4<<24), 0}}, {4, &JitArmIL::DynaRunTable4}, //"RunTable4", OPTYPE_SUBTABLE | (4<<24), 0}},
{19, &JitArmIL::DynaRunTable19}, //"RunTable19", OPTYPE_SUBTABLE | (19<<24), 0}}, {19, &JitArmIL::DynaRunTable19}, //"RunTable19", OPTYPE_SUBTABLE | (19<<24), 0}},
{31, &JitArmIL::DynaRunTable31}, //"RunTable31", OPTYPE_SUBTABLE | (31<<24), 0}}, {31, &JitArmIL::DynaRunTable31}, //"RunTable31", OPTYPE_SUBTABLE | (31<<24), 0}},
{59, &JitArmIL::DynaRunTable59}, //"RunTable59", OPTYPE_SUBTABLE | (59<<24), 0}}, {59, &JitArmIL::DynaRunTable59}, //"RunTable59", OPTYPE_SUBTABLE | (59<<24), 0}},
{63, &JitArmIL::DynaRunTable63}, //"RunTable63", OPTYPE_SUBTABLE | (63<<24), 0}}, {63, &JitArmIL::DynaRunTable63}, //"RunTable63", OPTYPE_SUBTABLE | (63<<24), 0}},
{16, &JitArmIL::bcx}, //"bcx", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {16, &JitArmIL::bcx}, //"bcx", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{18, &JitArmIL::bx}, //"bx", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {18, &JitArmIL::bx}, //"bx", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{1, &JitArmIL::HLEFunction}, //"HLEFunction", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {1, &JitArmIL::HLEFunction}, //"HLEFunction", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{2, &JitArmIL::Default}, //"DynaBlock", OPTYPE_SYSTEM, 0}}, {2, &JitArmIL::FallBackToInterpreter}, //"DynaBlock", OPTYPE_SYSTEM, 0}},
{3, &JitArmIL::Break}, //"twi", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {3, &JitArmIL::Break}, //"twi", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{17, &JitArmIL::sc}, //"sc", OPTYPE_SYSTEM, FL_ENDBLOCK, 1}}, {17, &JitArmIL::sc}, //"sc", OPTYPE_SYSTEM, FL_ENDBLOCK, 1}},
{7, &JitArmIL::Default}, //"mulli", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_RC_BIT, 2}}, {7, &JitArmIL::FallBackToInterpreter}, //"mulli", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_RC_BIT, 2}},
{8, &JitArmIL::Default}, //"subfic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}}, {8, &JitArmIL::FallBackToInterpreter}, //"subfic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}},
{10, &JitArmIL::cmpXX}, //"cmpli", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}}, {10, &JitArmIL::cmpXX}, //"cmpli", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}},
{11, &JitArmIL::cmpXX}, //"cmpi", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}}, {11, &JitArmIL::cmpXX}, //"cmpi", OPTYPE_INTEGER, FL_IN_A | FL_SET_CRn}},
{12, &JitArmIL::Default}, //"addic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}}, {12, &JitArmIL::FallBackToInterpreter}, //"addic", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CA}},
{13, &JitArmIL::Default}, //"addic_rc", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CR0}}, {13, &JitArmIL::FallBackToInterpreter}, //"addic_rc", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A | FL_SET_CR0}},
{14, &JitArmIL::reg_imm}, //"addi", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}}, {14, &JitArmIL::reg_imm}, //"addi", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}},
{15, &JitArmIL::reg_imm}, //"addis", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}}, {15, &JitArmIL::reg_imm}, //"addis", OPTYPE_INTEGER, FL_OUT_D | FL_IN_A0}},
{20, &JitArmIL::Default}, //"rlwimix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_A | FL_IN_S | FL_RC_BIT}}, {20, &JitArmIL::FallBackToInterpreter}, //"rlwimix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_A | FL_IN_S | FL_RC_BIT}},
{21, &JitArmIL::Default}, //"rlwinmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, {21, &JitArmIL::FallBackToInterpreter}, //"rlwinmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
{23, &JitArmIL::Default}, //"rlwnmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_IN_B | FL_RC_BIT}}, {23, &JitArmIL::FallBackToInterpreter}, //"rlwnmx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_IN_B | FL_RC_BIT}},
{24, &JitArmIL::reg_imm}, //"ori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, {24, &JitArmIL::reg_imm}, //"ori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
{25, &JitArmIL::reg_imm}, //"oris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, {25, &JitArmIL::reg_imm}, //"oris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
{26, &JitArmIL::reg_imm}, //"xori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, {26, &JitArmIL::reg_imm}, //"xori", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
{27, &JitArmIL::reg_imm}, //"xoris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}}, {27, &JitArmIL::reg_imm}, //"xoris", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S}},
{28, &JitArmIL::reg_imm}, //"andi_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}}, {28, &JitArmIL::reg_imm}, //"andi_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}},
{29, &JitArmIL::reg_imm}, //"andis_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}}, {29, &JitArmIL::reg_imm}, //"andis_rc", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_SET_CR0}},
{32, &JitArmIL::Default}, //"lwz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, {32, &JitArmIL::FallBackToInterpreter}, //"lwz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
{33, &JitArmIL::Default}, //"lwzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {33, &JitArmIL::FallBackToInterpreter}, //"lwzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
{34, &JitArmIL::Default}, //"lbz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, {34, &JitArmIL::FallBackToInterpreter}, //"lbz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
{35, &JitArmIL::Default}, //"lbzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {35, &JitArmIL::FallBackToInterpreter}, //"lbzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
{40, &JitArmIL::Default}, //"lhz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, {40, &JitArmIL::FallBackToInterpreter}, //"lhz", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
{41, &JitArmIL::Default}, //"lhzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {41, &JitArmIL::FallBackToInterpreter}, //"lhzu", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
{42, &JitArmIL::Default}, //"lha", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}}, {42, &JitArmIL::FallBackToInterpreter}, //"lha", OPTYPE_LOAD, FL_OUT_D | FL_IN_A}},
{43, &JitArmIL::Default}, //"lhau", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}}, {43, &JitArmIL::FallBackToInterpreter}, //"lhau", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A}},
{44, &JitArmIL::Default}, //"sth", OPTYPE_STORE, FL_IN_A | FL_IN_S}}, {44, &JitArmIL::FallBackToInterpreter}, //"sth", OPTYPE_STORE, FL_IN_A | FL_IN_S}},
{45, &JitArmIL::Default}, //"sthu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}}, {45, &JitArmIL::FallBackToInterpreter}, //"sthu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
{36, &JitArmIL::Default}, //"stw", OPTYPE_STORE, FL_IN_A | FL_IN_S}}, {36, &JitArmIL::FallBackToInterpreter}, //"stw", OPTYPE_STORE, FL_IN_A | FL_IN_S}},
{37, &JitArmIL::Default}, //"stwu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}}, {37, &JitArmIL::FallBackToInterpreter}, //"stwu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
{38, &JitArmIL::Default}, //"stb", OPTYPE_STORE, FL_IN_A | FL_IN_S}}, {38, &JitArmIL::FallBackToInterpreter}, //"stb", OPTYPE_STORE, FL_IN_A | FL_IN_S}},
{39, &JitArmIL::Default}, //"stbu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}}, {39, &JitArmIL::FallBackToInterpreter}, //"stbu", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_S}},
{46, &JitArmIL::Default}, //"lmw", OPTYPE_SYSTEM, FL_EVIL, 10}}, {46, &JitArmIL::FallBackToInterpreter}, //"lmw", OPTYPE_SYSTEM, FL_EVIL, 10}},
{47, &JitArmIL::Default}, //"stmw", OPTYPE_SYSTEM, FL_EVIL, 10}}, {47, &JitArmIL::FallBackToInterpreter}, //"stmw", OPTYPE_SYSTEM, FL_EVIL, 10}},
{48, &JitArmIL::Default}, //"lfs", OPTYPE_LOADFP, FL_IN_A}}, {48, &JitArmIL::FallBackToInterpreter}, //"lfs", OPTYPE_LOADFP, FL_IN_A}},
{49, &JitArmIL::Default}, //"lfsu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}}, {49, &JitArmIL::FallBackToInterpreter}, //"lfsu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}},
{50, &JitArmIL::Default}, //"lfd", OPTYPE_LOADFP, FL_IN_A}}, {50, &JitArmIL::FallBackToInterpreter}, //"lfd", OPTYPE_LOADFP, FL_IN_A}},
{51, &JitArmIL::Default}, //"lfdu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}}, {51, &JitArmIL::FallBackToInterpreter}, //"lfdu", OPTYPE_LOADFP, FL_OUT_A | FL_IN_A}},
{52, &JitArmIL::Default}, //"stfs", OPTYPE_STOREFP, FL_IN_A}}, {52, &JitArmIL::FallBackToInterpreter}, //"stfs", OPTYPE_STOREFP, FL_IN_A}},
{53, &JitArmIL::Default}, //"stfsu", OPTYPE_STOREFP, FL_OUT_A | FL_IN_A}}, {53, &JitArmIL::FallBackToInterpreter}, //"stfsu", OPTYPE_STOREFP, FL_OUT_A | FL_IN_A}},
{54, &JitArmIL::Default}, //"stfd", OPTYPE_STOREFP, FL_IN_A}}, {54, &JitArmIL::FallBackToInterpreter}, //"stfd", OPTYPE_STOREFP, FL_IN_A}},
{55, &JitArmIL::Default}, //"stfdu", OPTYPE_STOREFP, FL_OUT_A | FL_IN_A}}, {55, &JitArmIL::FallBackToInterpreter}, //"stfdu", OPTYPE_STOREFP, FL_OUT_A | FL_IN_A}},
{56, &JitArmIL::Default}, //"psq_l", OPTYPE_PS, FL_IN_A}}, {56, &JitArmIL::FallBackToInterpreter}, //"psq_l", OPTYPE_PS, FL_IN_A}},
{57, &JitArmIL::Default}, //"psq_lu", OPTYPE_PS, FL_OUT_A | FL_IN_A}}, {57, &JitArmIL::FallBackToInterpreter}, //"psq_lu", OPTYPE_PS, FL_OUT_A | FL_IN_A}},
{60, &JitArmIL::Default}, //"psq_st", OPTYPE_PS, FL_IN_A}}, {60, &JitArmIL::FallBackToInterpreter}, //"psq_st", OPTYPE_PS, FL_IN_A}},
{61, &JitArmIL::Default}, //"psq_stu", OPTYPE_PS, FL_OUT_A | FL_IN_A}}, {61, &JitArmIL::FallBackToInterpreter}, //"psq_stu", OPTYPE_PS, FL_OUT_A | FL_IN_A}},
//missing: 0, 5, 6, 9, 22, 30, 62, 58 //missing: 0, 5, 6, 9, 22, 30, 62, 58
{0, &JitArmIL::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {0, &JitArmIL::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{5, &JitArmIL::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {5, &JitArmIL::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{6, &JitArmIL::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {6, &JitArmIL::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{9, &JitArmIL::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {9, &JitArmIL::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{22, &JitArmIL::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {22, &JitArmIL::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{30, &JitArmIL::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {30, &JitArmIL::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{62, &JitArmIL::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {62, &JitArmIL::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
{58, &JitArmIL::Default}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}}, {58, &JitArmIL::FallBackToInterpreter}, //"unknown_instruction", OPTYPE_UNKNOWN, 0}},
}; };
static GekkoOPTemplate table4[] = static GekkoOPTemplate table4[] =
{ //SUBOP10 { //SUBOP10
{0, &JitArmIL::Default}, //"ps_cmpu0", OPTYPE_PS, FL_SET_CRn}}, {0, &JitArmIL::FallBackToInterpreter}, //"ps_cmpu0", OPTYPE_PS, FL_SET_CRn}},
{32, &JitArmIL::Default}, //"ps_cmpo0", OPTYPE_PS, FL_SET_CRn}}, {32, &JitArmIL::FallBackToInterpreter}, //"ps_cmpo0", OPTYPE_PS, FL_SET_CRn}},
{40, &JitArmIL::Default}, //"ps_neg", OPTYPE_PS, FL_RC_BIT}}, {40, &JitArmIL::FallBackToInterpreter}, //"ps_neg", OPTYPE_PS, FL_RC_BIT}},
{136, &JitArmIL::Default}, //"ps_nabs", OPTYPE_PS, FL_RC_BIT}}, {136, &JitArmIL::FallBackToInterpreter}, //"ps_nabs", OPTYPE_PS, FL_RC_BIT}},
{264, &JitArmIL::Default}, //"ps_abs", OPTYPE_PS, FL_RC_BIT}}, {264, &JitArmIL::FallBackToInterpreter}, //"ps_abs", OPTYPE_PS, FL_RC_BIT}},
{64, &JitArmIL::Default}, //"ps_cmpu1", OPTYPE_PS, FL_RC_BIT}}, {64, &JitArmIL::FallBackToInterpreter}, //"ps_cmpu1", OPTYPE_PS, FL_RC_BIT}},
{72, &JitArmIL::Default}, //"ps_mr", OPTYPE_PS, FL_RC_BIT}}, {72, &JitArmIL::FallBackToInterpreter}, //"ps_mr", OPTYPE_PS, FL_RC_BIT}},
{96, &JitArmIL::Default}, //"ps_cmpo1", OPTYPE_PS, FL_RC_BIT}}, {96, &JitArmIL::FallBackToInterpreter}, //"ps_cmpo1", OPTYPE_PS, FL_RC_BIT}},
{528, &JitArmIL::Default}, //"ps_merge00", OPTYPE_PS, FL_RC_BIT}}, {528, &JitArmIL::FallBackToInterpreter}, //"ps_merge00", OPTYPE_PS, FL_RC_BIT}},
{560, &JitArmIL::Default}, //"ps_merge01", OPTYPE_PS, FL_RC_BIT}}, {560, &JitArmIL::FallBackToInterpreter}, //"ps_merge01", OPTYPE_PS, FL_RC_BIT}},
{592, &JitArmIL::Default}, //"ps_merge10", OPTYPE_PS, FL_RC_BIT}}, {592, &JitArmIL::FallBackToInterpreter}, //"ps_merge10", OPTYPE_PS, FL_RC_BIT}},
{624, &JitArmIL::Default}, //"ps_merge11", OPTYPE_PS, FL_RC_BIT}}, {624, &JitArmIL::FallBackToInterpreter}, //"ps_merge11", OPTYPE_PS, FL_RC_BIT}},
{1014, &JitArmIL::Default}, //"dcbz_l", OPTYPE_SYSTEM, 0}}, {1014, &JitArmIL::FallBackToInterpreter}, //"dcbz_l", OPTYPE_SYSTEM, 0}},
}; };
static GekkoOPTemplate table4_2[] = static GekkoOPTemplate table4_2[] =
{ {
{10, &JitArmIL::Default}, //"ps_sum0", OPTYPE_PS, 0}}, {10, &JitArmIL::FallBackToInterpreter}, //"ps_sum0", OPTYPE_PS, 0}},
{11, &JitArmIL::Default}, //"ps_sum1", OPTYPE_PS, 0}}, {11, &JitArmIL::FallBackToInterpreter}, //"ps_sum1", OPTYPE_PS, 0}},
{12, &JitArmIL::Default}, //"ps_muls0", OPTYPE_PS, 0}}, {12, &JitArmIL::FallBackToInterpreter}, //"ps_muls0", OPTYPE_PS, 0}},
{13, &JitArmIL::Default}, //"ps_muls1", OPTYPE_PS, 0}}, {13, &JitArmIL::FallBackToInterpreter}, //"ps_muls1", OPTYPE_PS, 0}},
{14, &JitArmIL::Default}, //"ps_madds0", OPTYPE_PS, 0}}, {14, &JitArmIL::FallBackToInterpreter}, //"ps_madds0", OPTYPE_PS, 0}},
{15, &JitArmIL::Default}, //"ps_madds1", OPTYPE_PS, 0}}, {15, &JitArmIL::FallBackToInterpreter}, //"ps_madds1", OPTYPE_PS, 0}},
{18, &JitArmIL::Default}, //"ps_div", OPTYPE_PS, 0, 16}}, {18, &JitArmIL::FallBackToInterpreter}, //"ps_div", OPTYPE_PS, 0, 16}},
{20, &JitArmIL::Default}, //"ps_sub", OPTYPE_PS, 0}}, {20, &JitArmIL::FallBackToInterpreter}, //"ps_sub", OPTYPE_PS, 0}},
{21, &JitArmIL::Default}, //"ps_add", OPTYPE_PS, 0}}, {21, &JitArmIL::FallBackToInterpreter}, //"ps_add", OPTYPE_PS, 0}},
{23, &JitArmIL::Default}, //"ps_sel", OPTYPE_PS, 0}}, {23, &JitArmIL::FallBackToInterpreter}, //"ps_sel", OPTYPE_PS, 0}},
{24, &JitArmIL::Default}, //"ps_res", OPTYPE_PS, 0}}, {24, &JitArmIL::FallBackToInterpreter}, //"ps_res", OPTYPE_PS, 0}},
{25, &JitArmIL::Default}, //"ps_mul", OPTYPE_PS, 0}}, {25, &JitArmIL::FallBackToInterpreter}, //"ps_mul", OPTYPE_PS, 0}},
{26, &JitArmIL::Default}, //"ps_rsqrte", OPTYPE_PS, 0, 1}}, {26, &JitArmIL::FallBackToInterpreter}, //"ps_rsqrte", OPTYPE_PS, 0, 1}},
{28, &JitArmIL::Default}, //"ps_msub", OPTYPE_PS, 0}}, {28, &JitArmIL::FallBackToInterpreter}, //"ps_msub", OPTYPE_PS, 0}},
{29, &JitArmIL::Default}, //"ps_madd", OPTYPE_PS, 0}}, {29, &JitArmIL::FallBackToInterpreter}, //"ps_madd", OPTYPE_PS, 0}},
{30, &JitArmIL::Default}, //"ps_nmsub", OPTYPE_PS, 0}}, {30, &JitArmIL::FallBackToInterpreter}, //"ps_nmsub", OPTYPE_PS, 0}},
{31, &JitArmIL::Default}, //"ps_nmadd", OPTYPE_PS, 0}}, {31, &JitArmIL::FallBackToInterpreter}, //"ps_nmadd", OPTYPE_PS, 0}},
}; };
static GekkoOPTemplate table4_3[] = static GekkoOPTemplate table4_3[] =
{ {
{6, &JitArmIL::Default}, //"psq_lx", OPTYPE_PS, 0}}, {6, &JitArmIL::FallBackToInterpreter}, //"psq_lx", OPTYPE_PS, 0}},
{7, &JitArmIL::Default}, //"psq_stx", OPTYPE_PS, 0}}, {7, &JitArmIL::FallBackToInterpreter}, //"psq_stx", OPTYPE_PS, 0}},
{38, &JitArmIL::Default}, //"psq_lux", OPTYPE_PS, 0}}, {38, &JitArmIL::FallBackToInterpreter}, //"psq_lux", OPTYPE_PS, 0}},
{39, &JitArmIL::Default}, //"psq_stux", OPTYPE_PS, 0}}, {39, &JitArmIL::FallBackToInterpreter}, //"psq_stux", OPTYPE_PS, 0}},
}; };
static GekkoOPTemplate table19[] = static GekkoOPTemplate table19[] =
{ {
{528, &JitArmIL::bcctrx}, //"bcctrx", OPTYPE_BRANCH, FL_ENDBLOCK}}, {528, &JitArmIL::bcctrx}, //"bcctrx", OPTYPE_BRANCH, FL_ENDBLOCK}},
{16, &JitArmIL::bclrx}, //"bclrx", OPTYPE_BRANCH, FL_ENDBLOCK}}, {16, &JitArmIL::bclrx}, //"bclrx", OPTYPE_BRANCH, FL_ENDBLOCK}},
{257, &JitArmIL::crXX}, //"crand", OPTYPE_CR, FL_EVIL}}, {257, &JitArmIL::crXX}, //"crand", OPTYPE_CR, FL_EVIL}},
{129, &JitArmIL::crXX}, //"crandc", OPTYPE_CR, FL_EVIL}}, {129, &JitArmIL::crXX}, //"crandc", OPTYPE_CR, FL_EVIL}},
{289, &JitArmIL::crXX}, //"creqv", OPTYPE_CR, FL_EVIL}}, {289, &JitArmIL::crXX}, //"creqv", OPTYPE_CR, FL_EVIL}},
{225, &JitArmIL::crXX}, //"crnand", OPTYPE_CR, FL_EVIL}}, {225, &JitArmIL::crXX}, //"crnand", OPTYPE_CR, FL_EVIL}},
{33, &JitArmIL::crXX}, //"crnor", OPTYPE_CR, FL_EVIL}}, {33, &JitArmIL::crXX}, //"crnor", OPTYPE_CR, FL_EVIL}},
{449, &JitArmIL::crXX}, //"cror", OPTYPE_CR, FL_EVIL}}, {449, &JitArmIL::crXX}, //"cror", OPTYPE_CR, FL_EVIL}},
{417, &JitArmIL::crXX}, //"crorc", OPTYPE_CR, FL_EVIL}}, {417, &JitArmIL::crXX}, //"crorc", OPTYPE_CR, FL_EVIL}},
{193, &JitArmIL::crXX}, //"crxor", OPTYPE_CR, FL_EVIL}}, {193, &JitArmIL::crXX}, //"crxor", OPTYPE_CR, FL_EVIL}},
{150, &JitArmIL::Default}, //"isync", OPTYPE_ICACHE, FL_EVIL}}, {150, &JitArmIL::FallBackToInterpreter}, //"isync", OPTYPE_ICACHE, FL_EVIL}},
{0, &JitArmIL::Default}, //"mcrf", OPTYPE_SYSTEM, FL_EVIL}}, {0, &JitArmIL::FallBackToInterpreter}, //"mcrf", OPTYPE_SYSTEM, FL_EVIL}},
{50, &JitArmIL::rfi}, //"rfi", OPTYPE_SYSTEM, FL_ENDBLOCK | FL_CHECKEXCEPTIONS, 1}}, {50, &JitArmIL::rfi}, //"rfi", OPTYPE_SYSTEM, FL_ENDBLOCK | FL_CHECKEXCEPTIONS, 1}},
{18, &JitArmIL::Break}, //"rfid", OPTYPE_SYSTEM, FL_ENDBLOCK | FL_CHECKEXCEPTIONS}} {18, &JitArmIL::Break}, //"rfid", OPTYPE_SYSTEM, FL_ENDBLOCK | FL_CHECKEXCEPTIONS}}
}; };
static GekkoOPTemplate table31[] = static GekkoOPTemplate table31[] =
{ {
{28, &JitArmIL::boolX}, //"andx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {28, &JitArmIL::boolX}, //"andx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{60, &JitArmIL::boolX}, //"andcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {60, &JitArmIL::boolX}, //"andcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{444, &JitArmIL::boolX}, //"orx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {444, &JitArmIL::boolX}, //"orx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{124, &JitArmIL::boolX}, //"norx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {124, &JitArmIL::boolX}, //"norx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{316, &JitArmIL::boolX}, //"xorx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {316, &JitArmIL::boolX}, //"xorx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{412, &JitArmIL::boolX}, //"orcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {412, &JitArmIL::boolX}, //"orcx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{476, &JitArmIL::boolX}, //"nandx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {476, &JitArmIL::boolX}, //"nandx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{284, &JitArmIL::boolX}, //"eqvx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}}, {284, &JitArmIL::boolX}, //"eqvx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_SB | FL_RC_BIT}},
{0, &JitArmIL::cmpXX}, //"cmp", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}}, {0, &JitArmIL::cmpXX}, //"cmp", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}},
{32, &JitArmIL::cmpXX}, //"cmpl", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}}, {32, &JitArmIL::cmpXX}, //"cmpl", OPTYPE_INTEGER, FL_IN_AB | FL_SET_CRn}},
{26, &JitArmIL::Default}, //"cntlzwx",OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, {26, &JitArmIL::FallBackToInterpreter}, //"cntlzwx",OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
{922, &JitArmIL::Default}, //"extshx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, {922, &JitArmIL::FallBackToInterpreter}, //"extshx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
{954, &JitArmIL::Default}, //"extsbx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}}, {954, &JitArmIL::FallBackToInterpreter}, //"extsbx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_S | FL_RC_BIT}},
{536, &JitArmIL::Default}, //"srwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, {536, &JitArmIL::FallBackToInterpreter}, //"srwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
{792, &JitArmIL::Default}, //"srawx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, {792, &JitArmIL::FallBackToInterpreter}, //"srawx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
{824, &JitArmIL::Default}, //"srawix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, {824, &JitArmIL::FallBackToInterpreter}, //"srawix", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
{24, &JitArmIL::Default}, //"slwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}}, {24, &JitArmIL::FallBackToInterpreter}, //"slwx", OPTYPE_INTEGER, FL_OUT_A | FL_IN_B | FL_IN_S | FL_RC_BIT}},
{54, &JitArmIL::Default}, //"dcbst", OPTYPE_DCACHE, 0, 4}}, {54, &JitArmIL::FallBackToInterpreter}, //"dcbst", OPTYPE_DCACHE, 0, 4}},
{86, &JitArmIL::Default}, //"dcbf", OPTYPE_DCACHE, 0, 4}}, {86, &JitArmIL::FallBackToInterpreter}, //"dcbf", OPTYPE_DCACHE, 0, 4}},
{246, &JitArmIL::Default}, //"dcbtst", OPTYPE_DCACHE, 0, 1}}, {246, &JitArmIL::FallBackToInterpreter}, //"dcbtst", OPTYPE_DCACHE, 0, 1}},
{278, &JitArmIL::Default}, //"dcbt", OPTYPE_DCACHE, 0, 1}}, {278, &JitArmIL::FallBackToInterpreter}, //"dcbt", OPTYPE_DCACHE, 0, 1}},
{470, &JitArmIL::Default}, //"dcbi", OPTYPE_DCACHE, 0, 4}}, {470, &JitArmIL::FallBackToInterpreter}, //"dcbi", OPTYPE_DCACHE, 0, 4}},
{758, &JitArmIL::Default}, //"dcba", OPTYPE_DCACHE, 0, 4}}, {758, &JitArmIL::FallBackToInterpreter}, //"dcba", OPTYPE_DCACHE, 0, 4}},
{1014, &JitArmIL::Default}, //"dcbz", OPTYPE_DCACHE, 0, 4}}, {1014, &JitArmIL::FallBackToInterpreter}, //"dcbz", OPTYPE_DCACHE, 0, 4}},
//load word //load word
{23, &JitArmIL::Default}, //"lwzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {23, &JitArmIL::FallBackToInterpreter}, //"lwzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{55, &JitArmIL::Default}, //"lwzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, {55, &JitArmIL::FallBackToInterpreter}, //"lwzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
//load halfword //load halfword
{279, &JitArmIL::Default}, //"lhzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {279, &JitArmIL::FallBackToInterpreter}, //"lhzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{311, &JitArmIL::Default}, //"lhzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, {311, &JitArmIL::FallBackToInterpreter}, //"lhzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
//load halfword signextend //load halfword signextend
{343, &JitArmIL::Default}, //"lhax", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {343, &JitArmIL::FallBackToInterpreter}, //"lhax", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{375, &JitArmIL::Default}, //"lhaux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, {375, &JitArmIL::FallBackToInterpreter}, //"lhaux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
//load byte //load byte
{87, &JitArmIL::Default}, //"lbzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {87, &JitArmIL::FallBackToInterpreter}, //"lbzx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{119, &JitArmIL::Default}, //"lbzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}}, {119, &JitArmIL::FallBackToInterpreter}, //"lbzux", OPTYPE_LOAD, FL_OUT_D | FL_OUT_A | FL_IN_A | FL_IN_B}},
//load byte reverse //load byte reverse
{534, &JitArmIL::Default}, //"lwbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {534, &JitArmIL::FallBackToInterpreter}, //"lwbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
{790, &JitArmIL::Default}, //"lhbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}}, {790, &JitArmIL::FallBackToInterpreter}, //"lhbrx", OPTYPE_LOAD, FL_OUT_D | FL_IN_A0 | FL_IN_B}},
// Conditional load/store (Wii SMP) // Conditional load/store (Wii SMP)
{150, &JitArmIL::Default}, //"stwcxd", OPTYPE_STORE, FL_EVIL | FL_SET_CR0}}, {150, &JitArmIL::FallBackToInterpreter}, //"stwcxd", OPTYPE_STORE, FL_EVIL | FL_SET_CR0}},
{20, &JitArmIL::Default}, //"lwarx", OPTYPE_LOAD, FL_EVIL | FL_OUT_D | FL_IN_A0B | FL_SET_CR0}}, {20, &JitArmIL::FallBackToInterpreter}, //"lwarx", OPTYPE_LOAD, FL_EVIL | FL_OUT_D | FL_IN_A0B | FL_SET_CR0}},
//load string (interpret these) //load string (interpret these)
{533, &JitArmIL::Default}, //"lswx", OPTYPE_LOAD, FL_EVIL | FL_IN_A | FL_OUT_D}}, {533, &JitArmIL::FallBackToInterpreter}, //"lswx", OPTYPE_LOAD, FL_EVIL | FL_IN_A | FL_OUT_D}},
{597, &JitArmIL::Default}, //"lswi", OPTYPE_LOAD, FL_EVIL | FL_IN_AB | FL_OUT_D}}, {597, &JitArmIL::FallBackToInterpreter}, //"lswi", OPTYPE_LOAD, FL_EVIL | FL_IN_AB | FL_OUT_D}},
//store word //store word
{151, &JitArmIL::Default}, //"stwx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, {151, &JitArmIL::FallBackToInterpreter}, //"stwx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}},
{183, &JitArmIL::Default}, //"stwux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}}, {183, &JitArmIL::FallBackToInterpreter}, //"stwux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}},
//store halfword //store halfword
{407, &JitArmIL::Default}, //"sthx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, {407, &JitArmIL::FallBackToInterpreter}, //"sthx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}},
{439, &JitArmIL::Default}, //"sthux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}}, {439, &JitArmIL::FallBackToInterpreter}, //"sthux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}},
//store byte //store byte
{215, &JitArmIL::Default}, //"stbx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, {215, &JitArmIL::FallBackToInterpreter}, //"stbx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}},
{247, &JitArmIL::Default}, //"stbux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}}, {247, &JitArmIL::FallBackToInterpreter}, //"stbux", OPTYPE_STORE, FL_OUT_A | FL_IN_A | FL_IN_B}},
//store bytereverse //store bytereverse
{662, &JitArmIL::Default}, //"stwbrx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}}, {662, &JitArmIL::FallBackToInterpreter}, //"stwbrx", OPTYPE_STORE, FL_IN_A0 | FL_IN_B}},
{918, &JitArmIL::Default}, //"sthbrx", OPTYPE_STORE, FL_IN_A | FL_IN_B}}, {918, &JitArmIL::FallBackToInterpreter}, //"sthbrx", OPTYPE_STORE, FL_IN_A | FL_IN_B}},
{661, &JitArmIL::Default}, //"stswx", OPTYPE_STORE, FL_EVIL}}, {661, &JitArmIL::FallBackToInterpreter}, //"stswx", OPTYPE_STORE, FL_EVIL}},
{725, &JitArmIL::Default}, //"stswi", OPTYPE_STORE, FL_EVIL}}, {725, &JitArmIL::FallBackToInterpreter}, //"stswi", OPTYPE_STORE, FL_EVIL}},
// fp load/store // fp load/store
{535, &JitArmIL::Default}, //"lfsx", OPTYPE_LOADFP, FL_IN_A0 | FL_IN_B}}, {535, &JitArmIL::FallBackToInterpreter}, //"lfsx", OPTYPE_LOADFP, FL_IN_A0 | FL_IN_B}},
{567, &JitArmIL::Default}, //"lfsux", OPTYPE_LOADFP, FL_IN_A | FL_IN_B}}, {567, &JitArmIL::FallBackToInterpreter}, //"lfsux", OPTYPE_LOADFP, FL_IN_A | FL_IN_B}},
{599, &JitArmIL::Default}, //"lfdx", OPTYPE_LOADFP, FL_IN_A0 | FL_IN_B}}, {599, &JitArmIL::FallBackToInterpreter}, //"lfdx", OPTYPE_LOADFP, FL_IN_A0 | FL_IN_B}},
{631, &JitArmIL::Default}, //"lfdux", OPTYPE_LOADFP, FL_IN_A | FL_IN_B}}, {631, &JitArmIL::FallBackToInterpreter}, //"lfdux", OPTYPE_LOADFP, FL_IN_A | FL_IN_B}},
{663, &JitArmIL::Default}, //"stfsx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}}, {663, &JitArmIL::FallBackToInterpreter}, //"stfsx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}},
{695, &JitArmIL::Default}, //"stfsux", OPTYPE_STOREFP, FL_IN_A | FL_IN_B}}, {695, &JitArmIL::FallBackToInterpreter}, //"stfsux", OPTYPE_STOREFP, FL_IN_A | FL_IN_B}},
{727, &JitArmIL::Default}, //"stfdx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}}, {727, &JitArmIL::FallBackToInterpreter}, //"stfdx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}},
{759, &JitArmIL::Default}, //"stfdux", OPTYPE_STOREFP, FL_IN_A | FL_IN_B}}, {759, &JitArmIL::FallBackToInterpreter}, //"stfdux", OPTYPE_STOREFP, FL_IN_A | FL_IN_B}},
{983, &JitArmIL::Default}, //"stfiwx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}}, {983, &JitArmIL::FallBackToInterpreter}, //"stfiwx", OPTYPE_STOREFP, FL_IN_A0 | FL_IN_B}},
{19, &JitArmIL::Default}, //"mfcr", OPTYPE_SYSTEM, FL_OUT_D}}, {19, &JitArmIL::FallBackToInterpreter}, //"mfcr", OPTYPE_SYSTEM, FL_OUT_D}},
{83, &JitArmIL::Default}, //"mfmsr", OPTYPE_SYSTEM, FL_OUT_D}}, {83, &JitArmIL::FallBackToInterpreter}, //"mfmsr", OPTYPE_SYSTEM, FL_OUT_D}},
{144, &JitArmIL::Default}, //"mtcrf", OPTYPE_SYSTEM, 0}}, {144, &JitArmIL::FallBackToInterpreter}, //"mtcrf", OPTYPE_SYSTEM, 0}},
{146, &JitArmIL::mtmsr}, //"mtmsr", OPTYPE_SYSTEM, FL_ENDBLOCK}}, {146, &JitArmIL::mtmsr}, //"mtmsr", OPTYPE_SYSTEM, FL_ENDBLOCK}},
{210, &JitArmIL::Default}, //"mtsr", OPTYPE_SYSTEM, 0}}, {210, &JitArmIL::FallBackToInterpreter}, //"mtsr", OPTYPE_SYSTEM, 0}},
{242, &JitArmIL::Default}, //"mtsrin", OPTYPE_SYSTEM, 0}}, {242, &JitArmIL::FallBackToInterpreter}, //"mtsrin", OPTYPE_SYSTEM, 0}},
{339, &JitArmIL::Default}, //"mfspr", OPTYPE_SPR, FL_OUT_D}}, {339, &JitArmIL::FallBackToInterpreter}, //"mfspr", OPTYPE_SPR, FL_OUT_D}},
{467, &JitArmIL::Default}, //"mtspr", OPTYPE_SPR, 0, 2}}, {467, &JitArmIL::FallBackToInterpreter}, //"mtspr", OPTYPE_SPR, 0, 2}},
{371, &JitArmIL::Default}, //"mftb", OPTYPE_SYSTEM, FL_OUT_D | FL_TIMER}}, {371, &JitArmIL::FallBackToInterpreter}, //"mftb", OPTYPE_SYSTEM, FL_OUT_D | FL_TIMER}},
{512, &JitArmIL::Default}, //"mcrxr", OPTYPE_SYSTEM, 0}}, {512, &JitArmIL::FallBackToInterpreter}, //"mcrxr", OPTYPE_SYSTEM, 0}},
{595, &JitArmIL::Default}, //"mfsr", OPTYPE_SYSTEM, FL_OUT_D, 2}}, {595, &JitArmIL::FallBackToInterpreter}, //"mfsr", OPTYPE_SYSTEM, FL_OUT_D, 2}},
{659, &JitArmIL::Default}, //"mfsrin", OPTYPE_SYSTEM, FL_OUT_D, 2}}, {659, &JitArmIL::FallBackToInterpreter}, //"mfsrin", OPTYPE_SYSTEM, FL_OUT_D, 2}},
{4, &JitArmIL::Break}, //"tw", OPTYPE_SYSTEM, FL_ENDBLOCK, 1}}, {4, &JitArmIL::Break}, //"tw", OPTYPE_SYSTEM, FL_ENDBLOCK, 1}},
{598, &JitArmIL::Default}, //"sync", OPTYPE_SYSTEM, 0, 2}}, {598, &JitArmIL::FallBackToInterpreter}, //"sync", OPTYPE_SYSTEM, 0, 2}},
{982, &JitArmIL::icbi}, //"icbi", OPTYPE_SYSTEM, FL_ENDBLOCK, 3}}, {982, &JitArmIL::icbi}, //"icbi", OPTYPE_SYSTEM, FL_ENDBLOCK, 3}},
// Unused instructions on GC // Unused instructions on GC
{310, &JitArmIL::Default}, //"eciwx", OPTYPE_INTEGER, FL_RC_BIT}}, {310, &JitArmIL::FallBackToInterpreter}, //"eciwx", OPTYPE_INTEGER, FL_RC_BIT}},
{438, &JitArmIL::Default}, //"ecowx", OPTYPE_INTEGER, FL_RC_BIT}}, {438, &JitArmIL::FallBackToInterpreter}, //"ecowx", OPTYPE_INTEGER, FL_RC_BIT}},
{854, &JitArmIL::Default}, //"eieio", OPTYPE_INTEGER, FL_RC_BIT}}, {854, &JitArmIL::FallBackToInterpreter}, //"eieio", OPTYPE_INTEGER, FL_RC_BIT}},
{306, &JitArmIL::Default}, //"tlbie", OPTYPE_SYSTEM, 0}}, {306, &JitArmIL::FallBackToInterpreter}, //"tlbie", OPTYPE_SYSTEM, 0}},
{370, &JitArmIL::Default}, //"tlbia", OPTYPE_SYSTEM, 0}}, {370, &JitArmIL::FallBackToInterpreter}, //"tlbia", OPTYPE_SYSTEM, 0}},
{566, &JitArmIL::Default}, //"tlbsync", OPTYPE_SYSTEM, 0}}, {566, &JitArmIL::FallBackToInterpreter}, //"tlbsync", OPTYPE_SYSTEM, 0}},
}; };
static GekkoOPTemplate table31_2[] = static GekkoOPTemplate table31_2[] =
{ {
{266, &JitArmIL::Default}, //"addx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {266, &JitArmIL::FallBackToInterpreter}, //"addx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{778, &JitArmIL::Default}, //"addx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {778, &JitArmIL::FallBackToInterpreter}, //"addx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{10, &JitArmIL::Default}, //"addcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}}, {10, &JitArmIL::FallBackToInterpreter}, //"addcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}},
{138, &JitArmIL::Default}, //"addex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {138, &JitArmIL::FallBackToInterpreter}, //"addex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{234, &JitArmIL::Default}, //"addmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {234, &JitArmIL::FallBackToInterpreter}, //"addmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{202, &JitArmIL::Default}, //"addzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {202, &JitArmIL::FallBackToInterpreter}, //"addzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{491, &JitArmIL::Default}, //"divwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}}, {491, &JitArmIL::FallBackToInterpreter}, //"divwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}},
{1003, &JitArmIL::Default}, //"divwox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}}, {1003, &JitArmIL::FallBackToInterpreter}, //"divwox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}},
{459, &JitArmIL::Default}, //"divwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}}, {459, &JitArmIL::FallBackToInterpreter}, //"divwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}},
{971, &JitArmIL::Default}, //"divwuox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}}, {971, &JitArmIL::FallBackToInterpreter}, //"divwuox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 39}},
{75, &JitArmIL::Default}, //"mulhwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, {75, &JitArmIL::FallBackToInterpreter}, //"mulhwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
{11, &JitArmIL::Default}, //"mulhwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, {11, &JitArmIL::FallBackToInterpreter}, //"mulhwux", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
{235, &JitArmIL::Default}, //"mullwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, {235, &JitArmIL::FallBackToInterpreter}, //"mullwx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
{747, &JitArmIL::Default}, //"mullwox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}}, {747, &JitArmIL::FallBackToInterpreter}, //"mullwox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT, 4}},
{104, &JitArmIL::Default}, //"negx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {104, &JitArmIL::FallBackToInterpreter}, //"negx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{40, &JitArmIL::Default}, //"subfx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {40, &JitArmIL::FallBackToInterpreter}, //"subfx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{552, &JitArmIL::Default}, //"subox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}}, {552, &JitArmIL::FallBackToInterpreter}, //"subox", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_RC_BIT}},
{8, &JitArmIL::Default}, //"subfcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}}, {8, &JitArmIL::FallBackToInterpreter}, //"subfcx", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_SET_CA | FL_RC_BIT}},
{136, &JitArmIL::Default}, //"subfex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {136, &JitArmIL::FallBackToInterpreter}, //"subfex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{232, &JitArmIL::Default}, //"subfmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {232, &JitArmIL::FallBackToInterpreter}, //"subfmex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
{200, &JitArmIL::Default}, //"subfzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}}, {200, &JitArmIL::FallBackToInterpreter}, //"subfzex", OPTYPE_INTEGER, FL_OUT_D | FL_IN_AB | FL_READ_CA | FL_SET_CA | FL_RC_BIT}},
}; };
static GekkoOPTemplate table59[] = static GekkoOPTemplate table59[] =
{ {
{18, &JitArmIL::Default}, //{"fdivsx", OPTYPE_FPU, FL_RC_BIT_F, 16}}, {18, &JitArmIL::FallBackToInterpreter}, //{"fdivsx", OPTYPE_FPU, FL_RC_BIT_F, 16}},
{20, &JitArmIL::Default}, //"fsubsx", OPTYPE_FPU, FL_RC_BIT_F}}, {20, &JitArmIL::FallBackToInterpreter}, //"fsubsx", OPTYPE_FPU, FL_RC_BIT_F}},
{21, &JitArmIL::Default}, //"faddsx", OPTYPE_FPU, FL_RC_BIT_F}}, {21, &JitArmIL::FallBackToInterpreter}, //"faddsx", OPTYPE_FPU, FL_RC_BIT_F}},
// {22, &JitArmIL::Default}, //"fsqrtsx", OPTYPE_FPU, FL_RC_BIT_F}}, // {22, &JitArmIL::FallBackToInterpreter}, //"fsqrtsx", OPTYPE_FPU, FL_RC_BIT_F}},
{24, &JitArmIL::Default}, //"fresx", OPTYPE_FPU, FL_RC_BIT_F}}, {24, &JitArmIL::FallBackToInterpreter}, //"fresx", OPTYPE_FPU, FL_RC_BIT_F}},
{25, &JitArmIL::Default}, //"fmulsx", OPTYPE_FPU, FL_RC_BIT_F}}, {25, &JitArmIL::FallBackToInterpreter}, //"fmulsx", OPTYPE_FPU, FL_RC_BIT_F}},
{28, &JitArmIL::Default}, //"fmsubsx", OPTYPE_FPU, FL_RC_BIT_F}}, {28, &JitArmIL::FallBackToInterpreter}, //"fmsubsx", OPTYPE_FPU, FL_RC_BIT_F}},
{29, &JitArmIL::Default}, //"fmaddsx", OPTYPE_FPU, FL_RC_BIT_F}}, {29, &JitArmIL::FallBackToInterpreter}, //"fmaddsx", OPTYPE_FPU, FL_RC_BIT_F}},
{30, &JitArmIL::Default}, //"fnmsubsx", OPTYPE_FPU, FL_RC_BIT_F}}, {30, &JitArmIL::FallBackToInterpreter}, //"fnmsubsx", OPTYPE_FPU, FL_RC_BIT_F}},
{31, &JitArmIL::Default}, //"fnmaddsx", OPTYPE_FPU, FL_RC_BIT_F}}, {31, &JitArmIL::FallBackToInterpreter}, //"fnmaddsx", OPTYPE_FPU, FL_RC_BIT_F}},
}; };
static GekkoOPTemplate table63[] = static GekkoOPTemplate table63[] =
{ {
{264, &JitArmIL::Default}, //"fabsx", OPTYPE_FPU, FL_RC_BIT_F}}, {264, &JitArmIL::FallBackToInterpreter}, //"fabsx", OPTYPE_FPU, FL_RC_BIT_F}},
{32, &JitArmIL::Default}, //"fcmpo", OPTYPE_FPU, FL_RC_BIT_F}}, {32, &JitArmIL::FallBackToInterpreter}, //"fcmpo", OPTYPE_FPU, FL_RC_BIT_F}},
{0, &JitArmIL::Default}, //"fcmpu", OPTYPE_FPU, FL_RC_BIT_F}}, {0, &JitArmIL::FallBackToInterpreter}, //"fcmpu", OPTYPE_FPU, FL_RC_BIT_F}},
{14, &JitArmIL::Default}, //"fctiwx", OPTYPE_FPU, FL_RC_BIT_F}}, {14, &JitArmIL::FallBackToInterpreter}, //"fctiwx", OPTYPE_FPU, FL_RC_BIT_F}},
{15, &JitArmIL::Default}, //"fctiwzx", OPTYPE_FPU, FL_RC_BIT_F}}, {15, &JitArmIL::FallBackToInterpreter}, //"fctiwzx", OPTYPE_FPU, FL_RC_BIT_F}},
{72, &JitArmIL::Default}, //"fmrx", OPTYPE_FPU, FL_RC_BIT_F}}, {72, &JitArmIL::FallBackToInterpreter}, //"fmrx", OPTYPE_FPU, FL_RC_BIT_F}},
{136, &JitArmIL::Default}, //"fnabsx", OPTYPE_FPU, FL_RC_BIT_F}}, {136, &JitArmIL::FallBackToInterpreter}, //"fnabsx", OPTYPE_FPU, FL_RC_BIT_F}},
{40, &JitArmIL::Default}, //"fnegx", OPTYPE_FPU, FL_RC_BIT_F}}, {40, &JitArmIL::FallBackToInterpreter}, //"fnegx", OPTYPE_FPU, FL_RC_BIT_F}},
{12, &JitArmIL::Default}, //"frspx", OPTYPE_FPU, FL_RC_BIT_F}}, {12, &JitArmIL::FallBackToInterpreter}, //"frspx", OPTYPE_FPU, FL_RC_BIT_F}},
{64, &JitArmIL::Default}, //"mcrfs", OPTYPE_SYSTEMFP, 0}}, {64, &JitArmIL::FallBackToInterpreter}, //"mcrfs", OPTYPE_SYSTEMFP, 0}},
{583, &JitArmIL::Default}, //"mffsx", OPTYPE_SYSTEMFP, 0}}, {583, &JitArmIL::FallBackToInterpreter}, //"mffsx", OPTYPE_SYSTEMFP, 0}},
{70, &JitArmIL::Default}, //"mtfsb0x", OPTYPE_SYSTEMFP, 0, 2}}, {70, &JitArmIL::FallBackToInterpreter}, //"mtfsb0x", OPTYPE_SYSTEMFP, 0, 2}},
{38, &JitArmIL::Default}, //"mtfsb1x", OPTYPE_SYSTEMFP, 0, 2}}, {38, &JitArmIL::FallBackToInterpreter}, //"mtfsb1x", OPTYPE_SYSTEMFP, 0, 2}},
{134, &JitArmIL::Default}, //"mtfsfix", OPTYPE_SYSTEMFP, 0, 2}}, {134, &JitArmIL::FallBackToInterpreter}, //"mtfsfix", OPTYPE_SYSTEMFP, 0, 2}},
{711, &JitArmIL::Default}, //"mtfsfx", OPTYPE_SYSTEMFP, 0, 2}}, {711, &JitArmIL::FallBackToInterpreter}, //"mtfsfx", OPTYPE_SYSTEMFP, 0, 2}},
}; };
static GekkoOPTemplate table63_2[] = static GekkoOPTemplate table63_2[] =
{ {
{18, &JitArmIL::Default}, //"fdivx", OPTYPE_FPU, FL_RC_BIT_F, 30}}, {18, &JitArmIL::FallBackToInterpreter}, //"fdivx", OPTYPE_FPU, FL_RC_BIT_F, 30}},
{20, &JitArmIL::Default}, //"fsubx", OPTYPE_FPU, FL_RC_BIT_F}}, {20, &JitArmIL::FallBackToInterpreter}, //"fsubx", OPTYPE_FPU, FL_RC_BIT_F}},
{21, &JitArmIL::Default}, //"faddx", OPTYPE_FPU, FL_RC_BIT_F}}, {21, &JitArmIL::FallBackToInterpreter}, //"faddx", OPTYPE_FPU, FL_RC_BIT_F}},
{22, &JitArmIL::Default}, //"fsqrtx", OPTYPE_FPU, FL_RC_BIT_F}}, {22, &JitArmIL::FallBackToInterpreter}, //"fsqrtx", OPTYPE_FPU, FL_RC_BIT_F}},
{23, &JitArmIL::Default}, //"fselx", OPTYPE_FPU, FL_RC_BIT_F}}, {23, &JitArmIL::FallBackToInterpreter}, //"fselx", OPTYPE_FPU, FL_RC_BIT_F}},
{25, &JitArmIL::Default}, //"fmulx", OPTYPE_FPU, FL_RC_BIT_F}}, {25, &JitArmIL::FallBackToInterpreter}, //"fmulx", OPTYPE_FPU, FL_RC_BIT_F}},
{26, &JitArmIL::Default}, //"frsqrtex", OPTYPE_FPU, FL_RC_BIT_F}}, {26, &JitArmIL::FallBackToInterpreter}, //"frsqrtex", OPTYPE_FPU, FL_RC_BIT_F}},
{28, &JitArmIL::Default}, //"fmsubx", OPTYPE_FPU, FL_RC_BIT_F}}, {28, &JitArmIL::FallBackToInterpreter}, //"fmsubx", OPTYPE_FPU, FL_RC_BIT_F}},
{29, &JitArmIL::Default}, //"fmaddx", OPTYPE_FPU, FL_RC_BIT_F}}, {29, &JitArmIL::FallBackToInterpreter}, //"fmaddx", OPTYPE_FPU, FL_RC_BIT_F}},
{30, &JitArmIL::Default}, //"fnmsubx", OPTYPE_FPU, FL_RC_BIT_F}}, {30, &JitArmIL::FallBackToInterpreter}, //"fnmsubx", OPTYPE_FPU, FL_RC_BIT_F}},
{31, &JitArmIL::Default}, //"fnmaddx", OPTYPE_FPU, FL_RC_BIT_F}}, {31, &JitArmIL::FallBackToInterpreter}, //"fnmaddx", OPTYPE_FPU, FL_RC_BIT_F}},
}; };

4
Source/Core/Core/PowerPC/JitCommon/JitBase.h
View file

@ -28,14 +28,14 @@
#include "Core/PowerPC/JitCommon/JitCache.h" #include "Core/PowerPC/JitCommon/JitCache.h"
// Use these to control the instruction selection // Use these to control the instruction selection
// #define INSTRUCTION_START Default(inst); return; // #define INSTRUCTION_START FallBackToInterpreter(inst); return;
// #define INSTRUCTION_START PPCTables::CountInstruction(inst); // #define INSTRUCTION_START PPCTables::CountInstruction(inst);
#define INSTRUCTION_START #define INSTRUCTION_START
#define JITDISABLE(setting) \ #define JITDISABLE(setting) \
if (Core::g_CoreStartupParameter.bJITOff || \ if (Core::g_CoreStartupParameter.bJITOff || \
Core::g_CoreStartupParameter.setting) \ Core::g_CoreStartupParameter.setting) \
{ Default(inst); return; } { FallBackToInterpreter(inst); return; }
class JitBase : public CPUCoreBase class JitBase : public CPUCoreBase
{ {

12
Source/Core/Core/PowerPC/JitILCommon/IR.cpp
View file

@ -997,7 +997,7 @@ InstLoc IRBuilder::FoldICmpCRUnsigned(InstLoc Op1, InstLoc Op2) {
return EmitBiOp(ICmpCRUnsigned, Op1, Op2); return EmitBiOp(ICmpCRUnsigned, Op1, Op2);
} }
InstLoc IRBuilder::FoldInterpreterFallback(InstLoc Op1, InstLoc Op2) { InstLoc IRBuilder::FoldFallBackToInterpreter(InstLoc Op1, InstLoc Op2) {
for (unsigned i = 0; i < 32; i++) { for (unsigned i = 0; i < 32; i++) {
GRegCache[i] = 0; GRegCache[i] = 0;
GRegCacheStore[i] = 0; GRegCacheStore[i] = 0;
@ -1012,7 +1012,7 @@ InstLoc IRBuilder::FoldInterpreterFallback(InstLoc Op1, InstLoc Op2) {
} }
CTRCache = 0; CTRCache = 0;
CTRCacheStore = 0; CTRCacheStore = 0;
return EmitBiOp(InterpreterFallback, Op1, Op2); return EmitBiOp(FallBackToInterpreter, Op1, Op2);
} }
InstLoc IRBuilder::FoldDoubleBiOp(unsigned Opcode, InstLoc Op1, InstLoc Op2) { InstLoc IRBuilder::FoldDoubleBiOp(unsigned Opcode, InstLoc Op1, InstLoc Op2) {
@ -1047,7 +1047,7 @@ InstLoc IRBuilder::FoldBiOp(unsigned Opcode, InstLoc Op1, InstLoc Op2, unsigned
return FoldICmp(Opcode, Op1, Op2); return FoldICmp(Opcode, Op1, Op2);
case ICmpCRSigned: return FoldICmpCRSigned(Op1, Op2); case ICmpCRSigned: return FoldICmpCRSigned(Op1, Op2);
case ICmpCRUnsigned: return FoldICmpCRUnsigned(Op1, Op2); case ICmpCRUnsigned: return FoldICmpCRUnsigned(Op1, Op2);
case InterpreterFallback: return FoldInterpreterFallback(Op1, Op2); case FallBackToInterpreter: return FoldFallBackToInterpreter(Op1, Op2);
case FDMul: case FDAdd: case FDSub: return FoldDoubleBiOp(Opcode, Op1, Op2); case FDMul: case FDAdd: case FDSub: return FoldDoubleBiOp(Opcode, Op1, Op2);
default: return EmitBiOp(Opcode, Op1, Op2, extra); default: return EmitBiOp(Opcode, Op1, Op2, extra);
} }
@ -1128,7 +1128,7 @@ unsigned IRBuilder::getNumberOfOperands(InstLoc I) const {
static unsigned ZeroOp[] = {LoadCR, LoadLink, LoadMSR, LoadGReg, LoadCTR, InterpreterBranch, LoadCarry, RFIExit, LoadFReg, LoadFRegDENToZero, LoadGQR, Int3, }; static unsigned ZeroOp[] = {LoadCR, LoadLink, LoadMSR, LoadGReg, LoadCTR, InterpreterBranch, LoadCarry, RFIExit, LoadFReg, LoadFRegDENToZero, LoadGQR, Int3, };
static unsigned UOp[] = {StoreLink, BranchUncond, StoreCR, StoreMSR, StoreFPRF, StoreGReg, StoreCTR, Load8, Load16, Load32, SExt16, SExt8, Cntlzw, Not, StoreCarry, SystemCall, ShortIdleLoop, LoadSingle, LoadDouble, LoadPaired, StoreFReg, DupSingleToMReg, DupSingleToPacked, ExpandPackedToMReg, CompactMRegToPacked, FSNeg, FSRSqrt, FDNeg, FPDup0, FPDup1, FPNeg, DoubleToSingle, StoreGQR, StoreSRR, }; static unsigned UOp[] = {StoreLink, BranchUncond, StoreCR, StoreMSR, StoreFPRF, StoreGReg, StoreCTR, Load8, Load16, Load32, SExt16, SExt8, Cntlzw, Not, StoreCarry, SystemCall, ShortIdleLoop, LoadSingle, LoadDouble, LoadPaired, StoreFReg, DupSingleToMReg, DupSingleToPacked, ExpandPackedToMReg, CompactMRegToPacked, FSNeg, FSRSqrt, FDNeg, FPDup0, FPDup1, FPNeg, DoubleToSingle, StoreGQR, StoreSRR, };
static unsigned BiOp[] = {BranchCond, IdleBranch, And, Xor, Sub, Or, Add, Mul, Rol, Shl, Shrl, Sarl, ICmpEq, ICmpNe, ICmpUgt, ICmpUlt, ICmpSgt, ICmpSlt, ICmpSge, ICmpSle, Store8, Store16, Store32, ICmpCRSigned, ICmpCRUnsigned, InterpreterFallback, StoreSingle, StoreDouble, StorePaired, InsertDoubleInMReg, FSMul, FSAdd, FSSub, FDMul, FDAdd, FDSub, FPAdd, FPMul, FPSub, FPMerge00, FPMerge01, FPMerge10, FPMerge11, FDCmpCR, }; static unsigned BiOp[] = {BranchCond, IdleBranch, And, Xor, Sub, Or, Add, Mul, Rol, Shl, Shrl, Sarl, ICmpEq, ICmpNe, ICmpUgt, ICmpUlt, ICmpSgt, ICmpSlt, ICmpSge, ICmpSle, Store8, Store16, Store32, ICmpCRSigned, ICmpCRUnsigned, FallBackToInterpreter, StoreSingle, StoreDouble, StorePaired, InsertDoubleInMReg, FSMul, FSAdd, FSSub, FDMul, FDAdd, FDSub, FPAdd, FPMul, FPSub, FPMerge00, FPMerge01, FPMerge10, FPMerge11, FDCmpCR, };
for (auto& op : ZeroOp) { for (auto& op : ZeroOp) {
numberOfOperands[op] = 0; numberOfOperands[op] = 0;
} }
@ -1235,7 +1235,7 @@ static const std::string opcodeNames[] = {
"LoadMSR", "LoadGQR", "SExt8", "SExt16", "BSwap32", "BSwap16", "Cntlzw", "LoadMSR", "LoadGQR", "SExt8", "SExt16", "BSwap32", "BSwap16", "Cntlzw",
"Not", "Load8", "Load16", "Load32", "BranchUncond", "StoreGReg", "Not", "Load8", "Load16", "Load32", "BranchUncond", "StoreGReg",
"StoreCR", "StoreLink", "StoreCarry", "StoreCTR", "StoreMSR", "StoreFPRF", "StoreCR", "StoreLink", "StoreCarry", "StoreCTR", "StoreMSR", "StoreFPRF",
"StoreGQR", "StoreSRR", "InterpreterFallback", "Add", "Mul", "And", "Or", "StoreGQR", "StoreSRR", "FallBackToInterpreter", "Add", "Mul", "And", "Or",
"Xor", "MulHighUnsigned", "Sub", "Shl", "Shrl", "Sarl", "Rol", "Xor", "MulHighUnsigned", "Sub", "Shl", "Shrl", "Sarl", "Rol",
"ICmpCRSigned", "ICmpCRUnsigned", "ICmpEq", "ICmpNe", "ICmpUgt", "ICmpCRSigned", "ICmpCRUnsigned", "ICmpEq", "ICmpNe", "ICmpUgt",
"ICmpUlt", "ICmpUge", "ICmpUle", "ICmpSgt", "ICmpSlt", "ICmpSge", "ICmpUlt", "ICmpUge", "ICmpUle", "ICmpSgt", "ICmpSlt", "ICmpSge",
@ -1253,7 +1253,7 @@ static const std::string opcodeNames[] = {
"Tramp", "BlockStart", "BlockEnd", "Int3", "Tramp", "BlockStart", "BlockEnd", "Int3",
}; };
static const unsigned alwaysUsedList[] = { static const unsigned alwaysUsedList[] = {
InterpreterFallback, StoreGReg, StoreCR, StoreLink, StoreCTR, StoreMSR, FallBackToInterpreter, StoreGReg, StoreCR, StoreLink, StoreCTR, StoreMSR,
StoreGQR, StoreSRR, StoreCarry, StoreFPRF, Load8, Load16, Load32, Store8, StoreGQR, StoreSRR, StoreCarry, StoreFPRF, Load8, Load16, Load32, Store8,
Store16, Store32, StoreSingle, StoreDouble, StorePaired, StoreFReg, FDCmpCR, Store16, Store32, StoreSingle, StoreDouble, StorePaired, StoreFReg, FDCmpCR,
BlockStart, BlockEnd, IdleBranch, BranchCond, BranchUncond, ShortIdleLoop, BlockStart, BlockEnd, IdleBranch, BranchCond, BranchUncond, ShortIdleLoop,

8
Source/Core/Core/PowerPC/JitILCommon/IR.h
View file

@ -46,7 +46,7 @@ enum Opcode {
StoreGQR, StoreGQR,
StoreSRR, StoreSRR,
// Arbitrary interpreter instruction // Arbitrary interpreter instruction
InterpreterFallback, FallBackToInterpreter,
// Binary operators // Binary operators
// Commutative integer operators // Commutative integer operators
@ -227,7 +227,7 @@ private:
InstLoc FoldICmpCRUnsigned(InstLoc Op1, InstLoc Op2); InstLoc FoldICmpCRUnsigned(InstLoc Op1, InstLoc Op2);
InstLoc FoldDoubleBiOp(unsigned Opcode, InstLoc Op1, InstLoc Op2); InstLoc FoldDoubleBiOp(unsigned Opcode, InstLoc Op1, InstLoc Op2);
InstLoc FoldInterpreterFallback(InstLoc Op1, InstLoc Op2); InstLoc FoldFallBackToInterpreter(InstLoc Op1, InstLoc Op2);
InstLoc FoldZeroOp(unsigned Opcode, unsigned extra); InstLoc FoldZeroOp(unsigned Opcode, unsigned extra);
InstLoc FoldUOp(unsigned OpCode, InstLoc Op1, InstLoc FoldUOp(unsigned OpCode, InstLoc Op1,
@ -374,8 +374,8 @@ public:
InstLoc EmitICmpCRUnsigned(InstLoc op1, InstLoc op2) { InstLoc EmitICmpCRUnsigned(InstLoc op1, InstLoc op2) {
return FoldBiOp(ICmpCRUnsigned, op1, op2); return FoldBiOp(ICmpCRUnsigned, op1, op2);
} }
InstLoc EmitInterpreterFallback(InstLoc op1, InstLoc op2) { InstLoc EmitFallBackToInterpreter(InstLoc op1, InstLoc op2) {
return FoldBiOp(InterpreterFallback, op1, op2); return FoldBiOp(FallBackToInterpreter, op1, op2);
} }
InstLoc EmitInterpreterBranch() { InstLoc EmitInterpreterBranch() {
return FoldZeroOp(InterpreterBranch, 0); return FoldZeroOp(InterpreterBranch, 0);

2
Source/Core/Core/PowerPC/JitILCommon/JitILBase.h
View file

@ -39,7 +39,7 @@ public:
// OPCODES // OPCODES
virtual void unknown_instruction(UGeckoInstruction inst) = 0; virtual void unknown_instruction(UGeckoInstruction inst) = 0;
virtual void Default(UGeckoInstruction inst) = 0; virtual void FallBackToInterpreter(UGeckoInstruction inst) = 0;
virtual void DoNothing(UGeckoInstruction inst) = 0; virtual void DoNothing(UGeckoInstruction inst) = 0;
virtual void HLEFunction(UGeckoInstruction inst) = 0; virtual void HLEFunction(UGeckoInstruction inst) = 0;

2
Source/Core/Core/PowerPC/JitILCommon/JitILBase_Branch.cpp
View file

@ -17,7 +17,7 @@
// Zelda and many more games seem to pass the Acid Test. // Zelda and many more games seem to pass the Acid Test.
//#define NORMALBRANCH_START Default(inst); ibuild.EmitInterpreterBranch(); return; //#define NORMALBRANCH_START FallBackToInterpreter(inst); ibuild.EmitInterpreterBranch(); return;
#define NORMALBRANCH_START #define NORMALBRANCH_START
void JitILBase::sc(UGeckoInstruction inst) void JitILBase::sc(UGeckoInstruction inst)

39
Source/Core/Core/PowerPC/JitILCommon/JitILBase_FloatingPoint.cpp
View file

@ -10,13 +10,19 @@ void JitILBase::fp_arith_s(UGeckoInstruction inst)
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc || (inst.SUBOP5 != 25 && inst.SUBOP5 != 20 && if (inst.Rc || (inst.SUBOP5 != 25 && inst.SUBOP5 != 20 &&
inst.SUBOP5 != 21 && inst.SUBOP5 != 26)) { inst.SUBOP5 != 21 && inst.SUBOP5 != 26))
Default(inst); return; {
FallBackToInterpreter(inst);
return;
} }
// Only the interpreter has "proper" support for (some) FP flags // Only the interpreter has "proper" support for (some) FP flags
if (inst.SUBOP5 == 25 && Core::g_CoreStartupParameter.bEnableFPRF) { if (inst.SUBOP5 == 25 && Core::g_CoreStartupParameter.bEnableFPRF)
Default(inst); return; {
FallBackToInterpreter(inst);
return;
} }
IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.FA); IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.FA);
switch (inst.SUBOP5) switch (inst.SUBOP5)
{ {
@ -52,13 +58,19 @@ void JitILBase::fmaddXX(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc) { if (inst.Rc)
Default(inst); return; {
FallBackToInterpreter(inst);
return;
} }
// Only the interpreter has "proper" support for (some) FP flags // Only the interpreter has "proper" support for (some) FP flags
if (inst.SUBOP5 == 29 && Core::g_CoreStartupParameter.bEnableFPRF) { if (inst.SUBOP5 == 29 && Core::g_CoreStartupParameter.bEnableFPRF)
Default(inst); return; {
FallBackToInterpreter(inst);
return;
} }
IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.FA); IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.FA);
val = ibuild.EmitFDMul(val, ibuild.EmitLoadFReg(inst.FC)); val = ibuild.EmitFDMul(val, ibuild.EmitLoadFReg(inst.FC));
if (inst.SUBOP5 & 1) if (inst.SUBOP5 & 1)
@ -80,9 +92,13 @@ void JitILBase::fmrx(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
if (inst.Rc) {
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.FB); IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.FB);
val = ibuild.EmitInsertDoubleInMReg(val, ibuild.EmitLoadFReg(inst.FD)); val = ibuild.EmitInsertDoubleInMReg(val, ibuild.EmitLoadFReg(inst.FD));
ibuild.EmitStoreFReg(val, inst.FD); ibuild.EmitStoreFReg(val, inst.FD);
@ -105,7 +121,8 @@ void JitILBase::fsign(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITFloatingPointOff) JITDISABLE(bJITFloatingPointOff)
Default(inst);
FallBackToInterpreter(inst);
return; return;
// TODO // TODO

6
Source/Core/Core/PowerPC/JitILCommon/JitILBase_Integer.cpp
View file

@ -78,7 +78,7 @@ void JitILBase::reg_imm(UGeckoInstruction inst)
ComputeRC(ibuild, val); ComputeRC(ibuild, val);
break; break;
default: default:
Default(inst); FallBackToInterpreter(inst);
break; break;
} }
} }
@ -303,7 +303,9 @@ void JitILBase::mulhwux(UGeckoInstruction inst)
// skipped some of the special handling in here - if we get crashes, let the interpreter handle this op // skipped some of the special handling in here - if we get crashes, let the interpreter handle this op
void JitILBase::divwux(UGeckoInstruction inst) void JitILBase::divwux(UGeckoInstruction inst)
{ {
Default(inst); return; FallBackToInterpreter(inst);
return;
#if 0 #if 0
int a = inst.RA, b = inst.RB, d = inst.RD; int a = inst.RA, b = inst.RB, d = inst.RD;
gpr.FlushLockX(EDX); gpr.FlushLockX(EDX);

96
Source/Core/Core/PowerPC/JitILCommon/JitILBase_LoadStore.cpp
View file

@ -9,10 +9,17 @@ void JitILBase::lhax(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff) JITDISABLE(bJITLoadStoreOff)
if (js.memcheck) { Default(inst); return; }
if (js.memcheck)
{
FallBackToInterpreter(inst);
return;
}
IREmitter::InstLoc addr = ibuild.EmitLoadGReg(inst.RB); IREmitter::InstLoc addr = ibuild.EmitLoadGReg(inst.RB);
if (inst.RA) if (inst.RA)
addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA)); addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
IREmitter::InstLoc val = ibuild.EmitLoad16(addr); IREmitter::InstLoc val = ibuild.EmitLoad16(addr);
val = ibuild.EmitSExt16(val); val = ibuild.EmitSExt16(val);
ibuild.EmitStoreGReg(val, inst.RD); ibuild.EmitStoreGReg(val, inst.RD);
@ -22,12 +29,19 @@ void JitILBase::lXz(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff) JITDISABLE(bJITLoadStoreOff)
if (js.memcheck) { Default(inst); return; }
if (js.memcheck)
{
FallBackToInterpreter(inst);
return;
}
IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16); IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16);
if (inst.RA) if (inst.RA)
addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA)); addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
if (inst.OPCD & 1) if (inst.OPCD & 1)
ibuild.EmitStoreGReg(addr, inst.RA); ibuild.EmitStoreGReg(addr, inst.RA);
IREmitter::InstLoc val; IREmitter::InstLoc val;
switch (inst.OPCD & ~0x1) switch (inst.OPCD & ~0x1)
{ {
@ -53,11 +67,18 @@ void JitILBase::lha(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff) JITDISABLE(bJITLoadStoreOff)
if (js.memcheck) { Default(inst); return; }
IREmitter::InstLoc addr = if (js.memcheck)
ibuild.EmitIntConst((s32)(s16)inst.SIMM_16); {
FallBackToInterpreter(inst);
return;
}
IREmitter::InstLoc addr = ibuild.EmitIntConst((s32)(s16)inst.SIMM_16);
if (inst.RA) if (inst.RA)
addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA)); addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
IREmitter::InstLoc val = ibuild.EmitLoad16(addr); IREmitter::InstLoc val = ibuild.EmitLoad16(addr);
val = ibuild.EmitSExt16(val); val = ibuild.EmitSExt16(val);
ibuild.EmitStoreGReg(val, inst.RD); ibuild.EmitStoreGReg(val, inst.RD);
@ -67,7 +88,13 @@ void JitILBase::lXzx(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff) JITDISABLE(bJITLoadStoreOff)
if (js.memcheck) { Default(inst); return; }
if (js.memcheck)
{
FallBackToInterpreter(inst);
return;
}
IREmitter::InstLoc addr = ibuild.EmitLoadGReg(inst.RB); IREmitter::InstLoc addr = ibuild.EmitLoadGReg(inst.RB);
if (inst.RA) if (inst.RA)
@ -99,14 +126,16 @@ void JitILBase::dcbst(UGeckoInstruction inst)
// dcbt = 0x7c00022c // dcbt = 0x7c00022c
if ((Memory::ReadUnchecked_U32(js.compilerPC - 4) & 0x7c00022c) != 0x7c00022c) if ((Memory::ReadUnchecked_U32(js.compilerPC - 4) & 0x7c00022c) != 0x7c00022c)
{ {
Default(inst); return; FallBackToInterpreter(inst);
return;
} }
} }
// Zero cache line. // Zero cache line.
void JitILBase::dcbz(UGeckoInstruction inst) void JitILBase::dcbz(UGeckoInstruction inst)
{ {
Default(inst); return; FallBackToInterpreter(inst);
return;
// TODO! // TODO!
#if 0 #if 0
@ -133,13 +162,21 @@ void JitILBase::stX(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff) JITDISABLE(bJITLoadStoreOff)
if (js.memcheck) { Default(inst); return; }
IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16), if (js.memcheck)
value = ibuild.EmitLoadGReg(inst.RS); {
FallBackToInterpreter(inst);
return;
}
IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16);
IREmitter::InstLoc value = ibuild.EmitLoadGReg(inst.RS);
if (inst.RA) if (inst.RA)
addr = ibuild.EmitAdd(ibuild.EmitLoadGReg(inst.RA), addr); addr = ibuild.EmitAdd(ibuild.EmitLoadGReg(inst.RA), addr);
if (inst.OPCD & 1) if (inst.OPCD & 1)
ibuild.EmitStoreGReg(addr, inst.RA); ibuild.EmitStoreGReg(addr, inst.RA);
switch (inst.OPCD & ~1) switch (inst.OPCD & ~1)
{ {
case 36: ibuild.EmitStore32(value, addr); break; //stw case 36: ibuild.EmitStore32(value, addr); break; //stw
@ -153,12 +190,21 @@ void JitILBase::stXx(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff) JITDISABLE(bJITLoadStoreOff)
if (js.memcheck) { Default(inst); return; }
IREmitter::InstLoc addr = ibuild.EmitLoadGReg(inst.RB), if (js.memcheck)
value = ibuild.EmitLoadGReg(inst.RS); {
FallBackToInterpreter(inst);
return;
}
IREmitter::InstLoc addr = ibuild.EmitLoadGReg(inst.RB);
IREmitter::InstLoc value = ibuild.EmitLoadGReg(inst.RS);
addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA)); addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
if (inst.SUBOP10 & 32) if (inst.SUBOP10 & 32)
ibuild.EmitStoreGReg(addr, inst.RA); ibuild.EmitStoreGReg(addr, inst.RA);
switch (inst.SUBOP10 & ~32) switch (inst.SUBOP10 & ~32)
{ {
case 151: ibuild.EmitStore32(value, addr); break; //stw case 151: ibuild.EmitStore32(value, addr); break; //stw
@ -173,10 +219,18 @@ void JitILBase::lmw(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff) JITDISABLE(bJITLoadStoreOff)
if (js.memcheck) { Default(inst); return; }
if (js.memcheck)
{
FallBackToInterpreter(inst);
return;
}
IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16); IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16);
if (inst.RA) if (inst.RA)
addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA)); addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
for (int i = inst.RD; i < 32; i++) for (int i = inst.RD; i < 32; i++)
{ {
IREmitter::InstLoc val = ibuild.EmitLoad32(addr); IREmitter::InstLoc val = ibuild.EmitLoad32(addr);
@ -189,10 +243,18 @@ void JitILBase::stmw(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreOff) JITDISABLE(bJITLoadStoreOff)
if (js.memcheck) { Default(inst); return; }
if (js.memcheck)
{
FallBackToInterpreter(inst);
return;
}
IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16); IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16);
if (inst.RA) if (inst.RA)
addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA)); addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
for (int i = inst.RD; i < 32; i++) for (int i = inst.RD; i < 32; i++)
{ {
IREmitter::InstLoc val = ibuild.EmitLoadGReg(i); IREmitter::InstLoc val = ibuild.EmitLoadGReg(i);
@ -203,6 +265,6 @@ void JitILBase::stmw(UGeckoInstruction inst)
void JitILBase::icbi(UGeckoInstruction inst) void JitILBase::icbi(UGeckoInstruction inst)
{ {
Default(inst); FallBackToInterpreter(inst);
ibuild.EmitBranchUncond(ibuild.EmitIntConst(js.compilerPC + 4)); ibuild.EmitBranchUncond(ibuild.EmitIntConst(js.compilerPC + 4));
} }

76
Source/Core/Core/PowerPC/JitILCommon/JitILBase_LoadStoreFloating.cpp
View file

@ -13,10 +13,18 @@ void JitILBase::lfs(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreFloatingOff) JITDISABLE(bJITLoadStoreFloatingOff)
if (js.memcheck) { Default(inst); return; }
if (js.memcheck)
{
FallBackToInterpreter(inst);
return;
}
IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16), val; IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16), val;
if (inst.RA) if (inst.RA)
addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA)); addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
val = ibuild.EmitDupSingleToMReg(ibuild.EmitLoadSingle(addr)); val = ibuild.EmitDupSingleToMReg(ibuild.EmitLoadSingle(addr));
ibuild.EmitStoreFReg(val, inst.RD); ibuild.EmitStoreFReg(val, inst.RD);
return; return;
@ -27,14 +35,21 @@ void JitILBase::lfd(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreFloatingOff) JITDISABLE(bJITLoadStoreFloatingOff)
if (js.memcheck) { Default(inst); return; }
if (js.memcheck)
{
FallBackToInterpreter(inst);
return;
}
IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16), val; IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16), val;
if (inst.RA) if (inst.RA)
addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA)); addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
val = ibuild.EmitLoadFReg(inst.RD); val = ibuild.EmitLoadFReg(inst.RD);
val = ibuild.EmitInsertDoubleInMReg(ibuild.EmitLoadDouble(addr), val); val = ibuild.EmitInsertDoubleInMReg(ibuild.EmitLoadDouble(addr), val);
ibuild.EmitStoreFReg(val, inst.RD); ibuild.EmitStoreFReg(val, inst.RD);
return;
} }
@ -42,15 +57,22 @@ void JitILBase::stfd(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreFloatingOff) JITDISABLE(bJITLoadStoreFloatingOff)
if (js.memcheck) { Default(inst); return; }
IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16), if (js.memcheck)
val = ibuild.EmitLoadFReg(inst.RS); {
FallBackToInterpreter(inst);
return;
}
IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16);
IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.RS);
if (inst.RA) if (inst.RA)
addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA)); addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
if (inst.OPCD & 1) if (inst.OPCD & 1)
ibuild.EmitStoreGReg(addr, inst.RA); ibuild.EmitStoreGReg(addr, inst.RA);
ibuild.EmitStoreDouble(val, addr); ibuild.EmitStoreDouble(val, addr);
return;
} }
@ -58,16 +80,23 @@ void JitILBase::stfs(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreFloatingOff) JITDISABLE(bJITLoadStoreFloatingOff)
if (js.memcheck) { Default(inst); return; }
IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16), if (js.memcheck)
val = ibuild.EmitLoadFReg(inst.RS); {
FallBackToInterpreter(inst);
return;
}
IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_16);
IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.RS);
if (inst.RA) if (inst.RA)
addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA)); addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
if (inst.OPCD & 1) if (inst.OPCD & 1)
ibuild.EmitStoreGReg(addr, inst.RA); ibuild.EmitStoreGReg(addr, inst.RA);
val = ibuild.EmitDoubleToSingle(val); val = ibuild.EmitDoubleToSingle(val);
ibuild.EmitStoreSingle(val, addr); ibuild.EmitStoreSingle(val, addr);
return;
} }
@ -75,14 +104,21 @@ void JitILBase::stfsx(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreFloatingOff) JITDISABLE(bJITLoadStoreFloatingOff)
if (js.memcheck) { Default(inst); return; }
IREmitter::InstLoc addr = ibuild.EmitLoadGReg(inst.RB), if (js.memcheck)
val = ibuild.EmitLoadFReg(inst.RS); {
FallBackToInterpreter(inst);
return;
}
IREmitter::InstLoc addr = ibuild.EmitLoadGReg(inst.RB);
IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.RS);
if (inst.RA) if (inst.RA)
addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA)); addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
val = ibuild.EmitDoubleToSingle(val); val = ibuild.EmitDoubleToSingle(val);
ibuild.EmitStoreSingle(val, addr); ibuild.EmitStoreSingle(val, addr);
return;
} }
@ -90,10 +126,18 @@ void JitILBase::lfsx(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStoreFloatingOff) JITDISABLE(bJITLoadStoreFloatingOff)
if (js.memcheck) { Default(inst); return; }
if (js.memcheck)
{
FallBackToInterpreter(inst);
return;
}
IREmitter::InstLoc addr = ibuild.EmitLoadGReg(inst.RB), val; IREmitter::InstLoc addr = ibuild.EmitLoadGReg(inst.RB), val;
if (inst.RA) if (inst.RA)
addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA)); addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
val = ibuild.EmitDupSingleToMReg(ibuild.EmitLoadSingle(addr)); val = ibuild.EmitDupSingleToMReg(ibuild.EmitLoadSingle(addr));
ibuild.EmitStoreFReg(val, inst.RD); ibuild.EmitStoreFReg(val, inst.RD);
} }

42
Source/Core/Core/PowerPC/JitILCommon/JitILBase_LoadStorePaired.cpp
View file

@ -9,13 +9,28 @@ void JitILBase::psq_st(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStorePairedOff) JITDISABLE(bJITLoadStorePairedOff)
if (js.memcheck) { Default(inst); return; }
if (inst.W) {Default(inst); return;} if (js.memcheck)
IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_12), val; {
FallBackToInterpreter(inst);
return;
}
if (inst.W)
{
FallBackToInterpreter(inst);
return;
}
IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_12);
IREmitter::InstLoc val;
if (inst.RA) if (inst.RA)
addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA)); addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
if (inst.OPCD == 61) if (inst.OPCD == 61)
ibuild.EmitStoreGReg(addr, inst.RA); ibuild.EmitStoreGReg(addr, inst.RA);
val = ibuild.EmitLoadFReg(inst.RS); val = ibuild.EmitLoadFReg(inst.RS);
val = ibuild.EmitCompactMRegToPacked(val); val = ibuild.EmitCompactMRegToPacked(val);
ibuild.EmitStorePaired(val, addr, inst.I); ibuild.EmitStorePaired(val, addr, inst.I);
@ -25,13 +40,28 @@ void JitILBase::psq_l(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITLoadStorePairedOff) JITDISABLE(bJITLoadStorePairedOff)
if (js.memcheck) { Default(inst); return; }
if (inst.W) {Default(inst); return;} if (js.memcheck)
IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_12), val; {
FallBackToInterpreter(inst);
return;
}
if (inst.W)
{
FallBackToInterpreter(inst);
return;
}
IREmitter::InstLoc addr = ibuild.EmitIntConst(inst.SIMM_12);
IREmitter::InstLoc val;
if (inst.RA) if (inst.RA)
addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA)); addr = ibuild.EmitAdd(addr, ibuild.EmitLoadGReg(inst.RA));
if (inst.OPCD == 57) if (inst.OPCD == 57)
ibuild.EmitStoreGReg(addr, inst.RA); ibuild.EmitStoreGReg(addr, inst.RA);
val = ibuild.EmitLoadPaired(addr, inst.I | (inst.W << 3)); // The lower 3 bits is for GQR index. The next 1 bit is for inst.W val = ibuild.EmitLoadPaired(addr, inst.I | (inst.W << 3)); // The lower 3 bits is for GQR index. The next 1 bit is for inst.W
val = ibuild.EmitExpandPackedToMReg(val); val = ibuild.EmitExpandPackedToMReg(val);
ibuild.EmitStoreFReg(val, inst.RD); ibuild.EmitStoreFReg(val, inst.RD);

75
Source/Core/Core/PowerPC/JitILCommon/JitILBase_Paired.cpp
View file

@ -7,36 +7,47 @@
void JitILBase::ps_mr(UGeckoInstruction inst) void JitILBase::ps_mr(UGeckoInstruction inst)
{ {
Default(inst); return; FallBackToInterpreter(inst);
return;
} }
void JitILBase::ps_sel(UGeckoInstruction inst) void JitILBase::ps_sel(UGeckoInstruction inst)
{ {
Default(inst); return; FallBackToInterpreter(inst);
return;
} }
void JitILBase::ps_sign(UGeckoInstruction inst) void JitILBase::ps_sign(UGeckoInstruction inst)
{ {
Default(inst); return; FallBackToInterpreter(inst);
return;
} }
void JitILBase::ps_rsqrte(UGeckoInstruction inst) void JitILBase::ps_rsqrte(UGeckoInstruction inst)
{ {
Default(inst); return; FallBackToInterpreter(inst);
return;
} }
void JitILBase::ps_arith(UGeckoInstruction inst) void JitILBase::ps_arith(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
if (inst.Rc || (inst.SUBOP5 != 21 && inst.SUBOP5 != 20 && inst.SUBOP5 != 25)) {
Default(inst); return; if (inst.Rc || (inst.SUBOP5 != 21 && inst.SUBOP5 != 20 && inst.SUBOP5 != 25))
{
FallBackToInterpreter(inst);
return;
} }
IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.FA), rhs;
IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.FA);
IREmitter::InstLoc rhs;
if (inst.SUBOP5 == 25) if (inst.SUBOP5 == 25)
rhs = ibuild.EmitCompactMRegToPacked(ibuild.EmitLoadFReg(inst.FC)); rhs = ibuild.EmitCompactMRegToPacked(ibuild.EmitLoadFReg(inst.FC));
else else
rhs = ibuild.EmitCompactMRegToPacked(ibuild.EmitLoadFReg(inst.FB)); rhs = ibuild.EmitCompactMRegToPacked(ibuild.EmitLoadFReg(inst.FB));
val = ibuild.EmitCompactMRegToPacked(val); val = ibuild.EmitCompactMRegToPacked(val);
switch (inst.SUBOP5) switch (inst.SUBOP5)
@ -50,6 +61,7 @@ void JitILBase::ps_arith(UGeckoInstruction inst)
case 25: case 25:
val = ibuild.EmitFPMul(val, rhs); val = ibuild.EmitFPMul(val, rhs);
} }
val = ibuild.EmitExpandPackedToMReg(val); val = ibuild.EmitExpandPackedToMReg(val);
ibuild.EmitStoreFReg(val, inst.FD); ibuild.EmitStoreFReg(val, inst.FD);
} }
@ -59,13 +71,21 @@ void JitILBase::ps_sum(UGeckoInstruction inst)
// TODO: This operation strikes me as a bit strange... // TODO: This operation strikes me as a bit strange...
// perhaps we can optimize it depending on the users? // perhaps we can optimize it depending on the users?
// TODO: ps_sum breaks Sonic Colours (black screen) // TODO: ps_sum breaks Sonic Colours (black screen)
Default(inst); return; FallBackToInterpreter(inst);
return;
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
if (inst.Rc || inst.SUBOP5 != 10) {
Default(inst); return; if (inst.Rc || inst.SUBOP5 != 10)
{
FallBackToInterpreter(inst);
return;
} }
IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.FA), temp;
IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.FA);
IREmitter::InstLoc temp;
val = ibuild.EmitCompactMRegToPacked(val); val = ibuild.EmitCompactMRegToPacked(val);
val = ibuild.EmitFPDup0(val); val = ibuild.EmitFPDup0(val);
temp = ibuild.EmitCompactMRegToPacked(ibuild.EmitLoadFReg(inst.FB)); temp = ibuild.EmitCompactMRegToPacked(ibuild.EmitLoadFReg(inst.FB));
@ -81,11 +101,15 @@ void JitILBase::ps_muls(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
if (inst.Rc) {
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.FA),
rhs = ibuild.EmitLoadFReg(inst.FC); IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.FA);
IREmitter::InstLoc rhs = ibuild.EmitLoadFReg(inst.FC);
val = ibuild.EmitCompactMRegToPacked(val); val = ibuild.EmitCompactMRegToPacked(val);
rhs = ibuild.EmitCompactMRegToPacked(rhs); rhs = ibuild.EmitCompactMRegToPacked(rhs);
@ -106,12 +130,15 @@ void JitILBase::ps_mergeXX(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
if (inst.Rc) {
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
IREmitter::InstLoc val = ibuild.EmitCompactMRegToPacked(ibuild.EmitLoadFReg(inst.FA)), IREmitter::InstLoc val = ibuild.EmitCompactMRegToPacked(ibuild.EmitLoadFReg(inst.FA));
rhs = ibuild.EmitCompactMRegToPacked(ibuild.EmitLoadFReg(inst.FB)); IREmitter::InstLoc rhs = ibuild.EmitCompactMRegToPacked(ibuild.EmitLoadFReg(inst.FB));
switch (inst.SUBOP10) switch (inst.SUBOP10)
{ {
@ -130,6 +157,7 @@ void JitILBase::ps_mergeXX(UGeckoInstruction inst)
default: default:
_assert_msg_(DYNA_REC, 0, "ps_merge - invalid op"); _assert_msg_(DYNA_REC, 0, "ps_merge - invalid op");
} }
val = ibuild.EmitExpandPackedToMReg(val); val = ibuild.EmitExpandPackedToMReg(val);
ibuild.EmitStoreFReg(val, inst.FD); ibuild.EmitStoreFReg(val, inst.FD);
} }
@ -139,12 +167,16 @@ void JitILBase::ps_maddXX(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITPairedOff) JITDISABLE(bJITPairedOff)
if (inst.Rc) {
Default(inst); return; if (inst.Rc)
{
FallBackToInterpreter(inst);
return;
} }
IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.FA), op2, op3; IREmitter::InstLoc val = ibuild.EmitLoadFReg(inst.FA), op2, op3;
val = ibuild.EmitCompactMRegToPacked(val); val = ibuild.EmitCompactMRegToPacked(val);
switch (inst.SUBOP5) switch (inst.SUBOP5)
{ {
case 14: {//madds0 case 14: {//madds0
@ -194,6 +226,7 @@ void JitILBase::ps_maddXX(UGeckoInstruction inst)
break; break;
} }
} }
val = ibuild.EmitExpandPackedToMReg(val); val = ibuild.EmitExpandPackedToMReg(val);
ibuild.EmitStoreFReg(val, inst.FD); ibuild.EmitStoreFReg(val, inst.FD);
} }

16
Source/Core/Core/PowerPC/JitILCommon/JitILBase_SystemRegisters.cpp
View file

@ -9,12 +9,14 @@
void JitILBase::mtspr(UGeckoInstruction inst) void JitILBase::mtspr(UGeckoInstruction inst)
{ {
INSTRUCTION_START INSTRUCTION_START
JITDISABLE(bJITSystemRegistersOff) JITDISABLE(bJITSystemRegistersOff)
u32 iIndex = (inst.SPRU << 5) | (inst.SPRL & 0x1F); u32 iIndex = (inst.SPRU << 5) | (inst.SPRL & 0x1F);
switch(iIndex) {
switch (iIndex)
{
case SPR_TL: case SPR_TL:
case SPR_TU: case SPR_TU:
Default(inst); FallBackToInterpreter(inst);
return; return;
case SPR_LR: case SPR_LR:
ibuild.EmitStoreLink(ibuild.EmitLoadGReg(inst.RD)); ibuild.EmitStoreLink(ibuild.EmitLoadGReg(inst.RD));
@ -37,7 +39,7 @@ void JitILBase::mtspr(UGeckoInstruction inst)
ibuild.EmitStoreSRR(ibuild.EmitLoadGReg(inst.RD), iIndex - SPR_SRR0); ibuild.EmitStoreSRR(ibuild.EmitLoadGReg(inst.RD), iIndex - SPR_SRR0);
return; return;
default: default:
Default(inst); FallBackToInterpreter(inst);
return; return;
} }
} }
@ -51,7 +53,7 @@ void JitILBase::mfspr(UGeckoInstruction inst)
{ {
case SPR_TL: case SPR_TL:
case SPR_TU: case SPR_TU:
Default(inst); FallBackToInterpreter(inst);
return; return;
case SPR_LR: case SPR_LR:
ibuild.EmitStoreGReg(ibuild.EmitLoadLink(), inst.RD); ibuild.EmitStoreGReg(ibuild.EmitLoadLink(), inst.RD);
@ -70,7 +72,7 @@ void JitILBase::mfspr(UGeckoInstruction inst)
ibuild.EmitStoreGReg(ibuild.EmitLoadGQR(iIndex - SPR_GQR0), inst.RD); ibuild.EmitStoreGReg(ibuild.EmitLoadGQR(iIndex - SPR_GQR0), inst.RD);
return; return;
default: default:
Default(inst); FallBackToInterpreter(inst);
return; return;
} }
} }