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DSPLLE: Update sr bit enum

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Pokechu22 2023-01-21 22:36:45 -08:00
commit e7daeeac09
1 changed files with 28 additions and 14 deletions
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42
Source/Core/Core/DSP/DSPCore.h
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@ -203,21 +203,35 @@ enum : u16
SR_OVERFLOW = 0x0002, SR_OVERFLOW = 0x0002,
SR_ARITH_ZERO = 0x0004, SR_ARITH_ZERO = 0x0004,
SR_SIGN = 0x0008, SR_SIGN = 0x0008,
SR_OVER_S32 = 0x0010, // Set when there was mod/tst/cmp on accu and result is over s32 // Set when there was mod/tst/cmp on accu and result is over s32, i.e. the value can't fit in a
SR_TOP2BITS = 0x0020, // If the upper (ac?.m/ax?.h) 2 bits are equal // s32 (the value doesn't match the sign extension from 32 bits to 40 bits, and saturation would
// occur on a store if enabled).
SR_OVER_S32 = 0x0010,
// If the upper (ac?.m/ax?.h) 2 bits are equal
SR_TOP2BITS = 0x0020,
// Used by ANDF/ANDCF (and also SBSET #0)
SR_LOGIC_ZERO = 0x0040, SR_LOGIC_ZERO = 0x0040,
SR_OVERFLOW_STICKY = // Set at the same time as 0x2 (under same conditions) - but not cleared the same. SBSET #1.
0x0080, // Set at the same time as 0x2 (under same conditions) - but not cleared the same SR_OVERFLOW_STICKY = 0x0080,
SR_100 = 0x0100, // Unknown, always reads back as 0 // Unknown, always reads back as 0
SR_INT_ENABLE = 0x0200, // Not 100% sure but duddie says so. This should replace the hack, if so. SR_100 = 0x0100,
SR_400 = 0x0400, // Unknown // Must be set to receive exceptions other than the external interrupt. Disabled exceptions are
SR_EXT_INT_ENABLE = 0x0800, // Appears in zelda - seems to disable external interrupts // lost (not queued). SBSET #3.
SR_1000 = 0x1000, // Unknown SR_INT_ENABLE = 0x0200,
SR_MUL_MODIFY = 0x2000, // 1 = normal. 0 = x2 (M0, M2) (Free mul by 2) // Unknown
SR_40_MODE_BIT = 0x4000, // 0 = "16", 1 = "40" (SET16, SET40) Controls sign extension when SR_400 = 0x0400,
// loading mid accums and data saturation for stores from mid accums. // Appears in zelda uCode - must be set to enable external interrupts. SBSET #5.
SR_MUL_UNSIGNED = 0x8000, // 0 = normal. 1 = unsigned (CLR15, SET15) If set, treats ax?.l as SR_EXT_INT_ENABLE = 0x0800,
// unsigned (MULX family only). // Also enables external interrupts, and automatically cleared after any exception (unlike the
// other one). SBSET #6.
SR_EXT_INT_ENABLE_2 = 0x1000,
// 1 = normal. 0 = x2 (M0, M2) (Free mul by 2)
SR_MUL_MODIFY = 0x2000,
// 0 = "16", 1 = "40" (SET16, SET40). Controls sign extension when loading mid accums and data
// saturation for stores from mid accums.
SR_40_MODE_BIT = 0x4000,
// 0 = normal. 1 = unsigned (CLR15, SET15). If set, treats ax?.l as unsigned (MULX family only).
SR_MUL_UNSIGNED = 0x8000,
// This should be the bits affected by CMP. Does not include logic zero. // This should be the bits affected by CMP. Does not include logic zero.
SR_CMP_MASK = 0x3f SR_CMP_MASK = 0x3f