mirror of
https://github.com/dolphin-emu/dolphin.git
synced 2025-08-03 06:39:33 +00:00
Initial test regarding clearing
This commit is contained in:
parent
164e0fe54e
commit
e7de36489a
2 changed files with 5 additions and 3 deletions
|
@ -454,6 +454,7 @@ void handle_dsp_mail(void)
|
||||||
else if (mail == 0x88885370)
|
else if (mail == 0x88885370)
|
||||||
{
|
{
|
||||||
real_dsp.SetInterrupt(false);
|
real_dsp.SetInterrupt(false);
|
||||||
|
CON_PrintRow(4, 25, "Test %d", real_dsp.CheckInterrupt());
|
||||||
//real_dsp.SendMailTo(real_dsp.CheckInterrupt() ? 0x99995372 : 0x99995370);
|
//real_dsp.SendMailTo(real_dsp.CheckInterrupt() ? 0x99995372 : 0x99995370);
|
||||||
//while (real_dsp.CheckMailTo())
|
//while (real_dsp.CheckMailTo())
|
||||||
// ;
|
// ;
|
||||||
|
|
|
@ -30,10 +30,11 @@ test_main:
|
||||||
; We store a copy of $SR in $AR0.
|
; We store a copy of $SR in $AR0.
|
||||||
MRR $AR0, $SR
|
MRR $AR0, $SR
|
||||||
; $IX0 is set to SR_100, so we can add it to $AR0 repeatedly to cycle through $SR bits.
|
; $IX0 is set to SR_100, so we can add it to $AR0 repeatedly to cycle through $SR bits.
|
||||||
LRI $IX0, #0x0100
|
|
||||||
; Subtract $IX0 from $AR0, so that we can add it the first time to get $SR
|
; Subtract $IX0 from $AR0, so that we can add it the first time to get $SR
|
||||||
; (and have $AR0 always match $SR instead of overflowing)
|
; (and have $AR0 always match $SR instead of overflowing)
|
||||||
SUBARN $AR0
|
LRI $IX0, #0x2000
|
||||||
|
ADDARN $AR0, $IX0
|
||||||
|
LRI $IX0, #0x0100
|
||||||
|
|
||||||
LRIS $AX0.H, #1
|
LRIS $AX0.H, #1
|
||||||
CALL send_back
|
CALL send_back
|
||||||
|
@ -41,7 +42,7 @@ test_main:
|
||||||
; We're checking 5 bits in $sr, so 1 << 5 or 0x20 times.
|
; We're checking 5 bits in $sr, so 1 << 5 or 0x20 times.
|
||||||
BLOOPI #0x20, main_loop_last_ins
|
BLOOPI #0x20, main_loop_last_ins
|
||||||
CLR $ACC0
|
CLR $ACC0
|
||||||
ADDARN $AR0, $IX0
|
SUBARN $AR0
|
||||||
MRR $SR, $AR0
|
MRR $SR, $AR0
|
||||||
|
|
||||||
; Tell the CPU to set the external interrupt
|
; Tell the CPU to set the external interrupt
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue