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Arm(64)Emitter: Make some variables static
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2 changed files with 48 additions and 46 deletions
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@ -71,7 +71,7 @@ void ARM64XEmitter::FlushIcacheSection(u8* start, u8* end)
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// Exception generation
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const u32 ExcEnc[][3] = {
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static const u32 ExcEnc[][3] = {
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{0, 0, 1}, // SVC
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{0, 0, 2}, // HVC
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{0, 0, 3}, // SMC
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@ -83,13 +83,13 @@ const u32 ExcEnc[][3] = {
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};
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// Arithmetic generation
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const u32 ArithEnc[] = {
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static const u32 ArithEnc[] = {
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0x058, // ADD
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0x258, // SUB
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};
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// Conditional Select
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const u32 CondSelectEnc[][2] = {
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static const u32 CondSelectEnc[][2] = {
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{0, 0}, // CSEL
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{0, 1}, // CSINC
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{1, 0}, // CSINV
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@ -97,7 +97,7 @@ const u32 CondSelectEnc[][2] = {
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};
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// Data-Processing (1 source)
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const u32 Data1SrcEnc[][2] = {
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static const u32 Data1SrcEnc[][2] = {
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{0, 0}, // RBIT
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{0, 1}, // REV16
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{0, 2}, // REV32
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@ -107,7 +107,7 @@ const u32 Data1SrcEnc[][2] = {
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};
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// Data-Processing (2 source)
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const u32 Data2SrcEnc[] = {
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static const u32 Data2SrcEnc[] = {
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0x02, // UDIV
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0x03, // SDIV
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0x08, // LSLV
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@ -125,7 +125,7 @@ const u32 Data2SrcEnc[] = {
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};
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// Data-Processing (3 source)
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const u32 Data3SrcEnc[][2] = {
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static const u32 Data3SrcEnc[][2] = {
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{0, 0}, // MADD
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{0, 1}, // MSUB
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{1, 0}, // SMADDL (64Bit Only)
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@ -137,7 +137,7 @@ const u32 Data3SrcEnc[][2] = {
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};
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// Logical (shifted register)
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const u32 LogicalEnc[][2] = {
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static const u32 LogicalEnc[][2] = {
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{0, 0}, // AND
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{0, 1}, // BIC
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{1, 0}, // OOR
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@ -149,7 +149,7 @@ const u32 LogicalEnc[][2] = {
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};
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// Load/Store Exclusive
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u32 LoadStoreExcEnc[][5] = {
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static u32 LoadStoreExcEnc[][5] = {
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{0, 0, 0, 0, 0}, // STXRB
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{0, 0, 0, 0, 1}, // STLXRB
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{0, 0, 1, 0, 0}, // LDXRB
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