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Core/DSPCore: Consolidation of register accesses(except for the four hw
stacks), addition of a register cache(currently accumulators on 64bit only). It feels a bit slower, but the numbers are about the same. Caching accumulators doesn't change speed either. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6848 8ced0084-cf51-0410-be5f-012b33b47a6e
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17 changed files with 1196 additions and 882 deletions
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@ -195,16 +195,16 @@ inline u32 PtrOffset(void* ptr, void* base) {
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_assert_msg_(DYNA_REC, 0, "pointer offset out of range");
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return 0;
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}
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return distance;
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return (u32)distance;
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#else
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return (u32)ptr-(u32)base;
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#endif
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}
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//usage: int a[]; ARRAY_OFFSET(a,10)
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#define ARRAY_OFFSET(array,index) ((u64)&(array)[index]-(u64)&(array)[0])
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#define ARRAY_OFFSET(array,index) ((u32)((u64)&(array)[index]-(u64)&(array)[0]))
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//usage: struct {int e;} s; STRUCT_OFFSET(s,e)
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#define STRUCT_OFFSET(str,elem) ((u64)&(str).elem-(u64)&(str))
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#define STRUCT_OFFSET(str,elem) ((u32)((u64)&(str).elem-(u64)&(str)))
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struct FixupBranch
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{
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