mirror of
https://github.com/dolphin-emu/dolphin.git
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323 lines
8.1 KiB
C++
323 lines
8.1 KiB
C++
// Copyright 2008 Dolphin Emulator Project
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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// http://www.nvidia.com/object/General_FAQ.html#t6 !!!!!
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#include <mutex>
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#include "Common/ChunkFile.h"
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#include "Common/CommonTypes.h"
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#include "Common/Logging/Log.h"
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#include "Core/ConfigManager.h"
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#include "Core/Core.h"
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#include "Core/CoreTiming.h"
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#include "Core/HW/MMIO.h"
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#include "Core/HW/ProcessorInterface.h"
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#include "VideoCommon/BoundingBox.h"
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#include "VideoCommon/CommandProcessor.h"
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#include "VideoCommon/Fifo.h"
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#include "VideoCommon/PixelEngine.h"
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namespace PixelEngine
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{
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union UPEZConfReg
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{
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u16 Hex;
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struct
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{
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u16 ZCompEnable : 1; // Z Comparator Enable
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u16 Function : 3;
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u16 ZUpdEnable : 1;
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u16 : 11;
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};
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};
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union UPEAlphaConfReg
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{
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u16 Hex;
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struct
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{
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u16 BMMath : 1; // GX_BM_BLEND || GX_BM_SUBSTRACT
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u16 BMLogic : 1; // GX_BM_LOGIC
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u16 Dither : 1;
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u16 ColorUpdEnable : 1;
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u16 AlphaUpdEnable : 1;
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u16 DstFactor : 3;
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u16 SrcFactor : 3;
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u16 Substract : 1; // Additive mode by default
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u16 BlendOperator : 4;
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};
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};
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union UPEDstAlphaConfReg
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{
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u16 Hex;
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struct
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{
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u16 DstAlpha : 8;
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u16 Enable : 1;
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u16 : 7;
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};
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};
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union UPEAlphaModeConfReg
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{
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u16 Hex;
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struct
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{
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u16 Threshold : 8;
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u16 CompareMode : 8;
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};
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};
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// fifo Control Register
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union UPECtrlReg
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{
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struct
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{
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u16 PETokenEnable : 1;
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u16 PEFinishEnable : 1;
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u16 PEToken : 1; // write only
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u16 PEFinish : 1; // write only
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u16 : 12;
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};
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u16 Hex;
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UPECtrlReg() { Hex = 0; }
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UPECtrlReg(u16 _hex) { Hex = _hex; }
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};
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// STATE_TO_SAVE
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static UPEZConfReg m_ZConf;
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static UPEAlphaConfReg m_AlphaConf;
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static UPEDstAlphaConfReg m_DstAlphaConf;
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static UPEAlphaModeConfReg m_AlphaModeConf;
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static UPEAlphaReadReg m_AlphaRead;
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static UPECtrlReg m_Control;
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static std::mutex s_token_finish_mutex;
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static u16 s_token;
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static u16 s_token_pending;
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static bool s_token_interrupt_pending;
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static bool s_finish_interrupt_pending;
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static bool s_event_raised;
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static bool s_signal_token_interrupt;
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static bool s_signal_finish_interrupt;
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static CoreTiming::EventType* et_SetTokenFinishOnMainThread;
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enum
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{
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INT_CAUSE_PE_TOKEN = 0x200, // GP Token
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INT_CAUSE_PE_FINISH = 0x400, // GP Finished
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};
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void DoState(PointerWrap& p)
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{
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p.Do(m_ZConf);
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p.Do(m_AlphaConf);
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p.Do(m_DstAlphaConf);
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p.Do(m_AlphaModeConf);
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p.Do(m_AlphaRead);
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p.DoPOD(m_Control);
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p.Do(s_token);
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p.Do(s_token_pending);
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p.Do(s_token_interrupt_pending);
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p.Do(s_finish_interrupt_pending);
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p.Do(s_event_raised);
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p.Do(s_signal_token_interrupt);
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p.Do(s_signal_finish_interrupt);
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}
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static void UpdateInterrupts();
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static void SetTokenFinish_OnMainThread(u64 userdata, s64 cyclesLate);
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void Init()
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{
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m_Control.Hex = 0;
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m_ZConf.Hex = 0;
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m_AlphaConf.Hex = 0;
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m_DstAlphaConf.Hex = 0;
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m_AlphaModeConf.Hex = 0;
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m_AlphaRead.Hex = 0;
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s_token = 0;
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s_token_pending = 0;
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s_token_interrupt_pending = false;
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s_finish_interrupt_pending = false;
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s_event_raised = false;
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s_signal_token_interrupt = false;
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s_signal_finish_interrupt = false;
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et_SetTokenFinishOnMainThread =
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CoreTiming::RegisterEvent("SetTokenFinish", SetTokenFinish_OnMainThread);
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}
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void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
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{
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// Directly mapped registers.
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struct
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{
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u32 addr;
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u16* ptr;
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} directly_mapped_vars[] = {
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{PE_ZCONF, &m_ZConf.Hex},
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{PE_ALPHACONF, &m_AlphaConf.Hex},
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{PE_DSTALPHACONF, &m_DstAlphaConf.Hex},
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{PE_ALPHAMODE, &m_AlphaModeConf.Hex},
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{PE_ALPHAREAD, &m_AlphaRead.Hex},
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};
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for (auto& mapped_var : directly_mapped_vars)
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{
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mmio->Register(base | mapped_var.addr, MMIO::DirectRead<u16>(mapped_var.ptr),
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MMIO::DirectWrite<u16>(mapped_var.ptr));
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}
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// Performance queries registers: read only, need to call the video backend
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// to get the results.
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struct
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{
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u32 addr;
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PerfQueryType pqtype;
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} pq_regs[] = {
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{PE_PERF_ZCOMP_INPUT_ZCOMPLOC_L, PQ_ZCOMP_INPUT_ZCOMPLOC},
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{PE_PERF_ZCOMP_OUTPUT_ZCOMPLOC_L, PQ_ZCOMP_OUTPUT_ZCOMPLOC},
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{PE_PERF_ZCOMP_INPUT_L, PQ_ZCOMP_INPUT},
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{PE_PERF_ZCOMP_OUTPUT_L, PQ_ZCOMP_OUTPUT},
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{PE_PERF_BLEND_INPUT_L, PQ_BLEND_INPUT},
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{PE_PERF_EFB_COPY_CLOCKS_L, PQ_EFB_COPY_CLOCKS},
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};
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for (auto& pq_reg : pq_regs)
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{
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mmio->Register(base | pq_reg.addr, MMIO::ComplexRead<u16>([pq_reg](u32) {
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return g_video_backend->Video_GetQueryResult(pq_reg.pqtype) & 0xFFFF;
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}),
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MMIO::InvalidWrite<u16>());
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mmio->Register(base | (pq_reg.addr + 2), MMIO::ComplexRead<u16>([pq_reg](u32) {
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return g_video_backend->Video_GetQueryResult(pq_reg.pqtype) >> 16;
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}),
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MMIO::InvalidWrite<u16>());
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}
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// Control register
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mmio->Register(base | PE_CTRL_REGISTER, MMIO::DirectRead<u16>(&m_Control.Hex),
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MMIO::ComplexWrite<u16>([](u32, u16 val) {
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UPECtrlReg tmpCtrl(val);
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if (tmpCtrl.PEToken)
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s_signal_token_interrupt = false;
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if (tmpCtrl.PEFinish)
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s_signal_finish_interrupt = false;
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m_Control.PETokenEnable = tmpCtrl.PETokenEnable;
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m_Control.PEFinishEnable = tmpCtrl.PEFinishEnable;
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m_Control.PEToken = 0; // this flag is write only
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m_Control.PEFinish = 0; // this flag is write only
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DEBUG_LOG(PIXELENGINE, "(w16) CTRL_REGISTER: 0x%04x", val);
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UpdateInterrupts();
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}));
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// Token register, readonly.
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mmio->Register(base | PE_TOKEN_REG, MMIO::DirectRead<u16>(&s_token), MMIO::InvalidWrite<u16>());
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// BBOX registers, readonly and need to update a flag.
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for (int i = 0; i < 4; ++i)
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{
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mmio->Register(base | (PE_BBOX_LEFT + 2 * i), MMIO::ComplexRead<u16>([i](u32) {
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BoundingBox::active = false;
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return g_video_backend->Video_GetBoundingBox(i);
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}),
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MMIO::InvalidWrite<u16>());
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}
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}
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static void UpdateInterrupts()
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{
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// check if there is a token-interrupt
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ProcessorInterface::SetInterrupt(INT_CAUSE_PE_TOKEN,
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s_signal_token_interrupt && m_Control.PETokenEnable);
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// check if there is a finish-interrupt
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ProcessorInterface::SetInterrupt(INT_CAUSE_PE_FINISH,
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s_signal_finish_interrupt && m_Control.PEFinishEnable);
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}
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static void SetTokenFinish_OnMainThread(u64 userdata, s64 cyclesLate)
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{
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std::unique_lock<std::mutex> lk(s_token_finish_mutex);
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s_event_raised = false;
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s_token = s_token_pending;
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if (s_token_interrupt_pending)
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{
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s_token_interrupt_pending = false;
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s_signal_token_interrupt = true;
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UpdateInterrupts();
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}
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if (s_finish_interrupt_pending)
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{
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s_finish_interrupt_pending = false;
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s_signal_finish_interrupt = true;
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UpdateInterrupts();
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lk.unlock();
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Core::FrameUpdateOnCPUThread();
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}
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}
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// Raise the event handler above on the CPU thread.
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// s_token_finish_mutex must be locked.
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// THIS IS EXECUTED FROM VIDEO THREAD
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static void RaiseEvent()
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{
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if (s_event_raised)
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return;
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s_event_raised = true;
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CoreTiming::FromThread from = CoreTiming::FromThread::NON_CPU;
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if (!SConfig::GetInstance().bCPUThread || Fifo::UseDeterministicGPUThread())
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from = CoreTiming::FromThread::CPU;
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CoreTiming::ScheduleEvent(0, et_SetTokenFinishOnMainThread, 0, from);
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}
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// SetToken
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// THIS IS EXECUTED FROM VIDEO THREAD
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void SetToken(const u16 token, const bool interrupt)
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{
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DEBUG_LOG(PIXELENGINE, "VIDEO Backend raises INT_CAUSE_PE_TOKEN (btw, token: %04x)", token);
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std::lock_guard<std::mutex> lk(s_token_finish_mutex);
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s_token_pending = token;
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s_token_interrupt_pending |= interrupt;
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RaiseEvent();
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}
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// SetFinish
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// THIS IS EXECUTED FROM VIDEO THREAD (BPStructs.cpp) when a new frame has been drawn
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void SetFinish()
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{
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DEBUG_LOG(PIXELENGINE, "VIDEO Set Finish");
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std::lock_guard<std::mutex> lk(s_token_finish_mutex);
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s_finish_interrupt_pending |= true;
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RaiseEvent();
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}
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UPEAlphaReadReg GetAlphaReadMode()
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{
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return m_AlphaRead;
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}
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} // end of namespace PixelEngine
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