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bdk: display: remove malloc usage
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parent
3250b2e32a
commit
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2 changed files with 9 additions and 22 deletions
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018-2024 CTCaer
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* Copyright (c) 2018-2025 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -37,8 +37,8 @@
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extern volatile nyx_storage_t *nyx_str;
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static u32 _display_id = 0;
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static u32 _dsi_bl = -1;
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static bool _nx_aula = false;
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static u32 _dsi_bl = -1;
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static bool _nx_aula = false;
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static void _display_panel_and_hw_end(bool no_panel_deinit);
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@ -265,16 +265,9 @@ int display_dsi_vblank_read(u8 cmd, u32 len, void *data)
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void display_dsi_write(u8 cmd, u32 len, void *data)
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{
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static u8 *fifo8 = NULL;
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static u32 *fifo32 = NULL;
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u32 host_control;
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// Allocate fifo buffer.
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if (!fifo32)
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{
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fifo32 = malloc(DSI_STATUS_RX_FIFO_SIZE * 8 * sizeof(u32));
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fifo8 = (u8 *)fifo32;
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}
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u32 fifo32[DSI_STATUS_TX_FIFO_SIZE] = {0};
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u8 *fifo8 = (u8 *)fifo32;
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// Prepare data for long write.
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if (len >= 2)
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@ -319,15 +312,8 @@ void display_dsi_write(u8 cmd, u32 len, void *data)
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void display_dsi_vblank_write(u8 cmd, u32 len, void *data)
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{
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static u8 *fifo8 = NULL;
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static u32 *fifo32 = NULL;
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// Allocate fifo buffer.
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if (!fifo32)
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{
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fifo32 = malloc(DSI_STATUS_RX_FIFO_SIZE * 8 * sizeof(u32));
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fifo8 = (u8 *)fifo32;
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}
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u32 fifo32[DSI_STATUS_TX_FIFO_SIZE] = {0};
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u8 *fifo8 = (u8 *)fifo32;
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// Prepare data for long write.
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if (len >= 2)
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@ -571,7 +557,7 @@ void display_init()
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* When switching to the 16ff pad brick, the clock lane termination control
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* is separated from data lane termination. This change of the mipi cal
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* brings in a bug that the DSI pad clock termination code can't be loaded
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* in one time calibration. Trigger calibration twice.
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* in one time calibration on T210B01. Trigger calibration twice.
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*/
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reg_write_array((u32 *)MIPI_CAL_BASE, _di_mipi_pad_cal_config, ARRAY_SIZE(_di_mipi_pad_cal_config));
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for (u32 i = 0; i < 2; i++)
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@ -520,6 +520,7 @@
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#define DSI_STATUS 0x15
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#define DSI_STATUS_RX_FIFO_SIZE 0x1F
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#define DSI_STATUS_TX_FIFO_SIZE 0x20 // Actual depth is 64.
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#define DSI_INIT_SEQ_CONTROL 0x1A
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#define DSI_INIT_SEQ_DATA_0 0x1B
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