diff --git a/.gitignore b/.gitignore index f634a9b..de2d046 100755 --- a/.gitignore +++ b/.gitignore @@ -5,4 +5,6 @@ output/* loader/payload_00.h loader/payload_01.h tools/bin2c/bin2c +tools/bin2c/bin2c.exe tools/lz/lz77 +tools/lz/lz77.exe diff --git a/Makefile b/Makefile index b26a3f8..be95d5c 100755 --- a/Makefile +++ b/Makefile @@ -25,16 +25,17 @@ VPATH += $(dir $(wildcard ./$(BDKDIR)/)) $(dir $(wildcard ./$(BDKDIR)/*/)) $(dir OBJS = $(addprefix $(BUILDDIR)/$(TARGET)/, \ start.o exception_handlers.o \ main.o heap.o \ - gfx.o tui.o \ - fe_emmc_tools.o fe_info.o fe_tools.o \ + gfx.o logos.o tui.o \ + l4t.o fe_info.o fe_tools.o \ ) # Hardware. OBJS += $(addprefix $(BUILDDIR)/$(TARGET)/, \ - bpmp.o ccplex.o clock.o di.o gpio.o i2c.o irq.o mc.o sdram.o \ - pinmux.o pmc.o se.o smmu.o tsec.o uart.o \ - fuse.o kfuse.o minerva.o \ - sdmmc.o sdmmc_driver.o emummc.o nx_emmc.o nx_sd.o \ + bpmp.o ccplex.o clock.o di.o i2c.o irq.o timer.o \ + mc.o sdram.o minerva.o \ + gpio.o pinmux.o pmc.o se.o smmu.o tsec.o uart.o \ + fuse.o kfuse.o \ + sdmmc.o sdmmc_driver.o emmc.o sd.o emummc.o \ bq24193.o max17050.o max7762x.o max77620-rtc.o \ hw_init.o \ ) @@ -47,7 +48,7 @@ OBJS += $(addprefix $(BUILDDIR)/$(TARGET)/, \ # Horizon. OBJS += $(addprefix $(BUILDDIR)/$(TARGET)/, \ - hos.o hos_config.o pkg1.o pkg2.o pkg2_ini_kippatch.o fss.o secmon_exo.o \ + hos.o hos_config.o pkg1.o pkg2.o pkg3.o pkg2_ini_kippatch.o secmon_exo.o \ ) # Libraries. @@ -63,21 +64,27 @@ FFCFG_INC := '"../$(SOURCEDIR)/libs/fatfs/ffconf.h"' ################################################################################ CUSTOMDEFINES := -DIPL_LOAD_ADDR=$(IPL_LOAD_ADDR) -DBL_MAGIC=$(IPL_MAGIC) -CUSTOMDEFINES += -DBL_VER_MJ=$(BLVERSION_MAJOR) -DBL_VER_MN=$(BLVERSION_MINOR) -DBL_VER_HF=$(BLVERSION_HOTFX) -DBL_RESERVED=$(BLVERSION_RSVD) -CUSTOMDEFINES += -DNYX_VER_MJ=$(NYXVERSION_MAJOR) -DNYX_VER_MN=$(NYXVERSION_MINOR) -DNYX_VER_HF=$(NYXVERSION_HOTFX) -DNYX_RESERVED=$(NYXVERSION_RSVD) +CUSTOMDEFINES += -DBL_VER_MJ=$(BLVERSION_MAJOR) -DBL_VER_MN=$(BLVERSION_MINOR) -DBL_VER_HF=$(BLVERSION_HOTFX) -DBL_VER_RL=$(BLVERSION_REL) +CUSTOMDEFINES += -DNYX_VER_MJ=$(NYXVERSION_MAJOR) -DNYX_VER_MN=$(NYXVERSION_MINOR) -DNYX_VER_HF=$(NYXVERSION_HOTFX) -DNYX_VER_RL=$(NYXVERSION_REL) + +# BDK defines. +CUSTOMDEFINES += -DBDK_MALLOC_NO_DEFRAG -DBDK_MC_ENABLE_AHB_REDIRECT -DBDK_EMUMMC_ENABLE +CUSTOMDEFINES += -DBDK_WATCHDOG_FIQ_ENABLE -DBDK_RESTART_BL_ON_WDT CUSTOMDEFINES += -DGFX_INC=$(GFX_INC) -DFFCFG_INC=$(FFCFG_INC) #CUSTOMDEFINES += -DDEBUG # UART Logging: Max baudrate 12.5M. # DEBUG_UART_PORT - 0: UART_A, 1: UART_B, 2: UART_C. -#CUSTOMDEFINES += -DDEBUG_UART_BAUDRATE=115200 -DDEBUG_UART_INVERT=0 -DDEBUG_UART_PORT=0 +#CUSTOMDEFINES += -DDEBUG_UART_BAUDRATE=115200 -DDEBUG_UART_INVERT=0 -DDEBUG_UART_PORT=1 #TODO: Considering reinstating some of these when pointer warnings have been fixed. -WARNINGS := -Wall -Wno-array-bounds -Wno-stringop-overread -Wno-stringop-overflow +WARNINGS := -Wall -Wsign-compare -Wtype-limits -Wno-array-bounds -Wno-stringop-overread -Wno-stringop-overflow +#-fno-delete-null-pointer-checks +#-Wstack-usage=byte-size -fstack-usage -ARCH := -march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork -CFLAGS = $(ARCH) -O2 -g -nostdlib -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-inline -std=gnu11 $(WARNINGS) $(CUSTOMDEFINES) +ARCH := -march=armv4t -mtune=arm7tdmi -mthumb -mthumb-interwork $(WARNINGS) +CFLAGS = $(ARCH) -O2 -g -gdwarf-4 -nostdlib -ffunction-sections -fdata-sections -fomit-frame-pointer -fno-inline -std=gnu11 $(CUSTOMDEFINES) LDFLAGS = $(ARCH) -nostartfiles -lgcc -Wl,--nmagic,--gc-sections -Xlinker --defsym=IPL_LOAD_ADDR=$(IPL_LOAD_ADDR) MODULEDIRS := $(wildcard modules/*) @@ -94,15 +101,14 @@ TOOLS := $(TOOLSLZ) $(TOOLSB2C) all: $(TARGET).bin $(LDRDIR) @printf ICTC49 >> $(OUTPUTDIR)/$(TARGET).bin @echo "--------------------------------------" - @echo -n "Uncompr size: " + @echo "$(TARGET) size:" + @echo -n "Uncompr: " $(eval BIN_SIZE = $(shell wc -c < $(OUTPUTDIR)/$(TARGET)_unc.bin)) @echo $(BIN_SIZE)" Bytes" - @echo "Uncompr Max: 140288 Bytes + 3 KiB BSS" @if [ ${BIN_SIZE} -gt 140288 ]; then echo "\e[1;33mUncompr size exceeds limit!\e[0m"; fi - @echo -n "Payload size: " + @echo -n "Payload: " $(eval BIN_SIZE = $(shell wc -c < $(OUTPUTDIR)/$(TARGET).bin)) @echo $(BIN_SIZE)" Bytes" - @echo "Payload Max: 126296 Bytes" @if [ ${BIN_SIZE} -gt 126296 ]; then echo "\e[1;33mPayload size exceeds limit!\e[0m"; fi @echo "--------------------------------------" @@ -119,7 +125,7 @@ $(NYXDIR): $(LDRDIR): $(TARGET).bin @$(TOOLSLZ)/lz77 $(OUTPUTDIR)/$(TARGET).bin - mv $(OUTPUTDIR)/$(TARGET).bin $(OUTPUTDIR)/$(TARGET)_unc.bin + @mv $(OUTPUTDIR)/$(TARGET).bin $(OUTPUTDIR)/$(TARGET)_unc.bin @mv $(OUTPUTDIR)/$(TARGET).bin.00.lz payload_00 @mv $(OUTPUTDIR)/$(TARGET).bin.01.lz payload_01 @$(TOOLSB2C)/bin2c payload_00 > $(LDRDIR)/payload_00.h @@ -132,11 +138,11 @@ $(TOOLS): @$(MAKE) --no-print-directory -C $@ $(MAKECMDGOALS) -$(MAKEFLAGS) $(TARGET).bin: $(BUILDDIR)/$(TARGET)/$(TARGET).elf $(MODULEDIRS) $(NYXDIR) $(TOOLS) - $(OBJCOPY) -S -O binary $< $(OUTPUTDIR)/$@ + @$(OBJCOPY) -S -O binary $< $(OUTPUTDIR)/$@ $(BUILDDIR)/$(TARGET)/$(TARGET).elf: $(OBJS) @$(CC) $(LDFLAGS) -T $(SOURCEDIR)/link.ld $^ -o $@ - @echo "hekate was built with the following flags:\nCFLAGS: "$(CFLAGS)"\nLDFLAGS: "$(LDFLAGS) + @printf "$(TARGET) was built with the following flags:\nCFLAGS: $(CFLAGS)\nLDFLAGS: $(LDFLAGS)\n" $(BUILDDIR)/$(TARGET)/%.o: %.c @echo Building $@ diff --git a/README.md b/README.md index 761d0ef..6101ca1 100644 --- a/README.md +++ b/README.md @@ -50,13 +50,14 @@ Custom Graphical Nintendo Switch bootloader, firmware patcher, tools, and many m | \|__ background.bmp | Nyx - Custom background. User provided. | | \|__ icon_switch.bmp | Nyx - Default icon for CFWs. | | \|__ icon_payload.bmp | Nyx - Default icon for Payloads. | -| bootloader/sys/ | hekate and Nyx system modules folder. | -| \|__ emummc.kipm | emuMMC KIP1 module. !Important! | -| \|__ libsys_lp0.bso | LP0 (sleep mode) module. Important! | -| \|__ libsys_minerva.bso | Minerva Training Cell. Used for DRAM Frequency training. !Important! | -| \|__ nyx.bin | Nyx - hekate's GUI. !Important! | -| \|__ res.pak | Nyx resources package. !Important! | -| \|__ thk.bin | Atmosphère Tsec Hovi Keygen. !Important! | +| bootloader/sys/ | hekate and Nyx system modules folder. !Important! | +| \|__ emummc.kipm | emuMMC KIP1 module. | +| \|__ libsys_lp0.bso | LP0 (sleep mode) module. | +| \|__ libsys_minerva.bso | Minerva Training Cell. Used for DRAM Frequency training. | +| \|__ nyx.bin | Nyx - hekate's GUI. | +| \|__ res.pak | Nyx resources package. | +| \|__ thk.bin | Atmosphère Tsec Hovi Keygen. | +| \|__ /l4t/ | Folder with firmware relevant to L4T (Linux/Android). | | bootloader/screenshots/ | Folder where Nyx screenshots are saved | | bootloader/payloads/ | For the `Payloads` menu. All CFW bootloaders, tools, Linux payloads are supported. Autoboot only supported by including them into an ini. | | bootloader/libtools/ | Reserved | @@ -76,16 +77,17 @@ There are four possible type of entries. "**[ ]**": Boot entry, "**{ }**": Capti ### hekate Global Configuration keys/values (when entry is *[config]*): -| Config option | Description | -| ------------------ | ---------------------------------------------------------- | -| autoboot=0 | 0: Disable, #: Boot entry number to auto boot. | +| Config option | Description | +| ------------------ | -------------------------------------------------------------- | +| autoboot=0 | 0: Disable, #: Boot entry number to auto boot. | | autoboot_list=0 | 0: Read `autoboot` boot entry from hekate_ipl.ini, 1: Read from ini folder (ini files are ASCII ordered). | | bootwait=3 | 0: Disable (It also disables bootlogo. Having **VOL-** pressed since injection goes to menu.), #: Time to wait for **VOL-** to enter menu. Max: 20s. | +| noticker=0 | 0: Animated line is drawn during custom bootlogo, signifying time left to skip to menu. 1: Disable. | | autohosoff=1 | 0: Disable, 1: If woke up from HOS via an RTC alarm, shows logo, then powers off completely, 2: No logo, immediately powers off.| | autonogc=1 | 0: Disable, 1: Automatically applies nogc patch if unburnt fuses found and a >= 4.0.0 HOS is booted. | | bootprotect=0 | 0: Disable, 1: Protect bootloader folder from being corrupted by disallowing reading or editing in HOS. | | updater2p=0 | 0: Disable, 1: Force updates (if needed) the reboot2payload binary to be hekate. | -| backlight=100 | Screen backlight level. 0-255. | +| backlight=100 | Screen backlight level. 0-255. | ### Boot entry key/value combinations: @@ -97,21 +99,33 @@ There are four possible type of entries. "**[ ]**": Boot entry, "**{ }**": Capti | kernel={FILE path} | Replaces the kernel binary | | kip1={FILE path} | Replaces/Adds kernel initial process. Multiple can be set. | | kip1={FOLDER path}/* | Loads every .kip/.kip1 inside a folder. Compatible with single kip1 keys. | -| fss0={FILE path} | Takes an Atmosphere `package3` binary (formerly fusee-secondary.bin) and `extracts` all needed parts from it. kips, exosphere, warmboot and mesophere if enabled. | -| fss0experimental=1 | Enables loading of experimental content from a FSS0 storage | +| pkg3={FILE path} | Takes an Atmosphere `package3` binary and `extracts` all needed parts from it. kips, exosphere, warmboot and mesophere. | +| fss0={FILE path} | Same as above. !Deprecated! | +| pkg3ex=1 | Enables loading of experimental content from a PKG3/FSS0 storage | +| pkg3kip1skip={KIP name} | Skips loading a kip from `pkg3`/`fss0`. Allows multiple and `,` as separator. The name must exactly match the name in `PKG3`. | | exofatal={FILE path} | Replaces the exosphere fatal binary for Mariko | | ---------------------- | ---------------------------------------------------------- | -| kip1patch=patchname | Enables a kip1 patch. Specify with multiple lines and/or in one line with `,` as separator. If actual patch is not found, a warning will show up | +| kip1patch=patchname | Enables a kip1 patch. Allows multiple and `,` as separator. If actual patch is not found, a warning will show up. | | emupath={FOLDER path} | Forces emuMMC to use the selected one. (=emuMMC/RAW1, =emuMMC/SD00, etc). emuMMC must be created by hekate because it uses the raw_based/file_based files. | | emummcforce=1 | Forces the use of emuMMC. If emummc.ini is disabled or not found, then it causes an error. | | emummc_force_disable=1 | Disables emuMMC, if it's enabled. | -| stock=1 | Disables unneeded kernel patching and CFW kips when running stock or semi-stock. `If emuMMC is enabled, emummc_force_disabled=1` is required. emuMMC is not supported on stock. If additional KIPs are needed other than OFW's, you can define them with `kip1` key. No kip should be used that relies on Atmosphère patching, because it will hang. If `NOGC` is needed, use `kip1patch=nogc`. | +| stock=1 | OFW via hekate bootloader. Disables unneeded kernel patching and CFW kips when running stock. `If emuMMC is enabled, emummc_force_disable=1` is required. emuMMC is not supported on stock. If additional KIPs are needed other than OFW's, you can define them with `kip1` key. No kip should be used that relies on Atmosphère patching, because it will hang. If `NOGC` is needed, use `kip1patch=nogc`. | | fullsvcperm=1 | Disables SVC verification (full services permission). Doesn't work with Mesosphere as kernel. | | debugmode=1 | Enables Debug mode. Obsolete when used with exosphere as secmon. | -| atmosphere=1 | Enables Atmosphère patching. Not needed when `fss0` is used. | +| kernelprocid=1 | Enables stock kernel process id send/recv patching. Not needed when `pkg3`/`fss0` is used. | | ---------------------- | ---------------------------------------------------------- | | payload={FILE path} | Payload launching. Tools, Android/Linux, CFW bootloaders, etc. Any key above when used with that, doesn't get into account. | | ---------------------- | ---------------------------------------------------------- | +| l4t=1 | L4T Linux/Android native launching. | +| boot_prefixes={FOLDER path} | L4T bootstack directory. | +| ram_oc=0 | L4T RAM Overclocking. Check README_CONFIG.txt for more info. | +| ram_oc_vdd2=1100 | L4T RAM VDD2 Voltage. Set VDD2 (T210B01) or VDD2/VDDQ (T210) voltage. 1050-1175. | +| ram_oc_vddq=600 | L4T RAM VDDQ Voltage. Set VDDQ (T210B01). 550-650. | +| uart_port=0 | Enables logging on serial port for L4T uboot/kernel. | +| sld_type=0x31444C53 | Controls the type of seamless display support. 0x0: Disable, 0x31444C53: L4T seamless display. | +| Additional keys | Each distro supports more keys. Check README_CONFIG.txt for more info. | +| ---------------------- | ---------------------------------------------------------- | +| bootwait=3 | Overrides global bootwait from `[config]`. | | id=IDNAME | Identifies boot entry for forced boot via id. Max 7 chars. | | logopath={FILE path} | If it exists, it will load the specified bitmap. Otherwise `bootloader/bootlogo.bmp` will be used if exists | | icon={FILE path} | Force Nyx to use the icon defined here. If this is not found, it will check for a bmp named as the boot entry ([Test 2] -> `bootloader/res/Test 2.bmp`). Otherwise defaults will be used. | @@ -119,11 +133,11 @@ There are four possible type of entries. "**[ ]**": Boot entry, "**{ }**": Capti **Note1**: When using the wildcard (`/*`) with `kip1` you can still use the normal `kip1` after that to load extra single kips. -**Note2**: When using FSS0 it parses exosphere, warmboot and all core kips. You can override the first 2 by using `secmon`/`warmboot` after defining `fss0`. +**Note2**: When using PKG3/FSS0 it parses exosphere, warmboot and all core kips. You can override the first 2 by using `secmon`/`warmboot` after defining `pkg3`/`fss0`. You can define `kip1` to load an extra kip or many via the wildcard (`/*`) usage. -**Warning**: Careful when you define *fss0 core* kips when using `fss0` or the folder (when using `/*`) includes them. -This is in case the kips are incompatible between them. If compatible, you can override `fss0` kips with no issues (useful for testing with intermediate kip changes). In such cases, the `kip1` line must be under `fss0` line. +**Warning**: Careful when you override *pkg3/fss core* kips with `kip1`. +That's in case the kips are incompatible between them. If compatible, you can override `pkg3`/`fss0` kips with no issues (useful for testing with intermediate kip changes). In such cases, the `kip1` line must be **after** `pkg3`/`fss0` line. ### Boot entry key/value combinations for Exosphère: @@ -145,7 +159,7 @@ This is in case the kips are incompatible between them. If compatible, you can o ### Payload storage: -hekate has a boot storage in the binary that helps it configure it outside of BPMP enviroment: +hekate has a boot storage in the binary that helps it configure it outside of BPMP environment: | Offset / Name | Description | | ----------------------- | ----------------------------------------------------------------- | @@ -159,38 +173,45 @@ hekate has a boot storage in the binary that helps it configure it outside of BP | '0xA0' emummc_path[120] | When `Boot to emuMMC` is set, it will override the current emuMMC (boot entry or emummc.ini). Must be NULL terminated. | -If the main .ini is not found, it is created on the first hekate boot and only has the `[config]` entry. - - ### Nyx Configuration keys/values (nyx.ini): | Config option | Description | | ------------------ | ---------------------------------------------------------- | +| themebg=2d2d2d | Sets Nyx background color in HEX. EXPERIMENTAL. | | themecolor=167 | Sets Nyx color of text highlights. | +| entries5col=0 | 1: Sets Launch entry columns from 4 to 5 per line. For a total of 10 entries. | | timeoff=100 | Sets time offset in HEX. Must be in HOS epoch format | | homescreen=0 | Sets home screen. 0: Home menu, 1: All configs (merges Launch and More configs), 2: Launch, 3: More Configs. | | verification=1 | 0: Disable Backup/Restore verification, 1: Sparse (block based, fast and mostly reliable), 2: Full (sha256 based, slow and 100% reliable). | +| ------------------ | ------- The following options can only be edited in nyx.ini ------- | | umsemmcrw=0 | 1: eMMC/emuMMC UMS will be mounted as writable by default. | | jcdisable=0 | 1: Disables Joycon driver completely. | -| bpmpclock=1 | 0: Auto, 1: Faster, 2: Fast. Use 2 if Nyx hangs or some functions like UMS/Backup Verification fail. | +| jcforceright=0 | 1: Forces right joycon to be used as main mouse control. | +| bpmpclock=1 | 0: Auto, 1: Fastest, 2: Faster, 3: Fast. Use 2 or 3 if Nyx hangs or some functions like UMS/Backup Verification fail. | ``` hekate (c) 2018, naehrwert, st4rk. - (c) 2018-2021, CTCaer. + (c) 2018-2025, CTCaer. -Nyx GUI (c) 2019-2021, CTCaer. +Nyx GUI (c) 2019-2025, CTCaer. Thanks to: derrek, nedwill, plutoo, shuffle2, smea, thexyz, yellows8. Greetings to: fincs, hexkyz, SciresM, Shiny Quagsire, WinterMute. Open source and free packages used: - - FatFs R0.13a, Copyright (c) 2017, ChaN - - bcl-1.2.0, Copyright (c) 2003-2006, Marcus Geelnard - - Atmosphère (Exosphere types/panic, prc id kernel patches), - Copyright (c) 2018-2019, Atmosphère-NX - - elfload, Copyright (c) 2014 Owen Shepherd, Copyright (c) 2018 M4xw - - Littlev Graphics Library, Copyright (c) 2016 Gabor Kiss-Vamosi + - Littlev Graphics Library, + Copyright (c) 2016-2018 Gabor Kiss-Vamosi + - FatFs R0.13c, + Copyright (c) 2006-2018, ChaN + Copyright (c) 2018-2022, CTCaer + - bcl-1.2.0, + Copyright (c) 2003-2006, Marcus Geelnard + - blz, + Copyright (c) 2018, SciresM + - elfload, + Copyright (c) 2014 Owen Shepherd, + Copyright (c) 2018 M4xw ___ .-' `'. diff --git a/README_BOOTLOGO.md b/README_BOOTLOGO.md index accfe03..0a2b2bc 100644 --- a/README_BOOTLOGO.md +++ b/README_BOOTLOGO.md @@ -4,14 +4,16 @@ The bootlogo can be any size with a maximum of 720 x 1280. When it's smaller than 720 x 1280, it is automatically centered and the background takes the color of the first pixel. -When saving a landscape bootlogo, it should be rotated 90 degrees counterclockwise. +The process is to create a landscape bootlogo and then rotate it 90 degrees counterclockwise. Lastly, the supported format is 32-bit (ARGB) BMP. Classic 24-bit (RGB) BMPs are not supported for performance reasons. ## How to configure -If a boot entry specifies a custom logo path (`logopath=`), this is one will be loaded. +If a boot entry specifies a custom logo path (`logopath=`), this one will be loaded. If the above is not found or the format is not correct, it will try to load `bootloader/bootlogo.bmp`. If this is not found, the default hekate logo will be used. + +(`bootloader/bootlogo.bmp` is basically like a global bootlogo.) diff --git a/Versions.inc b/Versions.inc index 6033c27..c2278c1 100644 --- a/Versions.inc +++ b/Versions.inc @@ -1,11 +1,11 @@ # IPL Version. -BLVERSION_MAJOR := 5 -BLVERSION_MINOR := 6 -BLVERSION_HOTFX := 2 -BLVERSION_RSVD := 0 +BLVERSION_MAJOR := 6 +BLVERSION_MINOR := 3 +BLVERSION_HOTFX := 1 +BLVERSION_REL := 0 # Nyx Version. NYXVERSION_MAJOR := 1 -NYXVERSION_MINOR := 0 -NYXVERSION_HOTFX := 7 -NYXVERSION_RSVD := 0 +NYXVERSION_MINOR := 7 +NYXVERSION_HOTFX := 0 +NYXVERSION_REL := 0 diff --git a/bdk/bdk.h b/bdk/bdk.h new file mode 100644 index 0000000..1d8a05e --- /dev/null +++ b/bdk/bdk.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2022 CTCaer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef BDK_H +#define BDK_H + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#endif diff --git a/bdk/display/di.c b/bdk/display/di.c index ee4b45d..3eaf922 100644 --- a/bdk/display/di.c +++ b/bdk/display/di.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2025 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -28,6 +28,7 @@ #include #include #include +#include #include #include @@ -35,11 +36,32 @@ extern volatile nyx_storage_t *nyx_str; -static u32 _display_id = 0; -static bool nx_aula = false; +static u32 _display_id = 0; +static u32 _dsi_bl = -1; +static bool _nx_aula = false; static void _display_panel_and_hw_end(bool no_panel_deinit); +void display_enable_interrupt(u32 intr) +{ + DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) |= intr; +} + +void display_disable_interrupt(u32 intr) +{ + DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) &= ~intr; + DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = intr; +} + +void display_wait_interrupt(u32 intr) +{ + DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = intr; + + // Interrupts are masked. Poll status register for checking if fired. + while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & intr)) + ; +} + static void _display_dsi_wait(u32 timeout, u32 off, u32 mask) { u32 end = get_tmr_us() + timeout; @@ -57,9 +79,47 @@ static void _display_dsi_send_cmd(u8 cmd, u32 param, u32 wait) usleep(wait); } +static void _display_dsi_wait_vblank(bool enable) +{ + if (enable) + { + // Enable vblank interrupt. + display_enable_interrupt(DC_CMD_INT_FRAME_END_INT); + + // Use the 4th line to transmit the host cmd packet. + DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE | DSI_DSI_LINE_TYPE(4); + + // Wait for vblank before starting the transfer. + display_wait_interrupt(DC_CMD_INT_FRAME_END_INT); + } + else + { + // Wait for vblank before resetting sync points. + display_wait_interrupt(DC_CMD_INT_FRAME_END_INT); + usleep(14); + + // Reset all states of syncpt block. + DSI(_DSIREG(DSI_INCR_SYNCPT_CNTRL)) = DSI_INCR_SYNCPT_SOFT_RESET; + usleep(300); // Stabilization delay. + + // Clear syncpt block reset. + DSI(_DSIREG(DSI_INCR_SYNCPT_CNTRL)) = 0; + usleep(300); // Stabilization delay. + + // Restore video mode and host control. + DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0; + + // Disable and clear vblank interrupt. + display_disable_interrupt(DC_CMD_INT_FRAME_END_INT); + } +} + static void _display_dsi_read_rx_fifo(u32 *data) { u32 fifo_count = DSI(_DSIREG(DSI_STATUS)) & DSI_STATUS_RX_FIFO_SIZE; + if (fifo_count) + DSI(_DSIREG(DSI_TRIGGER)) = 0; + for (u32 i = 0; i < fifo_count; i++) { // Read or Drain RX FIFO. @@ -70,44 +130,26 @@ static void _display_dsi_read_rx_fifo(u32 *data) } } -int display_dsi_read(u8 cmd, u32 len, void *data, bool video_enabled) +int display_dsi_read(u8 cmd, u32 len, void *data) { int res = 0; - u32 host_control = 0; - u32 cmd_timeout = video_enabled ? 0 : 250000; u32 fifo[DSI_STATUS_RX_FIFO_SIZE] = {0}; // Drain RX FIFO. _display_dsi_read_rx_fifo(NULL); - // Save host control and enable host cmd packets during video. - if (video_enabled) - { - host_control = DSI(_DSIREG(DSI_HOST_CONTROL)); - - // Enable vblank interrupt. - DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) = DC_CMD_INT_FRAME_END_INT; - - // Use the 4th line to transmit the host cmd packet. - DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE | DSI_DSI_LINE_TYPE(4); - - // Wait for vblank before starting the transfer. - DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT; // Clear interrupt. - while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & DC_CMD_INT_FRAME_END_INT)) - ; - } - // Set reply size. _display_dsi_send_cmd(MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0); - _display_dsi_wait(cmd_timeout, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO); + _display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO); // Request register read. _display_dsi_send_cmd(MIPI_DSI_DCS_READ, cmd, 0); - _display_dsi_wait(cmd_timeout, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO); + _display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO); // Transfer bus control to device for transmitting the reply. - u32 high_speed = video_enabled ? DSI_HOST_CONTROL_HS : 0; - DSI(_DSIREG(DSI_HOST_CONTROL)) = DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_IMM_BTA | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC | high_speed; + DSI(_DSIREG(DSI_HOST_CONTROL)) |= DSI_HOST_CONTROL_IMM_BTA; + + // Wait for reply to complete. DSI_HOST_CONTROL_IMM_BTA bit acts as a DSI host read busy. _display_dsi_wait(150000, _DSIREG(DSI_HOST_CONTROL), DSI_HOST_CONTROL_IMM_BTA); // Wait a bit for the reply. @@ -146,47 +188,100 @@ int display_dsi_read(u8 cmd, u32 len, void *data, bool video_enabled) else res = 1; - // Disable host cmd packets during video and restore host control. - if (video_enabled) + return res; +} + +int display_dsi_vblank_read(u8 cmd, u32 len, void *data) +{ + int res = 0; + u32 host_control = 0; + u32 fifo[DSI_STATUS_RX_FIFO_SIZE] = {0}; + + // Drain RX FIFO. + _display_dsi_read_rx_fifo(NULL); + + // Save host control and enable host cmd packets during video. + host_control = DSI(_DSIREG(DSI_HOST_CONTROL)); + + _display_dsi_wait_vblank(true); + + // Set reply size. + _display_dsi_send_cmd(MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0); + _display_dsi_wait(0, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO); + + // Request register read. + _display_dsi_send_cmd(MIPI_DSI_DCS_READ, cmd, 0); + _display_dsi_wait(0, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST | DSI_TRIGGER_VIDEO); + + _display_dsi_wait_vblank(false); + + // Transfer bus control to device for transmitting the reply. + DSI(_DSIREG(DSI_HOST_CONTROL)) |= DSI_HOST_CONTROL_IMM_BTA; + + // Wait for reply to complete. DSI_HOST_CONTROL_IMM_BTA bit acts as a DSI host read busy. + _display_dsi_wait(150000, _DSIREG(DSI_HOST_CONTROL), DSI_HOST_CONTROL_IMM_BTA); + + // Wait a bit for the reply. + usleep(5000); + + // Read RX FIFO. + _display_dsi_read_rx_fifo(fifo); + + // Parse packet and copy over the data. + if ((fifo[0] & 0xFF) == DSI_ESCAPE_CMD) { - // Wait for vblank before reseting sync points. - DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT; // Clear interrupt. - while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & DC_CMD_INT_FRAME_END_INT)) - ; + // Act based on reply type. + switch (fifo[1] & 0xFF) + { + case GEN_LONG_RD_RES: + case DCS_LONG_RD_RES: + memcpy(data, &fifo[2], MIN((fifo[1] >> 8) & 0xFFFF, len)); + break; - // Reset all states of syncpt block. - DSI(_DSIREG(DSI_INCR_SYNCPT_CNTRL)) = DSI_INCR_SYNCPT_SOFT_RESET; - usleep(300); // Stabilization delay. + case GEN_1_BYTE_SHORT_RD_RES: + case DCS_1_BYTE_SHORT_RD_RES: + memcpy(data, &fifo[2], 1); + break; - // Clear syncpt block reset. - DSI(_DSIREG(DSI_INCR_SYNCPT_CNTRL)) = 0; - usleep(300); // Stabilization delay. + case GEN_2_BYTE_SHORT_RD_RES: + case DCS_2_BYTE_SHORT_RD_RES: + memcpy(data, &fifo[2], 2); + break; - // Restore video mode and host control. - DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0; - DSI(_DSIREG(DSI_HOST_CONTROL)) = host_control; - - // Disable and clear vblank interrupt. - DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) = 0; - DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT; + case ACK_ERROR_RES: + default: + res = 1; + break; + } } + else + res = 1; + + // Restore host control. + DSI(_DSIREG(DSI_HOST_CONTROL)) = host_control; return res; } -void display_dsi_write(u8 cmd, u32 len, void *data, bool video_enabled) +void display_dsi_write(u8 cmd, u32 len, void *data) { - u8 *fifo8; - u32 *fifo32; u32 host_control; + u32 fifo32[DSI_STATUS_TX_FIFO_SIZE] = {0}; + u8 *fifo8 = (u8 *)fifo32; - // Enable host cmd packets during video and save host control. - if (video_enabled) - DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE; + // Prepare data for long write. + if (len >= 2) + { + memcpy(&fifo8[5], data, len); + memset(&fifo8[5] + len, 0, len % sizeof(u32)); + len++; // Increase length by CMD. + } + + // Save host control. host_control = DSI(_DSIREG(DSI_HOST_CONTROL)); // Enable host transfer trigger. - DSI(_DSIREG(DSI_HOST_CONTROL)) = host_control | DSI_HOST_CONTROL_TX_TRIG_HOST; + DSI(_DSIREG(DSI_HOST_CONTROL)) = (host_control & ~(DSI_HOST_CONTROL_TX_TRIG_MASK)) | DSI_HOST_CONTROL_TX_TRIG_HOST; switch (len) { @@ -199,43 +294,36 @@ void display_dsi_write(u8 cmd, u32 len, void *data, bool video_enabled) break; default: - fifo32 = calloc(DSI_STATUS_RX_FIFO_SIZE * 8, 4); - fifo8 = (u8 *)fifo32; fifo32[0] = (len << 8) | MIPI_DSI_DCS_LONG_WRITE; fifo8[4] = cmd; - memcpy(&fifo8[5], data, len); - len += 4 + 1; // Increase length by CMD/length word and DCS CMD. - for (u32 i = 0; i < (ALIGN(len, 4) / 4); i++) + len += sizeof(u32); // Increase length by length word and DCS CMD. + for (u32 i = 0; i < (ALIGN(len, sizeof(u32)) / sizeof(u32)); i++) DSI(_DSIREG(DSI_WR_DATA)) = fifo32[i]; DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST; - free(fifo32); break; } // Wait for the write to happen. _display_dsi_wait(250000, _DSIREG(DSI_TRIGGER), DSI_TRIGGER_HOST); - // Disable host cmd packets during video and restore host control. - if (video_enabled) - DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0; + // Restore host control. DSI(_DSIREG(DSI_HOST_CONTROL)) = host_control; } void display_dsi_vblank_write(u8 cmd, u32 len, void *data) { - u8 *fifo8; - u32 *fifo32; + u32 fifo32[DSI_STATUS_TX_FIFO_SIZE] = {0}; + u8 *fifo8 = (u8 *)fifo32; - // Enable vblank interrupt. - DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) = DC_CMD_INT_FRAME_END_INT; + // Prepare data for long write. + if (len >= 2) + { + memcpy(&fifo8[5], data, len); + memset(&fifo8[5] + len, 0, len % sizeof(u32)); + len++; // Increase length by CMD. + } - // Use the 4th line to transmit the host cmd packet. - DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = DSI_CMD_PKT_VID_ENABLE | DSI_DSI_LINE_TYPE(4); - - // Wait for vblank before starting the transfer. - DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT; // Clear interrupt. - while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & DC_CMD_INT_FRAME_END_INT)) - ; + _display_dsi_wait_vblank(true); switch (len) { @@ -248,43 +336,21 @@ void display_dsi_vblank_write(u8 cmd, u32 len, void *data) break; default: - fifo32 = calloc(DSI_STATUS_RX_FIFO_SIZE * 8, 4); - fifo8 = (u8 *)fifo32; fifo32[0] = (len << 8) | MIPI_DSI_DCS_LONG_WRITE; fifo8[4] = cmd; - memcpy(&fifo8[5], data, len); - len += 4 + 1; // Increase length by CMD/length word and DCS CMD. - for (u32 i = 0; i < (ALIGN(len, 4) / 4); i++) + len += sizeof(u32); // Increase length by length word and DCS CMD. + for (u32 i = 0; i < (ALIGN(len, sizeof(u32)) / sizeof(u32)); i++) DSI(_DSIREG(DSI_WR_DATA)) = fifo32[i]; - free(fifo32); break; } - // Wait for vblank before reseting sync points. - DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT; // Clear interrupt. - while (!(DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) & DC_CMD_INT_FRAME_END_INT)) - ; - - // Reset all states of syncpt block. - DSI(_DSIREG(DSI_INCR_SYNCPT_CNTRL)) = DSI_INCR_SYNCPT_SOFT_RESET; - usleep(300); // Stabilization delay. - - // Clear syncpt block reset. - DSI(_DSIREG(DSI_INCR_SYNCPT_CNTRL)) = 0; - usleep(300); // Stabilization delay. - - // Restore video mode and host control. - DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0; - - // Disable and clear vblank interrupt. - DISPLAY_A(_DIREG(DC_CMD_INT_ENABLE)) = 0; - DISPLAY_A(_DIREG(DC_CMD_INT_STATUS)) = DC_CMD_INT_FRAME_END_INT; + _display_dsi_wait_vblank(false); } void display_init() { // Get Hardware type, as it's used in various DI functions. - nx_aula = fuse_read_hw_type() == FUSE_NX_HW_TYPE_AULA; + _nx_aula = fuse_read_hw_type() == FUSE_NX_HW_TYPE_AULA; // Check if display is already initialized. if (CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_L) & BIT(CLK_L_DISP1)) @@ -293,77 +359,52 @@ void display_init() // Get Chip ID. bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210; - // T210B01: Power on SD2 regulator for supplying LDO0. - if (!tegra_t210) - { - // Set SD2 regulator voltage. - max7762x_regulator_set_voltage(REGULATOR_SD2, 1325000); - - // Set slew rate and enable SD2 regulator. - i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD2_CFG, (1 << MAX77620_SD_SR_SHIFT) | MAX77620_SD_CFG1_FSRADE_SD_ENABLE); - max7762x_regulator_enable(REGULATOR_SD2, true); - - } - - // Enable power to display panel controller. + // Enable DSI AVDD. max7762x_regulator_set_voltage(REGULATOR_LDO0, 1200000); max7762x_regulator_enable(REGULATOR_LDO0, true); - if (tegra_t210) - max77620_config_gpio(7, MAX77620_GPIO_OUTPUT_ENABLE); // T210: LD0 -> GPIO7 -> Display panel. - // Enable Display Interface specific clocks. CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI); CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI); - - CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1); - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1); + CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_CLR) = BIT(CLK_L_DISP1); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_DISP1); CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = BIT(CLK_X_UART_FST_MIPI_CAL); - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL) = 10; // Set PLLP_OUT3 and div 6 (17MHz). + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL) = CLK_SRC_DIV(6); // Set PLLP_OUT3 and div 6 (68MHz). CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = BIT(CLK_W_DSIA_LP); - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = 10; // Set PLLP_OUT and div 6 (68MHz). + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP) = CLK_SRC_DIV(6); // Set PLLP_OUT and div 6 (68MHz). // Bring every IO rail out of deep power down. PMC(APBDEV_PMC_IO_DPD_REQ) = PMC_IO_DPD_REQ_DPD_OFF; PMC(APBDEV_PMC_IO_DPD2_REQ) = PMC_IO_DPD_REQ_DPD_OFF; - // Configure LCD pins. - PINMUX_AUX(PINMUX_AUX_NFC_EN) &= ~PINMUX_TRISTATE; // PULL_DOWN - PINMUX_AUX(PINMUX_AUX_NFC_INT) &= ~PINMUX_TRISTATE; // PULL_DOWN - PINMUX_AUX(PINMUX_AUX_LCD_RST) &= ~PINMUX_TRISTATE; // PULL_DOWN - - // Configure Backlight pins. - PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) &= ~PINMUX_TRISTATE; // PULL_DOWN | 1 - PINMUX_AUX(PINMUX_AUX_LCD_BL_EN) &= ~PINMUX_TRISTATE; // PULL_DOWN - - if (nx_aula) + // Configure LCD/BL pins. + if (!_nx_aula) { - // Configure LCD RST pin. - gpio_config(GPIO_PORT_V, GPIO_PIN_2, GPIO_MODE_GPIO); - gpio_output_enable(GPIO_PORT_V, GPIO_PIN_2, GPIO_OUTPUT_ENABLE); - } - else - { - // Set LCD +-5V pins mode and direction - gpio_config(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_MODE_GPIO); - gpio_output_enable(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_OUTPUT_ENABLE); + // Configure LCD pins. + PINMUX_AUX(PINMUX_AUX_NFC_EN) = PINMUX_PULL_DOWN; + PINMUX_AUX(PINMUX_AUX_NFC_INT) = PINMUX_PULL_DOWN; - // Enable LCD power. - gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_HIGH); // LCD +5V enable. - usleep(10000); - gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_HIGH); // LCD -5V enable. - usleep(10000); + // Configure Backlight pins. + PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = PINMUX_PULL_DOWN; + PINMUX_AUX(PINMUX_AUX_LCD_BL_EN) = PINMUX_PULL_DOWN; - // Configure Backlight PWM/EN and LCD RST pins (BL PWM, BL EN, LCD RST). - gpio_config(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_MODE_GPIO); - gpio_output_enable(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2, GPIO_OUTPUT_ENABLE); + // Enable LCD AVDD. + gpio_direction_output(GPIO_PORT_I, GPIO_PIN_0 | GPIO_PIN_1, GPIO_HIGH); + usleep(10000); // Wait minimum 4.2ms to stabilize. + + // Configure Backlight PWM/EN pins (BL PWM, BL EN). + gpio_direction_output(GPIO_PORT_V, GPIO_PIN_0 | GPIO_PIN_1, GPIO_LOW); // Enable Backlight power. gpio_write(GPIO_PORT_V, GPIO_PIN_1, GPIO_HIGH); } + // Configure LCD RST pin. + PINMUX_AUX(PINMUX_AUX_LCD_RST) = PINMUX_PULL_DOWN; + gpio_direction_output(GPIO_PORT_V, GPIO_PIN_2, GPIO_LOW); + // Power up supply regulator for display interface. MIPI_CAL(_DSIREG(MIPI_CAL_MIPI_BIAS_PAD_CFG2)) = 0; @@ -373,39 +414,25 @@ void display_init() APB_MISC(APB_MISC_GP_DSI_PAD_CONTROL) = 0; } - // Set DISP1 clock source and parent clock. - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DISP1) = 0x40000000; // PLLD_OUT. - u32 plld_div = (3 << 20) | (20 << 11) | 1; // DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 768 MHz, PLLD_OUT0 (DSI): 97.5 MHz (offset). - CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) = PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | plld_div; - - if (tegra_t210) - { - CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0x20; // PLLD_SETUP. - CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = 0x2D0AAA; // PLLD_ENABLE_CLK. - } - else - { - CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0; - CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = 0x2DFC00; // PLLD_ENABLE_CLK. - } + // Set DISP1 clock source, parent clock and DSI/PCLK to low power mode. + // T210: DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 100.0 MHz, PLLD_OUT0 (DSI-PCLK): 50.0 MHz. (PCLK: 16.66 MHz) + // T210B01: DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 97.8 MHz, PLLD_OUT0 (DSI-PCLK): 48.9 MHz. (PCLK: 16.30 MHz) + clock_enable_plld(3, 20, true, tegra_t210); // Setup Display Interface initial window configuration. - exec_cfg((u32 *)DISPLAY_A_BASE, _display_dc_setup_win_config, 94); + reg_write_array((u32 *)DISPLAY_A_BASE, _di_dc_setup_win_config, ARRAY_SIZE(_di_dc_setup_win_config)); - // Setup display communication interfaces. - exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config_part1, 8); - if (tegra_t210) - DSI(_DSIREG(DSI_INIT_SEQ_DATA_15)) = 0; - else - DSI(_DSIREG(DSI_INIT_SEQ_DATA_15_B01)) = 0; - exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config_part2, 14); + // Setup dsi init sequence packets. + reg_write_array((u32 *)DSI_BASE, _di_dsi_seq_pkt_reset_config0, ARRAY_SIZE(_di_dsi_seq_pkt_reset_config0)); + DSI(_DSIREG(tegra_t210 ? DSI_INIT_SEQ_DATA_15 : DSI_INIT_SEQ_DATA_15_B01)) = 0; + reg_write_array((u32 *)DSI_BASE, _di_dsi_seq_pkt_reset_config1, ARRAY_SIZE(_di_dsi_seq_pkt_reset_config1)); + + // Reset pad trimmers for T210B01. if (!tegra_t210) - exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config_part3_t210b01, 7); - exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config_part4, 10); - DSI(_DSIREG(DSI_PHY_TIMING_0)) = tegra_t210 ? 0x6070601 : 0x6070603; - exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config_part5, 12); - DSI(_DSIREG(DSI_PHY_TIMING_0)) = tegra_t210 ? 0x6070601 : 0x6070603; - exec_cfg((u32 *)DSI_BASE, _display_dsi_init_config_part6, 14); + reg_write_array((u32 *)DSI_BASE, _di_dsi_init_pads_t210b01, ARRAY_SIZE(_di_dsi_init_pads_t210b01)); + + // Setup init seq packet lengths, timings and power on DSI. + reg_write_array((u32 *)DSI_BASE, _di_dsi_init_config, ARRAY_SIZE(_di_dsi_init_config)); usleep(10000); // Enable LCD Reset. @@ -413,13 +440,13 @@ void display_init() usleep(60000); // Setup DSI device takeover timeout. - DSI(_DSIREG(DSI_BTA_TIMING)) = nx_aula ? 0x40103 : 0x50204; + DSI(_DSIREG(DSI_BTA_TIMING)) = _nx_aula ? 0x40103 : 0x50204; // Get Display ID. _display_id = 0xCCCCCC; for (u32 i = 0; i < 3; i++) { - if (!display_dsi_read(MIPI_DCS_GET_DISPLAY_ID, 3, &_display_id, DSI_VIDEO_DISABLED)) + if (!display_dsi_read(MIPI_DCS_GET_DISPLAY_ID, 3, &_display_id)) break; usleep(10000); @@ -435,24 +462,47 @@ void display_init() _display_id = PANEL_JDI_XXX062M; // For Aula ensure that we have a compatible panel id. - if (nx_aula && _display_id == 0xCCCC) - _display_id = PANEL_SAM_70_UNK; + if (_nx_aula && _display_id == 0xCCCC) + _display_id = PANEL_SAM_AMS699VC01; // Initialize display panel. switch (_display_id) { - case PANEL_SAM_70_UNK: + case PANEL_SAM_AMS699VC01: _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000); - _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM, 0xA0, 0); // Write 0 to 0xA0. - _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM, MIPI_DCS_SET_CONTROL_DISPLAY | (DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL << 8), 0); // Enable brightness control. + // Set color mode to basic (natural). Stock is Saturated (0x00). (Reset value is 0x20). + _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM, + MIPI_DCS_PRIV_SM_SET_COLOR_MODE | (DCS_SM_COLOR_MODE_BASIC << 8), 0); + // Enable backlight and smooth PWM. + _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM, + MIPI_DCS_SET_CONTROL_DISPLAY | ((DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL | DCS_CONTROL_DISPLAY_DIMMING_CTRL) << 8), 0); + + // Unlock Level 2 registers. + DSI(_DSIREG(DSI_WR_DATA)) = 0x539; // MIPI_DSI_DCS_LONG_WRITE: 5 bytes. + DSI(_DSIREG(DSI_WR_DATA)) = 0x5A5A5AE2; // MIPI_DCS_PRIV_SM_SET_REGS_LOCK: Unlock Level 2 registers. + DSI(_DSIREG(DSI_WR_DATA)) = 0x5A; + DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST; + + // Set registers offset and set PWM transition to 6 frames (100ms). + _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM, MIPI_DCS_PRIV_SM_SET_REG_OFFSET | (7 << 8), 0); + _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE_PARAM, MIPI_DCS_PRIV_SM_SET_ELVSS | (6 << 8), 0); + + // Relock Level 2 registers. + DSI(_DSIREG(DSI_WR_DATA)) = 0x539; // MIPI_DSI_DCS_LONG_WRITE: 5 bytes. + DSI(_DSIREG(DSI_WR_DATA)) = 0xA55A5AE2; // MIPI_DCS_PRIV_SM_SET_REGS_LOCK: Lock Level 2 registers. + DSI(_DSIREG(DSI_WR_DATA)) = 0xA5; + DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST; + + // Set backlight to 0%. DSI(_DSIREG(DSI_WR_DATA)) = 0x339; // MIPI_DSI_DCS_LONG_WRITE: 3 bytes. DSI(_DSIREG(DSI_WR_DATA)) = 0x000051; // MIPI_DCS_SET_BRIGHTNESS 0000: 0%. FF07: 100%. DSI(_DSIREG(DSI_TRIGGER)) = DSI_TRIGGER_HOST; usleep(5000); + _dsi_bl = 0; break; case PANEL_JDI_XXX062M: - exec_cfg((u32 *)DSI_BASE, _display_init_config_jdi, 43); + reg_write_array((u32 *)DSI_BASE, _di_dsi_panel_init_config_jdi, ARRAY_SIZE(_di_dsi_panel_init_config_jdi)); _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 180000); break; @@ -479,7 +529,7 @@ void display_init() case PANEL_INL_2J055IA_27A: case PANEL_AUO_A055TAN01: - case PANEL_V40_55_UNK: + case PANEL_SHP_LQ055T1SW10: default: // Allow spare part displays to work. _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_EXIT_SLEEP_MODE, 120000); break; @@ -488,29 +538,29 @@ void display_init() // Unblank display. _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_SET_DISPLAY_ON, 20000); - // Configure PLLD for DISP1. - plld_div = (1 << 20) | (24 << 11) | 1; // DIVM: 1, DIVN: 24, DIVP: 1. PLLD_OUT: 768 MHz, PLLD_OUT0 (DSI): 234 MHz (offset, it's ddr btw, so normally div2). - CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) = PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | plld_div; + // Setup final dsi clock. + // DIVM: 1, DIVN: 24, DIVP: 1. PLLD_OUT: 468.0 MHz, PLLD_OUT0 (DSI): 234.0 MHz. + clock_enable_plld(1, 24, false, tegra_t210); - if (tegra_t210) - CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0x20; // PLLD_SETUP. - else - CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = 0; - CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = 0x2DFC00; // Use new PLLD_SDM_DIN. + // Finalize DSI init packet sequence configuration. + reg_write_array((u32 *)DSI_BASE, _di_dsi_seq_pkt_video_non_burst_no_eot_config, ARRAY_SIZE(_di_dsi_seq_pkt_video_non_burst_no_eot_config)); - // Finalize DSI configuration. - DSI(_DSIREG(DSI_PAD_CONTROL_1)) = 0; - DSI(_DSIREG(DSI_PHY_TIMING_0)) = tegra_t210 ? 0x6070601 : 0x6070603; - exec_cfg((u32 *)DSI_BASE, _display_dsi_packet_config, 19); - // Set pixel clock dividers: 234 / 3 / 1 = 78 MHz (offset) for 60 Hz. + // Set 1-by-1 pixel/clock and pixel clock to 234 / 3 = 78 MHz. For 60 Hz refresh rate. DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4); // 4: div3. - exec_cfg((u32 *)DSI_BASE, _display_dsi_mode_config, 10); + + // Set DSI mode to HOST. + reg_write_array((u32 *)DSI_BASE, _di_dsi_host_mode_config, ARRAY_SIZE(_di_dsi_host_mode_config)); usleep(10000); - // Calibrate display communication pads. - u32 loops = tegra_t210 ? 1 : 2; // Find out why this is done 2 times on Mariko. - exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_pad_cal_config, 4); - for (u32 i = 0; i < loops; i++) + /* + * Calibrate display communication pads. + * When switching to the 16ff pad brick, the clock lane termination control + * is separated from data lane termination. This change of the mipi cal + * brings in a bug that the DSI pad clock termination code can't be loaded + * in one time calibration on T210B01. Trigger calibration twice. + */ + reg_write_array((u32 *)MIPI_CAL_BASE, _di_mipi_pad_cal_config, ARRAY_SIZE(_di_mipi_pad_cal_config)); + for (u32 i = 0; i < 2; i++) { // Set MIPI bias pad config. MIPI_CAL(_DSIREG(MIPI_CAL_MIPI_BIAS_PAD_CFG2)) = 0x10010; @@ -519,57 +569,77 @@ void display_init() // Set pad trimmers and set MIPI DSI cal offsets. if (tegra_t210) { - exec_cfg((u32 *)DSI_BASE, _display_dsi_pad_cal_config_t210, 4); - exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_dsi_cal_offsets_config_t210, 4); + reg_write_array((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210, ARRAY_SIZE(_di_dsi_pad_cal_config_t210)); + reg_write_array((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_prod_config_t210, ARRAY_SIZE(_di_mipi_dsi_cal_prod_config_t210)); } else { - exec_cfg((u32 *)DSI_BASE, _display_dsi_pad_cal_config_t210b01, 7); - exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_dsi_cal_offsets_config_t210b01, 4); + reg_write_array((u32 *)DSI_BASE, _di_dsi_pad_cal_config_t210b01, ARRAY_SIZE(_di_dsi_pad_cal_config_t210b01)); + reg_write_array((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_prod_config_t210b01, ARRAY_SIZE(_di_mipi_dsi_cal_prod_config_t210b01)); } - // Set the rest of MIPI cal offsets and apply calibration. - exec_cfg((u32 *)MIPI_CAL_BASE, _display_mipi_apply_dsi_cal_config, 12); + // Reset all unused MIPI cal offsets. + reg_write_array((u32 *)MIPI_CAL_BASE, _di_mipi_dsi_cal_unused_config, ARRAY_SIZE(_di_mipi_dsi_cal_unused_config)); + + // Set Prescale/filter and start calibration. + MIPI_CAL(_DSIREG(MIPI_CAL_MIPI_CAL_CTRL)) = 0x2A000001; } usleep(10000); // Enable video display controller. - exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_enable_config, 113); + reg_write_array((u32 *)DISPLAY_A_BASE, _di_dc_video_enable_config, ARRAY_SIZE(_di_dc_video_enable_config)); } void display_backlight_pwm_init() { - if (_display_id == PANEL_SAM_70_UNK) + if (_display_id == PANEL_SAM_AMS699VC01) return; + // Enable PWM clock. clock_enable_pwm(); - PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN; // Enable PWM and set it to 25KHz PFM. 29.5KHz is stock. + // Enable PWM and set it to 25KHz PFM. 29.5KHz is stock. + PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN; PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_FUNC_MASK) | 1; // Set PWM0 mode. + usleep(2); + gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight power mode. } void display_backlight(bool enable) { - gpio_write(GPIO_PORT_V, GPIO_PIN_0, enable ? GPIO_HIGH : GPIO_LOW); // Backlight PWM GPIO. + // Backlight PWM GPIO. + gpio_write(GPIO_PORT_V, GPIO_PIN_0, enable ? GPIO_HIGH : GPIO_LOW); } -void display_dsi_backlight_brightness(u32 brightness) +static void _display_dsi_backlight_brightness(u32 duty) { - u16 bl_ctrl = byte_swap_16((u16)(brightness * 8)); - display_dsi_vblank_write(MIPI_DCS_SET_BRIGHTNESS, 2, &bl_ctrl); -} - -void display_pwm_backlight_brightness(u32 brightness, u32 step_delay) -{ - u32 old_value = (PWM(PWM_CONTROLLER_PWM_CSR_0) >> 16) & 0xFF; - if (brightness == old_value) + if (_dsi_bl == duty) return; - if (old_value < brightness) + // Convert duty to candela. + u32 candela = duty * PANEL_SM_BL_CANDELA_MAX / 255; + + u16 bl_ctrl = byte_swap_16((u16)candela); + display_dsi_vblank_write(MIPI_DCS_SET_BRIGHTNESS, 2, &bl_ctrl); + + // Wait for backlight to completely turn off. 6 frames. + if (!duty) + usleep(100000); + + _dsi_bl = duty; +} + +static void _display_pwm_backlight_brightness(u32 duty, u32 step_delay) +{ + u32 old_value = (PWM(PWM_CONTROLLER_PWM_CSR_0) >> 16) & 0xFF; + if (duty == old_value) + return; + + if (old_value < duty) { - for (u32 i = old_value; i < brightness + 1; i++) + for (u32 i = old_value; i < duty + 1; i++) { PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN | (i << 16); usleep(step_delay); @@ -577,13 +647,13 @@ void display_pwm_backlight_brightness(u32 brightness, u32 step_delay) } else { - for (u32 i = old_value; i > brightness; i--) + for (u32 i = old_value; i > duty; i--) { PWM(PWM_CONTROLLER_PWM_CSR_0) = PWM_CSR_EN | (i << 16); usleep(step_delay); } } - if (!brightness) + if (!duty) PWM(PWM_CONTROLLER_PWM_CSR_0) = 0; } @@ -592,15 +662,18 @@ void display_backlight_brightness(u32 brightness, u32 step_delay) if (brightness > 255) brightness = 255; - if (_display_id != PANEL_SAM_70_UNK) - display_pwm_backlight_brightness(brightness, step_delay); + if (_display_id != PANEL_SAM_AMS699VC01) + _display_pwm_backlight_brightness(brightness, step_delay); else - display_dsi_backlight_brightness(brightness); + _display_dsi_backlight_brightness(brightness); } u32 display_get_backlight_brightness() { - return ((PWM(PWM_CONTROLLER_PWM_CSR_0) >> 16) & 0xFF); + if (_display_id != PANEL_SAM_AMS699VC01) + return ((PWM(PWM_CONTROLLER_PWM_CSR_0) >> 16) & 0xFF); + else + return _dsi_bl; } static void _display_panel_and_hw_end(bool no_panel_deinit) @@ -616,31 +689,43 @@ static void _display_panel_and_hw_end(bool no_panel_deinit) // Blank display. DSI(_DSIREG(DSI_WR_DATA)) = (MIPI_DCS_SET_DISPLAY_OFF << 8) | MIPI_DSI_DCS_SHORT_WRITE; + // Wait for 5 frames (HOST1X_CH0_SYNC_SYNCPT_9). + // Not here. Wait for 1 frame manually. + usleep(20000); + // Propagate changes to all register buffers and disable host cmd packets during video. - DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX | WRITE_MUX; + DISPLAY_A(_DIREG(DC_CMD_STATE_ACCESS)) = READ_MUX_ACTIVE | WRITE_MUX_ACTIVE; DSI(_DSIREG(DSI_VIDEO_MODE_CONTROL)) = 0; // De-initialize video controller. - exec_cfg((u32 *)DISPLAY_A_BASE, _display_video_disp_controller_disable_config, 17); - exec_cfg((u32 *)DSI_BASE, _display_dsi_timing_deinit_config, 16); + reg_write_array((u32 *)DISPLAY_A_BASE, _di_dc_video_disable_config, ARRAY_SIZE(_di_dc_video_disable_config)); - if (_display_id != PANEL_SAM_70_UNK) + // Set DISP1 clock source, parent clock and DSI/PCLK to low power mode. + // T210: DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 100.0 MHz, PLLD_OUT0 (DSI-PCLK): 50.0 MHz. (PCLK: 16.66 MHz) + // T210B01: DIVM: 1, DIVN: 20, DIVP: 3. PLLD_OUT: 97.8 MHz, PLLD_OUT0 (DSI-PCLK): 48.9 MHz. (PCLK: 16.30 MHz) + clock_enable_plld(3, 20, true, hw_get_chip_id() == GP_HIDREV_MAJOR_T210); + + // Set timings for lowpower clocks. + reg_write_array((u32 *)DSI_BASE, _di_dsi_timing_deinit_config, ARRAY_SIZE(_di_dsi_timing_deinit_config)); + + if (_display_id != PANEL_SAM_AMS699VC01) usleep(10000); // De-initialize display panel. switch (_display_id) { case PANEL_JDI_XXX062M: - exec_cfg((u32 *)DSI_BASE, _display_deinit_config_jdi, 22); + reg_write_array((u32 *)DSI_BASE, _di_dsi_panel_deinit_config_jdi, ARRAY_SIZE(_di_dsi_panel_deinit_config_jdi)); break; case PANEL_AUO_A062TAN01: - exec_cfg((u32 *)DSI_BASE, _display_deinit_config_auo, 37); + reg_write_array((u32 *)DSI_BASE, _di_dsi_panel_deinit_config_auo, ARRAY_SIZE(_di_dsi_panel_deinit_config_auo)); + usleep(5000); break; case PANEL_INL_2J055IA_27A: case PANEL_AUO_A055TAN01: - case PANEL_V40_55_UNK: + case PANEL_SHP_LQ055T1SW10: // Unlock extension cmds. DSI(_DSIREG(DSI_WR_DATA)) = 0x439; // MIPI_DSI_DCS_LONG_WRITE: 4 bytes. DSI(_DSIREG(DSI_WR_DATA)) = 0x9483FFB9; // MIPI_DCS_PRIV_SET_EXTC. (Pass: FF 83 94). @@ -653,7 +738,7 @@ static void _display_panel_and_hw_end(bool no_panel_deinit) DSI(_DSIREG(DSI_WR_DATA)) = 0x751548B1; // MIPI_DCS_PRIV_SET_POWER_CONTROL. (Not deep standby, BT5 / XDK, VRH gamma volt adj 53 / x40). else if (_display_id == PANEL_AUO_A055TAN01) DSI(_DSIREG(DSI_WR_DATA)) = 0x711148B1; // MIPI_DCS_PRIV_SET_POWER_CONTROL. (Not deep standby, BT1 / XDK, VRH gamma volt adj 49 / x40). - else // PANEL_V40_55_UNK. + else // PANEL_SHP_LQ055T1SW10. DSI(_DSIREG(DSI_WR_DATA)) = 0x731348B1; // MIPI_DCS_PRIV_SET_POWER_CONTROL. (Not deep standby, BT3 / XDK, VRH gamma volt adj 51 / x40). if (_display_id == PANEL_INL_2J055IA_27A || _display_id == PANEL_AUO_A055TAN01) { @@ -661,7 +746,7 @@ static void _display_panel_and_hw_end(bool no_panel_deinit) DSI(_DSIREG(DSI_WR_DATA)) = 0x71143209; DSI(_DSIREG(DSI_WR_DATA)) = 0x114D31; // (Unknown). } - else // PANEL_V40_55_UNK. + else // PANEL_SHP_LQ055T1SW10. { // (NVRH gamma volt adj 9, Amplifier current small / x30, FS0 freq Fosc/80 / FS1 freq Fosc/48, Enter standby / PON / VCOMG). DSI(_DSIREG(DSI_WR_DATA)) = 0x71243209; @@ -672,46 +757,44 @@ static void _display_panel_and_hw_end(bool no_panel_deinit) break; case PANEL_INL_P062CCA_AZ1: + case PANEL_SAM_AMS699VC01: default: break; } // Blank - powerdown. _display_dsi_send_cmd(MIPI_DSI_DCS_SHORT_WRITE, MIPI_DCS_ENTER_SLEEP_MODE, - (_display_id == PANEL_SAM_70_UNK) ? 120000 : 50000); + (_display_id == PANEL_SAM_AMS699VC01) ? 120000 : 50000); skip_panel_deinit: // Disable LCD power pins. gpio_write(GPIO_PORT_V, GPIO_PIN_2, GPIO_LOW); // LCD Reset disable. + usleep(10000); - if (!nx_aula) // HOS uses panel id. + if (!_nx_aula) // HOS uses panel id. { - usleep(10000); - gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_LOW); // LCD -5V disable. - usleep(10000); - gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_LOW); // LCD +5V disable. - usleep(10000); + gpio_write(GPIO_PORT_I, GPIO_PIN_1, GPIO_LOW); // LCD AVDD -5.4V disable. + gpio_write(GPIO_PORT_I, GPIO_PIN_0, GPIO_LOW); // LCD AVDD +5.4V disable. + + // Make sure LCD PWM backlight pin is in PWM0 mode. + gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight PWM. + PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = PINMUX_TRISTATE | PINMUX_PULL_DOWN | 1; // Set PWM0 mode. } - else - usleep(30000); // Aula Panel. + usleep(10000); // Disable Display Interface specific clocks. CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI); CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_CLR) = BIT(CLK_H_MIPI_CAL) | BIT(CLK_H_DSI); - CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1); - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_HOST1X) | BIT(CLK_L_DISP1); + CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_DISP1); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_DISP1); // Power down pads. - DSI(_DSIREG(DSI_PAD_CONTROL_0)) = DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF); + DSI(_DSIREG(DSI_PAD_CONTROL_0)) = DSI_PAD_CONTROL_VS1_PULLDN_CLK | DSI_PAD_CONTROL_VS1_PULLDN(0xF) | + DSI_PAD_CONTROL_VS1_PDIO_CLK | DSI_PAD_CONTROL_VS1_PDIO(0xF); DSI(_DSIREG(DSI_POWER_CONTROL)) = 0; - // Switch LCD PWM backlight pin to special function mode and enable PWM0 mode. - if (!nx_aula) - { - gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_SPIO); // Backlight PWM. - PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_TRISTATE) | PINMUX_TRISTATE; - PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) = (PINMUX_AUX(PINMUX_AUX_LCD_BL_PWM) & ~PINMUX_FUNC_MASK) | 1; // Set PWM0 mode. - } + // Disable DSI AVDD. + max7762x_regulator_enable(REGULATOR_LDO0, false); } void display_end() { _display_panel_and_hw_end(false); }; @@ -724,7 +807,7 @@ u16 display_get_decoded_panel_id() void display_set_decoded_panel_id(u32 id) { // Get Hardware type, as it's used in various DI functions. - nx_aula = fuse_read_hw_type() == FUSE_NX_HW_TYPE_AULA; + _nx_aula = fuse_read_hw_type() == FUSE_NX_HW_TYPE_AULA; // Decode Display ID. _display_id = ((id >> 8) & 0xFF00) | (id & 0xFF); @@ -733,131 +816,218 @@ void display_set_decoded_panel_id(u32 id) _display_id = PANEL_JDI_XXX062M; // For Aula ensure that we have a compatible panel id. - if (nx_aula && _display_id == 0xCCCC) - _display_id = PANEL_SAM_70_UNK; + if (_nx_aula && _display_id == 0xCCCC) + _display_id = PANEL_SAM_AMS699VC01; } void display_color_screen(u32 color) { - exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_one_color, 8); + // Disable all windows. + reg_write_array((u32 *)DISPLAY_A_BASE, _di_win_one_color, ARRAY_SIZE(_di_win_one_color)); // Configure display to show single color. - DISPLAY_A(_DIREG(DC_WIN_AD_WIN_OPTIONS)) = 0; - DISPLAY_A(_DIREG(DC_WIN_BD_WIN_OPTIONS)) = 0; - DISPLAY_A(_DIREG(DC_WIN_CD_WIN_OPTIONS)) = 0; DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color; - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = (DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE) | GENERAL_ACT_REQ; - usleep(35000); // No need to wait on Aula. - if (_display_id != PANEL_SAM_70_UNK) + // Arm and activate changes. + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE | WIN_D_UPDATE; + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ | WIN_D_ACT_REQ; + usleep(35000); // Wait 2 frames. No need on Aula. + + if (_display_id != PANEL_SAM_AMS699VC01) display_backlight(true); else - display_backlight_brightness(255, 0); + display_backlight_brightness(150, 0); } -u32 *display_init_framebuffer_pitch() +u32 *display_init_window_a_pitch() { // Sanitize framebuffer area. - memset((u32 *)IPL_FB_ADDRESS, 0, 0x3C0000); + memset((u32 *)IPL_FB_ADDRESS, 0, IPL_FB_SZ); - // This configures the framebuffer @ IPL_FB_ADDRESS with a resolution of 1280x720 (line stride 720). - exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_pitch, 32); - usleep(35000); // No need to wait on Aula. + // This configures the framebuffer @ IPL_FB_ADDRESS with a resolution of 720x1280 (line stride 720). + reg_write_array((u32 *)DISPLAY_A_BASE, _di_winA_pitch, ARRAY_SIZE(_di_winA_pitch)); + //usleep(35000); // Wait 2 frames. No need on Aula. - return (u32 *)IPL_FB_ADDRESS; + return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR)); } -u32 *display_init_framebuffer_pitch_inv() +u32 *display_init_window_a_pitch_vic() { - // This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 1280x720 (line stride 720). - exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_pitch_inv, 34); - usleep(35000); // No need to wait on Aula. + // This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 720x1280 (line stride 720). + if (_display_id != PANEL_SAM_AMS699VC01) + usleep(8000); // Wait half frame for PWM to apply. + reg_write_array((u32 *)DISPLAY_A_BASE, _di_winA_pitch_vic, ARRAY_SIZE(_di_winA_pitch_vic)); + if (_display_id != PANEL_SAM_AMS699VC01) + usleep(35000); // Wait 2 frames. - return (u32 *)NYX_FB_ADDRESS; + return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR)); } -u32 *display_init_framebuffer_block() +u32 *display_init_window_a_pitch_inv() { - // This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 1280x720 (line stride 720). - exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_block, 34); - usleep(35000); // No need to wait on Aula. + // This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 720x1280 (line stride 720). + reg_write_array((u32 *)DISPLAY_A_BASE, _di_winA_pitch_inv, ARRAY_SIZE(_di_winA_pitch_inv)); + usleep(35000); // Wait 2 frames. No need on Aula. - return (u32 *)NYX_FB_ADDRESS; + return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR)); } -u32 *display_init_framebuffer_log() +u32 *display_init_window_a_block() +{ + // This configures the framebuffer @ NYX_FB_ADDRESS with a resolution of 720x1280. + reg_write_array((u32 *)DISPLAY_A_BASE, _di_winA_block, ARRAY_SIZE(_di_winA_block)); + usleep(35000); // Wait 2 frames. No need on Aula. + + return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR)); +} + +u32 *display_init_window_d_console() { // This configures the framebuffer @ LOG_FB_ADDRESS with a resolution of 1280x720 (line stride 720). - exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer_log, 20); + reg_write_array((u32 *)DISPLAY_A_BASE, _di_winD_log, ARRAY_SIZE(_di_winD_log)); - return (u32 *)LOG_FB_ADDRESS; + return (u32 *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR)); } -void display_activate_console() +void display_window_disable(u32 window) { - DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window D. - DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = WIN_ENABLE; // Enable window DD. - DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0xFF80; - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; + // Select window C. + DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = BIT(WINDOW_SELECT + window); + + // Disable window C. + DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = 0; + + // Arm and activate changes. + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | BIT(WIN_UPDATE + window); + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | BIT(WIN_ACT_REQ + window); +} + +void display_set_framebuffer(u32 window, void *fb) +{ + // Select window. + DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = BIT(WINDOW_SELECT + window); + + // Set new fb address. + DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR)) = (u32)fb; + + // Arm and activate changes. + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | BIT(WIN_UPDATE + window); + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | BIT(WIN_ACT_REQ + window); +} + +void display_move_framebuffer(u32 window, void *fb) +{ + // Select window. + DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = BIT(WINDOW_SELECT + window); + + // Get current framebuffer address. + const void *fb_curr = (void *)DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR)); + u32 win_size = DISPLAY_A(_DIREG(DC_WIN_PRESCALED_SIZE)); + win_size = (win_size & 0x7FFF) * ((win_size >> 16) & 0x1FFF); + + // Copy fb over. + memcpy(fb, fb_curr, win_size); + + // Set new fb address. + DISPLAY_A(_DIREG(DC_WINBUF_START_ADDR)) = (u32)fb; + + // Arm and activate changes. + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | BIT(WIN_UPDATE + window); + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | BIT(WIN_ACT_REQ + window); +} + +void display_window_d_console_enable() +{ + // Only update active registers on vsync. + DISPLAY_A(_DIREG(DC_CMD_REG_ACT_CONTROL)) = DISPLAY_A(_DIREG(DC_CMD_REG_ACT_CONTROL)) & ~WIN_D_ACT_HCNTR_SEL; + + // Select window D. + DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; + + // Enable and setup window D. + DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = WIN_ENABLE; + DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0xFF80; // X: -128. + + // Arm and activate changes. + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ; + // Pull-down effect. for (u32 i = 0xFF80; i < 0x10000; i++) { + // Set window position. DISPLAY_A(_DIREG(DC_WIN_POSITION)) = i & 0xFFFF; - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; + + // Arm and activate changes. + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ; usleep(1000); } DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0; - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; + + // Arm and activate changes. + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ; } -void display_deactivate_console() +void display_window_d_console_disable() { - DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; // Select window D. + // Select window D. + DISPLAY_A(_DIREG(DC_CMD_DISPLAY_WINDOW_HEADER)) = WINDOW_D_SELECT; + // Pull-up effect. for (u32 i = 0xFFFF; i > 0xFF7F; i--) { + // Set window position. DISPLAY_A(_DIREG(DC_WIN_POSITION)) = i & 0xFFFF; - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; + + // Arm and activate changes. + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ; usleep(500); } - DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0; - DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = 0; // Disable window DD. - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; + // Disable window D. + DISPLAY_A(_DIREG(DC_WIN_POSITION)) = 0; + DISPLAY_A(_DIREG(DC_WIN_WIN_OPTIONS)) = 0; + + // Arm and activate changes. + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | WIN_D_UPDATE; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | WIN_D_ACT_REQ; } -void display_init_cursor(void *crs_fb, u32 size) +void display_cursor_init(void *crs_fb, u32 size) { // Setup cursor. - DISPLAY_A(_DIREG(DC_DISP_CURSOR_START_ADDR)) = CURSOR_CLIPPING(CURSOR_CLIP_WIN_A) | size | ((u32)crs_fb >> 10); - DISPLAY_A(_DIREG(DC_DISP_BLEND_CURSOR_CONTROL)) = - CURSOR_BLEND_R8G8B8A8 | CURSOR_BLEND_DST_FACTOR(CURSOR_BLEND_K1) | CURSOR_BLEND_SRC_FACTOR(CURSOR_BLEND_K1) | 0xFF; + DISPLAY_A(_DIREG(DC_DISP_CURSOR_START_ADDR)) = CURSOR_CLIPPING(CURSOR_CLIP_WIN_A) | size | ((u32)crs_fb >> 10); + DISPLAY_A(_DIREG(DC_DISP_BLEND_CURSOR_CONTROL)) = CURSOR_BLEND_R8G8B8A8 | + CURSOR_BLEND_DST_FACTOR(CURSOR_BLEND_K1) | + CURSOR_BLEND_SRC_FACTOR(CURSOR_BLEND_K1) | 0xFF; + // Enable cursor window. DISPLAY_A(_DIREG(DC_DISP_DISP_WIN_OPTIONS)) |= CURSOR_ENABLE; // Arm and activate changes. - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE; + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ; } -void display_set_pos_cursor(u32 x, u32 y) +void display_cursor_set_pos(u32 x, u32 y) { + // Set cursor position. DISPLAY_A(_DIREG(DC_DISP_CURSOR_POSITION)) = x | (y << 16); - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE; + // Arm and activate changes. + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ; } -void display_deinit_cursor() +void display_cursor_deinit() { DISPLAY_A(_DIREG(DC_DISP_BLEND_CURSOR_CONTROL)) = 0; DISPLAY_A(_DIREG(DC_DISP_DISP_WIN_OPTIONS)) &= ~CURSOR_ENABLE; - DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE; + + DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_UPDATE | CURSOR_UPDATE; DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = GENERAL_ACT_REQ | CURSOR_ACT_REQ; } diff --git a/bdk/display/di.h b/bdk/display/di.h index 9229a22..9a35d4f 100644 --- a/bdk/display/di.h +++ b/bdk/display/di.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2025 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -24,6 +24,11 @@ #define DSI_VIDEO_DISABLED 0 #define DSI_VIDEO_ENABLED 1 +#define WINDOW_A 0 +#define WINDOW_B 1 +#define WINDOW_C 2 +#define WINDOW_D 3 + /*! Display registers. */ #define _DIREG(reg) ((reg) * 4) @@ -43,13 +48,17 @@ // DC_CMD non-shadowed command/sync registers. #define DC_CMD_GENERAL_INCR_SYNCPT 0x00 +#define SYNCPT_GENERAL_INDX(x) (((x) & 0xFF) << 0) +#define SYNCPT_GENERAL_COND(x) (((x) & 0xFF) << 8) +#define COND_REG_WR_SAFE 3 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01 #define SYNCPT_CNTRL_SOFT_RESET BIT(0) #define SYNCPT_CNTRL_NO_STALL BIT(8) #define DC_CMD_CONT_SYNCPT_VSYNC 0x28 -#define SYNCPT_VSYNC_ENABLE BIT(8) +#define SYNCPT_VSYNC_INDX(x) (((x) & 0xFF) << 0) +#define SYNCPT_VSYNC_ENABLE BIT(8) #define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031 @@ -72,19 +81,25 @@ #define DC_CMD_INT_MASK 0x38 #define DC_CMD_INT_ENABLE 0x39 #define DC_CMD_INT_FRAME_END_INT BIT(1) +#define DC_CMD_INT_V_BLANK_INT BIT(2) +#define DC_CMD_INT_POLARITY 0x3B #define DC_CMD_STATE_ACCESS 0x40 -#define READ_MUX BIT(0) -#define WRITE_MUX BIT(2) +#define READ_MUX_ASSEMBLY 0x0 +#define WRITE_MUX_ASSEMBLY 0x0 +#define READ_MUX_ACTIVE BIT(0) +#define WRITE_MUX_ACTIVE BIT(2) #define DC_CMD_STATE_CONTROL 0x41 #define GENERAL_ACT_REQ BIT(0) +#define WIN_ACT_REQ 1 #define WIN_A_ACT_REQ BIT(1) #define WIN_B_ACT_REQ BIT(2) #define WIN_C_ACT_REQ BIT(3) #define WIN_D_ACT_REQ BIT(4) #define CURSOR_ACT_REQ BIT(7) #define GENERAL_UPDATE BIT(8) +#define WIN_UPDATE 9 #define WIN_A_UPDATE BIT(9) #define WIN_B_UPDATE BIT(10) #define WIN_C_UPDATE BIT(11) @@ -93,12 +108,19 @@ #define NC_HOST_TRIG BIT(24) #define DC_CMD_DISPLAY_WINDOW_HEADER 0x42 +#define WINDOW_SELECT 4 #define WINDOW_A_SELECT BIT(4) #define WINDOW_B_SELECT BIT(5) #define WINDOW_C_SELECT BIT(6) #define WINDOW_D_SELECT BIT(7) -#define DC_CMD_REG_ACT_CONTROL 0x043 +#define DC_CMD_REG_ACT_CONTROL 0x43 +#define GENERAL_ACT_HCNTR_SEL BIT(0) +#define WIN_A_ACT_HCNTR_SEL BIT(2) +#define WIN_B_ACT_HCNTR_SEL BIT(4) +#define WIN_C_ACT_HCNTR_SEL BIT(6) +#define CURSOR_ACT_HCNTR_SEL BIT(7) +#define WIN_D_ACT_HCNTR_SEL BIT(10) // DC_D_WIN_DD window D instance of DC_WIN #define DC_D_WIN_DD_WIN_OPTIONS 0x80 @@ -124,6 +146,32 @@ #define DC_COM_CRC_CONTROL 0x300 #define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x)) #define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x)) +#define LSC0_OUTPUT_POLARITY_LOW BIT(24) + +// CMU registers. +#define DC_COM_CMU_CSC_KRR 0x32A +#define DC_COM_CMU_CSC_KGR 0x32B +#define DC_COM_CMU_CSC_KBR 0x32C +#define DC_COM_CMU_CSC_KRG 0x32D +#define DC_COM_CMU_CSC_KGG 0x32E +#define DC_COM_CMU_CSC_KBG 0x32F +#define DC_COM_CMU_CSC_KRB 0x330 +#define DC_COM_CMU_CSC_KGB 0x331 +#define DC_COM_CMU_CSC_KBB 0x332 +#define DC_COM_CMU_LUT1 0x336 +#define LUT1_ADDR(x) ((x) & 0xFF) +#define LUT1_DATA(x) (((x) & 0xFFF) << 16) +#define LUT1_READ_DATA(x) (((x) >> 16) & 0xFFF) +#define DC_COM_CMU_LUT2 0x337 +#define LUT2_ADDR(x) ((x) & 0x3FF) +#define LUT2_DATA(x) (((x) & 0xFF) << 16) +#define LUT2_READ_DATA(x) (((x) >> 16) & 0xFF) +#define DC_COM_CMU_LUT1_READ 0x338 +#define LUT1_READ_ADDR(x) (((x) & 0xFF) << 8) +#define LUT1_READ_EN BIT(0) +#define DC_COM_CMU_LUT2_READ 0x339 +#define LUT2_READ_ADDR(x) (((x) & 0x3FF) << 8) +#define LUT2_READ_EN BIT(0) #define DC_COM_DSC_TOP_CTL 0x33E @@ -139,15 +187,32 @@ #define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 #define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404 + #define DC_DISP_DISP_TIMING_OPTIONS 0x405 +#define VSYNC_H_POSITION(x) (((x) & 0x1FFF) << 0) + #define DC_DISP_REF_TO_SYNC 0x406 +#define H_REF_TO_SYNC(x) (((x) & 0x1FFF) << 0) // Min 0 pixel clock. +#define V_REF_TO_SYNC(x) (((x) & 0x1FFF) << 16) // Min 1 line clock. + #define DC_DISP_SYNC_WIDTH 0x407 +#define H_SYNC_WIDTH(x) (((x) & 0x1FFF) << 0) // Min 1 pixel clock. +#define V_SYNC_WIDTH(x) (((x) & 0x1FFF) << 16) // Min 1 line clock. + #define DC_DISP_BACK_PORCH 0x408 +#define H_BACK_PORCH(x) (((x) & 0x1FFF) << 0) +#define V_BACK_PORCH(x) (((x) & 0x1FFF) << 16) + #define DC_DISP_ACTIVE 0x409 +#define H_DISP_ACTIVE(x) (((x) & 0x1FFF) << 0) // Min 16 pixel clock. +#define V_DISP_ACTIVE(x) (((x) & 0x1FFF) << 16) // Min 16 line clock. + #define DC_DISP_FRONT_PORCH 0x40A +#define H_FRONT_PORCH(x) (((x) & 0x1FFF) << 0) // Min -=PS_=-H_REF_TO_SYNC + 1 +#define V_FRONT_PORCH(x) (((x) & 0x1FFF) << 16) // Min -=PS_=-V_REF_TO_SYNC + 1 #define DC_DISP_DISP_CLOCK_CONTROL 0x42E -#define SHIFT_CLK_DIVIDER(x) ((x) & 0xff) +#define SHIFT_CLK_DIVIDER(x) ((x) & 0xFF) #define PIXEL_CLK_DIVIDER_PCD1 (0 << 8) #define PIXEL_CLK_DIVIDER_PCD1H (1 << 8) #define PIXEL_CLK_DIVIDER_PCD2 (2 << 8) @@ -178,11 +243,7 @@ #define DISP_ORDER_BLUE_RED (1 << 9) #define DC_DISP_DISP_COLOR_CONTROL 0x430 -#define DITHER_CONTROL_MASK (3 << 8) -#define DITHER_CONTROL_DISABLE (0 << 8) -#define DITHER_CONTROL_ORDERED (2 << 8) -#define DITHER_CONTROL_ERRDIFF (3 << 8) -#define BASE_COLOR_SIZE_MASK (0xf << 0) +#define BASE_COLOR_SIZE_MASK (0xF << 0) #define BASE_COLOR_SIZE_666 (0 << 0) #define BASE_COLOR_SIZE_111 (1 << 0) #define BASE_COLOR_SIZE_222 (2 << 0) @@ -192,6 +253,13 @@ #define BASE_COLOR_SIZE_565 (6 << 0) #define BASE_COLOR_SIZE_332 (7 << 0) #define BASE_COLOR_SIZE_888 (8 << 0) +#define DITHER_CONTROL_MASK (3 << 8) +#define DITHER_CONTROL_DISABLE (0 << 8) +#define DITHER_CONTROL_ORDERED (2 << 8) +#define DITHER_CONTROL_ERRDIFF (3 << 8) +#define DISP_COLOR_SWAP BIT(16) +#define BLANK_COLOR_WHITE BIT(17) +#define CMU_ENABLE BIT(20) #define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 #define SC0_H_QUALIFIER_NONE BIT(0) @@ -213,6 +281,7 @@ #define CURSOR_COLOR(r,g,b) (((r) & 0xFF) | (((g) & 0xFF) << 8) | (((b) & 0xFF) << 16)) #define DC_DISP_CURSOR_START_ADDR 0x43E +#define DC_DISP_CURSOR_START_ADDR_NS 0x43F #define CURSOR_CLIPPING(w) ((w) << 28) #define CURSOR_CLIP_WIN_A 1 #define CURSOR_CLIP_WIN_B 2 @@ -224,6 +293,7 @@ #define DC_DISP_CURSOR_POSITION 0x440 #define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4 #define DC_DISP_CURSOR_START_ADDR_HI 0x4EC +#define DC_DISP_CURSOR_START_ADDR_HI_NS 0x4ED #define DC_DISP_BLEND_CURSOR_CONTROL 0x4F1 #define CURSOR_BLEND_2BIT (0 << 24) #define CURSOR_BLEND_R8G8B8A8 (1 << 24) @@ -239,32 +309,44 @@ #define DC_DISP_SD_BL_CONTROL 0x4DC #define DC_DISP_BLEND_BACKGROUND_COLOR 0x4E4 -#define DC_WIN_CSC_YOF 0x611 -#define DC_WIN_CSC_KYRGB 0x612 -#define DC_WIN_CSC_KUR 0x613 -#define DC_WIN_CSC_KVR 0x614 -#define DC_WIN_CSC_KUG 0x615 -#define DC_WIN_CSC_KVG 0x616 -#define DC_WIN_CSC_KUB 0x617 -#define DC_WIN_CSC_KVB 0x618 +#define DC_WINC_COLOR_PALETTE 0x500 +#define COLOR_PALETTE_IDX(off) (DC_WINC_COLOR_PALETTE + (off)) +#define COLOR_PALETTE_RGB(rgb) (byte_swap_32(rgb) >> 8) +#define DC_WINC_PALETTE_COLOR_EXT 0x600 + +#define DC_WINC_H_FILTER_P(p) (0x601 + (p)) +#define DC_WINC_V_FILTER_P(p) (0x619 + (p)) +#define DC_WINC_H_FILTER_HI_P(p) (0x629 + (p)) + +#define DC_WINC_CSC_YOF 0x611 +#define DC_WINC_CSC_KYRGB 0x612 +#define DC_WINC_CSC_KUR 0x613 +#define DC_WINC_CSC_KVR 0x614 +#define DC_WINC_CSC_KUG 0x615 +#define DC_WINC_CSC_KVG 0x616 +#define DC_WINC_CSC_KUB 0x617 +#define DC_WINC_CSC_KVB 0x618 #define DC_WIN_AD_WIN_OPTIONS 0xB80 #define DC_WIN_BD_WIN_OPTIONS 0xD80 #define DC_WIN_CD_WIN_OPTIONS 0xF80 // The following registers are A/B/C shadows of the 0xB80/0xD80/0xF80 registers (see DISPLAY_WINDOW_HEADER). #define DC_WIN_WIN_OPTIONS 0x700 -#define H_DIRECTION BIT(0) -#define V_DIRECTION BIT(2) -#define SCAN_COLUMN BIT(4) -#define COLOR_EXPAND BIT(6) -#define CSC_ENABLE BIT(18) -#define WIN_ENABLE BIT(30) +#define H_DIRECTION BIT(0) +#define V_DIRECTION BIT(2) +#define SCAN_COLUMN BIT(4) +#define COLOR_EXPAND BIT(6) +#define H_FILTER_ENABLE BIT(8) +#define V_FILTER_ENABLE BIT(10) +#define COLOR_PALETTE_ENABLE BIT(16) +#define CSC_ENABLE BIT(18) +#define DV_ENABLE BIT(20) +#define WIN_ENABLE BIT(30) +#define H_FILTER_EXPAND BIT(31) #define DC_WIN_BUFFER_CONTROL 0x702 #define BUFFER_CONTROL_HOST 0 #define BUFFER_CONTROL_VI 1 -#define BUFFER_CONTROL_EPP 2 -#define BUFFER_CONTROL_MPEGE 3 #define BUFFER_CONTROL_SB2D 4 #define DC_WIN_COLOR_DEPTH 0x703 @@ -290,34 +372,55 @@ #define WIN_COLOR_DEPTH_YUV422R 0x17 #define WIN_COLOR_DEPTH_YCbCr422RA 0x18 #define WIN_COLOR_DEPTH_YUV422RA 0x19 +#define WIN_COLOR_DEPTH_X1R5G5B5 0x1E +#define WIN_COLOR_DEPTH_R5G5B5X1 0x1F +#define WIN_COLOR_DEPTH_X1B5G5R5 0x20 +#define WIN_COLOR_DEPTH_B5G5R5X1 0x21 +#define WIN_COLOR_DEPTH_YCbCr444P 0x29 +#define WIN_COLOR_DEPTH_YCrCb420SP 0x2A +#define WIN_COLOR_DEPTH_YCbCr420SP 0x2B +#define WIN_COLOR_DEPTH_YCrCb422SP 0x2C +#define WIN_COLOR_DEPTH_YCbCr422SP 0x2D +#define WIN_COLOR_DEPTH_YUV444P 0x34 +#define WIN_COLOR_DEPTH_YVU420SP 0x35 +#define WIN_COLOR_DEPTH_YUV420SP 0x36 +#define WIN_COLOR_DEPTH_YVU422SP 0x37 +#define WIN_COLOR_DEPTH_YUV422SP 0x38 +#define WIN_COLOR_DEPTH_YVU444SP 0x3B +#define WIN_COLOR_DEPTH_YUV444SP 0x3C #define DC_WIN_POSITION 0x704 -#define H_POSITION(x) (((x) & 0xFfff) << 0) -#define V_POSITION(x) (((x) & 0x1fff) << 16) +#define H_POSITION(x) (((x) & 0xFFFF) << 0) // Support negative. +#define V_POSITION(x) (((x) & 0xFFFF) << 16) // Support negative. #define DC_WIN_SIZE 0x705 -#define H_SIZE(x) (((x) & 0x1fff) << 0) -#define V_SIZE(x) (((x) & 0x1fff) << 16) +#define H_SIZE(x) (((x) & 0x1FFF) << 0) +#define V_SIZE(x) (((x) & 0x1FFF) << 16) #define DC_WIN_PRESCALED_SIZE 0x706 -#define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0) -#define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) +#define H_PRESCALED_SIZE(x) (((x) & 0x7FFF) << 0) +#define V_PRESCALED_SIZE(x) (((x) & 0x1FFF) << 16) #define DC_WIN_H_INITIAL_DDA 0x707 #define DC_WIN_V_INITIAL_DDA 0x708 #define DC_WIN_DDA_INC 0x709 -#define H_DDA_INC(x) (((x) & 0xffff) << 0) -#define V_DDA_INC(x) (((x) & 0xffff) << 16) +#define H_DDA_INC(x) (((x) & 0xFFFF) << 0) +#define V_DDA_INC(x) (((x) & 0xFFFF) << 16) #define DC_WIN_LINE_STRIDE 0x70A #define LINE_STRIDE(x) (x) -#define UV_LINE_STRIDE(x) (((x) & 0xffff) << 16) +#define UV_LINE_STRIDE(x) (((x) & 0xFFFF) << 16) + #define DC_WIN_DV_CONTROL 0x70E +#define DV_CTRL_R(r) (((r) & 7) << 16) +#define DV_CTRL_G(g) (((g) & 7) << 8) +#define DV_CTRL_B(b) (((b) & 7) << 0) #define DC_WINBUF_BLEND_LAYER_CONTROL 0x716 -#define WIN_K1(x) (((x) & 0xff) << 8) -#define WIN_K2(x) (((x) & 0xff) << 16) +#define WIN_BLEND_DEPTH(x) (((x) & 0xFF) << 0) +#define WIN_K1(x) (((x) & 0xFF) << 8) +#define WIN_K2(x) (((x) & 0xFF) << 16) #define WIN_BLEND_ENABLE (0 << 24) #define WIN_BLEND_BYPASS (1 << 24) @@ -348,8 +451,8 @@ #define WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_K2 (3 << 12) #define DC_WINBUF_BLEND_ALPHA_1BIT 0x719 -#define WIN_ALPHA_1BIT_WEIGHT0(x) (((x) & 0xff) << 0) -#define WIN_ALPHA_1BIT_WEIGHT1(x) (((x) & 0xff) << 8) +#define WIN_ALPHA_1BIT_WEIGHT0(x) (((x) & 0xFF) << 0) +#define WIN_ALPHA_1BIT_WEIGHT1(x) (((x) & 0xFF) << 8) /*! The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). */ #define DC_WINBUF_START_ADDR 0x800 @@ -361,6 +464,8 @@ #define BLOCK (2 << 0) #define BLOCK_HEIGHT(x) (((x) & 0x7) << 4) +#define DC_WINBUF_MEMFETCH_CONTROL 0x82B + /*! Display serial interface registers. */ #define _DSIREG(reg) ((reg) * 4) @@ -386,6 +491,7 @@ #define DSI_HOST_CONTROL_FIFO_SEL BIT(4) #define DSI_HOST_CONTROL_HS BIT(5) #define DSI_HOST_CONTROL_RAW BIT(6) +#define DSI_HOST_CONTROL_TX_TRIG_MASK (3 << 12) #define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12) #define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12) #define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12) @@ -414,6 +520,7 @@ #define DSI_STATUS 0x15 #define DSI_STATUS_RX_FIFO_SIZE 0x1F +#define DSI_STATUS_TX_FIFO_SIZE 0x20 // Actual depth is 64. #define DSI_INIT_SEQ_CONTROL 0x1A #define DSI_INIT_SEQ_DATA_0 0x1B @@ -433,30 +540,34 @@ #define DSI_PKT_SEQ_5_LO 0x2D #define DSI_PKT_SEQ_5_HI 0x2E #define DSI_DCS_CMDS 0x33 + #define DSI_PKT_LEN_0_1 0x34 #define DSI_PKT_LEN_2_3 0x35 #define DSI_PKT_LEN_4_5 0x36 #define DSI_PKT_LEN_6_7 0x37 +#define PKT0_LEN(x) (((x) & 0xFFFF) << 0) +#define PKT1_LEN(x) (((x) & 0xFFFF) << 16) + #define DSI_PHY_TIMING_0 0x3C #define DSI_PHY_TIMING_1 0x3D #define DSI_PHY_TIMING_2 0x3E #define DSI_BTA_TIMING 0x3F #define DSI_TIMEOUT_0 0x44 -#define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0) -#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16) +#define DSI_TIMEOUT_HTX(x) (((x) & 0xFFFF) << 0) +#define DSI_TIMEOUT_LRX(x) (((x) & 0xFFFF) << 16) #define DSI_TIMEOUT_1 0x45 -#define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0) -#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16) +#define DSI_TIMEOUT_TA(x) (((x) & 0xFFFF) << 0) +#define DSI_TIMEOUT_PR(x) (((x) & 0xFFFF) << 16) #define DSI_TO_TALLY 0x46 #define DSI_PAD_CONTROL_0 0x4B #define DSI_PAD_CONTROL_VS1_PDIO_CLK BIT(8) -#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0) +#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xF) << 0) #define DSI_PAD_CONTROL_VS1_PULLDN_CLK BIT(24) -#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16) +#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xF) << 16) #define DSI_PAD_CONTROL_CD 0x4C #define DSI_VIDEO_MODE_CONTROL 0x4E @@ -593,6 +704,7 @@ #define MIPI_DCS_GET_SCANLINE 0x45 #define MIPI_DCS_SET_TEAR_SCANLINE_WIDTH 0x46 #define MIPI_DCS_GET_SCANLINE_WIDTH 0x47 +#define MIPI_DSI_AREA_COLOR_MODE 0x4C #define MIPI_DCS_SET_BRIGHTNESS 0x51 // DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL. 1 byte. 0-7: DBV. #define MIPI_DCS_GET_BRIGHTNESS 0x52 // 1 byte. 0-7: DBV. #define MIPI_DCS_SET_CONTROL_DISPLAY 0x53 // 1 byte. 2: BL, 3: DD, 5: BCTRL. @@ -606,7 +718,9 @@ #define MIPI_DCS_READ_DDB_CONTINUE 0xA8 // 0x100 size. /*! MIPI DCS Panel Private CMDs. */ -#define MIPI_DCS_PRIV_UNK_A0 0xA0 +#define MIPI_DCS_PRIV_SM_SET_COLOR_MODE 0xA0 // 43 bytes. +#define MIPI_DCS_PRIV_SM_SET_REG_OFFSET 0xB0 +#define MIPI_DCS_PRIV_SM_SET_ELVSS 0xB1 // OLED backlight tuning. Byte7: PWM transition time in frames. #define MIPI_DCS_PRIV_SET_POWER_CONTROL 0xB1 #define MIPI_DCS_PRIV_SET_EXTC 0xB9 // Enable extended commands. #define MIPI_DCS_PRIV_UNK_BD 0xBD @@ -614,6 +728,9 @@ #define MIPI_DCS_PRIV_UNK_D6 0xD6 #define MIPI_DCS_PRIV_UNK_D8 0xD8 #define MIPI_DCS_PRIV_UNK_D9 0xD9 +#define MIPI_DCS_PRIV_SM_DISPLAY_ID 0xDD + // LVL1 LVL2 LVL3 UNK0 UNK1 +#define MIPI_DCS_PRIV_SM_SET_REGS_LOCK 0xE2 // Samsung: Lock (default): 5A5A A5A5 A5A5 A500 A500. Unlock: A5A5 5A5A 5A5A UNK UNK. #define MIPI_DCS_PRIV_READ_EXTC_CMD_SPI 0xFE // Read EXTC Command In SPI. 1 byte. 0-6: EXT_SPI_CNT, 7:EXT_SP. #define MIPI_DCS_PRIV_SET_EXTC_CMD_REG 0xFF // EXTC Command Set enable register. 5 bytes. Pass: FF 98 06 04, PAGE. @@ -648,30 +765,59 @@ #define DCS_GAMMA_CURVE_GC2_1_0 BIT(2) #define DCS_GAMMA_CURVE_GC3_1_0 BIT(3) // Are there more? +#define DCS_CONTROL_DISPLAY_SM_FLASHLIGHT BIT(2) #define DCS_CONTROL_DISPLAY_BACKLIGHT_CTRL BIT(2) -#define DCS_CONTROL_DISPLAY_DIMMING_CTRL BIT(3) +#define DCS_CONTROL_DISPLAY_DIMMING_CTRL BIT(3) // Transition fading. #define DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL BIT(5) +#define DCS_CONTROL_DISPLAY_HBM_CTRL0 BIT(6) +#define DCS_CONTROL_DISPLAY_HBM_CTRL1 BIT(7) + +#define DCS_SM_COLOR_MODE_SATURATED 0x00 // Disabled. Based on Vivid but over-saturated. +#define DCS_SM_COLOR_MODE_WASHED 0x45 +#define DCS_SM_COLOR_MODE_BASIC 0x03 // Real natural profile. +#define DCS_SM_COLOR_MODE_POR_RESET 0x20 // Reset value on power on. +#define DCS_SM_COLOR_MODE_NATURAL 0x23 // Not actually natural.. Extra saturation. +#define DCS_SM_COLOR_MODE_VIVID 0x65 // Saturated. +#define DCS_SM_COLOR_MODE_NIGHT0 0x43 // Based on Washed Out. +#define DCS_SM_COLOR_MODE_NIGHT1 0x15 // Based on Basic. +#define DCS_SM_COLOR_MODE_NIGHT2 0x35 // Based on Natural. +#define DCS_SM_COLOR_MODE_NIGHT3 0x75 // Based on Vivid. + +#define DCS_SM_COLOR_MODE_ENABLE BIT(0) + +#define PANEL_SM_BL_CANDELA_MAX 2047 /* Switch Panels: * - * 6.2" panels for Icosa and Iowa skus: + * 6.2" panels for Icosa and Iowa SKUs: * [10] 81 [26]: JDI LPM062M326A * [10] 96 [09]: JDI LAM062M109A * [20] 93 [0F]: InnoLux P062CCA-AZ1 (Rev A1) * [20] 95 [0F]: InnoLux P062CCA-AZ2 (Rev B1) - * [20] 96 [0F]: InnoLux P062CCA-AZ3 [UNCONFIRMED MODEL REV] - * [20] 98 [0F]: InnoLux P062CCA-??? [UNCONFIRMED MODEL REV] + * [20] 96 [0F]: InnoLux P062CCA-??? (Rev XX) [UNCONFIRMED MODEL+REV] + * [20] 97 [0F]: InnoLux P062CCA-??? (Rev XX) [UNCONFIRMED MODEL+REV] + * [20] 98 [0F]: InnoLux P062CCA-??? (Rev XX) [UNCONFIRMED MODEL+REV] + * [20] 99 [0F]: InnoLux P062CCA-??? (Rev XX) [UNCONFIRMED MODEL+REV] + * [30] 93 [0F]: AUO A062TAN00 (59.06A33.000) * [30] 94 [0F]: AUO A062TAN01 (59.06A33.001) * [30] 95 [0F]: AUO A062TAN02 (59.06A33.002) + * [30] 97 [0F]: AUO A062TAN02 (59.06A33.002) [From photo of assumed same panel] + * [30] 98 [0F]: AUO A062TAN0? [UNCONFIRMED MODEL] * [30] XX [0F]: AUO A062TAN03 (59.06A33.003) [UNCONFIRMED ID] * - * 5.5" panels for Hoag skus: - * [20] 94 [10]: InnoLux 2J055IA-27A (Rev B1) - * [30] 93 [10]: AUO A055TAN01 (59.05A30.001) - * [40] XX [10]: Vendor 40 [UNCONFIRMED ID] * - * 7.0" OLED panels for Aula skus: - * [50] XX [20]: Samsung AMS700XXXX [UNCONFIRMED ID and MODEL] + * 5.5" panels for Hoag SKU: + * [20] 94 [10]: InnoLux 2J055IA-27A (Rev B1) (6203B001P4000) + * [20] 95 [10]: InnoLux 2J055IA-27A (Rev XX) [UNCONFIRMED MODEL+REV] + * [20] 96 [10]: InnoLux 2J055IA-27A (Rev XX) [UNCONFIRMED MODEL+REV] + * [30] 93 [10]: AUO A055TAN01 (59.05A30.001) + * [30] 94 [10]: AUO A055TAN02 (59.05A30.002) + * [30] 95 [10]: AUO A055TAN03 (59.05A30.003) + * [40] 94 [10]: Sharp LQ055T1SW10 (Rev P) + * + * + * 7.0" OLED panels for Aula SKU: + * [50] 9B [20]: Samsung AMS699VC01-0 (Rev 2.5) */ /* Display ID Decoding: @@ -684,7 +830,7 @@ * 10h: Japan Display Inc. * 20h: InnoLux Corporation * 30h: AU Optronics - * 40h: Unknown0 + * 40h: Sharp * 50h: Samsung * * Boards, Panel Size: @@ -702,18 +848,36 @@ enum PANEL_AUO_A062TAN01 = 0x0F30, PANEL_INL_2J055IA_27A = 0x1020, PANEL_AUO_A055TAN01 = 0x1030, - PANEL_V40_55_UNK = 0x1040, - PANEL_SAM_70_UNK = 0x2050 + PANEL_SHP_LQ055T1SW10 = 0x1040, + PANEL_SAM_AMS699VC01 = 0x2050, + + // Found on 6/2" clones. Unknown markings. Quality seems JDI like. Has bad low backlight scaling. ID: [83] 94 [0F]. + PANEL_OEM_CLONE_6_2 = 0x0F83, + // Found on 5.5" clones with AUO A055TAN02 (59.05A30.001) fake markings. + PANEL_OEM_CLONE_5_5 = 0x00B3, + // Found on 5.5" clones with AUO A055TAN02 (59.05A30.001) fake markings. + PANEL_OEM_CLONE = 0x0000 }; void display_init(); void display_backlight_pwm_init(); void display_end(); +/*! Interrupt management. */ +void display_enable_interrupt(u32 intr); +void display_disable_interrupt(u32 intr); +void display_wait_interrupt(u32 intr); + /*! Get/Set Display panel ID. */ u16 display_get_decoded_panel_id(); void display_set_decoded_panel_id(u32 id); +/*! MIPI DCS register management */ +int display_dsi_read(u8 cmd, u32 len, void *data); +int display_dsi_vblank_read(u8 cmd, u32 len, void *data); +void display_dsi_write(u8 cmd, u32 len, void *data); +void display_dsi_vblank_write(u8 cmd, u32 len, void *data); + /*! Show one single color on the display. */ void display_color_screen(u32 color); @@ -722,18 +886,22 @@ void display_backlight(bool enable); void display_backlight_brightness(u32 brightness, u32 step_delay); u32 display_get_backlight_brightness(); -/*! Init display in full 1280x720 resolution (B8G8R8A8, line stride 768, framebuffer size = 1280*768*4 bytes). */ -u32 *display_init_framebuffer_pitch(); -u32 *display_init_framebuffer_pitch_inv(); -u32 *display_init_framebuffer_block(); -u32 *display_init_framebuffer_log(); -void display_activate_console(); -void display_deactivate_console(); -void display_init_cursor(void *crs_fb, u32 size); -void display_set_pos_cursor(u32 x, u32 y); -void display_deinit_cursor(); +u32 *display_init_window_a_pitch(); +u32 *display_init_window_a_pitch_vic(); +u32 *display_init_window_a_pitch_inv(); +u32 *display_init_window_a_block(); +u32 *display_init_window_d_console(); -void display_dsi_write(u8 cmd, u32 len, void *data, bool video_enabled); -int display_dsi_read(u8 cmd, u32 len, void *data, bool video_enabled); +void display_window_disable(u32 window); + +void display_set_framebuffer(u32 window, void *fb); +void display_move_framebuffer(u32 window, void *fb); + +void display_window_d_console_enable(); +void display_window_d_console_disable(); + +void display_cursor_init(void *crs_fb, u32 size); +void display_cursor_set_pos(u32 x, u32 y); +void display_cursor_deinit(); #endif diff --git a/bdk/display/di.inl b/bdk/display/di.inl index c1e5d84..d74130e 100644 --- a/bdk/display/di.inl +++ b/bdk/display/di.inl @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert -* Copyright (c) 2018-2020 CTCaer +* Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,122 +15,66 @@ * along with this program. If not, see . */ -//Display A config. -static const cfg_op_t _display_dc_setup_win_config[94] = { - {DC_CMD_STATE_ACCESS, 0}, +// Display A config. +static const reg_cfg_t _di_dc_setup_win_config[] = { + {DC_CMD_STATE_ACCESS, READ_MUX_ASSEMBLY | WRITE_MUX_ASSEMBLY}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_REG_ACT_CONTROL, 0x54}, // Select H counter for win A/B/C. + {DC_CMD_REG_ACT_CONTROL, WIN_A_ACT_HCNTR_SEL | WIN_B_ACT_HCNTR_SEL | WIN_C_ACT_HCNTR_SEL}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, {DC_DISP_DC_MCCIF_FIFOCTRL, 0}, {DC_DISP_DISP_MEM_HIGH_PRIORITY, 0}, {DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER, 0}, {DC_CMD_DISPLAY_POWER_CONTROL, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | PW4_ENABLE | PM0_ENABLE | PM1_ENABLE}, {DC_CMD_GENERAL_INCR_SYNCPT_CNTRL, SYNCPT_CNTRL_NO_STALL}, - {DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | 0x9}, // 9: SYNCPT - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {DC_CMD_STATE_ACCESS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_CMD_CONT_SYNCPT_VSYNC, SYNCPT_VSYNC_ENABLE | SYNCPT_VSYNC_INDX(9)}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE | WIN_D_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ | WIN_D_ACT_REQ}, + + /* Setup Windows A/B/C */ + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT | WINDOW_B_SELECT | WINDOW_C_SELECT | WINDOW_D_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_DV_CONTROL, 0}, /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, + {DC_WINC_CSC_YOF, 0xF0}, + {DC_WINC_CSC_KYRGB, 0x12A}, + {DC_WINC_CSC_KUR, 0}, + {DC_WINC_CSC_KVR, 0x198}, + {DC_WINC_CSC_KUG, 0x39B}, + {DC_WINC_CSC_KVG, 0x32F}, + {DC_WINC_CSC_KUB, 0x204}, + {DC_WINC_CSC_KVB, 0}, /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, - {DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, + {DC_COM_PIN_OUTPUT_POLARITY(1), LSC0_OUTPUT_POLARITY_LOW}, {DC_COM_PIN_OUTPUT_POLARITY(3), 0}, {DC_DISP_BLEND_BACKGROUND_COLOR, 0}, {DC_COM_CRC_CONTROL, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE | WIN_D_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ | WIN_D_ACT_REQ}, + {DC_WINBUF_BLEND_LAYER_CONTROL, WIN_BLEND_BYPASS | WIN_BLEND_DEPTH(255)}, {DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, {DC_DISP_DISP_WIN_OPTIONS, 0}, {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_STOP}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ} + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE | WIN_D_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ | WIN_D_ACT_REQ} }; -//DSI Init config. -static const cfg_op_t _display_dsi_init_config_part1[8] = { +// DSI Init config. +static const reg_cfg_t _di_dsi_seq_pkt_reset_config0[] = { {DSI_WR_DATA, 0}, {DSI_INT_ENABLE, 0}, {DSI_INT_STATUS, 0}, - {DSI_INT_MASK, 0}, + {DSI_INT_MASK, 0}, {DSI_INIT_SEQ_DATA_0, 0}, {DSI_INIT_SEQ_DATA_1, 0}, {DSI_INIT_SEQ_DATA_2, 0}, {DSI_INIT_SEQ_DATA_3, 0} }; -static const cfg_op_t _display_dsi_init_config_part2[14] = { +static const reg_cfg_t _di_dsi_seq_pkt_reset_config1[] = { {DSI_DCS_CMDS, 0}, {DSI_PKT_SEQ_0_LO, 0}, {DSI_PKT_SEQ_1_LO, 0}, @@ -146,7 +90,7 @@ static const cfg_op_t _display_dsi_init_config_part2[14] = { {DSI_PKT_SEQ_5_HI, 0}, {DSI_CONTROL, 0} }; -static const cfg_op_t _display_dsi_init_config_part3_t210b01[7] = { +static const reg_cfg_t _di_dsi_init_pads_t210b01[] = { {DSI_PAD_CONTROL_1, 0}, {DSI_PAD_CONTROL_2, 0}, {DSI_PAD_CONTROL_3, 0}, @@ -155,51 +99,59 @@ static const cfg_op_t _display_dsi_init_config_part3_t210b01[7] = { {DSI_PAD_CONTROL_6_B01, 0}, {DSI_PAD_CONTROL_7_B01, 0} }; -static const cfg_op_t _display_dsi_init_config_part4[10] = { +static const reg_cfg_t _di_dsi_init_config[] = { {DSI_PAD_CONTROL_CD, 0}, - {DSI_SOL_DELAY, 0x18}, - {DSI_MAX_THRESHOLD, 0x1E0}, + {DSI_SOL_DELAY, 24}, + {DSI_MAX_THRESHOLD, 480}, {DSI_TRIGGER, 0}, {DSI_INIT_SEQ_CONTROL, 0}, + {DSI_PKT_LEN_0_1, 0}, {DSI_PKT_LEN_2_3, 0}, {DSI_PKT_LEN_4_5, 0}, {DSI_PKT_LEN_6_7, 0}, - {DSI_PAD_CONTROL_1, 0} -}; -static const cfg_op_t _display_dsi_init_config_part5[12] = { + + {DSI_PAD_CONTROL_1, 0}, + + /* DSI PHY timings */ + {DSI_PHY_TIMING_0, 0x6070603}, {DSI_PHY_TIMING_1, 0x40A0E05}, {DSI_PHY_TIMING_2, 0x30109}, - {DSI_BTA_TIMING, 0x190A14}, + {DSI_BTA_TIMING, 0x190A14}, + /* DSI timeout */ {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, - {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, + {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x765) | DSI_TIMEOUT_TA(0x2000)}, {DSI_TO_TALLY, 0}, - {DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, // Enable + + {DSI_PAD_CONTROL_0, DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0)}, // Power up. {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, {DSI_POWER_CONTROL, 0}, {DSI_POWER_CONTROL, 0}, - {DSI_PAD_CONTROL_1, 0} -}; -static const cfg_op_t _display_dsi_init_config_part6[14] = { + {DSI_PAD_CONTROL_1, 0}, + + /* DSI PHY timings */ + {DSI_PHY_TIMING_0, 0x6070603}, {DSI_PHY_TIMING_1, 0x40A0E05}, {DSI_PHY_TIMING_2, 0x30118}, - {DSI_BTA_TIMING, 0x190A14}, + {DSI_BTA_TIMING, 0x190A14}, + /* DSI timeout */ {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, - {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)}, + {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)}, {DSI_TO_TALLY, 0}, + {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, {DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_MAX_THRESHOLD, 0x40}, + {DSI_MAX_THRESHOLD, 64}, {DSI_TRIGGER, 0}, {DSI_TX_CRC, 0}, {DSI_INIT_SEQ_CONTROL, 0} }; -//DSI panel config. -static const cfg_op_t _display_init_config_jdi[43] = { +// DSI panel JDI config. +static const reg_cfg_t _di_dsi_panel_init_config_jdi[] = { {DSI_WR_DATA, 0x0439}, // MIPI_DSI_DCS_LONG_WRITE: 4 bytes. {DSI_WR_DATA, 0x9483FFB9}, // MIPI_DCS_PRIV_SET_EXTC. (Pass: FF 83 94). {DSI_TRIGGER, DSI_TRIGGER_HOST}, @@ -245,14 +197,20 @@ static const cfg_op_t _display_init_config_jdi[43] = { {DSI_TRIGGER, DSI_TRIGGER_HOST} }; -//DSI packet config. -static const cfg_op_t _display_dsi_packet_config[19] = { +// DSI packet config. +static const reg_cfg_t _di_dsi_seq_pkt_video_non_burst_no_eot_config[] = { + {DSI_PAD_CONTROL_1, 0}, + + /* DSI PHY timings */ + {DSI_PHY_TIMING_0, 0x6070603}, {DSI_PHY_TIMING_1, 0x40A0E05}, {DSI_PHY_TIMING_2, 0x30172}, - {DSI_BTA_TIMING, 0x190A14}, + {DSI_BTA_TIMING, 0x190A14}, + /* DSI timeout */ {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xA40)}, - {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)}, + {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x5A2F) | DSI_TIMEOUT_TA(0x2000)}, {DSI_TO_TALLY, 0}, + {DSI_PKT_SEQ_0_LO, 0x40000208}, {DSI_PKT_SEQ_2_LO, 0x40000308}, {DSI_PKT_SEQ_4_LO, 0x40000308}, @@ -261,66 +219,66 @@ static const cfg_op_t _display_dsi_packet_config[19] = { {DSI_PKT_SEQ_3_HI, 0x2CC}, {DSI_PKT_SEQ_5_LO, 0x3F3B2B08}, {DSI_PKT_SEQ_5_HI, 0x2CC}, - {DSI_PKT_LEN_0_1, 0xCE0000}, - {DSI_PKT_LEN_2_3, 0x87001A2}, - {DSI_PKT_LEN_4_5, 0x190}, - {DSI_PKT_LEN_6_7, 0x190}, + {DSI_PKT_LEN_0_1, PKT1_LEN(206) | PKT0_LEN(0)}, + {DSI_PKT_LEN_2_3, PKT1_LEN(2160) | PKT0_LEN(418)}, + {DSI_PKT_LEN_4_5, PKT1_LEN(0) | PKT0_LEN(400)}, + {DSI_PKT_LEN_6_7, PKT1_LEN(0) | PKT0_LEN(400)}, {DSI_HOST_CONTROL, 0} }; -//DSI mode config. -static const cfg_op_t _display_dsi_mode_config[10] = { +// DSI mode config. +static const reg_cfg_t _di_dsi_host_mode_config[] = { {DSI_TRIGGER, 0}, {DSI_CONTROL, 0}, {DSI_SOL_DELAY, 6}, - {DSI_MAX_THRESHOLD, 0x1E0}, + {DSI_MAX_THRESHOLD, 480}, {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, {DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, - {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL| DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_FIFO_SEL | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, {DSI_CONTROL, DSI_CONTROL_HS_CLK_CTRL | DSI_CONTROL_FORMAT(3) | DSI_CONTROL_LANES(3) | DSI_CONTROL_VIDEO_ENABLE}, - {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, - {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC} + {DSI_HOST_CONTROL, DSI_HOST_CONTROL_TX_TRIG_SOL | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, + {DSI_HOST_CONTROL, DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_TX_TRIG_SOL | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC} }; -//MIPI CAL config. -static const cfg_op_t _display_mipi_pad_cal_config[4] = { +// MIPI CAL config. +static const reg_cfg_t _di_mipi_pad_cal_config[] = { {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0}, {MIPI_CAL_CIL_MIPI_CAL_STATUS, 0xF3F10000}, {MIPI_CAL_MIPI_BIAS_PAD_CFG0, 0}, {MIPI_CAL_MIPI_BIAS_PAD_CFG2, 0} }; -//DSI config. -static const cfg_op_t _display_dsi_pad_cal_config_t210[4] = { +// DSI pad config. +static const reg_cfg_t _di_dsi_pad_cal_config_t210[] = { {DSI_PAD_CONTROL_1, 0}, {DSI_PAD_CONTROL_2, 0}, {DSI_PAD_CONTROL_3, DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3)}, {DSI_PAD_CONTROL_4, 0} }; -static const cfg_op_t _display_dsi_pad_cal_config_t210b01[7] = { - {DSI_PAD_CONTROL_1, 0}, - {DSI_PAD_CONTROL_2, 0}, - {DSI_PAD_CONTROL_3, 0}, - {DSI_PAD_CONTROL_4, 0x77777}, +static const reg_cfg_t _di_dsi_pad_cal_config_t210b01[] = { + {DSI_PAD_CONTROL_1, 0}, + {DSI_PAD_CONTROL_2, 0}, + {DSI_PAD_CONTROL_3, 0}, + {DSI_PAD_CONTROL_4, 0x77777}, {DSI_PAD_CONTROL_5_B01, 0x77777}, - {DSI_PAD_CONTROL_6_B01, 0x1111}, + {DSI_PAD_CONTROL_6_B01, DSI_PAD_PREEMP_PD_CLK(0x1) | DSI_PAD_PREEMP_PU_CLK(0x1) | DSI_PAD_PREEMP_PD(0x01) | DSI_PAD_PREEMP_PU(0x1)}, {DSI_PAD_CONTROL_7_B01, 0} }; -//MIPI CAL config. -static const cfg_op_t _display_mipi_dsi_cal_offsets_config_t210[4] = { +// MIPI CAL config. +static const reg_cfg_t _di_mipi_dsi_cal_prod_config_t210[] = { {MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200200}, {MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200200}, {MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x200002}, {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x200002} }; -static const cfg_op_t _display_mipi_dsi_cal_offsets_config_t210b01[4] = { +static const reg_cfg_t _di_mipi_dsi_cal_prod_config_t210b01[] = { {MIPI_CAL_DSIA_MIPI_CAL_CONFIG, 0x200006}, {MIPI_CAL_DSIB_MIPI_CAL_CONFIG, 0x200006}, {MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2, 0x260000}, {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0x260000} }; -static const cfg_op_t _display_mipi_apply_dsi_cal_config[12] = { +static const reg_cfg_t _di_mipi_dsi_cal_unused_config[] = { {MIPI_CAL_CILA_MIPI_CAL_CONFIG, 0}, {MIPI_CAL_CILB_MIPI_CAL_CONFIG, 0}, {MIPI_CAL_CILC_MIPI_CAL_CONFIG, 0}, @@ -331,201 +289,88 @@ static const cfg_op_t _display_mipi_apply_dsi_cal_config[12] = { {MIPI_CAL_DSID_MIPI_CAL_CONFIG, 0}, {MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2, 0}, {MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2, 0}, - {MIPI_CAL_DSID_MIPI_CAL_CONFIG_2, 0}, - {MIPI_CAL_MIPI_CAL_CTRL, 0x2A000001} + {MIPI_CAL_DSID_MIPI_CAL_CONFIG_2, 0} }; -//Display A config. -static const cfg_op_t _display_video_disp_controller_enable_config[113] = { - {DC_CMD_STATE_ACCESS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_DV_CONTROL, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - /* Setup default YUV colorspace conversion coefficients */ - {DC_WIN_CSC_YOF, 0xF0}, - {DC_WIN_CSC_KYRGB, 0x12A}, - {DC_WIN_CSC_KUR, 0}, - {DC_WIN_CSC_KVR, 0x198}, - {DC_WIN_CSC_KUG, 0x39B}, - {DC_WIN_CSC_KVG, 0x32F}, - {DC_WIN_CSC_KUB, 0x204}, - {DC_WIN_CSC_KVB, 0}, - /* End of color coefficients */ - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, - {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, - {DC_COM_PIN_OUTPUT_POLARITY(1), 0x1000000}, - {DC_COM_PIN_OUTPUT_POLARITY(3), 0}, - {DC_DISP_BLEND_BACKGROUND_COLOR, 0}, - {DC_COM_CRC_CONTROL, 0}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WINBUF_BLEND_LAYER_CONTROL, 0x10000FF}, - {DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_STOP}, - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ}, - {DC_CMD_STATE_ACCESS, 0}, - - /* Set Display timings - * - * DC_DISP_REF_TO_SYNC: - * V_REF_TO_SYNC - 1 - * H_REF_TO_SYNC - 0 - * - * DC_DISP_SYNC_WIDTH: - * V_SYNC_WIDTH - 1 - * H_SYNC_WIDTH - 72 - * - * DC_DISP_BACK_PORCH: - * V_BACK_PORCH - 9 - * H_BACK_PORCH - 72 - * - * DC_DISP_ACTIVE: - * V_DISP_ACTIVE - 1280 - * H_DISP_ACTIVE - 720 - * - * DC_DISP_FRONT_PORCH: - * V_FRONT_PORCH - 10 - * H_FRONT_PORCH - 136 - */ - {DC_DISP_DISP_TIMING_OPTIONS, 0}, - {DC_DISP_REF_TO_SYNC, 0x10000}, - {DC_DISP_SYNC_WIDTH, 0x10048}, - {DC_DISP_BACK_PORCH, 0x90048}, - {DC_DISP_ACTIVE, 0x50002D0}, - {DC_DISP_FRONT_PORCH, 0xA0088}, // Sources say that this should happen before DC_DISP_ACTIVE cmd. +// Display A enable config. +static const reg_cfg_t _di_dc_video_enable_config[] = { + /* Set panel timings */ + {DC_DISP_DISP_TIMING_OPTIONS, VSYNC_H_POSITION(0)}, + {DC_DISP_REF_TO_SYNC, V_REF_TO_SYNC(1) | H_REF_TO_SYNC(0)}, + {DC_DISP_SYNC_WIDTH, V_SYNC_WIDTH(1) | H_SYNC_WIDTH(72)}, + {DC_DISP_BACK_PORCH, V_BACK_PORCH(9) | H_BACK_PORCH(72)}, + {DC_DISP_FRONT_PORCH, V_FRONT_PORCH(10) | H_FRONT_PORCH(136)}, + {DC_DISP_ACTIVE, V_DISP_ACTIVE(1280) | H_DISP_ACTIVE(720)}, /* End of Display timings */ {DC_DISP_SHIFT_CLOCK_OPTIONS, SC1_H_QUALIFIER_NONE | SC0_H_QUALIFIER_NONE}, {DC_COM_PIN_OUTPUT_ENABLE(1), 0}, {DC_DISP_DATA_ENABLE_OPTIONS, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL}, - {DC_DISP_DISP_INTERFACE_CONTROL, DISP_DATA_FORMAT_DF1P1C}, {DC_DISP_DISP_CLOCK_CONTROL, 0}, - {DC_CMD_DISPLAY_COMMAND_OPTION0, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, 0}, + + /* Start continuous display. */ {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_STATE_ACCESS, READ_MUX | WRITE_MUX}, - {DC_DISP_FRONT_PORCH, 0xA0088}, - {DC_CMD_STATE_ACCESS, 0}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {DC_CMD_GENERAL_INCR_SYNCPT, SYNCPT_GENERAL_COND(COND_REG_WR_SAFE) | SYNCPT_GENERAL_INDX(1)}, + {DC_CMD_GENERAL_INCR_SYNCPT, SYNCPT_GENERAL_COND(COND_REG_WR_SAFE) | SYNCPT_GENERAL_INDX(1)}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_STATE_ACCESS, 0}, - {DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)}, - {DC_DISP_DISP_COLOR_CONTROL, BASE_COLOR_SIZE_888}, - {DC_CMD_DISPLAY_COMMAND_OPTION0, 0} + + {DC_DISP_DISP_CLOCK_CONTROL, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(4)}, // 4: div3. }; -////Display A config. -static const cfg_op_t _display_video_disp_controller_disable_config[17] = { - {DC_DISP_FRONT_PORCH, 0xA0088}, +// Display A disable config. +static const reg_cfg_t _di_dc_video_disable_config[] = { {DC_CMD_INT_MASK, 0}, - {DC_CMD_STATE_ACCESS, 0}, + {DC_CMD_STATE_ACCESS, READ_MUX_ASSEMBLY | WRITE_MUX_ASSEMBLY}, {DC_CMD_INT_ENABLE, 0}, {DC_CMD_CONT_SYNCPT_VSYNC, 0}, + + /* Stop display. */ {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_STOP}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, - {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, - {DC_CMD_GENERAL_INCR_SYNCPT, 0x301}, + {DC_CMD_GENERAL_INCR_SYNCPT, SYNCPT_GENERAL_COND(COND_REG_WR_SAFE) | SYNCPT_GENERAL_INDX(1)}, + {DC_CMD_GENERAL_INCR_SYNCPT, SYNCPT_GENERAL_COND(COND_REG_WR_SAFE) | SYNCPT_GENERAL_INDX(1)}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, + // TODO: LCD panels should sleep for 40ms here. {DC_CMD_DISPLAY_POWER_CONTROL, 0}, {DC_CMD_STATE_CONTROL, GENERAL_UPDATE}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ}, }; -//DSI config. -static const cfg_op_t _display_dsi_timing_deinit_config[16] = { +// DSI deinit config. +static const reg_cfg_t _di_dsi_timing_deinit_config[] = { {DSI_POWER_CONTROL, 0}, {DSI_PAD_CONTROL_1, 0}, - {DSI_PHY_TIMING_0, 0x6070601}, + + /* DSI PHY timings */ + {DSI_PHY_TIMING_0, 0x6070603}, {DSI_PHY_TIMING_1, 0x40A0E05}, {DSI_PHY_TIMING_2, 0x30118}, - {DSI_BTA_TIMING, 0x190A14}, - {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF) }, - {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)}, + {DSI_BTA_TIMING, 0x190A14}, + /* DSI timeout */ + {DSI_TIMEOUT_0, DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(0xFFFF)}, + {DSI_TIMEOUT_1, DSI_TIMEOUT_PR(0x1343) | DSI_TIMEOUT_TA(0x2000)}, {DSI_TO_TALLY, 0}, + {DSI_HOST_CONTROL, DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC}, {DSI_CONTROL, DSI_CONTROL_LANES(3) | DSI_CONTROL_HOST_ENABLE}, {DSI_POWER_CONTROL, DSI_POWER_CONTROL_ENABLE}, - {DSI_MAX_THRESHOLD, 0x40}, + {DSI_MAX_THRESHOLD, 64}, {DSI_TRIGGER, 0}, {DSI_TX_CRC, 0}, {DSI_INIT_SEQ_CONTROL, 0} }; -//DSI config (if ver == 0x10). -static const cfg_op_t _display_deinit_config_jdi[22] = { +// DSI panel JDI deinit config. +static const reg_cfg_t _di_dsi_panel_deinit_config_jdi[] = { {DSI_WR_DATA, 0x439}, // MIPI_DSI_DCS_LONG_WRITE: 4 bytes. {DSI_WR_DATA, 0x9483FFB9}, // MIPI_DCS_PRIV_SET_EXTC. (Pass: FF 83 94). {DSI_TRIGGER, DSI_TRIGGER_HOST}, @@ -550,7 +395,8 @@ static const cfg_op_t _display_deinit_config_jdi[22] = { {DSI_TRIGGER, DSI_TRIGGER_HOST} }; -static const cfg_op_t _display_deinit_config_auo[37] = { +// DSI panel AUO deinit config. +static const reg_cfg_t _di_dsi_panel_deinit_config_auo[] = { {DSI_WR_DATA, 0x439}, // MIPI_DSI_DCS_LONG_WRITE: 4 bytes. {DSI_WR_DATA, 0x9483FFB9}, // MIPI_DCS_PRIV_SET_EXTC. (Pass: FF 83 94). {DSI_TRIGGER, DSI_TRIGGER_HOST}, @@ -591,156 +437,137 @@ static const cfg_op_t _display_deinit_config_auo[37] = { {DSI_TRIGGER, DSI_TRIGGER_HOST} }; -static const cfg_op_t _display_init_config_invert[3] = { +/* +static const reg_cfg_t _di_init_config_invert[] = { {DSI_WR_DATA, 0x239}, {DSI_WR_DATA, 0x02C1}, // INV_EN. {DSI_TRIGGER, DSI_TRIGGER_HOST}, }; +*/ -//Display A config. -static const cfg_op_t cfg_display_one_color[8] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, +// Display A Window A one color config. +static const reg_cfg_t _di_win_one_color[] = { + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT | WINDOW_B_SELECT | WINDOW_C_SELECT | WINDOW_D_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY} // Continuous display. }; -//Display A config linear pitch. -static const cfg_op_t cfg_display_framebuffer_pitch[32] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, +// Display A Window A linear pitch config. +static const reg_cfg_t _di_winA_pitch[] = { {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, {DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, // NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_WIN_WIN_OPTIONS, 0}, {DC_WIN_POSITION, 0}, //(0,0) {DC_WIN_H_INITIAL_DDA, 0}, {DC_WIN_V_INITIAL_DDA, 0}, - {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(720 * 4)}, - {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x. - {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, - {DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, // 720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. + {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(720 * 4)}, + {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x. + {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, + {DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, // 720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. {DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST}, {DC_WINBUF_SURFACE_KIND, PITCH}, {DC_WINBUF_START_ADDR, IPL_FB_ADDRESS}, // Framebuffer address. {DC_WINBUF_ADDR_H_OFFSET, 0}, {DC_WINBUF_ADDR_V_OFFSET, 0}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, {DC_WIN_WIN_OPTIONS, WIN_ENABLE}, // Enable window AD. {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, // Continuous display. - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} }; -//Display A config linear pitch inverse + Win D support. -static const cfg_op_t cfg_display_framebuffer_pitch_inv[34] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_D_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, +// Display A Window A linear pitch + Win D support config. +static const reg_cfg_t _di_winA_pitch_vic[] = { {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, {DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, // NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_WIN_WIN_OPTIONS, 0}, {DC_WIN_POSITION, 0}, //(0,0) {DC_WIN_H_INITIAL_DDA, 0}, {DC_WIN_V_INITIAL_DDA, 0}, - {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(720 * 4)}, - {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x. - {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, - {DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, // 720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. + {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(720 * 4)}, + {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x. + {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, + {DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, // 720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. + {DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST}, + {DC_WINBUF_SURFACE_KIND, PITCH}, + {DC_WINBUF_START_ADDR, NYX_FB_ADDRESS}, // Framebuffer address. + {DC_WINBUF_ADDR_H_OFFSET, 0}, + {DC_WINBUF_ADDR_V_OFFSET, 0}, + {DC_WIN_WIN_OPTIONS, WIN_ENABLE}, // Enable window AD. + {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, // Continuous display. + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} +}; + +// Display A Window A linear pitch inverse + Win D support config. +static const reg_cfg_t _di_winA_pitch_inv[] = { + {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, + {DC_WIN_WIN_OPTIONS, 0}, + {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, + {DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, // NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8. + {DC_WIN_POSITION, 0}, //(0,0) + {DC_WIN_H_INITIAL_DDA, 0}, + {DC_WIN_V_INITIAL_DDA, 0}, + {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(720 * 4)}, + {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x. + {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, + {DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(720 * 2) | LINE_STRIDE(720 * 4)}, // 720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. {DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST}, {DC_WINBUF_SURFACE_KIND, PITCH}, {DC_WINBUF_START_ADDR, NYX_FB_ADDRESS}, // Framebuffer address. {DC_WINBUF_ADDR_H_OFFSET, 0}, // Linear: 0x383FFC, Block: 0x3813FC. {DC_WINBUF_ADDR_V_OFFSET, 1279}, // Linear: 1279, Block: 0. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, {DC_WIN_WIN_OPTIONS, WIN_ENABLE | V_DIRECTION}, // Enable window AD. {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, // Continuous display. - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} }; -//Display A config block linear. -static const cfg_op_t cfg_display_framebuffer_block[34] = { - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_D_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_C_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_B_SELECT}, - {DC_WIN_WIN_OPTIONS, 0}, +// Display A Window A block linear config. +static const reg_cfg_t _di_winA_block[] = { {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_A_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, {DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, // NX Default: T_A8B8G8R8, WIN_COLOR_DEPTH_R8G8B8A8. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_WIN_WIN_OPTIONS, 0}, {DC_WIN_POSITION, 0}, //(0,0) {DC_WIN_H_INITIAL_DDA, 0}, {DC_WIN_V_INITIAL_DDA, 0}, - {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(720 * 4)}, - {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x. - {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, - {DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(1280 * 2) | LINE_STRIDE(1280 * 4)}, //720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. + {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(720 * 4)}, + {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x. + {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(720)}, + {DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(1280 * 2) | LINE_STRIDE(1280 * 4)}, //720*2x720*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. {DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST}, {DC_WINBUF_SURFACE_KIND, BLOCK_HEIGHT(4) | BLOCK}, {DC_WINBUF_START_ADDR, NYX_FB_ADDRESS}, // Framebuffer address. - {DC_WINBUF_ADDR_H_OFFSET, 0x3813FC}, // Linear: 0x383FFC, Block: 0x3813FC. + {DC_WINBUF_ADDR_H_OFFSET, 0x3813FC}, // Linear: 0x383FFC, Block: 0x3813FC. Block in HOS: 0x13FF. {DC_WINBUF_ADDR_V_OFFSET, 0}, // Linear: 1279, Block: 0. - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, - {DC_WIN_WIN_OPTIONS, 0}, - {DC_DISP_DISP_WIN_OPTIONS, DSI_ENABLE}, {DC_WIN_WIN_OPTIONS, WIN_ENABLE | SCAN_COLUMN | H_DIRECTION}, // Enable window AD. | SCAN_COLUMN | H_DIRECTION. {DC_CMD_DISPLAY_COMMAND, DISP_CTRL_MODE_C_DISPLAY}, // Continuous display. - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_A_UPDATE}, {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_A_ACT_REQ} }; -//Display D config. -static const cfg_op_t cfg_display_framebuffer_log[20] = { +// Display A Window D config. +static const reg_cfg_t _di_winD_log[] = { {DC_CMD_DISPLAY_WINDOW_HEADER, WINDOW_D_SELECT}, {DC_WIN_WIN_OPTIONS, 0}, {DC_WIN_COLOR_DEPTH, WIN_COLOR_DEPTH_B8G8R8A8}, {DC_WIN_POSITION, 0}, //(0,0) {DC_WIN_H_INITIAL_DDA, 0}, {DC_WIN_V_INITIAL_DDA, 0}, - {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(656 * 4)}, - {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x. - {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(656)}, - {DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(656 * 2) | LINE_STRIDE(656 * 4)}, //656*2x656*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. + {DC_WIN_PRESCALED_SIZE, V_PRESCALED_SIZE(1280) | H_PRESCALED_SIZE(656 * 4)}, + {DC_WIN_DDA_INC, V_DDA_INC(0x1000) | H_DDA_INC(0x1000)}, // 1.0x. + {DC_WIN_SIZE, V_SIZE(1280) | H_SIZE(656)}, + {DC_WIN_LINE_STRIDE, UV_LINE_STRIDE(656 * 2) | LINE_STRIDE(656 * 4)}, //656*2x656*4 (= 0x600 x 0xC00) bytes, see TRM for alignment requirements. {DC_WIN_BUFFER_CONTROL, BUFFER_CONTROL_HOST}, {DC_WINBUF_SURFACE_KIND, PITCH}, {DC_WINBUF_START_ADDR, LOG_FB_ADDRESS}, // Framebuffer address. {DC_WINBUF_ADDR_H_OFFSET, 0}, {DC_WINBUF_ADDR_V_OFFSET, 0}, - {DC_WINBUF_BLEND_LAYER_CONTROL, WIN_BLEND_ENABLE | WIN_K1(200)}, + {DC_WINBUF_BLEND_LAYER_CONTROL, WIN_BLEND_ENABLE | WIN_K1(200) | WIN_BLEND_DEPTH(0)}, {DC_WINBUF_BLEND_MATCH_SELECT, WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1 | WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1}, - {DC_WIN_WIN_OPTIONS, 0}, // Enable window DD. - {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_D_UPDATE}, - {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_D_ACT_REQ} + {DC_CMD_STATE_CONTROL, GENERAL_UPDATE | WIN_D_UPDATE}, + {DC_CMD_STATE_CONTROL, GENERAL_ACT_REQ | WIN_D_ACT_REQ}, }; diff --git a/bdk/display/vic.c b/bdk/display/vic.c new file mode 100644 index 0000000..1044448 --- /dev/null +++ b/bdk/display/vic.c @@ -0,0 +1,560 @@ +/* + * VIC driver for Tegra X1 + * + * Copyright (c) 2018-2024 CTCaer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +#include "vic.h" +#include +#include +#include +#include +#include +#include + +/* VIC Private registers */ +#define PVIC_FALCON_PA_OFFSET 0x1000 +#define PVIC_FALCON_ADDR 0x10AC +#define PVIC_FALCON_IDLESTATE 0x104C + +/* VIC Control and Status registers. */ +/* Fetch Control registers. */ +#define VIC_FC_COMPOSE 0x10000 +#define COMPOSE_START BIT(0) + +#define VIC_FC_CFG_STRUCT_SLOT_INDEX 0x10B00 + +#define VIC_FC_CFG_STRUCT_SLOT_CFG0 0x10B04 +#define SLOT_ENABLE BIT(0) +#define FIELD_CURRENT_ENABLE BIT(8) + +#define VIC_FC_CFG_STRUCT_SLOT_CFG2 0x10B0C +#define CACHE_WIDTH(n) ((n) << 16) +#define CACHE_WIDTH_16BX16 0 // Block Linear. +#define CACHE_WIDTH_32BX8 1 // Block Linear. Recommended for Block Linear. +#define CACHE_WIDTH_64BX4 2 // Block Linear, Pitch. Recommended for Pitch. +#define CACHE_WIDTH_128BX2 3 // Block Linear, Pitch. +#define OUTPUT_FLIP_X BIT(20) +#define OUTPUT_FLIP_Y BIT(21) +#define OUTPUT_TRANSPOSE BIT(22) + +#define VIC_FC_CFG_STRUCT_SLOT_SFC_SIZE 0x10B10 +#define VIC_FC_CFG_STRUCT_SLOT_LUMA_SIZE 0x10B14 +#define VIC_FC_CFG_STRUCT_SLOT_CHROMA_SIZE 0x10B18 +#define VIC_FC_CFG_STRUCT_SLOT_SRC_RECT_LR 0x10B1C +#define VIC_FC_CFG_STRUCT_SLOT_SRC_RECT_TB 0x10B20 +#define VIC_FC_CFG_STRUCT_SLOT_DST_RECT_LR 0x10B30 +#define VIC_FC_CFG_STRUCT_SLOT_DST_RECT_TB 0x10B34 +#define VIC_FC_CFG_STRUCT_TGT_RECT_LR 0x10B38 +#define VIC_FC_CFG_STRUCT_TGT_RECT_TB 0x10B3C +#define VIC_FC_SLOT_MAP 0x10C00 + +#define VIC_FC_FCE_CTRL 0x11000 +#define START_TRIGGER BIT(0) +#define HALT_TRIGGER BIT(1) +#define CLEAR_ERROR BIT(8) + +#define VIC_FC_FCE_UCODE_ADDR 0x11200 +#define VIC_FC_FCE_UCODE_INST 0x11300 + +/* Surface List registers. */ +#define VIC_SL_CFG_STRUCT_SLOT_INDEX 0x12100 +#define VIC_SL_CFG_STRUCT_SLOT_DST_RECT_LR 0x12200 +#define VIC_SL_CFG_STRUCT_SLOT_DST_RECT_TB 0x12300 +#define VIC_SL_CFG_STRUCT_TGT_RECT_LR 0x12400 +#define VIC_SL_CFG_STRUCT_TGT_RECT_TB 0x12500 +#define VIC_SL_CFG_STRUCT_SLOT_CFG0 0x12600 + +/* Surface Cache registers. */ +#define VIC_SC_PRAMBASE 0x14000 +#define VIC_SC_PRAMSIZE 0x14100 +#define VIC_SC_SFC0_BASE_LUMA(n) (0x14300 + (n) * 0x100) + +/* Blending Output registers. */ +#define VIC_BL_TARGET_BASADR 0x22000 +#define VIC_BL_CONFIG 0x22800 +#define SUBPARTITION_MODE BIT(0) +#define PROCESS_CFG_STRUCT_TRIGGER BIT(2) +#define SLOTMASK(n) ((n) << 8) + +#define VIC_BL_CFG_STRUCT_CFG0 0x22C00 +#define VIC_BL_CFG_STRUCT_SFC_SIZE 0x22C04 +#define VIC_BL_CFG_STRUCT_LUMA_SIZE 0x22C08 +#define VIC_BL_CFG_STRUCT_CHROMA_SIZE 0x22C0C +#define VIC_BL_CFG_STRUCT_TGT_RECT_LR 0x22C10 +#define VIC_BL_CFG_STRUCT_TGT_RECT_TB 0x22C14 + +// VIC_FC_CFG_STRUCT_SLOT_CFG2 & VIC_BL_CFG_STRUCT_CFG0. +#define BLK_KIND(n) ((n) << 8) +#define BLK_KIND_PITCH 0 +#define BLK_KIND_GENERIC_16BX2 1 +#define BLK_HEIGHT(n) ((n) << 12) +#define BLK_HEIGHT_ONE_GOB 0 +#define BLK_HEIGHT_SIXTEEN_GOBS 4 + +// Generic size macros. +#define SIZE_WIDTH(n) (((n) - 1) << 0) +#define SIZE_HEIGHT(n) (((n) - 1) << 16) +#define RECT_LEFT(n) ((n) << 0) +#define RECT_RIGHT(n) (((n) - 1) << 16) +#define RECT_TOP(n) ((n) << 0) +#define RECT_BOTTOM(n) (((n) - 1) << 16) + +#define FORMAT_PROGRESSIVE 0 +#define SOFT_CLAMP_MIN 0 +#define SOFT_CLAMP_MAX 0x3FFu +#define ALPHA_1_0 0x3FFu + +typedef struct _OutputConfig { + u64 AlphaFillMode:3; + u64 AlphaFillSlot:3; + u64 BackgroundAlpha:10; + u64 BackgroundR:10; + u64 BackgroundG:10; + u64 BackgroundB:10; + u64 RegammaMode:2; + u64 OutputFlipX:1; + u64 OutputFlipY:1; + u64 OutputTranspose:1; + u64 rsvd1:1; + u64 rsvd2:12; + u64 TargetRectLeft:14; + u64 rsvd3:2; + u64 TargetRectRight:14; + u64 rsvd4:2; + u64 TargetRectTop:14; + u64 rsvd5:2; + u64 TargetRectBottom:14; + u64 rsvd6:2; +} OutputConfig; + +typedef struct _OutputSurfaceConfig { + u64 OutPixelFormat:7; + u64 OutChromaLocHoriz:2; + u64 OutChromaLocVert:2; + u64 OutBlkKind:4; + u64 OutBlkHeight:4; + u64 rsvd0:3; + u64 rsvd1:10; + u64 OutSurfaceWidth:14; + u64 OutSurfaceHeight:14; + u64 rsvd2:4; + u64 OutLumaWidth:14; + u64 OutLumaHeight:14; + u64 rsvd3:4; + u64 OutChromaWidth:14; + u64 OutChromaHeight:14; + u64 rsvd4:4; +} OutputSurfaceConfig; + +typedef struct _SlotConfig { + u64 SlotEnable:1; + u64 DeNoise:1; + u64 AdvancedDenoise:1; + u64 CadenceDetect:1; + u64 MotionMap:1; + u64 MMapCombine:1; + u64 IsEven:1; + u64 ChromaEven:1; + u64 CurrentFieldEnable:1; + u64 PrevFieldEnable:1; + u64 NextFieldEnable:1; + u64 NextNrFieldEnable:1; + u64 CurMotionFieldEnable:1; + u64 PrevMotionFieldEnable:1; + u64 PpMotionFieldEnable:1; + u64 CombMotionFieldEnable:1; + u64 FrameFormat:4; + u64 FilterLengthY:2; + u64 FilterLengthX:2; + u64 Panoramic:12; + u64 rsvd1:22; + u64 DetailFltClamp:6; + u64 FilterNoise:10; + u64 FilterDetail:10; + u64 ChromaNoise:10; + u64 ChromaDetail:10; + u64 DeinterlaceMode:4; + u64 MotionAccumWeight:3; + u64 NoiseIir:11; + u64 LightLevel:4; + u64 rsvd4:2; + u64 SoftClampLow:10; + u64 SoftClampHigh:10; + u64 rsvd5:3; + u64 rsvd6:9; + u64 PlanarAlpha:10; + u64 ConstantAlpha:1; + u64 StereoInterleave:3; + u64 ClipEnabled:1; + u64 ClearRectMask:8; + u64 DegammaMode:2; + u64 rsvd7:1; + u64 DecompressEnable:1; + u64 rsvd9:5; + u64 DecompressCtbCount:8; + u64 DecompressZbcColor:32; + u64 rsvd12:24; + u64 SourceRectLeft:30; + u64 rsvd14:2; + u64 SourceRectRight:30; + u64 rsvd15:2; + u64 SourceRectTop:30; + u64 rsvd16:2; + u64 SourceRectBottom:30; + u64 rsvd17:2; + u64 DestRectLeft:14; + u64 rsvd18:2; + u64 DestRectRight:14; + u64 rsvd19:2; + u64 DestRectTop:14; + u64 rsvd20:2; + u64 DestRectBottom:14; + u64 rsvd21:2; + u64 rsvd22:32; + u64 rsvd23:32; +} SlotConfig; + +typedef struct _SlotSurfaceConfig { + u64 SlotPixelFormat:7; + u64 SlotChromaLocHoriz:2; + u64 SlotChromaLocVert:2; + u64 SlotBlkKind:4; + u64 SlotBlkHeight:4; + u64 SlotCacheWidth:3; + u64 rsvd0:10; + u64 SlotSurfaceWidth:14; + u64 SlotSurfaceHeight:14; + u64 rsvd1:4; + u64 SlotLumaWidth:14; + u64 SlotLumaHeight:14; + u64 rsvd2:4; + u64 SlotChromaWidth:14; + u64 SlotChromaHeight:14; + u64 rsvd3:4; +} SlotSurfaceConfig; + +typedef struct _SlotStruct { + SlotConfig slot_cfg; + SlotSurfaceConfig slot_sfc_cfg; + + // No need to configure. Reset to zeros. + u8 lumaKeyStruct[0x10]; + u8 colorMatrixStruct[0x20]; + u8 gamutMatrixStruct[0x20]; + u8 blendingSlotStruct[0x10]; +} SlotStruct; + +typedef struct _vic_config_t { + // No need to configure. Reset to zeros. + u8 pipeConfig[0x10]; + + OutputConfig out_cfg; + OutputSurfaceConfig out_sfc_cfg; + + // No need to configure. Reset to zeros. + u8 out_color_matrix[0x20]; + u8 clear_rect[0x10 * 4]; + + SlotStruct slots[8]; +} vic_config_t; + +// VIC Fetch Control Engine microcode. Dumped from L4T r33. +u8 vic_fce_ucode[] = { + 0x66, 0x00, 0x00, 0x00, 0x60, 0x07, 0x00, 0x00, 0x42, 0x40, 0x10, 0x00, 0x4E, 0x01, 0x40, 0x00, + 0x6A, 0x07, 0x00, 0x00, 0x6E, 0x23, 0x04, 0x00, 0x6C, 0x00, 0x00, 0x00, 0x4E, 0x01, 0x04, 0x00, + 0x6A, 0x0B, 0x00, 0x00, 0x6E, 0x1F, 0x04, 0x00, 0x6C, 0x00, 0x00, 0x00, 0x4E, 0x01, 0x10, 0x00, + 0x6A, 0x0F, 0x00, 0x00, 0x6E, 0x1F, 0x04, 0x00, 0x6C, 0x00, 0x00, 0x00, 0x48, 0x80, 0x02, 0x00, + 0x0E, 0x11, 0x00, 0x00, 0x6A, 0x14, 0x00, 0x00, 0x6E, 0x08, 0x06, 0x00, 0x6C, 0x00, 0x00, 0x00, + 0x4E, 0x01, 0x08, 0x00, 0x6A, 0x18, 0x00, 0x00, 0x6E, 0x26, 0x04, 0x00, 0x6C, 0x00, 0x00, 0x00, + 0x4E, 0x01, 0x20, 0x00, 0x6A, 0x1C, 0x00, 0x00, 0x6E, 0x26, 0x04, 0x00, 0x6C, 0x00, 0x00, 0x00, + 0x4E, 0x01, 0x02, 0x00, 0x6A, 0x20, 0x00, 0x00, 0x6E, 0x24, 0x00, 0x00, 0x6C, 0x00, 0x00, 0x00, + 0x56, 0x00, 0x10, 0x00, 0x56, 0x40, 0x10, 0x00, 0x22, 0x41, 0x01, 0x00, 0x6C, 0x00, 0x00, 0x00, + 0x62, 0x80, 0x01, 0x00, 0x60, 0x47, 0x00, 0x00, 0x60, 0x87, 0x00, 0x00, 0x01, 0x4A, 0x00, 0x00, + 0x55, 0xC0, 0x20, 0x00, 0x00, 0x59, 0x00, 0x00, 0x60, 0x87, 0x00, 0x00, 0x60, 0xC7, 0x00, 0x00, + 0x01, 0x93, 0x00, 0x00, 0x40, 0x82, 0x02, 0x00, 0x4E, 0x02, 0x00, 0x00, 0x6B, 0x34, 0x00, 0x00, + 0x43, 0xC1, 0x10, 0x00, 0x42, 0x02, 0x03, 0x00, 0x00, 0x23, 0x01, 0x00, 0x24, 0xD4, 0x00, 0x00, + 0x56, 0x40, 0x3D, 0x00, 0x04, 0xEB, 0x00, 0x00, 0x60, 0x07, 0x01, 0x00, 0x60, 0x47, 0x00, 0x00, + 0x6A, 0x3E, 0x00, 0x00, 0x55, 0xC0, 0x30, 0x00, 0x48, 0x00, 0x01, 0x00, 0x48, 0x40, 0x01, 0x00, + 0x48, 0x80, 0x01, 0x00, 0x6B, 0x28, 0x02, 0x00, 0x56, 0x40, 0x09, 0x00, 0x04, 0x4D, 0x01, 0x00, + 0x06, 0x4D, 0x00, 0x00, 0x42, 0xC0, 0x03, 0x00, 0x56, 0x80, 0x09, 0x00, 0x04, 0xFE, 0x01, 0x00, + 0x00, 0xF9, 0x01, 0x00, 0x4E, 0x02, 0x00, 0x00, 0x6B, 0x32, 0x02, 0x00, 0x55, 0x40, 0x2F, 0x00, + 0x56, 0x80, 0x0D, 0x00, 0x4F, 0x00, 0x00, 0x00, 0x6A, 0x0D, 0x02, 0x00, 0x55, 0x40, 0x31, 0x00, + 0x56, 0x80, 0x0B, 0x00, 0x0C, 0x2B, 0x00, 0x00, 0x6A, 0x13, 0x02, 0x00, 0x43, 0x45, 0x03, 0x00, + 0x42, 0x86, 0x03, 0x00, 0x4D, 0x06, 0x02, 0x00, 0x6A, 0x0D, 0x02, 0x00, 0x42, 0x86, 0x03, 0x00, + 0x22, 0x7E, 0x01, 0x00, 0x4E, 0x04, 0x00, 0x00, 0x6B, 0x32, 0x02, 0x00, 0x55, 0x40, 0x17, 0x00, + 0x0D, 0x2C, 0x00, 0x00, 0x56, 0xC0, 0x09, 0x00, 0x6A, 0x1E, 0x02, 0x00, 0x48, 0xC0, 0x01, 0x00, + 0x43, 0x04, 0x03, 0x00, 0x6C, 0x20, 0x02, 0x00, 0x55, 0x40, 0x19, 0x00, 0x01, 0x2C, 0x01, 0x00, + 0x65, 0x23, 0x01, 0x00, 0x42, 0x42, 0x03, 0x00, 0x00, 0x2C, 0x01, 0x00, 0x24, 0x14, 0x01, 0x00, + 0x00, 0x2C, 0x01, 0x00, 0x24, 0x14, 0x01, 0x00, 0x00, 0x3C, 0x01, 0x00, 0x42, 0x04, 0x09, 0x00, + 0x42, 0xC3, 0x02, 0x00, 0x65, 0x54, 0x01, 0x00, 0x65, 0x55, 0x01, 0x00, 0x42, 0x45, 0x0D, 0x00, + 0x62, 0x03, 0x00, 0x00, 0x62, 0x44, 0x00, 0x00, 0x62, 0x85, 0x00, 0x00, 0x62, 0xC2, 0x00, 0x00, + 0x22, 0x48, 0x1F, 0x00, 0x6F, 0x00, 0x00, 0x00, 0x48, 0x00, 0x01, 0x00, 0x6C, 0x28, 0x02, 0x00, + 0x62, 0x80, 0x01, 0x00, 0x60, 0x07, 0x00, 0x00, 0x60, 0x47, 0x00, 0x00, 0x60, 0x87, 0x00, 0x00, + 0x01, 0x01, 0x00, 0x00, 0x43, 0x00, 0x02, 0x00, 0x40, 0x00, 0x02, 0x00, 0x01, 0xCA, 0x01, 0x00, + 0x60, 0x03, 0x01, 0x00, 0x01, 0xA0, 0x01, 0x00, 0x60, 0x40, 0x00, 0x00, 0x65, 0x01, 0x00, 0x00, + 0x55, 0xC0, 0x2E, 0x00, 0x01, 0x18, 0x00, 0x00, 0x43, 0x00, 0x04, 0x00, 0x43, 0x41, 0x06, 0x00, + 0x6F, 0x00, 0x00, 0x00, 0x61, 0xC1, 0x00, 0x00, 0x61, 0x42, 0x01, 0x00, 0x65, 0xB5, 0x00, 0x00, + 0x65, 0x73, 0x01, 0x00, 0x65, 0x35, 0x01, 0x00, 0x65, 0x34, 0x01, 0x00, 0x42, 0x04, 0x0D, 0x00, + 0x01, 0x14, 0x01, 0x00, 0x42, 0x04, 0x03, 0x00, 0x00, 0x20, 0x00, 0x00, 0x43, 0x03, 0x05, 0x00, + 0x43, 0x85, 0x02, 0x00, 0x00, 0xAA, 0x00, 0x00, 0x48, 0x46, 0x01, 0x00, 0x65, 0xEB, 0x00, 0x00, + 0x00, 0x9A, 0x00, 0x00, 0x65, 0xB2, 0x01, 0x00, 0x00, 0xA6, 0x01, 0x00, 0x42, 0x86, 0x0D, 0x00, + 0x61, 0x42, 0x01, 0x00, 0x01, 0xAE, 0x01, 0x00, 0x00, 0x71, 0x00, 0x00, 0x42, 0x82, 0x08, 0x00, + 0x42, 0xC3, 0x08, 0x00, 0x48, 0x40, 0x01, 0x00, 0x6F, 0x00, 0x00, 0x00, 0x6E, 0x34, 0x02, 0x00, + 0x65, 0x79, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x6C, 0x36, 0x04, 0x00, 0x6E, 0x34, 0x02, 0x00, + 0x48, 0x7F, 0x01, 0x00, 0x6C, 0x0A, 0x06, 0x00, 0x6E, 0x34, 0x02, 0x00, 0x6E, 0x05, 0x04, 0x00, + 0x65, 0x79, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x41, 0x87, 0x03, 0x00, 0x65, 0xBA, 0x00, 0x00, + 0x65, 0xB2, 0x00, 0x00, 0x42, 0x82, 0x02, 0x00, 0x00, 0x51, 0x00, 0x00, 0x61, 0xC1, 0x00, 0x00, + 0x65, 0xFB, 0x00, 0x00, 0x65, 0xF3, 0x00, 0x00, 0x41, 0x87, 0x05, 0x00, 0x65, 0xF3, 0x00, 0x00, + 0x42, 0xC3, 0x08, 0x00, 0x00, 0x59, 0x00, 0x00, 0x60, 0xC7, 0x00, 0x00, 0x60, 0xC7, 0x00, 0x00, + 0x56, 0xC0, 0x21, 0x00, 0x04, 0xDF, 0x01, 0x00, 0x43, 0xC7, 0x15, 0x00, 0x00, 0x38, 0x00, 0x00, + 0x00, 0x79, 0x00, 0x00, 0x42, 0xC3, 0x20, 0x00, 0x43, 0xC3, 0x04, 0x00, 0x42, 0x00, 0x30, 0x00, + 0x42, 0x41, 0x30, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x4B, 0x00, 0x00, 0x60, 0xC7, 0x01, 0x00, + 0x22, 0x78, 0x01, 0x00, 0x22, 0x79, 0x03, 0x00, 0x22, 0x7F, 0x1F, 0x00, 0x6F, 0x00, 0x00, 0x00, + 0x6E, 0x34, 0x02, 0x00, 0x6E, 0x05, 0x04, 0x00, 0x4B, 0x41, 0x00, 0x00, 0x60, 0xC7, 0x01, 0x00, + 0x60, 0x87, 0x01, 0x00, 0x43, 0x86, 0x15, 0x00, 0x00, 0x30, 0x00, 0x00, 0x65, 0x39, 0x01, 0x00, + 0x42, 0x04, 0x05, 0x00, 0x4E, 0x05, 0x7E, 0x00, 0x6A, 0x1B, 0x06, 0x00, 0x55, 0xC0, 0x3D, 0x00, + 0x0A, 0x3C, 0x01, 0x00, 0x60, 0xC7, 0x01, 0x00, 0x22, 0x78, 0x01, 0x00, 0x22, 0x79, 0x03, 0x00, + 0x22, 0x7C, 0x09, 0x00, 0x22, 0x7F, 0x1F, 0x00, 0x6F, 0x00, 0x00, 0x00, 0x65, 0x7A, 0x01, 0x00, + 0x42, 0x45, 0x05, 0x00, 0x65, 0xBB, 0x01, 0x00, 0x42, 0x86, 0x05, 0x00, 0x55, 0xC0, 0x3D, 0x00, + 0x0A, 0x7D, 0x01, 0x00, 0x0A, 0xBE, 0x01, 0x00, 0x07, 0xC7, 0x01, 0x00, 0x0B, 0x7D, 0x01, 0x00, + 0x0B, 0xBE, 0x01, 0x00, 0x55, 0xC0, 0x3D, 0x00, 0x0A, 0x3C, 0x01, 0x00, 0x60, 0xC7, 0x01, 0x00, + 0x22, 0x78, 0x01, 0x00, 0x22, 0x79, 0x03, 0x00, 0x22, 0x7A, 0x05, 0x00, 0x22, 0x7B, 0x07, 0x00, + 0x22, 0x7C, 0x09, 0x00, 0x22, 0x7D, 0x0B, 0x00, 0x22, 0x7E, 0x0D, 0x00, 0x22, 0x7F, 0x1F, 0x00, + 0x6F, 0x00, 0x00, 0x00 +}; + +vic_config_t __attribute__((aligned (0x100))) vic_cfg = {0}; + +u32 _vic_read_priv(u32 addr) +{ + u32 addr_lsb = addr & 0xFF; + + // Set address LSB. + if (addr_lsb) + VIC(PVIC_FALCON_ADDR) = addr_lsb >> 2; + + // Set address. + u32 val = VIC(PVIC_FALCON_PA_OFFSET + (addr >> 6)); + + // Unset address LSB. + if (addr_lsb) + VIC(PVIC_FALCON_ADDR) = 0; + + return val; +} + +static void _vic_write_priv(u32 addr, u32 data) +{ + u32 addr_lsb = addr & 0xFF; + + // Set address LSB. + if (addr_lsb) + VIC(PVIC_FALCON_ADDR) = addr_lsb >> 2; + + // Set address. + VIC(PVIC_FALCON_PA_OFFSET + (addr >> 6)) = data; + + // Unset address LSB. + if (addr_lsb) + VIC(PVIC_FALCON_ADDR) = 0; +} + +static int _vic_wait_idle() +{ + u32 timeout_count = 15000; // 150ms. + + while (VIC(PVIC_FALCON_IDLESTATE)) + { + usleep(10); + + timeout_count--; + if (!timeout_count) + return -1; + }; + + return 0; +} + +void vic_set_surface(const vic_surface_t *sfc) +{ + u32 flip_x = 0; + u32 flip_y = 0; + u32 swap_xy = 0; + u32 const_alpha = 0; + + u32 width = sfc->width; + u32 height = sfc->height; + u32 pix_fmt = sfc->pix_fmt; + u32 src_buf = sfc->src_buf; + u32 dst_buf = sfc->dst_buf; + + // Get format alpha type. + switch (sfc->pix_fmt) + { + case VIC_PIX_FORMAT_L8: + case VIC_PIX_FORMAT_X1B5G5R5: + case VIC_PIX_FORMAT_B5G5R5X1: + case VIC_PIX_FORMAT_X8B8G8R8: + case VIC_PIX_FORMAT_X8R8G8B8: + case VIC_PIX_FORMAT_B8G8R8X8: + case VIC_PIX_FORMAT_R8G8B8X8: + const_alpha = 1; + break; + + case VIC_PIX_FORMAT_A8B8G8R8: + case VIC_PIX_FORMAT_A8R8G8B8: + case VIC_PIX_FORMAT_B8G8R8A8: + case VIC_PIX_FORMAT_R8G8B8A8: + default: + break; + } + + // Get rotation parameters. + switch (sfc->rotation) + { + case VIC_ROTATION_90: + swap_xy = 1; + break; + + case VIC_ROTATION_180: + flip_x = 1; + flip_y = 1; + break; + + case VIC_ROTATION_270: + flip_x = 1; + swap_xy = 1; + break; + + case VIC_ROTATION_0: + default: + break; + } + + // Set output surface format. + vic_cfg.out_sfc_cfg.OutPixelFormat = pix_fmt; + vic_cfg.out_sfc_cfg.OutBlkKind = BLK_KIND_PITCH; + vic_cfg.out_sfc_cfg.OutBlkHeight = 0; + + // Set output rotation/flip. + vic_cfg.out_cfg.OutputFlipX = flip_x; + vic_cfg.out_cfg.OutputFlipY = flip_y; + vic_cfg.out_cfg.OutputTranspose = swap_xy; + + // Set output surface resolution. + vic_cfg.out_sfc_cfg.OutSurfaceWidth = width - 1; + vic_cfg.out_sfc_cfg.OutSurfaceHeight = height - 1; + vic_cfg.out_sfc_cfg.OutLumaWidth = width - 1; + vic_cfg.out_sfc_cfg.OutLumaHeight = height - 1; + + // Set output destination rectangle. Anything outside will not be touched at output buffer. + vic_cfg.out_cfg.TargetRectLeft = 0; + vic_cfg.out_cfg.TargetRectRight = width - 1; + vic_cfg.out_cfg.TargetRectTop = 0; + vic_cfg.out_cfg.TargetRectBottom = height - 1; + + // Initialize slot parameters. + vic_cfg.slots[0].slot_cfg.SlotEnable = 1; + vic_cfg.slots[0].slot_cfg.SoftClampLow = SOFT_CLAMP_MIN; + vic_cfg.slots[0].slot_cfg.SoftClampHigh = SOFT_CLAMP_MAX; + vic_cfg.slots[0].slot_cfg.PlanarAlpha = ALPHA_1_0; + vic_cfg.slots[0].slot_cfg.ConstantAlpha = const_alpha; + vic_cfg.slots[0].slot_cfg.FrameFormat = FORMAT_PROGRESSIVE; + + // Set input source rectangle. + vic_cfg.slots[0].slot_cfg.SourceRectLeft = 0; + vic_cfg.slots[0].slot_cfg.SourceRectRight = (width - 1) << 16; + vic_cfg.slots[0].slot_cfg.SourceRectTop = 0; + vic_cfg.slots[0].slot_cfg.SourceRectBottom = (height - 1) << 16; + + // Set input destination rectangle. + vic_cfg.slots[0].slot_cfg.DestRectLeft = 0; + vic_cfg.slots[0].slot_cfg.DestRectRight = (width - 1); + vic_cfg.slots[0].slot_cfg.DestRectTop = 0; + vic_cfg.slots[0].slot_cfg.DestRectBottom = (height - 1); + + // Set input surface format. + vic_cfg.slots[0].slot_sfc_cfg.SlotPixelFormat = pix_fmt; + vic_cfg.slots[0].slot_sfc_cfg.SlotBlkKind = BLK_KIND_PITCH; + vic_cfg.slots[0].slot_sfc_cfg.SlotBlkHeight = 0; + vic_cfg.slots[0].slot_sfc_cfg.SlotCacheWidth = CACHE_WIDTH_64BX4; + + // Set input surface resolution. + vic_cfg.slots[0].slot_sfc_cfg.SlotSurfaceWidth = width - 1; + vic_cfg.slots[0].slot_sfc_cfg.SlotSurfaceHeight = height - 1; + vic_cfg.slots[0].slot_sfc_cfg.SlotLumaWidth = width - 1; + vic_cfg.slots[0].slot_sfc_cfg.SlotLumaHeight = height - 1; + + // Flush data. + bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLEAN_WAY, false); + + // Set parameters base and size. Causes a parse by surface cache. + _vic_write_priv(VIC_SC_PRAMBASE, (u32)&vic_cfg >> 8); + _vic_write_priv(VIC_SC_PRAMSIZE, sizeof(vic_config_t) >> 6); + + // Wait for surface cache to get ready. + _vic_wait_idle(); + + // Set slot mapping. + _vic_write_priv(VIC_FC_SLOT_MAP, 0xFFFFFFF0); + + // Set input surface buffer. + _vic_write_priv(VIC_SC_SFC0_BASE_LUMA(0), src_buf >> 8); + + // Set output surface buffer. + _vic_write_priv(VIC_BL_TARGET_BASADR, dst_buf >> 8); + + // Set blending config and push changes to surface cache. + _vic_write_priv(VIC_BL_CONFIG, SLOTMASK(0x1F) | PROCESS_CFG_STRUCT_TRIGGER | SUBPARTITION_MODE); + + // Wait for surface cache to get ready. + _vic_wait_idle(); +} + +int vic_compose() +{ + // Wait for surface cache to get ready. Otherwise VIC will hang. + int res = _vic_wait_idle(); + + // Start composition of a single frame. + _vic_write_priv(VIC_FC_COMPOSE, COMPOSE_START); + + return res; +} + +int vic_init() +{ + clock_enable_vic(); + + // Load Fetch Control Engine microcode. + for (u32 i = 0; i < sizeof(vic_fce_ucode) / sizeof(u32); i++) + { + _vic_write_priv(VIC_FC_FCE_UCODE_ADDR, (i * sizeof(u32))); + _vic_write_priv(VIC_FC_FCE_UCODE_INST, *(u32 *)&vic_fce_ucode[i * sizeof(u32)]); + } + + // Start Fetch Control Engine. + _vic_write_priv(VIC_FC_FCE_CTRL, START_TRIGGER); + + return _vic_wait_idle(); +} + +void vic_end() +{ + clock_disable_vic(); +} diff --git a/bdk/display/vic.h b/bdk/display/vic.h new file mode 100644 index 0000000..20fbe6c --- /dev/null +++ b/bdk/display/vic.h @@ -0,0 +1,66 @@ +/* + * VIC driver for Tegra X1 + * + * Copyright (c) 2018-2019 CTCaer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef _VIC_H_ +#define _VIC_H_ + +#include + +#define VIC_THI_SLCG_OVERRIDE_LOW_A 0x8C + +typedef enum _vic_rotation_t +{ + VIC_ROTATION_0 = 0, + VIC_ROTATION_90 = 1, + VIC_ROTATION_180 = 2, + VIC_ROTATION_270 = 3, +} vic_rotation_t; + +typedef enum _vic_pix_format_t +{ + VIC_PIX_FORMAT_L8 = 1, // 8-bit LUT. + VIC_PIX_FORMAT_X1B5G5R5 = 21, // 16-bit XBGR. + VIC_PIX_FORMAT_B5G5R5X1 = 23, // 16-bit BGRX. + + VIC_PIX_FORMAT_A8B8G8R8 = 31, // 32-bit ABGR. + VIC_PIX_FORMAT_A8R8G8B8 = 32, // 32-bit ARGB. + VIC_PIX_FORMAT_B8G8R8A8 = 33, // 32-bit BGRA. + VIC_PIX_FORMAT_R8G8B8A8 = 34, // 32-bit RGBA. + + VIC_PIX_FORMAT_X8B8G8R8 = 35, // 32-bit XBGR. + VIC_PIX_FORMAT_X8R8G8B8 = 36, // 32-bit XRGB. + VIC_PIX_FORMAT_B8G8R8X8 = 37, // 32-bit BGRX. + VIC_PIX_FORMAT_R8G8B8X8 = 38, // 32-bit RGBX. +} vic_pix_format_t; + +typedef struct _vic_surface_t +{ + u32 src_buf; + u32 dst_buf; + u32 width; + u32 height; + u32 pix_fmt; + u32 rotation; +} vic_surface_t; + +void vic_set_surface(const vic_surface_t *sfc); +int vic_compose(); +int vic_init(); +void vic_end(); + +#endif diff --git a/bdk/exception_handlers.S b/bdk/exception_handlers.S index 97d1ec6..2f38bb3 100644 --- a/bdk/exception_handlers.S +++ b/bdk/exception_handlers.S @@ -97,6 +97,10 @@ _irq_setup: MSR CPSR, #(MODE_IRQ | IRQ | FIQ) /* IRQ mode, IRQ/FIQ disabled */ LDR SP, =0x40040000 + /* Setup FIQ stack pointer */ + MSR CPSR, #(MODE_FIQ | IRQ | FIQ) /* FIQ mode, IRQ/FIQ disabled */ + LDR SP, =0x40040000 + /* Setup SYS stack pointer */ MSR CPSR, #(MODE_SYS | IRQ | FIQ) /* SYSTEM mode, IRQ/FIQ disabled */ LDR SP, =0x4003FF00 /* Will be changed later to DRAM */ @@ -111,7 +115,9 @@ _irq_setup: B ipl_main B . -_reset: +.globl excp_reset +.type excp_reset, %function +excp_reset: LDR R0, =EXCP_EN_ADDR LDR R1, =0x30505645 /* EVP0 */ STR R1, [R0] /* EVP0 in EXCP_EN_ADDR */ @@ -129,25 +135,25 @@ _reset_handler: LDR R0, =EXCP_TYPE_ADDR LDR R1, =0x545352 /* RST */ STR R1, [R0] /* RST in EXCP_TYPE_ADDR */ - B _reset + B excp_reset _undefined_handler: LDR R0, =EXCP_TYPE_ADDR LDR R1, =0x464455 /* UDF */ STR R1, [R0] /* UDF in EXCP_TYPE_ADDR */ - B _reset + B excp_reset _prefetch_abort_handler: LDR R0, =EXCP_TYPE_ADDR LDR R1, =0x54424150 /* PABT */ STR R1, [R0] /* PABT in EXCP_TYPE_ADDR */ - B _reset + B excp_reset _data_abort_handler: LDR R0, =EXCP_TYPE_ADDR LDR R1, =0x54424144 /* DABT */ STR R1, [R0] /* DABT in EXCP_TYPE_ADDR */ - B _reset + B excp_reset .globl irq_enable_cpu_irq_exceptions .type irq_enable_cpu_irq_exceptions, %function diff --git a/bdk/fatfs_cfg.h b/bdk/fatfs_cfg.h index a12585f..77b26dd 100644 --- a/bdk/fatfs_cfg.h +++ b/bdk/fatfs_cfg.h @@ -17,8 +17,12 @@ #ifndef _FATFS_CFG_H_ #define _FATFS_CFG_H_ +// define FFCFG_INC in a project to use a specific FatFS configuration. +// Example: FFCFG_INC := '"../$(PROJECT_DIR)/libs/fatfs/ffconf.h"' #ifdef FFCFG_INC #include FFCFG_INC +#else +#include "fatfs_conf.h" #endif #endif diff --git a/bdk/fatfs_conf.h b/bdk/fatfs_conf.h new file mode 100644 index 0000000..e87219d --- /dev/null +++ b/bdk/fatfs_conf.h @@ -0,0 +1,305 @@ +/*---------------------------------------------------------------------------/ +/ FatFs Functional Configurations +/---------------------------------------------------------------------------*/ + +#define FFCONF_DEF 86604 /* Revision ID */ + +/*---------------------------------------------------------------------------/ +/ Function Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_READONLY 0 +/* This option switches read-only configuration. (0:Read/Write or 1:Read-only) +/ Read-only configuration removes writing API functions, f_write(), f_sync(), +/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree() +/ and optional writing functions as well. */ + + +#define FF_FS_MINIMIZE 0 +/* This option defines minimization level to remove some basic API functions. +/ +/ 0: Basic functions are fully enabled. +/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename() +/ are removed. +/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. +/ 3: f_lseek() function is removed in addition to 2. */ + + +#define FF_USE_STRFUNC 2 +/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf(). +/ +/ 0: Disable string functions. +/ 1: Enable without LF-CRLF conversion. +/ 2: Enable with LF-CRLF conversion. */ + + +#define FF_USE_FIND 1 +/* This option switches filtered directory read functions, f_findfirst() and +/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */ + + +#define FF_USE_MKFS 0 +/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */ + +#if FF_USE_MKFS +#define FF_MKFS_LABEL "SWITCH SD " +#endif +/* This sets FAT/FAT32 label. Exactly 11 characters, all caps. */ + + +#define FF_USE_FASTSEEK 0 +/* This option switches fast seek function. (0:Disable or 1:Enable) */ + +#define FF_FASTFS 0 +#if FF_FASTFS +#undef FF_USE_FASTSEEK +#define FF_USE_FASTSEEK 1 +#endif +/* This option switches fast access to chained clusters. (0:Disable or 1:Enable) */ + + +#define FF_SIMPLE_GPT 1 +/* This option switches support for the first GPT partition. (0:Disable or 1:Enable) */ + + +#define FF_USE_EXPAND 0 +/* This option switches f_expand function. (0:Disable or 1:Enable) */ + + +#define FF_USE_CHMOD 1 +/* This option switches attribute manipulation functions, f_chmod() and f_utime(). +/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */ + + +#define FF_USE_LABEL 0 +/* This option switches volume label functions, f_getlabel() and f_setlabel(). +/ (0:Disable or 1:Enable) */ + + +#define FF_USE_FORWARD 0 +/* This option switches f_forward() function. (0:Disable or 1:Enable) */ + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/---------------------------------------------------------------------------*/ + +#define FF_CODE_PAGE 850 +/* This option specifies the OEM code page to be used on the target system. +/ Incorrect code page setting can cause a file open failure. +/ +/ 437 - U.S. +/ 720 - Arabic +/ 737 - Greek +/ 771 - KBL +/ 775 - Baltic +/ 850 - Latin 1 +/ 852 - Latin 2 +/ 855 - Cyrillic +/ 857 - Turkish +/ 860 - Portuguese +/ 861 - Icelandic +/ 862 - Hebrew +/ 863 - Canadian French +/ 864 - Arabic +/ 865 - Nordic +/ 866 - Russian +/ 869 - Greek 2 +/ 932 - Japanese (DBCS) +/ 936 - Simplified Chinese (DBCS) +/ 949 - Korean (DBCS) +/ 950 - Traditional Chinese (DBCS) +/ 0 - Include all code pages above and configured by f_setcp() +*/ + + +#define FF_USE_LFN 3 +#define FF_MAX_LFN 255 +/* The FF_USE_LFN switches the support for LFN (long file name). +/ +/ 0: Disable LFN. FF_MAX_LFN has no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function +/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and +/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled. +/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can +/ be in range of 12 to 255. It is recommended to be set 255 to fully support LFN +/ specification. +/ When use stack for the working buffer, take care on stack overflow. When use heap +/ memory for the working buffer, memory management functions, ff_memalloc() and +/ ff_memfree() in ffsystem.c, need to be added to the project. */ + + +#define FF_LFN_UNICODE 0 +/* This option switches the character encoding on the API when LFN is enabled. +/ +/ 0: ANSI/OEM in current CP (TCHAR = char) +/ 1: Unicode in UTF-16 (TCHAR = WCHAR) +/ 2: Unicode in UTF-8 (TCHAR = char) +/ 3: Unicode in UTF-32 (TCHAR = DWORD) +/ +/ Also behavior of string I/O functions will be affected by this option. +/ When LFN is not enabled, this option has no effect. */ + + +#define FF_LFN_BUF 255 +#define FF_SFN_BUF 12 +/* This set of options defines size of file name members in the FILINFO structure +/ which is used to read out directory items. These values should be suffcient for +/ the file names to read. The maximum possible length of the read file name depends +/ on character encoding. When LFN is not enabled, these options have no effect. */ + + +#define FF_STRF_ENCODE 0 +/* When FF_LFN_UNICODE >= 1 with LFN enabled, string I/O functions, f_gets(), +/ f_putc(), f_puts and f_printf() convert the character encoding in it. +/ This option selects assumption of character encoding ON THE FILE to be +/ read/written via those functions. +/ +/ 0: ANSI/OEM in current CP +/ 1: Unicode in UTF-16LE +/ 2: Unicode in UTF-16BE +/ 3: Unicode in UTF-8 +*/ + + +#define FF_FS_RPATH 0 +/* This option configures support for relative path. +/ +/ 0: Disable relative path and remove related functions. +/ 1: Enable relative path. f_chdir() and f_chdrive() are available. +/ 2: f_getcwd() function is available in addition to 1. +*/ + + +/*---------------------------------------------------------------------------/ +/ Drive/Volume Configurations +/---------------------------------------------------------------------------*/ + +#define FF_VOLUMES 1 +/* Number of volumes (logical drives) to be used. (1-10) */ + + +#define FF_STR_VOLUME_ID 0 +#define FF_VOLUME_STRS "sd" +/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings. +/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive +/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each +/ logical drives. Number of items must not be less than FF_VOLUMES. Valid +/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are +/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is +/ not defined, a user defined volume string table needs to be defined as: +/ +/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",... +/ Order is important. Any change to order, must also be reflected to diskio drive enum. +*/ + + +#define FF_MULTI_PARTITION 0 +/* This option switches support for multiple volumes on the physical drive. +/ By default (0), each logical drive number is bound to the same physical drive +/ number and only an FAT volume found on the physical drive will be mounted. +/ When this function is enabled (1), each logical drive number can be bound to +/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk() +/ funciton will be available. */ + + +#define FF_MIN_SS 512 +#define FF_MAX_SS 512 +/* This set of options configures the range of sector size to be supported. (512, +/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and +/ harddisk. But a larger value may be required for on-board flash memory and some +/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured +/ for variable sector size mode and disk_ioctl() function needs to implement +/ GET_SECTOR_SIZE command. */ + + +#define FF_USE_TRIM 0 +/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable) +/ To enable Trim function, also CTRL_TRIM command should be implemented to the +/ disk_ioctl() function. */ + + +#define FF_FS_NOFSINFO 1 +/* If you need to know correct free space on the FAT32 volume, set bit 0 of this +/ option, and f_getfree() function at first time after volume mount will force +/ a full FAT scan. Bit 1 controls the use of last allocated cluster number. +/ +/ bit0=0: Use free cluster count in the FSINFO if available. +/ bit0=1: Do not trust free cluster count in the FSINFO. +/ bit1=0: Use last allocated cluster number in the FSINFO if available. +/ bit1=1: Do not trust last allocated cluster number in the FSINFO. +*/ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/---------------------------------------------------------------------------*/ + +#define FF_FS_TINY 0 +/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny) +/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes. +/ Instead of private sector buffer eliminated from the file object, common sector +/ buffer in the filesystem object (FATFS) is used for the file data transfer. */ + + +#define FF_FS_EXFAT 1 +/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable) +/ To enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1) +/ Note that enabling exFAT discards ANSI C (C89) compatibility. */ + + +#define FF_FS_NORTC 1 +#define FF_NORTC_MON 1 +#define FF_NORTC_MDAY 1 +#define FF_NORTC_YEAR 2022 +/* The option FF_FS_NORTC switches timestamp function. If the system does not have +/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable +/ the timestamp function. Every object modified by FatFs will have a fixed timestamp +/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time. +/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be +/ added to the project to read current time form real-time clock. FF_NORTC_MON, +/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect. +/ These options have no effect at read-only configuration (FF_FS_READONLY = 1). */ + + +#define FF_FS_LOCK 0 +/* The option FF_FS_LOCK switches file lock function to control duplicated file open +/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY +/ is 1. +/ +/ 0: Disable file lock function. To avoid volume corruption, application program +/ should avoid illegal open, remove and rename to the open objects. +/ >0: Enable file lock function. The value defines how many files/sub-directories +/ can be opened simultaneously under file lock control. Note that the file +/ lock control is independent of re-entrancy. */ + + +/* #include // O/S definitions */ +#define FF_FS_REENTRANT 0 +#define FF_FS_TIMEOUT 1000 +#define FF_SYNC_t HANDLE +/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs +/ module itself. Note that regardless of this option, file access to different +/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs() +/ and f_fdisk() function, are always not re-entrant. Only file/directory access +/ to the same volume is under control of this function. +/ +/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect. +/ 1: Enable re-entrancy. Also user provided synchronization handlers, +/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() +/ function, must be added to the project. Samples are available in +/ option/syscall.c. +/ +/ The FF_FS_TIMEOUT defines timeout period in unit of time tick. +/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*, +/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be +/ included somewhere in the scope of ff.h. */ + + + +/*--- End of configuration options ---*/ diff --git a/bdk/ianos/elfload/elf.h b/bdk/ianos/elfload/elf.h index 196cf87..2a7111e 100644 --- a/bdk/ianos/elfload/elf.h +++ b/bdk/ianos/elfload/elf.h @@ -29,33 +29,34 @@ #ifndef ELF_H #define ELF_H -#include -typedef uint8_t Elf_Byte; +#include -typedef uint32_t Elf32_Addr; /* Unsigned program address */ -typedef uint32_t Elf32_Off; /* Unsigned file offset */ -typedef int32_t Elf32_Sword; /* Signed large integer */ -typedef uint32_t Elf32_Word; /* Unsigned large integer */ -typedef uint16_t Elf32_Half; /* Unsigned medium integer */ +typedef u8 Elf_Byte; -typedef uint64_t Elf64_Addr; -typedef uint64_t Elf64_Off; -typedef int32_t Elf64_Shalf; +typedef u32 Elf32_Addr; /* Unsigned program address */ +typedef u32 Elf32_Off; /* Unsigned file offset */ +typedef s32 Elf32_Sword; /* Signed large integer */ +typedef u32 Elf32_Word; /* Unsigned large integer */ +typedef u16 Elf32_Half; /* Unsigned medium integer */ + +typedef u64 Elf64_Addr; +typedef u64 Elf64_Off; +typedef s32 Elf64_Shalf; #ifdef __alpha__ -typedef int64_t Elf64_Sword; -typedef uint64_t Elf64_Word; +typedef s64 Elf64_Sword; +typedef u64 Elf64_Word; #else -typedef int32_t Elf64_Sword; -typedef uint32_t Elf64_Word; +typedef s32 Elf64_Sword; +typedef u32 Elf64_Word; #endif -typedef int64_t Elf64_Sxword; -typedef uint64_t Elf64_Xword; +typedef s64 Elf64_Sxword; +typedef u64 Elf64_Xword; -typedef uint32_t Elf64_Half; -typedef uint16_t Elf64_Quarter; +typedef u32 Elf64_Half; +typedef u16 Elf64_Quarter; /* * e_ident[] identification indexes @@ -376,7 +377,7 @@ typedef struct #define ELF64_R_SYM(info) ((info) >> 32) #define ELF64_R_TYPE(info) ((info)&0xFFFFFFFF) -#define ELF64_R_INFO(s, t) (((s) << 32) + (__uint32_t)(t)) +#define ELF64_R_INFO(s, t) (((s) << 32) + (u32)(t)) #if defined(__mips64__) && defined(__MIPSEL__) /* @@ -389,7 +390,7 @@ typedef struct #undef ELF64_R_INFO #define ELF64_R_TYPE(info) (swap32((info) >> 32)) #define ELF64_R_SYM(info) ((info)&0xFFFFFFFF) -#define ELF64_R_INFO(s, t) (((__uint64_t)swap32(t) << 32) + (__uint32_t)(s)) +#define ELF64_R_INFO(s, t) (((u64)swap32(t) << 32) + (u32)(s)) #endif /* __mips64__ && __MIPSEL__ */ /* Program Header */ @@ -444,7 +445,7 @@ typedef struct /* Dynamic structure */ typedef struct { - Elf32_Sword d_tag; /* controls meaning of d_val */ + Elf32_Word d_tag; /* controls meaning of d_val */ union { Elf32_Word d_val; /* Multiple meanings - see d_tag */ Elf32_Addr d_ptr; /* program virtual address */ diff --git a/bdk/ianos/elfload/elfload.c b/bdk/ianos/elfload/elfload.c index 16f8200..daf561a 100644 --- a/bdk/ianos/elfload/elfload.c +++ b/bdk/ianos/elfload/elfload.c @@ -25,7 +25,7 @@ el_status el_pread(el_ctx *ctx, void *def, size_t nb, size_t offset) } #define EL_PHOFF(ctx, num) (((ctx)->ehdr.e_phoff + (num) *(ctx)->ehdr.e_phentsize)) -el_status el_findphdr(el_ctx *ctx, Elf_Phdr *phdr, uint32_t type, unsigned *i) +el_status el_findphdr(el_ctx *ctx, Elf_Phdr *phdr, u32 type, unsigned *i) { el_status rv = EL_OK; for (; *i < ctx->ehdr.e_phnum; (*i)++) @@ -44,7 +44,7 @@ el_status el_findphdr(el_ctx *ctx, Elf_Phdr *phdr, uint32_t type, unsigned *i) } #define EL_SHOFF(ctx, num) (((ctx)->ehdr.e_shoff + (num) *(ctx)->ehdr.e_shentsize)) -el_status el_findshdr(el_ctx *ctx, Elf_Shdr *shdr, uint32_t type, unsigned *i) +el_status el_findshdr(el_ctx *ctx, Elf_Shdr *shdr, u32 type, unsigned *i) { el_status rv = EL_OK; @@ -213,7 +213,7 @@ el_status el_load(el_ctx *ctx, el_alloc_cb alloc) return rv; } -el_status el_finddyn(el_ctx *ctx, Elf_Dyn *dyn, uint32_t tag) +el_status el_finddyn(el_ctx *ctx, Elf_Dyn *dyn, u32 tag) { el_status rv = EL_OK; size_t ndyn = ctx->dynsize / sizeof(Elf_Dyn); @@ -231,7 +231,7 @@ el_status el_finddyn(el_ctx *ctx, Elf_Dyn *dyn, uint32_t tag) return EL_OK; } -el_status el_findrelocs(el_ctx *ctx, el_relocinfo *ri, uint32_t type) +el_status el_findrelocs(el_ctx *ctx, el_relocinfo *ri, u32 type) { el_status rv = EL_OK; diff --git a/bdk/ianos/elfload/elfload.h b/bdk/ianos/elfload/elfload.h index 2b9bb67..0a73e05 100644 --- a/bdk/ianos/elfload/elfload.h +++ b/bdk/ianos/elfload/elfload.h @@ -22,8 +22,6 @@ #include "elfarch.h" #include "elf.h" -#include - #ifdef DEBUG #include #define EL_DEBUG(format, ...) \ @@ -100,7 +98,7 @@ el_status el_load(el_ctx *ctx, el_alloc_cb alloccb); * If the end of the phdrs table was reached, *i is set to -1 and the contents * of *phdr are undefined */ -el_status el_findphdr(el_ctx *ctx, Elf_Phdr *phdr, uint32_t type, unsigned *i); +el_status el_findphdr(el_ctx *ctx, Elf_Phdr *phdr, u32 type, unsigned *i); /* Relocate the loaded executable */ el_status el_relocate(el_ctx *ctx); @@ -108,7 +106,7 @@ el_status el_relocate(el_ctx *ctx); /* find a dynamic table entry * returns the entry on success, dyn->d_tag = DT_NULL on failure */ -el_status el_finddyn(el_ctx *ctx, Elf_Dyn *dyn, uint32_t type); +el_status el_finddyn(el_ctx *ctx, Elf_Dyn *dyn, u32 type); typedef struct { @@ -122,6 +120,6 @@ typedef struct * pass DT_REL or DT_RELA for type * sets ri->entrysize = 0 if not found */ -el_status el_findrelocs(el_ctx *ctx, el_relocinfo *ri, uint32_t type); +el_status el_findrelocs(el_ctx *ctx, el_relocinfo *ri, u32 type); #endif diff --git a/bdk/ianos/elfload/elfreloc_aarch64.c b/bdk/ianos/elfload/elfreloc_aarch64.c index bbb0ce4..736ad46 100644 --- a/bdk/ianos/elfload/elfreloc_aarch64.c +++ b/bdk/ianos/elfload/elfreloc_aarch64.c @@ -23,9 +23,9 @@ el_status el_applyrela(el_ctx *ctx, Elf_RelA *rel) { - uintptr_t *p = (uintptr_t *)(rel->r_offset + ctx->base_load_paddr); - uint32_t type = ELF_R_TYPE(rel->r_info); - uint32_t sym = ELF_R_SYM(rel->r_info); + uptr *p = (uptr *)(rel->r_offset + ctx->base_load_paddr); + u32 type = ELF_R_TYPE(rel->r_info); + u32 sym = ELF_R_SYM(rel->r_info); switch (type) { @@ -53,9 +53,9 @@ el_status el_applyrela(el_ctx *ctx, Elf_RelA *rel) el_status el_applyrel(el_ctx *ctx, Elf_Rel *rel) { - uintptr_t *p = (uintptr_t *)(rel->r_offset + ctx->base_load_paddr); - uint32_t type = ELF_R_TYPE(rel->r_info); - uint32_t sym = ELF_R_SYM(rel->r_info); + uptr *p = (uptr *)(rel->r_offset + ctx->base_load_paddr); + u32 type = ELF_R_TYPE(rel->r_info); + u32 sym = ELF_R_SYM(rel->r_info); switch (type) { diff --git a/bdk/ianos/elfload/elfreloc_arm.c b/bdk/ianos/elfload/elfreloc_arm.c index 8b905cb..77ce654 100644 --- a/bdk/ianos/elfload/elfreloc_arm.c +++ b/bdk/ianos/elfload/elfreloc_arm.c @@ -20,9 +20,9 @@ el_status el_applyrel(el_ctx *ctx, Elf_Rel *rel) { - uint32_t sym = ELF_R_SYM(rel->r_info); // Symbol offset - uint32_t type = ELF_R_TYPE(rel->r_info); // Relocation Type - uintptr_t *p = (uintptr_t *)(rel->r_offset + ctx->base_load_paddr); // Target Addr + u32 sym = ELF_R_SYM(rel->r_info); // Symbol offset + u32 type = ELF_R_TYPE(rel->r_info); // Relocation Type + uptr *p = (uptr *)(rel->r_offset + ctx->base_load_paddr); // Target Addr #if 0 // For later symbol usage Elf32_Sym *elfSym; diff --git a/bdk/ianos/ianos.c b/bdk/ianos/ianos.c index 8deca45..99a996d 100644 --- a/bdk/ianos/ianos.c +++ b/bdk/ianos/ianos.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include @@ -74,19 +74,16 @@ uintptr_t ianos_loader(char *path, elfType_t type, void *moduleConfig) el_ctx ctx; uintptr_t epaddr = 0; - if (!sd_mount()) - goto elfLoadFinalOut; - // Read library. fileBuf = sd_file_read(path, NULL); if (!fileBuf) - goto elfLoadFinalOut; + goto out; ctx.pread = _ianos_read_cb; if (el_init(&ctx)) - goto elfLoadFinalOut; + goto out; // Set our relocated library's buffer. switch (type & 0xFFFF) @@ -100,15 +97,15 @@ uintptr_t ianos_loader(char *path, elfType_t type, void *moduleConfig) } if (!elfBuf) - goto elfLoadFinalOut; + goto out; // Load and relocate library. ctx.base_load_vaddr = ctx.base_load_paddr = (uintptr_t)elfBuf; if (el_load(&ctx, _ianos_alloc_cb)) - goto elfFreeOut; + goto out_free; if (el_relocate(&ctx)) - goto elfFreeOut; + goto out_free; // Launch. epaddr = ctx.ehdr.e_entry + (uintptr_t)elfBuf; @@ -116,11 +113,11 @@ uintptr_t ianos_loader(char *path, elfType_t type, void *moduleConfig) _ianos_call_ep(ep, moduleConfig); -elfFreeOut: +out_free: free(fileBuf); elfBuf = NULL; fileBuf = NULL; -elfLoadFinalOut: +out: return epaddr; } \ No newline at end of file diff --git a/bdk/input/als.c b/bdk/input/als.c index be55426..277f0d5 100644 --- a/bdk/input/als.c +++ b/bdk/input/als.c @@ -45,7 +45,7 @@ typedef struct _opt_win_cal_t } opt_win_cal_t; // Nintendo Switch Icosa/Iowa Optical Window calibration. -const opt_win_cal_t opt_win_cal_default[] = { +static const opt_win_cal_t opt_win_cal_default[] = { { 500, 5002, 7502 }, { 754, 2250, 2000 }, { 1029, 1999, 1667 }, @@ -54,14 +54,14 @@ const opt_win_cal_t opt_win_cal_default[] = { }; // Nintendo Switch Aula Optical Window calibration. -const opt_win_cal_t opt_win_cal_aula[] = { +static const opt_win_cal_t opt_win_cal_aula[] = { { 231, 9697, 30300 }, { 993, 3333, 2778 }, { 1478, 1621, 1053 }, { 7500, 81, 10 } }; -const u32 als_gain_idx_tbl[4] = { 1, 2, 64, 128 }; +static const u32 als_gain_idx_tbl[4] = { 1, 2, 64, 128 }; void set_als_cfg(als_ctxt_t *als_ctxt, u8 gain, u8 cycle) { @@ -70,10 +70,8 @@ void set_als_cfg(als_ctxt_t *als_ctxt, u8 gain, u8 cycle) if (!cycle) cycle = 1; - else if (cycle > 255) - cycle = 255; - i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_GAIN_REG), gain); + i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_GAIN_REG), gain); i2c_send_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_TIMING_REG), (256 - cycle)); als_ctxt->gain = gain; @@ -83,25 +81,25 @@ void set_als_cfg(als_ctxt_t *als_ctxt, u8 gain, u8 cycle) void get_als_lux(als_ctxt_t *als_ctxt) { u32 data[2]; - u32 visible_light; + u32 vi_light; u32 ir_light; u64 lux = 0; u32 itime_us = BH1730_ITIME_CYCLE_TO_US * als_ctxt->cycle; // Get visible and ir light raw data. Mode is continuous so waiting for new values doesn't matter. data[0] = i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA0LOW_REG)) + - (i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA0HIGH_REG)) << 8); + (i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA0HIGH_REG)) << 8); data[1] = i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA1LOW_REG)) + - (i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA1HIGH_REG)) << 8); + (i2c_recv_byte(I2C_2, BH1730_I2C_ADDR, BH1730_ADDR(BH1730_DATA1HIGH_REG)) << 8); - visible_light = data[0]; + vi_light = data[0]; ir_light = data[1]; - als_ctxt->over_limit = visible_light > 65534 || ir_light > 65534; - als_ctxt->vi_light = visible_light; + als_ctxt->vi_light = vi_light; als_ctxt->ir_light = ir_light; + als_ctxt->over_limit = vi_light > 65534 || ir_light > 65534; - if (!visible_light) + if (!vi_light) { als_ctxt->lux = 0; @@ -116,7 +114,7 @@ void get_als_lux(als_ctxt_t *als_ctxt) // Apply optical window calibration coefficients. for (u32 i = 0; i < opt_win_cal_count; i++) { - if (1000 * ir_light / visible_light < opt_win_cal[i].rc) + if (1000 * ir_light / vi_light < opt_win_cal[i].rc) { lux = ((u64)opt_win_cal[i].cv * data[0]) - (opt_win_cal[i].ci * data[1]); break; diff --git a/bdk/input/joycon.c b/bdk/input/joycon.c index 825e347..5e3243e 100644 --- a/bdk/input/joycon.c +++ b/bdk/input/joycon.c @@ -1,7 +1,7 @@ /* * Joy-Con UART driver for Nintendo Switch * - * Copyright (c) 2019-2021 CTCaer + * Copyright (c) 2019-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -22,14 +22,13 @@ #include #include #include -#include #include #include #include #include +#include #include #include -#include // For disabling driver when logging is enabled. #include @@ -42,8 +41,15 @@ #define JC_HORI_INPUT_RPT_CMD 0x9A #define JC_HORI_INPUT_RPT 0x00 -#define JC_WIRED_CMD_MAC 0x01 -#define JC_WIRED_CMD_10 0x10 +#define JC_WIRED_CMD_GET_INFO 0x01 +#define JC_WIRED_CMD_SET_CHARGER 0x02 +#define JC_WIRED_CMD_GET_CHARGER 0x03 +#define JC_WIRED_CMD_BATT_VOLT 0x06 +#define JC_WIRED_CMD_WAKE_REASON 0x07 +#define JC_WIRED_CMD_HID_CONN 0x10 +#define JC_WIRED_CMD_HID_DISC 0x11 +#define JC_WIRED_CMD_SET_HIDRATE 0x12 // Output report rate. +#define JC_WIRED_CMD_SET_BRATE 0x20 #define JC_HID_OUTPUT_RPT 0x01 #define JC_HID_RUMBLE_RPT 0x10 @@ -61,26 +67,67 @@ #define JC_HID_SUBCMD_RUMBLE_CTL 0x48 #define JC_HID_SUBCMD_SND_RUMBLE 0xFF +#define JC_SIO_OUTPUT_RPT 0x91 +#define JC_SIO_INPUT_RPT 0x92 +#define JC_SIO_CMD_ACK 0x80 + +#define JC_SIO_CMD_INIT 0x01 +#define JC_SIO_CMD_UNK02 0x02 +#define JC_SIO_CMD_VER_RPT 0x03 +#define JC_SIO_CMD_UNK20 0x20 // JC_WIRED_CMD_SET_BRATE +#define JC_SIO_CMD_UNK21 0x21 +#define JC_SIO_CMD_UNK22 0x22 +#define JC_SIO_CMD_UNK40 0x40 +#define JC_SIO_CMD_STATUS 0x41 +#define JC_SIO_CMD_IAP_VER 0x42 + + #define JC_BTN_MASK_L 0xFF2900 // 0xFFE900: with charge status. #define JC_BTN_MASK_R 0x0056FF -#define JC_ID_L 0x01 -#define JC_ID_R 0x02 -#define JC_ID_HORI 0x20 +#define JC_ID_L 0x01 // Joycon (L). Mask for Hori (L). +#define JC_ID_R 0x02 // Joycon (R). Mask for Hori (R). +#define JC_ID_HORI 0x20 // Mask for Hori. Actual ids: 0x21, 0x22. -#define JC_CRC8_INIT 0x00 -#define JC_CRC8_POLY 0x8D +#define JC_CRC8_POLY 0x8D + +enum +{ + JC_STATE_START = 0, + JC_STATE_HANDSHAKED = 1, + JC_STATE_BRATE_CHANGED = 2, + JC_STATE_BRATE_OK = 3, + JC_STATE_INIT_DONE = 4 +}; enum { JC_BATT_EMTPY = 0, - JC_BATT_CRIT = 2, - JC_BATT_LOW = 4, - JC_BATT_MID = 6, - JC_BATT_FULL = 8 + JC_BATT_CRIT = 1, + JC_BATT_LOW = 2, + JC_BATT_MID = 3, + JC_BATT_FULL = 4 }; -static const u8 init_jc[] = { +static const u8 sio_init[] = { + JC_SIO_OUTPUT_RPT, JC_SIO_CMD_INIT, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x95 +}; + +static const u8 sio_set_rpt_version[] = { + JC_SIO_OUTPUT_RPT, JC_SIO_CMD_VER_RPT, + // old fw: 0x00, 0x0D (0.13). New 3.4. + // force_update_en: 0x01 + 0x00, 0x00, 0x03, 0x04, 0x00, 0xDA +}; + +// Every 8ms. +static const u8 sio_pad_status[] = { + JC_SIO_OUTPUT_RPT, JC_SIO_CMD_STATUS, + 0x00, 0x00, 0x00, 0x00, 0x00, 0xB0 +}; + +static const u8 init_wake[] = { 0xA1, 0xA2, 0xA3, 0xA4 }; @@ -91,21 +138,47 @@ static const u8 init_handshake[] = { }; static const u8 init_get_info[] = { - 0x19, 0x01, 0x03, 0x07, 0x00, // Uart header. - JC_WIRED_CMD, JC_WIRED_CMD_MAC, // Wired cmd and subcmd. - 0x00, 0x00, 0x00, 0x00, 0x24 // Wired subcmd data and crc. + 0x19, 0x01, 0x03, 0x07, 0x00, // Uart header. + JC_WIRED_CMD, JC_WIRED_CMD_GET_INFO, // Wired cmd and subcmd. + 0x00, 0x00, 0x00, 0x00, 0x24 // Wired subcmd data and crc. }; -static const u8 init_finalize[] = { - 0x19, 0x01, 0x03, 0x07, 0x00, // Uart header. - JC_WIRED_CMD, JC_WIRED_CMD_10, // Wired cmd and subcmd. - 0x00, 0x00, 0x00, 0x00, 0x3D // Wired subcmd data and crc. +static const u8 init_switch_brate[] = { + 0x19, 0x01, 0x03, 0x0F, 0x00, // Uart header. + JC_WIRED_CMD, JC_WIRED_CMD_SET_BRATE, // Wired cmd and subcmd. + 0x08, 0x00, 0x00, 0xBD, 0xB1, // Wired subcmd data, data crc and crc. + // Baudrate 3 megabaud. + 0xC0, 0xC6, 0x2D, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +static const u8 init_hid_disconnect[] = { + 0x19, 0x01, 0x03, 0x07, 0x00, // Uart header. + JC_WIRED_CMD, JC_WIRED_CMD_HID_DISC, // Wired cmd and subcmd. + 0x00, 0x00, 0x00, 0x00, 0x0E // Wired subcmd data and crc. +}; + +static const u8 init_set_hid_rate[] = { + 0x19, 0x01, 0x03, 0x0B, 0x00, // Uart header. + JC_WIRED_CMD, JC_WIRED_CMD_SET_HIDRATE, // Wired cmd and subcmd. + 0x04, 0x00, 0x00, 0x12, 0xA6, // Wired subcmd data, data crc and crc. + // Output report rate 15 ms. + 0x0F, 0x00, 0x00, 0x00 + + // 5 ms. + // 0x04, 0x00, 0x00, 0x0E, 0xD5, + // 0x05, 0x00, 0x00, 0x00 +}; + +static const u8 init_hid_connect[] = { + 0x19, 0x01, 0x03, 0x07, 0x00, // Uart header. + JC_WIRED_CMD, JC_WIRED_CMD_HID_CONN, // Wired cmd and subcmd. + 0x00, 0x00, 0x00, 0x00, 0x3D // Wired subcmd data and crc. }; static const u8 nx_pad_status[] = { 0x19, 0x01, 0x03, 0x08, 0x00, // Uart header. JC_WIRED_HID, 0x00, // Wired cmd and hid cmd. - 0x01, 0x00, 0x00, 0x69, 0x2D, 0x1F // hid data and crc. + 0x01, 0x00, 0x00, 0x69, 0x2D, 0x1F // hid data, data crc and crc. }; static const u8 hori_pad_status[] = { @@ -149,8 +222,8 @@ typedef struct _jc_hid_in_rpt_t { u8 cmd; u8 pkt_id; - u8 conn_info:4; - u8 batt_info:4; + u8 conn_info:4; // Connection detect. + u8 batt_info:4; // Power info. u8 btn_right; u8 btn_shared; u8 btn_left; @@ -160,7 +233,7 @@ typedef struct _jc_hid_in_rpt_t u8 stick_h_right; u8 stick_m_right; u8 stick_v_right; - u8 vib_decider; + u8 vib_decider; // right:4, left:4 (bit3 en, bit2-0 buffer avail). u8 submcd_ack; u8 subcmd; u8 subcmd_data[]; @@ -185,36 +258,89 @@ typedef struct _jc_hid_in_pair_data_t u8 pad1; } jc_hid_in_pair_data_t; +typedef struct _jc_sio_out_rpt_t +{ + u8 cmd; + u8 subcmd; + u16 payload_size; + u8 data[2]; + u8 crc_payload; + u8 crc_hdr; + u8 payload[]; +} jc_sio_out_rpt_t; + +typedef struct _jc_sio_in_rpt_t +{ + u8 cmd; + u8 ack; + u16 payload_size; + u8 status; + u8 unk; + u8 crc_payload; + u8 crc_hdr; + u8 payload[]; +} jc_sio_in_rpt_t; + +typedef struct _jc_hid_in_sixaxis_rpt_t +{ + s16 acc_x; + s16 acc_y; + s16 acc_z; + s16 gyr_x; + s16 gyr_y; + s16 gyr_z; +} __attribute__((packed)) jc_hid_in_sixaxis_rpt_t; + +typedef struct _jc_sio_hid_in_rpt_t +{ + u8 type; + u8 pkt_id; + u8 unk; + u8 btn_right; + u8 btn_shared; + u8 btn_left; + u8 stick_h_left; + u8 stick_m_left; + u8 stick_v_left; + u8 stick_h_right; + u8 stick_m_right; + u8 stick_v_right; + u8 siaxis_rpt; // bit0-3: report num. bit4-7: imu type. + // Each report is 800 us? + jc_hid_in_sixaxis_rpt_t sixaxis[15]; +} jc_sio_hid_in_rpt_t; + typedef struct _joycon_ctxt_t { - u8 buf[0x100]; //FIXME: If heap is used, dumping breaks. - u8 uart; - u8 type; - u8 mac[6]; - u32 hw_init_done; + u8 buf[0x100]; //FIXME: If heap is used, dumping breaks. + u8 uart; + u8 type; + u8 state; u32 last_received_time; u32 last_status_req_time; - u8 rumble_sent; - u8 connected; + u8 mac[6]; + u8 pkt_id; + u8 rumble_sent; + u8 connected; + u8 detected; + u8 sio_mode; } joycon_ctxt_t; static joycon_ctxt_t jc_l = {0}; static joycon_ctxt_t jc_r = {0}; static bool jc_init_done = false; -static u32 hid_pkt_inc = 0; static jc_gamepad_rpt_t jc_gamepad; -void jc_power_supply(u8 uart, bool enable); - -static u8 jc_crc(u8 *data, u16 len) +static u8 _jc_crc(const u8 *data, u16 len, u8 init) { - u8 crc = JC_CRC8_INIT; - u16 i, j; - for (i = 0; i < len; i++) { + u8 crc = init; + for (u16 i = 0; i < len; i++) + { crc ^= data[i]; - for (j = 0; j < 8; j++) { + for (u16 j = 0; j < 8; j++) + { if ((crc & 0x80) != 0) crc = (u8)((crc << 1) ^ JC_CRC8_POLY); else @@ -224,13 +350,140 @@ static u8 jc_crc(u8 *data, u16 len) return crc; } -void joycon_send_raw(u8 uart_port, const u8 *buf, u16 size) +static void _jc_power_supply(u8 uart, bool enable) { - uart_send(uart_port, buf, size); - uart_wait_idle(uart_port, UART_TX_IDLE); + if (enable) + { + if (regulator_5v_get_dev_enabled(1 << uart)) + return; + + regulator_5v_enable(1 << uart); + + if (jc_gamepad.sio_mode) + return; + + if (jc_init_done) + { + if (uart == UART_C) + gpio_write(GPIO_PORT_CC, GPIO_PIN_3, GPIO_HIGH); + else + gpio_write(GPIO_PORT_K, GPIO_PIN_3, GPIO_HIGH); + return; + } + + if (uart == UART_C) + { + // Joy-Con(L) Charge Enable. + PINMUX_AUX(PINMUX_AUX_SPDIF_IN) = PINMUX_PULL_DOWN | 1; + gpio_direction_output(GPIO_PORT_CC, GPIO_PIN_3, GPIO_HIGH); + } + else + { + // Joy-Con(R) Charge Enable. + PINMUX_AUX(PINMUX_AUX_GPIO_PK3) = PINMUX_DRIVE_4X | PINMUX_PULL_DOWN | 2; + gpio_direction_output(GPIO_PORT_K, GPIO_PIN_3, GPIO_HIGH); + } + } + else + { + if (!regulator_5v_get_dev_enabled(1 << uart)) + return; + + regulator_5v_disable(1 << uart); + + if (jc_gamepad.sio_mode) + return; + + if (uart == UART_C) + gpio_write(GPIO_PORT_CC, GPIO_PIN_3, GPIO_LOW); + else + gpio_write(GPIO_PORT_K, GPIO_PIN_3, GPIO_LOW); + } } -static u16 jc_packet_add_uart_hdr(jc_wired_hdr_t *out, u8 wired_cmd, u8 *data, u16 size, bool crc) +static void _jc_detect() +{ + if (!jc_gamepad.sio_mode) + { + // Turn on Joy-Con detect. (UARTB/C TX). UART CTS also if HW flow control and irq is enabled. + PINMUX_AUX(PINMUX_AUX_UART2_TX) = PINMUX_INPUT_ENABLE; + PINMUX_AUX(PINMUX_AUX_UART3_TX) = PINMUX_INPUT_ENABLE; + gpio_direction_input(GPIO_PORT_G, GPIO_PIN_0); + gpio_direction_input(GPIO_PORT_D, GPIO_PIN_1); + usleep(20); + + //! HW BUG: Unlatch gpio buffer. + (void)gpio_read(GPIO_PORT_H, GPIO_PIN_6); + (void)gpio_read(GPIO_PORT_E, GPIO_PIN_6); + + // Read H6/E6 which are shared with UART TX pins. + jc_r.detected = !gpio_read(GPIO_PORT_H, GPIO_PIN_6); + jc_l.detected = !gpio_read(GPIO_PORT_E, GPIO_PIN_6); + + // Turn off Joy-Con detect. (UARTB/C TX). + PINMUX_AUX(PINMUX_AUX_UART2_TX) = 0; + PINMUX_AUX(PINMUX_AUX_UART3_TX) = 0; + gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO); + gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO); + usleep(20); + } + else + { + //! TODO: Is there a way to detect a broken Sio? + jc_l.detected = true; + } +} + +static void _jc_conn_check() +{ + _jc_detect(); + + if (jc_gamepad.sio_mode) + return; + + // Check if a Joy-Con was disconnected. + if (!jc_l.detected) + { + if (jc_l.connected) + _jc_power_supply(UART_C, false); + + jc_l.pkt_id = 0; + + jc_l.connected = false; + jc_l.rumble_sent = false; + + jc_gamepad.conn_l = false; + + jc_gamepad.batt_info_l = 0; + jc_gamepad.bt_conn_l.type = 0; + jc_gamepad.buttons &= ~JC_BTN_MASK_L; + } + + if (!jc_r.detected) + { + if (jc_r.connected) + _jc_power_supply(UART_B, false); + + jc_r.pkt_id = 0; + + jc_r.connected = false; + jc_r.rumble_sent = false; + + jc_gamepad.conn_r = false; + + jc_gamepad.batt_info_r = 0; + jc_gamepad.bt_conn_r.type = 0; + jc_gamepad.buttons &= ~JC_BTN_MASK_R; + } +} + +static void _joycon_send_raw(u8 uart_port, const u8 *buf, u16 size) +{ + uart_send(uart_port, buf, size); + uart_wait_xfer(uart_port, UART_TX_IDLE); +} + +static u16 _jc_packet_add_uart_hdr(jc_wired_hdr_t *out, u8 wired_cmd, const u8 *data, u16 size, bool crc) { out->uart_hdr.magic[0] = 0x19; out->uart_hdr.magic[1] = 0x01; @@ -243,14 +496,16 @@ static u16 jc_packet_add_uart_hdr(jc_wired_hdr_t *out, u8 wired_cmd, u8 *data, u if (data) memcpy(out->data, data, size); - out->crc = crc ? jc_crc(&out->uart_hdr.total_size_msb, sizeof(out->uart_hdr.total_size_msb) + sizeof(out->cmd) + sizeof(out->data)) : 0; + out->crc = crc ? _jc_crc(&out->uart_hdr.total_size_msb, + sizeof(out->uart_hdr.total_size_msb) + + sizeof(out->cmd) + sizeof(out->data), 0) : 0; return sizeof(jc_wired_hdr_t); } -static u16 jc_hid_output_rpt_craft(jc_wired_hdr_t *rpt, u8 *payload, u16 size, bool crc) +static u16 _jc_hid_output_rpt_craft(jc_wired_hdr_t *rpt, const u8 *payload, u16 size, bool crc) { - u16 pkt_size = jc_packet_add_uart_hdr(rpt, JC_WIRED_HID, NULL, 0, crc); + u16 pkt_size = _jc_packet_add_uart_hdr(rpt, JC_WIRED_HID, NULL, 0, crc); pkt_size += size; rpt->uart_hdr.total_size_lsb += size; @@ -263,34 +518,25 @@ static u16 jc_hid_output_rpt_craft(jc_wired_hdr_t *rpt, u8 *payload, u16 size, b return pkt_size; } -void jc_send_hid_output_rpt(u8 uart, u8 *payload, u16 size, bool crc) +static void _jc_send_hid_output_rpt(joycon_ctxt_t *jc, jc_hid_out_rpt_t *hid_pkt, u16 size, bool crc) { u8 rpt[0x50]; memset(rpt, 0, sizeof(rpt)); - u32 rpt_size = jc_hid_output_rpt_craft((jc_wired_hdr_t *)rpt, payload, size, crc); + hid_pkt->pkt_id = (jc->pkt_id++ & 0xF); + u32 rpt_size = _jc_hid_output_rpt_craft((jc_wired_hdr_t *)rpt, (u8 *)hid_pkt, size, crc); - joycon_send_raw(uart, rpt, rpt_size); + _joycon_send_raw(jc->uart, rpt, rpt_size); } -static u8 jc_hid_pkt_id_incr() +static void _jc_send_hid_cmd(joycon_ctxt_t *jc, u8 subcmd, const u8 *data, u16 size) { - u8 curr_id = hid_pkt_inc; - hid_pkt_inc++; + static const u8 rumble_neutral[8] = { 0x00, 0x01, 0x40, 0x40, 0x00, 0x01, 0x40, 0x40 }; + static const u8 rumble_init[8] = { 0xc2, 0xc8, 0x03, 0x72, 0xc2, 0xc8, 0x03, 0x72 }; - return (curr_id & 0xF); -} - -void jc_send_hid_cmd(u8 uart, u8 subcmd, u8 *data, u16 size) -{ - u8 temp[0x30]; - u8 rumble_neutral[8] = {0x00, 0x01, 0x40, 0x40, 0x00, 0x01, 0x40, 0x40}; - u8 rumble_init[8] = {0xc2, 0xc8, 0x03, 0x72, 0xc2, 0xc8, 0x03, 0x72}; - - memset(temp, 0, sizeof(temp)); + u8 temp[0x30] = {0}; jc_hid_out_rpt_t *hid_pkt = (jc_hid_out_rpt_t *)temp; - memcpy(hid_pkt->rumble, rumble_neutral, sizeof(rumble_neutral)); if (subcmd == JC_HID_SUBCMD_SND_RUMBLE) @@ -299,63 +545,59 @@ void jc_send_hid_cmd(u8 uart, u8 subcmd, u8 *data, u16 size) bool send_l_rumble = jc_l.connected && !jc_l.rumble_sent; // Enable rumble. - hid_pkt->cmd = JC_HID_OUTPUT_RPT; - hid_pkt->pkt_id = jc_hid_pkt_id_incr(); + hid_pkt->cmd = JC_HID_OUTPUT_RPT; hid_pkt->subcmd = JC_HID_SUBCMD_RUMBLE_CTL; hid_pkt->subcmd_data[0] = 1; if (send_r_rumble) - jc_send_hid_output_rpt(UART_B, (u8 *)hid_pkt, 0x10, false); + _jc_send_hid_output_rpt(&jc_r, hid_pkt, 0x10, false); if (send_l_rumble) - jc_send_hid_output_rpt(UART_C, (u8 *)hid_pkt, 0x10, false); + _jc_send_hid_output_rpt(&jc_l, hid_pkt, 0x10, false); // Send rumble. hid_pkt->cmd = JC_HID_RUMBLE_RPT; - hid_pkt->pkt_id = jc_hid_pkt_id_incr(); memcpy(hid_pkt->rumble, rumble_init, sizeof(rumble_init)); if (send_r_rumble) - jc_send_hid_output_rpt(UART_B, (u8 *)hid_pkt, 10, false); + _jc_send_hid_output_rpt(&jc_r, hid_pkt, 10, false); if (send_l_rumble) - jc_send_hid_output_rpt(UART_C, (u8 *)hid_pkt, 10, false); + _jc_send_hid_output_rpt(&jc_l, hid_pkt, 10, false); msleep(15); // Disable rumble. - hid_pkt->cmd = JC_HID_OUTPUT_RPT; - hid_pkt->pkt_id = jc_hid_pkt_id_incr(); + hid_pkt->cmd = JC_HID_OUTPUT_RPT; hid_pkt->subcmd = JC_HID_SUBCMD_RUMBLE_CTL; hid_pkt->subcmd_data[0] = 0; memcpy(hid_pkt->rumble, rumble_neutral, sizeof(rumble_neutral)); if (send_r_rumble) - jc_send_hid_output_rpt(UART_B, (u8 *)hid_pkt, 0x10, false); + _jc_send_hid_output_rpt(&jc_r, hid_pkt, 0x10, false); if (send_l_rumble) - jc_send_hid_output_rpt(UART_C, (u8 *)hid_pkt, 0x10, false); + _jc_send_hid_output_rpt(&jc_l, hid_pkt, 0x10, false); } else { - bool crc_needed = (jc_l.uart == uart) ? (jc_l.type & JC_ID_HORI) : (jc_r.type & JC_ID_HORI); + bool crc_needed = jc->type & JC_ID_HORI; - hid_pkt->cmd = JC_HID_OUTPUT_RPT; - hid_pkt->pkt_id = jc_hid_pkt_id_incr(); + hid_pkt->cmd = JC_HID_OUTPUT_RPT; hid_pkt->subcmd = subcmd; if (data) memcpy(hid_pkt->subcmd_data, data, size); - jc_send_hid_output_rpt(uart, (u8 *)hid_pkt, sizeof(jc_hid_out_rpt_t) + size, crc_needed); + _jc_send_hid_output_rpt(jc, hid_pkt, sizeof(jc_hid_out_rpt_t) + size, crc_needed); } } -static void jc_charging_decider(u8 batt, u8 uart) +static void _jc_charging_decider(u8 batt, u8 uart) { u32 system_batt_enough = max17050_get_cached_batt_volt() > 4000; // Power supply control based on battery levels and charging. - if ((batt >> 1 << 1) < JC_BATT_LOW) // Level without checking charging. - jc_power_supply(uart, true); - else if (batt > (system_batt_enough ? JC_BATT_FULL : JC_BATT_MID)) // Addresses the charging bit. - jc_power_supply(uart, false); + if ((batt >> 1) < JC_BATT_LOW) // Level without checking charging. + _jc_power_supply(uart, true); + else if (batt > (system_batt_enough ? JC_BATT_FULL : JC_BATT_MID) << 1) // Addresses the charging bit. + _jc_power_supply(uart, false); } -static void jc_parse_wired_hid(joycon_ctxt_t *jc, const u8* packet, u32 size) +static void _jc_parse_wired_hid(joycon_ctxt_t *jc, const u8 *packet, int size) { u32 btn_tmp; jc_hid_in_rpt_t *hid_pkt = (jc_hid_in_rpt_t *)packet; @@ -363,7 +605,14 @@ static void jc_parse_wired_hid(joycon_ctxt_t *jc, const u8* packet, u32 size) switch (hid_pkt->cmd) { case JC_HORI_INPUT_RPT: + if (!(jc->type & JC_ID_HORI)) + return; + case JC_HID_INPUT_RPT: + // Discard incomplete hid packets. + if (size < 12) + break; + btn_tmp = hid_pkt->btn_right | hid_pkt->btn_shared << 8 | hid_pkt->btn_left << 16; if (jc->type & JC_ID_L) @@ -390,7 +639,8 @@ static void jc_parse_wired_hid(joycon_ctxt_t *jc, const u8* packet, u32 size) jc_gamepad.conn_l = jc_l.connected; jc_gamepad.conn_r = jc_r.connected; - jc_charging_decider(hid_pkt->batt_info, jc->uart); + if (hid_pkt->cmd == JC_HID_INPUT_RPT) + _jc_charging_decider(hid_pkt->batt_info, jc->uart); break; case JC_HID_SUBMCD_RPT: if (hid_pkt->subcmd == JC_HID_SUBCMD_SPI_READ) @@ -402,10 +652,10 @@ static void jc_parse_wired_hid(joycon_ctxt_t *jc, const u8* packet, u32 size) else bt_conn = &jc_gamepad.bt_conn_r; - jc_hid_in_spi_read_t *spi_info = (jc_hid_in_spi_read_t *)hid_pkt->subcmd_data; + jc_hid_in_spi_read_t *spi_info = (jc_hid_in_spi_read_t *)hid_pkt->subcmd_data; jc_hid_in_pair_data_t *pair_data = (jc_hid_in_pair_data_t *)spi_info->data; - // Check if we reply is pairing info. + // Check if the reply is pairing info. if (spi_info->size == 0x1A && pair_data->magic == 0x95 && pair_data->size == 0x22) { bt_conn->type = jc->type; @@ -420,125 +670,192 @@ static void jc_parse_wired_hid(joycon_ctxt_t *jc, const u8* packet, u32 size) default: break; } - jc->last_received_time = get_tmr_ms(); } -static void jc_parse_wired_init(joycon_ctxt_t *jc, const u8* data, u32 size) +static void _jc_parse_wired_init(joycon_ctxt_t *jc, const u8 *data, int size) { + // Discard empty packets. + if (size <= 0) + return; + switch (data[0]) { - case JC_WIRED_CMD_MAC: + case JC_WIRED_CMD_GET_INFO: for (int i = 12; i > 6; i--) jc->mac[12 - i] = data[i]; jc->type = data[6]; jc->connected = true; + break; + case JC_WIRED_CMD_SET_BRATE: + jc->state = JC_STATE_BRATE_CHANGED; + break; + case JC_WIRED_CMD_HID_DISC: + jc->state = JC_STATE_BRATE_OK; + break; + case JC_WIRED_CMD_HID_CONN: + case JC_WIRED_CMD_SET_HIDRATE: + // done. default: break; } } -static void jc_uart_pkt_parse(joycon_ctxt_t *jc, const u8* packet, size_t size) +static void _jc_uart_pkt_parse(joycon_ctxt_t *jc, const jc_wired_hdr_t *pkt, int size) { - jc_wired_hdr_t *pkt = (jc_wired_hdr_t *)packet; switch (pkt->cmd) { case JC_HORI_INPUT_RPT_CMD: case JC_WIRED_HID: - jc_parse_wired_hid(jc, pkt->payload, (pkt->data[0] << 8) | pkt->data[1]); + _jc_parse_wired_hid(jc, pkt->payload, size - sizeof(jc_wired_hdr_t)); break; case JC_WIRED_INIT_REPLY: - jc_parse_wired_init(jc, pkt->data, size - sizeof(jc_uart_hdr_t) - 1); + _jc_parse_wired_init(jc, pkt->data, size - sizeof(jc_uart_hdr_t) - 1); + break; + case JC_INIT_HANDSHAKE: + jc->state = JC_STATE_HANDSHAKED; + break; + default: + break; + } + + jc->last_received_time = get_tmr_ms(); +} + +static void _jc_sio_parse_payload(joycon_ctxt_t *jc, u8 cmd, const u8 *payload, int size) +{ + switch (cmd) + { + case JC_SIO_CMD_STATUS: + // Discard incomplete packets. + if (size < 12) + break; + + jc_sio_hid_in_rpt_t *hid_pkt = (jc_sio_hid_in_rpt_t *)payload; + jc_gamepad.buttons = hid_pkt->btn_right | hid_pkt->btn_shared << 8 | hid_pkt->btn_left << 16; + jc_gamepad.home = !gpio_read(GPIO_PORT_V, GPIO_PIN_3); + + jc_gamepad.lstick_x = hid_pkt->stick_h_left | ((hid_pkt->stick_m_left & 0xF) << 8); + jc_gamepad.lstick_y = (hid_pkt->stick_m_left >> 4) | (hid_pkt->stick_v_left << 4); + jc_gamepad.rstick_x = hid_pkt->stick_h_right | ((hid_pkt->stick_m_right & 0xF) << 8); + jc_gamepad.rstick_y = (hid_pkt->stick_m_right >> 4) | (hid_pkt->stick_v_right << 4); + + jc_gamepad.batt_info_l = jc_l.connected; + jc_gamepad.batt_info_r = gpio_read(GPIO_PORT_E, GPIO_PIN_7); // Set IRQ status. + + jc_gamepad.conn_l = jc_l.connected; + jc_gamepad.conn_r = jc_l.connected; break; default: break; } } -static void jc_rcv_pkt(joycon_ctxt_t *jc) +static void _jc_sio_uart_pkt_parse(joycon_ctxt_t *jc, const jc_sio_in_rpt_t *pkt, int size) { - if (gpio_read(GPIO_PORT_E, GPIO_PIN_6) && jc->uart == UART_C) - return; - else if (gpio_read(GPIO_PORT_H, GPIO_PIN_6) && jc->uart == UART_B) + if (pkt->crc_hdr != _jc_crc((u8 *)pkt, sizeof(jc_sio_in_rpt_t) - 1, 0)) return; - // Check if device stopped sending data. - u32 uart_irq = uart_get_IIR(jc->uart); - if (uart_irq != UART_IIR_REDI) + u8 cmd = pkt->ack & (~JC_SIO_CMD_ACK); + switch (cmd) + { + case JC_SIO_CMD_INIT: + jc->connected = pkt->status == 0; + break; + case JC_SIO_CMD_VER_RPT: + if (jc->connected) + jc->connected = pkt->status == 0; + break; + case JC_SIO_CMD_IAP_VER: + case JC_SIO_CMD_STATUS: + _jc_sio_parse_payload(jc, cmd, pkt->payload, size - sizeof(jc_sio_in_rpt_t)); + break; + case JC_SIO_CMD_UNK02: + case JC_SIO_CMD_UNK20: + case JC_SIO_CMD_UNK21: + case JC_SIO_CMD_UNK22: + case JC_SIO_CMD_UNK40: + default: + break; + } + + jc->last_received_time = get_tmr_ms(); +} + +static void _jc_rcv_pkt(joycon_ctxt_t *jc) +{ + if (!jc->detected) return; u32 len = uart_recv(jc->uart, (u8 *)jc->buf, 0x100); + if (len < 8) + return; - // Check valid size and uart reply magic. - if (len > 7 && !memcmp(jc->buf, "\x19\x81\x03", 3)) + // For Joycon, check uart reply magic. + jc_wired_hdr_t *jc_pkt = (jc_wired_hdr_t *)jc->buf; + if (!jc->sio_mode && !memcmp(jc_pkt->uart_hdr.magic, "\x19\x81\x03", 3)) { - jc_wired_hdr_t *pkt = (jc_wired_hdr_t *)(jc->buf); + _jc_uart_pkt_parse(jc, jc_pkt, len); - jc_uart_pkt_parse(jc, jc->buf, pkt->uart_hdr.total_size_lsb + sizeof(jc_uart_hdr_t)); + return; + } + + // For Sio, check uart output report and command ack. + jc_sio_in_rpt_t *sio_pkt = (jc_sio_in_rpt_t *)(jc->buf); + if (jc->sio_mode && sio_pkt->cmd == JC_SIO_INPUT_RPT && (sio_pkt->ack & JC_SIO_CMD_ACK) == JC_SIO_CMD_ACK) + { + _jc_sio_uart_pkt_parse(jc, sio_pkt, len); + + return; } } -static bool jc_send_init_rumble(joycon_ctxt_t *jc) +static bool _jc_send_init_rumble(joycon_ctxt_t *jc) { // Send init rumble or request nx pad status report. if ((jc_r.connected && !jc_r.rumble_sent) || (jc_l.connected && !jc_l.rumble_sent)) { - gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO); - gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO); - - jc_send_hid_cmd(jc->uart, JC_HID_SUBCMD_SND_RUMBLE, NULL, 0); + _jc_send_hid_cmd(jc, JC_HID_SUBCMD_SND_RUMBLE, NULL, 0); if (jc_l.connected) jc_l.rumble_sent = true; if (jc_r.connected) jc_r.rumble_sent = true; - if (jc->uart != UART_B) - gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO); - else - gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO); - return 1; } return 0; } -static void jc_req_nx_pad_status(joycon_ctxt_t *jc) +static void _jc_req_nx_pad_status(joycon_ctxt_t *jc) { - bool is_nxpad = !(jc->type & JC_ID_HORI); + if (!jc->detected) + return; + + bool is_nxpad = !(jc->type & JC_ID_HORI) && !jc->sio_mode; + + if (jc->last_status_req_time > get_tmr_ms() || !jc->connected) + return; if (is_nxpad) { - bool sent_rumble = jc_send_init_rumble(jc); + bool sent_rumble = _jc_send_init_rumble(jc); if (sent_rumble) return; } - if (jc->last_status_req_time > get_tmr_ms() || !jc->connected) - return; - - // Turn off Joy-Con detect. - if (jc->uart == UART_B) - gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO); - else - gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO); - if (is_nxpad) - joycon_send_raw(jc->uart, nx_pad_status, sizeof(nx_pad_status)); + _joycon_send_raw(jc->uart, nx_pad_status, sizeof(nx_pad_status)); + else if (jc->sio_mode) + _joycon_send_raw(jc->uart, sio_pad_status, sizeof(sio_pad_status)); else - joycon_send_raw(jc->uart, hori_pad_status, sizeof(hori_pad_status)); + _joycon_send_raw(jc->uart, hori_pad_status, sizeof(hori_pad_status)); - // Turn Joy-Con detect on. - if (jc->uart == UART_B) - gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO); - else - gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO); - - jc->last_status_req_time = get_tmr_ms() + 15; + jc->last_status_req_time = get_tmr_ms() + (!jc->sio_mode ? 15 : 7); } -static bool _jc_validate_pairing_info(u8 *buf, bool *is_hos) +static bool _jc_validate_pairing_info(const u8 *buf, bool *is_hos) { u8 crc = 0; for (u32 i = 0; i < 0x22; i++) @@ -563,21 +880,23 @@ jc_gamepad_rpt_t *jc_get_bt_pairing_info(bool *is_l_hos, bool *is_r_hos) u8 retries; jc_bt_conn_t *bt_conn; - if (!jc_init_done) + if (!jc_init_done || jc_gamepad.sio_mode) return NULL; bt_conn = &jc_gamepad.bt_conn_l; memset(bt_conn->host_mac, 0, 6); - memset(bt_conn->ltk, 0, 16); + memset(bt_conn->ltk, 0, 16); bt_conn = &jc_gamepad.bt_conn_r; memset(bt_conn->host_mac, 0, 6); - memset(bt_conn->ltk, 0, 16); + memset(bt_conn->ltk, 0, 16); + + _jc_conn_check(); while (jc_l.last_status_req_time > get_tmr_ms()) { - jc_rcv_pkt(&jc_r); - jc_rcv_pkt(&jc_l); + _jc_rcv_pkt(&jc_r); + _jc_rcv_pkt(&jc_l); } jc_hid_in_spi_read_t subcmd_data_l; @@ -588,13 +907,13 @@ jc_gamepad_rpt_t *jc_get_bt_pairing_info(bool *is_l_hos, bool *is_r_hos) subcmd_data_r.addr = 0x2000; subcmd_data_r.size = 0x1A; - // Turn off Joy-Con detect. - gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO); - gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO); - bool jc_r_found = jc_r.connected ? false : true; bool jc_l_found = jc_l.connected ? false : true; + // Set mode to HW controlled RTS. + uart_set_mode(jc_l.uart, UART_AO_TX_HW_RX); + uart_set_mode(jc_r.uart, UART_AO_TX_HW_RX); + u32 total_retries = 10; retry: retries = 10; @@ -605,23 +924,26 @@ retry: { if (!jc_l_found) { - jc_send_hid_cmd(jc_l.uart, JC_HID_SUBCMD_SPI_READ, (u8 *)&subcmd_data_l, 5); + _jc_send_hid_cmd(&jc_l, JC_HID_SUBCMD_SPI_READ, (u8 *)&subcmd_data_l, 5); jc_l.last_status_req_time = get_tmr_ms() + 15; } if (!jc_r_found) { - jc_send_hid_cmd(jc_r.uart, JC_HID_SUBCMD_SPI_READ, (u8 *)&subcmd_data_r, 5); + _jc_send_hid_cmd(&jc_r, JC_HID_SUBCMD_SPI_READ, (u8 *)&subcmd_data_r, 5); jc_r.last_status_req_time = get_tmr_ms() + 15; } retries--; } + // Wait for the first 36 bytes to arrive. + msleep(5); + if (!jc_l_found) { memset(jc_l.buf, 0, 0x100); - jc_rcv_pkt(&jc_l); + _jc_rcv_pkt(&jc_l); bool is_hos = false; if (_jc_validate_pairing_info(&jc_l.buf[SPI_READ_OFFSET], &is_hos)) @@ -641,7 +963,7 @@ retry: if (!jc_r_found) { memset(jc_r.buf, 0, 0x100); - jc_rcv_pkt(&jc_r); + _jc_rcv_pkt(&jc_r); bool is_hos = false; if (_jc_validate_pairing_info(&jc_r.buf[SPI_READ_OFFSET], &is_hos)) @@ -674,189 +996,156 @@ retry: { bt_conn = &jc_gamepad.bt_conn_l; memset(bt_conn->host_mac, 0, 6); - memset(bt_conn->ltk, 0, 16); + memset(bt_conn->ltk, 0, 16); } if (!jc_r_found) { bt_conn = &jc_gamepad.bt_conn_r; memset(bt_conn->host_mac, 0, 6); - memset(bt_conn->ltk, 0, 16); + memset(bt_conn->ltk, 0, 16); } } - // Turn Joy-Con detect on. - gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO); - gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO); + // Restore mode to manual RTS. + uart_set_mode(jc_l.uart, UART_AO_TX_MN_RX); + uart_set_mode(jc_r.uart, UART_AO_TX_MN_RX); return &jc_gamepad; } -void jc_deinit() +static void _jc_init_conn(joycon_ctxt_t *jc) { - // Disable power. - jc_power_supply(UART_B, false); - jc_power_supply(UART_C, false); + if (!jc->detected) + return; - // Turn off Joy-Con detect. - gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO); - gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO); - - // Send sleep command. - u8 data = HCI_STATE_SLEEP; - - if (jc_r.connected && !(jc_r.type & JC_ID_HORI)) - { - jc_send_hid_cmd(UART_B, JC_HID_SUBCMD_HCI_STATE, &data, 1); - jc_rcv_pkt(&jc_r); - } - if (jc_l.connected && !(jc_l.type & JC_ID_HORI)) - { - jc_send_hid_cmd(UART_C, JC_HID_SUBCMD_HCI_STATE, &data, 1); - jc_rcv_pkt(&jc_l); - } - - // Disable UART B and C clocks. - clock_disable_uart(UART_B); - clock_disable_uart(UART_C); -} - -static void jc_init_conn(joycon_ctxt_t *jc) -{ if (((u32)get_tmr_ms() - jc->last_received_time) > 1000) { - jc_power_supply(jc->uart, true); + _jc_power_supply(jc->uart, true); - // Turn off Joy-Con detect. + // Mask out buttons and set connected to false. if (jc->uart == UART_B) { jc_gamepad.buttons &= ~JC_BTN_MASK_R; jc_gamepad.conn_r = false; - gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO); } else { jc_gamepad.buttons &= ~JC_BTN_MASK_L; jc_gamepad.conn_l = false; - gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO); } - uart_init(jc->uart, 1000000); - uart_invert(jc->uart, true, UART_INVERT_TXD); - uart_set_IIR(jc->uart); + // Initialize uart to 1 megabaud and manual RTS. + uart_init(jc->uart, 1000000, UART_AO_TX_MN_RX); - joycon_send_raw(jc->uart, init_jc, 4); - joycon_send_raw(jc->uart, init_handshake, sizeof(init_handshake)); - - msleep(5); - jc_rcv_pkt(jc); - - joycon_send_raw(jc->uart, init_get_info, sizeof(init_get_info)); - msleep(5); - jc_rcv_pkt(jc); - - if (!(jc->type & JC_ID_HORI)) + if (!jc->sio_mode) { - joycon_send_raw(jc->uart, init_finalize, sizeof(init_finalize)); + jc->state = JC_STATE_START; + + // Set TX and RTS inversion for Joycon. + uart_invert(jc->uart, true, UART_INVERT_TXD | UART_INVERT_RTS); + + // Wake up the controller. + _joycon_send_raw(jc->uart, init_wake, sizeof(init_wake)); + _jc_rcv_pkt(jc); // Clear RX FIFO. + + // Do a handshake. + u32 retries = 10; + while (retries && jc->state != JC_STATE_HANDSHAKED) + { + _joycon_send_raw(jc->uart, init_handshake, sizeof(init_handshake)); + msleep(5); + _jc_rcv_pkt(jc); + retries--; + } + + if (jc->state != JC_STATE_HANDSHAKED) + goto out; + + // Get info about the controller. + _joycon_send_raw(jc->uart, init_get_info, sizeof(init_get_info)); + msleep(2); + _jc_rcv_pkt(jc); + + if (!(jc->type & JC_ID_HORI)) + { + // Request 3 megabaud change. + _joycon_send_raw(jc->uart, init_switch_brate, sizeof(init_switch_brate)); + msleep(2); + _jc_rcv_pkt(jc); + + if (jc->state == JC_STATE_BRATE_CHANGED) + { + // Reinitialize uart to 3 megabaud and manual RTS. + uart_init(jc->uart, 3000000, UART_AO_TX_MN_RX); + uart_invert(jc->uart, true, UART_INVERT_TXD | UART_INVERT_RTS); + + // Disconnect HID. + retries = 10; + while (retries && jc->state != JC_STATE_BRATE_OK) + { + _joycon_send_raw(jc->uart, init_hid_disconnect, sizeof(init_hid_disconnect)); + msleep(5); + _jc_rcv_pkt(jc); + retries--; + } + + if (jc->state != JC_STATE_BRATE_OK) + goto out; + } + + // Create HID connection with the new rate. + _joycon_send_raw(jc->uart, init_hid_connect, sizeof(init_hid_connect)); + msleep(2); + _jc_rcv_pkt(jc); + + // Set hid packet rate. + _joycon_send_raw(jc->uart, init_set_hid_rate, sizeof(init_set_hid_rate)); + msleep(2); + _jc_rcv_pkt(jc); + } + else // Hori. Unset RTS inversion. + uart_invert(jc->uart, false, UART_INVERT_RTS); + } + else + { + // Set Sio NPOR low to configure BOOT0 mode. + gpio_write(GPIO_PORT_CC, GPIO_PIN_5, GPIO_LOW); + usleep(300); + gpio_write(GPIO_PORT_T, GPIO_PIN_0, GPIO_LOW); + gpio_write(GPIO_PORT_CC, GPIO_PIN_5, GPIO_HIGH); + msleep(100); + + // Clear RX FIFO. + _jc_rcv_pkt(jc); + + // Initialize the controller. + u32 retries = 10; + while (!jc->connected && retries) + { + _joycon_send_raw(jc->uart, sio_init, sizeof(sio_init)); + msleep(5); + _jc_rcv_pkt(jc); + retries--; + } + + if (!jc->connected) + goto out; + + // Set output report version. + _joycon_send_raw(jc->uart, sio_set_rpt_version, sizeof(sio_set_rpt_version)); msleep(5); - jc_rcv_pkt(jc); + _jc_rcv_pkt(jc); } - // Turn Joy-Con detect on. - if (jc->uart == UART_B) - gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO); - else - gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO); + // Initialization done. + jc->state = JC_STATE_INIT_DONE; +out: jc->last_received_time = get_tmr_ms(); - if (jc->connected) - jc_power_supply(jc->uart, false); - } -} - -static void jc_conn_check() -{ - // Check if a Joy-Con was disconnected. - if (gpio_read(GPIO_PORT_E, GPIO_PIN_6)) - { - jc_power_supply(UART_C, false); - - hid_pkt_inc = 0; - - jc_l.connected = false; - jc_l.rumble_sent = false; - - jc_gamepad.buttons &= ~JC_BTN_MASK_L; - jc_gamepad.conn_l = false; - - jc_gamepad.batt_info_l = 0; - jc_gamepad.bt_conn_l.type = 0; - } - - if (gpio_read(GPIO_PORT_H, GPIO_PIN_6)) - { - jc_power_supply(UART_B, false); - - hid_pkt_inc = 0; - - jc_r.connected = false; - jc_r.rumble_sent = false; - - jc_gamepad.buttons &= ~JC_BTN_MASK_R; - jc_gamepad.conn_r = false; - - jc_gamepad.batt_info_r = 0; - jc_gamepad.bt_conn_r.type = 0; - } -} - -void jc_power_supply(u8 uart, bool enable) -{ - if (enable) - { - if (regulator_5v_get_dev_enabled(1 << uart)) - return; - - regulator_5v_enable(1 << uart); - - if (jc_init_done) - { - if (uart == UART_C) - gpio_write(GPIO_PORT_CC, GPIO_PIN_3, GPIO_HIGH); - else - gpio_write(GPIO_PORT_K, GPIO_PIN_3, GPIO_HIGH); - return; - } - - if (uart == UART_C) - { - // Joy-Con(L) Charge Detect. - PINMUX_AUX(PINMUX_AUX_SPDIF_IN) = PINMUX_PULL_DOWN | 1; - gpio_config(GPIO_PORT_CC, GPIO_PIN_3, GPIO_MODE_GPIO); - gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_3, GPIO_OUTPUT_ENABLE); - gpio_write(GPIO_PORT_CC, GPIO_PIN_3, GPIO_HIGH); - } - else - { - // Joy-Con(R) Charge Detect. - PINMUX_AUX(PINMUX_AUX_GPIO_PK3) = PINMUX_DRIVE_4X | PINMUX_PULL_DOWN | 2; - gpio_config(GPIO_PORT_K, GPIO_PIN_3, GPIO_MODE_GPIO); - gpio_output_enable(GPIO_PORT_K, GPIO_PIN_3, GPIO_OUTPUT_ENABLE); - gpio_write(GPIO_PORT_K, GPIO_PIN_3, GPIO_HIGH); - } - } - else - { - if (!regulator_5v_get_dev_enabled(1 << uart)) - return; - - regulator_5v_disable(1 << uart); - - if (uart == UART_C) - gpio_write(GPIO_PORT_CC, GPIO_PIN_3, GPIO_LOW); - else - gpio_write(GPIO_PORT_K, GPIO_PIN_3, GPIO_LOW); + if (!jc->sio_mode && jc->connected && !(jc->type & JC_ID_HORI)) + _jc_power_supply(jc->uart, false); } } @@ -865,64 +1154,121 @@ void jc_init_hw() jc_l.uart = UART_C; jc_r.uart = UART_B; + jc_l.sio_mode = fuse_read_hw_type() == FUSE_NX_HW_TYPE_HOAG; + jc_gamepad.sio_mode = jc_l.sio_mode; + #if !defined(DEBUG_UART_PORT) || !(DEBUG_UART_PORT) - if (fuse_read_hw_type() == FUSE_NX_HW_TYPE_HOAG) - return; + _jc_power_supply(UART_C, true); + _jc_power_supply(UART_B, true); - jc_power_supply(UART_C, true); - jc_power_supply(UART_B, true); + // Sio Initialization. + if (jc_gamepad.sio_mode) + { + // Enable 4 MHz clock to Sio. + clock_enable_extperiph2(); + PINMUX_AUX(PINMUX_AUX_TOUCH_CLK) = PINMUX_PULL_DOWN; - // Joy-Con (R) IsAttached. - PINMUX_AUX(PINMUX_AUX_GPIO_PH6) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE; - gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_GPIO); + // Configure Sio HOME BUTTON. + PINMUX_AUX(PINMUX_AUX_LCD_GPIO1) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE | PINMUX_PULL_UP | 1; + gpio_direction_input(GPIO_PORT_V, GPIO_PIN_3); - // Joy-Con (L) IsAttached. + // Configure Sio IRQ + PINMUX_AUX(PINMUX_AUX_GPIO_PE7) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE | PINMUX_PULL_UP; + gpio_direction_input(GPIO_PORT_E, GPIO_PIN_7); + + // Configure Sio NRST and BOOT0. + PINMUX_AUX(PINMUX_AUX_CAM1_STROBE) = PINMUX_PULL_DOWN | 1; + PINMUX_AUX(PINMUX_AUX_CAM2_PWDN) = PINMUX_PULL_DOWN | 1; + + // Set BOOT0 to flash mode. (output high is sram mode). + gpio_direction_output(GPIO_PORT_T, GPIO_PIN_0, GPIO_LOW); + + // NRST to pull down. + gpio_direction_input(GPIO_PORT_T, GPIO_PIN_1); + + // Configure Sio NPOR. + PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN1) = PINMUX_IO_HV | PINMUX_LPDR | 1; + gpio_direction_output(GPIO_PORT_CC, GPIO_PIN_5, GPIO_LOW); + } + +#if 0 // Already set by hw init. + // Set Joy-Con IsAttached pinmux. Shared with UARTB/UARTC TX. PINMUX_AUX(PINMUX_AUX_GPIO_PE6) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE; + PINMUX_AUX(PINMUX_AUX_GPIO_PH6) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE; + + // Set Joy-Con IsAttached mode. Shared with UARTB/UARTC TX. gpio_config(GPIO_PORT_E, GPIO_PIN_6, GPIO_MODE_GPIO); + gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_GPIO); +#endif // Configure pinmuxing for UART B and C. - pinmux_config_uart(UART_B); + if (!jc_gamepad.sio_mode) + pinmux_config_uart(UART_B); pinmux_config_uart(UART_C); - // Ease the stress to APB. - bpmp_freq_t prev_fid = bpmp_clk_rate_set(BPMP_CLK_NORMAL); - // Enable UART B and C clocks. - clock_enable_uart(UART_B); + if (!jc_gamepad.sio_mode) + clock_enable_uart(UART_B); clock_enable_uart(UART_C); - // Restore OC. - bpmp_clk_rate_set(prev_fid); - - // Turn Joy-Con detect on. - gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO); - gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO); - jc_init_done = true; #endif } +void jc_deinit() +{ + if (!jc_init_done) + return; + + // Disable power. + _jc_power_supply(UART_B, false); + _jc_power_supply(UART_C, false); + + if (!jc_gamepad.sio_mode) + { + // Send sleep command. + u8 data = HCI_STATE_SLEEP; + if (jc_r.connected && !(jc_r.type & JC_ID_HORI)) + { + _jc_send_hid_cmd(&jc_r, JC_HID_SUBCMD_HCI_STATE, &data, 1); + _jc_rcv_pkt(&jc_r); + } + if (jc_l.connected && !(jc_l.type & JC_ID_HORI)) + { + _jc_send_hid_cmd(&jc_l, JC_HID_SUBCMD_HCI_STATE, &data, 1); + _jc_rcv_pkt(&jc_l); + } + } + else + { + // Disable Sio NPOR. + gpio_write(GPIO_PORT_CC, GPIO_PIN_5, GPIO_LOW); + + // Disable 4 MHz clock to Sio. + clock_disable_extperiph2(); + } + + // Disable UART B and C clocks. + if (!jc_gamepad.sio_mode) + clock_disable_uart(UART_B); + clock_disable_uart(UART_C); +} + jc_gamepad_rpt_t *joycon_poll() { if (!jc_init_done) return NULL; - if (!gpio_read(GPIO_PORT_H, GPIO_PIN_6)) - jc_init_conn(&jc_r); - if (!gpio_read(GPIO_PORT_E, GPIO_PIN_6)) - jc_init_conn(&jc_l); + _jc_conn_check(); - if (!gpio_read(GPIO_PORT_H, GPIO_PIN_6)) - jc_req_nx_pad_status(&jc_r); - if (!gpio_read(GPIO_PORT_E, GPIO_PIN_6)) - jc_req_nx_pad_status(&jc_l); + _jc_init_conn(&jc_r); + _jc_init_conn(&jc_l); - if (!gpio_read(GPIO_PORT_H, GPIO_PIN_6)) - jc_rcv_pkt(&jc_r); - if (!gpio_read(GPIO_PORT_E, GPIO_PIN_6)) - jc_rcv_pkt(&jc_l); + _jc_req_nx_pad_status(&jc_r); + _jc_req_nx_pad_status(&jc_l); - jc_conn_check(); + _jc_rcv_pkt(&jc_r); + _jc_rcv_pkt(&jc_l); return &jc_gamepad; } diff --git a/bdk/input/joycon.h b/bdk/input/joycon.h index 932c836..fbb789f 100644 --- a/bdk/input/joycon.h +++ b/bdk/input/joycon.h @@ -43,34 +43,34 @@ typedef struct _jc_gamepad_rpt_t struct { // Joy-Con (R). - u32 y:1; - u32 x:1; - u32 b:1; - u32 a:1; - u32 sr_r:1; - u32 sl_r:1; - u32 r:1; - u32 zr:1; +/*00*/ u32 y:1; +/*01*/ u32 x:1; +/*02*/ u32 b:1; +/*03*/ u32 a:1; +/*04*/ u32 sr_r:1; +/*05*/ u32 sl_r:1; +/*06*/ u32 r:1; +/*07*/ u32 zr:1; // Shared - u32 minus:1; - u32 plus:1; - u32 r3:1; - u32 l3:1; - u32 home:1; - u32 cap:1; - u32 pad:1; - u32 wired:1; +/*08*/ u32 minus:1; +/*09*/ u32 plus:1; +/*10*/ u32 r3:1; +/*11*/ u32 l3:1; +/*12*/ u32 home:1; +/*13*/ u32 cap:1; +/*14*/ u32 pad:1; +/*15*/ u32 wired:1; // Joy-Con (L). - u32 down:1; - u32 up:1; - u32 right:1; - u32 left:1; - u32 sr_l:1; - u32 sl_l:1; - u32 l:1; - u32 zl:1; +/*16*/ u32 down:1; +/*17*/ u32 up:1; +/*18*/ u32 right:1; +/*19*/ u32 left:1; +/*20*/ u32 sr_l:1; +/*21*/ u32 sl_l:1; +/*22*/ u32 l:1; +/*23*/ u32 zl:1; }; u32 buttons; }; @@ -83,16 +83,26 @@ typedef struct _jc_gamepad_rpt_t bool center_stick_r; bool conn_l; bool conn_r; - u8 batt_info_l; - u8 batt_info_r; + bool sio_mode; + u8 batt_info_l; // Also Sio Connected status. + u8 batt_info_r; // Also Sio IRQ. jc_bt_conn_t bt_conn_l; jc_bt_conn_t bt_conn_r; } jc_gamepad_rpt_t; -void jc_power_supply(u8 uart, bool enable); +typedef struct _jc_calib_t +{ + u16 x_max:12; + u16 y_max:12; + u16 x_center:12; + u16 y_center:12; + u16 x_min:12; + u16 y_min:12; +} __attribute__((packed)) jc_calib_t; + void jc_init_hw(); void jc_deinit(); jc_gamepad_rpt_t *joycon_poll(); jc_gamepad_rpt_t *jc_get_bt_pairing_info(bool *is_l_hos, bool *is_r_hos); -#endif \ No newline at end of file +#endif diff --git a/bdk/input/touch.c b/bdk/input/touch.c index 2aba0e4..f5b5098 100644 --- a/bdk/input/touch.c +++ b/bdk/input/touch.c @@ -2,7 +2,7 @@ * Touch driver for Nintendo Switch's STM FingerTip S (4CD60D) touch controller * * Copyright (c) 2018 langerhans - * Copyright (c) 2018-2020 CTCaer + * Copyright (c) 2018-2023 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -24,9 +24,9 @@ #include #include #include +#include #include #include -#include #include "touch.h" @@ -35,12 +35,12 @@ static touch_panel_info_t _panels[] = { - { 0, 1, 1, 1, "NISSHA NFT-K12D" }, - { 1, 0, 1, 1, "GiS GGM6 B2X" }, - { 2, 0, 0, 0, "NISSHA NBF-K9A" }, - { 3, 1, 0, 0, "GiS 5.5\"" }, - { 4, 0, 0, 1, "Unknown_001" }, - { -1, 1, 0, 1, "GiS VA 6.2\"" } + { 0, 1, 1, 1, "NISSHA NFT-K12D" },// 0. + { 1, 0, 1, 1, "GiS GGM6 B2X" },// 1. + { 2, 0, 0, 0, "NISSHA NBF-K9A" },// 3. + { 3, 1, 0, 0, "GiS 5.5\"" },// 4. + { 4, 0, 0, 1, "Samsung TSP" },// 5? + { -1, 1, 0, 1, "GiS VA 6.2\"" } // 2. }; static int touch_command(u8 cmd, u8 *buf, u8 size) @@ -87,19 +87,19 @@ static int touch_wait_event(u8 event, u8 status, u32 timeout, u8 *buf) static void _touch_compensate_limits(touch_event *event, bool touching) { - event->x = MAX(event->x, EDGE_OFFSET); - event->x = MIN(event->x, X_REAL_MAX); + event->x = MAX(event->x, EDGE_OFFSET); + event->x = MIN(event->x, X_REAL_MAX); event->x -= EDGE_OFFSET; u32 x_adj = (1280 * 1000) / (X_REAL_MAX - EDGE_OFFSET); - event->x = ((u32)event->x * x_adj) / 1000; + event->x = ((u32)event->x * x_adj) / 1000; if (touching) { - event->y = MAX(event->y, EDGE_OFFSET); - event->y = MIN(event->y, Y_REAL_MAX); + event->y = MAX(event->y, EDGE_OFFSET); + event->y = MIN(event->y, Y_REAL_MAX); event->y -= EDGE_OFFSET; u32 y_adj = (720 * 1000) / (Y_REAL_MAX - EDGE_OFFSET); - event->y = ((u32)event->y * y_adj) / 1000; + event->y = ((u32)event->y * y_adj) / 1000; } } @@ -115,6 +115,7 @@ static void _touch_process_contact_event(touch_event *event, bool touching) event->z = event->raw[5] | (event->raw[6] << 8); event->z = event->z << 6; + u16 tmp = 0x40; if ((event->raw[7] & 0x3F) != 1 && (event->raw[7] & 0x3F) != 0x3F) tmp = event->raw[7] & 0x3F; @@ -245,7 +246,7 @@ int touch_get_fw_info(touch_fw_info_t *fw) res = touch_read_reg(cmd, 3, buf, 8); if (!res) { - fw->fw_id = (buf[1] << 24) | (buf[2] << 16) | (buf[3] << 8) | buf[4]; + fw->fw_id = (buf[1] << 24) | (buf[2] << 16) | (buf[3] << 8) | buf[4]; fw->ftb_ver = (buf[6] << 8) | buf[5]; } @@ -400,30 +401,29 @@ static int touch_init() int touch_power_on() { - // Enable LDO6 for touchscreen AVDD supply. - max7762x_regulator_set_voltage(REGULATOR_LDO6, 2900000); - max7762x_regulator_enable(REGULATOR_LDO6, true); - - // Configure touchscreen VDD GPIO. - PINMUX_AUX(PINMUX_AUX_DAP4_SCLK) = PINMUX_PULL_DOWN | 1; - gpio_config(GPIO_PORT_J, GPIO_PIN_7, GPIO_MODE_GPIO); - gpio_output_enable(GPIO_PORT_J, GPIO_PIN_7, GPIO_OUTPUT_ENABLE); - gpio_write(GPIO_PORT_J, GPIO_PIN_7, GPIO_HIGH); - - // IRQ and more. - // PINMUX_AUX(PINMUX_AUX_TOUCH_INT) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE | PINMUX_PULL_UP | 3; - // gpio_config(GPIO_PORT_X, GPIO_PIN_1, GPIO_MODE_GPIO); - // gpio_write(GPIO_PORT_X, GPIO_PIN_1, GPIO_LOW); - // Configure Touscreen and GCAsic shared GPIO. PINMUX_AUX(PINMUX_AUX_CAM_I2C_SDA) = PINMUX_LPDR | PINMUX_INPUT_ENABLE | PINMUX_TRISTATE | PINMUX_PULL_UP | 2; - PINMUX_AUX(PINMUX_AUX_CAM_I2C_SCL) = PINMUX_IO_HV | PINMUX_LPDR | PINMUX_TRISTATE | PINMUX_PULL_DOWN | 2; + PINMUX_AUX(PINMUX_AUX_CAM_I2C_SCL) = PINMUX_IO_HV | PINMUX_LPDR | PINMUX_TRISTATE | PINMUX_PULL_DOWN | 2; // Unused. gpio_config(GPIO_PORT_S, GPIO_PIN_3, GPIO_MODE_GPIO); // GC detect. + // Configure touchscreen Touch Reset pin. + PINMUX_AUX(PINMUX_AUX_DAP4_SCLK) = PINMUX_PULL_DOWN | 1; + gpio_direction_output(GPIO_PORT_J, GPIO_PIN_7, GPIO_LOW); + usleep(20); + + // Enable LDO6 for touchscreen AVDD and DVDD supply. + max7762x_regulator_set_voltage(REGULATOR_LDO6, 2900000); + max7762x_regulator_enable(REGULATOR_LDO6, true); + // Initialize I2C3. pinmux_config_i2c(I2C_3); clock_enable_i2c(I2C_3); i2c_init(I2C_3); + usleep(1000); + + // Set Touch Reset pin. + gpio_write(GPIO_PORT_J, GPIO_PIN_7, GPIO_HIGH); + usleep(10000); // Wait for the touchscreen module to get ready. touch_wait_event(STMFTS_EV_CONTROLLER_READY, 0, 20, NULL); diff --git a/bdk/libs/compr/blz.c b/bdk/libs/compr/blz.c index 685ef4a..5bc9e49 100644 --- a/bdk/libs/compr/blz.c +++ b/bdk/libs/compr/blz.c @@ -20,33 +20,33 @@ #include "blz.h" -const blz_footer *blz_get_footer(const unsigned char *compData, unsigned int compDataLen, blz_footer *outFooter) +const blz_footer *blz_get_footer(const u8 *comp_data, u32 comp_data_size, blz_footer *out_footer) { - if (compDataLen < sizeof(blz_footer)) + if (comp_data_size < sizeof(blz_footer)) return NULL; - const blz_footer *srcFooter = (const blz_footer*)&compData[compDataLen - sizeof(blz_footer)]; - if (outFooter != NULL) - memcpy(outFooter, srcFooter, sizeof(blz_footer)); // Must be a memcpy because no umaligned accesses on ARMv4. + const blz_footer *src_footer = (const blz_footer *)&comp_data[comp_data_size - sizeof(blz_footer)]; + if (out_footer) + memcpy(out_footer, src_footer, sizeof(blz_footer)); // Must be a memcpy because no unaligned accesses on ARMv4. - return srcFooter; + return src_footer; } // From https://github.com/SciresM/hactool/blob/master/kip.c which is exactly how kernel does it, thanks SciresM! -int blz_uncompress_inplace(unsigned char *dataBuf, unsigned int compSize, const blz_footer *footer) +int blz_uncompress_inplace(u8 *data, u32 comp_size, const blz_footer *footer) { u32 addl_size = footer->addl_size; u32 header_size = footer->header_size; u32 cmp_and_hdr_size = footer->cmp_and_hdr_size; - unsigned char* cmp_start = &dataBuf[compSize] - cmp_and_hdr_size; + u8 *cmp_start = &data[comp_size] - cmp_and_hdr_size; u32 cmp_ofs = cmp_and_hdr_size - header_size; u32 out_ofs = cmp_and_hdr_size + addl_size; while (out_ofs) { - unsigned char control = cmp_start[--cmp_ofs]; - for (unsigned int i=0; i<8; i++) + u8 control = cmp_start[--cmp_ofs]; + for (u32 i = 0; i < 8; i++) { if (control & 0x80) { @@ -54,45 +54,48 @@ int blz_uncompress_inplace(unsigned char *dataBuf, unsigned int compSize, const return 0; // Out of bounds. cmp_ofs -= 2; - u16 seg_val = ((unsigned int)(cmp_start[cmp_ofs + 1]) << 8) | cmp_start[cmp_ofs]; + u16 seg_val = ((u32)(cmp_start[cmp_ofs + 1]) << 8) | cmp_start[cmp_ofs]; u32 seg_size = ((seg_val >> 12) & 0xF) + 3; u32 seg_ofs = (seg_val & 0x0FFF) + 3; - if (out_ofs < seg_size) // Kernel restricts segment copy to stay in bounds. + + // Kernel restricts segment copy to stay in bounds. + if (out_ofs < seg_size) seg_size = out_ofs; out_ofs -= seg_size; - for (unsigned int j = 0; j < seg_size; j++) + for (u32 j = 0; j < seg_size; j++) cmp_start[out_ofs + j] = cmp_start[out_ofs + j + seg_ofs]; } - else + else // Copy directly. { - // Copy directly. if (cmp_ofs < 1) - return 0; //out of bounds + return 0; // Out of bounds. cmp_start[--out_ofs] = cmp_start[--cmp_ofs]; } + control <<= 1; - if (out_ofs == 0) // Blz works backwards, so if it reaches byte 0, it's done. + + if (!out_ofs) // Blz works backwards, so if it reaches byte 0, it's done. return 1; - } } + } return 1; } -int blz_uncompress_srcdest(const unsigned char *compData, unsigned int compDataLen, unsigned char *dstData, unsigned int dstSize) +int blz_uncompress_srcdest(const u8 *comp_data, u32 comp_data_size, u8 *dst_data, u32 dst_size) { blz_footer footer; - const blz_footer *compFooterPtr = blz_get_footer(compData, compDataLen, &footer); - if (compFooterPtr == NULL) + const blz_footer *comp_footer = blz_get_footer(comp_data, comp_data_size, &footer); + if (!comp_footer) return 0; - // Decompression must be done in-place, so need to copy the relevant compressed data first. - unsigned int numCompBytes = (const unsigned char*)(compFooterPtr)-compData; - memcpy(dstData, compData, numCompBytes); - memset(&dstData[numCompBytes], 0, dstSize - numCompBytes); + // Decompression happens in-place, so need to copy the relevant compressed data first. + u32 comp_bytes = (const u8 *)comp_footer - comp_data; + memcpy(dst_data, comp_data, comp_bytes); + memset(&dst_data[comp_bytes], 0, dst_size - comp_bytes); - return blz_uncompress_inplace(dstData, compDataLen, &footer); + return blz_uncompress_inplace(dst_data, comp_data_size, &footer); } diff --git a/bdk/libs/compr/blz.h b/bdk/libs/compr/blz.h index a1cce37..bb058d8 100644 --- a/bdk/libs/compr/blz.h +++ b/bdk/libs/compr/blz.h @@ -26,11 +26,11 @@ typedef struct _blz_footer u32 addl_size; } blz_footer; -// Returns pointer to footer in compData if present, additionally copies it to outFooter if not NULL. -const blz_footer *blz_get_footer(const unsigned char *compData, unsigned int compDataLen, blz_footer *outFooter); +// Returns pointer to footer in comp_data if present, additionally copies it to out_footer if not NULL. +const blz_footer *blz_get_footer(const u8 *comp_data, u32 comp_data_size, blz_footer *out_footer); // Returns 0 on failure. -int blz_uncompress_inplace(unsigned char *dataBuf, unsigned int compSize, const blz_footer *footer); +int blz_uncompress_inplace(u8 *data, u32 comp_size, const blz_footer *footer); // Returns 0 on failure. -int blz_uncompress_srcdest(const unsigned char *compData, unsigned int compDataLen, unsigned char *dstData, unsigned int dstSize); +int blz_uncompress_srcdest(const u8 *comp_data, u32 comp_data_size, u8 *dst_data, u32 dst_size); #endif diff --git a/bdk/libs/compr/lz4.c b/bdk/libs/compr/lz4.c index 4f6f425..d6c22c6 100644 --- a/bdk/libs/compr/lz4.c +++ b/bdk/libs/compr/lz4.c @@ -92,22 +92,12 @@ # define LZ4_FORCE_O2_INLINE_GCC_PPC64LE static #endif -#if (defined(__GNUC__) && (__GNUC__ >= 3)) || (defined(__INTEL_COMPILER) && (__INTEL_COMPILER >= 800)) || defined(__clang__) -# define expect(expr,value) (__builtin_expect ((expr),(value)) ) -#else -# define expect(expr,value) (expr) -#endif - -#define likely(expr) expect((expr) != 0, 1) -#define unlikely(expr) expect((expr) != 0, 0) - - /*-************************************ * Memory routines **************************************/ #include /* malloc, calloc, free */ #define ALLOC(s) malloc(s) -#define ALLOC_AND_ZERO(s) calloc(1,s) +#define ALLOC_AND_ZERO(s) zalloc(s) #define FREEMEM free #include /* memset, memcpy */ #define MEM_INIT memset diff --git a/bdk/libs/fatfs/ff.c b/bdk/libs/fatfs/ff.c index 75e0271..109e87b 100644 --- a/bdk/libs/fatfs/ff.c +++ b/bdk/libs/fatfs/ff.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -3274,7 +3274,6 @@ static FRESULT find_volume ( /* FR_OK(0): successful, !=0: an error occurred */ stat = disk_status(fs->pdrv); if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */ if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check write protection if needed */ - EFSPRINTF("WPEN1"); return FR_WRITE_PROTECTED; } return FR_OK; /* The filesystem object is valid */ @@ -3289,11 +3288,9 @@ static FRESULT find_volume ( /* FR_OK(0): successful, !=0: an error occurred */ fs->pdrv = LD2PD(vol); /* Bind the logical drive and a physical drive */ stat = disk_initialize(fs->pdrv); /* Initialize the physical drive */ if (stat & STA_NOINIT) { /* Check if the initialization succeeded */ - EFSPRINTF("MDNR"); return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */ } if (!FF_FS_READONLY && mode && (stat & STA_PROTECT)) { /* Check disk write protection if needed */ - EFSPRINTF("WPEN2"); return FR_WRITE_PROTECTED; } #if FF_MAX_SS != FF_MIN_SS /* Get sector size (multiple sector size cfg only) */ @@ -4701,20 +4698,27 @@ FRESULT f_lseek ( DWORD *f_expand_cltbl ( FIL* fp, /* Pointer to the file object */ - UINT tblsz, /* Size of table */ + UINT tblsz, /* Size of table (2 DWORDs + 2 DWORDs per fragment) */ FSIZE_t ofs /* File pointer from top of file */ ) { + /* + * Cluster table structure: + * Size (DWORD) + * Padding (DWORD) + * (Cluster Offset (DWORD) + Sequential clusters (DWORD)) * Fragments + */ if (fp->flag & FA_WRITE) f_lseek(fp, ofs); /* Expand file if write is enabled */ if (!fp->cltbl) { /* Allocate memory for cluster link table */ fp->cltbl = (DWORD *)ff_memalloc(tblsz); + if (!fp->cltbl) return (void *)0; fp->cltbl[0] = tblsz; } if (f_lseek(fp, CREATE_LINKMAP)) { /* Create cluster link table */ ff_memfree(fp->cltbl); - fp->cltbl = NULL; + fp->cltbl = (void *)0; EFSPRINTF("CLTBLSZ"); - return NULL; + return (void *)0; } f_lseek(fp, 0); @@ -5882,7 +5886,7 @@ FRESULT f_mkfs ( stat = disk_initialize(pdrv); if (stat & STA_NOINIT) return FR_NOT_READY; if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; - if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 32768 || (sz_blk & (sz_blk - 1))) sz_blk = 1; /* Erase block to align data area */ + if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &sz_blk) != RES_OK || !sz_blk || sz_blk > 131072 || (sz_blk & (sz_blk - 1))) sz_blk = 2048; /* Erase block to align data area. 1MB minimum */ #if FF_MAX_SS != FF_MIN_SS /* Get sector size of the medium if variable sector size cfg. */ if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &ss) != RES_OK) return FR_DISK_ERR; if (ss > FF_MAX_SS || ss < FF_MIN_SS || (ss & (ss - 1))) return FR_DISK_ERR; @@ -5918,7 +5922,7 @@ FRESULT f_mkfs ( } else { /* Create a single-partition in this function */ if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_vol) != RES_OK) LEAVE_MKFS(FR_DISK_ERR); - b_vol = (opt & FM_SFD) ? 0 : 32768; /* Volume start sector. Align to 16MB */ + b_vol = (opt & FM_SFD) ? 0 : sz_blk; /* Volume start sector */ if (sz_vol < b_vol) LEAVE_MKFS(FR_MKFS_ABORTED); sz_vol -= b_vol; /* Volume size */ } @@ -6231,8 +6235,13 @@ FRESULT f_mkfs ( mem_set(buf, 0, ss); st_dword(buf + FSI_LeadSig, 0x41615252); st_dword(buf + FSI_StrucSig, 0x61417272); - st_dword(buf + FSI_Free_Count, n_clst - 1); /* Number of free clusters */ - st_dword(buf + FSI_Nxt_Free, 2); /* Last allocated cluster# */ + if (opt & FM_PRF2) { + st_dword(buf + FSI_Free_Count, 0xFFFFFFFF); /* Invalidate free count */ + st_dword(buf + FSI_Nxt_Free, 0xFFFFFFFF); /* Invalidate last allocated cluster */ + } else { + st_dword(buf + FSI_Free_Count, n_clst - 1); /* Number of free clusters */ + st_dword(buf + FSI_Nxt_Free, 2); /* Last allocated cluster# */ + } st_word(buf + BS_55AA, 0xAA55); disk_write(pdrv, buf, b_vol + 7, 1); /* Write backup FSINFO (VBR + 7) */ disk_write(pdrv, buf, b_vol + 1, 1); /* Write original FSINFO (VBR + 1) */ @@ -6241,11 +6250,18 @@ FRESULT f_mkfs ( /* Create PRF2SAFE info */ if (fmt == FS_FAT32 && opt & FM_PRF2) { mem_set(buf, 0, ss); - buf[16] = 0x64; /* Record type */ - st_dword(buf + 32, 0x03); /* Unknown. SYSTEM: 0x3F00. USER: 0x03. Volatile. */ - st_dword(buf + 36, 25); /* Entries. SYSTEM: 22. USER: 25.Static? */ - st_dword(buf + 508, 0x517BBFE0); /* Custom CRC32. SYSTEM: 0x6B673904. USER: 0x517BBFE0. */ - disk_write(pdrv, buf, b_vol + 3, 1); /* Write PRF2SAFE info (VBR + 3) */ + st_dword(buf + 0, 0x32465250); /* Magic PRF2 */ + st_dword(buf + 4, 0x45464153); /* Magic SAFE */ + buf[16] = 0x64; /* Record type */ + st_dword(buf + 32, 0x03); /* Unknown. SYSTEM: 0x3F00. USER: 0x03. Volatile. */ + if (sz_vol < 0x1000000) { + st_dword(buf + 36, 21 + 1); /* 22 Entries. */ + st_dword(buf + 508, 0x90BB2F39); /* Sector CRC32 */ + } else { + st_dword(buf + 36, 21 + 2); /* 23 Entries. */ + st_dword(buf + 508, 0x5EA8AFC8); /* Sector CRC32 */ + } + disk_write(pdrv, buf, b_vol + 3, 1); /* Write PRF2SAFE info (VBR + 3) */ } /* Initialize FAT area */ @@ -6737,6 +6753,8 @@ int f_puts ( putbuff pb; + if (str == (void *)0) return EOF; /* String is NULL */ + putc_init(&pb, fp); while (*str) putc_bfd(&pb, *str++); /* Put the string */ return putc_flush(&pb); @@ -6763,6 +6781,8 @@ int f_printf ( TCHAR c, d, str[32], *p; + if (fmt == (void *)0) return EOF; /* String is NULL */ + putc_init(&pb, fp); va_start(arp, fmt); diff --git a/nyx/nyx_gui/libs/fatfs/ffsystem.c b/bdk/libs/fatfs/ffsystem.c similarity index 79% rename from nyx/nyx_gui/libs/fatfs/ffsystem.c rename to bdk/libs/fatfs/ffsystem.c index cdd2a7a..b4af454 100644 --- a/nyx/nyx_gui/libs/fatfs/ffsystem.c +++ b/bdk/libs/fatfs/ffsystem.c @@ -1,16 +1,12 @@ /*------------------------------------------------------------------------*/ /* Sample Code of OS Dependent Functions for FatFs */ -/* (C) ChaN, 2018 */ -/* (C) CTCaer, 2018 */ +/* (C) ChaN, 2018 */ +/* (C) CTCaer, 2018-2024 */ /*------------------------------------------------------------------------*/ +#include #include -#include "../../config.h" -#include -#include - -extern nyx_config n_cfg; #if FF_USE_LFN == 3 /* Dynamic memory allocation */ @@ -22,7 +18,8 @@ void* ff_memalloc ( /* Returns pointer to the allocated memory block (null if no UINT msize /* Number of bytes to allocate */ ) { - return malloc(msize); /* Allocate a new memory block with POSIX API */ + // Ensure size is aligned to SDMMC block size. + return malloc(ALIGN(msize, SDMMC_DAT_BLOCKSIZE)); /* Allocate a new memory block with POSIX API */ } @@ -51,12 +48,7 @@ DWORD get_fattime ( { rtc_time_t time; - max77620_rtc_get_time(&time); - if (n_cfg.timeoff) - { - u32 epoch = (u32)((s32)max77620_rtc_date_to_epoch(&time) + (s32)n_cfg.timeoff); - max77620_rtc_epoch_to_date(epoch, &time); - } + max77620_rtc_get_time_adjusted(&time); return (((DWORD)(time.year - 1980) << 25) | ((DWORD)time.month << 21) | ((DWORD)time.day << 16) | ((DWORD)time.hour << 11) | ((DWORD)time.min << 5) | (time.sec >> 1)); diff --git a/bdk/libs/lv_conf.h b/bdk/libs/lv_conf.h index 7af36a4..89dc555 100644 --- a/bdk/libs/lv_conf.h +++ b/bdk/libs/lv_conf.h @@ -17,7 +17,7 @@ #ifndef LV_CONF_H #define LV_CONF_H -#include +#include #include /*=================== Dynamic memory @@ -147,10 +147,10 @@ #define LV_COMPILER_VLA_SUPPORTED 1 /* 1: Variable length array is supported*/ /*HAL settings*/ -#define LV_TICK_CUSTOM 1 /*1: use a custom tick source (removing the need to manually update the tick with `lv_tick_inc`) */ +#define LV_TICK_CUSTOM 1 /*1: use a custom tick source (removing the need to manually update the tick with `lv_tick_inc`) */ #if LV_TICK_CUSTOM == 1 -#define LV_TICK_CUSTOM_INCLUDE /*Header for the sys time function*/ -#define LV_TICK_CUSTOM_SYS_TIME_EXPR (get_tmr_ms()) /*Expression evaluating to current systime in ms*/ +#define LV_TICK_CUSTOM_INCLUDE /*Header for the sys time function*/ +#define LV_TICK_CUSTOM_SYS_TIME_EXPR ((u32)get_tmr_ms()) /*Expression evaluating to current systime in ms*/ #endif /*LV_TICK_CUSTOM*/ @@ -296,6 +296,9 @@ /*Message box (dependencies: lv_rect, lv_btnm, lv_label)*/ #define USE_LV_MBOX 1 +#if USE_LV_MBOX != 0 +# define LV_MBOX_CLOSE_ANIM_TIME 200 /*ms*/ +#endif /*Text area (dependencies: lv_label, lv_page)*/ #define USE_LV_TA 1 diff --git a/bdk/libs/lvgl/lv_core/lv_group.c b/bdk/libs/lvgl/lv_core/lv_group.c index 3fd4120..cedef7f 100644 --- a/bdk/libs/lvgl/lv_core/lv_group.c +++ b/bdk/libs/lvgl/lv_core/lv_group.c @@ -546,8 +546,8 @@ static void obj_to_foreground(lv_obj_t * obj) /*Move the last_top object to the foreground*/ lv_obj_t * par = lv_obj_get_parent(last_top); /*After list change it will be the new head*/ - lv_ll_chg_list(&par->child_ll, &par->child_ll, last_top); - lv_obj_invalidate(last_top); + if (lv_ll_chg_list(&par->child_ll, &par->child_ll, last_top)) + lv_obj_invalidate(last_top); /*Only invalidate if not top*/ } } diff --git a/bdk/libs/lvgl/lv_core/lv_indev.c b/bdk/libs/lvgl/lv_core/lv_indev.c index 763abf7..d1dc582 100644 --- a/bdk/libs/lvgl/lv_core/lv_indev.c +++ b/bdk/libs/lvgl/lv_core/lv_indev.c @@ -646,8 +646,8 @@ static void indev_proc_press(lv_indev_proc_t * proc) /*Move the last_top object to the foreground*/ lv_obj_t * par = lv_obj_get_parent(last_top); /*After list change it will be the new head*/ - lv_ll_chg_list(&par->child_ll, &par->child_ll, last_top); - lv_obj_invalidate(last_top); + if (lv_ll_chg_list(&par->child_ll, &par->child_ll, last_top)) + lv_obj_invalidate(last_top); /*Only invalidate if not top*/ } /*Send a signal about the press*/ diff --git a/bdk/libs/lvgl/lv_misc/lv_color.h b/bdk/libs/lvgl/lv_misc/lv_color.h index 3459b63..59f038f 100644 --- a/bdk/libs/lvgl/lv_misc/lv_color.h +++ b/bdk/libs/lvgl/lv_misc/lv_color.h @@ -412,17 +412,17 @@ static inline uint8_t lv_color_brightness(lv_color_t color) #endif #if LV_COLOR_DEPTH == 32 // Concatenate into one 32-bit set. -#define LV_COLOR_HEX(c) ((lv_color_t){.full = (c | 0xFF000000)}) +#define LV_COLOR_HEX(c) ((lv_color_t){.full = ((c) | 0xFF000000)}) #else -#define LV_COLOR_HEX(c) LV_COLOR_MAKE(((uint32_t)((uint32_t)c >> 16) & 0xFF), \ - ((uint32_t)((uint32_t)c >> 8) & 0xFF), \ - ((uint32_t) c & 0xFF)) +#define LV_COLOR_HEX(c) LV_COLOR_MAKE(((uint32_t)((uint32_t)(c) >> 16) & 0xFF), \ + ((uint32_t)((uint32_t)(c) >> 8) & 0xFF), \ + ((uint32_t) (c) & 0xFF)) #endif /*Usage LV_COLOR_HEX3(0x16C) which means LV_COLOR_HEX(0x1166CC)*/ -#define LV_COLOR_HEX3(c) LV_COLOR_MAKE((((c >> 4) & 0xF0) | ((c >> 8) & 0xF)), \ - ((uint32_t)(c & 0xF0) | ((c & 0xF0) >> 4)), \ - ((uint32_t)(c & 0xF) | ((c & 0xF) << 4))) +#define LV_COLOR_HEX3(c) LV_COLOR_MAKE(((((c) >> 4) & 0xF0) | (((c) >> 8) & 0xF)), \ + ((uint32_t)((c) & 0xF0) | (((c) & 0xF0) >> 4)), \ + ((uint32_t)((c) & 0xF) | (((c) & 0xF) << 4))) /** diff --git a/bdk/libs/lvgl/lv_misc/lv_ll.c b/bdk/libs/lvgl/lv_misc/lv_ll.c index 43d8847..5583311 100644 --- a/bdk/libs/lvgl/lv_misc/lv_ll.c +++ b/bdk/libs/lvgl/lv_misc/lv_ll.c @@ -215,9 +215,12 @@ void lv_ll_clear(lv_ll_t * ll_p) * @param ll_ori_p pointer to the original (old) linked list * @param ll_new_p pointer to the new linked list * @param node pointer to a node + * @return head changed */ -void lv_ll_chg_list(lv_ll_t * ll_ori_p, lv_ll_t * ll_new_p, void * node) +bool lv_ll_chg_list(lv_ll_t * ll_ori_p, lv_ll_t * ll_new_p, void * node) { + bool changed = ll_new_p->head != node; + lv_ll_rem(ll_ori_p, node); /*Set node as head*/ @@ -232,6 +235,8 @@ void lv_ll_chg_list(lv_ll_t * ll_ori_p, lv_ll_t * ll_new_p, void * node) if(ll_new_p->tail == NULL) { /*If there is no tail (first node) set the tail too*/ ll_new_p->tail = node; } + + return changed; } /** diff --git a/bdk/libs/lvgl/lv_misc/lv_ll.h b/bdk/libs/lvgl/lv_misc/lv_ll.h index 086ba40..5bde7e5 100644 --- a/bdk/libs/lvgl/lv_misc/lv_ll.h +++ b/bdk/libs/lvgl/lv_misc/lv_ll.h @@ -89,8 +89,9 @@ void lv_ll_clear(lv_ll_t * ll_p); * @param ll_ori_p pointer to the original (old) linked list * @param ll_new_p pointer to the new linked list * @param node pointer to a node + * @return head changed */ -void lv_ll_chg_list(lv_ll_t * ll_ori_p, lv_ll_t * ll_new_p, void * node); +bool lv_ll_chg_list(lv_ll_t * ll_ori_p, lv_ll_t * ll_new_p, void * node); /** * Return with head node of the linked list diff --git a/bdk/libs/lvgl/lv_themes/lv_theme_hekate.c b/bdk/libs/lvgl/lv_themes/lv_theme_hekate.c index d12732c..f151dbe 100644 --- a/bdk/libs/lvgl/lv_themes/lv_theme_hekate.c +++ b/bdk/libs/lvgl/lv_themes/lv_theme_hekate.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019 CTCaer + * Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -32,13 +32,16 @@ #define COLOR_HOS_TEAL_LIGHT (lv_color_hsv_to_rgb(_hue, 100, 72)) // 0x00B78F #define COLOR_HOS_TEAL (lv_color_hsv_to_rgb(_hue, 100, 64)) // 0x00A273 #define COLOR_HOS_ORANGE LV_COLOR_HEX(0xFF5500) -#define COLOR_HOS_BG_DARKER LV_COLOR_HEX(0x1B1B1B) -#define COLOR_HOS_BG_DARK LV_COLOR_HEX(0x222222) -#define COLOR_HOS_BG LV_COLOR_HEX(0x2D2D2D) -#define COLOR_HOS_BG_LIGHT LV_COLOR_HEX(0x3D3D3D) -#define COLOR_HOS_LIGHT_BORDER LV_COLOR_HEX(0x4D4D4D) #define COLOR_HOS_TXT_WHITE LV_COLOR_HEX(0xFBFBFB) +#define COLOR_BG_DARKER LV_COLOR_HEX(theme_bg_color ? (theme_bg_color - 0x121212) : 0x0B0B0B) // 0x1B1B1B. +#define COLOR_BG_DARK LV_COLOR_HEX(theme_bg_color ? (theme_bg_color - 0x0B0B0B) : 0x121212) // 0x222222. +#define COLOR_BG LV_COLOR_HEX(theme_bg_color) // 0x2D2D2D. +#define COLOR_BG_LIGHT LV_COLOR_HEX(theme_bg_color ? (theme_bg_color + 0x101010) : 0x2D2D2D) // 0x3D3D3D. +#define COLOR_BG_LIGHTER LV_COLOR_HEX(theme_bg_color ? (theme_bg_color + 0x191919) : 0x363636) // 0x464646. +#define COLOR_LIGHT_BORDER LV_COLOR_HEX(theme_bg_color ? (theme_bg_color + 0x202020) : 0x3D3D3D) // 0x4D4D4D. + + /********************** * TYPEDEFS **********************/ @@ -57,8 +60,9 @@ static lv_style_t def; static lv_style_t sb; /*Saved input parameters*/ -static uint16_t _hue; +static uint16_t _hue; static lv_font_t * _font; +uint32_t theme_bg_color; /********************** * MACROS @@ -80,18 +84,17 @@ static void basic_init(void) //def.image.opa = LV_OPA_COVER; lv_style_copy(&bg, &def); - bg.body.main_color = COLOR_HOS_BG; - //bg.body.main_color = LV_COLOR_BLACK; + bg.body.main_color = COLOR_BG; bg.body.grad_color = bg.body.main_color; bg.body.radius = 0; bg.body.empty = 1; lv_style_copy(&panel, &def); panel.body.radius = DEF_RADIUS; - panel.body.main_color = COLOR_HOS_BG; - panel.body.grad_color = COLOR_HOS_BG; + panel.body.main_color = COLOR_BG; + panel.body.grad_color = COLOR_BG; panel.body.border.width = 1; - panel.body.border.color = COLOR_HOS_LIGHT_BORDER; + panel.body.border.color = COLOR_LIGHT_BORDER; panel.body.border.opa = LV_OPA_COVER; panel.body.shadow.color = COLOR_SHADOW_LIGHT; panel.body.shadow.type = LV_SHADOW_BOTTOM; @@ -129,7 +132,7 @@ static void btn_init(void) static lv_style_t rel, pr, tgl_rel, tgl_pr, ina; lv_style_copy(&rel, &def); - rel.body.main_color = COLOR_HOS_BG_LIGHT; + rel.body.main_color = COLOR_BG_LIGHT; rel.body.grad_color = rel.body.main_color; rel.body.radius = 6; rel.body.padding.hor = LV_DPI / 3; @@ -139,7 +142,7 @@ static void btn_init(void) rel.body.shadow.type = LV_SHADOW_BOTTOM; rel.body.shadow.width = 6; rel.body.border.width = 0; - rel.body.border.color = COLOR_HOS_BG_LIGHT; + rel.body.border.color = COLOR_BG_LIGHT; rel.body.border.part = LV_BORDER_FULL; //rel.text.color = COLOR_HOS_TXT_WHITE; @@ -162,7 +165,7 @@ static void btn_init(void) tgl_pr.body.shadow.width = 0; lv_style_copy(&ina, &rel); - ina.body.main_color = COLOR_HOS_BG_DARK; + ina.body.main_color = COLOR_BG_DARK; ina.body.grad_color = ina.body.main_color; //ina.body.shadow.width = 0; ina.text.color = LV_COLOR_HEX(0x888888); @@ -207,7 +210,7 @@ static void img_init(void) img_light.image.intense = LV_OPA_80; lv_style_copy(&img_dark, &def); - img_dark.image.color = COLOR_HOS_BG_DARKER; + img_dark.image.color = COLOR_BG_DARKER; img_dark.image.intense = LV_OPA_80; @@ -250,7 +253,7 @@ static void bar_init(void) static lv_style_t bar_bg, bar_indic; lv_style_copy(&bar_bg, &def); - bar_bg.body.main_color = COLOR_HOS_LIGHT_BORDER; + bar_bg.body.main_color = COLOR_LIGHT_BORDER; bar_bg.body.grad_color = bar_bg.body.main_color; bar_bg.body.radius = 3; bar_bg.body.border.width = 0; @@ -536,9 +539,9 @@ static void mbox_init(void) static lv_style_t bg; lv_style_copy(&bg, theme.panel); - bg.body.main_color = LV_COLOR_HEX(0x464646); + bg.body.main_color = COLOR_BG_LIGHTER; bg.body.grad_color = bg.body.main_color; - bg.body.shadow.color = COLOR_HOS_BG; + bg.body.shadow.color = COLOR_BG; bg.body.shadow.type = LV_SHADOW_FULL; bg.body.shadow.width = 8; @@ -628,7 +631,7 @@ static void list_init(void) // pr.text.font = _font; lv_style_copy(&tgl_rel, &pr); - tgl_rel.body.main_color = COLOR_HOS_BG_LIGHT; + tgl_rel.body.main_color = COLOR_BG_LIGHT; tgl_rel.body.grad_color = tgl_rel.body.main_color; //tgl_rel.text.color = lv_color_hsv_to_rgb(_hue, 5, 95); tgl_rel.text.color = COLOR_HOS_TEAL_LIGHTER; @@ -639,7 +642,7 @@ static void list_init(void) tgl_pr.body.border.width = 0; lv_style_copy(&ina, &pr); - ina.body.main_color = COLOR_HOS_BG_DARK; + ina.body.main_color = COLOR_BG_DARK; ina.body.grad_color = ina.body.main_color; theme.list.sb = &sb; @@ -667,7 +670,7 @@ static void ddlist_init(void) bg.text.color = COLOR_HOS_TURQUOISE; lv_style_copy(&sel, &bg); - sel.body.main_color = COLOR_HOS_BG_LIGHT; + sel.body.main_color = COLOR_BG_LIGHT; sel.body.grad_color = sel.body.main_color; theme.ddlist.bg = &bg; @@ -713,7 +716,7 @@ static void tabview_init(void) indic.body.opa = LV_OPA_0; lv_style_copy(&btn_bg, &def); - btn_bg.body.main_color = COLOR_HOS_BG; + btn_bg.body.main_color = COLOR_BG; btn_bg.body.grad_color = btn_bg.body.main_color; btn_bg.body.radius = 0; btn_bg.body.empty = 1; @@ -734,7 +737,7 @@ static void tabview_init(void) rel.text.font = _font; lv_style_copy(&pr, &def); - pr.body.main_color = COLOR_HOS_BG_LIGHT; + pr.body.main_color = COLOR_BG_LIGHT; pr.body.grad_color = pr.body.main_color; pr.body.border.width = 0; pr.body.empty = 0; @@ -750,7 +753,7 @@ static void tabview_init(void) tgl_rel.text.color = COLOR_HOS_TURQUOISE; lv_style_copy(&tgl_pr, &def); - tgl_pr.body.main_color = COLOR_HOS_BG_LIGHT; + tgl_pr.body.main_color = COLOR_BG_LIGHT; tgl_pr.body.grad_color = tgl_pr.body.main_color; tgl_pr.body.border.width = 0; tgl_pr.body.empty = 0; @@ -797,7 +800,7 @@ static void win_init(void) static lv_style_t header, rel, pr; lv_style_copy(&header, &def); - header.body.main_color = COLOR_HOS_BG; + header.body.main_color = COLOR_BG; header.body.grad_color = header.body.main_color; header.body.radius = 0; header.body.border.width = 0; @@ -843,10 +846,11 @@ static void win_init(void) * @param font pointer to a font (NULL to use the default) * @return pointer to the initialized theme */ -lv_theme_t * lv_theme_hekate_init(uint16_t hue, lv_font_t * font) +lv_theme_t * lv_theme_hekate_init(uint32_t bg_color, uint16_t hue, lv_font_t * font) { if(font == NULL) font = LV_FONT_DEFAULT; + theme_bg_color = bg_color; _hue = hue; _font = font; diff --git a/bdk/libs/lvgl/lv_themes/lv_theme_hekate.h b/bdk/libs/lvgl/lv_themes/lv_theme_hekate.h index cc61d2d..45448b9 100644 --- a/bdk/libs/lvgl/lv_themes/lv_theme_hekate.h +++ b/bdk/libs/lvgl/lv_themes/lv_theme_hekate.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019 CTCaer + * Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -35,6 +35,14 @@ extern "C" { /********************* * DEFINES *********************/ +#define COLOR_HOS_BG_BASE_DEFAULT 0x1B1B1B +#define COLOR_HOS_BG_BASE_BLACK 0x000000 + +#define COLOR_HOS_BG_DARKER 0x1B1B1B +#define COLOR_HOS_BG_DARK 0x222222 +#define COLOR_HOS_BG 0x2D2D2D +#define COLOR_HOS_BG_LIGHT 0x3D3D3D +#define COLOR_HOS_LIGHT_BORDER 0x4D4D4D /********************** * TYPEDEFS @@ -44,13 +52,15 @@ extern "C" { * GLOBAL PROTOTYPES **********************/ +extern uint32_t theme_bg_color; + /** * Initialize the material theme * @param hue [0..360] hue value from HSV color space to define the theme's base color * @param font pointer to a font (NULL to use the default) * @return pointer to the initialized theme */ -lv_theme_t * lv_theme_hekate_init(uint16_t hue, lv_font_t *font); +lv_theme_t * lv_theme_hekate_init(uint32_t bg_color, uint16_t hue, lv_font_t *font); /** * Get a pointer to the theme diff --git a/bdk/mem/emc.h b/bdk/mem/emc.h index ea5420a..a1b4c3a 100644 --- a/bdk/mem/emc.h +++ b/bdk/mem/emc.h @@ -2,7 +2,7 @@ * arch/arm/mach-tegra/tegra21_emc.h * * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. - * Copyright (c) 2019-2020, CTCaer. + * Copyright (c) 2019-2024, CTCaer. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,6 +23,7 @@ #ifndef _EMC_H_ #define _EMC_H_ +#define EMC_INTSTATUS 0x0 #define EMC_DBG 0x8 #define EMC_CFG 0xC #define EMC_CONFIG_SAMPLE_DELAY 0x5f0 @@ -698,6 +699,8 @@ typedef enum _emc_mr_t { + MR0_FEAT = 0, + MR4_TEMP = 4, MR5_MAN_ID = 5, MR6_REV_ID1 = 6, MR7_REV_ID2 = 7, @@ -710,7 +713,7 @@ enum EMC_CHAN1 = 1 }; -typedef struct _emc_mr_data_t +typedef struct _emc_mr_chip_data_t { // Device 0. u8 rank0_ch0; @@ -719,6 +722,12 @@ typedef struct _emc_mr_data_t // Device 1. u8 rank1_ch0; u8 rank1_ch1; +} emc_mr_chip_data_t; + +typedef struct _emc_mr_data_t +{ + emc_mr_chip_data_t chip0; + emc_mr_chip_data_t chip1; } emc_mr_data_t; #endif diff --git a/bdk/mem/heap.c b/bdk/mem/heap.c index d249140..ad70729 100644 --- a/bdk/mem/heap.c +++ b/bdk/mem/heap.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,33 +19,44 @@ #include "heap.h" #include -static void _heap_create(heap_t *heap, u32 start) +heap_t _heap; + +static void _heap_create(void *start) { - heap->start = start; - heap->first = NULL; + _heap.start = start; + _heap.first = NULL; + _heap.last = NULL; } // Node info is before node address. -static u32 _heap_alloc(heap_t *heap, u32 size) +static void *_heap_alloc(u32 size) { hnode_t *node, *new_node; // Align to cache line size. size = ALIGN(size, sizeof(hnode_t)); - if (!heap->first) + // First allocation. + if (!_heap.first) { - node = (hnode_t *)heap->start; + node = (hnode_t *)_heap.start; node->used = 1; node->size = size; node->prev = NULL; node->next = NULL; - heap->first = node; - return (u32)node + sizeof(hnode_t); + _heap.first = node; + _heap.last = node; + + return (void *)node + sizeof(hnode_t); } - node = heap->first; +#ifdef BDK_MALLOC_NO_DEFRAG + // Get the last allocated block. + node = _heap.last; +#else + // Get first block and find the first available one. + node = _heap.first; while (true) { // Check if there's available unused node. @@ -53,7 +64,7 @@ static u32 _heap_alloc(heap_t *heap, u32 size) { // Size and offset of the new unused node. u32 new_size = node->size - size; - new_node = (hnode_t *)((u32)node + sizeof(hnode_t) + size); + new_node = (hnode_t *)((void *)node + sizeof(hnode_t) + size); // If there's aligned unused space from the old node, // create a new one and set the leftover size. @@ -76,7 +87,7 @@ static u32 _heap_alloc(heap_t *heap, u32 size) node->size = size; node->used = 1; - return (u32)node + sizeof(hnode_t); + return (void *)node + sizeof(hnode_t); } // No unused node found, try the next one. @@ -85,23 +96,29 @@ static u32 _heap_alloc(heap_t *heap, u32 size) else break; } +#endif // No unused node found, create a new one. - new_node = (hnode_t *)((u32)node + sizeof(hnode_t) + node->size); + new_node = (hnode_t *)((void *)node + sizeof(hnode_t) + node->size); new_node->used = 1; new_node->size = size; new_node->prev = node; new_node->next = NULL; - node->next = new_node; - return (u32)new_node + sizeof(hnode_t); + node->next = new_node; + _heap.last = new_node; + + return (void *)new_node + sizeof(hnode_t); } -static void _heap_free(heap_t *heap, u32 addr) +static void _heap_free(void *addr) { hnode_t *node = (hnode_t *)(addr - sizeof(hnode_t)); node->used = 0; - node = heap->first; + node = _heap.first; + +#ifndef BDK_MALLOC_NO_DEFRAG + // Do simple defragmentation on next blocks. while (node) { if (!node->used) @@ -117,36 +134,42 @@ static void _heap_free(heap_t *heap, u32 addr) } node = node->next; } +#endif } -heap_t _heap; - -void heap_init(u32 base) +void heap_init(void *base) { - _heap_create(&_heap, base); + _heap_create(base); } -void heap_copy(heap_t *heap) +void heap_set(heap_t *heap) { memcpy(&_heap, heap, sizeof(heap_t)); } void *malloc(u32 size) { - return (void *)_heap_alloc(&_heap, size); + return _heap_alloc(size); } void *calloc(u32 num, u32 size) { - void *res = (void *)_heap_alloc(&_heap, num * size); + void *res = (void *)_heap_alloc(num * size); memset(res, 0, ALIGN(num * size, sizeof(hnode_t))); // Clear the aligned size. return res; } +void *zalloc(u32 size) +{ + void *res = (void *)_heap_alloc(size); + memset(res, 0, ALIGN(size, sizeof(hnode_t))); // Clear the aligned size. + return res; +} + void free(void *buf) { - if ((u32)buf >= _heap.start) - _heap_free(&_heap, (u32)buf); + if (buf >= _heap.start) + _heap_free(buf); } void heap_monitor(heap_monitor_t *mon, bool print_node_stats) @@ -158,7 +181,10 @@ void heap_monitor(heap_monitor_t *mon, bool print_node_stats) while (true) { if (node->used) + { + mon->nodes_used++; mon->used += node->size + sizeof(hnode_t); + } else mon->total += node->size + sizeof(hnode_t); @@ -174,4 +200,5 @@ void heap_monitor(heap_monitor_t *mon, bool print_node_stats) break; } mon->total += mon->used; + mon->nodes_total = count; } diff --git a/bdk/mem/heap.h b/bdk/mem/heap.h index 811f13d..c898ee0 100644 --- a/bdk/mem/heap.h +++ b/bdk/mem/heap.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -31,20 +31,24 @@ typedef struct _hnode typedef struct _heap { - u32 start; + void *start; hnode_t *first; + hnode_t *last; } heap_t; typedef struct { - u32 total; - u32 used; + u32 total; + u32 used; + u32 nodes_total; + u32 nodes_used; } heap_monitor_t; -void heap_init(u32 base); -void heap_copy(heap_t *heap); +void heap_init(void *base); +void heap_set(heap_t *heap); void *malloc(u32 size); void *calloc(u32 num, u32 size); +void *zalloc(u32 size); void free(void *buf); void heap_monitor(heap_monitor_t *mon, bool print_node_stats); diff --git a/bdk/mem/mc.c b/bdk/mem/mc.c index d577bd7..4e6ede6 100644 --- a/bdk/mem/mc.c +++ b/bdk/mem/mc.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,13 +17,11 @@ #include #include +#include #include #include -#include -//#define CONFIG_ENABLE_AHB_REDIRECT - -void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock) +void mc_config_tzdram_carveout(u32 bom, u32 size1mb, bool lock) { MC(MC_SEC_CARVEOUT_BOM) = bom; MC(MC_SEC_CARVEOUT_SIZE_MB) = size1mb; @@ -33,105 +31,56 @@ void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock) void mc_config_carveout() { + // Enable ACR GSR3. *(vu32 *)0x8005FFFC = 0xC0EDBBCC; MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = 1; MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = 0; MC(MC_VIDEO_PROTECT_BOM) = 0; - MC(MC_VIDEO_PROTECT_SIZE_MB) = 0; - MC(MC_VIDEO_PROTECT_REG_CTRL) = 1; + MC(MC_VIDEO_PROTECT_REG_CTRL) = VPR_CTRL_LOCKED; - // Configure TSEC carveout @ 0x90000000, 1MB. - //mc_config_tsec_carveout(0x90000000, 1, false); - mc_config_tsec_carveout(0, 0, true); + // Configure TZDRAM carveout @ 0x90000000, 1MB. + //mc_config_tzdram_carveout(0x90000000, 1, false); + mc_config_tzdram_carveout(0, 0, true); MC(MC_MTS_CARVEOUT_BOM) = 0; - MC(MC_MTS_CARVEOUT_SIZE_MB) = 0; - MC(MC_MTS_CARVEOUT_ADR_HI) = 0; MC(MC_MTS_CARVEOUT_REG_CTRL) = 1; - MC(MC_SECURITY_CARVEOUT1_BOM) = 0; - MC(MC_SECURITY_CARVEOUT1_BOM_HI) = 0; MC(MC_SECURITY_CARVEOUT1_SIZE_128KB) = 0; - MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0) = 0; - MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1) = 0; MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2) = 0; MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3) = 0; - MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4) = 0; - MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; - MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; - MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; - MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; - MC(MC_SECURITY_CARVEOUT1_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; - MC(MC_SECURITY_CARVEOUT1_CFG0) = 0x4000006; + MC(MC_SECURITY_CARVEOUT1_CFG0) = SEC_CARVEOUT_CFG_LOCKED | + SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY | + SEC_CARVEOUT_CFG_APERTURE_ID(0) | + SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH; MC(MC_SECURITY_CARVEOUT2_BOM) = 0x80020000; - MC(MC_SECURITY_CARVEOUT2_BOM_HI) = 0; - MC(MC_SECURITY_CARVEOUT2_SIZE_128KB) = 2; - MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0; - MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0; - MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = 0x3100000; - MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0; - MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = 0x300; - MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; - MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; - MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; - MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; - MC(MC_SECURITY_CARVEOUT2_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; - MC(MC_SECURITY_CARVEOUT2_CFG0) = 0x440167E; + MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = SEC_CARVEOUT_CA2_R_GPU | SEC_CARVEOUT_CA2_W_GPU | SEC_CARVEOUT_CA2_R_TSEC; - MC(MC_SECURITY_CARVEOUT3_BOM) = 0; - MC(MC_SECURITY_CARVEOUT3_BOM_HI) = 0; - MC(MC_SECURITY_CARVEOUT3_SIZE_128KB) = 0; - MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0; - MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0; - MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = 0x3000000; - MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0; - MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = 0x300; - MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; - MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; - MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; - MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; - MC(MC_SECURITY_CARVEOUT3_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; - MC(MC_SECURITY_CARVEOUT3_CFG0) = 0x4401E7E; - - MC(MC_SECURITY_CARVEOUT4_BOM) = 0; - MC(MC_SECURITY_CARVEOUT4_BOM_HI) = 0; MC(MC_SECURITY_CARVEOUT4_SIZE_128KB) = 0; - MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS0) = 0; - MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS1) = 0; MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS2) = 0; - MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS3) = 0; MC(MC_SECURITY_CARVEOUT4_CLIENT_ACCESS4) = 0; - MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; - MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; - MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; - MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; - MC(MC_SECURITY_CARVEOUT4_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; - MC(MC_SECURITY_CARVEOUT4_CFG0) = 0x8F; + MC(MC_SECURITY_CARVEOUT4_CFG0) = SEC_CARVEOUT_CFG_TZ_SECURE | + SEC_CARVEOUT_CFG_LOCKED | + SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY | + SEC_CARVEOUT_CFG_RD_NS | + SEC_CARVEOUT_CFG_WR_NS; - MC(MC_SECURITY_CARVEOUT5_BOM) = 0; - MC(MC_SECURITY_CARVEOUT5_BOM_HI) = 0; MC(MC_SECURITY_CARVEOUT5_SIZE_128KB) = 0; - MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS0) = 0; - MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS1) = 0; MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS2) = 0; - MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS3) = 0; - MC(MC_SECURITY_CARVEOUT5_CLIENT_ACCESS4) = 0; - MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS0) = 0; - MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS1) = 0; - MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS2) = 0; - MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS3) = 0; - MC(MC_SECURITY_CARVEOUT5_CLIENT_FORCE_INTERNAL_ACCESS4) = 0; - MC(MC_SECURITY_CARVEOUT5_CFG0) = 0x8F; + MC(MC_SECURITY_CARVEOUT5_CFG0) = SEC_CARVEOUT_CFG_TZ_SECURE | + SEC_CARVEOUT_CFG_LOCKED | + SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY | + SEC_CARVEOUT_CFG_RD_NS | + SEC_CARVEOUT_CFG_WR_NS; } -void mc_enable_ahb_redirect(bool full_aperture) +void mc_enable_ahb_redirect() { // Enable ARC_CLK_OVR_ON. - CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) = (CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) & 0xFFF7FFFF) | 0x80000; - //MC(MC_IRAM_REG_CTRL) &= 0xFFFFFFFE; - MC(MC_IRAM_BOM) = 0x40000000; - MC(MC_IRAM_TOM) = full_aperture ? DRAM_START : 0x4003F000; + CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) |= BIT(19); + //MC(MC_IRAM_REG_CTRL) &= ~BIT(0); + MC(MC_IRAM_BOM) = IRAM_BASE; + MC(MC_IRAM_TOM) = DRAM_START; // Default is only IRAM: 0x4003F000. } void mc_disable_ahb_redirect() @@ -139,24 +88,34 @@ void mc_disable_ahb_redirect() MC(MC_IRAM_BOM) = 0xFFFFF000; MC(MC_IRAM_TOM) = 0; // Disable IRAM_CFG_WRITE_ACCESS (sticky). - //MC(MC_IRAM_REG_CTRL) = MC(MC_IRAM_REG_CTRL) & 0xFFFFFFFE | 1; + //MC(MC_IRAM_REG_CTRL) |= BIT(0); // Disable ARC_CLK_OVR_ON. - CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) &= 0xFFF7FFFF; + CLOCK(CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD) &= ~BIT(19); +} + +bool mc_client_has_access(void *address) +{ + // Check if address is in DRAM or if arbitration for IRAM is enabled. + if ((u32)address >= DRAM_START) + return true; // Access by default. + else if ((u32)address >= IRAM_BASE && MC(MC_IRAM_BOM) == IRAM_BASE) + return true; // Access by AHB arbitration. + + // No access to address space. + return false; } void mc_enable() { // Reset EMC source to PLLP. - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF) | 0x40000000; - // Enable memory clocks. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_EMC); - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_MEM); + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) & 0x1FFFFFFF) | (2 << 29u); + // Enable and clear reset for memory clocks. + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM); CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = BIT(CLK_X_EMC_DLL); - // Clear clock resets for memory. CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM); usleep(5); -#ifdef CONFIG_ENABLE_AHB_REDIRECT +#ifdef BDK_MC_ENABLE_AHB_REDIRECT mc_enable_ahb_redirect(); #else mc_disable_ahb_redirect(); diff --git a/bdk/mem/mc.h b/bdk/mem/mc.h index d873c7d..300bbfd 100644 --- a/bdk/mem/mc.h +++ b/bdk/mem/mc.h @@ -23,8 +23,9 @@ void mc_config_tsec_carveout(u32 bom, u32 size1mb, bool lock); void mc_config_carveout(); void mc_config_carveout_finalize(); -void mc_enable_ahb_redirect(bool full_aperture); +void mc_enable_ahb_redirect(); void mc_disable_ahb_redirect(); +bool mc_client_has_access(void *address); void mc_enable(); #endif diff --git a/bdk/mem/mc_t210.h b/bdk/mem/mc_t210.h index a7a9877..ff96b9d 100644 --- a/bdk/mem/mc_t210.h +++ b/bdk/mem/mc_t210.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2014, NVIDIA Corporation. All rights reserved. + * Copyright (c) 2014, NVIDIA Corporation. + * Copyright (c) 2018-2023, CTCaer * * This software is licensed under the terms of the GNU General Public * License version 2, as published by the Free Software Foundation, and @@ -14,6 +15,22 @@ #ifndef _MC_T210_H_ #define _MC_T210_H_ +/*! MC SMMU registers */ +#define MC_SMMU_CONFIG 0x10 +#define MC_SMMU_TLB_CONFIG 0x14 +#define MC_SMMU_PTC_CONFIG 0x18 +#define MC_SMMU_PTB_ASID 0x1c +#define MC_SMMU_PTB_DATA 0x20 +#define MC_SMMU_TLB_FLUSH 0x30 +#define MC_SMMU_PTC_FLUSH 0x34 +#define MC_SMMU_ASID_SECURITY 0x38 +#define MC_SMMU_TRANSLATION_ENABLE_0 0x228 +#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c +#define MC_SMMU_TRANSLATION_ENABLE_2 0x230 +#define MC_SMMU_TRANSLATION_ENABLE_3 0x234 +#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98 + +/*! MC General registers */ #define MC_INTSTATUS 0x0 #define MC_INTMASK 0x4 #define MC_ERR_STATUS 0x8 @@ -464,11 +481,111 @@ #define MC_UNTRANSLATED_REGION_CHECK 0x948 #define MC_DA_CONFIG0 0x9dc +/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS0 */ +#define SEC_CARVEOUT_CA0_R_PTCR BIT(0) +#define SEC_CARVEOUT_CA0_R_DISPLAY0A BIT(1) +#define SEC_CARVEOUT_CA0_R_DISPLAY0AB BIT(2) +#define SEC_CARVEOUT_CA0_R_DISPLAY0B BIT(3) +#define SEC_CARVEOUT_CA0_R_DISPLAY0BB BIT(4) +#define SEC_CARVEOUT_CA0_R_DISPLAY0C BIT(5) +#define SEC_CARVEOUT_CA0_R_DISPLAY0CB BIT(6) +#define SEC_CARVEOUT_CA0_R_AFI BIT(14) +#define SEC_CARVEOUT_CA0_R_BPMP_C BIT(15) +#define SEC_CARVEOUT_CA0_R_DISPLAYHC BIT(16) +#define SEC_CARVEOUT_CA0_R_DISPLAYHCB BIT(17) +#define SEC_CARVEOUT_CA0_R_HDA BIT(21) +#define SEC_CARVEOUT_CA0_R_HOST1XDMA BIT(22) +#define SEC_CARVEOUT_CA0_R_HOST1X BIT(23) +#define SEC_CARVEOUT_CA0_R_NVENC BIT(28) +#define SEC_CARVEOUT_CA0_R_PPCSAHBDMA BIT(29) +#define SEC_CARVEOUT_CA0_R_PPCSAHBSLV BIT(30) +#define SEC_CARVEOUT_CA0_R_SATAR BIT(31) + +/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS1 */ +#define SEC_CARVEOUT_CA1_R_VDEBSEV BIT(2) +#define SEC_CARVEOUT_CA1_R_VDEMBE BIT(3) +#define SEC_CARVEOUT_CA1_R_VDEMCE BIT(4) +#define SEC_CARVEOUT_CA1_R_VDETPE BIT(5) +#define SEC_CARVEOUT_CA1_R_CCPLEXLP_C BIT(6) +#define SEC_CARVEOUT_CA1_R_CCPLEX_C BIT(7) +#define SEC_CARVEOUT_CA1_W_NVENC BIT(11) +#define SEC_CARVEOUT_CA1_W_AFI BIT(17) +#define SEC_CARVEOUT_CA1_W_BPMP_C BIT(18) +#define SEC_CARVEOUT_CA1_W_HDA BIT(21) +#define SEC_CARVEOUT_CA1_W_HOST1X BIT(22) +#define SEC_CARVEOUT_CA1_W_CCPLEXLP_C BIT(24) +#define SEC_CARVEOUT_CA1_W_CCPLEX_C BIT(25) +#define SEC_CARVEOUT_CA1_W_PPCSAHBDMA BIT(27) +#define SEC_CARVEOUT_CA1_W_PPCSAHBSLV BIT(28) +#define SEC_CARVEOUT_CA1_W_SATA BIT(29) +#define SEC_CARVEOUT_CA1_W_VDEBSEV BIT(30) +#define SEC_CARVEOUT_CA1_W_VDEDBG BIT(31) + +/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS2 */ +#define SEC_CARVEOUT_CA2_W_VDEMBE BIT(0) +#define SEC_CARVEOUT_CA2_W_VDETPM BIT(1) +#define SEC_CARVEOUT_CA2_R_ISPRA BIT(4) +#define SEC_CARVEOUT_CA2_W_ISPWA BIT(6) +#define SEC_CARVEOUT_CA2_W_ISPWB BIT(7) +#define SEC_CARVEOUT_CA2_R_XUSB_HOST BIT(10) +#define SEC_CARVEOUT_CA2_W_XUSB_HOST BIT(11) +#define SEC_CARVEOUT_CA2_R_XUSB_DEV BIT(12) +#define SEC_CARVEOUT_CA2_W_XUSB_DEV BIT(13) +#define SEC_CARVEOUT_CA2_R_SE2 BIT(14) +#define SEC_CARVEOUT_CA2_W_SE2 BIT(16) +#define SEC_CARVEOUT_CA2_R_TSEC BIT(20) +#define SEC_CARVEOUT_CA2_W_TSEC BIT(21) +#define SEC_CARVEOUT_CA2_R_ADSP_SC BIT(22) +#define SEC_CARVEOUT_CA2_W_ADSP_SC BIT(23) +#define SEC_CARVEOUT_CA2_R_GPU BIT(24) +#define SEC_CARVEOUT_CA2_W_GPU BIT(25) +#define SEC_CARVEOUT_CA2_R_DISPLAYT BIT(26) + +/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS3 */ +#define SEC_CARVEOUT_CA3_R_SDMMCA BIT(0) +#define SEC_CARVEOUT_CA3_R_SDMMCAA BIT(1) +#define SEC_CARVEOUT_CA3_R_SDMMC BIT(2) +#define SEC_CARVEOUT_CA3_R_SDMMCAB BIT(3) +#define SEC_CARVEOUT_CA3_W_SDMMCA BIT(4) +#define SEC_CARVEOUT_CA3_W_SDMMCAA BIT(5) +#define SEC_CARVEOUT_CA3_W_SDMMC BIT(6) +#define SEC_CARVEOUT_CA3_W_SDMMCAB BIT(7) +#define SEC_CARVEOUT_CA3_R_VIC BIT(12) +#define SEC_CARVEOUT_CA3_W_VIC BIT(13) +#define SEC_CARVEOUT_CA3_W_VIW BIT(18) +#define SEC_CARVEOUT_CA3_R_DISPLAYD BIT(19) +#define SEC_CARVEOUT_CA3_R_NVDEC BIT(24) +#define SEC_CARVEOUT_CA3_W_NVDEC BIT(25) +#define SEC_CARVEOUT_CA3_R_APE BIT(26) +#define SEC_CARVEOUT_CA3_W_APE BIT(27) +#define SEC_CARVEOUT_CA3_R_NVJPG BIT(30) +#define SEC_CARVEOUT_CA3_W_NVJPG BIT(31) + +/*! MC_SECURITY_CARVEOUTX_CLIENT_FORCE_INTERNAL_ACCESS4 */ +#define SEC_CARVEOUT_CA4_R_SE BIT(0) +#define SEC_CARVEOUT_CA4_W_SE BIT(1) +#define SEC_CARVEOUT_CA4_R_AXIAP BIT(2) +#define SEC_CARVEOUT_CA4_W_AXIAP BIT(3) +#define SEC_CARVEOUT_CA4_R_ETR BIT(4) +#define SEC_CARVEOUT_CA4_W_ETR BIT(5) +#define SEC_CARVEOUT_CA4_R_TSECB BIT(6) +#define SEC_CARVEOUT_CA4_W_TSECB BIT(7) +#define SEC_CARVEOUT_CA4_R_GPU2 BIT(8) +#define SEC_CARVEOUT_CA4_W_GPU2 BIT(9) + +// MC_VIDEO_PROTECT_REG_CTRL +#define VPR_LOCK_MODE_SHIFT 0 +#define VPR_CTRL_UNLOCKED (0 << VPR_LOCK_MODE_SHIFT) +#define VPR_CTRL_LOCKED (1 << VPR_LOCK_MODE_SHIFT) +#define VPR_PROTECT_MODE_SHIFT 1 +#define SEC_CTRL_SECURE (0 << VPR_PROTECT_MODE_SHIFT) +#define VPR_CTRL_TZ_SECURE (1 << VPR_PROTECT_MODE_SHIFT) + // MC_SECURITY_CARVEOUTX_CFG0 // Mode of LOCK_MODE. #define PROTECT_MODE_SHIFT 0 -#define SEC_CARVEOUT_CFG_SECURE (0 << PROTECT_MODE_SHIFT0) -#define SEC_CARVEOUT_CFG_TZ_SECURE (1 << PROTECT_MODE_SHIFT0) +#define SEC_CARVEOUT_CFG_ALL_SECURE (0 << PROTECT_MODE_SHIFT) +#define SEC_CARVEOUT_CFG_TZ_SECURE (1 << PROTECT_MODE_SHIFT) // Enables PROTECT_MODE. #define LOCK_MODE_SHIFT 1 #define SEC_CARVEOUT_CFG_UNLOCKED (0 << LOCK_MODE_SHIFT) @@ -479,30 +596,31 @@ #define SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY (1 << ADDRESS_TYPE_SHIFT) #define READ_ACCESS_LEVEL_SHIFT 3 -#define SEC_CARVEOUT_CFG_RD_ALL (1 << READ_ACCESS_LEVEL_SHIFT) -#define SEC_CARVEOUT_CFG_RD_UNK (2 << READ_ACCESS_LEVEL_SHIFT) +#define SEC_CARVEOUT_CFG_RD_NS (1 << READ_ACCESS_LEVEL_SHIFT) +#define SEC_CARVEOUT_CFG_RD_SEC (2 << READ_ACCESS_LEVEL_SHIFT) #define SEC_CARVEOUT_CFG_RD_FALCON_LS (4 << READ_ACCESS_LEVEL_SHIFT) #define SEC_CARVEOUT_CFG_RD_FALCON_HS (8 << READ_ACCESS_LEVEL_SHIFT) #define WRITE_ACCESS_LEVEL_SHIFT 7 -#define SEC_CARVEOUT_CFG_WR_ALL (1 << WRITE_ACCESS_LEVEL_SHIFT) -#define SEC_CARVEOUT_CFG_WR_UNK (2 << WRITE_ACCESS_LEVEL_SHIFT) +#define SEC_CARVEOUT_CFG_WR_NS (1 << WRITE_ACCESS_LEVEL_SHIFT) +#define SEC_CARVEOUT_CFG_WR_SEC (2 << WRITE_ACCESS_LEVEL_SHIFT) #define SEC_CARVEOUT_CFG_WR_FALCON_LS (4 << WRITE_ACCESS_LEVEL_SHIFT) #define SEC_CARVEOUT_CFG_WR_FALCON_HS (8 << WRITE_ACCESS_LEVEL_SHIFT) #define SEC_CARVEOUT_CFG_APERTURE_ID_MASK (3 << 11) +#define SEC_CARVEOUT_CFG_APERTURE_ID(id) ((id) << 11) #define DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT 14 -#define SEC_CARVEOUT_CFG_DIS_RD_CHECK_L0 (1 << DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT) -#define SEC_CARVEOUT_CFG_DIS_RD_CHECK_L1 (2 << DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT) -#define SEC_CARVEOUT_CFG_DIS_RD_CHECK_L2 (4 << DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT) -#define SEC_CARVEOUT_CFG_DIS_RD_CHECK_L3 (8 << DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT) +#define SEC_CARVEOUT_CFG_DIS_RD_CHECK_NS (1 << DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT) +#define SEC_CARVEOUT_CFG_DIS_RD_CHECK_SEC (2 << DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT) +#define SEC_CARVEOUT_CFG_DIS_RD_CHECK_FLCN_LS (4 << DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT) +#define SEC_CARVEOUT_CFG_DIS_RD_CHECK_FLCN_HS (8 << DISABLE_READ_CHECK_ACCESS_LEVEL_SHIFT) #define DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT 18 -#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_L0 (1 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT) -#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_L1 (2 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT) -#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_L2 (4 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT) -#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_L3 (8 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT) +#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_NS (1 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT) +#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_SEC (2 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT) +#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_FLCN_LS (4 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT) +#define SEC_CARVEOUT_CFG_DIS_WR_CHECK_FLCN_HS (8 << DISABLE_WRITE_CHECK_ACCESS_LEVEL_SHIFT) #define SEC_CARVEOUT_CFG_SEND_CFG_TO_GPU BIT(22) diff --git a/bdk/mem/minerva.c b/bdk/mem/minerva.c index 2560dfe..3fd05e4 100644 --- a/bdk/mem/minerva.c +++ b/bdk/mem/minerva.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 CTCaer + * Copyright (c) 2019-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,21 +19,26 @@ #include "minerva.h" -#include #include +#include #include #include #include #include #include +#define TABLE_FREQ_KHZ_OFFSET 0x40 +#define TABLE_LA_REGS_T210_OFFSET 0x1284 +#define TABLE_LA_REGS_T210B01_OFFSET 0xFA4 +#define LA_SDMMC1_INDEX 6 + extern volatile nyx_storage_t *nyx_str; void (*minerva_cfg)(mtc_config_t *mtc_cfg, void *); u32 minerva_init() { - u32 curr_ram_idx = 0; + u32 tbl_idx = 0; minerva_cfg = NULL; mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg; @@ -42,7 +47,7 @@ u32 minerva_init() if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01) return 0; -#ifdef NYX +#ifdef BDK_MINERVA_CFG_FROM_RAM // Set table to nyx storage. mtc_cfg->mtc_table = (emc_table_t *)nyx_str->mtc_table; @@ -97,13 +102,14 @@ u32 minerva_init() return 1; // Get current frequency - for (curr_ram_idx = 0; curr_ram_idx < 10; curr_ram_idx++) + u32 current_emc_clk_src = CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC); + for (tbl_idx = 0; tbl_idx < mtc_cfg->table_entries; tbl_idx++) { - if (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) == mtc_cfg->mtc_table[curr_ram_idx].clk_src_emc) + if (current_emc_clk_src == mtc_cfg->mtc_table[tbl_idx].clk_src_emc) break; } - mtc_cfg->rate_from = mtc_cfg->mtc_table[curr_ram_idx].rate_khz; + mtc_cfg->rate_from = mtc_cfg->mtc_table[tbl_idx].rate_khz; mtc_cfg->rate_to = FREQ_204; mtc_cfg->train_mode = OP_TRAIN; minerva_cfg(mtc_cfg, NULL); @@ -139,6 +145,27 @@ void minerva_change_freq(minerva_freq_t freq) } } +void minerva_sdmmc_la_program(void *table, bool t210b01) +{ + + u32 freq = *(u32 *)(table + TABLE_FREQ_KHZ_OFFSET); + u32 *la_scale_regs = (u32 *)(table + (t210b01 ? TABLE_LA_REGS_T210B01_OFFSET : TABLE_LA_REGS_T210_OFFSET)); + + // Adjust SDMMC1 latency allowance. + switch (freq) + { + case 204000: + la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 50; + break; + case 408000: + la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 25; + break; + default: + la_scale_regs[LA_SDMMC1_INDEX] = (la_scale_regs[LA_SDMMC1_INDEX] & 0xFF0000) | 20; + break; + } +} + void minerva_prep_boot_freq() { if (!minerva_cfg) @@ -156,6 +183,72 @@ void minerva_prep_boot_freq() minerva_change_freq(FREQ_800); } +void minerva_prep_boot_l4t(u32 oc_freq, u32 opt_custom) +{ + if (!minerva_cfg) + return; + + mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg; + + // Program SDMMC LA regs. + for (u32 i = 0; i < mtc_cfg->table_entries; i++) + minerva_sdmmc_la_program(&mtc_cfg->mtc_table[i], false); + + // Add OC frequency. + if (oc_freq && mtc_cfg->mtc_table[mtc_cfg->table_entries - 1].rate_khz == FREQ_1600) + { + memcpy(&mtc_cfg->mtc_table[mtc_cfg->table_entries], + &mtc_cfg->mtc_table[mtc_cfg->table_entries - 1], + sizeof(emc_table_t)); + + mtc_cfg->mtc_table[mtc_cfg->table_entries].opt_custom = opt_custom; + mtc_cfg->mtc_table[mtc_cfg->table_entries].rate_khz = oc_freq; + mtc_cfg->table_entries++; + } + + // Trim table. + int entries = 0; + for (u32 i = 0; i < mtc_cfg->table_entries; i++) + { + // Copy frequencies from 204/408/800 MHz and 1333+ MHz. + int rate = mtc_cfg->mtc_table[i].rate_khz; + if (rate == FREQ_204 || + rate == FREQ_408 || + rate == FREQ_800 || + rate >= FREQ_1333) + { + memcpy(&mtc_cfg->mtc_table[entries], &mtc_cfg->mtc_table[i], sizeof(emc_table_t)); + entries++; + } + } + mtc_cfg->table_entries = entries; + + // Set init frequency. + minerva_change_freq(FREQ_204); + + // Train the rest of the frequencies. + mtc_cfg->train_mode = OP_TRAIN; + for (u32 i = 0; i < mtc_cfg->table_entries; i++) + { + // Skip already trained frequencies and OC freq (Arachne handles it). + if (mtc_cfg->mtc_table[i].trained || mtc_cfg->rate_to == oc_freq) + continue; + + // Train frequency. + mtc_cfg->rate_to = mtc_cfg->mtc_table[i].rate_khz; + minerva_cfg(mtc_cfg, NULL); + } + + // Do FSP WAR and scale to 800 MHz as boot freq. + bool fsp_opwr_disabled = !(EMC(EMC_MRW3) & 0xC0); + if (fsp_opwr_disabled) + minerva_change_freq(FREQ_1333); + minerva_change_freq(FREQ_800); + + // Do not let other mtc ops. + mtc_cfg->init_done = 0; +} + void minerva_periodic_training() { if (!minerva_cfg) @@ -167,4 +260,22 @@ void minerva_periodic_training() mtc_cfg->train_mode = OP_PERIODIC_TRAIN; minerva_cfg(mtc_cfg, NULL); } -} \ No newline at end of file +} + +emc_table_t *minerva_get_mtc_table() +{ + if (!minerva_cfg) + return NULL; + + mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg; + return mtc_cfg->mtc_table; +} + +int minerva_get_mtc_table_entries() +{ + if (!minerva_cfg) + return 0; + + mtc_config_t *mtc_cfg = (mtc_config_t *)&nyx_str->mtc_cfg; + return mtc_cfg->table_entries; +} diff --git a/bdk/mem/minerva.h b/bdk/mem/minerva.h index 51cb215..e78bb41 100644 --- a/bdk/mem/minerva.h +++ b/bdk/mem/minerva.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 CTCaer + * Copyright (c) 2019-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -27,8 +27,8 @@ typedef struct { - s32 rate_to; - s32 rate_from; + u32 rate_to; + u32 rate_from; emc_table_t *mtc_table; u32 table_entries; emc_table_t *current_emc_table; @@ -38,7 +38,7 @@ typedef struct bool emc_2X_clk_src_is_pllmb; bool fsp_for_src_freq; bool train_ram_patterns; - bool init_done; + u32 init_done; } mtc_config_t; enum train_mode_t @@ -53,14 +53,20 @@ enum train_mode_t typedef enum { FREQ_204 = 204000, + FREQ_408 = 408000, FREQ_800 = 800000, + FREQ_1333 = 1331200, FREQ_1600 = 1600000 } minerva_freq_t; extern void (*minerva_cfg)(mtc_config_t *mtc_cfg, void *); u32 minerva_init(); void minerva_change_freq(minerva_freq_t freq); +void minerva_sdmmc_la_program(void *table, bool t210b01); void minerva_prep_boot_freq(); +void minerva_prep_boot_l4t(u32 oc_freq, u32 opt_custom); void minerva_periodic_training(); +emc_table_t *minerva_get_mtc_table(); +int minerva_get_mtc_table_entries(); #endif diff --git a/bdk/mem/mtc_table.h b/bdk/mem/mtc_table.h index e24fa81..7802280 100644 --- a/bdk/mem/mtc_table.h +++ b/bdk/mem/mtc_table.h @@ -481,7 +481,8 @@ typedef struct u32 rate_khz; u32 min_volt; u32 gpu_min_volt; - char clock_src[32]; + char clock_src[28]; + u32 opt_custom; u32 clk_src_emc; u32 needs_training; u32 training_pattern; diff --git a/bdk/mem/sdram.c b/bdk/mem/sdram.c index 0f2ce3e..4aa98fa 100644 --- a/bdk/mem/sdram.c +++ b/bdk/mem/sdram.c @@ -1,7 +1,7 @@ /* * Copyright (c) 2018 naehrwert * Copyright (c) 2018 balika011 - * Copyright (c) 2019-2021 CTCaer + * Copyright (c) 2019-2023 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -31,48 +31,55 @@ #include #include #include +#include #include -#include -#define CONFIG_SDRAM_KEEP_ALIVE +#define DRAM_ID(x) BIT(x) +#define DRAM_CC(x) BIT(x) typedef struct _sdram_vendor_patch_t { u32 val; - u32 offset:16; u32 dramcf:16; + u32 offset:16; } sdram_vendor_patch_t; static const u8 dram_encoding_t210b01[] = { - LPDDR4X_UNUSED, - LPDDR4X_UNUSED, - LPDDR4X_UNUSED, - LPDDR4X_4GB_HYNIX_1Y_A, - LPDDR4X_UNUSED, - LPDDR4X_4GB_HYNIX_1Y_A, - LPDDR4X_4GB_HYNIX_1Y_A, - LPDDR4X_4GB_SAMSUNG_X1X2, - LPDDR4X_NO_PATCH, - LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ, - LPDDR4X_NO_PATCH, - LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046, - LPDDR4X_NO_PATCH, - LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ, - LPDDR4X_NO_PATCH, - LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046, - LPDDR4X_4GB_SAMSUNG_Y, - LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL, - LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL, - LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL, - LPDDR4X_4GB_SAMSUNG_1Y_Y, - LPDDR4X_8GB_SAMSUNG_1Y_Y, - LPDDR4X_UNUSED, // Removed. - LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL, - LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL, - LPDDR4X_4GB_MICRON_1Y_A, - LPDDR4X_4GB_MICRON_1Y_A, - LPDDR4X_4GB_MICRON_1Y_A, - LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL, +/* 00 */ LPDDR4X_UNUSED, +/* 01 */ LPDDR4X_UNUSED, +/* 02 */ LPDDR4X_UNUSED, +/* 03 */ LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE, +/* 04 */ LPDDR4X_UNUSED, +/* 05 */ LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE, +/* 06 */ LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE, +/* 07 */ LPDDR4X_UNUSED, +/* 08 */ LPDDR4X_NO_PATCH, +/* 09 */ LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ, +/* 10 */ LPDDR4X_NO_PATCH, +/* 11 */ LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE, +/* 12 */ LPDDR4X_NO_PATCH, +/* 13 */ LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ, +/* 14 */ LPDDR4X_NO_PATCH, +/* 15 */ LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE, +/* 16 */ LPDDR4X_UNUSED, +/* 17 */ LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL, +/* 18 */ LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL, +/* 19 */ LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL, +/* 20 */ LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL, +/* 21 */ LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL, +/* 22 */ LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL, +/* 23 */ LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL, +/* 24 */ LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL, +/* 25 */ LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF, +/* 26 */ LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF, +/* 27 */ LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF, +/* 28 */ LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL, +/* 29 */ LPDDR4X_4GB_HYNIX_H54G46CYRBX267, +/* 30 */ LPDDR4X_4GB_HYNIX_H54G46CYRBX267, +/* 31 */ LPDDR4X_4GB_HYNIX_H54G46CYRBX267, +/* 32 */ LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB, +/* 33 */ LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB, +/* 34 */ LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB, }; #include "sdram_config.inl" @@ -118,6 +125,18 @@ static void _sdram_req_mrr_data(u32 data, bool dual_channel) emc_mr_data_t sdram_read_mrx(emc_mr_t mrx) { emc_mr_data_t data; + u32 mrr; + bool dual_rank = EMC(EMC_ADR_CFG) & 1; + bool dual_channel = (EMC(EMC_FBIO_CFG7) >> 2) & 1; // Each EMC channel is a RAM chip module. + + // Clear left overs. + for (u32 i = 0; i < 16; i++) + { + (void)EMC(EMC_MRR); + usleep(1); + } + + memset(&data, 0xFF, sizeof(emc_mr_data_t)); /* * When a dram chip has only one rank, then the info from the 2 ranks differs. @@ -125,28 +144,106 @@ emc_mr_data_t sdram_read_mrx(emc_mr_t mrx) */ // Get Device 0 (Rank 0) info from both dram chips (channels). - _sdram_req_mrr_data(BIT(31) | (mrx << 16), EMC_CHAN0); - data.rank0_ch0 = EMC(EMC_MRR) & 0xFF; - data.rank0_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8); + _sdram_req_mrr_data((2u << 30) | (mrx << 16), dual_channel); - // Get Device 1 (Rank 1) info from both dram chips (channels). - _sdram_req_mrr_data(BIT(30) | (mrx << 16), EMC_CHAN1); - data.rank1_ch0 = EMC(EMC_MRR) & 0xFF; - data.rank1_ch1 = (EMC(EMC_MRR) & 0xFF00 >> 8); + // Ram module 0 info. + mrr = EMC_CH0(EMC_MRR); + data.chip0.rank0_ch0 = mrr & 0xFF; + data.chip0.rank0_ch1 = (mrr & 0xFF00 >> 8); + + // Ram module 1 info. + if (dual_channel) + { + mrr = EMC_CH1(EMC_MRR); + data.chip1.rank0_ch0 = mrr & 0xFF; + data.chip1.rank0_ch1 = (mrr & 0xFF00 >> 8); + } + + // If Rank 1 exists, get info. + if (dual_rank) + { + // Get Device 1 (Rank 1) info from both dram chips (channels). + _sdram_req_mrr_data((1u << 30) | (mrx << 16), dual_channel); + + // Ram module 0 info. + mrr = EMC_CH0(EMC_MRR); + data.chip0.rank1_ch0 = mrr & 0xFF; + data.chip0.rank1_ch1 = (mrr & 0xFF00 >> 8); + + // Ram module 1 info. + if (dual_channel) + { + mrr = EMC_CH1(EMC_MRR); + data.chip1.rank1_ch0 = mrr & 0xFF; + data.chip1.rank1_ch1 = (mrr & 0xFF00 >> 8); + } + } return data; } +void sdram_src_pllc(bool enable) +{ + static bool enabled = false; + + if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210 || enable == enabled) + return; + + enabled = enable; + + // Clear CC interrupt. + EMC(EMC_INTSTATUS) = BIT(4); + (void)EMC(EMC_INTSTATUS); + + u32 clk_src_emc = _dram_cfg_08_10_12_14_samsung_hynix_4gb.emc_clock_source; + + if (enable) + { + // Check if clock source is not the expected one. + if (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) != clk_src_emc) + return; + + // Set source as PLLC_OUT0. + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = 0x20188004; + } + else + { + // Restore MC/EMC clock. + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = clk_src_emc; + } + + // Wait for CC interrupt. + while (!(EMC(EMC_INTSTATUS) & BIT(4))) + usleep(1); +} + static void _sdram_config_t210(const sdram_params_t210_t *params) { + // VDDP Select. + PMC(APBDEV_PMC_VDDP_SEL) = params->pmc_vddp_sel; + usleep(params->pmc_vddp_sel_wait); + + // Set DDR pad voltage. + PMC(APBDEV_PMC_DDR_PWR) = PMC(APBDEV_PMC_DDR_PWR); // Normally params->pmc_ddr_pwr. + + // Turn on MEM IO Power. + PMC(APBDEV_PMC_NO_IOPOWER) &= PMC_NO_IOPOWER_SDMMC1; // Only keep SDMMC1 state. (Was params->pmc_no_io_power). + PMC(APBDEV_PMC_REG_SHORT) = params->pmc_reg_short; + + PMC(APBDEV_PMC_DDR_CNTRL) = params->pmc_ddr_ctrl; + + // Patch 1 using BCT spare variables + if (params->emc_bct_spare0) + *(vu32 *)params->emc_bct_spare0 = params->emc_bct_spare1; + // Program DPD3/DPD4 regs (coldboot path). // Enable sel_dpd on unused pins. - u32 dpd_req = (params->emc_pmc_scratch1 & 0x3FFFFFFF) | 0x80000000; + u32 dpd_req = (params->emc_pmc_scratch1 & 0x3FFFFFFF) | PMC_IO_DPD_REQ_DPD_ON; PMC(APBDEV_PMC_IO_DPD3_REQ) = (dpd_req ^ 0xFFFF) & 0xC000FFFF; usleep(params->pmc_io_dpd3_req_wait); // Disable e_dpd_vttgen. - dpd_req = (params->emc_pmc_scratch2 & 0x3FFFFFFF) | 0x80000000; + dpd_req = (params->emc_pmc_scratch2 & 0x3FFFFFFF) | PMC_IO_DPD_REQ_DPD_ON; PMC(APBDEV_PMC_IO_DPD4_REQ) = (dpd_req & 0xFFFF0000) ^ 0x3FFF0000; usleep(params->pmc_io_dpd4_req_wait); @@ -157,45 +254,42 @@ static void _sdram_config_t210(const sdram_params_t210_t *params) PMC(APBDEV_PMC_WEAK_BIAS) = 0; usleep(1); - // Start clocks. + // Start PLLM. CLOCK(CLK_RST_CONTROLLER_PLLM_MISC1) = params->pllm_setup_control; CLOCK(CLK_RST_CONTROLLER_PLLM_MISC2) = 0; -#ifdef CONFIG_SDRAM_KEEP_ALIVE - CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = - (params->pllm_feedback_divider << 8) | params->pllm_input_divider | ((params->pllm_post_divider & 0xFFFF) << 20) | PLLCX_BASE_ENABLE; -#else u32 pllm_div = (params->pllm_feedback_divider << 8) | params->pllm_input_divider | ((params->pllm_post_divider & 0xFFFF) << 20); CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = pllm_div; CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) = pllm_div | PLLCX_BASE_ENABLE; -#endif u32 wait_end = get_tmr_us() + 300; - while (!(CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) & 0x8000000)) + while (!(CLOCK(CLK_RST_CONTROLLER_PLLM_BASE) & BIT(27))) { if (get_tmr_us() >= wait_end) - goto break_nosleep; + goto lock_timeout; } usleep(10); -break_nosleep: +lock_timeout: + // Set clock sources. CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = ((params->mc_emem_arb_misc0 >> 11) & 0x10000) | (params->emc_clock_source & 0xFFFEFFFF); if (params->emc_clock_source_dll) CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL) = params->emc_clock_source_dll; if (params->clear_clock2_mc1) - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_CLR) = 0x40000000; // Clear Reset to MC1. + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_CLR) = BIT(CLK_W_MC1); // Clear Reset to MC1. // Enable and clear reset for memory clocks. CLOCK(CLK_RST_CONTROLLER_CLK_ENB_H_SET) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM); CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = BIT(CLK_X_EMC_DLL); CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_CLR) = BIT(CLK_H_EMC) | BIT(CLK_H_MEM); - // Set pad macros. + // Set pad vtt levels. EMC(EMC_PMACRO_VTTGEN_CTRL_0) = params->emc_pmacro_vttgen_ctrl0; EMC(EMC_PMACRO_VTTGEN_CTRL_1) = params->emc_pmacro_vttgen_ctrl1; EMC(EMC_PMACRO_VTTGEN_CTRL_2) = params->emc_pmacro_vttgen_ctrl2; - EMC(EMC_TIMING_CONTROL) = 1; // Trigger timing update so above writes take place. + // Trigger timing update so above writes take place. + EMC(EMC_TIMING_CONTROL) = 1; usleep(10); // Ensure the regulators settle. // Select EMC write mux. @@ -207,7 +301,7 @@ break_nosleep: // Program CMD mapping. Required before brick mapping, else // we can't guarantee CK will be differential at all times. - EMC(EMC_FBIO_CFG7) = params->emc_fbio_cfg7; + EMC(EMC_FBIO_CFG7) = params->emc_fbio_cfg7; EMC(EMC_CMD_MAPPING_CMD0_0) = params->emc_cmd_mapping_cmd0_0; EMC(EMC_CMD_MAPPING_CMD0_1) = params->emc_cmd_mapping_cmd0_1; EMC(EMC_CMD_MAPPING_CMD0_2) = params->emc_cmd_mapping_cmd0_2; @@ -220,7 +314,7 @@ break_nosleep: EMC(EMC_CMD_MAPPING_CMD3_0) = params->emc_cmd_mapping_cmd3_0; EMC(EMC_CMD_MAPPING_CMD3_1) = params->emc_cmd_mapping_cmd3_1; EMC(EMC_CMD_MAPPING_CMD3_2) = params->emc_cmd_mapping_cmd3_2; - EMC(EMC_CMD_MAPPING_BYTE) = params->emc_cmd_mapping_byte; + EMC(EMC_CMD_MAPPING_BYTE) = params->emc_cmd_mapping_byte; // Program brick mapping. EMC(EMC_PMACRO_BRICK_MAPPING_0) = params->emc_pmacro_brick_mapping0; @@ -232,6 +326,7 @@ break_nosleep: // This is required to do any reads from the pad macros. EMC(EMC_CONFIG_SAMPLE_DELAY) = params->emc_config_sample_delay; + // Set data pipes mode. EMC(EMC_FBIO_CFG8) = params->emc_fbio_cfg8; // Set swizzle for Rank 0. @@ -249,12 +344,12 @@ break_nosleep: if (params->emc_bct_spare6) *(vu32 *)params->emc_bct_spare6 = params->emc_bct_spare7; - // Set pad controls. - EMC(EMC_XM2COMPPADCTRL) = params->emc_xm2_comp_pad_ctrl; + // Program calibration impedance. + EMC(EMC_XM2COMPPADCTRL) = params->emc_xm2_comp_pad_ctrl; EMC(EMC_XM2COMPPADCTRL2) = params->emc_xm2_comp_pad_ctrl2; EMC(EMC_XM2COMPPADCTRL3) = params->emc_xm2_comp_pad_ctrl3; - // Program Autocal controls with shadowed register fields. + // Program Autocal controls. EMC(EMC_AUTO_CAL_CONFIG2) = params->emc_auto_cal_config2; EMC(EMC_AUTO_CAL_CONFIG3) = params->emc_auto_cal_config3; EMC(EMC_AUTO_CAL_CONFIG4) = params->emc_auto_cal_config4; @@ -263,71 +358,79 @@ break_nosleep: EMC(EMC_AUTO_CAL_CONFIG7) = params->emc_auto_cal_config7; EMC(EMC_AUTO_CAL_CONFIG8) = params->emc_auto_cal_config8; - EMC(EMC_PMACRO_RX_TERM) = params->emc_pmacro_rx_term; - EMC(EMC_PMACRO_DQ_TX_DRV) = params->emc_pmacro_dq_tx_drive; - EMC(EMC_PMACRO_CA_TX_DRV) = params->emc_pmacro_ca_tx_drive; - EMC(EMC_PMACRO_CMD_TX_DRV) = params->emc_pmacro_cmd_tx_drive; + // Program termination and drive strength + EMC(EMC_PMACRO_RX_TERM) = params->emc_pmacro_rx_term; + EMC(EMC_PMACRO_DQ_TX_DRV) = params->emc_pmacro_dq_tx_drive; + EMC(EMC_PMACRO_CA_TX_DRV) = params->emc_pmacro_ca_tx_drive; + EMC(EMC_PMACRO_CMD_TX_DRV) = params->emc_pmacro_cmd_tx_drive; EMC(EMC_PMACRO_AUTOCAL_CFG_COMMON) = params->emc_pmacro_auto_cal_common; - EMC(EMC_AUTO_CAL_CHANNEL) = params->emc_auto_cal_channel; - EMC(EMC_PMACRO_ZCTRL) = params->emc_pmacro_zcrtl; + EMC(EMC_AUTO_CAL_CHANNEL) = params->emc_auto_cal_channel; + EMC(EMC_PMACRO_ZCTRL) = params->emc_pmacro_zcrtl; - EMC(EMC_DLL_CFG_0) = params->emc_dll_cfg0; - EMC(EMC_DLL_CFG_1) = params->emc_dll_cfg1; + // Program dll config. + EMC(EMC_DLL_CFG_0) = params->emc_dll_cfg0; + EMC(EMC_DLL_CFG_1) = params->emc_dll_cfg1; EMC(EMC_CFG_DIG_DLL_1) = params->emc_cfg_dig_dll_1; + // Program barrelshift. EMC(EMC_DATA_BRLSHFT_0) = params->emc_data_brlshft0; EMC(EMC_DATA_BRLSHFT_1) = params->emc_data_brlshft1; - EMC(EMC_DQS_BRLSHFT_0) = params->emc_dqs_brlshft0; - EMC(EMC_DQS_BRLSHFT_1) = params->emc_dqs_brlshft1; - EMC(EMC_CMD_BRLSHFT_0) = params->emc_cmd_brlshft0; - EMC(EMC_CMD_BRLSHFT_1) = params->emc_cmd_brlshft1; - EMC(EMC_CMD_BRLSHFT_2) = params->emc_cmd_brlshft2; - EMC(EMC_CMD_BRLSHFT_3) = params->emc_cmd_brlshft3; + EMC(EMC_DQS_BRLSHFT_0) = params->emc_dqs_brlshft0; + EMC(EMC_DQS_BRLSHFT_1) = params->emc_dqs_brlshft1; + EMC(EMC_CMD_BRLSHFT_0) = params->emc_cmd_brlshft0; + EMC(EMC_CMD_BRLSHFT_1) = params->emc_cmd_brlshft1; + EMC(EMC_CMD_BRLSHFT_2) = params->emc_cmd_brlshft2; + EMC(EMC_CMD_BRLSHFT_3) = params->emc_cmd_brlshft3; EMC(EMC_QUSE_BRLSHFT_0) = params->emc_quse_brlshft0; EMC(EMC_QUSE_BRLSHFT_1) = params->emc_quse_brlshft1; EMC(EMC_QUSE_BRLSHFT_2) = params->emc_quse_brlshft2; EMC(EMC_QUSE_BRLSHFT_3) = params->emc_quse_brlshft3; + // Program pad macros controls and termination. EMC(EMC_PMACRO_BRICK_CTRL_RFU1) = (params->emc_pmacro_brick_ctrl_rfu1 & 0x1BF01BF) | 0x1E401E40; - EMC(EMC_PMACRO_PAD_CFG_CTRL) = params->emc_pmacro_pad_cfg_ctrl; + EMC(EMC_PMACRO_PAD_CFG_CTRL) = params->emc_pmacro_pad_cfg_ctrl; - EMC(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->emc_pmacro_cmd_brick_ctrl_fdpd; - EMC(EMC_PMACRO_BRICK_CTRL_RFU2) = params->emc_pmacro_brick_ctrl_rfu2 & 0xFF7FFF7F; + EMC(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->emc_pmacro_cmd_brick_ctrl_fdpd; + EMC(EMC_PMACRO_BRICK_CTRL_RFU2) = params->emc_pmacro_brick_ctrl_rfu2 & 0xFF7FFF7F; EMC(EMC_PMACRO_DATA_BRICK_CTRL_FDPD) = params->emc_pmacro_data_brick_ctrl_fdpd; - EMC(EMC_PMACRO_BG_BIAS_CTRL_0) = params->emc_pmacro_bg_bias_ctrl0; - EMC(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->emc_pmacro_data_pad_rx_ctrl; - EMC(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->emc_pmacro_cmd_pad_rx_ctrl; - EMC(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->emc_pmacro_data_pad_tx_ctrl; - EMC(EMC_PMACRO_DATA_RX_TERM_MODE) = params->emc_pmacro_data_rx_term_mode; - EMC(EMC_PMACRO_CMD_RX_TERM_MODE) = params->emc_pmacro_cmd_rx_term_mode; - EMC(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->emc_pmacro_cmd_pad_tx_ctrl; + EMC(EMC_PMACRO_BG_BIAS_CTRL_0) = params->emc_pmacro_bg_bias_ctrl0; + EMC(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->emc_pmacro_data_pad_rx_ctrl; + EMC(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->emc_pmacro_cmd_pad_rx_ctrl; + EMC(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->emc_pmacro_data_pad_tx_ctrl; + EMC(EMC_PMACRO_DATA_RX_TERM_MODE) = params->emc_pmacro_data_rx_term_mode; + EMC(EMC_PMACRO_CMD_RX_TERM_MODE) = params->emc_pmacro_cmd_rx_term_mode; + EMC(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->emc_pmacro_cmd_pad_tx_ctrl; - EMC(EMC_CFG_3) = params->emc_cfg3; - EMC(EMC_PMACRO_TX_PWRD_0) = params->emc_pmacro_tx_pwrd0; - EMC(EMC_PMACRO_TX_PWRD_1) = params->emc_pmacro_tx_pwrd1; - EMC(EMC_PMACRO_TX_PWRD_2) = params->emc_pmacro_tx_pwrd2; - EMC(EMC_PMACRO_TX_PWRD_3) = params->emc_pmacro_tx_pwrd3; - EMC(EMC_PMACRO_TX_PWRD_4) = params->emc_pmacro_tx_pwrd4; - EMC(EMC_PMACRO_TX_PWRD_5) = params->emc_pmacro_tx_pwrd5; + // Program pad macro pins/bytes. + EMC(EMC_CFG_3) = params->emc_cfg3; + EMC(EMC_PMACRO_TX_PWRD_0) = params->emc_pmacro_tx_pwrd0; + EMC(EMC_PMACRO_TX_PWRD_1) = params->emc_pmacro_tx_pwrd1; + EMC(EMC_PMACRO_TX_PWRD_2) = params->emc_pmacro_tx_pwrd2; + EMC(EMC_PMACRO_TX_PWRD_3) = params->emc_pmacro_tx_pwrd3; + EMC(EMC_PMACRO_TX_PWRD_4) = params->emc_pmacro_tx_pwrd4; + EMC(EMC_PMACRO_TX_PWRD_5) = params->emc_pmacro_tx_pwrd5; EMC(EMC_PMACRO_TX_SEL_CLK_SRC_0) = params->emc_pmacro_tx_sel_clk_src0; EMC(EMC_PMACRO_TX_SEL_CLK_SRC_1) = params->emc_pmacro_tx_sel_clk_src1; EMC(EMC_PMACRO_TX_SEL_CLK_SRC_2) = params->emc_pmacro_tx_sel_clk_src2; EMC(EMC_PMACRO_TX_SEL_CLK_SRC_3) = params->emc_pmacro_tx_sel_clk_src3; EMC(EMC_PMACRO_TX_SEL_CLK_SRC_4) = params->emc_pmacro_tx_sel_clk_src4; EMC(EMC_PMACRO_TX_SEL_CLK_SRC_5) = params->emc_pmacro_tx_sel_clk_src5; - EMC(EMC_PMACRO_DDLL_BYPASS) = params->emc_pmacro_ddll_bypass; - EMC(EMC_PMACRO_DDLL_PWRD_0) = params->emc_pmacro_ddll_pwrd0; - EMC(EMC_PMACRO_DDLL_PWRD_1) = params->emc_pmacro_ddll_pwrd1; - EMC(EMC_PMACRO_DDLL_PWRD_2) = params->emc_pmacro_ddll_pwrd2; - EMC(EMC_PMACRO_CMD_CTRL_0) = params->emc_pmacro_cmd_ctrl0; - EMC(EMC_PMACRO_CMD_CTRL_1) = params->emc_pmacro_cmd_ctrl1; - EMC(EMC_PMACRO_CMD_CTRL_2) = params->emc_pmacro_cmd_ctrl2; - EMC(EMC_PMACRO_IB_VREF_DQ_0) = params->emc_pmacro_ib_vref_dq_0; - EMC(EMC_PMACRO_IB_VREF_DQ_1) = params->emc_pmacro_ib_vref_dq_1; - EMC(EMC_PMACRO_IB_VREF_DQS_0) = params->emc_pmacro_ib_vref_dqs_0; - EMC(EMC_PMACRO_IB_VREF_DQS_1) = params->emc_pmacro_ib_vref_dqs_1; - EMC(EMC_PMACRO_IB_RXRT) = params->emc_pmacro_ib_rxrt; + EMC(EMC_PMACRO_DDLL_BYPASS) = params->emc_pmacro_ddll_bypass; + EMC(EMC_PMACRO_DDLL_PWRD_0) = params->emc_pmacro_ddll_pwrd0; + EMC(EMC_PMACRO_DDLL_PWRD_1) = params->emc_pmacro_ddll_pwrd1; + EMC(EMC_PMACRO_DDLL_PWRD_2) = params->emc_pmacro_ddll_pwrd2; + EMC(EMC_PMACRO_CMD_CTRL_0) = params->emc_pmacro_cmd_ctrl0; + EMC(EMC_PMACRO_CMD_CTRL_1) = params->emc_pmacro_cmd_ctrl1; + EMC(EMC_PMACRO_CMD_CTRL_2) = params->emc_pmacro_cmd_ctrl2; + // Program inbound vref setting. + EMC(EMC_PMACRO_IB_VREF_DQ_0) = params->emc_pmacro_ib_vref_dq_0; + EMC(EMC_PMACRO_IB_VREF_DQ_1) = params->emc_pmacro_ib_vref_dq_1; + EMC(EMC_PMACRO_IB_VREF_DQS_0) = params->emc_pmacro_ib_vref_dqs_0; + EMC(EMC_PMACRO_IB_VREF_DQS_1) = params->emc_pmacro_ib_vref_dqs_1; + EMC(EMC_PMACRO_IB_RXRT) = params->emc_pmacro_ib_rxrt; + + // Program quse trimmers. EMC(EMC_PMACRO_QUSE_DDLL_RANK0_0) = params->emc_pmacro_quse_ddll_rank0_0; EMC(EMC_PMACRO_QUSE_DDLL_RANK0_1) = params->emc_pmacro_quse_ddll_rank0_1; EMC(EMC_PMACRO_QUSE_DDLL_RANK0_2) = params->emc_pmacro_quse_ddll_rank0_2; @@ -340,8 +443,9 @@ break_nosleep: EMC(EMC_PMACRO_QUSE_DDLL_RANK1_3) = params->emc_pmacro_quse_ddll_rank1_3; EMC(EMC_PMACRO_QUSE_DDLL_RANK1_4) = params->emc_pmacro_quse_ddll_rank1_4; EMC(EMC_PMACRO_QUSE_DDLL_RANK1_5) = params->emc_pmacro_quse_ddll_rank1_5; - EMC(EMC_PMACRO_BRICK_CTRL_RFU1) = params->emc_pmacro_brick_ctrl_rfu1; + EMC(EMC_PMACRO_BRICK_CTRL_RFU1) = params->emc_pmacro_brick_ctrl_rfu1; + // Program outbound trimmers. EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0) = params->emc_pmacro_ob_ddll_long_dq_rank0_0; EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1) = params->emc_pmacro_ob_ddll_long_dq_rank0_1; EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2) = params->emc_pmacro_ob_ddll_long_dq_rank0_2; @@ -376,11 +480,12 @@ break_nosleep: EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2) = params->emc_pmacro_ib_ddll_long_dqs_rank1_2; EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3) = params->emc_pmacro_ib_ddll_long_dqs_rank1_3; - EMC(EMC_PMACRO_DDLL_LONG_CMD_0) = params->emc_pmacro_ddll_long_cmd_0; - EMC(EMC_PMACRO_DDLL_LONG_CMD_1) = params->emc_pmacro_ddll_long_cmd_1; - EMC(EMC_PMACRO_DDLL_LONG_CMD_2) = params->emc_pmacro_ddll_long_cmd_2; - EMC(EMC_PMACRO_DDLL_LONG_CMD_3) = params->emc_pmacro_ddll_long_cmd_3; - EMC(EMC_PMACRO_DDLL_LONG_CMD_4) = params->emc_pmacro_ddll_long_cmd_4; + // Program clock trimmers. + EMC(EMC_PMACRO_DDLL_LONG_CMD_0) = params->emc_pmacro_ddll_long_cmd_0; + EMC(EMC_PMACRO_DDLL_LONG_CMD_1) = params->emc_pmacro_ddll_long_cmd_1; + EMC(EMC_PMACRO_DDLL_LONG_CMD_2) = params->emc_pmacro_ddll_long_cmd_2; + EMC(EMC_PMACRO_DDLL_LONG_CMD_3) = params->emc_pmacro_ddll_long_cmd_3; + EMC(EMC_PMACRO_DDLL_LONG_CMD_4) = params->emc_pmacro_ddll_long_cmd_4; EMC(EMC_PMACRO_DDLL_SHORT_CMD_0) = params->emc_pmacro_ddll_short_cmd_0; EMC(EMC_PMACRO_DDLL_SHORT_CMD_1) = params->emc_pmacro_ddll_short_cmd_1; EMC(EMC_PMACRO_DDLL_SHORT_CMD_2) = params->emc_pmacro_ddll_short_cmd_2; @@ -392,21 +497,22 @@ break_nosleep: if (params->emc_bct_spare4) *(vu32 *)params->emc_bct_spare4 = params->emc_bct_spare5; - EMC(EMC_TIMING_CONTROL) = 1; // Trigger timing update so above writes take place. + // Trigger timing update so above writes take place. + EMC(EMC_TIMING_CONTROL) = 1; // Initialize MC VPR settings. - MC(MC_VIDEO_PROTECT_BOM) = params->mc_video_protect_bom; - MC(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->mc_video_protect_bom_adr_hi; - MC(MC_VIDEO_PROTECT_SIZE_MB) = params->mc_video_protect_size_mb; - MC(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->mc_video_protect_vpr_override; - MC(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->mc_video_protect_vpr_override1; + MC(MC_VIDEO_PROTECT_BOM) = params->mc_video_protect_bom; + MC(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->mc_video_protect_bom_adr_hi; + MC(MC_VIDEO_PROTECT_SIZE_MB) = params->mc_video_protect_size_mb; + MC(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->mc_video_protect_vpr_override; + MC(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->mc_video_protect_vpr_override1; MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = params->mc_video_protect_gpu_override0; MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = params->mc_video_protect_gpu_override1; // Program SDRAM geometry parameters. - MC(MC_EMEM_ADR_CFG) = params->mc_emem_adr_cfg; - MC(MC_EMEM_ADR_CFG_DEV0) = params->mc_emem_adr_cfg_dev0; - MC(MC_EMEM_ADR_CFG_DEV1) = params->mc_emem_adr_cfg_dev1; + MC(MC_EMEM_ADR_CFG) = params->mc_emem_adr_cfg; + MC(MC_EMEM_ADR_CFG_DEV0) = params->mc_emem_adr_cfg_dev0; + MC(MC_EMEM_ADR_CFG_DEV1) = params->mc_emem_adr_cfg_dev1; MC(MC_EMEM_ADR_CFG_CHANNEL_MASK) = params->mc_emem_adr_cfg_channel_mask; // Program bank swizzling. @@ -418,46 +524,47 @@ break_nosleep: MC(MC_EMEM_CFG) = params->mc_emem_cfg; // Program SEC carveout (base and size). - MC(MC_SEC_CARVEOUT_BOM) = params->mc_sec_carveout_bom; - MC(MC_SEC_CARVEOUT_ADR_HI) = params->mc_sec_carveout_adr_hi; + MC(MC_SEC_CARVEOUT_BOM) = params->mc_sec_carveout_bom; + MC(MC_SEC_CARVEOUT_ADR_HI) = params->mc_sec_carveout_adr_hi; MC(MC_SEC_CARVEOUT_SIZE_MB) = params->mc_sec_carveout_size_mb; // Program MTS carveout (base and size). - MC(MC_MTS_CARVEOUT_BOM) = params->mc_mts_carveout_bom; - MC(MC_MTS_CARVEOUT_ADR_HI) = params->mc_mts_carveout_adr_hi; + MC(MC_MTS_CARVEOUT_BOM) = params->mc_mts_carveout_bom; + MC(MC_MTS_CARVEOUT_ADR_HI) = params->mc_mts_carveout_adr_hi; MC(MC_MTS_CARVEOUT_SIZE_MB) = params->mc_mts_carveout_size_mb; // Program the memory arbiter. - MC(MC_EMEM_ARB_CFG) = params->mc_emem_arb_cfg; + MC(MC_EMEM_ARB_CFG) = params->mc_emem_arb_cfg; MC(MC_EMEM_ARB_OUTSTANDING_REQ) = params->mc_emem_arb_outstanding_req; - MC(MC_EMEM_ARB_REFPB_HP_CTRL) = params->emc_emem_arb_refpb_hp_ctrl; + MC(MC_EMEM_ARB_REFPB_HP_CTRL) = params->emc_emem_arb_refpb_hp_ctrl; MC(MC_EMEM_ARB_REFPB_BANK_CTRL) = params->emc_emem_arb_refpb_bank_ctrl; - MC(MC_EMEM_ARB_TIMING_RCD) = params->mc_emem_arb_timing_rcd; - MC(MC_EMEM_ARB_TIMING_RP) = params->mc_emem_arb_timing_rp; - MC(MC_EMEM_ARB_TIMING_RC) = params->mc_emem_arb_timing_rc; - MC(MC_EMEM_ARB_TIMING_RAS) = params->mc_emem_arb_timing_ras; - MC(MC_EMEM_ARB_TIMING_FAW) = params->mc_emem_arb_timing_faw; - MC(MC_EMEM_ARB_TIMING_RRD) = params->mc_emem_arb_timing_rrd; - MC(MC_EMEM_ARB_TIMING_RAP2PRE) = params->mc_emem_arb_timing_rap2pre; - MC(MC_EMEM_ARB_TIMING_WAP2PRE) = params->mc_emem_arb_timing_wap2pre; - MC(MC_EMEM_ARB_TIMING_R2R) = params->mc_emem_arb_timing_r2r; - MC(MC_EMEM_ARB_TIMING_W2W) = params->mc_emem_arb_timing_w2w; - MC(MC_EMEM_ARB_TIMING_CCDMW) = params->mc_emem_arb_timing_ccdmw; - MC(MC_EMEM_ARB_TIMING_R2W) = params->mc_emem_arb_timing_r2w; - MC(MC_EMEM_ARB_TIMING_W2R) = params->mc_emem_arb_timing_w2r; - MC(MC_EMEM_ARB_TIMING_RFCPB) = params->mc_emem_arb_timing_rfcpb; - MC(MC_EMEM_ARB_DA_TURNS) = params->mc_emem_arb_da_turns; - MC(MC_EMEM_ARB_DA_COVERS) = params->mc_emem_arb_da_covers; - MC(MC_EMEM_ARB_MISC0) = params->mc_emem_arb_misc0; - MC(MC_EMEM_ARB_MISC1) = params->mc_emem_arb_misc1; - MC(MC_EMEM_ARB_MISC2) = params->mc_emem_arb_misc2; - MC(MC_EMEM_ARB_RING1_THROTTLE) = params->mc_emem_arb_ring1_throttle; - MC(MC_EMEM_ARB_OVERRIDE) = params->mc_emem_arb_override; - MC(MC_EMEM_ARB_OVERRIDE_1) = params->mc_emem_arb_override1; - MC(MC_EMEM_ARB_RSV) = params->mc_emem_arb_rsv; - MC(MC_DA_CONFIG0) = params->mc_da_cfg0; + MC(MC_EMEM_ARB_TIMING_RCD) = params->mc_emem_arb_timing_rcd; + MC(MC_EMEM_ARB_TIMING_RP) = params->mc_emem_arb_timing_rp; + MC(MC_EMEM_ARB_TIMING_RC) = params->mc_emem_arb_timing_rc; + MC(MC_EMEM_ARB_TIMING_RAS) = params->mc_emem_arb_timing_ras; + MC(MC_EMEM_ARB_TIMING_FAW) = params->mc_emem_arb_timing_faw; + MC(MC_EMEM_ARB_TIMING_RRD) = params->mc_emem_arb_timing_rrd; + MC(MC_EMEM_ARB_TIMING_RAP2PRE) = params->mc_emem_arb_timing_rap2pre; + MC(MC_EMEM_ARB_TIMING_WAP2PRE) = params->mc_emem_arb_timing_wap2pre; + MC(MC_EMEM_ARB_TIMING_R2R) = params->mc_emem_arb_timing_r2r; + MC(MC_EMEM_ARB_TIMING_W2W) = params->mc_emem_arb_timing_w2w; + MC(MC_EMEM_ARB_TIMING_CCDMW) = params->mc_emem_arb_timing_ccdmw; + MC(MC_EMEM_ARB_TIMING_R2W) = params->mc_emem_arb_timing_r2w; + MC(MC_EMEM_ARB_TIMING_W2R) = params->mc_emem_arb_timing_w2r; + MC(MC_EMEM_ARB_TIMING_RFCPB) = params->mc_emem_arb_timing_rfcpb; + MC(MC_EMEM_ARB_DA_TURNS) = params->mc_emem_arb_da_turns; + MC(MC_EMEM_ARB_DA_COVERS) = params->mc_emem_arb_da_covers; + MC(MC_EMEM_ARB_MISC0) = params->mc_emem_arb_misc0; + MC(MC_EMEM_ARB_MISC1) = params->mc_emem_arb_misc1; + MC(MC_EMEM_ARB_MISC2) = params->mc_emem_arb_misc2; + MC(MC_EMEM_ARB_RING1_THROTTLE) = params->mc_emem_arb_ring1_throttle; + MC(MC_EMEM_ARB_OVERRIDE) = params->mc_emem_arb_override; + MC(MC_EMEM_ARB_OVERRIDE_1) = params->mc_emem_arb_override1; + MC(MC_EMEM_ARB_RSV) = params->mc_emem_arb_rsv; + MC(MC_DA_CONFIG0) = params->mc_da_cfg0; - MC(MC_TIMING_CONTROL) = 1; // Trigger MC timing update. + // Trigger MC timing update. + MC(MC_TIMING_CONTROL) = 1; // Program second-level clock enable overrides. MC(MC_CLKEN_OVERRIDE) = params->mc_clken_override; @@ -479,8 +586,9 @@ break_nosleep: EMC(EMC_AUTO_CAL_VREF_SEL_0) = params->emc_auto_cal_vref_sel0; EMC(EMC_AUTO_CAL_VREF_SEL_1) = params->emc_auto_cal_vref_sel1; + // Program/Start auto calibration. EMC(EMC_AUTO_CAL_INTERVAL) = params->emc_auto_cal_interval; - EMC(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config; + EMC(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config; usleep(params->emc_auto_cal_wait); // Patch 5 using BCT spare variables. @@ -488,96 +596,100 @@ break_nosleep: *(vu32 *)params->emc_bct_spare8 = params->emc_bct_spare9; // Program EMC timing configuration. - EMC(EMC_CFG_2) = params->emc_cfg2; - EMC(EMC_CFG_PIPE) = params->emc_cfg_pipe; - EMC(EMC_CFG_PIPE_1) = params->emc_cfg_pipe1; - EMC(EMC_CFG_PIPE_2) = params->emc_cfg_pipe2; - EMC(EMC_CMDQ) = params->emc_cmd_q; - EMC(EMC_MC2EMCQ) = params->emc_mc2emc_q; - EMC(EMC_MRS_WAIT_CNT) = params->emc_mrs_wait_cnt; - EMC(EMC_MRS_WAIT_CNT2) = params->emc_mrs_wait_cnt2; - EMC(EMC_FBIO_CFG5) = params->emc_fbio_cfg5; - EMC(EMC_RC) = params->emc_rc; - EMC(EMC_RFC) = params->emc_rfc; - EMC(EMC_RFCPB) = params->emc_rfc_pb; - EMC(EMC_REFCTRL2) = params->emc_ref_ctrl2; - EMC(EMC_RFC_SLR) = params->emc_rfc_slr; - EMC(EMC_RAS) = params->emc_ras; - EMC(EMC_RP) = params->emc_rp; - EMC(EMC_TPPD) = params->emc_tppd; - EMC(EMC_R2R) = params->emc_r2r; - EMC(EMC_W2W) = params->emc_w2w; - EMC(EMC_R2W) = params->emc_r2w; - EMC(EMC_W2R) = params->emc_w2r; - EMC(EMC_R2P) = params->emc_r2p; - EMC(EMC_W2P) = params->emc_w2p; - EMC(EMC_CCDMW) = params->emc_ccdmw; - EMC(EMC_RD_RCD) = params->emc_rd_rcd; - EMC(EMC_WR_RCD) = params->emc_wr_rcd; - EMC(EMC_RRD) = params->emc_rrd; - EMC(EMC_REXT) = params->emc_rext; - EMC(EMC_WEXT) = params->emc_wext; - EMC(EMC_WDV) = params->emc_wdv; - EMC(EMC_WDV_CHK) = params->emc_wdv_chk; - EMC(EMC_WSV) = params->emc_wsv; - EMC(EMC_WEV) = params->emc_wev; - EMC(EMC_WDV_MASK) = params->emc_wdv_mask; - EMC(EMC_WS_DURATION) = params->emc_ws_duration; - EMC(EMC_WE_DURATION) = params->emc_we_duration; - EMC(EMC_QUSE) = params->emc_quse; - EMC(EMC_QUSE_WIDTH) = params->emc_quse_width; - EMC(EMC_IBDLY) = params->emc_ibdly; - EMC(EMC_OBDLY) = params->emc_obdly; - EMC(EMC_EINPUT) = params->emc_einput; + EMC(EMC_CFG_2) = params->emc_cfg2; + EMC(EMC_CFG_PIPE) = params->emc_cfg_pipe; + EMC(EMC_CFG_PIPE_1) = params->emc_cfg_pipe1; + EMC(EMC_CFG_PIPE_2) = params->emc_cfg_pipe2; + EMC(EMC_CMDQ) = params->emc_cmd_q; + EMC(EMC_MC2EMCQ) = params->emc_mc2emc_q; + EMC(EMC_MRS_WAIT_CNT) = params->emc_mrs_wait_cnt; + EMC(EMC_MRS_WAIT_CNT2) = params->emc_mrs_wait_cnt2; + EMC(EMC_FBIO_CFG5) = params->emc_fbio_cfg5; + EMC(EMC_RC) = params->emc_rc; + EMC(EMC_RFC) = params->emc_rfc; + EMC(EMC_RFCPB) = params->emc_rfc_pb; + EMC(EMC_REFCTRL2) = params->emc_ref_ctrl2; + EMC(EMC_RFC_SLR) = params->emc_rfc_slr; + EMC(EMC_RAS) = params->emc_ras; + EMC(EMC_RP) = params->emc_rp; + EMC(EMC_TPPD) = params->emc_tppd; + EMC(EMC_R2R) = params->emc_r2r; + EMC(EMC_W2W) = params->emc_w2w; + EMC(EMC_R2W) = params->emc_r2w; + EMC(EMC_W2R) = params->emc_w2r; + EMC(EMC_R2P) = params->emc_r2p; + EMC(EMC_W2P) = params->emc_w2p; + EMC(EMC_CCDMW) = params->emc_ccdmw; + EMC(EMC_RD_RCD) = params->emc_rd_rcd; + EMC(EMC_WR_RCD) = params->emc_wr_rcd; + EMC(EMC_RRD) = params->emc_rrd; + EMC(EMC_REXT) = params->emc_rext; + EMC(EMC_WEXT) = params->emc_wext; + EMC(EMC_WDV) = params->emc_wdv; + EMC(EMC_WDV_CHK) = params->emc_wdv_chk; + EMC(EMC_WSV) = params->emc_wsv; + EMC(EMC_WEV) = params->emc_wev; + EMC(EMC_WDV_MASK) = params->emc_wdv_mask; + EMC(EMC_WS_DURATION) = params->emc_ws_duration; + EMC(EMC_WE_DURATION) = params->emc_we_duration; + EMC(EMC_QUSE) = params->emc_quse; + EMC(EMC_QUSE_WIDTH) = params->emc_quse_width; + EMC(EMC_IBDLY) = params->emc_ibdly; + EMC(EMC_OBDLY) = params->emc_obdly; + EMC(EMC_EINPUT) = params->emc_einput; EMC(EMC_EINPUT_DURATION) = params->emc_einput_duration; - EMC(EMC_PUTERM_EXTRA) = params->emc_puterm_extra; - EMC(EMC_PUTERM_WIDTH) = params->emc_puterm_width; + EMC(EMC_PUTERM_EXTRA) = params->emc_puterm_extra; + EMC(EMC_PUTERM_WIDTH) = params->emc_puterm_width; EMC(EMC_PMACRO_COMMON_PAD_TX_CTRL) = params->emc_pmacro_common_pad_tx_ctrl; - EMC(EMC_DBG) = params->emc_dbg; - EMC(EMC_QRST) = params->emc_qrst; - EMC(EMC_ISSUE_QRST) = 1; - EMC(EMC_ISSUE_QRST) = 0; - EMC(EMC_QSAFE) = params->emc_qsafe; - EMC(EMC_RDV) = params->emc_rdv; - EMC(EMC_RDV_MASK) = params->emc_rdv_mask; - EMC(EMC_RDV_EARLY) = params->emc_rdv_early; - EMC(EMC_RDV_EARLY_MASK) = params->emc_rdv_early_mask; - EMC(EMC_QPOP) = params->emc_qpop; - EMC(EMC_REFRESH) = params->emc_refresh; - EMC(EMC_BURST_REFRESH_NUM) = params->emc_burst_refresh_num; + EMC(EMC_DBG) = params->emc_dbg; + + // Clear read fifo. + EMC(EMC_QRST) = params->emc_qrst; + EMC(EMC_ISSUE_QRST) = 1; + EMC(EMC_ISSUE_QRST) = 0; + + // Program the rest of EMC timing configuration. + EMC(EMC_QSAFE) = params->emc_qsafe; + EMC(EMC_RDV) = params->emc_rdv; + EMC(EMC_RDV_MASK) = params->emc_rdv_mask; + EMC(EMC_RDV_EARLY) = params->emc_rdv_early; + EMC(EMC_RDV_EARLY_MASK) = params->emc_rdv_early_mask; + EMC(EMC_QPOP) = params->emc_qpop; + EMC(EMC_REFRESH) = params->emc_refresh; + EMC(EMC_BURST_REFRESH_NUM) = params->emc_burst_refresh_num; EMC(EMC_PRE_REFRESH_REQ_CNT) = params->emc_prerefresh_req_cnt; - EMC(EMC_PDEX2WR) = params->emc_pdex2wr; - EMC(EMC_PDEX2RD) = params->emc_pdex2rd; - EMC(EMC_PCHG2PDEN) = params->emc_pchg2pden; - EMC(EMC_ACT2PDEN) = params->emc_act2pden; - EMC(EMC_AR2PDEN) = params->emc_ar2pden; - EMC(EMC_RW2PDEN) = params->emc_rw2pden; - EMC(EMC_CKE2PDEN) = params->emc_cke2pden; - EMC(EMC_PDEX2CKE) = params->emc_pdex2che; - EMC(EMC_PDEX2MRR) = params->emc_pdex2mrr; - EMC(EMC_TXSR) = params->emc_txsr; - EMC(EMC_TXSRDLL) = params->emc_txsr_dll; - EMC(EMC_TCKE) = params->emc_tcke; - EMC(EMC_TCKESR) = params->emc_tckesr; - EMC(EMC_TPD) = params->emc_tpd; - EMC(EMC_TFAW) = params->emc_tfaw; - EMC(EMC_TRPAB) = params->emc_trpab; - EMC(EMC_TCLKSTABLE) = params->emc_tclkstable; - EMC(EMC_TCLKSTOP) = params->emc_tclkstop; - EMC(EMC_TREFBW) = params->emc_trefbw; - EMC(EMC_ODT_WRITE) = params->emc_odt_write; - EMC(EMC_CFG_DIG_DLL) = params->emc_cfg_dig_dll; - EMC(EMC_CFG_DIG_DLL_PERIOD) = params->emc_cfg_dig_dll_period; + EMC(EMC_PDEX2WR) = params->emc_pdex2wr; + EMC(EMC_PDEX2RD) = params->emc_pdex2rd; + EMC(EMC_PCHG2PDEN) = params->emc_pchg2pden; + EMC(EMC_ACT2PDEN) = params->emc_act2pden; + EMC(EMC_AR2PDEN) = params->emc_ar2pden; + EMC(EMC_RW2PDEN) = params->emc_rw2pden; + EMC(EMC_CKE2PDEN) = params->emc_cke2pden; + EMC(EMC_PDEX2CKE) = params->emc_pdex2che; + EMC(EMC_PDEX2MRR) = params->emc_pdex2mrr; + EMC(EMC_TXSR) = params->emc_txsr; + EMC(EMC_TXSRDLL) = params->emc_txsr_dll; + EMC(EMC_TCKE) = params->emc_tcke; + EMC(EMC_TCKESR) = params->emc_tckesr; + EMC(EMC_TPD) = params->emc_tpd; + EMC(EMC_TFAW) = params->emc_tfaw; + EMC(EMC_TRPAB) = params->emc_trpab; + EMC(EMC_TCLKSTABLE) = params->emc_tclkstable; + EMC(EMC_TCLKSTOP) = params->emc_tclkstop; + EMC(EMC_TREFBW) = params->emc_trefbw; + EMC(EMC_ODT_WRITE) = params->emc_odt_write; + EMC(EMC_CFG_DIG_DLL) = params->emc_cfg_dig_dll; + EMC(EMC_CFG_DIG_DLL_PERIOD) = params->emc_cfg_dig_dll_period; // Don't write CFG_ADR_EN (bit 1) here - lock bit written later. - EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare & 0xFFFFFFFD; - EMC(EMC_CFG_RSV) = params->emc_cfg_rsv; + EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare & 0xFFFFFFFD; + EMC(EMC_CFG_RSV) = params->emc_cfg_rsv; EMC(EMC_PMC_SCRATCH1) = params->emc_pmc_scratch1; EMC(EMC_PMC_SCRATCH2) = params->emc_pmc_scratch2; EMC(EMC_PMC_SCRATCH3) = params->emc_pmc_scratch3; EMC(EMC_ACPD_CONTROL) = params->emc_acpd_control; - EMC(EMC_TXDSRVTTGEN) = params->emc_txdsrvttgen; + EMC(EMC_TXDSRVTTGEN) = params->emc_txdsrvttgen; // Set pipe bypass enable bits before sending any DRAM commands. EMC(EMC_CFG) = (params->emc_cfg & 0xE) | 0x3C00000; @@ -586,14 +698,16 @@ break_nosleep: if (params->boot_rom_patch_control & BIT(31)) { *(vu32 *)(APB_MISC_BASE + params->boot_rom_patch_control * 4) = params->boot_rom_patch_data; - MC(MC_TIMING_CONTROL) = 1; // Trigger MC timing update. + + // Trigger MC timing update. + MC(MC_TIMING_CONTROL) = 1; } // Release SEL_DPD_CMD. - PMC(APBDEV_PMC_IO_DPD3_REQ) = ((params->emc_pmc_scratch1 & 0x3FFFFFFF) | 0x40000000) & 0xCFFF0000; + PMC(APBDEV_PMC_IO_DPD3_REQ) = (params->emc_pmc_scratch1 & 0xFFF0000) | PMC_IO_DPD_REQ_DPD_OFF; usleep(params->pmc_io_dpd3_req_wait); - // Set autocal interval if not configured. + // Stall auto call measurements if periodic calibration is disabled. if (!params->emc_auto_cal_interval) EMC(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config | 0x200; @@ -602,16 +716,12 @@ break_nosleep: // ZQ CAL setup (not actually issuing ZQ CAL now). if (params->emc_zcal_warm_cold_boot_enables & 1) { - if (params->memory_type == MEMORY_TYPE_DDR3L) - EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt << 3; - if (params->memory_type == MEMORY_TYPE_LPDDR4) - { - EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt; - EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; - } + EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt; + EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; } - EMC(EMC_TIMING_CONTROL) = 1; // Trigger timing update so above writes take place. + // Trigger timing update so above writes take place. + EMC(EMC_TIMING_CONTROL) = 1; usleep(params->emc_timing_control_wait); // Deassert HOLD_CKE_LOW. @@ -620,68 +730,51 @@ break_nosleep: // Set clock enable signal. u32 pin_gpio_cfg = (params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12); - if (params->memory_type == MEMORY_TYPE_DDR3L || params->memory_type == MEMORY_TYPE_LPDDR4) - { - EMC(EMC_PIN) = pin_gpio_cfg; - (void)EMC(EMC_PIN); - usleep(params->emc_pin_extra_wait + 200); - EMC(EMC_PIN) = pin_gpio_cfg | 0x100; - (void)EMC(EMC_PIN); - } + EMC(EMC_PIN) = pin_gpio_cfg; + (void)EMC(EMC_PIN); + usleep(params->emc_pin_extra_wait + 200); + EMC(EMC_PIN) = pin_gpio_cfg | 0x100; + (void)EMC(EMC_PIN); - if (params->memory_type == MEMORY_TYPE_LPDDR4) - usleep(params->emc_pin_extra_wait + 2000); - else if (params->memory_type == MEMORY_TYPE_DDR3L) - usleep(params->emc_pin_extra_wait + 500); + usleep(params->emc_pin_extra_wait + 2000); // Enable clock enable signal. EMC(EMC_PIN) = pin_gpio_cfg | 0x101; (void)EMC(EMC_PIN); usleep(params->emc_pin_program_wait); - // Send NOP (trigger just needs to be non-zero). - if (params->memory_type != MEMORY_TYPE_LPDDR4) - EMC(EMC_NOP) = (params->emc_dev_select << 30) + 1; - - // On coldboot w/LPDDR2/3, wait 200 uSec after asserting CKE high. - if (params->memory_type == MEMORY_TYPE_LPDDR2) - usleep(params->emc_pin_extra_wait + 200); - // Init zq calibration, - if (params->memory_type == MEMORY_TYPE_LPDDR4) + // Patch 6 using BCT spare variables. + if (params->emc_bct_spare10) + *(vu32 *)params->emc_bct_spare10 = params->emc_bct_spare11; + + // Write mode registers. + EMC(EMC_MRW2) = params->emc_mrw2; + EMC(EMC_MRW) = params->emc_mrw1; + EMC(EMC_MRW3) = params->emc_mrw3; + EMC(EMC_MRW4) = params->emc_mrw4; + EMC(EMC_MRW6) = params->emc_mrw6; + EMC(EMC_MRW14) = params->emc_mrw14; + + EMC(EMC_MRW8) = params->emc_mrw8; + EMC(EMC_MRW12) = params->emc_mrw12; + EMC(EMC_MRW9) = params->emc_mrw9; + EMC(EMC_MRW13) = params->emc_mrw13; + + if (params->emc_zcal_warm_cold_boot_enables & 1) { - // Patch 6 using BCT spare variables. - if (params->emc_bct_spare10) - *(vu32 *)params->emc_bct_spare10 = params->emc_bct_spare11; + // Issue ZQCAL start, device 0. + EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev0; + usleep(params->emc_zcal_init_wait); - // Write mode registers. - EMC(EMC_MRW2) = params->emc_mrw2; - EMC(EMC_MRW) = params->emc_mrw1; - EMC(EMC_MRW3) = params->emc_mrw3; - EMC(EMC_MRW4) = params->emc_mrw4; - EMC(EMC_MRW6) = params->emc_mrw6; - EMC(EMC_MRW14) = params->emc_mrw14; - - EMC(EMC_MRW8) = params->emc_mrw8; - EMC(EMC_MRW12) = params->emc_mrw12; - EMC(EMC_MRW9) = params->emc_mrw9; - EMC(EMC_MRW13) = params->emc_mrw13; - - if (params->emc_zcal_warm_cold_boot_enables & 1) + // Issue ZQCAL latch. + EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev0 ^ 3; + // Same for device 1. + if (!(params->emc_dev_select & 2)) { - // Issue ZQCAL start, device 0. - EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev0; + EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev1; usleep(params->emc_zcal_init_wait); - - // Issue ZQCAL latch. - EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev0 ^ 3; - // Same for device 1. - if (!(params->emc_dev_select & 2)) - { - EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev1; - usleep(params->emc_zcal_init_wait); - EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev1 ^ 3; - } + EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev1 ^ 3; } } @@ -689,36 +782,35 @@ break_nosleep: PMC(APBDEV_PMC_DDR_CFG) = params->pmc_ddr_cfg; // Start periodic ZQ calibration (LPDDRx only). - if (params->memory_type && params->memory_type <= MEMORY_TYPE_LPDDR4) - { - EMC(EMC_ZCAL_INTERVAL) = params->emc_zcal_interval; - EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt; - EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; - } + EMC(EMC_ZCAL_INTERVAL) = params->emc_zcal_interval; + EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt; + EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; // Patch 7 using BCT spare variables. if (params->emc_bct_spare12) *(vu32 *)params->emc_bct_spare12 = params->emc_bct_spare13; - EMC(EMC_TIMING_CONTROL) = 1; // Trigger timing update so above writes take place. + // Trigger timing update so above writes take place. + EMC(EMC_TIMING_CONTROL) = 1; if (params->emc_extra_refresh_num) EMC(EMC_REF) = (((1 << params->emc_extra_refresh_num) - 1) << 8) | (params->emc_dev_select << 30) | 3; // Enable refresh. - EMC(EMC_REFCTRL) = params->emc_dev_select | 0x80000000; + EMC(EMC_REFCTRL) = params->emc_dev_select | BIT(31); EMC(EMC_DYN_SELF_REF_CONTROL) = params->emc_dyn_self_ref_control; - EMC(EMC_CFG_UPDATE) = params->emc_cfg_update; - EMC(EMC_CFG) = params->emc_cfg; - EMC(EMC_FDPD_CTRL_DQ) = params->emc_fdpd_ctrl_dq; + EMC(EMC_CFG_UPDATE) = params->emc_cfg_update; + EMC(EMC_CFG) = params->emc_cfg; + EMC(EMC_FDPD_CTRL_DQ) = params->emc_fdpd_ctrl_dq; EMC(EMC_FDPD_CTRL_CMD) = params->emc_fdpd_ctrl_cmd; - EMC(EMC_SEL_DPD_CTRL) = params->emc_sel_dpd_ctrl; + EMC(EMC_SEL_DPD_CTRL) = params->emc_sel_dpd_ctrl; // Write addr swizzle lock bit. - EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare | 2; + EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare | BIT(1); - EMC(EMC_TIMING_CONTROL) = 1; // Re-trigger timing to latch power saving functions. + // Re-trigger timing to latch power saving functions. + EMC(EMC_TIMING_CONTROL) = 1; // Enable EMC pipe clock gating. EMC(EMC_CFG_PIPE_CLK) = params->emc_cfg_pipe_clk; @@ -731,8 +823,8 @@ break_nosleep: // Lock carveouts per BCT cfg. MC(MC_VIDEO_PROTECT_REG_CTRL) = params->mc_video_protect_write_access; - MC(MC_SEC_CARVEOUT_REG_CTRL) = params->mc_sec_carveout_protect_write_access; - MC(MC_MTS_CARVEOUT_REG_CTRL) = params->mc_mts_carveout_reg_ctrl; + MC(MC_SEC_CARVEOUT_REG_CTRL) = params->mc_sec_carveout_protect_write_access; + MC(MC_MTS_CARVEOUT_REG_CTRL) = params->mc_mts_carveout_reg_ctrl; // Disable write access to a bunch of EMC registers. MC(MC_EMEM_CFG_ACCESS_CTRL) = 1; @@ -740,8 +832,19 @@ break_nosleep: static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) { - u32 pmc_scratch1 = ~params->emc_pmc_scratch1; - u32 pmc_scratch2 = ~params->emc_pmc_scratch2; + // VDDP Select. + PMC(APBDEV_PMC_VDDP_SEL) = params->pmc_vddp_sel; + usleep(params->pmc_vddp_sel_wait); + + // Turn on MEM IO Power. + PMC(APBDEV_PMC_NO_IOPOWER) &= PMC_NO_IOPOWER_SDMMC1; // Only keep SDMMC1 state. (Was params->pmc_no_io_power). + PMC(APBDEV_PMC_REG_SHORT) = params->pmc_reg_short; + + PMC(APBDEV_PMC_DDR_CNTRL) = params->pmc_ddr_ctrl; + + // Patch 1 using BCT spare variables + if (params->emc_bct_spare0) + *(vu32 *)params->emc_bct_spare0 = params->emc_bct_spare1; // Override HW FSM if needed. if (params->clk_rst_pllm_misc20_override_enable) @@ -749,21 +852,23 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) // Program DPD3/DPD4 regs (coldboot path). // Enable sel_dpd on unused pins. - PMC(APBDEV_PMC_WEAK_BIAS) = (pmc_scratch1 & 0x1000) << 19 | (pmc_scratch1 & 0xFFF) << 18 | (pmc_scratch1 & 0x8000) << 15; - PMC(APBDEV_PMC_IO_DPD3_REQ) = (pmc_scratch1 & 0x9FFF) + 0x80000000; + u32 pmc_scratch1 = ~params->emc_pmc_scratch1; + PMC(APBDEV_PMC_WEAK_BIAS) = (pmc_scratch1 & 0x1000) << 19 | (pmc_scratch1 & 0xFFF) << 18 | (pmc_scratch1 & 0x8000) << 15; + PMC(APBDEV_PMC_IO_DPD3_REQ) = (pmc_scratch1 & 0x9FFF) | PMC_IO_DPD_REQ_DPD_ON; usleep(params->pmc_io_dpd3_req_wait); // Disable e_dpd_vttgen. - PMC(APBDEV_PMC_IO_DPD4_REQ) = (pmc_scratch2 & 0x3FFF0000) | 0x80000000; + u32 pmc_scratch2 = ~params->emc_pmc_scratch2; + PMC(APBDEV_PMC_IO_DPD4_REQ) = (pmc_scratch2 & 0x3FFF0000) | PMC_IO_DPD_REQ_DPD_ON; usleep(params->pmc_io_dpd4_req_wait); // Disable e_dpd_bg. - PMC(APBDEV_PMC_IO_DPD4_REQ) = (pmc_scratch2 & 0x1FFF) | 0x80000000; + PMC(APBDEV_PMC_IO_DPD4_REQ) = (pmc_scratch2 & 0x1FFF) | PMC_IO_DPD_REQ_DPD_ON; usleep(1); // Program CMD mapping. Required before brick mapping, else // we can't guarantee CK will be differential at all times. - EMC(EMC_FBIO_CFG7) = params->emc_fbio_cfg7; + EMC(EMC_FBIO_CFG7) = params->emc_fbio_cfg7; EMC(EMC_CMD_MAPPING_CMD0_0) = params->emc_cmd_mapping_cmd0_0; EMC(EMC_CMD_MAPPING_CMD0_1) = params->emc_cmd_mapping_cmd0_1; EMC(EMC_CMD_MAPPING_CMD0_2) = params->emc_cmd_mapping_cmd0_2; @@ -776,7 +881,7 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) EMC(EMC_CMD_MAPPING_CMD3_0) = params->emc_cmd_mapping_cmd3_0; EMC(EMC_CMD_MAPPING_CMD3_1) = params->emc_cmd_mapping_cmd3_1; EMC(EMC_CMD_MAPPING_CMD3_2) = params->emc_cmd_mapping_cmd3_2; - EMC(EMC_CMD_MAPPING_BYTE) = params->emc_cmd_mapping_byte; + EMC(EMC_CMD_MAPPING_BYTE) = params->emc_cmd_mapping_byte; // Program brick mapping. EMC(EMC_PMACRO_BRICK_MAPPING_0) = params->emc_pmacro_brick_mapping0; @@ -799,11 +904,12 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) if (params->emc_bct_spare_secure4) *(vu32 *)params->emc_bct_spare_secure4 = params->emc_bct_spare_secure5; - EMC(EMC_TIMING_CONTROL) = 1; // Trigger timing update so above writes take place. + // Trigger timing update so above writes take place. + EMC(EMC_TIMING_CONTROL) = 1; usleep(params->pmc_vddp_sel_wait + 2); // Ensure the regulators settle. // Set clock sources. - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = params->emc_clock_source; + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) = params->emc_clock_source; CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL) = params->emc_clock_source_dll; // Select EMC write mux. @@ -816,6 +922,7 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) // This is required to do any reads from the pad macros. EMC(EMC_CONFIG_SAMPLE_DELAY) = params->emc_config_sample_delay; + // Set data pipes mode. EMC(EMC_FBIO_CFG8) = params->emc_fbio_cfg8; // Set swizzle for Rank 0. @@ -833,12 +940,12 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) if (params->emc_bct_spare6) *(vu32 *)params->emc_bct_spare6 = params->emc_bct_spare7; - // Set pad controls. - EMC(EMC_XM2COMPPADCTRL) = params->emc_xm2_comp_pad_ctrl; + // Program calibration impedance. + EMC(EMC_XM2COMPPADCTRL) = params->emc_xm2_comp_pad_ctrl; EMC(EMC_XM2COMPPADCTRL2) = params->emc_xm2_comp_pad_ctrl2; EMC(EMC_XM2COMPPADCTRL3) = params->emc_xm2_comp_pad_ctrl3; - // Program Autocal controls with shadowed register fields. + // Program Autocal controls. EMC(EMC_AUTO_CAL_CONFIG2) = params->emc_auto_cal_config2; EMC(EMC_AUTO_CAL_CONFIG3) = params->emc_auto_cal_config3; EMC(EMC_AUTO_CAL_CONFIG4) = params->emc_auto_cal_config4; @@ -847,51 +954,56 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) EMC(EMC_AUTO_CAL_CONFIG7) = params->emc_auto_cal_config7; EMC(EMC_AUTO_CAL_CONFIG8) = params->emc_auto_cal_config8; - EMC(EMC_PMACRO_RX_TERM) = params->emc_pmacro_rx_term; - EMC(EMC_PMACRO_DQ_TX_DRV) = params->emc_pmacro_dq_tx_drive; - EMC(EMC_PMACRO_CA_TX_DRV) = params->emc_pmacro_ca_tx_drive; - EMC(EMC_PMACRO_CMD_TX_DRV) = params->emc_pmacro_cmd_tx_drive; + // Program termination and drive strength + EMC(EMC_PMACRO_RX_TERM) = params->emc_pmacro_rx_term; + EMC(EMC_PMACRO_DQ_TX_DRV) = params->emc_pmacro_dq_tx_drive; + EMC(EMC_PMACRO_CA_TX_DRV) = params->emc_pmacro_ca_tx_drive; + EMC(EMC_PMACRO_CMD_TX_DRV) = params->emc_pmacro_cmd_tx_drive; EMC(EMC_PMACRO_AUTOCAL_CFG_COMMON) = params->emc_pmacro_auto_cal_common; - EMC(EMC_AUTO_CAL_CHANNEL) = params->emc_auto_cal_channel; - EMC(EMC_PMACRO_ZCTRL) = params->emc_pmacro_zcrtl; + EMC(EMC_AUTO_CAL_CHANNEL) = params->emc_auto_cal_channel; + EMC(EMC_PMACRO_ZCTRL) = params->emc_pmacro_zcrtl; - EMC(EMC_DLL_CFG_0) = params->emc_dll_cfg0; - EMC(EMC_DLL_CFG_1) = params->emc_dll_cfg1; + // Program dll config. + EMC(EMC_DLL_CFG_0) = params->emc_dll_cfg0; + EMC(EMC_DLL_CFG_1) = params->emc_dll_cfg1; EMC(EMC_CFG_DIG_DLL_1) = params->emc_cfg_dig_dll_1; + // Program barrelshift. EMC(EMC_DATA_BRLSHFT_0) = params->emc_data_brlshft0; EMC(EMC_DATA_BRLSHFT_1) = params->emc_data_brlshft1; - EMC(EMC_DQS_BRLSHFT_0) = params->emc_dqs_brlshft0; - EMC(EMC_DQS_BRLSHFT_1) = params->emc_dqs_brlshft1; - EMC(EMC_CMD_BRLSHFT_0) = params->emc_cmd_brlshft0; - EMC(EMC_CMD_BRLSHFT_1) = params->emc_cmd_brlshft1; - EMC(EMC_CMD_BRLSHFT_2) = params->emc_cmd_brlshft2; - EMC(EMC_CMD_BRLSHFT_3) = params->emc_cmd_brlshft3; + EMC(EMC_DQS_BRLSHFT_0) = params->emc_dqs_brlshft0; + EMC(EMC_DQS_BRLSHFT_1) = params->emc_dqs_brlshft1; + EMC(EMC_CMD_BRLSHFT_0) = params->emc_cmd_brlshft0; + EMC(EMC_CMD_BRLSHFT_1) = params->emc_cmd_brlshft1; + EMC(EMC_CMD_BRLSHFT_2) = params->emc_cmd_brlshft2; + EMC(EMC_CMD_BRLSHFT_3) = params->emc_cmd_brlshft3; EMC(EMC_QUSE_BRLSHFT_0) = params->emc_quse_brlshft0; EMC(EMC_QUSE_BRLSHFT_1) = params->emc_quse_brlshft1; EMC(EMC_QUSE_BRLSHFT_2) = params->emc_quse_brlshft2; EMC(EMC_QUSE_BRLSHFT_3) = params->emc_quse_brlshft3; + // Program pad macros controls and termination. EMC(EMC_PMACRO_BRICK_CTRL_RFU1) = params->emc_pmacro_brick_ctrl_rfu1; - EMC(EMC_PMACRO_PAD_CFG_CTRL) = params->emc_pmacro_pad_cfg_ctrl; + EMC(EMC_PMACRO_PAD_CFG_CTRL) = params->emc_pmacro_pad_cfg_ctrl; - EMC(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->emc_pmacro_cmd_brick_ctrl_fdpd; - EMC(EMC_PMACRO_BRICK_CTRL_RFU2) = params->emc_pmacro_brick_ctrl_rfu2; + EMC(EMC_PMACRO_CMD_BRICK_CTRL_FDPD) = params->emc_pmacro_cmd_brick_ctrl_fdpd; + EMC(EMC_PMACRO_BRICK_CTRL_RFU2) = params->emc_pmacro_brick_ctrl_rfu2; EMC(EMC_PMACRO_DATA_BRICK_CTRL_FDPD) = params->emc_pmacro_data_brick_ctrl_fdpd; - EMC(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->emc_pmacro_data_pad_rx_ctrl; - EMC(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->emc_pmacro_cmd_pad_rx_ctrl; - EMC(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->emc_pmacro_data_pad_tx_ctrl; - EMC(EMC_PMACRO_DATA_RX_TERM_MODE) = params->emc_pmacro_data_rx_term_mode; - EMC(EMC_PMACRO_CMD_RX_TERM_MODE) = params->emc_pmacro_cmd_rx_term_mode; - EMC(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->emc_pmacro_cmd_pad_tx_ctrl & 0xEFFFFFFF; + EMC(EMC_PMACRO_DATA_PAD_RX_CTRL) = params->emc_pmacro_data_pad_rx_ctrl; + EMC(EMC_PMACRO_CMD_PAD_RX_CTRL) = params->emc_pmacro_cmd_pad_rx_ctrl; + EMC(EMC_PMACRO_DATA_PAD_TX_CTRL) = params->emc_pmacro_data_pad_tx_ctrl; + EMC(EMC_PMACRO_DATA_RX_TERM_MODE) = params->emc_pmacro_data_rx_term_mode; + EMC(EMC_PMACRO_CMD_RX_TERM_MODE) = params->emc_pmacro_cmd_rx_term_mode; + EMC(EMC_PMACRO_CMD_PAD_TX_CTRL) = params->emc_pmacro_cmd_pad_tx_ctrl & 0xEFFFFFFF; - EMC(EMC_CFG_3) = params->emc_cfg3; - EMC(EMC_PMACRO_TX_PWRD_0) = params->emc_pmacro_tx_pwrd0; - EMC(EMC_PMACRO_TX_PWRD_1) = params->emc_pmacro_tx_pwrd1; - EMC(EMC_PMACRO_TX_PWRD_2) = params->emc_pmacro_tx_pwrd2; - EMC(EMC_PMACRO_TX_PWRD_3) = params->emc_pmacro_tx_pwrd3; - EMC(EMC_PMACRO_TX_PWRD_4) = params->emc_pmacro_tx_pwrd4; - EMC(EMC_PMACRO_TX_PWRD_5) = params->emc_pmacro_tx_pwrd5; + // Program pad macro pins/bytes. + EMC(EMC_CFG_3) = params->emc_cfg3; + EMC(EMC_PMACRO_TX_PWRD_0) = params->emc_pmacro_tx_pwrd0; + EMC(EMC_PMACRO_TX_PWRD_1) = params->emc_pmacro_tx_pwrd1; + EMC(EMC_PMACRO_TX_PWRD_2) = params->emc_pmacro_tx_pwrd2; + EMC(EMC_PMACRO_TX_PWRD_3) = params->emc_pmacro_tx_pwrd3; + EMC(EMC_PMACRO_TX_PWRD_4) = params->emc_pmacro_tx_pwrd4; + EMC(EMC_PMACRO_TX_PWRD_5) = params->emc_pmacro_tx_pwrd5; EMC(EMC_PMACRO_TX_SEL_CLK_SRC_0) = params->emc_pmacro_tx_sel_clk_src0; EMC(EMC_PMACRO_TX_SEL_CLK_SRC_1) = params->emc_pmacro_tx_sel_clk_src1; EMC(EMC_PMACRO_TX_SEL_CLK_SRC_2) = params->emc_pmacro_tx_sel_clk_src2; @@ -906,34 +1018,37 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) EMC(EMC_PMACRO_PERBIT_FGCG_CTRL_3) = params->emc_pmacro_perbit_fgcg_ctrl3; EMC(EMC_PMACRO_PERBIT_FGCG_CTRL_4) = params->emc_pmacro_perbit_fgcg_ctrl4; EMC(EMC_PMACRO_PERBIT_FGCG_CTRL_5) = params->emc_pmacro_perbit_fgcg_ctrl5; - EMC(EMC_PMACRO_PERBIT_RFU_CTRL_0) = params->emc_pmacro_perbit_rfu_ctrl0; - EMC(EMC_PMACRO_PERBIT_RFU_CTRL_1) = params->emc_pmacro_perbit_rfu_ctrl1; - EMC(EMC_PMACRO_PERBIT_RFU_CTRL_2) = params->emc_pmacro_perbit_rfu_ctrl2; - EMC(EMC_PMACRO_PERBIT_RFU_CTRL_3) = params->emc_pmacro_perbit_rfu_ctrl3; - EMC(EMC_PMACRO_PERBIT_RFU_CTRL_4) = params->emc_pmacro_perbit_rfu_ctrl4; - EMC(EMC_PMACRO_PERBIT_RFU_CTRL_5) = params->emc_pmacro_perbit_rfu_ctrl5; + EMC(EMC_PMACRO_PERBIT_RFU_CTRL_0) = params->emc_pmacro_perbit_rfu_ctrl0; + EMC(EMC_PMACRO_PERBIT_RFU_CTRL_1) = params->emc_pmacro_perbit_rfu_ctrl1; + EMC(EMC_PMACRO_PERBIT_RFU_CTRL_2) = params->emc_pmacro_perbit_rfu_ctrl2; + EMC(EMC_PMACRO_PERBIT_RFU_CTRL_3) = params->emc_pmacro_perbit_rfu_ctrl3; + EMC(EMC_PMACRO_PERBIT_RFU_CTRL_4) = params->emc_pmacro_perbit_rfu_ctrl4; + EMC(EMC_PMACRO_PERBIT_RFU_CTRL_5) = params->emc_pmacro_perbit_rfu_ctrl5; EMC(EMC_PMACRO_PERBIT_RFU1_CTRL_0) = params->emc_pmacro_perbit_rfu1_ctrl0; EMC(EMC_PMACRO_PERBIT_RFU1_CTRL_1) = params->emc_pmacro_perbit_rfu1_ctrl1; EMC(EMC_PMACRO_PERBIT_RFU1_CTRL_2) = params->emc_pmacro_perbit_rfu1_ctrl2; EMC(EMC_PMACRO_PERBIT_RFU1_CTRL_3) = params->emc_pmacro_perbit_rfu1_ctrl3; EMC(EMC_PMACRO_PERBIT_RFU1_CTRL_4) = params->emc_pmacro_perbit_rfu1_ctrl4; EMC(EMC_PMACRO_PERBIT_RFU1_CTRL_5) = params->emc_pmacro_perbit_rfu1_ctrl5; - EMC(EMC_PMACRO_DATA_PI_CTRL) = params->emc_pmacro_data_pi_ctrl; - EMC(EMC_PMACRO_CMD_PI_CTRL) = params->emc_pmacro_cmd_pi_ctrl; + EMC(EMC_PMACRO_DATA_PI_CTRL) = params->emc_pmacro_data_pi_ctrl; + EMC(EMC_PMACRO_CMD_PI_CTRL) = params->emc_pmacro_cmd_pi_ctrl; - EMC(EMC_PMACRO_DDLL_BYPASS) = params->emc_pmacro_ddll_bypass; - EMC(EMC_PMACRO_DDLL_PWRD_0) = params->emc_pmacro_ddll_pwrd0; - EMC(EMC_PMACRO_DDLL_PWRD_1) = params->emc_pmacro_ddll_pwrd1; - EMC(EMC_PMACRO_DDLL_PWRD_2) = params->emc_pmacro_ddll_pwrd2; - EMC(EMC_PMACRO_CMD_CTRL_0) = params->emc_pmacro_cmd_ctrl0; - EMC(EMC_PMACRO_CMD_CTRL_1) = params->emc_pmacro_cmd_ctrl1; - EMC(EMC_PMACRO_CMD_CTRL_2) = params->emc_pmacro_cmd_ctrl2; - EMC(EMC_PMACRO_IB_VREF_DQ_0) = params->emc_pmacro_ib_vref_dq_0; - EMC(EMC_PMACRO_IB_VREF_DQ_1) = params->emc_pmacro_ib_vref_dq_1; + EMC(EMC_PMACRO_DDLL_BYPASS) = params->emc_pmacro_ddll_bypass; + EMC(EMC_PMACRO_DDLL_PWRD_0) = params->emc_pmacro_ddll_pwrd0; + EMC(EMC_PMACRO_DDLL_PWRD_1) = params->emc_pmacro_ddll_pwrd1; + EMC(EMC_PMACRO_DDLL_PWRD_2) = params->emc_pmacro_ddll_pwrd2; + EMC(EMC_PMACRO_CMD_CTRL_0) = params->emc_pmacro_cmd_ctrl0; + EMC(EMC_PMACRO_CMD_CTRL_1) = params->emc_pmacro_cmd_ctrl1; + EMC(EMC_PMACRO_CMD_CTRL_2) = params->emc_pmacro_cmd_ctrl2; + + // Program inbound vref setting. + EMC(EMC_PMACRO_IB_VREF_DQ_0) = params->emc_pmacro_ib_vref_dq_0; + EMC(EMC_PMACRO_IB_VREF_DQ_1) = params->emc_pmacro_ib_vref_dq_1; EMC(EMC_PMACRO_IB_VREF_DQS_0) = params->emc_pmacro_ib_vref_dqs_0; EMC(EMC_PMACRO_IB_VREF_DQS_1) = params->emc_pmacro_ib_vref_dqs_1; - EMC(EMC_PMACRO_IB_RXRT) = params->emc_pmacro_ib_rxrt; + EMC(EMC_PMACRO_IB_RXRT) = params->emc_pmacro_ib_rxrt; + // Program quse trimmers. EMC(EMC_PMACRO_QUSE_DDLL_RANK0_0) = params->emc_pmacro_quse_ddll_rank0_0; EMC(EMC_PMACRO_QUSE_DDLL_RANK0_1) = params->emc_pmacro_quse_ddll_rank0_1; EMC(EMC_PMACRO_QUSE_DDLL_RANK0_2) = params->emc_pmacro_quse_ddll_rank0_2; @@ -947,6 +1062,7 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) EMC(EMC_PMACRO_QUSE_DDLL_RANK1_4) = params->emc_pmacro_quse_ddll_rank1_4; EMC(EMC_PMACRO_QUSE_DDLL_RANK1_5) = params->emc_pmacro_quse_ddll_rank1_5; + // Program outbound trimmers. EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0) = params->emc_pmacro_ob_ddll_long_dq_rank0_0; EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1) = params->emc_pmacro_ob_ddll_long_dq_rank0_1; EMC(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2) = params->emc_pmacro_ob_ddll_long_dq_rank0_2; @@ -981,11 +1097,12 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2) = params->emc_pmacro_ib_ddll_long_dqs_rank1_2; EMC(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3) = params->emc_pmacro_ib_ddll_long_dqs_rank1_3; - EMC(EMC_PMACRO_DDLL_LONG_CMD_0) = params->emc_pmacro_ddll_long_cmd_0; - EMC(EMC_PMACRO_DDLL_LONG_CMD_1) = params->emc_pmacro_ddll_long_cmd_1; - EMC(EMC_PMACRO_DDLL_LONG_CMD_2) = params->emc_pmacro_ddll_long_cmd_2; - EMC(EMC_PMACRO_DDLL_LONG_CMD_3) = params->emc_pmacro_ddll_long_cmd_3; - EMC(EMC_PMACRO_DDLL_LONG_CMD_4) = params->emc_pmacro_ddll_long_cmd_4; + // Program clock trimmers. + EMC(EMC_PMACRO_DDLL_LONG_CMD_0) = params->emc_pmacro_ddll_long_cmd_0; + EMC(EMC_PMACRO_DDLL_LONG_CMD_1) = params->emc_pmacro_ddll_long_cmd_1; + EMC(EMC_PMACRO_DDLL_LONG_CMD_2) = params->emc_pmacro_ddll_long_cmd_2; + EMC(EMC_PMACRO_DDLL_LONG_CMD_3) = params->emc_pmacro_ddll_long_cmd_3; + EMC(EMC_PMACRO_DDLL_LONG_CMD_4) = params->emc_pmacro_ddll_long_cmd_4; EMC(EMC_PMACRO_DDLL_SHORT_CMD_0) = params->emc_pmacro_ddll_short_cmd_0; EMC(EMC_PMACRO_DDLL_SHORT_CMD_1) = params->emc_pmacro_ddll_short_cmd_1; EMC(EMC_PMACRO_DDLL_SHORT_CMD_2) = params->emc_pmacro_ddll_short_cmd_2; @@ -999,27 +1116,28 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) // Patch 4 to 6 using BCT spare secure variables. if (params->emc_bct_spare_secure6) - *(vu32 *)params->emc_bct_spare_secure6 = params->emc_bct_spare_secure7; + *(vu32 *)params->emc_bct_spare_secure6 = params->emc_bct_spare_secure7; if (params->emc_bct_spare_secure8) - *(vu32 *)params->emc_bct_spare_secure8 = params->emc_bct_spare_secure9; + *(vu32 *)params->emc_bct_spare_secure8 = params->emc_bct_spare_secure9; if (params->emc_bct_spare_secure10) *(vu32 *)params->emc_bct_spare_secure10 = params->emc_bct_spare_secure11; - EMC(EMC_TIMING_CONTROL) = 1; // Trigger timing update so above writes take place. + // Trigger timing update so above writes take place. + EMC(EMC_TIMING_CONTROL) = 1; // Initialize MC VPR settings. - MC(MC_VIDEO_PROTECT_BOM) = params->mc_video_protect_bom; - MC(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->mc_video_protect_bom_adr_hi; - MC(MC_VIDEO_PROTECT_SIZE_MB) = params->mc_video_protect_size_mb; - MC(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->mc_video_protect_vpr_override; - MC(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->mc_video_protect_vpr_override1; + MC(MC_VIDEO_PROTECT_BOM) = params->mc_video_protect_bom; + MC(MC_VIDEO_PROTECT_BOM_ADR_HI) = params->mc_video_protect_bom_adr_hi; + MC(MC_VIDEO_PROTECT_SIZE_MB) = params->mc_video_protect_size_mb; + MC(MC_VIDEO_PROTECT_VPR_OVERRIDE) = params->mc_video_protect_vpr_override; + MC(MC_VIDEO_PROTECT_VPR_OVERRIDE1) = params->mc_video_protect_vpr_override1; MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_0) = params->mc_video_protect_gpu_override0; MC(MC_VIDEO_PROTECT_GPU_OVERRIDE_1) = params->mc_video_protect_gpu_override1; // Program SDRAM geometry parameters. - MC(MC_EMEM_ADR_CFG) = params->mc_emem_adr_cfg; - MC(MC_EMEM_ADR_CFG_DEV0) = params->mc_emem_adr_cfg_dev0; - MC(MC_EMEM_ADR_CFG_DEV1) = params->mc_emem_adr_cfg_dev1; + MC(MC_EMEM_ADR_CFG) = params->mc_emem_adr_cfg; + MC(MC_EMEM_ADR_CFG_DEV0) = params->mc_emem_adr_cfg_dev0; + MC(MC_EMEM_ADR_CFG_DEV1) = params->mc_emem_adr_cfg_dev1; MC(MC_EMEM_ADR_CFG_CHANNEL_MASK) = params->mc_emem_adr_cfg_channel_mask; // Program bank swizzling. @@ -1031,46 +1149,47 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) MC(MC_EMEM_CFG) = params->mc_emem_cfg; // Program SEC carveout (base and size). - MC(MC_SEC_CARVEOUT_BOM) = params->mc_sec_carveout_bom; - MC(MC_SEC_CARVEOUT_ADR_HI) = params->mc_sec_carveout_adr_hi; + MC(MC_SEC_CARVEOUT_BOM) = params->mc_sec_carveout_bom; + MC(MC_SEC_CARVEOUT_ADR_HI) = params->mc_sec_carveout_adr_hi; MC(MC_SEC_CARVEOUT_SIZE_MB) = params->mc_sec_carveout_size_mb; // Program MTS carveout (base and size). - MC(MC_MTS_CARVEOUT_BOM) = params->mc_mts_carveout_bom; - MC(MC_MTS_CARVEOUT_ADR_HI) = params->mc_mts_carveout_adr_hi; + MC(MC_MTS_CARVEOUT_BOM) = params->mc_mts_carveout_bom; + MC(MC_MTS_CARVEOUT_ADR_HI) = params->mc_mts_carveout_adr_hi; MC(MC_MTS_CARVEOUT_SIZE_MB) = params->mc_mts_carveout_size_mb; // Program the memory arbiter. - MC(MC_EMEM_ARB_CFG) = params->mc_emem_arb_cfg; + MC(MC_EMEM_ARB_CFG) = params->mc_emem_arb_cfg; MC(MC_EMEM_ARB_OUTSTANDING_REQ) = params->mc_emem_arb_outstanding_req; - MC(MC_EMEM_ARB_REFPB_HP_CTRL) = params->emc_emem_arb_refpb_hp_ctrl; + MC(MC_EMEM_ARB_REFPB_HP_CTRL) = params->emc_emem_arb_refpb_hp_ctrl; MC(MC_EMEM_ARB_REFPB_BANK_CTRL) = params->emc_emem_arb_refpb_bank_ctrl; - MC(MC_EMEM_ARB_TIMING_RCD) = params->mc_emem_arb_timing_rcd; - MC(MC_EMEM_ARB_TIMING_RP) = params->mc_emem_arb_timing_rp; - MC(MC_EMEM_ARB_TIMING_RC) = params->mc_emem_arb_timing_rc; - MC(MC_EMEM_ARB_TIMING_RAS) = params->mc_emem_arb_timing_ras; - MC(MC_EMEM_ARB_TIMING_FAW) = params->mc_emem_arb_timing_faw; - MC(MC_EMEM_ARB_TIMING_RRD) = params->mc_emem_arb_timing_rrd; - MC(MC_EMEM_ARB_TIMING_RAP2PRE) = params->mc_emem_arb_timing_rap2pre; - MC(MC_EMEM_ARB_TIMING_WAP2PRE) = params->mc_emem_arb_timing_wap2pre; - MC(MC_EMEM_ARB_TIMING_R2R) = params->mc_emem_arb_timing_r2r; - MC(MC_EMEM_ARB_TIMING_W2W) = params->mc_emem_arb_timing_w2w; - MC(MC_EMEM_ARB_TIMING_CCDMW) = params->mc_emem_arb_timing_ccdmw; - MC(MC_EMEM_ARB_TIMING_R2W) = params->mc_emem_arb_timing_r2w; - MC(MC_EMEM_ARB_TIMING_W2R) = params->mc_emem_arb_timing_w2r; - MC(MC_EMEM_ARB_TIMING_RFCPB) = params->mc_emem_arb_timing_rfcpb; - MC(MC_EMEM_ARB_DA_TURNS) = params->mc_emem_arb_da_turns; - MC(MC_EMEM_ARB_DA_COVERS) = params->mc_emem_arb_da_covers; - MC(MC_EMEM_ARB_MISC0) = params->mc_emem_arb_misc0; - MC(MC_EMEM_ARB_MISC1) = params->mc_emem_arb_misc1; - MC(MC_EMEM_ARB_MISC2) = params->mc_emem_arb_misc2; - MC(MC_EMEM_ARB_RING1_THROTTLE) = params->mc_emem_arb_ring1_throttle; - MC(MC_EMEM_ARB_OVERRIDE) = params->mc_emem_arb_override; - MC(MC_EMEM_ARB_OVERRIDE_1) = params->mc_emem_arb_override1; - MC(MC_EMEM_ARB_RSV) = params->mc_emem_arb_rsv; - MC(MC_DA_CONFIG0) = params->mc_da_cfg0; + MC(MC_EMEM_ARB_TIMING_RCD) = params->mc_emem_arb_timing_rcd; + MC(MC_EMEM_ARB_TIMING_RP) = params->mc_emem_arb_timing_rp; + MC(MC_EMEM_ARB_TIMING_RC) = params->mc_emem_arb_timing_rc; + MC(MC_EMEM_ARB_TIMING_RAS) = params->mc_emem_arb_timing_ras; + MC(MC_EMEM_ARB_TIMING_FAW) = params->mc_emem_arb_timing_faw; + MC(MC_EMEM_ARB_TIMING_RRD) = params->mc_emem_arb_timing_rrd; + MC(MC_EMEM_ARB_TIMING_RAP2PRE) = params->mc_emem_arb_timing_rap2pre; + MC(MC_EMEM_ARB_TIMING_WAP2PRE) = params->mc_emem_arb_timing_wap2pre; + MC(MC_EMEM_ARB_TIMING_R2R) = params->mc_emem_arb_timing_r2r; + MC(MC_EMEM_ARB_TIMING_W2W) = params->mc_emem_arb_timing_w2w; + MC(MC_EMEM_ARB_TIMING_CCDMW) = params->mc_emem_arb_timing_ccdmw; + MC(MC_EMEM_ARB_TIMING_R2W) = params->mc_emem_arb_timing_r2w; + MC(MC_EMEM_ARB_TIMING_W2R) = params->mc_emem_arb_timing_w2r; + MC(MC_EMEM_ARB_TIMING_RFCPB) = params->mc_emem_arb_timing_rfcpb; + MC(MC_EMEM_ARB_DA_TURNS) = params->mc_emem_arb_da_turns; + MC(MC_EMEM_ARB_DA_COVERS) = params->mc_emem_arb_da_covers; + MC(MC_EMEM_ARB_MISC0) = params->mc_emem_arb_misc0; + MC(MC_EMEM_ARB_MISC1) = params->mc_emem_arb_misc1; + MC(MC_EMEM_ARB_MISC2) = params->mc_emem_arb_misc2; + MC(MC_EMEM_ARB_RING1_THROTTLE) = params->mc_emem_arb_ring1_throttle; + MC(MC_EMEM_ARB_OVERRIDE) = params->mc_emem_arb_override; + MC(MC_EMEM_ARB_OVERRIDE_1) = params->mc_emem_arb_override1; + MC(MC_EMEM_ARB_RSV) = params->mc_emem_arb_rsv; + MC(MC_DA_CONFIG0) = params->mc_da_cfg0; - MC(MC_TIMING_CONTROL) = 1; // Trigger MC timing update. + // Trigger MC timing update. + MC(MC_TIMING_CONTROL) = 1; // Program second-level clock enable overrides. MC(MC_CLKEN_OVERRIDE) = params->mc_clken_override; @@ -1092,8 +1211,9 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) EMC(EMC_AUTO_CAL_VREF_SEL_0) = params->emc_auto_cal_vref_sel0; EMC(EMC_AUTO_CAL_VREF_SEL_1) = params->emc_auto_cal_vref_sel1; + // Program/Start auto calibration. EMC(EMC_AUTO_CAL_INTERVAL) = params->emc_auto_cal_interval; - EMC(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config; + EMC(EMC_AUTO_CAL_CONFIG) = params->emc_auto_cal_config; usleep(params->emc_auto_cal_wait); // Patch 5 using BCT spare variables. @@ -1103,99 +1223,104 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) EMC(EMC_AUTO_CAL_CONFIG9) = params->emc_auto_cal_config9; // Program EMC timing configuration. - EMC(EMC_CFG_2) = params->emc_cfg2; - EMC(EMC_CFG_PIPE) = params->emc_cfg_pipe; - EMC(EMC_CFG_PIPE_1) = params->emc_cfg_pipe1; - EMC(EMC_CFG_PIPE_2) = params->emc_cfg_pipe2; - EMC(EMC_CMDQ) = params->emc_cmd_q; - EMC(EMC_MC2EMCQ) = params->emc_mc2emc_q; - EMC(EMC_MRS_WAIT_CNT) = params->emc_mrs_wait_cnt; - EMC(EMC_MRS_WAIT_CNT2) = params->emc_mrs_wait_cnt2; - EMC(EMC_FBIO_CFG5) = params->emc_fbio_cfg5; - EMC(EMC_RC) = params->emc_rc; - EMC(EMC_RFC) = params->emc_rfc; - EMC(EMC_RFCPB) = params->emc_rfc_pb; - EMC(EMC_REFCTRL2) = params->emc_ref_ctrl2; - EMC(EMC_RFC_SLR) = params->emc_rfc_slr; - EMC(EMC_RAS) = params->emc_ras; - EMC(EMC_RP) = params->emc_rp; - EMC(EMC_TPPD) = params->emc_tppd; - EMC(EMC_CTT) = params->emc_trtm; - EMC(EMC_FBIO_TWTM) = params->emc_twtm; - EMC(EMC_FBIO_TRATM) = params->emc_tratm; - EMC(EMC_FBIO_TWATM) = params->emc_twatm; - EMC(EMC_FBIO_TR2REF) = params->emc_tr2ref; - EMC(EMC_R2R) = params->emc_r2r; - EMC(EMC_W2W) = params->emc_w2w; - EMC(EMC_R2W) = params->emc_r2w; - EMC(EMC_W2R) = params->emc_w2r; - EMC(EMC_R2P) = params->emc_r2p; - EMC(EMC_W2P) = params->emc_w2p; - EMC(EMC_CCDMW) = params->emc_ccdmw; - EMC(EMC_RD_RCD) = params->emc_rd_rcd; - EMC(EMC_WR_RCD) = params->emc_wr_rcd; - EMC(EMC_RRD) = params->emc_rrd; - EMC(EMC_REXT) = params->emc_rext; - EMC(EMC_WEXT) = params->emc_wext; - EMC(EMC_WDV) = params->emc_wdv; - EMC(EMC_WDV_CHK) = params->emc_wdv_chk; - EMC(EMC_WSV) = params->emc_wsv; - EMC(EMC_WEV) = params->emc_wev; - EMC(EMC_WDV_MASK) = params->emc_wdv_mask; - EMC(EMC_WS_DURATION) = params->emc_ws_duration; - EMC(EMC_WE_DURATION) = params->emc_we_duration; - EMC(EMC_QUSE) = params->emc_quse; - EMC(EMC_QUSE_WIDTH) = params->emc_quse_width; - EMC(EMC_IBDLY) = params->emc_ibdly; - EMC(EMC_OBDLY) = params->emc_obdly; - EMC(EMC_EINPUT) = params->emc_einput; + EMC(EMC_CFG_2) = params->emc_cfg2; + EMC(EMC_CFG_PIPE) = params->emc_cfg_pipe; + EMC(EMC_CFG_PIPE_1) = params->emc_cfg_pipe1; + EMC(EMC_CFG_PIPE_2) = params->emc_cfg_pipe2; + EMC(EMC_CMDQ) = params->emc_cmd_q; + EMC(EMC_MC2EMCQ) = params->emc_mc2emc_q; + EMC(EMC_MRS_WAIT_CNT) = params->emc_mrs_wait_cnt; + EMC(EMC_MRS_WAIT_CNT2) = params->emc_mrs_wait_cnt2; + EMC(EMC_FBIO_CFG5) = params->emc_fbio_cfg5; + EMC(EMC_RC) = params->emc_rc; + EMC(EMC_RFC) = params->emc_rfc; + EMC(EMC_RFCPB) = params->emc_rfc_pb; + EMC(EMC_REFCTRL2) = params->emc_ref_ctrl2; + EMC(EMC_RFC_SLR) = params->emc_rfc_slr; + EMC(EMC_RAS) = params->emc_ras; + EMC(EMC_RP) = params->emc_rp; + EMC(EMC_TPPD) = params->emc_tppd; + EMC(EMC_CTT) = params->emc_trtm; + EMC(EMC_FBIO_TWTM) = params->emc_twtm; + EMC(EMC_FBIO_TRATM) = params->emc_tratm; + EMC(EMC_FBIO_TWATM) = params->emc_twatm; + EMC(EMC_FBIO_TR2REF) = params->emc_tr2ref; + EMC(EMC_R2R) = params->emc_r2r; + EMC(EMC_W2W) = params->emc_w2w; + EMC(EMC_R2W) = params->emc_r2w; + EMC(EMC_W2R) = params->emc_w2r; + EMC(EMC_R2P) = params->emc_r2p; + EMC(EMC_W2P) = params->emc_w2p; + EMC(EMC_CCDMW) = params->emc_ccdmw; + EMC(EMC_RD_RCD) = params->emc_rd_rcd; + EMC(EMC_WR_RCD) = params->emc_wr_rcd; + EMC(EMC_RRD) = params->emc_rrd; + EMC(EMC_REXT) = params->emc_rext; + EMC(EMC_WEXT) = params->emc_wext; + EMC(EMC_WDV) = params->emc_wdv; + EMC(EMC_WDV_CHK) = params->emc_wdv_chk; + EMC(EMC_WSV) = params->emc_wsv; + EMC(EMC_WEV) = params->emc_wev; + EMC(EMC_WDV_MASK) = params->emc_wdv_mask; + EMC(EMC_WS_DURATION) = params->emc_ws_duration; + EMC(EMC_WE_DURATION) = params->emc_we_duration; + EMC(EMC_QUSE) = params->emc_quse; + EMC(EMC_QUSE_WIDTH) = params->emc_quse_width; + EMC(EMC_IBDLY) = params->emc_ibdly; + EMC(EMC_OBDLY) = params->emc_obdly; + EMC(EMC_EINPUT) = params->emc_einput; EMC(EMC_EINPUT_DURATION) = params->emc_einput_duration; - EMC(EMC_PUTERM_EXTRA) = params->emc_puterm_extra; - EMC(EMC_PUTERM_WIDTH) = params->emc_puterm_width; - EMC(EMC_DBG) = params->emc_dbg; - EMC(EMC_QRST) = params->emc_qrst; - EMC(EMC_ISSUE_QRST) = 1; - EMC(EMC_ISSUE_QRST) = 0; - EMC(EMC_QSAFE) = params->emc_qsafe; - EMC(EMC_RDV) = params->emc_rdv; - EMC(EMC_RDV_MASK) = params->emc_rdv_mask; - EMC(EMC_RDV_EARLY) = params->emc_rdv_early; - EMC(EMC_RDV_EARLY_MASK) = params->emc_rdv_early_mask; - EMC(EMC_QPOP) = params->emc_qpop; - EMC(EMC_REFRESH) = params->emc_refresh; - EMC(EMC_BURST_REFRESH_NUM) = params->emc_burst_refresh_num; + EMC(EMC_PUTERM_EXTRA) = params->emc_puterm_extra; + EMC(EMC_PUTERM_WIDTH) = params->emc_puterm_width; + + EMC(EMC_DBG) = params->emc_dbg; + + // Clear read fifo. + EMC(EMC_QRST) = params->emc_qrst; + EMC(EMC_ISSUE_QRST) = 1; + EMC(EMC_ISSUE_QRST) = 0; + + // Program the rest of EMC timing configuration. + EMC(EMC_QSAFE) = params->emc_qsafe; + EMC(EMC_RDV) = params->emc_rdv; + EMC(EMC_RDV_MASK) = params->emc_rdv_mask; + EMC(EMC_RDV_EARLY) = params->emc_rdv_early; + EMC(EMC_RDV_EARLY_MASK) = params->emc_rdv_early_mask; + EMC(EMC_QPOP) = params->emc_qpop; + EMC(EMC_REFRESH) = params->emc_refresh; + EMC(EMC_BURST_REFRESH_NUM) = params->emc_burst_refresh_num; EMC(EMC_PRE_REFRESH_REQ_CNT) = params->emc_prerefresh_req_cnt; - EMC(EMC_PDEX2WR) = params->emc_pdex2wr; - EMC(EMC_PDEX2RD) = params->emc_pdex2rd; - EMC(EMC_PCHG2PDEN) = params->emc_pchg2pden; - EMC(EMC_ACT2PDEN) = params->emc_act2pden; - EMC(EMC_AR2PDEN) = params->emc_ar2pden; - EMC(EMC_RW2PDEN) = params->emc_rw2pden; - EMC(EMC_CKE2PDEN) = params->emc_cke2pden; - EMC(EMC_PDEX2CKE) = params->emc_pdex2che; - EMC(EMC_PDEX2MRR) = params->emc_pdex2mrr; - EMC(EMC_TXSR) = params->emc_txsr; - EMC(EMC_TXSRDLL) = params->emc_txsr_dll; - EMC(EMC_TCKE) = params->emc_tcke; - EMC(EMC_TCKESR) = params->emc_tckesr; - EMC(EMC_TPD) = params->emc_tpd; - EMC(EMC_TFAW) = params->emc_tfaw; - EMC(EMC_TRPAB) = params->emc_trpab; - EMC(EMC_TCLKSTABLE) = params->emc_tclkstable; - EMC(EMC_TCLKSTOP) = params->emc_tclkstop; - EMC(EMC_TREFBW) = params->emc_trefbw; - EMC(EMC_ODT_WRITE) = params->emc_odt_write; - EMC(EMC_CFG_DIG_DLL) = params->emc_cfg_dig_dll; - EMC(EMC_CFG_DIG_DLL_PERIOD) = params->emc_cfg_dig_dll_period; + EMC(EMC_PDEX2WR) = params->emc_pdex2wr; + EMC(EMC_PDEX2RD) = params->emc_pdex2rd; + EMC(EMC_PCHG2PDEN) = params->emc_pchg2pden; + EMC(EMC_ACT2PDEN) = params->emc_act2pden; + EMC(EMC_AR2PDEN) = params->emc_ar2pden; + EMC(EMC_RW2PDEN) = params->emc_rw2pden; + EMC(EMC_CKE2PDEN) = params->emc_cke2pden; + EMC(EMC_PDEX2CKE) = params->emc_pdex2che; + EMC(EMC_PDEX2MRR) = params->emc_pdex2mrr; + EMC(EMC_TXSR) = params->emc_txsr; + EMC(EMC_TXSRDLL) = params->emc_txsr_dll; + EMC(EMC_TCKE) = params->emc_tcke; + EMC(EMC_TCKESR) = params->emc_tckesr; + EMC(EMC_TPD) = params->emc_tpd; + EMC(EMC_TFAW) = params->emc_tfaw; + EMC(EMC_TRPAB) = params->emc_trpab; + EMC(EMC_TCLKSTABLE) = params->emc_tclkstable; + EMC(EMC_TCLKSTOP) = params->emc_tclkstop; + EMC(EMC_TREFBW) = params->emc_trefbw; + EMC(EMC_ODT_WRITE) = params->emc_odt_write; + EMC(EMC_CFG_DIG_DLL) = params->emc_cfg_dig_dll; + EMC(EMC_CFG_DIG_DLL_PERIOD) = params->emc_cfg_dig_dll_period; // Don't write CFG_ADR_EN (bit 1) here - lock bit written later. - EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare & 0xFFFFFFFD; - EMC(EMC_CFG_RSV) = params->emc_cfg_rsv; + EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare & 0xFFFFFFFD; + EMC(EMC_CFG_RSV) = params->emc_cfg_rsv; EMC(EMC_PMC_SCRATCH1) = params->emc_pmc_scratch1; EMC(EMC_PMC_SCRATCH2) = params->emc_pmc_scratch2; EMC(EMC_PMC_SCRATCH3) = params->emc_pmc_scratch3; EMC(EMC_ACPD_CONTROL) = params->emc_acpd_control; - EMC(EMC_TXDSRVTTGEN) = params->emc_txdsrvttgen; + EMC(EMC_TXDSRVTTGEN) = params->emc_txdsrvttgen; EMC(EMC_PMACRO_DSR_VTTGEN_CTRL0) = params->emc_pmacro_dsr_vttgen_ctrl0; // Set pipe bypass enable bits before sending any DRAM commands. @@ -1205,7 +1330,9 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) if (params->boot_rom_patch_control) { *(vu32 *)params->boot_rom_patch_control = params->boot_rom_patch_data; - MC(MC_TIMING_CONTROL) = 1; // Trigger MC timing update. + + // Trigger MC timing update. + MC(MC_TIMING_CONTROL) = 1; } // Patch 7 to 9 using BCT spare secure variables. @@ -1217,7 +1344,7 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) *(vu32 *)params->emc_bct_spare_secure16 = params->emc_bct_spare_secure17; // Release SEL_DPD_CMD. - PMC(APBDEV_PMC_IO_DPD3_REQ) = ((params->emc_pmc_scratch1 & 0x3FFFFFFF) | 0x40000000) & 0xCFFF0000; + PMC(APBDEV_PMC_IO_DPD3_REQ) = (params->emc_pmc_scratch1 & 0xFFF0000) | PMC_IO_DPD_REQ_DPD_OFF; usleep(params->pmc_io_dpd3_req_wait); // Set transmission pad control parameters. @@ -1226,16 +1353,12 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) // ZQ CAL setup (not actually issuing ZQ CAL now). if (params->emc_zcal_warm_cold_boot_enables & 1) { - if (params->memory_type == MEMORY_TYPE_DDR3L) - EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt << 3; - if (params->memory_type == MEMORY_TYPE_LPDDR4) - { - EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt; - EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; - } + EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt; + EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; } - EMC(EMC_TIMING_CONTROL) = 1; // Trigger timing update so above writes take place. + // Trigger timing update so above writes take place. + EMC(EMC_TIMING_CONTROL) = 1; usleep(params->emc_timing_control_wait); // Deassert HOLD_CKE_LOW. @@ -1244,68 +1367,51 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) // Set clock enable signal. u32 pin_gpio_cfg = (params->emc_pin_gpio_enable << 16) | (params->emc_pin_gpio << 12); - if (params->memory_type == MEMORY_TYPE_DDR3L || params->memory_type == MEMORY_TYPE_LPDDR4) - { - EMC(EMC_PIN) = pin_gpio_cfg; - (void)EMC(EMC_PIN); - usleep(params->emc_pin_extra_wait + 200); - EMC(EMC_PIN) = pin_gpio_cfg | 0x100; - (void)EMC(EMC_PIN); - } + EMC(EMC_PIN) = pin_gpio_cfg; + (void)EMC(EMC_PIN); + usleep(params->emc_pin_extra_wait + 200); + EMC(EMC_PIN) = pin_gpio_cfg | 0x100; + (void)EMC(EMC_PIN); - if (params->memory_type == MEMORY_TYPE_LPDDR4) - usleep(params->emc_pin_extra_wait + 2000); - else if (params->memory_type == MEMORY_TYPE_DDR3L) - usleep(params->emc_pin_extra_wait + 500); + usleep(params->emc_pin_extra_wait + 2000); // Enable clock enable signal. EMC(EMC_PIN) = pin_gpio_cfg | 0x101; (void)EMC(EMC_PIN); usleep(params->emc_pin_program_wait); - // Send NOP (trigger just needs to be non-zero). - if (params->memory_type != MEMORY_TYPE_LPDDR4) - EMC(EMC_NOP) = (params->emc_dev_select << 30) + 1; - - // On coldboot w/LPDDR2/3, wait 200 uSec after asserting CKE high. - if (params->memory_type == MEMORY_TYPE_LPDDR2) - usleep(params->emc_pin_extra_wait + 200); - // Init zq calibration, - if (params->memory_type == MEMORY_TYPE_LPDDR4) + // Patch 6 using BCT spare variables. + if (params->emc_bct_spare10) + *(vu32 *)params->emc_bct_spare10 = params->emc_bct_spare11; + + // Write mode registers. + EMC(EMC_MRW2) = params->emc_mrw2; + EMC(EMC_MRW) = params->emc_mrw1; + EMC(EMC_MRW3) = params->emc_mrw3; + EMC(EMC_MRW4) = params->emc_mrw4; + EMC(EMC_MRW6) = params->emc_mrw6; + EMC(EMC_MRW14) = params->emc_mrw14; + + EMC(EMC_MRW8) = params->emc_mrw8; + EMC(EMC_MRW12) = params->emc_mrw12; + EMC(EMC_MRW9) = params->emc_mrw9; + EMC(EMC_MRW13) = params->emc_mrw13; + + if (params->emc_zcal_warm_cold_boot_enables & 1) { - // Patch 6 using BCT spare variables. - if (params->emc_bct_spare10) - *(vu32 *)params->emc_bct_spare10 = params->emc_bct_spare11; + // Issue ZQCAL start, device 0. + EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev0; + usleep(params->emc_zcal_init_wait); - // Write mode registers. - EMC(EMC_MRW2) = params->emc_mrw2; - EMC(EMC_MRW) = params->emc_mrw1; - EMC(EMC_MRW3) = params->emc_mrw3; - EMC(EMC_MRW4) = params->emc_mrw4; - EMC(EMC_MRW6) = params->emc_mrw6; - EMC(EMC_MRW14) = params->emc_mrw14; - - EMC(EMC_MRW8) = params->emc_mrw8; - EMC(EMC_MRW12) = params->emc_mrw12; - EMC(EMC_MRW9) = params->emc_mrw9; - EMC(EMC_MRW13) = params->emc_mrw13; - - if (params->emc_zcal_warm_cold_boot_enables & 1) + // Issue ZQCAL latch. + EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev0 ^ 3; + // Same for device 1. + if (!(params->emc_dev_select & 2)) { - // Issue ZQCAL start, device 0. - EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev0; + EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev1; usleep(params->emc_zcal_init_wait); - - // Issue ZQCAL latch. - EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev0 ^ 3; - // Same for device 1. - if (!(params->emc_dev_select & 2)) - { - EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev1; - usleep(params->emc_zcal_init_wait); - EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev1 ^ 3; - } + EMC(EMC_ZQ_CAL) = params->emc_zcal_init_dev1 ^ 3; } } @@ -1321,35 +1427,34 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) PMC(APBDEV_PMC_DDR_CFG) = params->pmc_ddr_cfg; // Start periodic ZQ calibration (LPDDRx only). - if (params->memory_type == MEMORY_TYPE_LPDDR2 || params->memory_type == MEMORY_TYPE_DDR3L || params->memory_type == MEMORY_TYPE_LPDDR4) - { - EMC(EMC_ZCAL_INTERVAL) = params->emc_zcal_interval; - EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt; - EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; - } + EMC(EMC_ZCAL_INTERVAL) = params->emc_zcal_interval; + EMC(EMC_ZCAL_WAIT_CNT) = params->emc_zcal_wait_cnt; + EMC(EMC_ZCAL_MRW_CMD) = params->emc_zcal_mrw_cmd; // Patch 7 using BCT spare variables. if (params->emc_bct_spare12) *(vu32 *)params->emc_bct_spare12 = params->emc_bct_spare13; - EMC(EMC_TIMING_CONTROL) = 1; // Trigger timing update so above writes take place. + // Trigger timing update so above writes take place. + EMC(EMC_TIMING_CONTROL) = 1; if (params->emc_extra_refresh_num) EMC(EMC_REF) = ((1 << params->emc_extra_refresh_num << 8) - 253) | (params->emc_dev_select << 30); // Enable refresh. - EMC(EMC_REFCTRL) = params->emc_dev_select | 0x80000000; + EMC(EMC_REFCTRL) = params->emc_dev_select | BIT(31); EMC(EMC_DYN_SELF_REF_CONTROL) = params->emc_dyn_self_ref_control; - EMC(EMC_CFG) = params->emc_cfg; - EMC(EMC_FDPD_CTRL_DQ) = params->emc_fdpd_ctrl_dq; + EMC(EMC_CFG) = params->emc_cfg; + EMC(EMC_FDPD_CTRL_DQ) = params->emc_fdpd_ctrl_dq; EMC(EMC_FDPD_CTRL_CMD) = params->emc_fdpd_ctrl_cmd; - EMC(EMC_SEL_DPD_CTRL) = params->emc_sel_dpd_ctrl; + EMC(EMC_SEL_DPD_CTRL) = params->emc_sel_dpd_ctrl; // Write addr swizzle lock bit. - EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare | 2; + EMC(EMC_FBIO_SPARE) = params->emc_fbio_spare | BIT(1); - EMC(EMC_TIMING_CONTROL) = 1; // Re-trigger timing to latch power saving functions. + // Re-trigger timing to latch power saving functions. + EMC(EMC_TIMING_CONTROL) = 1; EMC(EMC_CFG_UPDATE) = params->emc_cfg_update; @@ -1364,8 +1469,8 @@ static void _sdram_config_t210b01(const sdram_params_t210b01_t *params) // Lock carveouts per BCT cfg. MC(MC_VIDEO_PROTECT_REG_CTRL) = params->mc_video_protect_write_access; - MC(MC_SEC_CARVEOUT_REG_CTRL) = params->mc_sec_carveout_protect_write_access; - MC(MC_MTS_CARVEOUT_REG_CTRL) = params->mc_mts_carveout_reg_ctrl; + MC(MC_SEC_CARVEOUT_REG_CTRL) = params->mc_sec_carveout_protect_write_access; + MC(MC_MTS_CARVEOUT_REG_CTRL) = params->mc_mts_carveout_reg_ctrl; // Disable write access to a bunch of EMC registers. MC(MC_EMEM_CFG_ACCESS_CTRL) = 1; @@ -1406,7 +1511,7 @@ void *sdram_get_params_t210b01() return (void *)params; for (u32 i = 0; i < ARRAY_SIZE(sdram_cfg_vendor_patches_t210b01); i++) - if (sdram_cfg_vendor_patches_t210b01[i].dramcf == dram_code) + if (sdram_cfg_vendor_patches_t210b01[i].dramcf & DRAM_CC(dram_code)) params[sdram_cfg_vendor_patches_t210b01[i].offset] = sdram_cfg_vendor_patches_t210b01[i].val; return (void *)params; @@ -1450,61 +1555,28 @@ void *sdram_get_params_patched() return (void *)sdram_params; } -static void _sdram_init_t210() -{ - const sdram_params_t210_t *params = (const sdram_params_t210_t *)_sdram_get_params_t210(); - - // Set DRAM voltage. - max7762x_regulator_set_voltage(REGULATOR_SD1, 1100000); // HOS uses 1.125V - - // VDDP Select. - PMC(APBDEV_PMC_VDDP_SEL) = params->pmc_vddp_sel; - usleep(params->pmc_vddp_sel_wait); - - // Set DDR pad voltage. - PMC(APBDEV_PMC_DDR_PWR) = PMC(APBDEV_PMC_DDR_PWR); - - // Turn on MEM IO Power. - PMC(APBDEV_PMC_NO_IOPOWER) = params->pmc_no_io_power; - PMC(APBDEV_PMC_REG_SHORT) = params->pmc_reg_short; - - PMC(APBDEV_PMC_DDR_CNTRL) = params->pmc_ddr_ctrl; - - // Patch 1 using BCT spare variables - if (params->emc_bct_spare0) - *(vu32 *)params->emc_bct_spare0 = params->emc_bct_spare1; - - _sdram_config_t210(params); -} - -static void _sdram_init_t210b01() -{ - const sdram_params_t210b01_t *params = (const sdram_params_t210b01_t *)sdram_get_params_t210b01(); - - // VDDP Select. - PMC(APBDEV_PMC_VDDP_SEL) = params->pmc_vddp_sel; - usleep(params->pmc_vddp_sel_wait); - - // Turn on MEM IO Power. - PMC(APBDEV_PMC_NO_IOPOWER) = params->pmc_no_io_power; - PMC(APBDEV_PMC_REG_SHORT) = params->pmc_reg_short; - - PMC(APBDEV_PMC_DDR_CNTRL) = params->pmc_ddr_ctrl; - - // Patch 1 using BCT spare variables - if (params->emc_bct_spare0) - *(vu32 *)params->emc_bct_spare0 = params->emc_bct_spare1; - - _sdram_config_t210b01(params); -} - void sdram_init() { // Disable remote sense for SD1. i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD_CFG2, MAX77620_SD_CNF2_ROVS_EN_SD0 | MAX77620_SD_CNF2_RSVD); if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210) - _sdram_init_t210(); + { + const sdram_params_t210_t *params = (const sdram_params_t210_t *)_sdram_get_params_t210(); + if (params->memory_type != MEMORY_TYPE_LPDDR4) + return; + + // Set DRAM voltage. + max7762x_regulator_set_voltage(REGULATOR_SD1, 1125000); // HOS: 1.125V. Bootloader: 1.1V. + + _sdram_config_t210(params); + } else - _sdram_init_t210b01(); + { + const sdram_params_t210b01_t *params = (const sdram_params_t210b01_t *)sdram_get_params_t210b01(); + if (params->memory_type != MEMORY_TYPE_LPDDR4) + return; + + _sdram_config_t210b01(params); + } } diff --git a/bdk/mem/sdram.h b/bdk/mem/sdram.h index 3caac47..10fb705 100644 --- a/bdk/mem/sdram.h +++ b/bdk/mem/sdram.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2020-2021 CTCaer + * Copyright (c) 2020-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -23,107 +23,119 @@ /* * Tegra X1/X1+ EMC/DRAM Bandwidth Chart: * - * Note: BWbits T210 = Hz x ddr x bus width x channels = Hz x 2 x 32 x 2. - * BWbits T210B01 = Hz x ddr x bus width x channels = Hz x 2 x 64 x 2. - * Both assume that both sub-partitions are used and thus reaching max - * bandwidth per channel. (T210: 2x16-bit, T210B01: 2x32-bit). - * Retail Mariko use one sub-partition, in order to meet Erista perf. - * - * T210 T210B01 - * 40.8 MHz: 0.61 1.22 GiB/s - * 68.0 MHz: 1.01 2.02 GiB/s - * 102.0 MHz: 1.52 3.04 GiB/s - * 204.0 MHz: 3.04 6.08 GiB/s <-- Tegra X1/X1+ Init/SC7 Frequency - * 408.0 MHz: 6.08 12.16 GiB/s - * 665.6 MHz: 9.92 19.84 GiB/s - * 800.0 MHz: 11.92 23.84 GiB/s <-- Tegra X1/X1+ Nvidia OS Boot Frequency - * 1065.6 MHz: 15.89 31.78 GiB/s - * 1331.2 MHz: 19.84 39.68 GiB/s - * 1600.0 MHz: 23.84 47.68 GiB/s <-- Tegra X1/X1+ HOS Max Frequency - * 1862.4 MHz: 27.75 55.50 GiB/s <-- Tegra X1 Official Max Frequency - * 2131.2 MHz: 31.76 63.52 GiB/s <-- Tegra X1+ Official Max Frequency + * Note: Max BWbits = Hz x ddr x bus width x channels = Hz x 2 x 32 x 2. + * Max BWbits = Hz x ddr x bus width x channels = Hz x 2 x 64 x 1. + * Configurations supported: 1x32, 2x32, 1x64. + * x64 ram modules can be used by combining the 2 32-bit channels into one. * + * 204.0 MHz: 3.04 <-- Tegra X1/X1+ Init/SC7 Frequency + * 408.0 MHz: 6.08 + * 665.6 MHz: 9.92 + * 800.0 MHz: 11.92 <-- Tegra X1/X1+ Nvidia OS Boot Frequency + * 1065.6 MHz: 15.89 + * 1331.2 MHz: 19.84 + * 1600.0 MHz: 23.84 + * 1862.4 MHz: 27.75 <-- Tegra X1 Official Max Frequency + * 2131.2 MHz: 31.76 <-- Tegra X1+ Official Max Frequency. Not all regs have support for > 2046 MHz. */ enum sdram_ids_erista { // LPDDR4 3200Mbps. - LPDDR4_ICOSA_4GB_SAMSUNG_K4F6E304HB_MGCH = 0, - LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE = 1, - LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WT = 2, - LPDDR4_COPPER_4GB_SAMSUNG_K4F6E304HB_MGCH = 3, // Changed to Iowa Hynix 4GB 1Y-A. - LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH = 4, - LPDDR4_COPPER_4GB_HYNIX_H9HCNNNBPUMLHR_NLE = 5, // Changed to Hoag Hynix 4GB 1Y-A. - LPDDR4_COPPER_4GB_MICRON_MT53B512M32D2NP_062_WT = 6, // Changed to Aula Hynix 4GB 1Y-A. + LPDDR4_ICOSA_4GB_SAMSUNG_K4F6E304HB_MGCH = 0, // Die-B. (2y-01). + LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE = 1, // Die-M. (2y-01). + LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WTC = 2, // Die-C. (2y-01). + + LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH = 4, // Die-C. (2y-01). + + /* + * Custom hekate/L4T supported 8GB. 7 dram id can be easily applied in fuses. + * + * 4GB modules: + * Samsung K4FBE3D4HM-MGCH/CJ/CL. MG/TF/GF/TH/GH: Package + Temperature. + * Hynix H9HCNNNCPUMLXR-NME/NEE/NEI. E/I: Temperature. + * Hynix H54G56BYYVX046/QX046/PX046. V/Q/P: Package + Temperature. + */ + LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX = 7, // XX: CH/CJ/CL. }; enum sdram_ids_mariko { + /* + * Nintendo Switch LPDRR4X generations: + * - 1x nm are 1st-gen + * - 1y nm are 2nd-gen + * - 1z/a nm are 3rd-gen + */ + // LPDDR4X 4266Mbps. - LPDDR4X_IOWA_4GB_HYNIX_1Y_A = 3, // Replaced from Copper. - LPDDR4X_HOAG_4GB_HYNIX_1Y_A = 5, // Replaced from Copper. - LPDDR4X_AULA_4GB_HYNIX_1Y_A = 6, // Replaced from Copper. + LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLXR_NEE = 3, // Die-M. (1y-01). + LPDDR4X_AULA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE = 5, // Die-M. (1y-01). + LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE = 6, // Die-M. (1y-01). // LPDDR4X 3733Mbps. - LPDDR4X_IOWA_4GB_SAMSUNG_X1X2 = 7, + LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AM_MGCJ = 8, // Die-M. (1x-03). + LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AM_MGCJ = 9, // Die-M. (1x-03). + LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLHR_NME = 10, // Die-M. (1x-03). + LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTE = 11, // Die-E. (1x-03). D9WGB. 4266Mbps. - LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AM_MGCJ = 8, // Die-M. - LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AM_MGCJ = 9, // Die-M. - LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLHR_NME = 10, // Die-M. - LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WT = 11, // 4266Mbps. WT:E. Die-E. - - LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AM_MGCJ = 12, // Die-M. - LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AM_MGCJ = 13, // Die-M. - LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLHR_NME = 14, // Die-M. - LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WT = 15, // 4266Mbps. WT:E. Die-E. + LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AM_MGCJ = 12, // Die-M. (1x-03). + LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AM_MGCJ = 13, // Die-M. (1x-03). + LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLHR_NME = 14, // Die-M. (1x-03). + LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTE = 15, // Die-E. (1x-03). D9WGB. 4266Mbps. // LPDDR4X 4266Mbps. - LPDDR4X_IOWA_4GB_SAMSUNG_Y = 16, + LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 17, // Die-A. (1y-X03). + LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 18, // Die-A. (1y-X03). + LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 19, // Die-A. (1y-X03). - LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 17, // Die-A. - LPDDR4X_IOWA_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 18, // Die-A. - LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 19, // Die-A. + LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AB_MGCL = 20, // Die-B. (1z-01). 40% lp. + LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AB_MGCL = 21, // Die-B. (1z-01). 40% lp. + LPDDR4X_AULA_4GB_SAMSUNG_K4U6E3S4AB_MGCL = 22, // Die-B. (1z-01). 40% lp. - LPDDR4X_IOWA_4GB_SAMSUNG_1Y_Y = 20, - LPDDR4X_IOWA_8GB_SAMSUNG_1Y_Y = 21, + LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 23, // Die-A. (1y-X03). + LPDDR4X_AULA_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 24, // Die-A. (1y-X03). - // LPDDR4X_AULA_8GB_SAMSUNG_1Y_A = 22, // Unused. + LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 25, // Die-F. (1y-01). D9XRR. + LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTF = 26, // Die-F. (1y-01). D9XRR. + LPDDR4X_AULA_4GB_MICRON_MT53E512M32D2NP_046_WTF = 27, // Die-F. (1y-01). D9XRR. - LPDDR4X_HOAG_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 23, // Die-A. - LPDDR4X_AULA_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 24, // Die-A. + LPDDR4X_AULA_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 28, // Die-A. (1y-X03). 2nd gen. - LPDDR4X_IOWA_4GB_MICRON_1Y_A = 25, - LPDDR4X_HOAG_4GB_MICRON_1Y_A = 26, - LPDDR4X_AULA_4GB_MICRON_1Y_A = 27, + // Old naming scheme: H9HCNNNBKMCLXR-NEE + LPDDR4X_IOWA_4GB_HYNIX_H54G46CYRBX267 = 29, // Die-C. (1a-01). 61% lp. + LPDDR4X_HOAG_4GB_HYNIX_H54G46CYRBX267 = 30, // Die-C. (1a-01). 61% lp. + LPDDR4X_AULA_4GB_HYNIX_H54G46CYRBX267 = 31, // Die-C. (1a-01). 61% lp. - LPDDR4X_AULA_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 28, // Die-A. + LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D1NP_046_WTB = 32, // Die-B. (1a-01). D8BQM. 61% lp. + LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D1NP_046_WTB = 33, // Die-B. (1a-01). D8BQM. 61% lp. + LPDDR4X_AULA_4GB_MICRON_MT53E512M32D1NP_046_WTB = 34, // Die-B. (1a-01). D8BQM. 61% lp. }; enum sdram_codes_mariko { - LPDDR4X_NO_PATCH = 0, - LPDDR4X_UNUSED = 0, + LPDDR4X_NO_PATCH = 0, + LPDDR4X_UNUSED = 0, // LPDDR4X_4GB_SAMSUNG_K4U6E3S4AM_MGCJ DRAM IDs: 08, 12. // LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLHR_NME DRAM IDs: 10, 14. - LPDDR4X_4GB_SAMSUNG_X1X2 = 1, // DRAM IDs: 07. - LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ = 2, // DRAM IDs: 09, 13. - LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046 = 3, // DRAM IDs: 11, 15. - LPDDR4X_4GB_SAMSUNG_Y = 4, // DRAM IDs: 16. - LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 5, // DRAM IDs: 17, 19, 24. - LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 6, // DRAM IDs: 18, 23, 28. - LPDDR4X_4GB_SAMSUNG_1Y_Y = 7, // DRAM IDs: 20. - LPDDR4X_8GB_SAMSUNG_1Y_Y = 8, // DRAM IDs: 21. - //LPDDR4X_8GB_SAMSUNG_1Y_A = 9, // DRAM IDs: 22. Unused. - LPDDR4X_4GB_MICRON_1Y_A = 10, // DRAM IDs: 25, 26, 27. - LPDDR4X_4GB_HYNIX_1Y_A = 11, // DRAM IDs: 03, 05, 06. + LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ = 1, // DRAM IDs: 09, 13. + LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE = 2, // DRAM IDs: 11, 15. + LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL = 3, // DRAM IDs: 17, 19, 24. + LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL = 4, // DRAM IDs: 18, 23, 28. + LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL = 5, // DRAM IDs: 20, 21, 22. + LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF = 6, // DRAM IDs: 25, 26, 27. + LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE = 7, // DRAM IDs: 03, 05, 06. + LPDDR4X_4GB_HYNIX_H54G46CYRBX267 = 8, // DRAM IDs: 29, 30, 31. + LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB = 9, // DRAM IDs: 32, 33, 34. }; void sdram_init(); void *sdram_get_params_patched(); void *sdram_get_params_t210b01(); void sdram_lp0_save_params(const void *params); +void sdram_src_pllc(bool enable); emc_mr_data_t sdram_read_mrx(emc_mr_t mrx); #endif diff --git a/bdk/mem/sdram_config.inl b/bdk/mem/sdram_config.inl index 4548981..e6d6f0b 100644 --- a/bdk/mem/sdram_config.inl +++ b/bdk/mem/sdram_config.inl @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2020-2021 CTCaer + * Copyright (c) 2020-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,8 +17,6 @@ #define DRAM_CFG_T210_SIZE 1896 -#define DRAM_ID(x) BIT(x) - static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = { /* Specifies the type of memory device */ .memory_type = MEMORY_TYPE_LPDDR4, @@ -436,9 +434,9 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = { .emc_dll_cfg0 = 0x1F13412F, .emc_dll_cfg1 = 0x00010014, - .emc_pmc_scratch1 = 0x4FAFFFFF, + .emc_pmc_scratch1 = 0x4FAFFFFF, // APBDEV_PMC_IO_DPD3_REQ. .emc_pmc_scratch2 = 0x7FFFFFFF, - .emc_pmc_scratch3 = 0x4006D70B, + .emc_pmc_scratch3 = 0x4006D70B, // APBDEV_PMC_DDR_CNTRL. .emc_pmacro_pad_cfg_ctrl = 0x00020000, .emc_pmacro_vttgen_ctrl0 = 0x00030808, @@ -491,8 +489,8 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = { /* DRAM size information */ .mc_emem_adr_cfg = 0x00000001, // 2 Ranks. - .mc_emem_adr_cfg_dev0 = 0x00070302, // Rank 0 Density 512MB. - .mc_emem_adr_cfg_dev1 = 0x00070302, // Rank 1 Density 512MB. + .mc_emem_adr_cfg_dev0 = 0x00070302, // Chip 0 Density 512MB. + .mc_emem_adr_cfg_dev1 = 0x00070302, // Chip 1 Density 512MB. .mc_emem_adr_cfg_channel_mask = 0xFFFF2400, .mc_emem_adr_cfg_bank_mask0 = 0x6E574400, .mc_emem_adr_cfg_bank_mask1 = 0x39722800, @@ -501,7 +499,7 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = { * Specifies the value for MC_EMEM_CFG which holds the external memory * size (in KBytes) */ - .mc_emem_cfg = 0x00001000, // 4GB total density. + .mc_emem_cfg = 0x00001000, // 4GB total density. Max 8GB. /* MC arbitration configuration */ .mc_emem_arb_cfg = 0x08000001, @@ -543,13 +541,19 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = { .mc_video_protect_bom = 0xFFF00000, .mc_video_protect_bom_adr_hi = 0x00000000, .mc_video_protect_size_mb = 0x00000000, - .mc_video_protect_vpr_override = 0xE4BAC343, - .mc_video_protect_vpr_override1 = 0x00001ED3, - .mc_video_protect_gpu_override0 = 0x00000000, - .mc_video_protect_gpu_override1 = 0x00000000, + + // AFI, BPMP, HC, ISP2, CCPLEX, PPCS (AHB), SATA, VI, XUSB_HOST, XUSB_DEV, ADSP, PPCS1 (AHB), DC1, SDMMC1A, SDMMC2A, SDMMC3A. Plus TSEC, NVENC. + .mc_video_protect_vpr_override = 0xE4FACB43, // Default: 0xE4BAC343. New: 0xE4FACB43. + TSEC, NVENC. + // SDMMC4A, ISP2B, PPCS2 (AHB), APE, SE, HC1, SE1, AXIAP, ETR. Plus TSECB, TSEC1, TSECB1. + .mc_video_protect_vpr_override1 = 0x0000FED3, // Default: 0x00001ED3. New: 0x0000FED3. + TSECB, TSEC1, TSECB1. + + .mc_video_protect_gpu_override0 = 0x2A800000, // Default: 0x00000000. Forced to 1 by HOS Secmon. + .mc_video_protect_gpu_override1 = 0x00000002, // Default: 0x00000000. Forced to 0 by HOS Secmon. + .mc_sec_carveout_bom = 0xFFF00000, .mc_sec_carveout_adr_hi = 0x00000000, .mc_sec_carveout_size_mb = 0x00000000, + .mc_video_protect_write_access = 0x00000000, .mc_sec_carveout_protect_write_access = 0x00000000, @@ -644,53 +648,27 @@ static const sdram_params_t210_t _dram_cfg_0_samsung_4gb = { .mc_mts_carveout_reg_ctrl = 0x00000000 }; +#define DCFG_OFFSET_OF(m) (OFFSET_OF(sdram_params_t210_t, m) / 4) static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210[] = { // Hynix timing config. - { 0x0000000D, 0x10C / 4, DRAM_ID(1) }, // emc_r2w. - { 0x00000001, 0x16C / 4, DRAM_ID(1) }, // emc_puterm_extra. - { 0x80000000, 0x170 / 4, DRAM_ID(1) }, // emc_puterm_width. - { 0x00000210, 0x4F4 / 4, DRAM_ID(1) }, // emc_pmacro_data_rx_term_mode. - { 0x00000005, 0x5C0 / 4, DRAM_ID(1) }, // mc_emem_arb_timing_r2w. + { 0x0000000D, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(emc_r2w) }, + { 0x00000001, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(emc_puterm_extra) }, + { 0x80000000, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(emc_puterm_width) }, + { 0x00000210, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(emc_pmacro_data_rx_term_mode) }, + { 0x00000005, DRAM_ID(LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE), DCFG_OFFSET_OF(mc_emem_arb_timing_r2w) }, // Samsung 6GB density config. - { 0x000C0302, 0x56C / 4, DRAM_ID(4) }, // mc_emem_adr_cfg_dev0. 768MB Rank 0 density. - { 0x000C0302, 0x570 / 4, DRAM_ID(4) }, // mc_emem_adr_cfg_dev1. 768MB Rank 1 density. - { 0x00001800, 0x584 / 4, DRAM_ID(4) }, // mc_emem_cfg. 6GB total density. + { 0x000C0302, DRAM_ID(LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH), DCFG_OFFSET_OF(mc_emem_adr_cfg_dev0) }, // 768MB Chip 0 density. + { 0x000C0302, DRAM_ID(LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH), DCFG_OFFSET_OF(mc_emem_adr_cfg_dev1) }, // 768MB Chip 1 density. + { 0x00001800, DRAM_ID(LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH), DCFG_OFFSET_OF(mc_emem_cfg) }, // 6GB total density. Max 8GB. -#ifdef CONFIG_SDRAM_COPPER_SUPPORT - // Copper prototype Samsung/Hynix/Micron timing configs. - { 0x0000003A, 0xEC / 4, DRAM_ID(6) }, // emc_rfc. Auto refresh. - { 0x0000001D, 0xF0 / 4, DRAM_ID(6) }, // emc_rfc_pb. Bank Auto refresh. - { 0x0000000D, 0x10C / 4, DRAM_ID(5) }, // emc_r2w. - { 0x00000001, 0x16C / 4, DRAM_ID(5) }, // emc_puterm_extra. - { 0x80000000, 0x170 / 4, DRAM_ID(5) }, // emc_puterm_width. - { 0x00000012, 0x1B0 / 4, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_rw2pden. - { 0x0000003B, 0x1C0 / 4, DRAM_ID(6) }, // emc_txsr. - { 0x0000003B, 0x1C4 / 4, DRAM_ID(6) }, // emc_txsr_dll. - { 0x00000003, 0x1DC / 4, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_tclkstable. - { 0x00120015, 0x334 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank0_4. - { 0x00160012, 0x338 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank0_5. - { 0x00120015, 0x34C / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank1_4. - { 0x00160012, 0x350 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dq_rank1_5. - { 0x002F0032, 0x354 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_0. - { 0x00310032, 0x358 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_1. - { 0x00360034, 0x35C / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_2. - { 0x0033002F, 0x360 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_3. - { 0x00000006, 0x364 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank0_4. - { 0x002F0032, 0x36C / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_0. - { 0x00310032, 0x370 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_1. - { 0x00360034, 0x374 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_2. - { 0x0033002F, 0x378 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_3. - { 0x00000006, 0x37C / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ob_ddll_long_dqs_rank1_4. - { 0x00150015, 0x3A4 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_0. - { 0x00120012, 0x3AC / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_2. - { 0x00160016, 0x3B0 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_3. - { 0x00000015, 0x3B4 / 4, DRAM_ID(5) | DRAM_ID(6) }, // emc_pmacro_ddll_long_cmd_4. - { 0x00000012, 0x49C / 4, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_cmd_brlshft2. - { 0x00000012, 0x4A0 / 4, DRAM_ID(3) | DRAM_ID(5) | DRAM_ID(6) }, // emc_cmd_brlshft3. - { 0x00000210, 0x4F4 / 4, DRAM_ID(5) }, // emc_pmacro_data_rx_term_mode. - { 0x00000005, 0x5C0 / 4, DRAM_ID(5) }, // mc_emem_arb_timing_r2w. - { 0x00000007, 0x5C8 / 4, DRAM_ID(6) }, // mc_emem_arb_timing_rfcpb. Bank refresh. - { 0x72A30504, 0x5D4 / 4, DRAM_ID(6) }, // mc_emem_arb_misc0. -#endif + // Samsung 8GB density config. + { 0x0000003A, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX), DCFG_OFFSET_OF(emc_rfc) }, + { 0x0000001D, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX), DCFG_OFFSET_OF(emc_rfc_pb) }, + { 0x0000003B, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX), DCFG_OFFSET_OF(emc_txsr) }, + { 0x0000003B, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX), DCFG_OFFSET_OF(emc_txsr_dll) }, + { 0x00080302, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX), DCFG_OFFSET_OF(mc_emem_adr_cfg_dev0) }, // 1024MB Chip 0 density. + { 0x00080302, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX), DCFG_OFFSET_OF(mc_emem_adr_cfg_dev1) }, // 1024MB Chip 1 density. + { 0x00002000, DRAM_ID(LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX), DCFG_OFFSET_OF(mc_emem_cfg) }, // 8GB total density. Max 8GB. }; +#undef DCFG_OFFSET_OF diff --git a/bdk/mem/sdram_config_t210b01.inl b/bdk/mem/sdram_config_t210b01.inl index 0d1d617..3879e0c 100644 --- a/bdk/mem/sdram_config_t210b01.inl +++ b/bdk/mem/sdram_config_t210b01.inl @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021 CTCaer + * Copyright (c) 2020-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -542,8 +542,8 @@ static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = { /* DRAM size information */ .mc_emem_adr_cfg = 0x00000000, // 1 Rank. - .mc_emem_adr_cfg_dev0 = 0x00080302, // Rank 0 Density 1024MB. - .mc_emem_adr_cfg_dev1 = 0x00080302, // Rank 1 Density 1024MB. + .mc_emem_adr_cfg_dev0 = 0x00080302, // Chip 0 Density 1024MB. + .mc_emem_adr_cfg_dev1 = 0x00080302, // Chip 1 Density 1024MB. .mc_emem_adr_cfg_channel_mask = 0xFFFF2400, .mc_emem_adr_cfg_bank_mask0 = 0x6E574400, .mc_emem_adr_cfg_bank_mask1 = 0x39722800, @@ -552,7 +552,7 @@ static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = { * Specifies the value for MC_EMEM_CFG which holds the external memory * size (in KBytes) */ - .mc_emem_cfg = 0x00001000, // 4GB total density. + .mc_emem_cfg = 0x00001000, // 4GB total density. Max 8GB. /* MC arbitration configuration */ .mc_emem_arb_cfg = 0x08000001, @@ -594,13 +594,19 @@ static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = { .mc_video_protect_bom = 0xFFF00000, .mc_video_protect_bom_adr_hi = 0x00000000, .mc_video_protect_size_mb = 0x00000000, - .mc_video_protect_vpr_override = 0xE4BAC343, - .mc_video_protect_vpr_override1 = 0x06001ED3, // Add SE2, SE2B. - .mc_video_protect_gpu_override0 = 0x00000000, - .mc_video_protect_gpu_override1 = 0x00000000, + + // AFI, BPMP, HC, ISP2, CCPLEX, PPCS (AHB), SATA, VI, XUSB_HOST, XUSB_DEV, ADSP, PPCS1 (AHB), DC1, SDMMC1A, SDMMC2A, SDMMC3A. Plus TSEC, NVENC. + .mc_video_protect_vpr_override = 0xE4FACB43, // Default: 0xE4BAC343. + // SDMMC4A, ISP2B, PPCS2 (AHB), APE, SE, HC1, SE1, AXIAP, ETR. Plus SE2, SE2B and TSECB, TSEC1, TSECB1. + .mc_video_protect_vpr_override1 = 0x0600FED3, // Default: 0x06001ED3. + + .mc_video_protect_gpu_override0 = 0x2A800000, // Default: 0x00000000. Forced to 1 by HOS Secmon. + .mc_video_protect_gpu_override1 = 0x00000002, // Default: 0x00000000. Forced to 0 by HOS Secmon. + .mc_sec_carveout_bom = 0xFFF00000, .mc_sec_carveout_adr_hi = 0x00000000, .mc_sec_carveout_size_mb = 0x00000000, + .mc_video_protect_write_access = 0x00000000, .mc_sec_carveout_protect_write_access = 0x00000000, @@ -701,291 +707,106 @@ static const sdram_params_t210b01_t _dram_cfg_08_10_12_14_samsung_hynix_4gb = { .bct_na = 0x00000000, }; -//!TODO Find out what mc_video_protect_gpu_override0 and mc_video_protect_gpu_override1 new bits are. +#define DRAM_CC_LPDDR4X_PMACRO_IB (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ)) +#define DRAM_CC_LPDDR4X_PUPD_VPR (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ) | \ + DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE) | \ + DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL) | \ + DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL) | \ + DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \ + DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE) | \ + DRAM_CC(LPDDR4X_4GB_HYNIX_H54G46CYRBX267) | \ + DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB) | \ + DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL)) + +#define DRAM_CC_LPDDR4X_DSR (DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTE) | \ + DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL) | \ + DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \ + DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE) | \ + DRAM_CC(LPDDR4X_4GB_HYNIX_H54G46CYRBX267) | \ + DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB) | \ + DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL)) + +#define DRAM_CC_LPDDR4X_QUSE (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ) | \ + DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL) | \ + DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL) | \ + DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \ + DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE) | \ + DRAM_CC(LPDDR4X_4GB_HYNIX_H54G46CYRBX267) | \ + DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB) | \ + DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL)) + +#define DRAM_CC_LPDDR4X_FAW (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL) | \ + DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046_WTF) | \ + DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE) | \ + DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB)) + +#define DRAM_CC_LPDDR4X_VPR (DRAM_CC(LPDDR4X_4GB_HYNIX_H9HCNNNBKMMLXR_NEE) | \ + DRAM_CC(LPDDR4X_4GB_HYNIX_H54G46CYRBX267) | \ + DRAM_CC(LPDDR4X_4GB_MICRON_MT53E512M32D1NP_046_WTB) | \ + DRAM_CC(LPDDR4X_4GB_SAMSUNG_K4U6E3S4AB_MGCL)) + +#define DRAM_CC_LPDDR4X_8GB (DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ) | \ + DRAM_CC(LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL)) + +#define DCFG_OFFSET_OF(m) (OFFSET_OF(sdram_params_t210b01_t, m) / 4) static const sdram_vendor_patch_t sdram_cfg_vendor_patches_t210b01[] = { - // Samsung LPDDR4X 4GB X1X2 for prototype Iowa. - { 0x000E0022, 0x3AC / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dq_rank0_4. - { 0x001B0010, 0x3B0 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dq_rank0_5. - { 0x000E0022, 0x3C4 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dq_rank1_4. - { 0x001B0010, 0x3C8 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dq_rank1_5. - { 0x00490043, 0x3CC / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank0_0. - { 0x00420045, 0x3D0 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank0_1. - { 0x00490047, 0x3D4 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank0_2. - { 0x00460047, 0x3D8 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank0_3. - { 0x00000016, 0x3DC / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank0_4. - { 0x00100000, 0x3E0 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank0_5. - { 0x00490043, 0x3E4 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank1_0. - { 0x00420045, 0x3E8 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank1_1. - { 0x00490047, 0x3EC / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank1_2. - { 0x00460047, 0x3F0 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank1_3. - { 0x00000016, 0x3F4 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank1_4. - { 0x00100000, 0x3F8 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ob_ddll_long_dqs_rank1_5. - { 0x00220022, 0x41C / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ddll_long_cmd_0. - { 0x000E000E, 0x420 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ddll_long_cmd_1. - { 0x00100010, 0x424 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ddll_long_cmd_2. - { 0x001B001B, 0x428 / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ddll_long_cmd_3. - { 0x00000022, 0x42C / 4, LPDDR4X_4GB_SAMSUNG_X1X2 }, // emc_pmacro_ddll_long_cmd_4. - // Samsung LPDDR4X 8GB K4UBE3D4AM-MGCJ Die-M for SDEV Iowa and Hoag. - { 0x05500000, 0x0D4 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_auto_cal_config2. - { 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_auto_cal_vref_sel0. - { 0x00000001, 0x134 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_adr_cfg. 2 Ranks. - { 0x00000006, 0x1CC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_quse. - { 0x00000005, 0x1D0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_quse_width. - { 0x00000003, 0x1DC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_einput. - { 0x0000000C, 0x1E0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_einput_duration. - { 0x08010004, 0x2B8 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw1. - { 0x08020000, 0x2BC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw2. - { 0x080D0000, 0x2C0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw3. - { 0x08033131, 0x2C8 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw6. - { 0x080B0000, 0x2CC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw8. - { 0x0C0E5D5D, 0x2D0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw9. - { 0x080C5D5D, 0x2D4 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw10. - { 0x0C0D0808, 0x2D8 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw12. - { 0x0C0D0000, 0x2DC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw13. - { 0x08161414, 0x2E0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw14. - { 0x08010004, 0x2E4 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_mrw_extra. - { 0x00000000, 0x340 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_dev_select. Both devices. - { 0x35353535, 0x350 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_vref_dq_0. - { 0x35353535, 0x354 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_vref_dq_1. - { 0x00100010, 0x3FC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_ddll_long_dqs_rank0_0. - { 0x00100010, 0x400 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_ddll_long_dqs_rank0_1. - { 0x00100010, 0x404 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_ddll_long_dqs_rank0_2. - { 0x00100010, 0x408 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_ddll_long_dqs_rank0_3. - { 0x00100010, 0x40C / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_ddll_long_dqs_rank1_0. - { 0x00100010, 0x410 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_ddll_long_dqs_rank1_1. - { 0x00100010, 0x414 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_ddll_long_dqs_rank1_2. - { 0x00100010, 0x418 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_ib_ddll_long_dqs_rank1_3. - { 0x0051004F, 0x450 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_zcal_mrw_cmd. - { 0x40000001, 0x45C / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_zcal_init_dev1. - { 0x00000000, 0x594 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_tx_pwrd4. - { 0x00001000, 0x598 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // emc_pmacro_tx_pwrd5. - { 0x00000001, 0x630 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // mc_emem_adr_cfg. 2 Ranks. - { 0x00002000, 0x64C / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // mc_emem_cfg. 8GB total density. - { 0x00000002, 0x680 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // mc_emem_arb_timing_r2r. - { 0x02020001, 0x694 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // mc_emem_arb_da_turns. - { 0x2A800000, 0x6DC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // mc_video_protect_gpu_override0. - { 0x00000002, 0x6E0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AM_MGCJ }, // mc_video_protect_gpu_override1. + { 0x35353535, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_vref_dq_0) }, + { 0x35353535, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_vref_dq_1) }, + { 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank0_0) }, + { 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank0_1) }, + { 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank0_2) }, + { 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank0_3) }, + { 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank1_0) }, + { 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank1_1) }, + { 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank1_2) }, + { 0x00100010, DRAM_CC_LPDDR4X_PMACRO_IB, DCFG_OFFSET_OF(emc_pmacro_ib_ddll_long_dqs_rank1_3) }, - // Micron LPDDR4X 4GB MT53D1024M32D1NP-053-WT Die-E for retail Iowa and Hoag. - { 0x05500000, 0x0D4 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046 }, // emc_auto_cal_config2. - { 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046 }, // emc_auto_cal_vref_sel0. - { 0x88161414, 0x2E0 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046 }, // emc_mrw14. - { 0x80000713, 0x32C / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046 }, // emc_dyn_self_ref_control. - { 0x2A800000, 0x6DC / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046 }, // mc_video_protect_gpu_override0. - { 0x00000002, 0x6E0 / 4, LPDDR4X_4GB_MICRON_MT53E512M32D2NP_046 }, // mc_video_protect_gpu_override1. + /*! Shared patched between DRAM Codes. */ + { 0x05500000, DRAM_CC_LPDDR4X_PUPD_VPR, DCFG_OFFSET_OF(emc_auto_cal_config2) }, + { 0xC9AFBCBC, DRAM_CC_LPDDR4X_PUPD_VPR, DCFG_OFFSET_OF(emc_auto_cal_vref_sel0) }, - // Samsung LPDDR4X 4GB (Y01) Die-? for Iowa. - { 0x05500000, 0x0D4 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_auto_cal_config2. - { 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_auto_cal_vref_sel0. - { 0x88161414, 0x2E0 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_mrw14. - { 0x80000713, 0x32C / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_dyn_self_ref_control. - { 0x32323232, 0x350 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_vref_dq_0. - { 0x32323232, 0x354 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_vref_dq_1. - { 0x000F0018, 0x3AC / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dq_rank0_4. - { 0x000F0018, 0x3C4 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dq_rank1_4. - { 0x00440048, 0x3CC / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_0. - { 0x00440045, 0x3D0 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_1. - { 0x00470047, 0x3D4 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_2. - { 0x0005000D, 0x3DC / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_4. - { 0x00440048, 0x3E4 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_0. - { 0x00440045, 0x3E8 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_1. - { 0x00470047, 0x3EC / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_2. - { 0x0005000D, 0x3F4 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_4. - { 0x00780078, 0x3FC / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_ddll_long_dqs_rank0_0. - { 0x00780078, 0x400 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_ddll_long_dqs_rank0_1. - { 0x00780078, 0x404 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_ddll_long_dqs_rank0_2. - { 0x00780078, 0x408 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_ddll_long_dqs_rank0_3. - { 0x00780078, 0x40C / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_ddll_long_dqs_rank1_0. - { 0x00780078, 0x410 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_ddll_long_dqs_rank1_1. - { 0x00780078, 0x414 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_ddll_long_dqs_rank1_2. - { 0x00780078, 0x418 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ib_ddll_long_dqs_rank1_3. - { 0x00180018, 0x41C / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ddll_long_cmd_0. - { 0x000F000F, 0x420 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ddll_long_cmd_1. - { 0x00000018, 0x42C / 4, LPDDR4X_4GB_SAMSUNG_Y }, // emc_pmacro_ddll_long_cmd_4. - { 0x2A800000, 0x6DC / 4, LPDDR4X_4GB_SAMSUNG_Y }, // mc_video_protect_gpu_override0. - { 0x00000002, 0x6E0 / 4, LPDDR4X_4GB_SAMSUNG_Y }, // mc_video_protect_gpu_override1. + // Moved to default config. + // { 0x2A800000, DRAM_CC_LPDDR4X_PUPD_VPR, DCFG_OFFSET_OF(mc_video_protect_gpu_override0) }, + // { 0x00000002, DRAM_CC_LPDDR4X_PUPD_VPR, DCFG_OFFSET_OF(mc_video_protect_gpu_override1) }, - // Samsung LPDDR4X 4GB K4U6E3S4AA-MGCL 10nm-class (1y-X03) Die-A for retail Iowa, Hoag and Aula. - { 0x05500000, 0x0D4 / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // emc_auto_cal_config2. - { 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // emc_auto_cal_vref_sel0. - { 0x00000006, 0x1CC / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // emc_quse. - { 0x00000005, 0x1D0 / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // emc_quse_width. - { 0x00000003, 0x1DC / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // emc_einput. - { 0x0000000C, 0x1E0 / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // emc_einput_duration. - { 0x88161414, 0x2E0 / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // emc_mrw14. - { 0x80000713, 0x32C / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // emc_dyn_self_ref_control. - { 0x2A800000, 0x6DC / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // mc_video_protect_gpu_override0. - { 0x00000002, 0x6E0 / 4, LPDDR4X_4GB_SAMSUNG_K4U6E3S4AA_MGCL }, // mc_video_protect_gpu_override1. + { 0x88161414, DRAM_CC_LPDDR4X_DSR, DCFG_OFFSET_OF(emc_mrw14) }, + { 0x80000713, DRAM_CC_LPDDR4X_DSR, DCFG_OFFSET_OF(emc_dyn_self_ref_control) }, - // Samsung LPDDR4X 8GB K4UBE3D4AA-MGCL 10nm-class (1y-X03) Die-A for SDEV Iowa, Hoag and Aula. - { 0x05500000, 0x0D4 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_auto_cal_config2. - { 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_auto_cal_vref_sel0. - { 0x00000001, 0x134 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_adr_cfg. 2 Ranks. - { 0x00000006, 0x1CC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_quse. - { 0x00000005, 0x1D0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_quse_width. - { 0x00000003, 0x1DC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_einput. - { 0x0000000C, 0x1E0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_einput_duration. - { 0x00000008, 0x24C / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_tfaw. - { 0x08010004, 0x2B8 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw1. - { 0x08020000, 0x2BC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw2. - { 0x080D0000, 0x2C0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw3. - { 0x08033131, 0x2C8 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw6. - { 0x080B0000, 0x2CC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw8. - { 0x0C0E5D5D, 0x2D0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw9. - { 0x080C5D5D, 0x2D4 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw10. - { 0x0C0D0808, 0x2D8 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw12. - { 0x0C0D0000, 0x2DC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw13. - { 0x08161414, 0x2E0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw14. - { 0x08010004, 0x2E4 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_mrw_extra. - { 0x00000000, 0x340 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_dev_select. Both devices. - { 0x0051004F, 0x450 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_zcal_mrw_cmd. - { 0x40000001, 0x45C / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_zcal_init_dev1. - { 0x00000000, 0x594 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_pmacro_tx_pwrd4. - { 0x00001000, 0x598 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // emc_pmacro_tx_pwrd5. - { 0x00000001, 0x630 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // mc_emem_adr_cfg. 2 Ranks. - { 0x00002000, 0x64C / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // mc_emem_cfg. 8GB total density. - { 0x00000001, 0x670 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // mc_emem_arb_timing_faw. - { 0x00000002, 0x680 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // mc_emem_arb_timing_r2r. - { 0x02020001, 0x694 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // mc_emem_arb_da_turns. - { 0x2A800000, 0x6DC / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // mc_video_protect_gpu_override0. - { 0x00000002, 0x6E0 / 4, LPDDR4X_8GB_SAMSUNG_K4UBE3D4AA_MGCL }, // mc_video_protect_gpu_override1. + { 0x00000006, DRAM_CC_LPDDR4X_QUSE, DCFG_OFFSET_OF(emc_quse) }, + { 0x00000005, DRAM_CC_LPDDR4X_QUSE, DCFG_OFFSET_OF(emc_quse_width) }, + { 0x00000003, DRAM_CC_LPDDR4X_QUSE, DCFG_OFFSET_OF(emc_einput) }, + { 0x0000000C, DRAM_CC_LPDDR4X_QUSE, DCFG_OFFSET_OF(emc_einput_duration) }, - // Samsung LPDDR4X 4GB 10nm-class (1y-Y01) Die-? for Iowa. - { 0x05500000, 0x0D4 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_auto_cal_config2. - { 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_auto_cal_vref_sel0. - { 0x00000008, 0x24C / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_tfaw. - { 0x88161414, 0x2E0 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_mrw14. - { 0x80000713, 0x32C / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_dyn_self_ref_control. - { 0x000F0018, 0x3AC / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dq_rank0_4. - { 0x000F0018, 0x3C4 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dq_rank1_4. - { 0x00440048, 0x3CC / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_0. - { 0x00440045, 0x3D0 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_1. - { 0x00470047, 0x3D4 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_2. - { 0x0005000D, 0x3DC / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_4. - { 0x00440048, 0x3E4 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_0. - { 0x00440045, 0x3E8 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_1. - { 0x00470047, 0x3EC / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_2. - { 0x0005000D, 0x3F4 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_4. - { 0x00180018, 0x41C / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ddll_long_cmd_0. - { 0x000F000F, 0x420 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ddll_long_cmd_1. - { 0x00000018, 0x42C / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // emc_pmacro_ddll_long_cmd_4. - { 0x00000001, 0x670 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // mc_emem_arb_timing_faw. - { 0x2A800000, 0x6DC / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // mc_video_protect_gpu_override0. - { 0x00000002, 0x6E0 / 4, LPDDR4X_4GB_SAMSUNG_1Y_Y }, // mc_video_protect_gpu_override1. + { 0x00000008, DRAM_CC_LPDDR4X_FAW, DCFG_OFFSET_OF(emc_tfaw) }, + { 0x00000001, DRAM_CC_LPDDR4X_FAW, DCFG_OFFSET_OF(mc_emem_arb_timing_faw) }, - // Samsung LPDDR4X 8GB 10nm-class (1y-Y01) Die-? for SDEV Iowa. - { 0x05500000, 0x0D4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_auto_cal_config2. - { 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_auto_cal_vref_sel0. - { 0x00000001, 0x134 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_adr_cfg. 2 Ranks. - { 0x00000008, 0x24C / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_tfaw. - { 0x08010004, 0x2B8 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw1. - { 0x08020000, 0x2BC / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw2. - { 0x080D0000, 0x2C0 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw3. - { 0x08033131, 0x2C8 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw6. - { 0x080B0000, 0x2CC / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw8. - { 0x0C0E5D5D, 0x2D0 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw9. - { 0x080C5D5D, 0x2D4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw10. - { 0x0C0D0808, 0x2D8 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw12. - { 0x0C0D0000, 0x2DC / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw13. - { 0x08161414, 0x2E0 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw14. - { 0x08010004, 0x2E4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_mrw_extra. - { 0x00000000, 0x340 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_dev_select. Both devices. - { 0x32323232, 0x350 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ib_vref_dq_0. - { 0x32323232, 0x354 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ib_vref_dq_1. - { 0x000F0018, 0x3AC / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dq_rank0_4. - { 0x000F0018, 0x3C4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dq_rank1_4. - { 0x00440048, 0x3CC / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_0. - { 0x00440045, 0x3D0 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_1. - { 0x00470047, 0x3D4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_2. - { 0x0005000D, 0x3DC / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank0_4. - { 0x00440048, 0x3E4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_0. - { 0x00440045, 0x3E8 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_1. - { 0x00470047, 0x3EC / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_2. - { 0x0005000D, 0x3F4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ob_ddll_long_dqs_rank1_4. - { 0x00180018, 0x41C / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ddll_long_cmd_0. - { 0x000F000F, 0x420 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ddll_long_cmd_1. - { 0x00000018, 0x42C / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_ddll_long_cmd_4. - { 0x0051004F, 0x450 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_zcal_mrw_cmd. - { 0x40000001, 0x45C / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_zcal_init_dev1. - { 0x00000000, 0x594 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_tx_pwrd4. - { 0x00001000, 0x598 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // emc_pmacro_tx_pwrd5. - { 0x00000001, 0x630 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // mc_emem_adr_cfg. 2 Ranks. - { 0x00002000, 0x64C / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // mc_emem_cfg. 8GB total density. - { 0x00000001, 0x670 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // mc_emem_arb_timing_faw. - { 0x00000002, 0x680 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // mc_emem_arb_timing_r2r. - { 0x02020001, 0x694 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // mc_emem_arb_da_turns. - { 0x2A800000, 0x6DC / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // mc_video_protect_gpu_override0. - { 0x00000002, 0x6E0 / 4, LPDDR4X_8GB_SAMSUNG_1Y_Y }, // mc_video_protect_gpu_override1. + // Moved to default config. + // { 0xE4FACB43, DRAM_CC_LPDDR4X_VPR, DCFG_OFFSET_OF(mc_video_protect_vpr_override) }, // + TSEC, NVENC. + // { 0x0600FED3, DRAM_CC_LPDDR4X_VPR, DCFG_OFFSET_OF(mc_video_protect_vpr_override1) }, // + TSECB, TSEC1, TSECB1. -/* - // Samsung LPDDR4X 8GB 10nm-class (1y-A01) Die-? for SDEV Aula? - { 0x00000001, 0x134 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_adr_cfg. 2 Ranks. - { 0x08010004, 0x2B8 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw1. - { 0x08020000, 0x2BC / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw2. - { 0x080D0000, 0x2C0 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw3. - { 0x08033131, 0x2C8 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw6. - { 0x080B0000, 0x2CC / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw8. - { 0x0C0E5D5D, 0x2D0 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw9. - { 0x080C5D5D, 0x2D4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw10. - { 0x0C0D0808, 0x2D8 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw12. - { 0x0C0D0000, 0x2DC / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw13. - { 0x08161414, 0x2E0 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw14. - { 0x08010004, 0x2E4 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_mrw_extra. - { 0x00000000, 0x340 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_dev_select. Both devices. - { 0x35353535, 0x350 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_vref_dq_0. - { 0x35353535, 0x354 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_vref_dq_1. - { 0x35353535, 0x358 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_vref_dqs_0. - { 0x35353535, 0x35C / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_vref_dqs_1. - { 0x00480048, 0x3FC / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_ddll_long_dqs_rank0_0. - { 0x00480048, 0x400 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_ddll_long_dqs_rank0_1. - { 0x00480048, 0x404 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_ddll_long_dqs_rank0_2. - { 0x00480048, 0x408 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_ddll_long_dqs_rank0_3. - { 0x00480048, 0x40C / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_ddll_long_dqs_rank1_0. - { 0x00480048, 0x410 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_ddll_long_dqs_rank1_1. - { 0x00480048, 0x414 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_ddll_long_dqs_rank1_2. - { 0x00480048, 0x418 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_ib_ddll_long_dqs_rank1_3. - { 0x0051004F, 0x450 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_zcal_mrw_cmd. - { 0x40000001, 0x45C / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_zcal_init_dev1. - { 0x00010100, 0x594 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_tx_pwrd4. - { 0x00400010, 0x598 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // emc_pmacro_tx_pwrd5. - { 0x00000001, 0x630 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // mc_emem_adr_cfg. 2 Ranks. - { 0x00002000, 0x64C / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // mc_emem_cfg. 8GB total density. - { 0x00000002, 0x670 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // mc_emem_arb_timing_faw. - { 0x00000002, 0x680 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // mc_emem_arb_timing_r2r. - { 0x02020001, 0x694 / 4, LPDDR4X_8GB_SAMSUNG_1Y_A }, // mc_emem_arb_da_turns. -*/ - // Micron LPDDR4X 4GB 10nm-class (1y-01) Die-A for Unknown Iowa/Hoag/Aula. - { 0x05500000, 0x0D4 / 4, LPDDR4X_4GB_MICRON_1Y_A }, // emc_auto_cal_config2. - { 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_4GB_MICRON_1Y_A }, // emc_auto_cal_vref_sel0. - { 0x00000006, 0x1CC / 4, LPDDR4X_4GB_MICRON_1Y_A }, // emc_quse. - { 0x00000005, 0x1D0 / 4, LPDDR4X_4GB_MICRON_1Y_A }, // emc_quse_width. - { 0x00000003, 0x1DC / 4, LPDDR4X_4GB_MICRON_1Y_A }, // emc_einput. - { 0x0000000C, 0x1E0 / 4, LPDDR4X_4GB_MICRON_1Y_A }, // emc_einput_duration. - { 0x00000008, 0x24C / 4, LPDDR4X_4GB_MICRON_1Y_A }, // emc_tfaw. - { 0x88161414, 0x2E0 / 4, LPDDR4X_4GB_MICRON_1Y_A }, // emc_mrw14. - { 0x80000713, 0x32C / 4, LPDDR4X_4GB_MICRON_1Y_A }, // emc_dyn_self_ref_control. - { 0x00000001, 0x670 / 4, LPDDR4X_4GB_MICRON_1Y_A }, // mc_emem_arb_timing_faw. - { 0x2A800000, 0x6DC / 4, LPDDR4X_4GB_MICRON_1Y_A }, // mc_video_protect_gpu_override0. - { 0x00000002, 0x6E0 / 4, LPDDR4X_4GB_MICRON_1Y_A }, // mc_video_protect_gpu_override1. - - // Hynix LPDDR4X 4GB 10nm-class (1y-01) Die-A for Unknown Iowa/Hoag/Aula. - { 0x05500000, 0x0D4 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_auto_cal_config2. - { 0xC9AFBCBC, 0x0F4 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_auto_cal_vref_sel0. - { 0x00000006, 0x1CC / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_quse. - { 0x00000005, 0x1D0 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_quse_width. - { 0x00000003, 0x1DC / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_einput. - { 0x0000000C, 0x1E0 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_einput_duration. - { 0x00000008, 0x24C / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_tfaw. - { 0x88161414, 0x2E0 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_mrw14. - { 0x80000713, 0x32C / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // emc_dyn_self_ref_control. - { 0x00000001, 0x670 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // mc_emem_arb_timing_faw. - { 0xE4FACB43, 0x6D4 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // mc_video_protect_vpr_override. + TSEC, NVENC. - { 0x0600FED3, 0x6D8 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // mc_video_protect_vpr_override1. + TSECB, TSEC1, TSECB1. - { 0x2A800000, 0x6DC / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // mc_video_protect_gpu_override0. - { 0x00000002, 0x6E0 / 4, LPDDR4X_4GB_HYNIX_1Y_A }, // mc_video_protect_gpu_override1. - - //!TODO: Too many duplicates. + { 0x00000001, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(emc_adr_cfg) }, // 2 Ranks. + { 0x08010004, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(emc_mrw1) }, + { 0x08020000, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(emc_mrw2) }, + { 0x080D0000, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(emc_mrw3) }, + { 0x08033131, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(emc_mrw6) }, + { 0x080B0000, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(emc_mrw8) }, + { 0x0C0E5D5D, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(emc_mrw9) }, + { 0x080C5D5D, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(emc_mrw10) }, + { 0x0C0D0808, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(emc_mrw12) }, + { 0x0C0D0000, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(emc_mrw13) }, + { 0x08161414, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(emc_mrw14) }, + { 0x08010004, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(emc_mrw_extra) }, + { 0x00000000, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(emc_dev_select) }, // Both devices. + { 0x0051004F, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(emc_zcal_mrw_cmd) }, + { 0x40000001, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(emc_zcal_init_dev1) }, + { 0x00000000, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(emc_pmacro_tx_pwrd4) }, + { 0x00001000, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(emc_pmacro_tx_pwrd5) }, + { 0x00000001, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(mc_emem_adr_cfg) }, // 2 Ranks. + { 0x00002000, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(mc_emem_cfg) }, // 8GB total density. Max 8GB. + { 0x00000002, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(mc_emem_arb_timing_r2r) }, + { 0x02020001, DRAM_CC_LPDDR4X_8GB, DCFG_OFFSET_OF(mc_emem_arb_da_turns) }, }; +#undef DCFG_OFFSET_OF diff --git a/bdk/mem/sdram_lp0.c b/bdk/mem/sdram_lp0.c deleted file mode 100644 index 1e50103..0000000 --- a/bdk/mem/sdram_lp0.c +++ /dev/null @@ -1,1538 +0,0 @@ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * Copyright 2014 Google Inc. - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 CTCaer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include -#include -#include -#include - -#define pack(src, src_bits, dst, dst_bits) { \ - u32 mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \ - dst &= ~(mask << (0 ? dst_bits)); \ - dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); \ -} - -#define s(param, src_bits, pmcreg, dst_bits) \ - pack(sdram->param, src_bits, pmc->pmcreg, dst_bits) - -#define c(value, pmcreg, dst_bits) \ - pack(value, (1 ? dst_bits) - (0 ? dst_bits) : 0, pmc->pmcreg, dst_bits) - -/* 32 bits version of s macro */ -#define s32(param, pmcreg) pmc->pmcreg = sdram->param - -/* 32 bits version c macro */ -#define c32(value, pmcreg) pmc->pmcreg = value - -/* - * This function reads SDRAM parameters from the common BCT format and - * writes them into PMC scratch registers (where the BootROM expects them - * on LP0 resume). - */ -static void _sdram_lp0_save_params_t210(const void *params) -{ - struct sdram_params_t210 *sdram = (struct sdram_params_t210 *)params; - struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs *)PMC_BASE; - - //TODO: pkg1.1 (1.X - 3.X) reads them from MC. - // Patch carveout parameters. - /*sdram->McGeneralizedCarveout1Bom = 0; - sdram->McGeneralizedCarveout1BomHi = 0; - sdram->McGeneralizedCarveout1Size128kb = 0; - sdram->McGeneralizedCarveout1Access0 = 0; - sdram->McGeneralizedCarveout1Access1 = 0; - sdram->McGeneralizedCarveout1Access2 = 0; - sdram->McGeneralizedCarveout1Access3 = 0; - sdram->McGeneralizedCarveout1Access4 = 0; - sdram->McGeneralizedCarveout1ForceInternalAccess0 = 0; - sdram->McGeneralizedCarveout1ForceInternalAccess1 = 0; - sdram->McGeneralizedCarveout1ForceInternalAccess2 = 0; - sdram->McGeneralizedCarveout1ForceInternalAccess3 = 0; - sdram->McGeneralizedCarveout1ForceInternalAccess4 = 0; - sdram->McGeneralizedCarveout1Cfg0 = 0; - sdram->McGeneralizedCarveout2Bom = 0x80020000; - sdram->McGeneralizedCarveout2BomHi = 0; - sdram->McGeneralizedCarveout2Size128kb = 2; - sdram->McGeneralizedCarveout2Access0 = 0; - sdram->McGeneralizedCarveout2Access1 = 0; - sdram->McGeneralizedCarveout2Access2 = 0x3000000; - sdram->McGeneralizedCarveout2Access3 = 0; - sdram->McGeneralizedCarveout2Access4 = 0x300; - sdram->McGeneralizedCarveout2ForceInternalAccess0 = 0; - sdram->McGeneralizedCarveout2ForceInternalAccess1 = 0; - sdram->McGeneralizedCarveout2ForceInternalAccess2 = 0; - sdram->McGeneralizedCarveout2ForceInternalAccess3 = 0; - sdram->McGeneralizedCarveout2ForceInternalAccess4 = 0; - sdram->McGeneralizedCarveout2Cfg0 = 0x440167E; - sdram->McGeneralizedCarveout3Bom = 0; - sdram->McGeneralizedCarveout3BomHi = 0; - sdram->McGeneralizedCarveout3Size128kb = 0; - sdram->McGeneralizedCarveout3Access0 = 0; - sdram->McGeneralizedCarveout3Access1 = 0; - sdram->McGeneralizedCarveout3Access2 = 0x3000000; - sdram->McGeneralizedCarveout3Access3 = 0; - sdram->McGeneralizedCarveout3Access4 = 0x300; - sdram->McGeneralizedCarveout3ForceInternalAccess0 = 0; - sdram->McGeneralizedCarveout3ForceInternalAccess1 = 0; - sdram->McGeneralizedCarveout3ForceInternalAccess2 = 0; - sdram->McGeneralizedCarveout3ForceInternalAccess3 = 0; - sdram->McGeneralizedCarveout3ForceInternalAccess4 = 0; - sdram->McGeneralizedCarveout3Cfg0 = 0x4401E7E; - sdram->McGeneralizedCarveout4Bom = 0; - sdram->McGeneralizedCarveout4BomHi = 0; - sdram->McGeneralizedCarveout4Size128kb = 0; - sdram->McGeneralizedCarveout4Access0 = 0; - sdram->McGeneralizedCarveout4Access1 = 0; - sdram->McGeneralizedCarveout4Access2 = 0; - sdram->McGeneralizedCarveout4Access3 = 0; - sdram->McGeneralizedCarveout4Access4 = 0; - sdram->McGeneralizedCarveout4ForceInternalAccess0 = 0; - sdram->McGeneralizedCarveout4ForceInternalAccess1 = 0; - sdram->McGeneralizedCarveout4ForceInternalAccess2 = 0; - sdram->McGeneralizedCarveout4ForceInternalAccess3 = 0; - sdram->McGeneralizedCarveout4ForceInternalAccess4 = 0; - sdram->McGeneralizedCarveout4Cfg0 = 0x8F; - sdram->McGeneralizedCarveout5Bom = 0; - sdram->McGeneralizedCarveout5BomHi = 0; - sdram->McGeneralizedCarveout5Size128kb = 0; - sdram->McGeneralizedCarveout5Access0 = 0; - sdram->McGeneralizedCarveout5Access1 = 0; - sdram->McGeneralizedCarveout5Access2 = 0; - sdram->McGeneralizedCarveout5Access3 = 0; - sdram->McGeneralizedCarveout5Access4 = 0; - sdram->McGeneralizedCarveout5ForceInternalAccess0 = 0; - sdram->McGeneralizedCarveout5ForceInternalAccess1 = 0; - sdram->McGeneralizedCarveout5ForceInternalAccess2 = 0; - sdram->McGeneralizedCarveout5ForceInternalAccess3 = 0; - sdram->McGeneralizedCarveout5ForceInternalAccess4 = 0; - sdram->McGeneralizedCarveout5Cfg0 = 0x8F;*/ - - //TODO: this is 4.X+ behaviour which seems to work fine for < 4.X. - // Patch carveout parameters. - sdram->McGeneralizedCarveout1Cfg0 = 0; - sdram->McGeneralizedCarveout2Cfg0 = 0; - sdram->McGeneralizedCarveout3Cfg0 = 0; - sdram->McGeneralizedCarveout4Cfg0 = 0; - sdram->McGeneralizedCarveout5Cfg0 = 0; - - // Patch SDRAM parameters. - u32 t0 = sdram->EmcSwizzleRank0Byte0 << 5 >> 29 > sdram->EmcSwizzleRank0Byte0 << 1 >> 29; - u32 t1 = (t0 & 0xFFFFFFEF) | ((sdram->EmcSwizzleRank1Byte0 << 5 >> 29 > sdram->EmcSwizzleRank1Byte0 << 1 >> 29) << 4); - u32 t2 = (t1 & 0xFFFFFFFD) | ((sdram->EmcSwizzleRank0Byte1 << 5 >> 29 > sdram->EmcSwizzleRank0Byte1 << 1 >> 29) << 1); - u32 t3 = (t2 & 0xFFFFFFDF) | ((sdram->EmcSwizzleRank1Byte1 << 5 >> 29 > sdram->EmcSwizzleRank1Byte1 << 1 >> 29) << 5); - u32 t4 = (t3 & 0xFFFFFFFB) | ((sdram->EmcSwizzleRank0Byte2 << 5 >> 29 > sdram->EmcSwizzleRank0Byte2 << 1 >> 29) << 2); - u32 t5 = (t4 & 0xFFFFFFBF) | ((sdram->EmcSwizzleRank1Byte2 << 5 >> 29 > sdram->EmcSwizzleRank1Byte2 << 1 >> 29) << 6); - u32 t6 = (t5 & 0xFFFFFFF7) | ((sdram->EmcSwizzleRank0Byte3 << 5 >> 29 > sdram->EmcSwizzleRank0Byte3 << 1 >> 29) << 3); - u32 t7 = (t6 & 0xFFFFFF7F) | ((sdram->EmcSwizzleRank1Byte3 << 5 >> 29 > sdram->EmcSwizzleRank1Byte3 << 1 >> 29) << 7); - sdram->SwizzleRankByteEncode = t7; - sdram->EmcBctSpare2 = 0x40000DD8; - sdram->EmcBctSpare3 = t7; - - s(EmcClockSource, 7:0, scratch6, 15:8); - s(EmcClockSourceDll, 7:0, scratch6, 23:16); - s(EmcClockSource, 31:29, scratch6, 26:24); - s(EmcClockSourceDll, 31:29, scratch6, 29:27); - s(EmcClockSourceDll, 11:10, scratch6, 31:30); - s(ClkRstControllerPllmMisc2Override, 9:8, scratch7, 1:0); - s(ClkRstControllerPllmMisc2Override, 2:1, scratch7, 3:2); - s(EmcZqCalLpDdr4WarmBoot, 31:30, scratch7, 5:4); - s(EmcClockSource, 15:15, scratch7, 6:6); - s(EmcClockSource, 26:26, scratch7, 7:7); - s(EmcClockSource, 20:20, scratch7, 8:8); - s(EmcClockSource, 19:19, scratch7, 9:9); - s(ClkRstControllerPllmMisc2Override, 13:13, scratch7, 10:10); - s(ClkRstControllerPllmMisc2Override, 12:12, scratch7, 11:11); - s(ClkRstControllerPllmMisc2Override, 11:11, scratch7, 12:12); - s(ClkRstControllerPllmMisc2Override, 10:10, scratch7, 13:13); - s(ClkRstControllerPllmMisc2Override, 5:5, scratch7, 14:14); - s(ClkRstControllerPllmMisc2Override, 4:4, scratch7, 15:15); - s(ClkRstControllerPllmMisc2Override, 3:3, scratch7, 16:16); - s(ClkRstControllerPllmMisc2Override, 0:0, scratch7, 17:17); - s(EmcZqCalLpDdr4WarmBoot, 1:0, scratch7, 19:18); - s(EmcZqCalLpDdr4WarmBoot, 4:4, scratch7, 20:20); - s(EmcOdtWrite, 5:0, scratch7, 26:21); - s(EmcOdtWrite, 11:8, scratch7, 30:27); - s(EmcOdtWrite, 31:31, scratch7, 31:31); - s(EmcFdpdCtrlCmdNoRamp, 0:0, scratch13, 30:30); - s(EmcCfgPipeClk, 0:0, scratch13, 31:31); - s(McEmemArbMisc2, 0:0, scratch14, 30:30); - s(McDaCfg0, 0:0, scratch14, 31:31); - s(EmcQRst, 6:0, scratch15, 26:20); - s(EmcQRst, 20:16, scratch15, 31:27); - s(EmcPmacroCmdTxDrv, 5:0, scratch16, 25:20); - s(EmcPmacroCmdTxDrv, 13:8, scratch16, 31:26); - s(EmcPmacroAutocalCfg0, 2:0, scratch17, 22:20); - s(EmcPmacroAutocalCfg0, 10:8, scratch17, 25:23); - s(EmcPmacroAutocalCfg0, 18:16, scratch17, 28:26); - s(EmcPmacroAutocalCfg0, 26:24, scratch17, 31:29); - s(EmcPmacroAutocalCfg1, 2:0, scratch18, 22:20); - s(EmcPmacroAutocalCfg1, 10:8, scratch18, 25:23); - s(EmcPmacroAutocalCfg1, 18:16, scratch18, 28:26); - s(EmcPmacroAutocalCfg1, 26:24, scratch18, 31:29); - s(EmcPmacroAutocalCfg2, 2:0, scratch19, 22:20); - s(EmcPmacroAutocalCfg2, 10:8, scratch19, 25:23); - s(EmcPmacroAutocalCfg2, 18:16, scratch19, 28:26); - s(EmcPmacroAutocalCfg2, 26:24, scratch19, 31:29); - s32(EmcCfgRsv,scratch22); - s32(EmcAutoCalConfig, scratch23); - s32(EmcAutoCalVrefSel0, scratch24); - s32(EmcPmacroBrickCtrlRfu1, scratch25); - s32(EmcPmacroBrickCtrlRfu2, scratch26); - s32(EmcPmcScratch1, scratch27); - s32(EmcPmcScratch2, scratch28); - s32(EmcPmcScratch3, scratch29); - s32(McEmemArbDaTurns, scratch30); - s(EmcFbioSpare, 31:24, scratch58, 7:0); - s(EmcFbioSpare, 23:16, scratch58, 15:8); - s(EmcFbioSpare, 15:8, scratch58, 23:16); - s(EmcFbioSpare, 7:2, scratch58, 29:24); - s(EmcFbioSpare, 0:0, scratch58, 30:30); - s(EmcDllCfg0, 29:0, scratch59, 29:0); - s(EmcPmacroDdllBypass, 11:0, scratch60, 11:0); - s(EmcPmacroDdllBypass, 27:13, scratch60, 26:12); - s(EmcPmacroDdllBypass, 31:29, scratch60, 29:27); - s(McEmemArbMisc0, 14:0, scratch61, 14:0); - s(McEmemArbMisc0, 30:16, scratch61, 29:15); - s(EmcFdpdCtrlCmd, 16:0, scratch62, 16:0); - s(EmcFdpdCtrlCmd, 31:20, scratch62, 28:17); - s(EmcAutoCalConfig2, 27:0, scratch63, 27:0); - s(EmcBurstRefreshNum, 3:0, scratch63, 31:28); - s(EmcPmacroZctrl, 27:0, scratch64, 27:0); - s(EmcTppd, 3:0, scratch64, 31:28); - s(EmcCfgDigDll, 10:0, scratch65, 10:0); - s(EmcCfgDigDll, 25:12, scratch65, 24:11); - s(EmcCfgDigDll, 27:27, scratch65, 25:25); - s(EmcCfgDigDll, 31:30, scratch65, 27:26); - s(EmcR2r, 3:0, scratch65, 31:28); - s(EmcFdpdCtrlDq, 16:0, scratch66, 16:0); - s(EmcFdpdCtrlDq, 28:20, scratch66, 25:17); - s(EmcFdpdCtrlDq, 31:30, scratch66, 27:26); - s(EmcW2w, 3:0, scratch66, 31:28); - s(EmcPmacroTxPwrd4, 13:0, scratch67, 13:0); - s(EmcPmacroTxPwrd4, 29:16, scratch67, 27:14); - s(EmcPmacroCommonPadTxCtrl, 3:0, scratch67, 31:28); - s(EmcPmacroTxPwrd5, 13:0, scratch68, 13:0); - s(EmcPmacroTxPwrd5, 29:16, scratch68, 27:14); - s(EmcPmacroDdllPwrd0, 4:0, scratch69, 4:0); - s(EmcPmacroDdllPwrd0, 12:6, scratch69, 11:5); - s(EmcPmacroDdllPwrd0, 20:14, scratch69, 18:12); - s(EmcPmacroDdllPwrd0, 28:22, scratch69, 25:19); - s(EmcPmacroDdllPwrd0, 31:30, scratch69, 27:26); - s(EmcCfg, 4:4, scratch69, 31:31); - s(EmcPmacroDdllPwrd1, 4:0, scratch70, 4:0); - s(EmcPmacroDdllPwrd1, 12:6, scratch70, 11:5); - s(EmcPmacroDdllPwrd1, 20:14, scratch70, 18:12); - s(EmcPmacroDdllPwrd1, 28:22, scratch70, 25:19); - s(EmcPmacroDdllPwrd1, 31:30, scratch70, 27:26); - s(EmcCfg, 5:5, scratch70, 31:31); - s(EmcPmacroDdllPwrd2, 4:0, scratch71, 4:0); - s(EmcPmacroDdllPwrd2, 12:6, scratch71, 11:5); - s(EmcPmacroDdllPwrd2, 20:14, scratch71, 18:12); - s(EmcPmacroDdllPwrd2, 28:22, scratch71, 25:19); - s(EmcPmacroDdllPwrd2, 31:30, scratch71, 27:26); - s(EmcFbioCfg5, 23:20, scratch71, 31:28); - s(EmcPmacroIbVrefDq_0, 6:0, scratch72, 6:0); - s(EmcPmacroIbVrefDq_0, 14:8, scratch72, 13:7); - s(EmcPmacroIbVrefDq_0, 22:16, scratch72, 20:14); - s(EmcPmacroIbVrefDq_0, 30:24, scratch72, 27:21); - s(EmcFbioCfg5, 15:13, scratch72, 30:28); - s(EmcCfg, 6:6, scratch72, 31:31); - s(EmcPmacroIbVrefDq_1, 6:0, scratch73, 6:0); - s(EmcPmacroIbVrefDq_1, 14:8, scratch73, 13:7); - s(EmcPmacroIbVrefDq_1, 22:16, scratch73, 20:14); - s(EmcPmacroIbVrefDq_1, 30:24, scratch73, 27:21); - s(EmcCfg2, 5:3, scratch73, 30:28); - s(EmcCfg, 7:7, scratch73, 31:31); - s(EmcPmacroIbVrefDqs_0, 6:0, scratch74, 6:0); - s(EmcPmacroIbVrefDqs_0, 14:8, scratch74, 13:7); - s(EmcPmacroIbVrefDqs_0, 22:16, scratch74, 20:14); - s(EmcPmacroIbVrefDqs_0, 30:24, scratch74, 27:21); - s(EmcCfg, 17:16, scratch74, 29:28); - s(EmcFbioCfg5, 1:0, scratch74, 31:30); - s(EmcPmacroIbVrefDqs_1, 6:0, scratch75, 6:0); - s(EmcPmacroIbVrefDqs_1, 14:8, scratch75, 13:7); - s(EmcPmacroIbVrefDqs_1, 22:16, scratch75, 20:14); - s(EmcPmacroIbVrefDqs_1, 30:24, scratch75, 27:21); - s(EmcFbioCfg5, 3:2, scratch75, 29:28); - s(EmcCfg2, 27:26, scratch75, 31:30); - s(EmcPmacroDdllShortCmd_0, 6:0, scratch76, 6:0); - s(EmcPmacroDdllShortCmd_0, 14:8, scratch76, 13:7); - s(EmcPmacroDdllShortCmd_0, 22:16, scratch76, 20:14); - s(EmcPmacroDdllShortCmd_0, 30:24, scratch76, 27:21); - s(EmcPmacroCmdPadTxCtrl, 3:2, scratch76, 29:28); - s(EmcPmacroCmdPadTxCtrl, 7:6, scratch76, 31:30); - s(EmcPmacroDdllShortCmd_1, 6:0, scratch77, 6:0); - s(EmcPmacroDdllShortCmd_1, 14:8, scratch77, 13:7); - s(EmcPmacroDdllShortCmd_1, 22:16, scratch77, 20:14); - s(EmcPmacroDdllShortCmd_1, 30:24, scratch77, 27:21); - s(EmcPmacroCmdPadTxCtrl, 11:10, scratch77, 29:28); - s(EmcPmacroCmdPadTxCtrl, 15:14, scratch77, 31:30); - s(EmcAutoCalChannel, 5:0, scratch78, 5:0); - s(EmcAutoCalChannel, 11:8, scratch78, 9:6); - s(EmcAutoCalChannel, 27:16, scratch78, 21:10); - s(EmcAutoCalChannel, 31:29, scratch78, 24:22); - s(EmcConfigSampleDelay, 6:0, scratch78, 31:25); - s(EmcPmacroRxTerm, 5:0, scratch79, 5:0); - s(EmcPmacroRxTerm, 13:8, scratch79, 11:6); - s(EmcPmacroRxTerm, 21:16, scratch79, 17:12); - s(EmcPmacroRxTerm, 29:24, scratch79, 23:18); - s(EmcRc, 7:0, scratch79, 31:24); - s(EmcPmacroDqTxDrv, 5:0, scratch80, 5:0); - s(EmcPmacroDqTxDrv, 13:8, scratch80, 11:6); - s(EmcPmacroDqTxDrv, 21:16, scratch80, 17:12); - s(EmcPmacroDqTxDrv, 29:24, scratch80, 23:18); - s(EmcSelDpdCtrl, 5:2, scratch80, 27:24); - s(EmcSelDpdCtrl, 8:8, scratch80, 28:28); - s(EmcSelDpdCtrl, 18:16, scratch80, 31:29); - s(EmcPmacroCaTxDrv, 5:0, scratch81, 5:0); - s(EmcPmacroCaTxDrv, 13:8, scratch81, 11:6); - s(EmcPmacroCaTxDrv, 21:16, scratch81, 17:12); - s(EmcPmacroCaTxDrv, 29:24, scratch81, 23:18); - s(EmcObdly, 5:0, scratch81, 29:24); - s(EmcObdly, 29:28, scratch81, 31:30); - s(EmcZcalInterval, 23:10, scratch82, 13:0); - s(EmcZcalInterval, 9:0, scratch82, 23:14); - s(EmcPmacroCmdRxTermMode, 1:0, scratch82, 25:24); - s(EmcPmacroCmdRxTermMode, 5:4, scratch82, 27:26); - s(EmcPmacroCmdRxTermMode, 9:8, scratch82, 29:28); - s(EmcPmacroCmdRxTermMode, 13:12, scratch82, 31:30); - s(EmcDataBrlshft0, 23:0, scratch83, 23:0); - s(EmcPmacroDataRxTermMode, 1:0, scratch83, 25:24); - s(EmcPmacroDataRxTermMode, 5:4, scratch83, 27:26); - s(EmcPmacroDataRxTermMode, 9:8, scratch83, 29:28); - s(EmcPmacroDataRxTermMode, 13:12, scratch83, 31:30); - s(EmcDataBrlshft1, 23:0, scratch84, 23:0); - s(McEmemArbTimingRc, 7:0, scratch84, 31:24); - s(EmcDqsBrlshft0, 23:0, scratch85, 23:0); - s(McEmemArbRsv, 7:0, scratch85, 31:24); - s(EmcDqsBrlshft1, 23:0, scratch86, 23:0); - s(EmcCfgPipe2, 11:0, scratch87, 11:0); - s(EmcCfgPipe2, 27:16, scratch87, 23:12); - s(EmcCfgPipe1, 11:0, scratch88, 11:0); - s(EmcCfgPipe1, 27:16, scratch88, 23:12); - s(EmcPmacroCmdCtrl0, 5:0, scratch89, 5:0); - s(EmcPmacroCmdCtrl0, 13:8, scratch89, 11:6); - s(EmcPmacroCmdCtrl0, 21:16, scratch89, 17:12); - s(EmcPmacroCmdCtrl0, 29:24, scratch89, 23:18); - s(EmcPmacroCmdCtrl1, 5:0, scratch90, 5:0); - s(EmcPmacroCmdCtrl1, 13:8, scratch90, 11:6); - s(EmcPmacroCmdCtrl1, 21:16, scratch90, 17:12); - s(EmcPmacroCmdCtrl1, 29:24, scratch90, 23:18); - s(EmcRas, 6:0, scratch90, 30:24); - s(EmcCfg, 8:8, scratch90, 31:31); - s(EmcPmacroVttgenCtrl2, 23:0, scratch91, 23:0); - s(EmcW2p, 6:0, scratch91, 30:24); - s(EmcCfg, 9:9, scratch91, 31:31); - s(EmcPmacroCmdPadRxCtrl, 2:0, scratch92, 2:0); - s(EmcPmacroCmdPadRxCtrl, 5:4, scratch92, 4:3); - s(EmcPmacroCmdPadRxCtrl, 10:8, scratch92, 7:5); - s(EmcPmacroCmdPadRxCtrl, 22:12, scratch92, 18:8); - s(EmcPmacroCmdPadRxCtrl, 28:24, scratch92, 23:19); - s(EmcQSafe, 6:0, scratch92, 30:24); - s(EmcCfg, 18:18, scratch92, 31:31); - s(EmcPmacroDataPadRxCtrl, 2:0, scratch93, 2:0); - s(EmcPmacroDataPadRxCtrl, 5:4, scratch93, 4:3); - s(EmcPmacroDataPadRxCtrl, 10:8, scratch93, 7:5); - s(EmcPmacroDataPadRxCtrl, 22:12, scratch93, 18:8); - s(EmcPmacroDataPadRxCtrl, 28:24, scratch93, 23:19); - s(EmcRdv, 6:0, scratch93, 30:24); - s(EmcCfg, 21:21, scratch93, 31:31); - s(McEmemArbDaCovers, 23:0, scratch94, 23:0); - s(EmcRw2Pden, 6:0, scratch94, 30:24); - s(EmcCfg, 22:22, scratch94, 31:31); - s(EmcPmacroCmdCtrl2, 5:0, scratch95, 5:0); - s(EmcPmacroCmdCtrl2, 13:9, scratch95, 10:6); - s(EmcPmacroCmdCtrl2, 21:16, scratch95, 16:11); - s(EmcPmacroCmdCtrl2, 29:24, scratch95, 22:17); - s(EmcRfcPb, 8:0, scratch95, 31:23); - s(EmcPmacroQuseDdllRank0_0, 10:0, scratch96, 10:0); - s(EmcPmacroQuseDdllRank0_0, 26:16, scratch96, 21:11); - s(EmcCfgUpdate, 2:0, scratch96, 24:22); - s(EmcCfgUpdate, 10:8, scratch96, 27:25); - s(EmcCfgUpdate, 31:28, scratch96, 31:28); - s(EmcPmacroQuseDdllRank0_1, 10:0, scratch97, 10:0); - s(EmcPmacroQuseDdllRank0_1, 26:16, scratch97, 21:11); - s(EmcRfc, 9:0, scratch97, 31:22); - s(EmcPmacroQuseDdllRank0_2, 10:0, scratch98, 10:0); - s(EmcPmacroQuseDdllRank0_2, 26:16, scratch98, 21:11); - s(EmcTxsr, 9:0, scratch98, 31:22); - s(EmcPmacroQuseDdllRank0_3, 10:0, scratch99, 10:0); - s(EmcPmacroQuseDdllRank0_3, 26:16, scratch99, 21:11); - s(EmcMc2EmcQ, 2:0, scratch99, 24:22); - s(EmcMc2EmcQ, 10:8, scratch99, 27:25); - s(EmcMc2EmcQ, 27:24, scratch99, 31:28); - s(EmcPmacroQuseDdllRank0_4, 10:0, scratch100, 10:0); - s(EmcPmacroQuseDdllRank0_4, 26:16, scratch100, 21:11); - s(McEmemArbRing1Throttle, 4:0, scratch100, 26:22); - s(McEmemArbRing1Throttle, 20:16, scratch100, 31:27); - s(EmcPmacroQuseDdllRank0_5, 10:0, scratch101, 10:0); - s(EmcPmacroQuseDdllRank0_5, 26:16, scratch101, 21:11); - s(EmcPmacroQuseDdllRank1_0, 10:0, scratch102, 10:0); - s(EmcPmacroQuseDdllRank1_0, 26:16, scratch102, 21:11); - s(EmcAr2Pden, 8:0, scratch102, 30:22); - s(EmcCfg, 23:23, scratch102, 31:31); - s(EmcPmacroQuseDdllRank1_1, 10:0, scratch103, 10:0); - s(EmcPmacroQuseDdllRank1_1, 26:16, scratch103, 21:11); - s(EmcRfcSlr, 8:0, scratch103, 30:22); - s(EmcCfg, 24:24, scratch103, 31:31); - s(EmcPmacroQuseDdllRank1_2, 10:0, scratch104, 10:0); - s(EmcPmacroQuseDdllRank1_2, 26:16, scratch104, 21:11); - s(EmcIbdly, 6:0, scratch104, 28:22); - s(EmcIbdly, 29:28, scratch104, 30:29); - s(EmcCfg, 25:25, scratch104, 31:31); - s(EmcPmacroQuseDdllRank1_3, 10:0, scratch105, 10:0); - s(EmcPmacroQuseDdllRank1_3, 26:16, scratch105, 21:11); - s(McEmemArbTimingRFCPB, 8:0, scratch105, 30:22); - s(EmcCfg, 26:26, scratch105, 31:31); - s(EmcPmacroQuseDdllRank1_4, 10:0, scratch106, 10:0); - s(EmcPmacroQuseDdllRank1_4, 26:16, scratch106, 21:11); - s(EmcTfaw, 6:0, scratch106, 28:22); - s(EmcPmacroDataPadTxCtrl, 3:2, scratch106, 30:29); - s(EmcCfg, 28:28, scratch106, 31:31); - s(EmcPmacroQuseDdllRank1_5, 10:0, scratch107, 10:0); - s(EmcPmacroQuseDdllRank1_5, 26:16, scratch107, 21:11); - s(EmcTClkStable, 6:0, scratch107, 28:22); - s(EmcPmacroDataPadTxCtrl, 7:6, scratch107, 30:29); - s(EmcCfg, 29:29, scratch107, 31:31); - s(EmcPmacroObDdllLongDqRank0_0, 10:0, scratch108, 10:0); - s(EmcPmacroObDdllLongDqRank0_0, 26:16, scratch108, 21:11); - s(EmcPdex2Mrr, 6:0, scratch108, 28:22); - s(EmcPmacroDataPadTxCtrl, 11:10, scratch108, 30:29); - s(EmcCfg, 30:30, scratch108, 31:31); - s(EmcPmacroObDdllLongDqRank0_1, 10:0, scratch109, 10:0); - s(EmcPmacroObDdllLongDqRank0_1, 26:16, scratch109, 21:11); - s(EmcRdvMask, 6:0, scratch109, 28:22); - s(EmcPmacroDataPadTxCtrl, 15:14, scratch109, 30:29); - s(EmcCfg, 31:31, scratch109, 31:31); - s(EmcPmacroObDdllLongDqRank0_2, 10:0, scratch110, 10:0); - s(EmcPmacroObDdllLongDqRank0_2, 26:16, scratch110, 21:11); - s(EmcRdvEarlyMask, 6:0, scratch110, 28:22); - s(EmcFbioCfg5, 4:4, scratch110, 29:29); - s(EmcFbioCfg5, 8:8, scratch110, 30:30); - s(EmcFbioCfg5, 10:10, scratch110, 31:31); - s(EmcPmacroObDdllLongDqRank0_3, 10:0, scratch111, 10:0); - s(EmcPmacroObDdllLongDqRank0_3, 26:16, scratch111, 21:11); - s(EmcRdvEarly, 6:0, scratch111, 28:22); - s(EmcFbioCfg5, 12:12, scratch111, 29:29); - s(EmcFbioCfg5, 25:24, scratch111, 31:30); - s(EmcPmacroObDdllLongDqRank0_4, 10:0, scratch112, 10:0); - s(EmcPmacroObDdllLongDqRank0_4, 26:16, scratch112, 21:11); - s(EmcPmacroDdllShortCmd_2, 6:0, scratch112, 28:22); - s(EmcFbioCfg5, 28:26, scratch112, 31:29); - s(EmcPmacroObDdllLongDqRank0_5, 10:0, scratch113, 10:0); - s(EmcPmacroObDdllLongDqRank0_5, 26:16, scratch113, 21:11); - s(McEmemArbTimingRp, 6:0, scratch113, 28:22); - s(EmcFbioCfg5, 31:30, scratch113, 30:29); - s(EmcCfg2, 0:0, scratch113, 31:31); - s(EmcPmacroObDdllLongDqRank1_0, 10:0, scratch114, 10:0); - s(EmcPmacroObDdllLongDqRank1_0, 26:16, scratch114, 21:11); - s(McEmemArbTimingRas, 6:0, scratch114, 28:22); - s(EmcCfg2, 2:1, scratch114, 30:29); - s(EmcCfg2, 7:7, scratch114, 31:31); - s(EmcPmacroObDdllLongDqRank1_1, 10:0, scratch115, 10:0); - s(EmcPmacroObDdllLongDqRank1_1, 26:16, scratch115, 21:11); - s(McEmemArbTimingFaw, 6:0, scratch115, 28:22); - s(EmcCfg2, 11:10, scratch115, 30:29); - s(EmcCfg2, 14:14, scratch115, 31:31); - s(EmcPmacroObDdllLongDqRank1_2, 10:0, scratch123, 10:0); - s(EmcPmacroObDdllLongDqRank1_2, 26:16, scratch123, 21:11); - s(McEmemArbTimingRap2Pre, 6:0, scratch123, 28:22); - s(EmcCfg2, 16:15, scratch123, 30:29); - s(EmcCfg2, 20:20, scratch123, 31:31); - s(EmcPmacroObDdllLongDqRank1_3, 10:0, scratch124, 10:0); - s(EmcPmacroObDdllLongDqRank1_3, 26:16, scratch124, 21:11); - s(McEmemArbTimingWap2Pre, 6:0, scratch124, 28:22); - s(EmcCfg2, 24:22, scratch124, 31:29); - s(EmcPmacroObDdllLongDqRank1_4, 10:0, scratch125, 10:0); - s(EmcPmacroObDdllLongDqRank1_4, 26:16, scratch125, 21:11); - s(McEmemArbTimingR2W, 6:0, scratch125, 28:22); - s(EmcCfg2, 25:25, scratch125, 29:29); - s(EmcCfg2, 29:28, scratch125, 31:30); - s(EmcPmacroObDdllLongDqRank1_5, 10:0, scratch126, 10:0); - s(EmcPmacroObDdllLongDqRank1_5, 26:16, scratch126, 21:11); - s(McEmemArbTimingW2R, 6:0, scratch126, 28:22); - s(EmcCfg2, 31:30, scratch126, 30:29); - s(EmcCfgPipe, 0:0, scratch126, 31:31); - s(EmcPmacroObDdllLongDqsRank0_0, 10:0, scratch127, 10:0); - s(EmcPmacroObDdllLongDqsRank0_0, 26:16, scratch127, 21:11); - s(EmcRp, 5:0, scratch127, 27:22); - s(EmcCfgPipe, 4:1, scratch127, 31:28); - s(EmcPmacroObDdllLongDqsRank0_1, 10:0, scratch128, 10:0); - s(EmcPmacroObDdllLongDqsRank0_1, 26:16, scratch128, 21:11); - s(EmcR2w, 5:0, scratch128, 27:22); - s(EmcCfgPipe, 8:5, scratch128, 31:28); - s(EmcPmacroObDdllLongDqsRank0_2, 10:0, scratch129, 10:0); - s(EmcPmacroObDdllLongDqsRank0_2, 26:16, scratch129, 21:11); - s(EmcW2r, 5:0, scratch129, 27:22); - s(EmcCfgPipe, 11:9, scratch129, 30:28); - s(EmcCfgPipe, 16:16, scratch129, 31:31); - s(EmcPmacroObDdllLongDqsRank0_3, 10:0, scratch130, 10:0); - s(EmcPmacroObDdllLongDqsRank0_3, 26:16, scratch130, 21:11); - s(EmcR2p, 5:0, scratch130, 27:22); - s(EmcCfgPipe, 20:17, scratch130, 31:28); - s(EmcPmacroObDdllLongDqsRank0_4, 10:0, scratch131, 10:0); - s(EmcPmacroObDdllLongDqsRank0_4, 26:16, scratch131, 21:11); - s(EmcCcdmw, 5:0, scratch131, 27:22); - s(EmcCfgPipe, 24:21, scratch131, 31:28); - s(EmcPmacroObDdllLongDqsRank0_5, 10:0, scratch132, 10:0); - s(EmcPmacroObDdllLongDqsRank0_5, 26:16, scratch132, 21:11); - s(EmcRdRcd, 5:0, scratch132, 27:22); - s(EmcCfgPipe, 27:25, scratch132, 30:28); - s(EmcPmacroTxPwrd0, 0:0, scratch132, 31:31); - s(EmcPmacroObDdllLongDqsRank1_0, 10:0, scratch133, 10:0); - s(EmcPmacroObDdllLongDqsRank1_0, 26:16, scratch133, 21:11); - s(EmcWrRcd, 5:0, scratch133, 27:22); - s(EmcPmacroTxPwrd0, 4:1, scratch133, 31:28); - s(EmcPmacroObDdllLongDqsRank1_1, 10:0, scratch134, 10:0); - s(EmcPmacroObDdllLongDqsRank1_1, 26:16, scratch134, 21:11); - s(EmcWdv, 5:0, scratch134, 27:22); - s(EmcPmacroTxPwrd0, 8:5, scratch134, 31:28); - s(EmcPmacroObDdllLongDqsRank1_2, 10:0, scratch135, 10:0); - s(EmcPmacroObDdllLongDqsRank1_2, 26:16, scratch135, 21:11); - s(EmcQUse, 5:0, scratch135, 27:22); - s(EmcPmacroTxPwrd0, 12:9, scratch135, 31:28); - s(EmcPmacroObDdllLongDqsRank1_3, 10:0, scratch136, 10:0); - s(EmcPmacroObDdllLongDqsRank1_3, 26:16, scratch136, 21:11); - s(EmcPdEx2Wr, 5:0, scratch136, 27:22); - s(EmcPmacroTxPwrd0, 13:13, scratch136, 28:28); - s(EmcPmacroTxPwrd0, 18:16, scratch136, 31:29); - s(EmcPmacroObDdllLongDqsRank1_4, 10:0, scratch137, 10:0); - s(EmcPmacroObDdllLongDqsRank1_4, 26:16, scratch137, 21:11); - s(EmcPdEx2Rd, 5:0, scratch137, 27:22); - s(EmcPmacroTxPwrd0, 22:19, scratch137, 31:28); - s(EmcPmacroObDdllLongDqsRank1_5, 10:0, scratch138, 10:0); - s(EmcPmacroObDdllLongDqsRank1_5, 26:16, scratch138, 21:11); - s(EmcPdex2Cke, 5:0, scratch138, 27:22); - s(EmcPmacroTxPwrd0, 26:23, scratch138, 31:28); - s(EmcPmacroIbDdllLongDqsRank0_0, 10:0, scratch139, 10:0); - s(EmcPmacroIbDdllLongDqsRank0_0, 26:16, scratch139, 21:11); - s(EmcPChg2Pden, 5:0, scratch139, 27:22); - s(EmcPmacroTxPwrd0, 29:27, scratch139, 30:28); - s(EmcPmacroTxPwrd1, 0:0, scratch139, 31:31); - s(EmcPmacroIbDdllLongDqsRank0_1, 10:0, scratch140, 10:0); - s(EmcPmacroIbDdllLongDqsRank0_1, 26:16, scratch140, 21:11); - s(EmcAct2Pden, 5:0, scratch140, 27:22); - s(EmcPmacroTxPwrd1, 4:1, scratch140, 31:28); - s(EmcPmacroIbDdllLongDqsRank0_2, 10:0, scratch141, 10:0); - s(EmcPmacroIbDdllLongDqsRank0_2, 26:16, scratch141, 21:11); - s(EmcCke2Pden, 5:0, scratch141, 27:22); - s(EmcPmacroTxPwrd1, 8:5, scratch141, 31:28); - s(EmcPmacroIbDdllLongDqsRank0_3, 10:0, scratch142, 10:0); - s(EmcPmacroIbDdllLongDqsRank0_3, 26:16, scratch142, 21:11); - s(EmcTcke, 5:0, scratch142, 27:22); - s(EmcPmacroTxPwrd1, 12:9, scratch142, 31:28); - s(EmcPmacroIbDdllLongDqsRank1_0, 10:0, scratch143, 10:0); - s(EmcPmacroIbDdllLongDqsRank1_0, 26:16, scratch143, 21:11); - s(EmcTrpab, 5:0, scratch143, 27:22); - s(EmcPmacroTxPwrd1, 13:13, scratch143, 28:28); - s(EmcPmacroTxPwrd1, 18:16, scratch143, 31:29); - s(EmcPmacroIbDdllLongDqsRank1_1, 10:0, scratch144, 10:0); - s(EmcPmacroIbDdllLongDqsRank1_1, 26:16, scratch144, 21:11); - s(EmcClkenOverride, 3:1, scratch144, 24:22); - s(EmcClkenOverride, 8:6, scratch144, 27:25); - s(EmcPmacroTxPwrd1, 22:19, scratch144, 31:28); - s(EmcPmacroIbDdllLongDqsRank1_2, 10:0, scratch145, 10:0); - s(EmcPmacroIbDdllLongDqsRank1_2, 26:16, scratch145, 21:11); - s(EmcEInput, 5:0, scratch145, 27:22); - s(EmcPmacroTxPwrd1, 26:23, scratch145, 31:28); - s(EmcPmacroIbDdllLongDqsRank1_3, 10:0, scratch146, 10:0); - s(EmcPmacroIbDdllLongDqsRank1_3, 26:16, scratch146, 21:11); - s(EmcEInputDuration, 5:0, scratch146, 27:22); - s(EmcPmacroTxPwrd1, 29:27, scratch146, 30:28); - s(EmcPmacroTxPwrd2, 0:0, scratch146, 31:31); - s(EmcPmacroDdllLongCmd_0, 10:0, scratch147, 10:0); - s(EmcPmacroDdllLongCmd_0, 26:16, scratch147, 21:11); - s(EmcPutermExtra, 5:0, scratch147, 27:22); - s(EmcPmacroTxPwrd2, 4:1, scratch147, 31:28); - s(EmcPmacroDdllLongCmd_1, 10:0, scratch148, 10:0); - s(EmcPmacroDdllLongCmd_1, 26:16, scratch148, 21:11); - s(EmcTckesr, 5:0, scratch148, 27:22); - s(EmcPmacroTxPwrd2, 8:5, scratch148, 31:28); - s(EmcPmacroDdllLongCmd_2, 10:0, scratch149, 10:0); - s(EmcPmacroDdllLongCmd_2, 26:16, scratch149, 21:11); - s(EmcTpd, 5:0, scratch149, 27:22); - s(EmcPmacroTxPwrd2, 12:9, scratch149, 31:28); - s(EmcPmacroDdllLongCmd_3, 10:0, scratch150, 10:0); - s(EmcPmacroDdllLongCmd_3, 26:16, scratch150, 21:11); - s(EmcWdvMask, 5:0, scratch150, 27:22); - s(EmcPmacroTxPwrd2, 13:13, scratch150, 28:28); - s(EmcPmacroTxPwrd2, 18:16, scratch150, 31:29); - s(McEmemArbCfg, 8:0, scratch151, 8:0); - s(McEmemArbCfg, 20:16, scratch151, 13:9); - s(McEmemArbCfg, 31:24, scratch151, 21:14); - s(EmcWdvChk, 5:0, scratch151, 27:22); - s(EmcPmacroTxPwrd2, 22:19, scratch151, 31:28); - s(McEmemArbMisc1, 12:0, scratch152, 12:0); - s(McEmemArbMisc1, 25:21, scratch152, 17:13); - s(McEmemArbMisc1, 31:28, scratch152, 21:18); - s(EmcCmdBrlshft0, 5:0, scratch152, 27:22); - s(EmcPmacroTxPwrd2, 26:23, scratch152, 31:28); - s(EmcMrsWaitCnt2, 9:0, scratch153, 9:0); - s(EmcMrsWaitCnt2, 26:16, scratch153, 20:10); - s(EmcPmacroIbRxrt, 10:0, scratch153, 31:21); - s(EmcMrsWaitCnt, 9:0, scratch154, 9:0); - s(EmcMrsWaitCnt, 26:16, scratch154, 20:10); - s(EmcPmacroDdllLongCmd_4, 10:0, scratch154, 31:21); - s(EmcAutoCalInterval, 20:0, scratch155, 20:0); - s(McEmemArbOutstandingReq, 8:0, scratch155, 29:21); - s(McEmemArbOutstandingReq, 31:30, scratch155, 31:30); - s(McEmemArbRefpbHpCtrl, 6:0, scratch156, 6:0); - s(McEmemArbRefpbHpCtrl, 14:8, scratch156, 13:7); - s(McEmemArbRefpbHpCtrl, 22:16, scratch156, 20:14); - s(EmcCmdBrlshft1, 5:0, scratch156, 26:21); - s(EmcRrd, 4:0, scratch156, 31:27); - s(EmcQuseBrlshft0, 19:0, scratch157, 19:0); - s(EmcFbioCfg8, 27:16, scratch157, 31:20); - s(EmcQuseBrlshft1, 19:0, scratch158, 19:0); - s(EmcTxsrDll, 11:0, scratch158, 31:20); - s(EmcQuseBrlshft2, 19:0, scratch159, 19:0); - s(EmcTxdsrvttgen, 11:0, scratch159, 31:20); - s(EmcQuseBrlshft3, 19:0, scratch160, 19:0); - s(EmcPmacroVttgenCtrl0, 3:0, scratch160, 23:20); - s(EmcPmacroVttgenCtrl0, 11:8, scratch160, 27:24); - s(EmcPmacroVttgenCtrl0, 19:16, scratch160, 31:28); - s(EmcPmacroVttgenCtrl1, 19:0, scratch161, 19:0); - s(EmcCmdBrlshft2, 5:0, scratch161, 25:20); - s(EmcCmdBrlshft3, 5:0, scratch161, 31:26); - s(EmcAutoCalConfig3, 5:0, scratch162, 5:0); - s(EmcAutoCalConfig3, 13:8, scratch162, 11:6); - s(EmcAutoCalConfig3, 18:16, scratch162, 14:12); - s(EmcAutoCalConfig3, 22:20, scratch162, 17:15); - s(EmcTRefBw, 13:0, scratch162, 31:18); - s(EmcAutoCalConfig4, 5:0, scratch163, 5:0); - s(EmcAutoCalConfig4, 13:8, scratch163, 11:6); - s(EmcAutoCalConfig4, 18:16, scratch163, 14:12); - s(EmcAutoCalConfig4, 22:20, scratch163, 17:15); - s(EmcQpop, 6:0, scratch163, 24:18); - s(EmcQpop, 22:16, scratch163, 31:25); - s(EmcAutoCalConfig5, 5:0, scratch164, 5:0); - s(EmcAutoCalConfig5, 13:8, scratch164, 11:6); - s(EmcAutoCalConfig5, 18:16, scratch164, 14:12); - s(EmcAutoCalConfig5, 22:20, scratch164, 17:15); - s(EmcPmacroAutocalCfgCommon, 5:0, scratch164, 23:18); - s(EmcPmacroAutocalCfgCommon, 13:8, scratch164, 29:24); - s(EmcPmacroAutocalCfgCommon, 16:16, scratch164, 30:30); - s(EmcPmacroTxPwrd2, 27:27, scratch164, 31:31); - s(EmcAutoCalConfig6, 5:0, scratch165, 5:0); - s(EmcAutoCalConfig6, 13:8, scratch165, 11:6); - s(EmcAutoCalConfig6, 18:16, scratch165, 14:12); - s(EmcAutoCalConfig6, 22:20, scratch165, 17:15); - s(EmcWev, 5:0, scratch165, 23:18); - s(EmcWsv, 5:0, scratch165, 29:24); - s(EmcPmacroTxPwrd2, 29:28, scratch165, 31:30); - s(EmcAutoCalConfig7, 5:0, scratch166, 5:0); - s(EmcAutoCalConfig7, 13:8, scratch166, 11:6); - s(EmcAutoCalConfig7, 18:16, scratch166, 14:12); - s(EmcAutoCalConfig7, 22:20, scratch166, 17:15); - s(EmcCfg3, 2:0, scratch166, 20:18); - s(EmcCfg3, 6:4, scratch166, 23:21); - s(EmcQuseWidth, 3:0, scratch166, 27:24); - s(EmcQuseWidth, 29:28, scratch166, 29:28); - s(EmcPmacroTxPwrd3, 1:0, scratch166, 31:30); - s(EmcAutoCalConfig8, 5:0, scratch167, 5:0); - s(EmcAutoCalConfig8, 13:8, scratch167, 11:6); - s(EmcAutoCalConfig8, 18:16, scratch167, 14:12); - s(EmcAutoCalConfig8, 22:20, scratch167, 17:15); - s(EmcPmacroBgBiasCtrl0, 2:0, scratch167, 20:18); - s(EmcPmacroBgBiasCtrl0, 6:4, scratch167, 23:21); - s(McEmemArbTimingRcd, 5:0, scratch167, 29:24); - s(EmcPmacroTxPwrd3, 3:2, scratch167, 31:30); - s(EmcXm2CompPadCtrl2, 17:0, scratch168, 17:0); - s(McEmemArbTimingCcdmw, 5:0, scratch168, 23:18); - s(McEmemArbOverride, 27:27, scratch168, 24:24); - s(McEmemArbOverride, 26:26, scratch168, 25:25); - s(McEmemArbOverride, 16:16, scratch168, 26:26); - s(McEmemArbOverride, 10:10, scratch168, 27:27); - s(McEmemArbOverride, 4:4, scratch168, 28:28); - s(McEmemArbOverride, 3:3, scratch168, 29:29); - s(EmcPmacroTxPwrd3, 5:4, scratch168, 31:30); - s(EmcXm2CompPadCtrl3, 17:0, scratch169, 17:0); - s(EmcRext, 4:0, scratch169, 22:18); - s(EmcTClkStop, 4:0, scratch169, 27:23); - s(EmcPmacroTxPwrd3, 9:6, scratch169, 31:28); - s(EmcZcalWaitCnt, 10:0, scratch170, 10:0); - s(EmcZcalWaitCnt, 21:16, scratch170, 16:11); - s(EmcZcalWaitCnt, 31:31, scratch170, 17:17); - s(EmcWext, 4:0, scratch170, 22:18); - s(EmcRefctrl2, 0:0, scratch170, 23:23); - s(EmcRefctrl2, 26:24, scratch170, 26:24); - s(EmcRefctrl2, 31:31, scratch170, 27:27); - s(EmcPmacroTxPwrd3, 13:10, scratch170, 31:28); - s(EmcZcalMrwCmd, 7:0, scratch171, 7:0); - s(EmcZcalMrwCmd, 23:16, scratch171, 15:8); - s(EmcZcalMrwCmd, 31:30, scratch171, 17:16); - s(EmcWeDuration, 4:0, scratch171, 22:18); - s(EmcWsDuration, 4:0, scratch171, 27:23); - s(EmcPmacroTxPwrd3, 19:16, scratch171, 31:28); - s(EmcSwizzleRank0Byte0, 2:0, scratch172, 2:0); - s(EmcSwizzleRank0Byte0, 6:4, scratch172, 5:3); - s(EmcSwizzleRank0Byte0, 10:8, scratch172, 8:6); - s(EmcSwizzleRank0Byte0, 14:12, scratch172, 11:9); - s(EmcSwizzleRank0Byte0, 18:16, scratch172, 14:12); - s(EmcSwizzleRank0Byte0, 22:20, scratch172, 17:15); - s(EmcPutermWidth, 31:31, scratch172, 18:18); - s(EmcPutermWidth, 3:0, scratch172, 22:19); - s(McEmemArbTimingRrd, 4:0, scratch172, 27:23); - s(EmcPmacroTxPwrd3, 23:20, scratch172, 31:28); - s(EmcSwizzleRank0Byte1, 2:0, scratch173, 2:0); - s(EmcSwizzleRank0Byte1, 6:4, scratch173, 5:3); - s(EmcSwizzleRank0Byte1, 10:8, scratch173, 8:6); - s(EmcSwizzleRank0Byte1, 14:12, scratch173, 11:9); - s(EmcSwizzleRank0Byte1, 18:16, scratch173, 14:12); - s(EmcSwizzleRank0Byte1, 22:20, scratch173, 17:15); - s(McEmemArbTimingR2R, 4:0, scratch173, 22:18); - s(McEmemArbTimingW2W, 4:0, scratch173, 27:23); - s(EmcPmacroTxPwrd3, 27:24, scratch173, 31:28); - s(EmcSwizzleRank0Byte2, 2:0, scratch174, 2:0); - s(EmcSwizzleRank0Byte2, 6:4, scratch174, 5:3); - s(EmcSwizzleRank0Byte2, 10:8, scratch174, 8:6); - s(EmcSwizzleRank0Byte2, 14:12, scratch174, 11:9); - s(EmcSwizzleRank0Byte2, 18:16, scratch174, 14:12); - s(EmcSwizzleRank0Byte2, 22:20, scratch174, 17:15); - s(EmcPmacroTxPwrd3, 29:28, scratch174, 19:18); - s(EmcPmacroTxSelClkSrc0, 11:0, scratch174, 31:20); - s(EmcSwizzleRank0Byte3, 2:0, scratch175, 2:0); - s(EmcSwizzleRank0Byte3, 6:4, scratch175, 5:3); - s(EmcSwizzleRank0Byte3, 10:8, scratch175, 8:6); - s(EmcSwizzleRank0Byte3, 14:12, scratch175, 11:9); - s(EmcSwizzleRank0Byte3, 18:16, scratch175, 14:12); - s(EmcSwizzleRank0Byte3, 22:20, scratch175, 17:15); - s(EmcPmacroTxSelClkSrc0, 27:16, scratch175, 29:18); - s(EmcPmacroTxSelClkSrc1, 1:0, scratch175, 31:30); - s(EmcSwizzleRank1Byte0, 2:0, scratch176, 2:0); - s(EmcSwizzleRank1Byte0, 6:4, scratch176, 5:3); - s(EmcSwizzleRank1Byte0, 10:8, scratch176, 8:6); - s(EmcSwizzleRank1Byte0, 14:12, scratch176, 11:9); - s(EmcSwizzleRank1Byte0, 18:16, scratch176, 14:12); - s(EmcSwizzleRank1Byte0, 22:20, scratch176, 17:15); - s(EmcPmacroTxSelClkSrc1, 11:2, scratch176, 27:18); - s(EmcPmacroTxSelClkSrc1, 19:16, scratch176, 31:28); - s(EmcSwizzleRank1Byte1, 2:0, scratch177, 2:0); - s(EmcSwizzleRank1Byte1, 6:4, scratch177, 5:3); - s(EmcSwizzleRank1Byte1, 10:8, scratch177, 8:6); - s(EmcSwizzleRank1Byte1, 14:12, scratch177, 11:9); - s(EmcSwizzleRank1Byte1, 18:16, scratch177, 14:12); - s(EmcSwizzleRank1Byte1, 22:20, scratch177, 17:15); - s(EmcPmacroTxSelClkSrc1, 27:20, scratch177, 25:18); - s(EmcPmacroTxSelClkSrc3, 5:0, scratch177, 31:26); - s(EmcSwizzleRank1Byte2, 2:0, scratch178, 2:0); - s(EmcSwizzleRank1Byte2, 6:4, scratch178, 5:3); - s(EmcSwizzleRank1Byte2, 10:8, scratch178, 8:6); - s(EmcSwizzleRank1Byte2, 14:12, scratch178, 11:9); - s(EmcSwizzleRank1Byte2, 18:16, scratch178, 14:12); - s(EmcSwizzleRank1Byte2, 22:20, scratch178, 17:15); - s(EmcPmacroTxSelClkSrc3, 11:6, scratch178, 23:18); - s(EmcPmacroTxSelClkSrc3, 23:16, scratch178, 31:24); - s(EmcSwizzleRank1Byte3, 2:0, scratch179, 2:0); - s(EmcSwizzleRank1Byte3, 6:4, scratch179, 5:3); - s(EmcSwizzleRank1Byte3, 10:8, scratch179, 8:6); - s(EmcSwizzleRank1Byte3, 14:12, scratch179, 11:9); - s(EmcSwizzleRank1Byte3, 18:16, scratch179, 14:12); - s(EmcSwizzleRank1Byte3, 22:20, scratch179, 17:15); - s(EmcPmacroTxSelClkSrc3, 27:24, scratch179, 21:18); - s(EmcPmacroTxSelClkSrc2, 9:0, scratch179, 31:22); - s(EmcPmacroCmdBrickCtrlFdpd, 17:0, scratch180, 17:0); - s(EmcPmacroTxSelClkSrc2, 11:10, scratch180, 19:18); - s(EmcPmacroTxSelClkSrc2, 27:16, scratch180, 31:20); - s(EmcPmacroDataBrickCtrlFdpd, 17:0, scratch181, 17:0); - s(EmcPmacroTxSelClkSrc4, 11:0, scratch181, 29:18); - s(EmcPmacroTxSelClkSrc4, 17:16, scratch181, 31:30); - s(EmcFbioCfg7, 16:0, scratch182, 16:0); - s(McEmemArbRefpbBankCtrl, 6:0, scratch182, 23:17); - s(McEmemArbRefpbBankCtrl, 14:8, scratch182, 30:24); - s(McEmemArbRefpbBankCtrl, 31:31, scratch182, 31:31); - s(EmcDynSelfRefControl, 15:0, scratch183, 15:0); - s(EmcDynSelfRefControl, 31:31, scratch183, 16:16); - s(EmcPmacroTxSelClkSrc4, 27:18, scratch183, 26:17); - s(EmcPmacroTxSelClkSrc5, 4:0, scratch183, 31:27); - s(EmcDllCfg1, 16:0, scratch184, 16:0); - s(EmcPmacroTxSelClkSrc5, 11:5, scratch184, 23:17); - s(EmcPmacroTxSelClkSrc5, 23:16, scratch184, 31:24); - s(EmcPmacroPadCfgCtrl, 1:0, scratch185, 1:0); - s(EmcPmacroPadCfgCtrl, 6:5, scratch185, 3:2); - s(EmcPmacroPadCfgCtrl, 11:9, scratch185, 6:4); - s(EmcPmacroPadCfgCtrl, 13:13, scratch185, 7:7); - s(EmcPmacroPadCfgCtrl, 17:16, scratch185, 9:8); - s(EmcPmacroPadCfgCtrl, 21:20, scratch185, 11:10); - s(EmcPmacroPadCfgCtrl, 25:24, scratch185, 13:12); - s(EmcPmacroPadCfgCtrl, 30:28, scratch185, 16:14); - s(EmcPmacroTxSelClkSrc5, 27:24, scratch185, 20:17); - s(EmcPmacroCmdPadTxCtrl, 1:0, scratch185, 22:21); - s(EmcPmacroCmdPadTxCtrl, 5:4, scratch185, 24:23); - s(EmcPmacroCmdPadTxCtrl, 9:8, scratch185, 26:25); - s(EmcPmacroCmdPadTxCtrl, 13:12, scratch185, 28:27); - s(EmcPmacroCmdPadTxCtrl, 16:16, scratch185, 29:29); - s(EmcPmacroCmdPadTxCtrl, 21:20, scratch185, 31:30); - s(EmcRefresh, 15:0, scratch186, 15:0); - s(EmcCmdQ, 4:0, scratch186, 20:16); - s(EmcCmdQ, 10:8, scratch186, 23:21); - s(EmcCmdQ, 14:12, scratch186, 26:24); - s(EmcCmdQ, 28:24, scratch186, 31:27); - s(EmcAcpdControl, 15:0, scratch187, 15:0); - s(EmcAutoCalVrefSel1, 15:0, scratch187, 31:16); - s(EmcXm2CompPadCtrl, 1:0, scratch188, 1:0); - s(EmcXm2CompPadCtrl, 6:3, scratch188, 5:2); - s(EmcXm2CompPadCtrl, 9:9, scratch188, 6:6); - s(EmcXm2CompPadCtrl, 19:11, scratch188, 15:7); - s(EmcCfgDigDllPeriod, 15:0, scratch188, 31:16); - s(EmcCfgDigDll_1, 15:0, scratch189, 15:0); - s(EmcPreRefreshReqCnt, 15:0, scratch189, 31:16); - s(EmcPmacroCmdPadTxCtrl, 27:24, scratch190, 19:16); - s(EmcPmacroDataPadTxCtrl, 1:0, scratch190, 21:20); - s(EmcPmacroDataPadTxCtrl, 5:4, scratch190, 23:22); - s(EmcPmacroDataPadTxCtrl, 9:8, scratch190, 25:24); - s(EmcPmacroDataPadTxCtrl, 13:12, scratch190, 27:26); - s(EmcPmacroDataPadTxCtrl, 16:16, scratch190, 28:28); - s(EmcPmacroDataPadTxCtrl, 21:20, scratch190, 30:29); - s(EmcPmacroDataPadTxCtrl, 24:24, scratch190, 31:31); - s(EmcPmacroDataPadTxCtrl, 27:25, scratch191, 2:0); - - s(EmcPinGpio, 1:0, scratch8, 31:30); - s(EmcPinGpioEn, 1:0, scratch9, 31:30); - s(EmcDevSelect, 1:0, scratch10, 31:30); - s(EmcZcalWarmColdBootEnables, 1:0, scratch11, 31:30); - s(EmcCfgDigDllPeriodWarmBoot, 1:0, scratch12, 31:30); - s32(EmcBctSpare13, scratch31); - s32(EmcBctSpare12, scratch32); - s32(EmcBctSpare7, scratch33); - s32(EmcBctSpare6, scratch40); - s32(EmcBctSpare5, scratch42); - s32(EmcBctSpare4, scratch44); - s32(EmcBctSpare3, scratch45); - s32(EmcBctSpare2, scratch46); - s32(EmcBctSpare1, scratch47); - s32(EmcBctSpare0, scratch48); - s32(EmcBctSpare9, scratch50); - s32(EmcBctSpare8, scratch51); - s32(BootRomPatchData, scratch56); - s32(BootRomPatchControl, scratch57); - s(McClkenOverrideAllWarmBoot, 0:0, scratch58, 31:31); - s(EmcClkenOverrideAllWarmBoot, 0:0, scratch59, 30:30); - s(EmcMrsWarmBootEnable, 0:0, scratch59, 31:31); - s(ClearClk2Mc1, 0:0, scratch60, 30:30); - s(EmcWarmBootExtraModeRegWriteEnable, 0:0, scratch60, 31:31); - s(ClkRstControllerPllmMisc2OverrideEnable, 0:0, scratch61, 30:30); - s(EmcDbgWriteMux, 0:0, scratch61, 31:31); - s(EmcExtraRefreshNum, 2:0, scratch62, 31:29); - s(PmcIoDpd3ReqWait, 2:0, scratch68, 30:28); - s(AhbArbitrationXbarCtrlMemInitDone, 0:0, scratch68, 31:31); - s(MemoryType, 2:0, scratch69, 30:28); - s(PmcIoDpd4ReqWait, 2:0, scratch70, 30:28); - s(EmcTimingControlWait, 7:0, scratch86, 31:24); - s(EmcZcalWarmBootWait, 7:0, scratch87, 31:24); - s(WarmBootWait, 7:0, scratch88, 31:24); - s(EmcPinProgramWait, 7:0, scratch89, 31:24); - s(EmcAutoCalWait, 9:0, scratch101, 31:22); - s(SwizzleRankByteEncode, 15:0, scratch190, 15:0); - - switch (sdram->MemoryType) - { - case NvBootMemoryType_LpDdr2: - case NvBootMemoryType_LpDdr4: - s(EmcMrwLpddr2ZcalWarmBoot, 23:16, scratch5, 7:0); - s(EmcMrwLpddr2ZcalWarmBoot, 7:0, scratch5, 15:8); - s(EmcWarmBootMrwExtra, 23:16, scratch5, 23:16); - s(EmcWarmBootMrwExtra, 7:0, scratch5, 31:24); - s(EmcMrwLpddr2ZcalWarmBoot, 31:30, scratch6, 1:0); - s(EmcWarmBootMrwExtra, 31:30, scratch6, 3:2); - s(EmcMrwLpddr2ZcalWarmBoot, 27:26, scratch6, 5:4); - s(EmcWarmBootMrwExtra, 27:26, scratch6, 7:6); - s(EmcMrw6, 27:0, scratch8, 27:0); - s(EmcMrw6, 31:30, scratch8, 29:28); - s(EmcMrw8, 27:0, scratch9, 27:0); - s(EmcMrw8, 31:30, scratch9, 29:28); - s(EmcMrw9, 27:0, scratch10, 27:0); - s(EmcMrw9, 31:30, scratch10, 29:28); - s(EmcMrw10, 27:0, scratch11, 27:0); - s(EmcMrw10, 31:30, scratch11, 29:28); - s(EmcMrw12, 27:0, scratch12, 27:0); - s(EmcMrw12, 31:30, scratch12, 29:28); - s(EmcMrw13, 27:0, scratch13, 27:0); - s(EmcMrw13, 31:30, scratch13, 29:28); - s(EmcMrw14, 27:0, scratch14, 27:0); - s(EmcMrw14, 31:30, scratch14, 29:28); - s(EmcMrw1, 7:0, scratch15, 7:0); - s(EmcMrw1, 23:16, scratch15, 15:8); - s(EmcMrw1, 27:26, scratch15, 17:16); - s(EmcMrw1, 31:30, scratch15, 19:18); - s(EmcWarmBootMrwExtra, 7:0, scratch16, 7:0); - s(EmcWarmBootMrwExtra, 23:16, scratch16, 15:8); - s(EmcWarmBootMrwExtra, 27:26, scratch16, 17:16); - s(EmcWarmBootMrwExtra, 31:30, scratch16, 19:18); - s(EmcMrw2, 7:0, scratch17, 7:0); - s(EmcMrw2, 23:16, scratch17, 15:8); - s(EmcMrw2, 27:26, scratch17, 17:16); - s(EmcMrw2, 31:30, scratch17, 19:18); - s(EmcMrw3, 7:0, scratch18, 7:0); - s(EmcMrw3, 23:16, scratch18, 15:8); - s(EmcMrw3, 27:26, scratch18, 17:16); - s(EmcMrw3, 31:30, scratch18, 19:18); - s(EmcMrw4, 7:0, scratch19, 7:0); - s(EmcMrw4, 23:16, scratch19, 15:8); - s(EmcMrw4, 27:26, scratch19, 17:16); - s(EmcMrw4, 31:30, scratch19, 19:18); - break; - case NvBootMemoryType_Ddr3: - s(EmcMrs, 13:0, scratch5, 13:0); - s(EmcEmrs, 13:0, scratch5, 27:14); - s(EmcMrs, 21:20, scratch5, 29:28); - s(EmcMrs, 31:30, scratch5, 31:30); - s(EmcEmrs2, 13:0, scratch8, 13:0); - s(EmcEmrs3, 13:0, scratch8, 27:14); - s(EmcEmrs, 21:20, scratch8, 29:28); - s(EmcWarmBootMrsExtra, 13:0, scratch9, 13:0); - s(EmcEmrs, 31:30, scratch9, 15:14); - s(EmcEmrs2, 21:20, scratch9, 17:16); - s(EmcEmrs2, 31:30, scratch9, 19:18); - s(EmcEmrs3, 21:20, scratch9, 21:20); - s(EmcEmrs3, 31:30, scratch9, 23:22); - s(EmcWarmBootMrsExtra, 31:30, scratch9, 25:24); - s(EmcWarmBootMrsExtra, 21:20, scratch9, 27:26); - s(EmcZqCalDdr3WarmBoot, 31:30, scratch9, 29:28); - s(EmcMrs, 27:26, scratch10, 1:0); - s(EmcEmrs, 27:26, scratch10, 3:2); - s(EmcEmrs2, 27:26, scratch10, 5:4); - s(EmcEmrs3, 27:26, scratch10, 7:6); - s(EmcWarmBootMrsExtra, 27:27, scratch10, 8:8); - s(EmcWarmBootMrsExtra, 26:26, scratch10, 9:9); - s(EmcZqCalDdr3WarmBoot, 0:0, scratch10, 10:10); - s(EmcZqCalDdr3WarmBoot, 4:4, scratch10, 11:11); - break; - } - - s32(EmcCmdMappingByte, secure_scratch8); - s32(EmcPmacroBrickMapping0, secure_scratch9); - s32(EmcPmacroBrickMapping1, secure_scratch10); - s32(EmcPmacroBrickMapping2, secure_scratch11); - s32(McVideoProtectGpuOverride0, secure_scratch12); - s(EmcCmdMappingCmd0_0, 6:0, secure_scratch13, 6:0); - s(EmcCmdMappingCmd0_0, 14:8, secure_scratch13, 13:7); - s(EmcCmdMappingCmd0_0, 22:16, secure_scratch13, 20:14); - s(EmcCmdMappingCmd0_0, 30:24, secure_scratch13, 27:21); - s(McVideoProtectBomAdrHi, 1:0, secure_scratch13, 29:28); - s(McVideoProtectWriteAccess, 1:0, secure_scratch13, 31:30); - s(EmcCmdMappingCmd0_1, 6:0, secure_scratch14, 6:0); - s(EmcCmdMappingCmd0_1, 14:8, secure_scratch14, 13:7); - s(EmcCmdMappingCmd0_1, 22:16, secure_scratch14, 20:14); - s(EmcCmdMappingCmd0_1, 30:24, secure_scratch14, 27:21); - s(McSecCarveoutAdrHi, 1:0, secure_scratch14, 29:28); - s(McMtsCarveoutAdrHi, 1:0, secure_scratch14, 31:30); - s(EmcCmdMappingCmd1_0, 6:0, secure_scratch15, 6:0); - s(EmcCmdMappingCmd1_0, 14:8, secure_scratch15, 13:7); - s(EmcCmdMappingCmd1_0, 22:16, secure_scratch15, 20:14); - s(EmcCmdMappingCmd1_0, 30:24, secure_scratch15, 27:21); - s(McGeneralizedCarveout5BomHi, 1:0, secure_scratch15, 29:28); - s(McGeneralizedCarveout3BomHi, 1:0, secure_scratch15, 31:30); - s(EmcCmdMappingCmd1_1, 6:0, secure_scratch16, 6:0); - s(EmcCmdMappingCmd1_1, 14:8, secure_scratch16, 13:7); - s(EmcCmdMappingCmd1_1, 22:16, secure_scratch16, 20:14); - s(EmcCmdMappingCmd1_1, 30:24, secure_scratch16, 27:21); - s(McGeneralizedCarveout2BomHi, 1:0, secure_scratch16, 29:28); - s(McGeneralizedCarveout4BomHi, 1:0, secure_scratch16, 31:30); - s(EmcCmdMappingCmd2_0, 6:0, secure_scratch17, 6:0); - s(EmcCmdMappingCmd2_0, 14:8, secure_scratch17, 13:7); - s(EmcCmdMappingCmd2_0, 22:16, secure_scratch17, 20:14); - s(EmcCmdMappingCmd2_0, 30:24, secure_scratch17, 27:21); - s(McGeneralizedCarveout1BomHi, 1:0, secure_scratch17, 29:28); - s(EmcAdrCfg, 0:0, secure_scratch17, 30:30); - s(EmcFbioSpare, 1:1, secure_scratch17, 31:31); - s(EmcCmdMappingCmd2_1, 6:0, secure_scratch18, 6:0); - s(EmcCmdMappingCmd2_1, 14:8, secure_scratch18, 13:7); - s(EmcCmdMappingCmd2_1, 22:16, secure_scratch18, 20:14); - s(EmcCmdMappingCmd2_1, 30:24, secure_scratch18, 27:21); - s(EmcFbioCfg8, 15:15, secure_scratch18, 28:28); - s(McEmemAdrCfg, 0:0, secure_scratch18, 29:29); - s(McSecCarveoutProtectWriteAccess, 0:0, secure_scratch18, 30:30); - s(McMtsCarveoutRegCtrl, 0:0, secure_scratch18, 31:31); - s(EmcCmdMappingCmd3_0, 6:0, secure_scratch19, 6:0); - s(EmcCmdMappingCmd3_0, 14:8, secure_scratch19, 13:7); - s(EmcCmdMappingCmd3_0, 22:16, secure_scratch19, 20:14); - s(EmcCmdMappingCmd3_0, 30:24, secure_scratch19, 27:21); - s(McGeneralizedCarveout2Cfg0, 6:3, secure_scratch19, 31:28); - s(EmcCmdMappingCmd3_1, 6:0, secure_scratch20, 6:0); - s(EmcCmdMappingCmd3_1, 14:8, secure_scratch20, 13:7); - s(EmcCmdMappingCmd3_1, 22:16, secure_scratch20, 20:14); - s(EmcCmdMappingCmd3_1, 30:24, secure_scratch20, 27:21); - s(McGeneralizedCarveout2Cfg0, 10:7, secure_scratch20, 31:28); - s(McGeneralizedCarveout4Cfg0, 26:0, secure_scratch39, 26:0); - s(McGeneralizedCarveout2Cfg0, 17:14, secure_scratch39, 30:27); - s(McVideoProtectVprOverride, 0:0, secure_scratch39, 31:31); - s(McGeneralizedCarveout5Cfg0, 26:0, secure_scratch40, 26:0); - s(McGeneralizedCarveout2Cfg0, 21:18, secure_scratch40, 30:27); - s(McVideoProtectVprOverride, 1:1, secure_scratch40, 31:31); - s(EmcCmdMappingCmd0_2, 6:0, secure_scratch41, 6:0); - s(EmcCmdMappingCmd0_2, 14:8, secure_scratch41, 13:7); - s(EmcCmdMappingCmd0_2, 22:16, secure_scratch41, 20:14); - s(EmcCmdMappingCmd0_2, 27:24, secure_scratch41, 24:21); - s(McGeneralizedCarveout1Cfg0, 6:3, secure_scratch41, 28:25); - s(McGeneralizedCarveout2Cfg0, 13:11, secure_scratch41, 31:29); - s(EmcCmdMappingCmd1_2, 6:0, secure_scratch42, 6:0); - s(EmcCmdMappingCmd1_2, 14:8, secure_scratch42, 13:7); - s(EmcCmdMappingCmd1_2, 22:16, secure_scratch42, 20:14); - s(EmcCmdMappingCmd1_2, 27:24, secure_scratch42, 24:21); - s(McGeneralizedCarveout1Cfg0, 13:7, secure_scratch42, 31:25); - s(EmcCmdMappingCmd2_2, 6:0, secure_scratch43, 6:0); - s(EmcCmdMappingCmd2_2, 14:8, secure_scratch43, 13:7); - s(EmcCmdMappingCmd2_2, 22:16, secure_scratch43, 20:14); - s(EmcCmdMappingCmd2_2, 27:24, secure_scratch43, 24:21); - s(McGeneralizedCarveout1Cfg0, 17:14, secure_scratch43, 28:25); - s(McGeneralizedCarveout3Cfg0, 13:11, secure_scratch43, 31:29); - s(EmcCmdMappingCmd3_2, 6:0, secure_scratch44, 6:0); - s(EmcCmdMappingCmd3_2, 14:8, secure_scratch44, 13:7); - s(EmcCmdMappingCmd3_2, 22:16, secure_scratch44, 20:14); - s(EmcCmdMappingCmd3_2, 27:24, secure_scratch44, 24:21); - s(McGeneralizedCarveout1Cfg0, 21:18, secure_scratch44, 28:25); - s(McVideoProtectVprOverride, 3:2, secure_scratch44, 30:29); - s(McVideoProtectVprOverride, 6:6, secure_scratch44, 31:31); - s(McEmemAdrCfgChannelMask, 31:9, secure_scratch45, 22:0); - s(McEmemAdrCfgDev0, 2:0, secure_scratch45, 25:23); - s(McEmemAdrCfgDev0, 9:8, secure_scratch45, 27:26); - s(McEmemAdrCfgDev0, 19:16, secure_scratch45, 31:28); - s(McEmemAdrCfgBankMask0, 31:10, secure_scratch46, 21:0); - s(McEmemAdrCfgDev1, 2:0, secure_scratch46, 24:22); - s(McEmemAdrCfgDev1, 9:8, secure_scratch46, 26:25); - s(McEmemAdrCfgDev1, 19:16, secure_scratch46, 30:27); - s(McVideoProtectVprOverride, 7:7, secure_scratch46, 31:31); - s(McEmemAdrCfgBankMask1, 31:10, secure_scratch47, 21:0); - s(McGeneralizedCarveout3Cfg0, 10:3, secure_scratch47, 29:22); - s(McVideoProtectVprOverride, 9:8, secure_scratch47, 31:30); - s(McEmemAdrCfgBankMask2, 31:10, secure_scratch48, 21:0); - s(McGeneralizedCarveout3Cfg0, 21:14, secure_scratch48, 29:22); - s(McVideoProtectVprOverride, 11:11, secure_scratch48, 30:30); - s(McVideoProtectVprOverride, 14:14, secure_scratch48, 31:31); - s(McVideoProtectGpuOverride1, 15:0, secure_scratch49, 15:0); - s(McEmemCfg, 13:0, secure_scratch49, 29:16); - s(McEmemCfg, 31:31, secure_scratch49, 30:30); - s(McVideoProtectVprOverride, 15:15, secure_scratch49, 31:31); - s(McGeneralizedCarveout3Bom, 31:17, secure_scratch50, 14:0); - s(McGeneralizedCarveout1Bom, 31:17, secure_scratch50, 29:15); - s(McVideoProtectVprOverride, 18:17, secure_scratch50, 31:30); - s(McGeneralizedCarveout4Bom, 31:17, secure_scratch51, 14:0); - s(McGeneralizedCarveout2Bom, 31:17, secure_scratch51, 29:15); - s(McVideoProtectVprOverride, 20:19, secure_scratch51, 31:30); - s(McGeneralizedCarveout5Bom, 31:17, secure_scratch52, 14:0); - s(McVideoProtectBom, 31:20, secure_scratch52, 26:15); - s(McVideoProtectVprOverride, 23:21, secure_scratch52, 29:27); - s(McVideoProtectVprOverride, 26:26, secure_scratch52, 30:30); - s(McVideoProtectVprOverride, 29:29, secure_scratch52, 31:31); - s(McVideoProtectSizeMb, 11:0, secure_scratch53, 11:0); - s(McSecCarveoutBom, 31:20, secure_scratch53, 23:12); - s(McVideoProtectVprOverride, 31:30, secure_scratch53, 25:24); - s(McVideoProtectVprOverride1, 1:0, secure_scratch53, 27:26); - s(McVideoProtectVprOverride1, 7:4, secure_scratch53, 31:28); - s(McSecCarveoutSizeMb, 11:0, secure_scratch54, 11:0); - s(McMtsCarveoutBom, 31:20, secure_scratch54, 23:12); - s(McVideoProtectVprOverride1, 15:8, secure_scratch54, 31:24); - s(McMtsCarveoutSizeMb, 11:0, secure_scratch55, 11:0); - s(McGeneralizedCarveout4Size128kb, 11:0, secure_scratch55, 23:12); - s(McVideoProtectVprOverride1, 16:16, secure_scratch55, 24:24); - s(McGeneralizedCarveout2Cfg0, 2:0, secure_scratch55, 27:25); - s(McGeneralizedCarveout2Cfg0, 25:22, secure_scratch55, 31:28); - s(McGeneralizedCarveout3Size128kb, 11:0, secure_scratch56, 11:0); - s(McGeneralizedCarveout2Size128kb, 11:0, secure_scratch56, 23:12); - s(McGeneralizedCarveout2Cfg0, 26:26, secure_scratch56, 24:24); - s(McGeneralizedCarveout1Cfg0, 2:0, secure_scratch56, 27:25); - s(McGeneralizedCarveout1Cfg0, 25:22, secure_scratch56, 31:28); - s(McGeneralizedCarveout1Size128kb, 11:0, secure_scratch57, 11:0); - s(McGeneralizedCarveout5Size128kb, 11:0, secure_scratch57, 23:12); - s(McGeneralizedCarveout1Cfg0, 26:26, secure_scratch57, 24:24); - s(McGeneralizedCarveout3Cfg0, 2:0, secure_scratch57, 27:25); - s(McGeneralizedCarveout3Cfg0, 25:22, secure_scratch57, 31:28); - s(McGeneralizedCarveout3Cfg0, 26:26, secure_scratch58, 0:0); - - s32(McGeneralizedCarveout1Access0, secure_scratch59); - s32(McGeneralizedCarveout1Access1, secure_scratch60); - s32(McGeneralizedCarveout1Access2, secure_scratch61); - s32(McGeneralizedCarveout1Access3, secure_scratch62); - s32(McGeneralizedCarveout1Access4, secure_scratch63); - s32(McGeneralizedCarveout2Access0, secure_scratch64); - s32(McGeneralizedCarveout2Access1, secure_scratch65); - s32(McGeneralizedCarveout2Access2, secure_scratch66); - s32(McGeneralizedCarveout2Access3, secure_scratch67); - s32(McGeneralizedCarveout2Access4, secure_scratch68); - s32(McGeneralizedCarveout3Access0, secure_scratch69); - s32(McGeneralizedCarveout3Access1, secure_scratch70); - s32(McGeneralizedCarveout3Access2, secure_scratch71); - s32(McGeneralizedCarveout3Access3, secure_scratch72); - s32(McGeneralizedCarveout3Access4, secure_scratch73); - s32(McGeneralizedCarveout4Access0, secure_scratch74); - s32(McGeneralizedCarveout4Access1, secure_scratch75); - s32(McGeneralizedCarveout4Access2, secure_scratch76); - s32(McGeneralizedCarveout4Access3, secure_scratch77); - s32(McGeneralizedCarveout4Access4, secure_scratch78); - s32(McGeneralizedCarveout5Access0, secure_scratch79); - s32(McGeneralizedCarveout5Access1, secure_scratch80); - s32(McGeneralizedCarveout5Access2, secure_scratch81); - s32(McGeneralizedCarveout5Access3, secure_scratch82); - s32(McGeneralizedCarveout1ForceInternalAccess0, secure_scratch84); - s32(McGeneralizedCarveout1ForceInternalAccess1, secure_scratch85); - s32(McGeneralizedCarveout1ForceInternalAccess2, secure_scratch86); - s32(McGeneralizedCarveout1ForceInternalAccess3, secure_scratch87); - s32(McGeneralizedCarveout1ForceInternalAccess4, secure_scratch88); - s32(McGeneralizedCarveout2ForceInternalAccess0, secure_scratch89); - s32(McGeneralizedCarveout2ForceInternalAccess1, secure_scratch90); - s32(McGeneralizedCarveout2ForceInternalAccess2, secure_scratch91); - s32(McGeneralizedCarveout2ForceInternalAccess3, secure_scratch92); - s32(McGeneralizedCarveout2ForceInternalAccess4, secure_scratch93); - s32(McGeneralizedCarveout3ForceInternalAccess0, secure_scratch94); - s32(McGeneralizedCarveout3ForceInternalAccess1, secure_scratch95); - s32(McGeneralizedCarveout3ForceInternalAccess2, secure_scratch96); - s32(McGeneralizedCarveout3ForceInternalAccess3, secure_scratch97); - s32(McGeneralizedCarveout3ForceInternalAccess4, secure_scratch98); - s32(McGeneralizedCarveout4ForceInternalAccess0, secure_scratch99); - s32(McGeneralizedCarveout4ForceInternalAccess1, secure_scratch100); - s32(McGeneralizedCarveout4ForceInternalAccess2, secure_scratch101); - s32(McGeneralizedCarveout4ForceInternalAccess3, secure_scratch102); - s32(McGeneralizedCarveout4ForceInternalAccess4, secure_scratch103); - s32(McGeneralizedCarveout5ForceInternalAccess0, secure_scratch104); - s32(McGeneralizedCarveout5ForceInternalAccess1, secure_scratch105); - s32(McGeneralizedCarveout5ForceInternalAccess2, secure_scratch106); - s32(McGeneralizedCarveout5ForceInternalAccess3, secure_scratch107); - - c32(0, scratch2); - s(PllMInputDivider, 7:0, scratch2, 7:0); - s(PllMFeedbackDivider, 7:0, scratch2, 15:8); - s(PllMPostDivider, 4:0, scratch2, 20:16); - s(PllMKVCO, 0:0, scratch2, 21:21); - s(PllMKCP, 1:0, scratch2, 23:22); - - c32(0, scratch35); - s(PllMSetupControl, 15:0, scratch35, 15:0); - - c32(0, scratch3); - s(PllMInputDivider, 7:0, scratch3, 7:0); - c(0x3e, scratch3, 15:8); - c(0, scratch3, 20:16); - s(PllMKVCO, 0:0, scratch3, 21:21); - s(PllMKCP, 1:0, scratch3, 23:22); - - c32(0, scratch36); - s(PllMSetupControl, 23:0, scratch36, 23:0); - - c32(0, scratch4); - s(PllMStableTime, 9:0, scratch4, 9:0); -} - -#pragma GCC diagnostic ignored "-Wparentheses" - -static void _sdram_lp0_save_params_t210b01(const void *params) -{ - struct sdram_params_t210b01 *sdram = (struct sdram_params_t210b01 *)params; - struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs *)PMC_BASE; - - u32 tmp = 0; - - sdram->mc_generalized_carveout1_cfg0 = 0; - sdram->mc_generalized_carveout2_cfg0 = 0; - sdram->mc_generalized_carveout3_cfg0 = 0; - sdram->mc_generalized_carveout4_cfg0 = 0; - sdram->mc_generalized_carveout5_cfg0 = 0; - - // Patch SDRAM parameters. - u32 t0 = sdram->emc_swizzle_rank0_byte0 << 5 >> 29 > sdram->emc_swizzle_rank0_byte0 << 1 >> 29; - u32 t1 = (t0 & 0xFFFFFFEF) | ((sdram->emc_swizzle_rank1_byte0 << 5 >> 29 > sdram->emc_swizzle_rank1_byte0 << 1 >> 29) << 4); - u32 t2 = (t1 & 0xFFFFFFFD) | ((sdram->emc_swizzle_rank0_byte1 << 5 >> 29 > sdram->emc_swizzle_rank0_byte1 << 1 >> 29) << 1); - u32 t3 = (t2 & 0xFFFFFFDF) | ((sdram->emc_swizzle_rank1_byte1 << 5 >> 29 > sdram->emc_swizzle_rank1_byte1 << 1 >> 29) << 5); - u32 t4 = (t3 & 0xFFFFFFFB) | ((sdram->emc_swizzle_rank0_byte2 << 5 >> 29 > sdram->emc_swizzle_rank0_byte2 << 1 >> 29) << 2); - u32 t5 = (t4 & 0xFFFFFFBF) | ((sdram->emc_swizzle_rank1_byte2 << 5 >> 29 > sdram->emc_swizzle_rank1_byte2 << 1 >> 29) << 6); - u32 t6 = (t5 & 0xFFFFFFF7) | ((sdram->emc_swizzle_rank0_byte3 << 5 >> 29 > sdram->emc_swizzle_rank0_byte3 << 1 >> 29) << 3); - u32 t7 = (t6 & 0xFFFFFF7F) | ((sdram->emc_swizzle_rank1_byte3 << 5 >> 29 > sdram->emc_swizzle_rank1_byte3 << 1 >> 29) << 7); - sdram->swizzle_rank_byte_encode = t7; - sdram->emc_bct_spare2 = 0x40000DD8; - sdram->emc_bct_spare3 = t7; - - s(emc_clock_source, 7:0, scratch6, 15:8); - s(emc_clock_source_dll, 7:0, scratch6, 23:16); - s(emc_clock_source, 31:29, scratch6, 26:24); - s(emc_clock_source_dll, 31:29, scratch6, 29:27); - s(emc_clock_source_dll, 11:10, scratch6, 31:30); - pmc->scratch7 = (sdram->emc_rc << 24) | ((sdram->emc_zqcal_lpddr4_warm_boot << 27 >> 31 << 23) | ((sdram->emc_zqcal_lpddr4_warm_boot << 30 >> 31 << 22) | ((sdram->emc_zqcal_lpddr4_warm_boot << 21) & 0x3FFFFF | ((sdram->clk_rst_pllm_misc20_override << 20) & 0x1FFFFF | ((sdram->clk_rst_pllm_misc20_override << 28 >> 31 << 19) | ((sdram->clk_rst_pllm_misc20_override << 27 >> 31 << 18) | ((sdram->clk_rst_pllm_misc20_override << 26 >> 31 << 17) | ((sdram->clk_rst_pllm_misc20_override << 21 >> 31 << 16) | ((sdram->clk_rst_pllm_misc20_override << 20 >> 31 << 15) | ((sdram->clk_rst_pllm_misc20_override << 19 >> 31 << 14) | ((sdram->clk_rst_pllm_misc20_override << 18 >> 31 << 13) | ((sdram->emc_clock_source << 15 >> 31 << 12) | ((sdram->emc_clock_source << 11 >> 31 << 11) | ((sdram->emc_clock_source << 12 >> 31 << 10) | ((sdram->emc_clock_source << 6 >> 31 << 9) | ((sdram->emc_clock_source << 16 >> 31 << 8) | ((32 * sdram->emc_clock_source >> 31 << 7) | ((16 * sdram->emc_clock_source >> 31 << 6) | (16 * (sdram->emc_zqcal_lpddr4_warm_boot >> 30) | (4 * (sdram->clk_rst_pllm_misc20_override << 29 >> 30) | ((sdram->clk_rst_pllm_misc20_override << 22 >> 30) | 4 * (pmc->scratch7 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFFFFFF; - pmc->scratch8 = (sdram->emc_pmacro_bg_bias_ctrl0 << 18 >> 30 << 30) | ((4 * pmc->scratch8) >> 2); - pmc->scratch14 = ((u8)(sdram->emc_cfg_pipe_clk) << 31) | (2 * (((u8)(sdram->emc_fdpd_ctrl_cmd_no_ramp) << 30) | pmc->scratch14 & 0xBFFFFFFF) >> 1); - s(emc_qrst, 6:0, scratch15, 26:20); - s(emc_qrst, 20:16, scratch15, 31:27); - s(emc_pmacro_cmd_tx_drive, 5:0, scratch16, 25:20); - s(emc_pmacro_cmd_tx_drive, 13:8, scratch16, 31:26); - pmc->scratch17 = (16 * sdram->emc_fbio_cfg8 >> 31 << 31) | (2 * ((32 * sdram->emc_fbio_cfg8 >> 31 << 30) | ((sdram->emc_fbio_cfg8 << 6 >> 31 << 29) | ((sdram->emc_fbio_cfg8 << 7 >> 31 << 28) | ((sdram->emc_fbio_cfg8 << 8 >> 31 << 27) | ((sdram->emc_fbio_cfg8 << 9 >> 31 << 26) | ((sdram->emc_fbio_cfg8 << 10 >> 31 << 25) | ((sdram->emc_fbio_cfg8 << 11 >> 31 << 24) | ((sdram->emc_fbio_cfg8 << 12 >> 31 << 23) | ((sdram->emc_fbio_cfg8 << 13 >> 31 << 22) | ((sdram->emc_fbio_cfg8 << 14 >> 31 << 21) | ((sdram->emc_fbio_cfg8 << 15 >> 31 << 20) | pmc->scratch17 & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch18 = ((u16)(sdram->emc_txsr_dll) << 20) | pmc->scratch18 & 0xFFFFF; - pmc->scratch19 = (sdram->emc_txdsrvttgen << 20) | pmc->scratch19 & 0xFFFFF; - s32(emc_cfg_rsv, scratch22); - s32(emc_auto_cal_config, scratch23); - s32(emc_auto_cal_vref_sel0, scratch24); - s32(emc_pmacro_brick_ctrl_rfu1, scratch25); - s32(emc_pmacro_brick_ctrl_rfu2, scratch26); - s32(emc_pmc_scratch1, scratch27); - s32(emc_pmc_scratch2, scratch28); - s32(emc_pmc_scratch3, scratch29); - pmc->scratch30 = (sdram->emc_pmacro_perbit_rfu_ctrl0 >> 30 << 30) | (4 * ((4 * sdram->emc_pmacro_perbit_rfu_ctrl0 >> 30 << 28) | ((16 * sdram->emc_pmacro_perbit_rfu_ctrl0 >> 30 << 26) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 6 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 8 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 10 >> 30 << 20) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 12 >> 30 << 18) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 14 >> 30 << 16) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 16 >> 30 << 14) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 18 >> 30 << 12) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 20 >> 30 << 10) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 22 >> 30 << 8) | ((sdram->emc_pmacro_perbit_rfu_ctrl0 << 24 >> 30 << 6) | (16 * (sdram->emc_pmacro_perbit_rfu_ctrl0 << 26 >> 30) | (4 * (sdram->emc_pmacro_perbit_rfu_ctrl0 << 28 >> 30) | (sdram->emc_pmacro_perbit_rfu_ctrl0 & 3 | 4 * (pmc->scratch30 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xCFFFFFFF) >> 2); - pmc->scratch31 = (sdram->emc_pmacro_perbit_rfu_ctrl1 >> 30 << 30) | (4 * ((4 * sdram->emc_pmacro_perbit_rfu_ctrl1 >> 30 << 28) | ((16 * sdram->emc_pmacro_perbit_rfu_ctrl1 >> 30 << 26) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 6 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 8 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 10 >> 30 << 20) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 12 >> 30 << 18) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 14 >> 30 << 16) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 16 >> 30 << 14) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 18 >> 30 << 12) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 20 >> 30 << 10) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 22 >> 30 << 8) | ((sdram->emc_pmacro_perbit_rfu_ctrl1 << 24 >> 30 << 6) | (16 * (sdram->emc_pmacro_perbit_rfu_ctrl1 << 26 >> 30) | (4 * (sdram->emc_pmacro_perbit_rfu_ctrl1 << 28 >> 30) | (sdram->emc_pmacro_perbit_rfu_ctrl1 & 3 | 4 * (pmc->scratch31 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xCFFFFFFF) >> 2); - pmc->scratch32 = (sdram->emc_pmacro_perbit_rfu_ctrl2 >> 30 << 30) | (4 * ((4 * sdram->emc_pmacro_perbit_rfu_ctrl2 >> 30 << 28) | ((16 * sdram->emc_pmacro_perbit_rfu_ctrl2 >> 30 << 26) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 6 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 8 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 10 >> 30 << 20) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 12 >> 30 << 18) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 14 >> 30 << 16) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 16 >> 30 << 14) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 18 >> 30 << 12) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 20 >> 30 << 10) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 22 >> 30 << 8) | ((sdram->emc_pmacro_perbit_rfu_ctrl2 << 24 >> 30 << 6) | (16 * (sdram->emc_pmacro_perbit_rfu_ctrl2 << 26 >> 30) | (4 * (sdram->emc_pmacro_perbit_rfu_ctrl2 << 28 >> 30) | (sdram->emc_pmacro_perbit_rfu_ctrl2 & 3 | 4 * (pmc->scratch32 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xCFFFFFFF) >> 2); - pmc->scratch33 = (sdram->emc_pmacro_perbit_rfu_ctrl3 >> 30 << 30) | (4 * ((4 * sdram->emc_pmacro_perbit_rfu_ctrl3 >> 30 << 28) | ((16 * sdram->emc_pmacro_perbit_rfu_ctrl3 >> 30 << 26) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 6 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 8 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 10 >> 30 << 20) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 12 >> 30 << 18) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 14 >> 30 << 16) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 16 >> 30 << 14) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 18 >> 30 << 12) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 20 >> 30 << 10) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 22 >> 30 << 8) | ((sdram->emc_pmacro_perbit_rfu_ctrl3 << 24 >> 30 << 6) | (16 * (sdram->emc_pmacro_perbit_rfu_ctrl3 << 26 >> 30) | (4 * (sdram->emc_pmacro_perbit_rfu_ctrl3 << 28 >> 30) | (sdram->emc_pmacro_perbit_rfu_ctrl3 & 3 | 4 * (pmc->scratch33 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xCFFFFFFF) >> 2); - pmc->scratch40 = (sdram->emc_pmacro_perbit_rfu_ctrl4 >> 30 << 30) | (4 * ((4 * sdram->emc_pmacro_perbit_rfu_ctrl4 >> 30 << 28) | ((16 * sdram->emc_pmacro_perbit_rfu_ctrl4 >> 30 << 26) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 6 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 8 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 10 >> 30 << 20) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 12 >> 30 << 18) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 14 >> 30 << 16) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 16 >> 30 << 14) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 18 >> 30 << 12) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 20 >> 30 << 10) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 22 >> 30 << 8) | ((sdram->emc_pmacro_perbit_rfu_ctrl4 << 24 >> 30 << 6) | (16 * (sdram->emc_pmacro_perbit_rfu_ctrl4 << 26 >> 30) | (4 * (sdram->emc_pmacro_perbit_rfu_ctrl4 << 28 >> 30) | (sdram->emc_pmacro_perbit_rfu_ctrl4 & 3 | 4 * (pmc->scratch40 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xCFFFFFFF) >> 2); - pmc->scratch42 = (sdram->emc_pmacro_perbit_rfu_ctrl5 >> 30 << 30) | (4 * ((4 * sdram->emc_pmacro_perbit_rfu_ctrl5 >> 30 << 28) | ((16 * sdram->emc_pmacro_perbit_rfu_ctrl5 >> 30 << 26) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 6 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 8 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 10 >> 30 << 20) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 12 >> 30 << 18) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 14 >> 30 << 16) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 16 >> 30 << 14) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 18 >> 30 << 12) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 20 >> 30 << 10) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 22 >> 30 << 8) | ((sdram->emc_pmacro_perbit_rfu_ctrl5 << 24 >> 30 << 6) | (16 * (sdram->emc_pmacro_perbit_rfu_ctrl5 << 26 >> 30) | (4 * (sdram->emc_pmacro_perbit_rfu_ctrl5 << 28 >> 30) | (sdram->emc_pmacro_perbit_rfu_ctrl5 & 3 | 4 * (pmc->scratch42 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xCFFFFFFF) >> 2); - pmc->scratch44 = (sdram->mc_emem_arb_da_turns >> 24 << 24) | ((sdram->mc_emem_arb_da_turns >> 16 << 16) | ((sdram->mc_emem_arb_da_turns << 16 >> 24 << 8) | (sdram->mc_emem_arb_da_turns & 0xFF | (pmc->scratch44 >> 8 << 8)) & 0xFFFF00FF) & 0xFF00FFFF) & 0xFFFFFF; - pmc->scratch64 = ((u16)(sdram->mc_emem_arb_misc2) << 31) | (2 * ((sdram->emc_fbio_spare << 30) | ((sdram->emc_fbio_spare << 24 >> 26 << 24) | ((sdram->emc_fbio_spare << 16 >> 24 << 16) | ((sdram->emc_fbio_spare << 8 >> 24 << 8) | ((sdram->emc_fbio_spare >> 24) | (pmc->scratch64 >> 8 << 8)) & 0xFFFF00FF) & 0xFF00FFFF) & 0xC0FFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch65 = ((u16)(sdram->mc_da_cfg0) << 31 >> 1) | ((2 * sdram->mc_emem_arb_misc0 >> 29 << 27) | ((16 * sdram->mc_emem_arb_misc0 >> 31 << 26) | ((32 * sdram->mc_emem_arb_misc0 >> 26 << 20) | ((sdram->mc_emem_arb_misc0 << 11 >> 27 << 15) | ((sdram->mc_emem_arb_misc0 << 17 >> 25 << 8) | ((u8)sdram->mc_emem_arb_misc0 | (pmc->scratch65 >> 8 << 8)) & 0xFFFF80FF) & 0xFFF07FFF) & 0xFC0FFFFF) & 0xFBFFFFFF) & 0xC7FFFFFF) & 0xBFFFFFFF; - pmc->scratch66 = (sdram->emc_fdpd_ctrl_cmd >> 30 << 27) | ((4 * sdram->emc_fdpd_ctrl_cmd >> 31 << 26) | ((8 * sdram->emc_fdpd_ctrl_cmd >> 27 << 21) | ((sdram->emc_fdpd_ctrl_cmd << 8 >> 28 << 17) | ((sdram->emc_fdpd_ctrl_cmd << 15 >> 27 << 12) | ((sdram->emc_fdpd_ctrl_cmd << 20 >> 28 << 8) | ((u8)sdram->emc_fdpd_ctrl_cmd | (pmc->scratch66 >> 8 << 8)) & 0xFFFFF0FF) & 0xFFFE0FFF) & 0xFFE1FFFF) & 0xFC1FFFFF) & 0xFBFFFFFF) & 0xE7FFFFFF; - pmc->scratch67 = ((u8)(sdram->emc_burst_refresh_num) << 28) | ((16 * sdram->emc_auto_cal_config2 >> 30 << 26) | ((sdram->emc_auto_cal_config2 << 6 >> 30 << 24) | ((sdram->emc_auto_cal_config2 << 8 >> 30 << 22) | ((sdram->emc_auto_cal_config2 << 10 >> 30 << 20) | ((sdram->emc_auto_cal_config2 << 12 >> 30 << 18) | ((sdram->emc_auto_cal_config2 << 14 >> 30 << 16) | ((sdram->emc_auto_cal_config2 << 16 >> 30 << 14) | ((sdram->emc_auto_cal_config2 << 18 >> 30 << 12) | ((sdram->emc_auto_cal_config2 << 20 >> 30 << 10) | ((sdram->emc_auto_cal_config2 << 22 >> 30 << 8) | ((sdram->emc_auto_cal_config2 << 24 >> 30 << 6) | (16 * (sdram->emc_auto_cal_config2 << 26 >> 30) | (4 * (sdram->emc_auto_cal_config2 << 28 >> 30) | (sdram->emc_auto_cal_config2 & 3 | 4 * (pmc->scratch67 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xFFFFFFF; - pmc->scratch68 = ((u8)(sdram->emc_tppd) << 28) | ((sdram->emc_cfg_dig_dll >> 31 << 27) | ((2 * sdram->emc_cfg_dig_dll >> 31 << 26) | ((16 * sdram->emc_cfg_dig_dll >> 31 << 25) | ((sdram->emc_cfg_dig_dll << 6 >> 22 << 15) | ((sdram->emc_cfg_dig_dll << 16 >> 31 << 14) | ((sdram->emc_cfg_dig_dll << 17 >> 31 << 13) | ((sdram->emc_cfg_dig_dll << 18 >> 30 << 11) | ((sdram->emc_cfg_dig_dll << 21 >> 29 << 8) | ((sdram->emc_cfg_dig_dll << 24 >> 30 << 6) | (32 * (sdram->emc_cfg_dig_dll << 26 >> 31) | (16 * (sdram->emc_cfg_dig_dll << 27 >> 31) | (8 * (sdram->emc_cfg_dig_dll << 28 >> 31) | (4 * (sdram->emc_cfg_dig_dll << 29 >> 31) | (2 * (sdram->emc_cfg_dig_dll << 30 >> 31) | (sdram->emc_cfg_dig_dll & 1 | 2 * (pmc->scratch68 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFF3F) & 0xFFFFF8FF) & 0xFFFFE7FF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFE007FFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xFFFFFFF; - pmc->scratch69 = (sdram->emc_r2r << 28) | ((sdram->emc_fdpd_ctrl_dq >> 30 << 26) | ((8 * sdram->emc_fdpd_ctrl_dq >> 27 << 21) | ((sdram->emc_fdpd_ctrl_dq << 8 >> 28 << 17) | ((sdram->emc_fdpd_ctrl_dq << 15 >> 27 << 12) | ((sdram->emc_fdpd_ctrl_dq << 20 >> 28 << 8) | ((u8)sdram->emc_fdpd_ctrl_dq | (pmc->scratch69 >> 8 << 8)) & 0xFFFFF0FF) & 0xFFFE0FFF) & 0xFFE1FFFF) & 0xFC1FFFFF) & 0xF3FFFFFF) & 0xFFFFFFF; - pmc->scratch70 = (sdram->emc_w2w << 28) | ((2 * sdram->emc_pmacro_ib_vref_dq_0 >> 25 << 21) | ((sdram->emc_pmacro_ib_vref_dq_0 << 9 >> 25 << 14) | ((sdram->emc_pmacro_ib_vref_dq_0 << 17 >> 25 << 7) | (sdram->emc_pmacro_ib_vref_dq_0 & 0x7F | (pmc->scratch70 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xFFFFFFF; - pmc->scratch71 = (sdram->emc_pmacro_vttgen_ctrl0 << 12 >> 28 << 28) | ((2 * sdram->emc_pmacro_ib_vref_dq_1 >> 25 << 21) | ((sdram->emc_pmacro_ib_vref_dq_1 << 9 >> 25 << 14) | ((sdram->emc_pmacro_ib_vref_dq_1 << 17 >> 25 << 7) | ((pmc->scratch71 >> 7 << 7) | sdram->emc_pmacro_ib_vref_dq_1 & 0x7F) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xFFFFFFF; - pmc->scratch72 = (((sdram->emc_pmacro_ib_vref_dqs_0 << 17 >> 25 << 7) | ((pmc->scratch72 >> 7 << 7) | sdram->emc_pmacro_ib_vref_dqs_0 & 0x7F) & 0xFFFFC07F) & 0xFFE03FFF | (sdram->emc_pmacro_ib_vref_dqs_0 << 9 >> 25 << 14)) & 0xF01FFFFF | (2 * sdram->emc_pmacro_ib_vref_dqs_0 >> 25 << 21); - pmc->scratch73 = (2 * sdram->emc_pmacro_ib_vref_dqs_1 >> 25 << 21) | ((sdram->emc_pmacro_ib_vref_dqs_1 << 9 >> 25 << 14) | ((sdram->emc_pmacro_ib_vref_dqs_1 << 17 >> 25 << 7) | ((pmc->scratch73 >> 7 << 7) | sdram->emc_pmacro_ib_vref_dqs_1 & 0x7F) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF; - pmc->scratch74 = (2 * sdram->emc_pmacro_ddll_short_cmd_0 >> 25 << 21) | ((sdram->emc_pmacro_ddll_short_cmd_0 << 9 >> 25 << 14) | ((sdram->emc_pmacro_ddll_short_cmd_0 << 17 >> 25 << 7) | (sdram->emc_pmacro_ddll_short_cmd_0 & 0x7F | (pmc->scratch74 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF; - pmc->scratch75 = (2 * sdram->emc_pmacro_ddll_short_cmd_1 >> 25 << 21) | ((sdram->emc_pmacro_ddll_short_cmd_1 << 9 >> 25 << 14) | ((sdram->emc_pmacro_ddll_short_cmd_1 << 17 >> 25 << 7) | (sdram->emc_pmacro_ddll_short_cmd_1 & 0x7F | (pmc->scratch75 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF; - pmc->scratch76 = (sdram->emc_rp << 26) | ((4 * sdram->emc_dll_cfg0 >> 31 << 25) | ((8 * sdram->emc_dll_cfg0 >> 31 << 24) | ((16 * sdram->emc_dll_cfg0 >> 28 << 20) | ((sdram->emc_dll_cfg0 << 8 >> 28 << 16) | ((sdram->emc_dll_cfg0 << 12 >> 28 << 12) | ((sdram->emc_dll_cfg0 << 16 >> 28 << 8) | ((sdram->emc_dll_cfg0 << 20 >> 24) | (pmc->scratch76 >> 8 << 8)) & 0xFFFFF0FF) & 0xFFFF0FFF) & 0xFFF0FFFF) & 0xFF0FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0x3FFFFFF; - tmp = (sdram->emc_pmacro_tx_pwrd0 << 12 >> 31 << 16) | ((sdram->emc_pmacro_tx_pwrd0 << 13 >> 31 << 15) | ((sdram->emc_pmacro_tx_pwrd0 << 14 >> 31 << 14) | ((sdram->emc_pmacro_tx_pwrd0 << 15 >> 31 << 13) | ((sdram->emc_pmacro_tx_pwrd0 << 18 >> 31 << 12) | ((sdram->emc_pmacro_tx_pwrd0 << 19 >> 31 << 11) | ((sdram->emc_pmacro_tx_pwrd0 << 21 >> 31 << 10) | ((sdram->emc_pmacro_tx_pwrd0 << 22 >> 31 << 9) | ((sdram->emc_pmacro_tx_pwrd0 << 23 >> 31 << 8) | ((sdram->emc_pmacro_tx_pwrd0 << 24 >> 31 << 7) | ((sdram->emc_pmacro_tx_pwrd0 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_tx_pwrd0 << 26 >> 31) | (16 * (sdram->emc_pmacro_tx_pwrd0 << 27 >> 31) | (8 * (sdram->emc_pmacro_tx_pwrd0 << 28 >> 31) | (4 * (sdram->emc_pmacro_tx_pwrd0 << 29 >> 31) | (2 * (sdram->emc_pmacro_tx_pwrd0 << 30 >> 31) | (sdram->emc_pmacro_tx_pwrd0 & 1 | 2 * (pmc->scratch77 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF; - pmc->scratch77 = (sdram->emc_r2w << 26) | ((4 * sdram->emc_pmacro_tx_pwrd0 >> 31 << 25) | ((8 * sdram->emc_pmacro_tx_pwrd0 >> 31 << 24) | ((32 * sdram->emc_pmacro_tx_pwrd0 >> 31 << 23) | ((sdram->emc_pmacro_tx_pwrd0 << 6 >> 31 << 22) | ((sdram->emc_pmacro_tx_pwrd0 << 7 >> 31 << 21) | ((sdram->emc_pmacro_tx_pwrd0 << 8 >> 31 << 20) | ((sdram->emc_pmacro_tx_pwrd0 << 9 >> 31 << 19) | ((sdram->emc_pmacro_tx_pwrd0 << 10 >> 31 << 18) | ((sdram->emc_pmacro_tx_pwrd0 << 11 >> 31 << 17) | tmp & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0x3FFFFFF; - tmp = ((8 * sdram->emc_pmacro_tx_pwrd1 >> 31 << 24) | ((32 * sdram->emc_pmacro_tx_pwrd1 >> 31 << 23) | ((sdram->emc_pmacro_tx_pwrd1 << 6 >> 31 << 22) | ((sdram->emc_pmacro_tx_pwrd1 << 7 >> 31 << 21) | ((sdram->emc_pmacro_tx_pwrd1 << 8 >> 31 << 20) | ((sdram->emc_pmacro_tx_pwrd1 << 9 >> 31 << 19) | ((sdram->emc_pmacro_tx_pwrd1 << 10 >> 31 << 18) | ((sdram->emc_pmacro_tx_pwrd1 << 11 >> 31 << 17) | ((sdram->emc_pmacro_tx_pwrd1 << 12 >> 31 << 16) | ((sdram->emc_pmacro_tx_pwrd1 << 13 >> 31 << 15) | ((sdram->emc_pmacro_tx_pwrd1 << 14 >> 31 << 14) | ((sdram->emc_pmacro_tx_pwrd1 << 15 >> 31 << 13) | ((sdram->emc_pmacro_tx_pwrd1 << 18 >> 31 << 12) | ((sdram->emc_pmacro_tx_pwrd1 << 19 >> 31 << 11) | ((sdram->emc_pmacro_tx_pwrd1 << 21 >> 31 << 10) | ((sdram->emc_pmacro_tx_pwrd1 << 22 >> 31 << 9) | ((sdram->emc_pmacro_tx_pwrd1 << 23 >> 31 << 8) | ((sdram->emc_pmacro_tx_pwrd1 << 24 >> 31 << 7) | ((sdram->emc_pmacro_tx_pwrd1 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_tx_pwrd1 << 26 >> 31) | (16 * (sdram->emc_pmacro_tx_pwrd1 << 27 >> 31) | (8 * (sdram->emc_pmacro_tx_pwrd1 << 28 >> 31) | (4 * (sdram->emc_pmacro_tx_pwrd1 << 29 >> 31) | (2 * (sdram->emc_pmacro_tx_pwrd1 << 30 >> 31) | (sdram->emc_pmacro_tx_pwrd1 & 1 | 2 * (pmc->scratch78 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF; - pmc->scratch78 = (sdram->emc_w2r << 26) | ((4 * sdram->emc_pmacro_tx_pwrd1 >> 31 << 25) | tmp) & 0x3FFFFFF; - tmp = ((8 * sdram->emc_pmacro_tx_pwrd2 >> 31 << 24) | ((32 * sdram->emc_pmacro_tx_pwrd2 >> 31 << 23) | ((sdram->emc_pmacro_tx_pwrd2 << 6 >> 31 << 22) | ((sdram->emc_pmacro_tx_pwrd2 << 7 >> 31 << 21) | ((sdram->emc_pmacro_tx_pwrd2 << 8 >> 31 << 20) | ((sdram->emc_pmacro_tx_pwrd2 << 9 >> 31 << 19) | ((sdram->emc_pmacro_tx_pwrd2 << 10 >> 31 << 18) | ((sdram->emc_pmacro_tx_pwrd2 << 11 >> 31 << 17) | ((sdram->emc_pmacro_tx_pwrd2 << 12 >> 31 << 16) | ((sdram->emc_pmacro_tx_pwrd2 << 13 >> 31 << 15) | ((sdram->emc_pmacro_tx_pwrd2 << 14 >> 31 << 14) | ((sdram->emc_pmacro_tx_pwrd2 << 15 >> 31 << 13) | ((sdram->emc_pmacro_tx_pwrd2 << 18 >> 31 << 12) | ((sdram->emc_pmacro_tx_pwrd2 << 19 >> 31 << 11) | ((sdram->emc_pmacro_tx_pwrd2 << 21 >> 31 << 10) | ((sdram->emc_pmacro_tx_pwrd2 << 22 >> 31 << 9) | ((sdram->emc_pmacro_tx_pwrd2 << 23 >> 31 << 8) | ((sdram->emc_pmacro_tx_pwrd2 << 24 >> 31 << 7) | ((sdram->emc_pmacro_tx_pwrd2 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_tx_pwrd2 << 26 >> 31) | (16 * (sdram->emc_pmacro_tx_pwrd2 << 27 >> 31) | (8 * (sdram->emc_pmacro_tx_pwrd2 << 28 >> 31) | (4 * (sdram->emc_pmacro_tx_pwrd2 << 29 >> 31) | (2 * (sdram->emc_pmacro_tx_pwrd2 << 30 >> 31) | (sdram->emc_pmacro_tx_pwrd2 & 1 | 2 * (pmc->scratch79 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF; - pmc->scratch79 = (sdram->emc_r2p << 26) | ((4 * sdram->emc_pmacro_tx_pwrd2 >> 31 << 25) | tmp) & 0x3FFFFFF; - tmp = (sdram->emc_pmacro_tx_pwrd3 << 23 >> 31 << 8) | ((sdram->emc_pmacro_tx_pwrd3 << 24 >> 31 << 7) | ((sdram->emc_pmacro_tx_pwrd3 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_tx_pwrd3 << 26 >> 31) | (16 * (sdram->emc_pmacro_tx_pwrd3 << 27 >> 31) | (8 * (sdram->emc_pmacro_tx_pwrd3 << 28 >> 31) | (4 * (sdram->emc_pmacro_tx_pwrd3 << 29 >> 31) | (2 * (sdram->emc_pmacro_tx_pwrd3 << 30 >> 31) | (sdram->emc_pmacro_tx_pwrd3 & 1 | 2 * (pmc->scratch80 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF; - pmc->scratch80 = ((u8)(sdram->emc_ccdmw) << 26) | ((4 * sdram->emc_pmacro_tx_pwrd3 >> 31 << 25) | ((8 * sdram->emc_pmacro_tx_pwrd3 >> 31 << 24) | ((32 * sdram->emc_pmacro_tx_pwrd3 >> 31 << 23) | ((sdram->emc_pmacro_tx_pwrd3 << 6 >> 31 << 22) | ((sdram->emc_pmacro_tx_pwrd3 << 7 >> 31 << 21) | ((sdram->emc_pmacro_tx_pwrd3 << 8 >> 31 << 20) | ((sdram->emc_pmacro_tx_pwrd3 << 9 >> 31 << 19) | ((sdram->emc_pmacro_tx_pwrd3 << 10 >> 31 << 18) | ((sdram->emc_pmacro_tx_pwrd3 << 11 >> 31 << 17) | ((sdram->emc_pmacro_tx_pwrd3 << 12 >> 31 << 16) | ((sdram->emc_pmacro_tx_pwrd3 << 13 >> 31 << 15) | ((sdram->emc_pmacro_tx_pwrd3 << 14 >> 31 << 14) | ((sdram->emc_pmacro_tx_pwrd3 << 15 >> 31 << 13) | ((sdram->emc_pmacro_tx_pwrd3 << 18 >> 31 << 12) | ((sdram->emc_pmacro_tx_pwrd3 << 19 >> 31 << 11) | ((sdram->emc_pmacro_tx_pwrd3 << 21 >> 31 << 10) | ((sdram->emc_pmacro_tx_pwrd3 << 22 >> 31 << 9) | tmp & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0x3FFFFFF; - tmp = ((8 * sdram->emc_pmacro_tx_pwrd4 >> 31 << 24) | ((32 * sdram->emc_pmacro_tx_pwrd4 >> 31 << 23) | ((sdram->emc_pmacro_tx_pwrd4 << 6 >> 31 << 22) | ((sdram->emc_pmacro_tx_pwrd4 << 7 >> 31 << 21) | ((sdram->emc_pmacro_tx_pwrd4 << 8 >> 31 << 20) | ((sdram->emc_pmacro_tx_pwrd4 << 9 >> 31 << 19) | ((sdram->emc_pmacro_tx_pwrd4 << 10 >> 31 << 18) | ((sdram->emc_pmacro_tx_pwrd4 << 11 >> 31 << 17) | ((sdram->emc_pmacro_tx_pwrd4 << 12 >> 31 << 16) | ((sdram->emc_pmacro_tx_pwrd4 << 13 >> 31 << 15) | ((sdram->emc_pmacro_tx_pwrd4 << 14 >> 31 << 14) | ((sdram->emc_pmacro_tx_pwrd4 << 15 >> 31 << 13) | ((sdram->emc_pmacro_tx_pwrd4 << 18 >> 31 << 12) | ((sdram->emc_pmacro_tx_pwrd4 << 19 >> 31 << 11) | ((sdram->emc_pmacro_tx_pwrd4 << 21 >> 31 << 10) | ((sdram->emc_pmacro_tx_pwrd4 << 22 >> 31 << 9) | ((sdram->emc_pmacro_tx_pwrd4 << 23 >> 31 << 8) | ((sdram->emc_pmacro_tx_pwrd4 << 24 >> 31 << 7) | ((sdram->emc_pmacro_tx_pwrd4 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_tx_pwrd4 << 26 >> 31) | (16 * (sdram->emc_pmacro_tx_pwrd4 << 27 >> 31) | (8 * (sdram->emc_pmacro_tx_pwrd4 << 28 >> 31) | (4 * (sdram->emc_pmacro_tx_pwrd4 << 29 >> 31) | (2 * (sdram->emc_pmacro_tx_pwrd4 << 30 >> 31) | (sdram->emc_pmacro_tx_pwrd4 & 1 | 2 * (pmc->scratch81 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF; - pmc->scratch81 = ((u8)(sdram->emc_rd_rcd) << 26) | ((4 * sdram->emc_pmacro_tx_pwrd4 >> 31 << 25) | tmp) & 0x3FFFFFF; - tmp = ((8 * sdram->emc_pmacro_tx_pwrd5 >> 31 << 24) | ((32 * sdram->emc_pmacro_tx_pwrd5 >> 31 << 23) | ((sdram->emc_pmacro_tx_pwrd5 << 6 >> 31 << 22) | ((sdram->emc_pmacro_tx_pwrd5 << 7 >> 31 << 21) | ((sdram->emc_pmacro_tx_pwrd5 << 8 >> 31 << 20) | ((sdram->emc_pmacro_tx_pwrd5 << 9 >> 31 << 19) | ((sdram->emc_pmacro_tx_pwrd5 << 10 >> 31 << 18) | ((sdram->emc_pmacro_tx_pwrd5 << 11 >> 31 << 17) | ((sdram->emc_pmacro_tx_pwrd5 << 12 >> 31 << 16) | ((sdram->emc_pmacro_tx_pwrd5 << 13 >> 31 << 15) | ((sdram->emc_pmacro_tx_pwrd5 << 14 >> 31 << 14) | ((sdram->emc_pmacro_tx_pwrd5 << 15 >> 31 << 13) | ((sdram->emc_pmacro_tx_pwrd5 << 18 >> 31 << 12) | ((sdram->emc_pmacro_tx_pwrd5 << 19 >> 31 << 11) | ((sdram->emc_pmacro_tx_pwrd5 << 21 >> 31 << 10) | ((sdram->emc_pmacro_tx_pwrd5 << 22 >> 31 << 9) | ((sdram->emc_pmacro_tx_pwrd5 << 23 >> 31 << 8) | ((sdram->emc_pmacro_tx_pwrd5 << 24 >> 31 << 7) | ((sdram->emc_pmacro_tx_pwrd5 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_tx_pwrd5 << 26 >> 31) | (16 * (sdram->emc_pmacro_tx_pwrd5 << 27 >> 31) | (8 * (sdram->emc_pmacro_tx_pwrd5 << 28 >> 31) | (4 * (sdram->emc_pmacro_tx_pwrd5 << 29 >> 31) | (2 * (sdram->emc_pmacro_tx_pwrd5 << 30 >> 31) | (sdram->emc_pmacro_tx_pwrd5 & 1 | 2 * (pmc->scratch82 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF; - pmc->scratch82 = ((u16)(sdram->emc_wr_rcd) << 26) | ((4 * sdram->emc_pmacro_tx_pwrd5 >> 31 << 25) | tmp) & 0x3FFFFFF; - pmc->scratch83 = ((u8)(sdram->emc_config_sample_delay) << 25) | ((sdram->emc_auto_cal_channel >> 31 << 24) | ((2 * sdram->emc_auto_cal_channel >> 31 << 23) | ((4 * sdram->emc_auto_cal_channel >> 31 << 22) | ((16 * sdram->emc_auto_cal_channel >> 25 << 15) | ((sdram->emc_auto_cal_channel << 11 >> 27 << 10) | ((sdram->emc_auto_cal_channel << 20 >> 28 << 6) | (sdram->emc_auto_cal_channel & 0x3F | (pmc->scratch83 >> 6 << 6)) & 0xFFFFFC3F) & 0xFFFF83FF) & 0xFFC07FFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0x1FFFFFF; - pmc->scratch84 = (sdram->emc_sel_dpd_ctrl << 13 >> 29 << 29) | ((sdram->emc_sel_dpd_ctrl << 23 >> 31 << 28) | ((sdram->emc_sel_dpd_ctrl << 26 >> 31 << 27) | ((sdram->emc_sel_dpd_ctrl << 27 >> 31 << 26) | ((sdram->emc_sel_dpd_ctrl << 28 >> 31 << 25) | ((sdram->emc_sel_dpd_ctrl << 29 >> 31 << 24) | ((4 * sdram->emc_pmacro_rx_term >> 26 << 18) | ((sdram->emc_pmacro_rx_term << 10 >> 26 << 12) | ((sdram->emc_pmacro_rx_term << 18 >> 26 << 6) | (sdram->emc_pmacro_rx_term & 0x3F | (pmc->scratch84 >> 6 << 6)) & 0xFFFFF03F) & 0xFFFC0FFF) & 0xFF03FFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0x1FFFFFFF; - pmc->scratch85 = (4 * sdram->emc_obdly >> 30 << 30) | (4 * ((sdram->emc_obdly << 24) | ((4 * sdram->emc_pmacro_dq_tx_drive >> 26 << 18) | ((sdram->emc_pmacro_dq_tx_drive << 10 >> 26 << 12) | ((sdram->emc_pmacro_dq_tx_drive << 18 >> 26 << 6) | (sdram->emc_pmacro_dq_tx_drive & 0x3F | (pmc->scratch85 >> 6 << 6)) & 0xFFFFF03F) & 0xFFFC0FFF) & 0xFF03FFFF) & 0xC0FFFFFF) >> 2); - pmc->scratch86 = (sdram->emc_pmacro_vttgen_ctrl1 << 10 >> 30 << 30) | (4 * ((sdram->emc_pmacro_vttgen_ctrl1 << 16 >> 26 << 24) | ((4 * sdram->emc_pmacro_ca_tx_drive >> 26 << 18) | ((sdram->emc_pmacro_ca_tx_drive << 10 >> 26 << 12) | ((sdram->emc_pmacro_ca_tx_drive << 18 >> 26 << 6) | (sdram->emc_pmacro_ca_tx_drive & 0x3F | (pmc->scratch86 >> 6 << 6)) & 0xFFFFF03F) & 0xFFFC0FFF) & 0xFF03FFFF) & 0xC0FFFFFF) >> 2); - pmc->scratch87 = (sdram->emc_pmacro_vttgen_ctrl2 >> 16 << 24) | ((16 * sdram->emc_pmacro_zcrtl >> 30 << 22) | ((sdram->emc_pmacro_zcrtl << 6 >> 30 << 20) | ((sdram->emc_pmacro_zcrtl << 8 >> 30 << 18) | ((sdram->emc_pmacro_zcrtl << 10 >> 30 << 16) | ((sdram->emc_pmacro_zcrtl << 12 >> 30 << 14) | ((sdram->emc_pmacro_zcrtl << 14 >> 30 << 12) | ((sdram->emc_pmacro_zcrtl << 16 >> 30 << 10) | ((sdram->emc_pmacro_zcrtl << 18 >> 30 << 8) | ((sdram->emc_pmacro_zcrtl << 20 >> 30 << 6) | (16 * (sdram->emc_pmacro_zcrtl << 22 >> 30) | (4 * (sdram->emc_pmacro_zcrtl << 24 >> 30) | ((sdram->emc_pmacro_zcrtl << 26 >> 30) | 4 * (pmc->scratch87 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFFFFFF; - pmc->scratch88 = (sdram->mc_emem_arb_timing_rc << 24) | ((sdram->emc_zcal_interval << 14) | ((sdram->emc_zcal_interval << 8 >> 18) | (pmc->scratch88 >> 14 << 14)) & 0xFF003FFF) & 0xFFFFFF; - pmc->scratch89 = ((u16)(sdram->mc_emem_arb_rsv) << 24) | ((sdram->emc_data_brlshft0 << 8 >> 29 << 21) | ((sdram->emc_data_brlshft0 << 11 >> 29 << 18) | ((sdram->emc_data_brlshft0 << 14 >> 29 << 15) | ((sdram->emc_data_brlshft0 << 17 >> 29 << 12) | ((sdram->emc_data_brlshft0 << 20 >> 29 << 9) | ((sdram->emc_data_brlshft0 << 23 >> 29 << 6) | (8 * (sdram->emc_data_brlshft0 << 26 >> 29) | (sdram->emc_data_brlshft0 & 7 | 8 * (pmc->scratch89 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF) & 0xFFFFFF; - pmc->scratch90 = (sdram->emc_data_brlshft1 << 8 >> 29 << 21) | ((sdram->emc_data_brlshft1 << 11 >> 29 << 18) | ((sdram->emc_data_brlshft1 << 14 >> 29 << 15) | ((sdram->emc_data_brlshft1 << 17 >> 29 << 12) | ((sdram->emc_data_brlshft1 << 20 >> 29 << 9) | ((sdram->emc_data_brlshft1 << 23 >> 29 << 6) | (8 * (sdram->emc_data_brlshft1 << 26 >> 29) | (sdram->emc_data_brlshft1 & 7 | 8 * (pmc->scratch90 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF; - pmc->scratch91 = (sdram->emc_dqs_brlshft0 << 8 >> 29 << 21) | ((sdram->emc_dqs_brlshft0 << 11 >> 29 << 18) | ((sdram->emc_dqs_brlshft0 << 14 >> 29 << 15) | ((sdram->emc_dqs_brlshft0 << 17 >> 29 << 12) | ((sdram->emc_dqs_brlshft0 << 20 >> 29 << 9) | ((sdram->emc_dqs_brlshft0 << 23 >> 29 << 6) | (8 * (sdram->emc_dqs_brlshft0 << 26 >> 29) | (sdram->emc_dqs_brlshft0 & 7 | 8 * (pmc->scratch91 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF; - pmc->scratch92 = (sdram->emc_dqs_brlshft1 << 8 >> 29 << 21) | ((sdram->emc_dqs_brlshft1 << 11 >> 29 << 18) | ((sdram->emc_dqs_brlshft1 << 14 >> 29 << 15) | ((sdram->emc_dqs_brlshft1 << 17 >> 29 << 12) | ((sdram->emc_dqs_brlshft1 << 20 >> 29 << 9) | ((sdram->emc_dqs_brlshft1 << 23 >> 29 << 6) | (8 * (sdram->emc_dqs_brlshft1 << 26 >> 29) | (sdram->emc_dqs_brlshft1 & 7 | 8 * (pmc->scratch92 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF; - pmc->scratch93 = (2 * sdram->emc_swizzle_rank0_byte0 >> 29 << 21) | ((32 * sdram->emc_swizzle_rank0_byte0 >> 29 << 18) | ((sdram->emc_swizzle_rank0_byte0 << 9 >> 29 << 15) | ((sdram->emc_swizzle_rank0_byte0 << 13 >> 29 << 12) | ((sdram->emc_swizzle_rank0_byte0 << 17 >> 29 << 9) | ((sdram->emc_swizzle_rank0_byte0 << 21 >> 29 << 6) | (8 * (sdram->emc_swizzle_rank0_byte0 << 25 >> 29) | (sdram->emc_swizzle_rank0_byte0 & 7 | 8 * (pmc->scratch93 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF; - pmc->scratch94 = ((u8)(sdram->emc_cfg) << 27 >> 31 << 31) | (2 * ((sdram->emc_ras << 24) | ((2 * sdram->emc_swizzle_rank0_byte1 >> 29 << 21) | ((32 * sdram->emc_swizzle_rank0_byte1 >> 29 << 18) | ((sdram->emc_swizzle_rank0_byte1 << 9 >> 29 << 15) | ((sdram->emc_swizzle_rank0_byte1 << 13 >> 29 << 12) | ((sdram->emc_swizzle_rank0_byte1 << 17 >> 29 << 9) | ((sdram->emc_swizzle_rank0_byte1 << 21 >> 29 << 6) | (8 * (sdram->emc_swizzle_rank0_byte1 << 25 >> 29) | (sdram->emc_swizzle_rank0_byte1 & 7 | 8 * (pmc->scratch94 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF) & 0x80FFFFFF) >> 1); - pmc->scratch95 = ((u8)(sdram->emc_cfg) << 26 >> 31 << 31) | (2 * ((sdram->emc_w2p << 24) | ((2 * sdram->emc_swizzle_rank0_byte2 >> 29 << 21) | ((32 * sdram->emc_swizzle_rank0_byte2 >> 29 << 18) | ((sdram->emc_swizzle_rank0_byte2 << 9 >> 29 << 15) | ((sdram->emc_swizzle_rank0_byte2 << 13 >> 29 << 12) | ((sdram->emc_swizzle_rank0_byte2 << 17 >> 29 << 9) | ((sdram->emc_swizzle_rank0_byte2 << 21 >> 29 << 6) | (8 * (sdram->emc_swizzle_rank0_byte2 << 25 >> 29) | (sdram->emc_swizzle_rank0_byte2 & 7 | 8 * (pmc->scratch95 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF) & 0x80FFFFFF) >> 1); - pmc->scratch96 = ((u8)(sdram->emc_cfg) << 25 >> 31 << 31) | (2 * ((sdram->emc_qsafe << 24) | ((2 * sdram->emc_swizzle_rank0_byte3 >> 29 << 21) | (((sdram->emc_swizzle_rank0_byte3 << 9 >> 29 << 15) | ((sdram->emc_swizzle_rank0_byte3 << 13 >> 29 << 12) | ((sdram->emc_swizzle_rank0_byte3 << 17 >> 29 << 9) | ((sdram->emc_swizzle_rank0_byte3 << 21 >> 29 << 6) | (8 * (sdram->emc_swizzle_rank0_byte3 << 25 >> 29) | (sdram->emc_swizzle_rank0_byte3 & 7 | 8 * (pmc->scratch96 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF | (32 * sdram->emc_swizzle_rank0_byte3 >> 29 << 18)) & 0xFF1FFFFF) & 0x80FFFFFF) >> 1); - pmc->scratch97 = ((u8)(sdram->emc_cfg) << 24 >> 31 << 31) | (2 * ((sdram->emc_rdv << 24) | ((2 * sdram->emc_swizzle_rank1_byte0 >> 29 << 21) | (((sdram->emc_swizzle_rank1_byte0 << 9 >> 29 << 15) | ((sdram->emc_swizzle_rank1_byte0 << 13 >> 29 << 12) | ((sdram->emc_swizzle_rank1_byte0 << 17 >> 29 << 9) | ((sdram->emc_swizzle_rank1_byte0 << 21 >> 29 << 6) | (8 * (sdram->emc_swizzle_rank1_byte0 << 25 >> 29) | (sdram->emc_swizzle_rank1_byte0 & 7 | 8 * (pmc->scratch97 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF | (32 * sdram->emc_swizzle_rank1_byte0 >> 29 << 18)) & 0xFF1FFFFF) & 0x80FFFFFF) >> 1); - pmc->scratch98 = ((u16)(sdram->emc_cfg) << 23 >> 31 << 31) | (2 * (((u16)(sdram->emc_rw2pden) << 24) | ((2 * sdram->emc_swizzle_rank1_byte1 >> 29 << 21) | ((32 * sdram->emc_swizzle_rank1_byte1 >> 29 << 18) | ((sdram->emc_swizzle_rank1_byte1 << 9 >> 29 << 15) | ((sdram->emc_swizzle_rank1_byte1 << 13 >> 29 << 12) | ((sdram->emc_swizzle_rank1_byte1 << 17 >> 29 << 9) | ((sdram->emc_swizzle_rank1_byte1 << 21 >> 29 << 6) | (8 * (sdram->emc_swizzle_rank1_byte1 << 25 >> 29) | (sdram->emc_swizzle_rank1_byte1 & 7 | 8 * (pmc->scratch98 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF) & 0x80FFFFFF) >> 1); - pmc->scratch99 = ((u16)(sdram->emc_cfg) << 22 >> 31 << 31) | (2 * ((sdram->emc_tfaw << 24) | ((2 * sdram->emc_swizzle_rank1_byte2 >> 29 << 21) | ((32 * sdram->emc_swizzle_rank1_byte2 >> 29 << 18) | ((sdram->emc_swizzle_rank1_byte2 << 9 >> 29 << 15) | ((sdram->emc_swizzle_rank1_byte2 << 13 >> 29 << 12) | ((sdram->emc_swizzle_rank1_byte2 << 17 >> 29 << 9) | ((sdram->emc_swizzle_rank1_byte2 << 21 >> 29 << 6) | (8 * (sdram->emc_swizzle_rank1_byte2 << 25 >> 29) | (sdram->emc_swizzle_rank1_byte2 & 7 | 8 * (pmc->scratch99 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF) & 0x80FFFFFF) >> 1); - pmc->scratch100 = (sdram->emc_cfg << 13 >> 31 << 31) | (2 * ((sdram->emc_tclkstable << 24) | ((2 * sdram->emc_swizzle_rank1_byte3 >> 29 << 21) | ((32 * sdram->emc_swizzle_rank1_byte3 >> 29 << 18) | ((sdram->emc_swizzle_rank1_byte3 << 9 >> 29 << 15) | ((sdram->emc_swizzle_rank1_byte3 << 13 >> 29 << 12) | ((sdram->emc_swizzle_rank1_byte3 << 17 >> 29 << 9) | ((sdram->emc_swizzle_rank1_byte3 << 21 >> 29 << 6) | (8 * (sdram->emc_swizzle_rank1_byte3 << 25 >> 29) | (sdram->emc_swizzle_rank1_byte3 & 7 | 8 * (pmc->scratch100 >> 3)) & 0xFFFFFFC7) & 0xFFFFFE3F) & 0xFFFFF1FF) & 0xFFFF8FFF) & 0xFFFC7FFF) & 0xFFE3FFFF) & 0xFF1FFFFF) & 0x80FFFFFF) >> 1); - tmp = 2 * (((u8)(sdram->emc_trtm) << 24) | ((16 * sdram->emc_cfg_pipe2 >> 31 << 23) | ((32 * sdram->emc_cfg_pipe2 >> 31 << 22) | ((sdram->emc_cfg_pipe2 << 6 >> 31 << 21) | ((sdram->emc_cfg_pipe2 << 7 >> 31 << 20) | ((sdram->emc_cfg_pipe2 << 8 >> 31 << 19) | ((sdram->emc_cfg_pipe2 << 9 >> 31 << 18) | ((sdram->emc_cfg_pipe2 << 10 >> 31 << 17) | ((sdram->emc_cfg_pipe2 << 11 >> 31 << 16) | ((sdram->emc_cfg_pipe2 << 12 >> 31 << 15) | ((sdram->emc_cfg_pipe2 << 13 >> 31 << 14) | ((sdram->emc_cfg_pipe2 << 14 >> 31 << 13) | ((sdram->emc_cfg_pipe2 << 15 >> 31 << 12) | ((sdram->emc_cfg_pipe2 << 20 >> 31 << 11) | ((sdram->emc_cfg_pipe2 << 21 >> 31 << 10) | ((sdram->emc_cfg_pipe2 << 22 >> 31 << 9) | ((sdram->emc_cfg_pipe2 << 23 >> 31 << 8) | ((sdram->emc_cfg_pipe2 << 24 >> 31 << 7) | ((sdram->emc_cfg_pipe2 << 25 >> 31 << 6) | (32 * (sdram->emc_cfg_pipe2 << 26 >> 31) | (16 * (sdram->emc_cfg_pipe2 << 27 >> 31) | (8 * (sdram->emc_cfg_pipe2 << 28 >> 31) | (4 * (sdram->emc_cfg_pipe2 << 29 >> 31) | (2 * (sdram->emc_cfg_pipe2 << 30 >> 31) | (sdram->emc_cfg_pipe2 & 1 | 2 * (pmc->scratch101 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0x80FFFFFF) >> 1; - pmc->scratch101 = (sdram->emc_cfg << 10 >> 31 << 31) | tmp; - tmp = (2 * (pmc->scratch102 >> 1) | sdram->emc_cfg_pipe1 & 1) & 0xFFFFFFFD; - pmc->scratch102 = (sdram->emc_cfg << 9 >> 31 << 31) | (2 * (((u8)(sdram->emc_twtm) << 24) | ((16 * sdram->emc_cfg_pipe1 >> 31 << 23) | ((32 * sdram->emc_cfg_pipe1 >> 31 << 22) | ((sdram->emc_cfg_pipe1 << 6 >> 31 << 21) | ((sdram->emc_cfg_pipe1 << 7 >> 31 << 20) | ((sdram->emc_cfg_pipe1 << 8 >> 31 << 19) | ((sdram->emc_cfg_pipe1 << 9 >> 31 << 18) | ((sdram->emc_cfg_pipe1 << 10 >> 31 << 17) | ((sdram->emc_cfg_pipe1 << 11 >> 31 << 16) | ((sdram->emc_cfg_pipe1 << 12 >> 31 << 15) | ((sdram->emc_cfg_pipe1 << 13 >> 31 << 14) | ((sdram->emc_cfg_pipe1 << 14 >> 31 << 13) | ((sdram->emc_cfg_pipe1 << 15 >> 31 << 12) | ((sdram->emc_cfg_pipe1 << 20 >> 31 << 11) | ((sdram->emc_cfg_pipe1 << 21 >> 31 << 10) | ((sdram->emc_cfg_pipe1 << 22 >> 31 << 9) | ((sdram->emc_cfg_pipe1 << 23 >> 31 << 8) | ((sdram->emc_cfg_pipe1 << 24 >> 31 << 7) | ((sdram->emc_cfg_pipe1 << 25 >> 31 << 6) | (32 * (sdram->emc_cfg_pipe1 << 26 >> 31) | (16 * (sdram->emc_cfg_pipe1 << 27 >> 31) | (8 * (sdram->emc_cfg_pipe1 << 28 >> 31) | (4 * (sdram->emc_cfg_pipe1 << 29 >> 31) | (2 * (sdram->emc_cfg_pipe1 << 30 >> 31) | tmp) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0x80FFFFFF) >> 1); - tmp = 2 * (((u8)(sdram->emc_tratm) << 24) | ((sdram->emc_pmacro_ddll_pwrd0 >> 31 << 23) | ((2 * sdram->emc_pmacro_ddll_pwrd0 >> 31 << 22) | ((8 * sdram->emc_pmacro_ddll_pwrd0 >> 31 << 21) | ((16 * sdram->emc_pmacro_ddll_pwrd0 >> 31 << 20) | ((32 * sdram->emc_pmacro_ddll_pwrd0 >> 31 << 19) | ((sdram->emc_pmacro_ddll_pwrd0 << 6 >> 31 << 18) | ((sdram->emc_pmacro_ddll_pwrd0 << 8 >> 31 << 17) | ((sdram->emc_pmacro_ddll_pwrd0 << 9 >> 31 << 16) | ((sdram->emc_pmacro_ddll_pwrd0 << 11 >> 31 << 15) | ((sdram->emc_pmacro_ddll_pwrd0 << 12 >> 31 << 14) | ((sdram->emc_pmacro_ddll_pwrd0 << 13 >> 31 << 13) | ((sdram->emc_pmacro_ddll_pwrd0 << 14 >> 31 << 12) | ((sdram->emc_pmacro_ddll_pwrd0 << 16 >> 31 << 11) | ((sdram->emc_pmacro_ddll_pwrd0 << 17 >> 31 << 10) | ((sdram->emc_pmacro_ddll_pwrd0 << 19 >> 31 << 9) | ((sdram->emc_pmacro_ddll_pwrd0 << 20 >> 31 << 8) | ((sdram->emc_pmacro_ddll_pwrd0 << 21 >> 31 << 7) | ((sdram->emc_pmacro_ddll_pwrd0 << 22 >> 31 << 6) | (32 * (sdram->emc_pmacro_ddll_pwrd0 << 24 >> 31) | (16 * (sdram->emc_pmacro_ddll_pwrd0 << 25 >> 31) | (8 * (sdram->emc_pmacro_ddll_pwrd0 << 27 >> 31) | (4 * (sdram->emc_pmacro_ddll_pwrd0 << 28 >> 31) | (2 * (sdram->emc_pmacro_ddll_pwrd0 << 29 >> 31) | ((sdram->emc_pmacro_ddll_pwrd0 << 30 >> 31) | 2 * (pmc->scratch103 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0x80FFFFFF) >> 1; - pmc->scratch103 = (sdram->emc_cfg << 8 >> 31 << 31) | tmp; - tmp = 2 * (((u8)(sdram->emc_twatm) << 24) | ((sdram->emc_pmacro_ddll_pwrd1 >> 31 << 23) | ((2 * sdram->emc_pmacro_ddll_pwrd1 >> 31 << 22) | ((8 * sdram->emc_pmacro_ddll_pwrd1 >> 31 << 21) | ((16 * sdram->emc_pmacro_ddll_pwrd1 >> 31 << 20) | ((32 * sdram->emc_pmacro_ddll_pwrd1 >> 31 << 19) | ((sdram->emc_pmacro_ddll_pwrd1 << 6 >> 31 << 18) | ((sdram->emc_pmacro_ddll_pwrd1 << 8 >> 31 << 17) | ((sdram->emc_pmacro_ddll_pwrd1 << 9 >> 31 << 16) | ((sdram->emc_pmacro_ddll_pwrd1 << 11 >> 31 << 15) | ((sdram->emc_pmacro_ddll_pwrd1 << 12 >> 31 << 14) | ((sdram->emc_pmacro_ddll_pwrd1 << 13 >> 31 << 13) | ((sdram->emc_pmacro_ddll_pwrd1 << 14 >> 31 << 12) | ((sdram->emc_pmacro_ddll_pwrd1 << 16 >> 31 << 11) | ((sdram->emc_pmacro_ddll_pwrd1 << 17 >> 31 << 10) | ((sdram->emc_pmacro_ddll_pwrd1 << 19 >> 31 << 9) | ((sdram->emc_pmacro_ddll_pwrd1 << 20 >> 31 << 8) | ((sdram->emc_pmacro_ddll_pwrd1 << 21 >> 31 << 7) | ((sdram->emc_pmacro_ddll_pwrd1 << 22 >> 31 << 6) | (32 * (sdram->emc_pmacro_ddll_pwrd1 << 24 >> 31) | (16 * (sdram->emc_pmacro_ddll_pwrd1 << 25 >> 31) | (8 * (sdram->emc_pmacro_ddll_pwrd1 << 27 >> 31) | (4 * (sdram->emc_pmacro_ddll_pwrd1 << 28 >> 31) | (2 * (sdram->emc_pmacro_ddll_pwrd1 << 29 >> 31) | ((sdram->emc_pmacro_ddll_pwrd1 << 30 >> 31) | 2 * (pmc->scratch104 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0x80FFFFFF) >> 1; - pmc->scratch104 = (sdram->emc_cfg << 7 >> 31 << 31) | tmp; - tmp = (sdram->emc_pmacro_ddll_pwrd2 << 22 >> 31 << 6) | (32 * (sdram->emc_pmacro_ddll_pwrd2 << 24 >> 31) | (16 * (sdram->emc_pmacro_ddll_pwrd2 << 25 >> 31) | (8 * (sdram->emc_pmacro_ddll_pwrd2 << 27 >> 31) | (4 * (sdram->emc_pmacro_ddll_pwrd2 << 28 >> 31) | (2 * (sdram->emc_pmacro_ddll_pwrd2 << 29 >> 31) | ((sdram->emc_pmacro_ddll_pwrd2 << 30 >> 31) | 2 * (pmc->scratch105 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF; - pmc->scratch105 = (sdram->emc_cfg << 6 >> 31 << 31) | (2 * (((u8)(sdram->emc_tr2ref) << 24) | ((sdram->emc_pmacro_ddll_pwrd2 >> 31 << 23) | ((2 * sdram->emc_pmacro_ddll_pwrd2 >> 31 << 22) | ((8 * sdram->emc_pmacro_ddll_pwrd2 >> 31 << 21) | ((16 * sdram->emc_pmacro_ddll_pwrd2 >> 31 << 20) | ((32 * sdram->emc_pmacro_ddll_pwrd2 >> 31 << 19) | ((sdram->emc_pmacro_ddll_pwrd2 << 6 >> 31 << 18) | ((sdram->emc_pmacro_ddll_pwrd2 << 8 >> 31 << 17) | ((sdram->emc_pmacro_ddll_pwrd2 << 9 >> 31 << 16) | ((sdram->emc_pmacro_ddll_pwrd2 << 11 >> 31 << 15) | ((sdram->emc_pmacro_ddll_pwrd2 << 12 >> 31 << 14) | ((sdram->emc_pmacro_ddll_pwrd2 << 13 >> 31 << 13) | ((sdram->emc_pmacro_ddll_pwrd2 << 14 >> 31 << 12) | ((sdram->emc_pmacro_ddll_pwrd2 << 16 >> 31 << 11) | ((sdram->emc_pmacro_ddll_pwrd2 << 17 >> 31 << 10) | ((sdram->emc_pmacro_ddll_pwrd2 << 19 >> 31 << 9) | ((sdram->emc_pmacro_ddll_pwrd2 << 20 >> 31 << 8) | ((sdram->emc_pmacro_ddll_pwrd2 << 21 >> 31 << 7) | tmp & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0x80FFFFFF) >> 1); - pmc->scratch106 = (32 * sdram->emc_cfg >> 31 << 31) | (2 * (((u16)(sdram->emc_pdex2mrr) << 24) | ((8 * sdram->emc_pmacro_ddll_periodic_offset >> 31 << 23) | ((16 * sdram->emc_pmacro_ddll_periodic_offset >> 31 << 22) | ((32 * sdram->emc_pmacro_ddll_periodic_offset >> 31 << 21) | ((sdram->emc_pmacro_ddll_periodic_offset << 6 >> 31 << 20) | ((sdram->emc_pmacro_ddll_periodic_offset << 7 >> 31 << 19) | ((sdram->emc_pmacro_ddll_periodic_offset << 8 >> 31 << 18) | ((sdram->emc_pmacro_ddll_periodic_offset << 9 >> 31 << 17) | ((sdram->emc_pmacro_ddll_periodic_offset << 10 >> 31 << 16) | ((sdram->emc_pmacro_ddll_periodic_offset << 11 >> 31 << 15) | ((sdram->emc_pmacro_ddll_periodic_offset << 15 >> 31 << 14) | ((sdram->emc_pmacro_ddll_periodic_offset << 16 >> 31 << 13) | ((sdram->emc_pmacro_ddll_periodic_offset << 17 >> 31 << 12) | ((sdram->emc_pmacro_ddll_periodic_offset << 18 >> 31 << 11) | ((sdram->emc_pmacro_ddll_periodic_offset << 19 >> 31 << 10) | ((sdram->emc_pmacro_ddll_periodic_offset << 20 >> 31 << 9) | ((sdram->emc_pmacro_ddll_periodic_offset << 21 >> 31 << 8) | ((sdram->emc_pmacro_ddll_periodic_offset << 22 >> 31 << 7) | ((sdram->emc_pmacro_ddll_periodic_offset << 23 >> 31 << 6) | (sdram->emc_pmacro_ddll_periodic_offset & 0x3F | (pmc->scratch106 >> 6 << 6)) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0x80FFFFFF) >> 1); - pmc->scratch107 = (8 * sdram->emc_cfg >> 31 << 31) | (2 * ((sdram->emc_clken_override << 15 >> 31 << 30) | ((sdram->emc_clken_override << 23 >> 31 << 29) | ((sdram->emc_clken_override << 24 >> 31 << 28) | ((sdram->emc_clken_override << 25 >> 31 << 27) | ((sdram->emc_clken_override << 28 >> 31 << 26) | ((sdram->emc_clken_override << 29 >> 31 << 25) | ((sdram->emc_clken_override << 30 >> 31 << 24) | ((sdram->mc_emem_arb_da_covers << 8 >> 24 << 16) | ((sdram->mc_emem_arb_da_covers << 16 >> 24 << 8) | (sdram->mc_emem_arb_da_covers & 0xFF | (pmc->scratch107 >> 8 << 8)) & 0xFFFF00FF) & 0xFF00FFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch108 = (sdram->emc_rfc_pb << 23) | ((sdram->emc_xm2_comp_pad_ctrl >> 24 << 15) | ((sdram->emc_xm2_comp_pad_ctrl << 12 >> 24 << 7) | ((sdram->emc_xm2_comp_pad_ctrl << 20 >> 31 << 6) | (32 * (sdram->emc_xm2_comp_pad_ctrl << 22 >> 31) | (4 * (sdram->emc_xm2_comp_pad_ctrl << 25 >> 29) | (sdram->emc_xm2_comp_pad_ctrl & 3 | 4 * (pmc->scratch108 >> 2)) & 0xFFFFFFE3) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFF807F) & 0xFF807FFF) & 0x7FFFFF; - pmc->scratch109 = (sdram->emc_cfg_update >> 31 << 31) | (2 * ((2 * sdram->emc_cfg_update >> 31 << 30) | ((4 * sdram->emc_cfg_update >> 31 << 29) | ((8 * sdram->emc_cfg_update >> 31 << 28) | ((sdram->emc_cfg_update << 21 >> 30 << 26) | ((sdram->emc_cfg_update << 23 >> 31 << 25) | ((sdram->emc_cfg_update << 29 >> 30 << 23) | ((sdram->emc_cfg_update << 22) & 0x7FFFFF | ((sdram->emc_auto_cal_config3 << 8 >> 28 << 18) | ((sdram->emc_auto_cal_config3 << 12 >> 28 << 14) | ((sdram->emc_auto_cal_config3 << 17 >> 25 << 7) | ((pmc->scratch109 >> 7 << 7) | sdram->emc_auto_cal_config3 & 0x7F) & 0xFFFFC07F) & 0xFFFC3FFF) & 0xFFC3FFFF) & 0xFFBFFFFF) & 0xFE7FFFFF) & 0xFDFFFFFF) & 0xF3FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch110 = (sdram->emc_rfc << 22) | ((sdram->emc_auto_cal_config4 << 8 >> 28 << 18) | ((sdram->emc_auto_cal_config4 << 12 >> 28 << 14) | ((sdram->emc_auto_cal_config4 << 17 >> 25 << 7) | (sdram->emc_auto_cal_config4 & 0x7F | (pmc->scratch110 >> 7 << 7)) & 0xFFFFC07F) & 0xFFFC3FFF) & 0xFFC3FFFF) & 0x3FFFFF; - pmc->scratch111 = ((u16)(sdram->emc_txsr) << 22) | ((sdram->emc_auto_cal_config5 << 8 >> 28 << 18) | ((sdram->emc_auto_cal_config5 << 12 >> 28 << 14) | ((sdram->emc_auto_cal_config5 << 17 >> 25 << 7) | ((pmc->scratch111 >> 7 << 7) | sdram->emc_auto_cal_config5 & 0x7F) & 0xFFFFC07F) & 0xFFFC3FFF) & 0xFFC3FFFF) & 0x3FFFFF; - pmc->scratch112 = (16 * sdram->emc_mc2emc_q >> 28 << 28) | ((sdram->emc_mc2emc_q << 21 >> 29 << 25) | ((sdram->emc_mc2emc_q << 22) & 0x1FFFFFF | ((sdram->emc_auto_cal_config6 << 8 >> 28 << 18) | ((sdram->emc_auto_cal_config6 << 12 >> 28 << 14) | ((sdram->emc_auto_cal_config6 << 17 >> 25 << 7) | (sdram->emc_auto_cal_config6 & 0x7F | (pmc->scratch112 >> 7 << 7)) & 0xFFFFC07F) & 0xFFFC3FFF) & 0xFFC3FFFF) & 0xFE3FFFFF) & 0xF1FFFFFF) & 0xFFFFFFF; - pmc->scratch113 = (sdram->mc_emem_arb_ring1_throttle << 11 >> 27 << 27) | ((sdram->mc_emem_arb_ring1_throttle << 22) | ((sdram->emc_auto_cal_config7 << 8 >> 28 << 18) | ((sdram->emc_auto_cal_config7 << 12 >> 28 << 14) | ((sdram->emc_auto_cal_config7 << 17 >> 25 << 7) | (sdram->emc_auto_cal_config7 & 0x7F | (pmc->scratch113 >> 7 << 7)) & 0xFFFFC07F) & 0xFFFC3FFF) & 0xFFC3FFFF) & 0xF83FFFFF) & 0x7FFFFFF; - pmc->scratch114 = (sdram->emc_auto_cal_config8 << 8 >> 28 << 18) | ((sdram->emc_auto_cal_config8 << 12 >> 28 << 14) | ((sdram->emc_auto_cal_config8 << 17 >> 25 << 7) | (sdram->emc_auto_cal_config8 & 0x7F | (pmc->scratch114 >> 7 << 7)) & 0xFFFFC07F) & 0xFFFC3FFF) & 0xFFC3FFFF; - pmc->scratch115 = (4 * sdram->emc_cfg >> 31 << 31) | (2 * (((u16)(sdram->emc_ar2pden) << 22) | ((sdram->emc_fbio_cfg7 << 10 >> 30 << 20) | ((sdram->emc_fbio_cfg7 << 12 >> 31 << 19) | ((sdram->emc_fbio_cfg7 << 13 >> 31 << 18) | ((sdram->emc_fbio_cfg7 << 14 >> 31 << 17) | ((sdram->emc_fbio_cfg7 << 15 >> 31 << 16) | ((sdram->emc_fbio_cfg7 << 16 >> 31 << 15) | ((sdram->emc_fbio_cfg7 << 17 >> 31 << 14) | ((sdram->emc_fbio_cfg7 << 18 >> 31 << 13) | ((sdram->emc_fbio_cfg7 << 19 >> 31 << 12) | ((sdram->emc_fbio_cfg7 << 20 >> 31 << 11) | ((sdram->emc_fbio_cfg7 << 21 >> 31 << 10) | ((sdram->emc_fbio_cfg7 << 22 >> 31 << 9) | ((sdram->emc_fbio_cfg7 << 23 >> 31 << 8) | ((sdram->emc_fbio_cfg7 << 24 >> 31 << 7) | ((sdram->emc_fbio_cfg7 << 25 >> 31 << 6) | (32 * (sdram->emc_fbio_cfg7 << 26 >> 31) | (16 * (sdram->emc_fbio_cfg7 << 27 >> 31) | (8 * (sdram->emc_fbio_cfg7 << 28 >> 31) | (4 * (sdram->emc_fbio_cfg7 << 29 >> 31) | (2 * (sdram->emc_fbio_cfg7 << 30 >> 31) | (sdram->emc_fbio_cfg7 & 1 | 2 * (pmc->scratch115 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFCFFFFF) & 0x803FFFFF) >> 1); - pmc->scratch123 = (2 * sdram->emc_cfg >> 31 << 31) | (2 * ((sdram->emc_rfc_slr << 22) | ((32 * sdram->emc_pmacro_quse_ddll_rank0_0 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank0_0 & 0x7FF | (pmc->scratch123 >> 11 << 11)) & 0xFFC007FF) & 0x803FFFFF) >> 1); - pmc->scratch124 = (sdram->emc_cfg >> 31 << 31) | (2 * ((4 * sdram->emc_ibdly >> 30 << 29) | ((sdram->emc_ibdly << 22) & 0x1FFFFFFF | ((32 * sdram->emc_pmacro_quse_ddll_rank0_1 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank0_1 & 0x7FF | (pmc->scratch124 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x9FFFFFFF) >> 1); - pmc->scratch125 = (sdram->emc_fbio_cfg5 << 27 >> 31 << 31) | (2 * (((u16)(sdram->mc_emem_arb_timing_rfcpb) << 22) | ((32 * sdram->emc_pmacro_quse_ddll_rank0_2 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank0_2 & 0x7FF | (pmc->scratch125 >> 11 << 11)) & 0xFFC007FF) & 0x803FFFFF) >> 1); - pmc->scratch126 = (sdram->emc_fbio_cfg5 << 16 >> 29 << 29) | ((sdram->emc_auto_cal_config9 << 25 >> 31 << 28) | ((sdram->emc_auto_cal_config9 << 26 >> 31 << 27) | ((sdram->emc_auto_cal_config9 << 27 >> 31 << 26) | ((sdram->emc_auto_cal_config9 << 28 >> 31 << 25) | ((sdram->emc_auto_cal_config9 << 29 >> 31 << 24) | ((sdram->emc_auto_cal_config9 << 30 >> 31 << 23) | ((sdram->emc_auto_cal_config9 << 22) & 0x7FFFFF | ((32 * sdram->emc_pmacro_quse_ddll_rank0_3 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank0_3 & 0x7FF | (pmc->scratch126 >> 11 << 11)) & 0xFFC007FF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0x1FFFFFFF; - pmc->scratch127 = ((u8)(sdram->emc_cfg2) << 26 >> 29 << 29) | ((sdram->emc_rdv_mask << 22) | ((32 * sdram->emc_pmacro_quse_ddll_rank0_4 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank0_4 & 0x7FF | (pmc->scratch127 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x1FFFFFFF; - pmc->scratch128 = (sdram->emc_pmacro_cmd_pad_tx_ctrl << 27 >> 29 << 29) | (((u8)(sdram->emc_rdv_early_mask) << 22) | ((32 * sdram->emc_pmacro_quse_ddll_rank0_5 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank0_5 & 0x7FF | (pmc->scratch128 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x1FFFFFFF; - pmc->scratch129 = (sdram->emc_pmacro_cmd_pad_tx_ctrl << 22 >> 29 << 29) | ((sdram->emc_rdv_early << 22) | ((32 * sdram->emc_pmacro_quse_ddll_rank1_0 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank1_0 & 0x7FF | (pmc->scratch129 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x1FFFFFFF; - pmc->scratch130 = (sdram->emc_pmacro_cmd_pad_tx_ctrl << 17 >> 29 << 29) | ((4 * sdram->emc_quse_width >> 31 << 28) | ((8 * sdram->emc_quse_width >> 31 << 27) | ((sdram->emc_quse_width << 22) & 0x7FFFFFF | ((32 * sdram->emc_pmacro_quse_ddll_rank1_1 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank1_1 & 0x7FF | (pmc->scratch130 >> 11 << 11)) & 0xFFC007FF) & 0xF83FFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0x1FFFFFFF; - pmc->scratch131 = (sdram->emc_pmacro_cmd_pad_tx_ctrl << 12 >> 29 << 29) | (((u16)(sdram->emc_pmacro_ddll_short_cmd_2) << 22) | ((32 * sdram->emc_pmacro_quse_ddll_rank1_2 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank1_2 & 0x7FF | (pmc->scratch131 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x1FFFFFFF; - pmc->scratch132 = (sdram->emc_pmacro_data_pad_tx_ctrl << 27 >> 29 << 29) | ((sdram->emc_pmacro_cmd_rx_term_mode << 18 >> 31 << 28) | ((sdram->emc_pmacro_cmd_rx_term_mode << 22 >> 30 << 26) | ((sdram->emc_pmacro_cmd_rx_term_mode << 26 >> 30 << 24) | ((sdram->emc_pmacro_cmd_rx_term_mode << 22) & 0xFFFFFF | ((32 * sdram->emc_pmacro_quse_ddll_rank1_3 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank1_3 & 0x7FF | (pmc->scratch132 >> 11 << 11)) & 0xFFC007FF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xEFFFFFFF) & 0x1FFFFFFF; - pmc->scratch133 = (sdram->emc_pmacro_data_pad_tx_ctrl << 22 >> 29 << 29) | ((sdram->emc_pmacro_data_rx_term_mode << 18 >> 31 << 28) | ((sdram->emc_pmacro_data_rx_term_mode << 22 >> 30 << 26) | ((sdram->emc_pmacro_data_rx_term_mode << 26 >> 30 << 24) | ((sdram->emc_pmacro_data_rx_term_mode << 22) & 0xFFFFFF | ((32 * sdram->emc_pmacro_quse_ddll_rank1_4 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank1_4 & 0x7FF | (pmc->scratch133 >> 11 << 11)) & 0xFFC007FF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xEFFFFFFF) & 0x1FFFFFFF; - pmc->scratch134 = (sdram->emc_pmacro_data_pad_tx_ctrl << 17 >> 29 << 29) | ((sdram->mc_emem_arb_timing_rp << 22) | ((32 * sdram->emc_pmacro_quse_ddll_rank1_5 >> 21 << 11) | (sdram->emc_pmacro_quse_ddll_rank1_5 & 0x7FF | (pmc->scratch134 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x1FFFFFFF; - pmc->scratch135 = (sdram->emc_pmacro_data_pad_tx_ctrl << 12 >> 29 << 29) | ((sdram->mc_emem_arb_timing_ras << 22) | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank0_0 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank0_0 & 0x7FF | (pmc->scratch135 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x1FFFFFFF; - pmc->scratch136 = (sdram->emc_fbio_cfg5 << 23 >> 31 << 31) | (2 * ((sdram->emc_cfg << 14 >> 30 << 29) | ((sdram->mc_emem_arb_timing_faw << 22) & 0x1FFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank0_1 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank0_1 & 0x7FF | (pmc->scratch136 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x9FFFFFFF) >> 1); - pmc->scratch137 = (sdram->emc_fbio_cfg5 << 21 >> 31 << 31) | (2 * ((sdram->emc_fbio_cfg5 << 29) | ((sdram->mc_emem_arb_timing_rap2pre << 22) & 0x1FFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank0_2 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank0_2 & 0x7FF | (pmc->scratch137 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x9FFFFFFF) >> 1); - pmc->scratch138 = (sdram->emc_fbio_cfg5 << 19 >> 31 << 31) | (2 * ((sdram->emc_fbio_cfg5 << 28 >> 30 << 29) | ((sdram->mc_emem_arb_timing_wap2pre << 22) & 0x1FFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank0_3 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank0_3 & 0x7FF | (pmc->scratch138 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x9FFFFFFF) >> 1); - pmc->scratch139 = (sdram->emc_fbio_cfg5 << 7 >> 31 << 31) | (2 * ((16 * sdram->emc_cfg2 >> 30 << 29) | (((u8)(sdram->mc_emem_arb_timing_r2w) << 22) & 0x1FFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank0_4 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank0_4 & 0x7FF | (pmc->scratch139 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0x9FFFFFFF) >> 1); - pmc->scratch140 = (16 * sdram->emc_fbio_cfg5 >> 31 << 31) | (2 * ((32 * sdram->emc_fbio_cfg5 >> 31 << 30) | ((sdram->emc_fbio_cfg5 << 6 >> 31 << 29) | (((u8)(sdram->mc_emem_arb_timing_w2r) << 22) & 0x1FFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank0_5 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank0_5 & 0x7FF | (pmc->scratch140 >> 11 << 11)) & 0xFFC007FF) & 0xE03FFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch141 = (sdram->emc_fbio_cfg5 << 8 >> 28 << 28) | (((u16)(sdram->emc_wdv) << 22) | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank1_0 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank1_0 & 0x7FF | (pmc->scratch141 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xFFFFFFF; - pmc->scratch142 = ((u8)(sdram->emc_cfg2) << 31) | (2 * ((sdram->emc_fbio_cfg5 >> 31 << 30) | ((2 * sdram->emc_fbio_cfg5 >> 31 << 29) | ((8 * sdram->emc_fbio_cfg5 >> 31 << 28) | ((sdram->emc_quse << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank1_1 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank1_1 & 0x7FF | (pmc->scratch142 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch143 = (((u16)(sdram->emc_cfg2) << 21) >> 31 << 31) | (2 * ((((u16)(sdram->emc_cfg2) << 24) >> 31 << 30) | ((((u16)(sdram->emc_cfg2) << 29) >> 31 << 29) | ((((u16)(sdram->emc_cfg2) << 30) >> 31 << 28) | (((u8)(sdram->emc_pdex2wr) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank1_2 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank1_2 & 0x7FF | (pmc->scratch143 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch144 = (sdram->emc_cfg2 << 15 >> 31 << 31) | (2 * ((sdram->emc_cfg2 << 16 >> 31 << 30) | ((sdram->emc_cfg2 << 17 >> 31 << 29) | ((sdram->emc_cfg2 << 20 >> 31 << 28) | (((u8)(sdram->emc_pdex2rd) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank1_3 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank1_3 & 0x7FF | (pmc->scratch144 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch145 = (sdram->emc_cfg2 << 7 >> 31 << 31) | (2 * ((sdram->emc_cfg2 << 8 >> 31 << 30) | ((sdram->emc_cfg2 << 9 >> 31 << 29) | ((sdram->emc_cfg2 << 11 >> 31 << 28) | (((u16)(sdram->emc_pdex2che) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank1_4 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank1_4 & 0x7FF | (pmc->scratch145 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch146 = (2 * sdram->emc_cfg2 >> 31 << 31) | (2 * ((4 * sdram->emc_cfg2 >> 31 << 30) | (((sdram->emc_cfg2 << 6 >> 31 << 28) | (((u8)(sdram->emc_pchg2pden) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dq_rank1_5 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dq_rank1_5 & 0x7FF | (pmc->scratch146 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF | (8 * sdram->emc_cfg2 >> 31 << 29)) & 0xBFFFFFFF) >> 1); - pmc->scratch147 = (((u8)(sdram->emc_cfg_pipe) << 29) >> 31 << 31) | (2 * ((((u8)(sdram->emc_cfg_pipe) << 30) >> 31 << 30) | ((((u8)(sdram->emc_cfg_pipe) << 31) >> 2) | ((sdram->emc_cfg2 >> 31 << 28) | (((u16)(sdram->emc_act2pden) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank0_0 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank0_0 & 0x7FF | (pmc->scratch147 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch148 = (((u8)(sdram->emc_cfg_pipe) << 25) >> 31 << 31) | (2 * ((((u8)(sdram->emc_cfg_pipe) << 26) >> 31 << 30) | ((((u8)(sdram->emc_cfg_pipe) << 27) >> 31 << 29) | ((((u8)(sdram->emc_cfg_pipe) << 28) >> 31 << 28) | (((u16)(sdram->emc_cke2pden) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank0_1 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank0_1 & 0x7FF | (pmc->scratch148 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch149 = (((u16)(sdram->emc_cfg_pipe) << 21) >> 31 << 31) | (2 * ((((u16)(sdram->emc_cfg_pipe) << 22) >> 31 << 30) | ((((u16)(sdram->emc_cfg_pipe) << 23) >> 31 << 29) | ((((u16)(sdram->emc_cfg_pipe) << 24) >> 31 << 28) | ((sdram->emc_tcke << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank0_2 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank0_2 & 0x7FF | (pmc->scratch149 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch150 = (sdram->emc_cfg_pipe << 13 >> 31 << 31) | (2 * ((sdram->emc_cfg_pipe << 14 >> 31 << 30) | (((sdram->emc_cfg_pipe << 20 >> 31 << 28) | ((sdram->emc_trpab << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank0_3 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank0_3 & 0x7FF | (pmc->scratch150 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF | (sdram->emc_cfg_pipe << 15 >> 31 << 29)) & 0xBFFFFFFF) >> 1); - pmc->scratch151 = (sdram->emc_cfg_pipe << 9 >> 31 << 31) | (2 * ((sdram->emc_cfg_pipe << 10 >> 31 << 30) | ((sdram->emc_cfg_pipe << 11 >> 31 << 29) | ((sdram->emc_cfg_pipe << 12 >> 31 << 28) | ((sdram->emc_einput << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank0_4 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank0_4 & 0x7FF | (pmc->scratch151 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch152 = (32 * sdram->emc_cfg_pipe >> 31 << 31) | (2 * ((sdram->emc_cfg_pipe << 6 >> 31 << 30) | ((sdram->emc_cfg_pipe << 7 >> 31 << 29) | ((sdram->emc_cfg_pipe << 8 >> 31 << 28) | ((sdram->emc_einput_duration << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank0_5 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank0_5 & 0x7FF | (pmc->scratch152 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch153 = (((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 29) >> 31 << 31) | (2 * ((((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 30) >> 31 << 30) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 31) >> 2) | ((16 * sdram->emc_cfg_pipe >> 31 << 28) | ((sdram->emc_puterm_extra << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank1_0 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank1_0 & 0x7FF | (pmc->scratch153 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch154 = (((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 25) >> 31 << 31) | (2 * ((((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 26) >> 31 << 30) | (((((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 28) >> 31 << 28) | ((sdram->emc_tckesr << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank1_1 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank1_1 & 0x7FF | (pmc->scratch154 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF | (((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 27) >> 31 << 29)) & 0xBFFFFFFF) >> 1); - pmc->scratch155 = (((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 21) >> 31 << 31) | (2 * ((((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 22) >> 31 << 30) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 23) >> 31 << 29) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src0) << 24) >> 31 << 28) | ((sdram->emc_tpd << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank1_2 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank1_2 & 0x7FF | (pmc->scratch155 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch156 = (sdram->emc_pmacro_tx_sel_clk_src0 << 12 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src0 << 13 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src0 << 14 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src0 << 15 >> 31 << 28) | ((sdram->emc_wdv_mask << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank1_3 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank1_3 & 0x7FF | (pmc->scratch156 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch157 = (sdram->emc_pmacro_tx_sel_clk_src0 << 8 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src0 << 9 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src0 << 10 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src0 << 11 >> 31 << 28) | (((u16)(sdram->emc_wdv_chk) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank1_4 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank1_4 & 0x7FF | (pmc->scratch157 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch158 = ((u16)(sdram->emc_pmacro_tx_sel_clk_src1) << 31) | (2 * ((32 * sdram->emc_pmacro_tx_sel_clk_src0 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src0 << 6 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src0 << 7 >> 31 << 28) | (((u8)(sdram->emc_cmd_brlshft0) << 26 >> 29 << 25) | (((u8)(sdram->emc_cmd_brlshft0) << 22) & 0x1FFFFFF | ((32 * sdram->emc_pmacro_ob_ddll_long_dqs_rank1_5 >> 21 << 11) | (sdram->emc_pmacro_ob_ddll_long_dqs_rank1_5 & 0x7FF | (pmc->scratch158 >> 11 << 11)) & 0xFFC007FF) & 0xFE3FFFFF) & 0xF1FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch159 = (((u16)(sdram->emc_pmacro_tx_sel_clk_src1) << 27) >> 31 << 31) | (2 * ((((u16)(sdram->emc_pmacro_tx_sel_clk_src1) << 28) >> 31 << 30) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src1) << 29) >> 31 << 29) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src1) << 30) >> 31 << 28) | (((u8)(sdram->emc_cmd_brlshft1) << 26 >> 29 << 25) | (((u8)(sdram->emc_cmd_brlshft1) << 22) & 0x1FFFFFF | ((32 * sdram->emc_pmacro_ib_ddll_long_dqs_rank0_0 >> 21 << 11) | (sdram->emc_pmacro_ib_ddll_long_dqs_rank0_0 & 0x7FF | (pmc->scratch159 >> 11 << 11)) & 0xFFC007FF) & 0xFE3FFFFF) & 0xF1FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch160 = (((u16)(sdram->emc_pmacro_tx_sel_clk_src1) << 23) >> 31 << 31) | (2 * ((((u16)(sdram->emc_pmacro_tx_sel_clk_src1) << 24) >> 31 << 30) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src1) << 25) >> 31 << 29) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src1) << 26) >> 31 << 28) | (((u8)(sdram->emc_cmd_brlshft2) << 26 >> 29 << 25) | (((u8)(sdram->emc_cmd_brlshft2) << 22) & 0x1FFFFFF | ((32 * sdram->emc_pmacro_ib_ddll_long_dqs_rank0_1 >> 21 << 11) | (sdram->emc_pmacro_ib_ddll_long_dqs_rank0_1 & 0x7FF | (pmc->scratch160 >> 11 << 11)) & 0xFFC007FF) & 0xFE3FFFFF) & 0xF1FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch161 = (sdram->emc_pmacro_tx_sel_clk_src1 << 14 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src1 << 15 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src1 << 21 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src1 << 22 >> 31 << 28) | (((u8)(sdram->emc_cmd_brlshft3) << 26 >> 29 << 25) | (((u8)(sdram->emc_cmd_brlshft3) << 22) & 0x1FFFFFF | ((32 * sdram->emc_pmacro_ib_ddll_long_dqs_rank0_2 >> 21 << 11) | (sdram->emc_pmacro_ib_ddll_long_dqs_rank0_2 & 0x7FF | (pmc->scratch161 >> 11 << 11)) & 0xFFC007FF) & 0xFE3FFFFF) & 0xF1FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch162 = (sdram->emc_pmacro_tx_sel_clk_src1 << 10 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src1 << 11 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src1 << 12 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src1 << 13 >> 31 << 28) | (((u16)(sdram->emc_wev) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ib_ddll_long_dqs_rank0_3 >> 21 << 11) | (sdram->emc_pmacro_ib_ddll_long_dqs_rank0_3 & 0x7FF | (pmc->scratch162 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch163 = (sdram->emc_pmacro_tx_sel_clk_src1 << 6 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src1 << 7 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src1 << 8 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src1 << 9 >> 31 << 28) | (((u16)(sdram->emc_wsv) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ib_ddll_long_dqs_rank1_0 >> 21 << 11) | (sdram->emc_pmacro_ib_ddll_long_dqs_rank1_0 & 0x7FF | (pmc->scratch163 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch164 = (((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 29) >> 31 << 31) | (2 * ((((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 30) >> 31 << 30) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 31) >> 2) | ((32 * sdram->emc_pmacro_tx_sel_clk_src1 >> 31 << 28) | (((u8)(sdram->emc_cfg3) << 25 >> 29 << 25) | (((u8)(sdram->emc_cfg3) << 22) & 0x1FFFFFF | ((32 * sdram->emc_pmacro_ib_ddll_long_dqs_rank1_1 >> 21 << 11) | (sdram->emc_pmacro_ib_ddll_long_dqs_rank1_1 & 0x7FF | (pmc->scratch164 >> 11 << 11)) & 0xFFC007FF) & 0xFE3FFFFF) & 0xF1FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch165 = (((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 25) >> 31 << 31) | (2 * ((((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 26) >> 31 << 30) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 27) >> 31 << 29) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 28) >> 31 << 28) | ((sdram->emc_puterm_width << 23) & 0xFFFFFFF | ((sdram->emc_puterm_width >> 31 << 22) | ((32 * sdram->emc_pmacro_ib_ddll_long_dqs_rank1_2 >> 21 << 11) | (sdram->emc_pmacro_ib_ddll_long_dqs_rank1_2 & 0x7FF | (pmc->scratch165 >> 11 << 11)) & 0xFFC007FF) & 0xFFBFFFFF) & 0xF07FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch166 = (((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 21) >> 31 << 31) | (2 * ((((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 22) >> 31 << 30) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 23) >> 31 << 29) | ((((u16)(sdram->emc_pmacro_tx_sel_clk_src3) << 24) >> 31 << 28) | ((sdram->mc_emem_arb_timing_rcd << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ib_ddll_long_dqs_rank1_3 >> 21 << 11) | (sdram->emc_pmacro_ib_ddll_long_dqs_rank1_3 & 0x7FF | (pmc->scratch166 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch167 = (sdram->emc_pmacro_tx_sel_clk_src3 << 12 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src3 << 13 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src3 << 14 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src3 << 15 >> 31 << 28) | (((u16)(sdram->mc_emem_arb_timing_ccdmw) << 22) & 0xFFFFFFF | ((32 * sdram->emc_pmacro_ddll_long_cmd_0 >> 21 << 11) | (sdram->emc_pmacro_ddll_long_cmd_0 & 0x7FF | (pmc->scratch167 >> 11 << 11)) & 0xFFC007FF) & 0xF03FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch168 = (sdram->emc_pmacro_tx_sel_clk_src3 << 8 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src3 << 9 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src3 << 10 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src3 << 11 >> 31 << 28) | ((sdram->mc_emem_arb_override << 28 >> 31 << 27) | (((sdram->mc_emem_arb_override << 21 >> 31 << 25) | ((sdram->mc_emem_arb_override << 15 >> 31 << 24) | ((32 * sdram->mc_emem_arb_override >> 31 << 23) | ((16 * sdram->mc_emem_arb_override >> 31 << 22) | ((32 * sdram->emc_pmacro_ddll_long_cmd_1 >> 21 << 11) | (sdram->emc_pmacro_ddll_long_cmd_1 & 0x7FF | (pmc->scratch168 >> 11 << 11)) & 0xFFC007FF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF | (sdram->mc_emem_arb_override << 27 >> 31 << 26)) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch169 = ((u16)(sdram->emc_rext) << 27) | (((u16)(sdram->emc_rrd) << 22) | ((32 * sdram->emc_pmacro_ddll_long_cmd_2 >> 21 << 11) | (sdram->emc_pmacro_ddll_long_cmd_2 & 0x7FF | (pmc->scratch169 >> 11 << 11)) & 0xFFC007FF) & 0xF83FFFFF) & 0x7FFFFFF; - pmc->scratch170 = ((u16)(sdram->emc_wext) << 27) | ((sdram->emc_tclkstop << 22) | ((32 * sdram->emc_pmacro_ddll_long_cmd_3 >> 21 << 11) | (sdram->emc_pmacro_ddll_long_cmd_3 & 0x7FF | (pmc->scratch170 >> 11 << 11)) & 0xFFC007FF) & 0xF83FFFFF) & 0x7FFFFFF; - tmp = (32 * sdram->emc_pmacro_perbit_fgcg_ctrl0 >> 31 << 21) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 6 >> 31 << 20) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 7 >> 31 << 19) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 8 >> 31 << 18) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 9 >> 31 << 17) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 10 >> 31 << 16) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 11 >> 31 << 15) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 12 >> 31 << 14) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 13 >> 31 << 13) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 14 >> 31 << 12) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 15 >> 31 << 11) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 21 >> 31 << 10) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 22 >> 31 << 9) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 23 >> 31 << 8) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 24 >> 31 << 7) | ((sdram->emc_pmacro_perbit_fgcg_ctrl0 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_perbit_fgcg_ctrl0 << 26 >> 31) | (16 * (sdram->emc_pmacro_perbit_fgcg_ctrl0 << 27 >> 31) | (8 * (sdram->emc_pmacro_perbit_fgcg_ctrl0 << 28 >> 31) | (4 * (sdram->emc_pmacro_perbit_fgcg_ctrl0 << 29 >> 31) | (2 * (sdram->emc_pmacro_perbit_fgcg_ctrl0 << 30 >> 31) | (sdram->emc_pmacro_perbit_fgcg_ctrl0 & 1 | 2 * (pmc->scratch171 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF; - pmc->scratch171 = (sdram->emc_we_duration << 27) | ((sdram->emc_ref_ctrl2 >> 31 << 26) | ((32 * sdram->emc_ref_ctrl2 >> 29 << 23) | ((sdram->emc_ref_ctrl2 << 22) & 0x7FFFFF | tmp & 0xFFBFFFFF) & 0xFC7FFFFF) & 0xFBFFFFFF) & 0x7FFFFFF; - tmp = (sdram->emc_pmacro_pad_cfg_ctrl << 22 >> 31 << 28) | ((sdram->emc_pmacro_pad_cfg_ctrl << 27) & 0xFFFFFFF | ((sdram->emc_ws_duration << 22) & 0x7FFFFFF | ((32 * sdram->emc_pmacro_perbit_fgcg_ctrl1 >> 31 << 21) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 6 >> 31 << 20) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 7 >> 31 << 19) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 8 >> 31 << 18) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 9 >> 31 << 17) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 10 >> 31 << 16) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 11 >> 31 << 15) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 12 >> 31 << 14) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 13 >> 31 << 13) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 14 >> 31 << 12) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 15 >> 31 << 11) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 21 >> 31 << 10) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 22 >> 31 << 9) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 23 >> 31 << 8) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 24 >> 31 << 7) | ((sdram->emc_pmacro_perbit_fgcg_ctrl1 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_perbit_fgcg_ctrl1 << 26 >> 31) | (16 * (sdram->emc_pmacro_perbit_fgcg_ctrl1 << 27 >> 31) | (8 * (sdram->emc_pmacro_perbit_fgcg_ctrl1 << 28 >> 31) | (4 * (sdram->emc_pmacro_perbit_fgcg_ctrl1 << 29 >> 31) | (2 * (sdram->emc_pmacro_perbit_fgcg_ctrl1 << 30 >> 31) | (sdram->emc_pmacro_perbit_fgcg_ctrl1 & 1 | 2 * (pmc->scratch172 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xF83FFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF; - pmc->scratch172 = (sdram->emc_pmacro_pad_cfg_ctrl << 14 >> 30 << 30) | (4 * ((sdram->emc_pmacro_pad_cfg_ctrl << 18 >> 31 << 29) | tmp & 0xDFFFFFFF) >> 2); - pmc->scratch173 = ((u8)(sdram->mc_emem_arb_timing_r2r) << 27) | ((sdram->mc_emem_arb_timing_rrd << 22) | ((32 * sdram->emc_pmacro_perbit_fgcg_ctrl2 >> 31 << 21) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 6 >> 31 << 20) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 7 >> 31 << 19) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 8 >> 31 << 18) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 9 >> 31 << 17) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 10 >> 31 << 16) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 11 >> 31 << 15) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 12 >> 31 << 14) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 13 >> 31 << 13) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 14 >> 31 << 12) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 15 >> 31 << 11) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 21 >> 31 << 10) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 22 >> 31 << 9) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 23 >> 31 << 8) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 24 >> 31 << 7) | ((sdram->emc_pmacro_perbit_fgcg_ctrl2 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_perbit_fgcg_ctrl2 << 26 >> 31) | (16 * (sdram->emc_pmacro_perbit_fgcg_ctrl2 << 27 >> 31) | (8 * (sdram->emc_pmacro_perbit_fgcg_ctrl2 << 28 >> 31) | (4 * (sdram->emc_pmacro_perbit_fgcg_ctrl2 << 29 >> 31) | (2 * (sdram->emc_pmacro_perbit_fgcg_ctrl2 << 30 >> 31) | (sdram->emc_pmacro_perbit_fgcg_ctrl2 & 1 | 2 * (pmc->scratch173 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xF83FFFFF) & 0x7FFFFFF; - tmp = 32 * (sdram->emc_pmacro_perbit_fgcg_ctrl3 << 26 >> 31) | (16 * (sdram->emc_pmacro_perbit_fgcg_ctrl3 << 27 >> 31) | (8 * (sdram->emc_pmacro_perbit_fgcg_ctrl3 << 28 >> 31) | (4 * (sdram->emc_pmacro_perbit_fgcg_ctrl3 << 29 >> 31) | (2 * (sdram->emc_pmacro_perbit_fgcg_ctrl3 << 30 >> 31) | (sdram->emc_pmacro_perbit_fgcg_ctrl3 & 1 | 2 * (pmc->scratch174 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF; - pmc->scratch174 = ((u16)(sdram->emc_pmacro_tx_sel_clk_src2) << 30 >> 31 << 31) | (2 * (((u16)(sdram->emc_pmacro_tx_sel_clk_src2) << 30) | ((32 * sdram->emc_pmacro_tx_sel_clk_src3 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src3 << 6 >> 31 << 28) | ((sdram->emc_pmacro_tx_sel_clk_src3 << 7 >> 31 << 27) | (((u8)(sdram->mc_emem_arb_timing_w2w) << 22) & 0x7FFFFFF | ((32 * sdram->emc_pmacro_perbit_fgcg_ctrl3 >> 31 << 21) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 6 >> 31 << 20) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 7 >> 31 << 19) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 8 >> 31 << 18) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 9 >> 31 << 17) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 10 >> 31 << 16) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 11 >> 31 << 15) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 12 >> 31 << 14) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 13 >> 31 << 13) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 14 >> 31 << 12) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 15 >> 31 << 11) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 21 >> 31 << 10) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 22 >> 31 << 9) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 23 >> 31 << 8) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 24 >> 31 << 7) | ((sdram->emc_pmacro_perbit_fgcg_ctrl3 << 25 >> 31 << 6) | tmp & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xF83FFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - tmp = (sdram->emc_pmacro_tx_sel_clk_src2 << 28 >> 31 << 23) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 29 >> 31 << 22) | ((32 * sdram->emc_pmacro_perbit_fgcg_ctrl4 >> 31 << 21) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 6 >> 31 << 20) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 7 >> 31 << 19) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 8 >> 31 << 18) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 9 >> 31 << 17) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 10 >> 31 << 16) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 11 >> 31 << 15) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 12 >> 31 << 14) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 13 >> 31 << 13) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 14 >> 31 << 12) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 15 >> 31 << 11) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 21 >> 31 << 10) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 22 >> 31 << 9) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 23 >> 31 << 8) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 24 >> 31 << 7) | ((sdram->emc_pmacro_perbit_fgcg_ctrl4 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_perbit_fgcg_ctrl4 << 26 >> 31) | (16 * (sdram->emc_pmacro_perbit_fgcg_ctrl4 << 27 >> 31) | (8 * (sdram->emc_pmacro_perbit_fgcg_ctrl4 << 28 >> 31) | (4 * (sdram->emc_pmacro_perbit_fgcg_ctrl4 << 29 >> 31) | (2 * (sdram->emc_pmacro_perbit_fgcg_ctrl4 << 30 >> 31) | (sdram->emc_pmacro_perbit_fgcg_ctrl4 & 1 | 2 * (pmc->scratch175 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF; - pmc->scratch175 = (sdram->emc_pmacro_tx_sel_clk_src2 << 15 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src2 << 21 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 22 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 23 >> 31 << 28) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 24 >> 31 << 27) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 25 >> 31 << 26) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 26 >> 31 << 25) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 27 >> 31 << 24) | tmp & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - tmp = (sdram->emc_pmacro_tx_sel_clk_src2 << 12 >> 31 << 24) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 13 >> 31 << 23) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 14 >> 31 << 22) | ((32 * sdram->emc_pmacro_perbit_fgcg_ctrl5 >> 31 << 21) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 6 >> 31 << 20) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 7 >> 31 << 19) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 8 >> 31 << 18) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 9 >> 31 << 17) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 10 >> 31 << 16) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 11 >> 31 << 15) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 12 >> 31 << 14) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 13 >> 31 << 13) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 14 >> 31 << 12) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 15 >> 31 << 11) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 21 >> 31 << 10) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 22 >> 31 << 9) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 23 >> 31 << 8) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 24 >> 31 << 7) | ((sdram->emc_pmacro_perbit_fgcg_ctrl5 << 25 >> 31 << 6) | (32 * (sdram->emc_pmacro_perbit_fgcg_ctrl5 << 26 >> 31) | (16 * (sdram->emc_pmacro_perbit_fgcg_ctrl5 << 27 >> 31) | (8 * (sdram->emc_pmacro_perbit_fgcg_ctrl5 << 28 >> 31) | (4 * (sdram->emc_pmacro_perbit_fgcg_ctrl5 << 29 >> 31) | (2 * (sdram->emc_pmacro_perbit_fgcg_ctrl5 << 30 >> 31) | (sdram->emc_pmacro_perbit_fgcg_ctrl5 & 1 | 2 * (pmc->scratch176 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF; - pmc->scratch176 = (32 * sdram->emc_pmacro_tx_sel_clk_src2 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src2 << 6 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 7 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 8 >> 31 << 28) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 9 >> 31 << 27) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 10 >> 31 << 26) | ((sdram->emc_pmacro_tx_sel_clk_src2 << 11 >> 31 << 25) | tmp & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch177 = (sdram->emc_pmacro_tx_sel_clk_src4 << 22 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src4 << 23 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 24 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 25 >> 31 << 28) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 26 >> 31 << 27) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 27 >> 31 << 26) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 28 >> 31 << 25) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 29 >> 31 << 24) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 30 >> 31 << 23) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 22) & 0x7FFFFF | ((sdram->mc_emem_arb_cfg >> 28 << 18) | ((16 * sdram->mc_emem_arb_cfg >> 28 << 14) | ((sdram->mc_emem_arb_cfg << 11 >> 27 << 9) | (sdram->mc_emem_arb_cfg & 0x1FF | (pmc->scratch177 >> 9 << 9)) & 0xFFFFC1FF) & 0xFFFC3FFF) & 0xFFC3FFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch178 = (sdram->emc_pmacro_tx_sel_clk_src4 << 7 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src4 << 8 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 9 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 10 >> 31 << 28) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 11 >> 31 << 27) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 12 >> 31 << 26) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 13 >> 31 << 25) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 14 >> 31 << 24) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 15 >> 31 << 23) | ((sdram->emc_pmacro_tx_sel_clk_src4 << 21 >> 31 << 22) | ((sdram->mc_emem_arb_misc1 >> 28 << 18) | ((sdram->mc_emem_arb_misc1 << 6 >> 30 << 16) | ((sdram->mc_emem_arb_misc1 << 8 >> 29 << 13) | (16 * (sdram->mc_emem_arb_misc1 << 19 >> 23) | (8 * (sdram->mc_emem_arb_misc1 << 28 >> 31) | (4 * (sdram->mc_emem_arb_misc1 << 29 >> 31) | (2 * (sdram->mc_emem_arb_misc1 << 30 >> 31) | (sdram->mc_emem_arb_misc1 & 1 | 2 * (pmc->scratch178 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFE00F) & 0xFFFF1FFF) & 0xFFFCFFFF) & 0xFFC3FFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch179 = (sdram->emc_odt_write >> 31 << 31) | (2 * ((sdram->emc_odt_write << 20 >> 28 << 27) | ((sdram->emc_odt_write << 26 >> 31 << 26) | ((sdram->emc_odt_write << 27 >> 31 << 25) | ((sdram->emc_odt_write << 21) & 0x1FFFFFF | ((32 * sdram->emc_mrs_wait_cnt2 >> 21 << 10) | (sdram->emc_mrs_wait_cnt2 & 0x3FF | (pmc->scratch179 >> 10 << 10)) & 0xFFE003FF) & 0xFE1FFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0x87FFFFFF) >> 1); - pmc->scratch180 = (sdram->emc_pmacro_ib_rxrt << 21) | ((32 * sdram->emc_mrs_wait_cnt >> 21 << 10) | (sdram->emc_mrs_wait_cnt & 0x3FF | (pmc->scratch180 >> 10 << 10)) & 0xFFE003FF) & 0x1FFFFF; - pmc->scratch181 = ((u16)(sdram->emc_pmacro_ddll_long_cmd_4) << 21) | sdram->emc_auto_cal_interval & 0x1FFFFF; - pmc->scratch182 = (sdram->mc_emem_arb_outstanding_req >> 31 << 31) | (2 * ((2 * sdram->mc_emem_arb_outstanding_req >> 31 << 30) | ((sdram->mc_emem_arb_outstanding_req << 23 >> 2) | ((sdram->emc_emem_arb_refpb_hp_ctrl << 9 >> 25 << 14) | ((sdram->emc_emem_arb_refpb_hp_ctrl << 17 >> 25 << 7) | (sdram->emc_emem_arb_refpb_hp_ctrl & 0x7F | (pmc->scratch182 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xC01FFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch183 = (4 * sdram->emc_pmacro_cmd_ctrl0 >> 31 << 31) | (2 * ((8 * sdram->emc_pmacro_cmd_ctrl0 >> 31 << 30) | ((sdram->emc_pmacro_cmd_ctrl0 << 7 >> 31 << 29) | ((sdram->emc_pmacro_cmd_ctrl0 << 10 >> 31 << 28) | ((sdram->emc_pmacro_cmd_ctrl0 << 11 >> 31 << 27) | ((sdram->emc_pmacro_cmd_ctrl0 << 15 >> 31 << 26) | ((sdram->emc_pmacro_cmd_ctrl0 << 18 >> 31 << 25) | ((sdram->emc_pmacro_cmd_ctrl0 << 19 >> 31 << 24) | ((sdram->emc_pmacro_cmd_ctrl0 << 23 >> 31 << 23) | ((sdram->emc_pmacro_cmd_ctrl0 << 26 >> 31 << 22) | ((sdram->emc_pmacro_cmd_ctrl0 << 27 >> 31 << 21) | ((sdram->emc_pmacro_cmd_ctrl0 << 20) & 0x1FFFFF | ((4 * sdram->emc_xm2_comp_pad_ctrl2 >> 26 << 14) | ((sdram->emc_xm2_comp_pad_ctrl2 << 10 >> 30 << 12) | ((sdram->emc_xm2_comp_pad_ctrl2 << 14 >> 31 << 11) | ((sdram->emc_xm2_comp_pad_ctrl2 << 15 >> 31 << 10) | ((sdram->emc_xm2_comp_pad_ctrl2 << 16 >> 30 << 8) | ((sdram->emc_xm2_comp_pad_ctrl2 << 18 >> 30 << 6) | (4 * (sdram->emc_xm2_comp_pad_ctrl2 << 26 >> 28) | (sdram->emc_xm2_comp_pad_ctrl2 & 3 | 4 * (pmc->scratch183 >> 2)) & 0xFFFFFFC3) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFCFFF) & 0xFFF03FFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch184 = (4 * sdram->emc_pmacro_cmd_ctrl1 >> 31 << 31) | (2 * ((8 * sdram->emc_pmacro_cmd_ctrl1 >> 31 << 30) | ((sdram->emc_pmacro_cmd_ctrl1 << 7 >> 31 << 29) | ((sdram->emc_pmacro_cmd_ctrl1 << 10 >> 31 << 28) | ((sdram->emc_pmacro_cmd_ctrl1 << 11 >> 31 << 27) | ((sdram->emc_pmacro_cmd_ctrl1 << 15 >> 31 << 26) | ((sdram->emc_pmacro_cmd_ctrl1 << 18 >> 31 << 25) | ((sdram->emc_pmacro_cmd_ctrl1 << 19 >> 31 << 24) | ((sdram->emc_pmacro_cmd_ctrl1 << 23 >> 31 << 23) | ((sdram->emc_pmacro_cmd_ctrl1 << 26 >> 31 << 22) | ((sdram->emc_pmacro_cmd_ctrl1 << 27 >> 31 << 21) | ((sdram->emc_pmacro_cmd_ctrl1 << 20) & 0x1FFFFF | ((sdram->emc_cfg_dig_dll_1 << 12 >> 28 << 16) | ((sdram->emc_cfg_dig_dll_1 << 16 >> 28 << 12) | ((sdram->emc_cfg_dig_dll_1 << 20 >> 26 << 6) | (2 * (sdram->emc_cfg_dig_dll_1 << 26 >> 27) | (sdram->emc_cfg_dig_dll_1 & 1 | 2 * (pmc->scratch184 >> 1)) & 0xFFFFFFC1) & 0xFFFFF03F) & 0xFFFF0FFF) & 0xFFF0FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch185 = (4 * sdram->emc_pmacro_cmd_ctrl2 >> 31 << 31) | (2 * ((8 * sdram->emc_pmacro_cmd_ctrl2 >> 31 << 30) | ((sdram->emc_pmacro_cmd_ctrl2 << 7 >> 31 << 29) | ((sdram->emc_pmacro_cmd_ctrl2 << 10 >> 31 << 28) | ((sdram->emc_pmacro_cmd_ctrl2 << 11 >> 31 << 27) | ((sdram->emc_pmacro_cmd_ctrl2 << 15 >> 31 << 26) | ((sdram->emc_pmacro_cmd_ctrl2 << 18 >> 31 << 25) | ((sdram->emc_pmacro_cmd_ctrl2 << 19 >> 31 << 24) | ((sdram->emc_pmacro_cmd_ctrl2 << 23 >> 31 << 23) | ((sdram->emc_pmacro_cmd_ctrl2 << 26 >> 31 << 22) | ((sdram->emc_pmacro_cmd_ctrl2 << 27 >> 31 << 21) | ((sdram->emc_pmacro_cmd_ctrl2 << 20) & 0x1FFFFF | ((sdram->emc_quse_brlshft0 << 12 >> 27 << 15) | ((sdram->emc_quse_brlshft0 << 17 >> 27 << 10) | (32 * (sdram->emc_quse_brlshft0 << 22 >> 27) | (sdram->emc_quse_brlshft0 & 0x1F | 32 * (pmc->scratch185 >> 5)) & 0xFFFFFC1F) & 0xFFFF83FF) & 0xFFF07FFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch186 = (sdram->emc_pmacro_dsr_vttgen_ctrl0 >> 8 << 24) | ((sdram->emc_pmacro_dsr_vttgen_ctrl0 << 20) | ((sdram->emc_quse_brlshft1 << 12 >> 27 << 15) | ((sdram->emc_quse_brlshft1 << 17 >> 27 << 10) | (32 * (sdram->emc_quse_brlshft1 << 22 >> 27) | (sdram->emc_quse_brlshft1 & 0x1F | 32 * (pmc->scratch186 >> 5)) & 0xFFFFFC1F) & 0xFFFF83FF) & 0xFFF07FFF) & 0xFF0FFFFF) & 0xFFFFFF; - pmc->scratch187 = (sdram->emc_pmacro_perbit_rfu1_ctrl0 << 10 >> 30 << 30) | (4 * ((sdram->emc_pmacro_perbit_rfu1_ctrl0 << 12 >> 30 << 28) | ((sdram->emc_pmacro_perbit_rfu1_ctrl0 << 14 >> 30 << 26) | ((sdram->emc_pmacro_perbit_rfu1_ctrl0 << 26 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu1_ctrl0 << 28 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu1_ctrl0 << 20) & 0x3FFFFF | ((sdram->emc_quse_brlshft2 << 12 >> 27 << 15) | ((sdram->emc_quse_brlshft2 << 17 >> 27 << 10) | (32 * (sdram->emc_quse_brlshft2 << 22 >> 27) | (sdram->emc_quse_brlshft2 & 0x1F | 32 * (pmc->scratch187 >> 5)) & 0xFFFFFC1F) & 0xFFFF83FF) & 0xFFF07FFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xCFFFFFFF) >> 2); - pmc->scratch188 = (sdram->emc_pmacro_perbit_rfu1_ctrl1 << 10 >> 30 << 30) | (4 * ((sdram->emc_pmacro_perbit_rfu1_ctrl1 << 12 >> 30 << 28) | ((sdram->emc_pmacro_perbit_rfu1_ctrl1 << 14 >> 30 << 26) | ((sdram->emc_pmacro_perbit_rfu1_ctrl1 << 26 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu1_ctrl1 << 28 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu1_ctrl1 << 20) & 0x3FFFFF | ((sdram->emc_quse_brlshft3 << 12 >> 27 << 15) | ((sdram->emc_quse_brlshft3 << 17 >> 27 << 10) | (32 * (sdram->emc_quse_brlshft3 << 22 >> 27) | (sdram->emc_quse_brlshft3 & 0x1F | 32 * (pmc->scratch188 >> 5)) & 0xFFFFFC1F) & 0xFFFF83FF) & 0xFFF07FFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF) & 0xCFFFFFFF) >> 2); - pmc->scratch189 = (sdram->emc_trefbw << 18) | ((sdram->emc_dbg >> 31 << 17) | ((2 * sdram->emc_dbg >> 31 << 16) | ((4 * sdram->emc_dbg >> 31 << 15) | ((8 * sdram->emc_dbg >> 31 << 14) | ((16 * sdram->emc_dbg >> 30 << 12) | ((sdram->emc_dbg << 6 >> 31 << 11) | ((sdram->emc_dbg << 7 >> 31 << 10) | ((sdram->emc_dbg << 18 >> 31 << 9) | ((sdram->emc_dbg << 19 >> 31 << 8) | ((sdram->emc_dbg << 20 >> 31 << 7) | ((sdram->emc_dbg << 21 >> 31 << 6) | (32 * (sdram->emc_dbg << 22 >> 31) | (16 * (sdram->emc_dbg << 27 >> 31) | (8 * (sdram->emc_dbg << 28 >> 31) | (4 * (sdram->emc_dbg << 29 >> 31) | (2 * (sdram->emc_dbg << 30 >> 31) | (sdram->emc_dbg & 1 | 2 * (pmc->scratch189 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFCFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0x3FFFF; - pmc->scratch191 = (sdram->emc_qpop << 9 >> 25 << 25) | ((sdram->emc_qpop << 18) | ((sdram->emc_zcal_wait_cnt >> 31 << 17) | ((sdram->emc_zcal_wait_cnt << 10 >> 26 << 11) | (sdram->emc_zcal_wait_cnt & 0x7FF | (pmc->scratch191 >> 11 << 11)) & 0xFFFE07FF) & 0xFFFDFFFF) & 0xFE03FFFF) & 0x1FFFFFF; - pmc->scratch192 = (sdram->emc_pmacro_tx_sel_clk_src4 << 6 >> 31 << 31) | (2 * ((sdram->emc_pmacro_auto_cal_common << 15 >> 31 << 30) | ((sdram->emc_pmacro_auto_cal_common << 18 >> 26 << 24) | ((sdram->emc_pmacro_auto_cal_common << 18) & 0xFFFFFF | ((sdram->emc_zcal_mrw_cmd >> 30 << 16) | ((sdram->emc_zcal_mrw_cmd << 8 >> 24 << 8) | (sdram->emc_zcal_mrw_cmd & 0xFF | (pmc->scratch192 >> 8 << 8)) & 0xFFFF00FF) & 0xFFFCFFFF) & 0xFF03FFFF) & 0xC0FFFFFF) & 0xBFFFFFFF) >> 1); - tmp = (sdram->emc_dll_cfg1 << 7 >> 31 << 17) | ((sdram->emc_dll_cfg1 << 10 >> 31 << 16) | ((sdram->emc_dll_cfg1 << 11 >> 31 << 15) | ((sdram->emc_dll_cfg1 << 14 >> 30 << 13) | ((sdram->emc_dll_cfg1 << 18 >> 31 << 12) | ((sdram->emc_dll_cfg1 << 19 >> 31 << 11) | ((pmc->scratch193 >> 11 << 11) | sdram->emc_dll_cfg1 & 0x7FF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFF9FFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF; - pmc->scratch193 = (sdram->emc_pmacro_tx_sel_clk_src5 << 31) | (2 * ((32 * sdram->emc_pmacro_tx_sel_clk_src4 >> 31 << 30) | ((sdram->emc_pmacro_perbit_rfu1_ctrl2 << 10 >> 30 << 28) | (((sdram->emc_pmacro_perbit_rfu1_ctrl2 << 14 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu1_ctrl2 << 26 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu1_ctrl2 << 28 >> 30 << 20) | ((sdram->emc_pmacro_perbit_rfu1_ctrl2 << 18) & 0xFFFFF | tmp & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF | (sdram->emc_pmacro_perbit_rfu1_ctrl2 << 12 >> 30 << 26)) & 0xCFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch194 = (sdram->emc_pmacro_tx_sel_clk_src5 << 29 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src5 << 30 >> 31 << 30) | ((sdram->emc_pmacro_perbit_rfu1_ctrl3 << 10 >> 30 << 28) | (((sdram->emc_pmacro_perbit_rfu1_ctrl3 << 14 >> 30 << 24) | (((sdram->emc_pmacro_perbit_rfu1_ctrl3 << 28 >> 30 << 20) | ((sdram->emc_pmacro_perbit_rfu1_ctrl3 << 18) & 0xFFFFF | ((sdram->emc_pmacro_cmd_brick_ctrl_fdpd << 14 >> 30 << 16) | ((sdram->emc_pmacro_cmd_brick_ctrl_fdpd << 16 >> 30 << 14) | ((sdram->emc_pmacro_cmd_brick_ctrl_fdpd << 18 >> 30 << 12) | ((sdram->emc_pmacro_cmd_brick_ctrl_fdpd << 20 >> 30 << 10) | ((sdram->emc_pmacro_cmd_brick_ctrl_fdpd << 22 >> 30 << 8) | ((sdram->emc_pmacro_cmd_brick_ctrl_fdpd << 24 >> 30 << 6) | (16 * (sdram->emc_pmacro_cmd_brick_ctrl_fdpd << 26 >> 30) | (4 * (sdram->emc_pmacro_cmd_brick_ctrl_fdpd << 28 >> 30) | (sdram->emc_pmacro_cmd_brick_ctrl_fdpd & 3 | 4 * (pmc->scratch194 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF | (sdram->emc_pmacro_perbit_rfu1_ctrl3 << 26 >> 30 << 22)) & 0xFCFFFFFF) & 0xF3FFFFFF | (sdram->emc_pmacro_perbit_rfu1_ctrl3 << 12 >> 30 << 26)) & 0xCFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch195 = (sdram->emc_pmacro_tx_sel_clk_src5 << 27 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src5 << 28 >> 31 << 30) | ((sdram->emc_pmacro_perbit_rfu1_ctrl4 << 10 >> 30 << 28) | (((sdram->emc_pmacro_perbit_rfu1_ctrl4 << 14 >> 30 << 24) | ((sdram->emc_pmacro_perbit_rfu1_ctrl4 << 26 >> 30 << 22) | ((sdram->emc_pmacro_perbit_rfu1_ctrl4 << 28 >> 30 << 20) | ((sdram->emc_pmacro_perbit_rfu1_ctrl4 << 18) & 0xFFFFF | ((sdram->emc_pmacro_data_brick_ctrl_fdpd << 14 >> 30 << 16) | ((sdram->emc_pmacro_data_brick_ctrl_fdpd << 16 >> 30 << 14) | ((sdram->emc_pmacro_data_brick_ctrl_fdpd << 18 >> 30 << 12) | ((sdram->emc_pmacro_data_brick_ctrl_fdpd << 20 >> 30 << 10) | ((sdram->emc_pmacro_data_brick_ctrl_fdpd << 22 >> 30 << 8) | ((sdram->emc_pmacro_data_brick_ctrl_fdpd << 24 >> 30 << 6) | (16 * (sdram->emc_pmacro_data_brick_ctrl_fdpd << 26 >> 30) | (4 * (sdram->emc_pmacro_data_brick_ctrl_fdpd << 28 >> 30) | (sdram->emc_pmacro_data_brick_ctrl_fdpd & 3 | 4 * (pmc->scratch195 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFCF) & 0xFFFFFF3F) & 0xFFFFFCFF) & 0xFFFFF3FF) & 0xFFFFCFFF) & 0xFFFF3FFF) & 0xFFFCFFFF) & 0xFFF3FFFF) & 0xFFCFFFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xF3FFFFFF | (sdram->emc_pmacro_perbit_rfu1_ctrl4 << 12 >> 30 << 26)) & 0xCFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch196 = (sdram->emc_emem_arb_refpb_bank_ctrl >> 31 << 31) | (2 * ((sdram->emc_emem_arb_refpb_bank_ctrl << 17 >> 25 << 24) | ((sdram->emc_emem_arb_refpb_bank_ctrl << 17) & 0xFFFFFF | ((sdram->emc_dyn_self_ref_control >> 31 << 16) | (sdram->emc_dyn_self_ref_control & 0xFFFF | (pmc->scratch196 >> 16 << 16)) & 0xFFFEFFFF) & 0xFF01FFFF) & 0x80FFFFFF) >> 1); - pmc->scratch197 = (sdram->emc_pmacro_tx_sel_clk_src5 << 24 >> 31 << 31) | (2 * ((sdram->emc_pmacro_tx_sel_clk_src5 << 25 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 26 >> 31 << 29) | ((sdram->emc_pmacro_perbit_rfu1_ctrl5 << 10 >> 30 << 27) | (((sdram->emc_pmacro_perbit_rfu1_ctrl5 << 14 >> 30 << 23) | ((sdram->emc_pmacro_perbit_rfu1_ctrl5 << 26 >> 30 << 21) | ((sdram->emc_pmacro_perbit_rfu1_ctrl5 << 28 >> 30 << 19) | ((sdram->emc_pmacro_perbit_rfu1_ctrl5 << 17) & 0x7FFFF | ((16 * sdram->emc_pmacro_cmd_pad_rx_ctrl >> 28 << 13) | ((sdram->emc_pmacro_cmd_pad_rx_ctrl << 8 >> 31 << 12) | ((sdram->emc_pmacro_cmd_pad_rx_ctrl << 9 >> 31 << 11) | ((sdram->emc_pmacro_cmd_pad_rx_ctrl << 10 >> 31 << 10) | ((sdram->emc_pmacro_cmd_pad_rx_ctrl << 12 >> 28 << 6) | (32 * (sdram->emc_pmacro_cmd_pad_rx_ctrl << 16 >> 31) | (16 * (sdram->emc_pmacro_cmd_pad_rx_ctrl << 19 >> 31) | (4 * (sdram->emc_pmacro_cmd_pad_rx_ctrl << 26 >> 30) | (sdram->emc_pmacro_cmd_pad_rx_ctrl & 3 | 4 * (pmc->scratch197 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFC3F) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFE1FFF) & 0xFFF9FFFF) & 0xFFE7FFFF) & 0xFF9FFFFF) & 0xFE7FFFFF) & 0xF9FFFFFF | (sdram->emc_pmacro_perbit_rfu1_ctrl5 << 12 >> 30 << 25)) & 0xE7FFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch198 = (sdram->emc_pmacro_cmd_pad_tx_ctrl << 31) | (2 * ((32 * sdram->emc_pmacro_tx_sel_clk_src5 >> 31 << 30) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 6 >> 31 << 29) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 7 >> 31 << 28) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 8 >> 31 << 27) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 9 >> 31 << 26) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 10 >> 31 << 25) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 11 >> 31 << 24) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 12 >> 31 << 23) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 13 >> 31 << 22) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 14 >> 31 << 21) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 15 >> 31 << 20) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 21 >> 31 << 19) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 22 >> 31 << 18) | ((sdram->emc_pmacro_tx_sel_clk_src5 << 23 >> 31 << 17) | ((16 * sdram->emc_pmacro_data_pad_rx_ctrl >> 28 << 13) | ((sdram->emc_pmacro_data_pad_rx_ctrl << 8 >> 31 << 12) | ((sdram->emc_pmacro_data_pad_rx_ctrl << 9 >> 31 << 11) | ((sdram->emc_pmacro_data_pad_rx_ctrl << 10 >> 31 << 10) | ((sdram->emc_pmacro_data_pad_rx_ctrl << 12 >> 28 << 6) | (32 * (sdram->emc_pmacro_data_pad_rx_ctrl << 16 >> 31) | (16 * (sdram->emc_pmacro_data_pad_rx_ctrl << 19 >> 31) | (4 * (sdram->emc_pmacro_data_pad_rx_ctrl << 26 >> 30) | (sdram->emc_pmacro_data_pad_rx_ctrl & 3 | 4 * (pmc->scratch198 >> 2)) & 0xFFFFFFF3) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFC3F) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFE1FFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch199 = (8 * sdram->emc_cmd_q >> 27 << 27) | ((sdram->emc_cmd_q << 17 >> 29 << 24) | ((sdram->emc_cmd_q << 21 >> 29 << 21) | ((sdram->emc_cmd_q << 16) & 0x1FFFFF | (((u16)(sdram->emc_refresh) << 16 >> 22 << 6) | (sdram->emc_refresh & 0x3F | (pmc->scratch199 >> 6 << 6)) & 0xFFFF003F) & 0xFFE0FFFF) & 0xFF1FFFFF) & 0xF8FFFFFF) & 0x7FFFFFF; - pmc->scratch210 = (sdram->emc_auto_cal_vref_sel1 << 16 >> 31 << 31) | (2 * ((sdram->emc_auto_cal_vref_sel1 << 17 >> 25 << 24) | ((sdram->emc_auto_cal_vref_sel1 << 24 >> 31 << 23) | ((sdram->emc_auto_cal_vref_sel1 << 16) & 0x7FFFFF | (sdram->emc_acpd_control & 0xFFFF | (pmc->scratch210 >> 16 << 16)) & 0xFF80FFFF) & 0xFF7FFFFF) & 0x80FFFFFF) >> 1); - tmp = 8 * (sdram->emc_pmacro_auto_cal_cfg0 << 28 >> 31) | (4 * (sdram->emc_pmacro_auto_cal_cfg0 << 29 >> 31) | (2 * (sdram->emc_pmacro_auto_cal_cfg0 << 30 >> 31) | (sdram->emc_pmacro_auto_cal_cfg0 & 1 | 2 * (pmc->scratch211 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7; - tmp = (sdram->emc_pmacro_auto_cal_cfg1 << 7 >> 31 << 28) | ((sdram->emc_pmacro_auto_cal_cfg1 << 12 >> 31 << 27) | ((sdram->emc_pmacro_auto_cal_cfg1 << 13 >> 31 << 26) | ((sdram->emc_pmacro_auto_cal_cfg1 << 14 >> 31 << 25) | ((sdram->emc_pmacro_auto_cal_cfg1 << 15 >> 31 << 24) | ((sdram->emc_pmacro_auto_cal_cfg1 << 20 >> 31 << 23) | ((sdram->emc_pmacro_auto_cal_cfg1 << 21 >> 31 << 22) | ((sdram->emc_pmacro_auto_cal_cfg1 << 22 >> 31 << 21) | ((sdram->emc_pmacro_auto_cal_cfg1 << 23 >> 31 << 20) | ((sdram->emc_pmacro_auto_cal_cfg1 << 28 >> 31 << 19) | ((sdram->emc_pmacro_auto_cal_cfg1 << 29 >> 31 << 18) | ((sdram->emc_pmacro_auto_cal_cfg1 << 30 >> 31 << 17) | ((sdram->emc_pmacro_auto_cal_cfg1 << 16) & 0x1FFFF | ((16 * sdram->emc_pmacro_auto_cal_cfg0 >> 31 << 15) | ((32 * sdram->emc_pmacro_auto_cal_cfg0 >> 31 << 14) | ((sdram->emc_pmacro_auto_cal_cfg0 << 6 >> 31 << 13) | ((sdram->emc_pmacro_auto_cal_cfg0 << 7 >> 31 << 12) | ((sdram->emc_pmacro_auto_cal_cfg0 << 12 >> 31 << 11) | ((sdram->emc_pmacro_auto_cal_cfg0 << 13 >> 31 << 10) | ((sdram->emc_pmacro_auto_cal_cfg0 << 14 >> 31 << 9) | ((sdram->emc_pmacro_auto_cal_cfg0 << 15 >> 31 << 8) | ((sdram->emc_pmacro_auto_cal_cfg0 << 20 >> 31 << 7) | ((sdram->emc_pmacro_auto_cal_cfg0 << 21 >> 31 << 6) | (32 * (sdram->emc_pmacro_auto_cal_cfg0 << 22 >> 31) | (16 * (sdram->emc_pmacro_auto_cal_cfg0 << 23 >> 31) | tmp & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF; - pmc->scratch211 = (16 * sdram->emc_pmacro_auto_cal_cfg1 >> 31 << 31) | (2 * ((32 * sdram->emc_pmacro_auto_cal_cfg1 >> 31 << 30) | ((sdram->emc_pmacro_auto_cal_cfg1 << 6 >> 31 << 29) | tmp & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->scratch212 = (sdram->emc_xm2_comp_pad_ctrl3 << 8 >> 28 << 28) | ((sdram->emc_xm2_comp_pad_ctrl3 << 14 >> 31 << 27) | ((sdram->emc_xm2_comp_pad_ctrl3 << 15 >> 31 << 26) | ((sdram->emc_xm2_comp_pad_ctrl3 << 16 >> 30 << 24) | ((sdram->emc_xm2_comp_pad_ctrl3 << 18 >> 30 << 22) | ((sdram->emc_xm2_comp_pad_ctrl3 << 26 >> 28 << 18) | ((sdram->emc_xm2_comp_pad_ctrl3 << 16) & 0x3FFFF | ((16 * sdram->emc_pmacro_auto_cal_cfg2 >> 31 << 15) | ((32 * sdram->emc_pmacro_auto_cal_cfg2 >> 31 << 14) | ((sdram->emc_pmacro_auto_cal_cfg2 << 6 >> 31 << 13) | ((sdram->emc_pmacro_auto_cal_cfg2 << 7 >> 31 << 12) | ((sdram->emc_pmacro_auto_cal_cfg2 << 12 >> 31 << 11) | ((sdram->emc_pmacro_auto_cal_cfg2 << 13 >> 31 << 10) | ((sdram->emc_pmacro_auto_cal_cfg2 << 14 >> 31 << 9) | ((sdram->emc_pmacro_auto_cal_cfg2 << 15 >> 31 << 8) | ((sdram->emc_pmacro_auto_cal_cfg2 << 20 >> 31 << 7) | ((sdram->emc_pmacro_auto_cal_cfg2 << 21 >> 31 << 6) | (32 * (sdram->emc_pmacro_auto_cal_cfg2 << 22 >> 31) | (16 * (sdram->emc_pmacro_auto_cal_cfg2 << 23 >> 31) | (8 * (sdram->emc_pmacro_auto_cal_cfg2 << 28 >> 31) | (4 * (sdram->emc_pmacro_auto_cal_cfg2 << 29 >> 31) | (2 * (sdram->emc_pmacro_auto_cal_cfg2 << 30 >> 31) | (sdram->emc_pmacro_auto_cal_cfg2 & 1 | 2 * (pmc->scratch212 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFCFFFF) & 0xFFC3FFFF) & 0xFF3FFFFF) & 0xFCFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xFFFFFFF; - pmc->scratch213 = ((u16)(sdram->emc_prerefresh_req_cnt) << 16) | (u16)(sdram->emc_cfg_dig_dll_period); - pmc->scratch214 = (sdram->emc_pmacro_data_pi_ctrl << 10 >> 26 << 26) | ((sdram->emc_pmacro_data_pi_ctrl << 19 >> 31 << 25) | ((sdram->emc_pmacro_data_pi_ctrl << 20 >> 28 << 21) | ((sdram->emc_pmacro_data_pi_ctrl << 27 >> 31 << 20) | ((sdram->emc_pmacro_data_pi_ctrl << 16) & 0xFFFFF | ((sdram->emc_pmacro_ddll_bypass >> 31 << 15) | ((2 * sdram->emc_pmacro_ddll_bypass >> 31 << 14) | ((4 * sdram->emc_pmacro_ddll_bypass >> 31 << 13) | ((16 * sdram->emc_pmacro_ddll_bypass >> 31 << 12) | ((32 * sdram->emc_pmacro_ddll_bypass >> 31 << 11) | ((sdram->emc_pmacro_ddll_bypass << 6 >> 31 << 10) | ((sdram->emc_pmacro_ddll_bypass << 7 >> 31 << 9) | ((sdram->emc_pmacro_ddll_bypass << 15 >> 31 << 8) | ((sdram->emc_pmacro_ddll_bypass << 16 >> 31 << 7) | ((sdram->emc_pmacro_ddll_bypass << 17 >> 31 << 6) | (32 * (sdram->emc_pmacro_ddll_bypass << 18 >> 31) | (16 * (sdram->emc_pmacro_ddll_bypass << 20 >> 31) | (8 * (sdram->emc_pmacro_ddll_bypass << 21 >> 31) | (4 * (sdram->emc_pmacro_ddll_bypass << 22 >> 31) | (2 * (sdram->emc_pmacro_ddll_bypass << 23 >> 31) | (sdram->emc_pmacro_ddll_bypass & 1 | 2 * (pmc->scratch214 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFF0FFFF) & 0xFFEFFFFF) & 0xFE1FFFFF) & 0xFDFFFFFF) & 0x3FFFFFF; - pmc->scratch215 = (sdram->emc_pmacro_cmd_pi_ctrl << 10 >> 26 << 10) | ((sdram->emc_pmacro_cmd_pi_ctrl << 19 >> 31 << 9) | (32 * (sdram->emc_pmacro_cmd_pi_ctrl << 20 >> 28) | (16 * (sdram->emc_pmacro_cmd_pi_ctrl << 27 >> 31) | (sdram->emc_pmacro_cmd_pi_ctrl & 0xF | 16 * (pmc->scratch215 >> 4)) & 0xFFFFFFEF) & 0xFFFFFE1F) & 0xFFFFFDFF) & 0xFFFF03FF; - tmp = (sdram->emc_pmacro_data_pad_tx_ctrl << 7 >> 31 << 24) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 8 >> 31 << 23) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 9 >> 31 << 22) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 10 >> 31 << 21) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 15 >> 31 << 20) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 16 >> 31 << 19) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 21 >> 31 << 18) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 25 >> 31 << 17) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 26 >> 31 << 16) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 15) & 0xFFFF | ((2 * sdram->emc_pmacro_cmd_pad_tx_ctrl >> 31 << 14) | ((4 * sdram->emc_pmacro_cmd_pad_tx_ctrl >> 31 << 13) | ((8 * sdram->emc_pmacro_cmd_pad_tx_ctrl >> 31 << 12) | ((16 * sdram->emc_pmacro_cmd_pad_tx_ctrl >> 31 << 11) | ((32 * sdram->emc_pmacro_cmd_pad_tx_ctrl >> 31 << 10) | ((sdram->emc_pmacro_cmd_pad_tx_ctrl << 6 >> 31 << 9) | ((sdram->emc_pmacro_cmd_pad_tx_ctrl << 7 >> 31 << 8) | ((sdram->emc_pmacro_cmd_pad_tx_ctrl << 8 >> 31 << 7) | ((sdram->emc_pmacro_cmd_pad_tx_ctrl << 9 >> 31 << 6) | (32 * (sdram->emc_pmacro_cmd_pad_tx_ctrl << 10 >> 31) | (16 * (sdram->emc_pmacro_cmd_pad_tx_ctrl << 15 >> 31) | (8 * (sdram->emc_pmacro_cmd_pad_tx_ctrl << 16 >> 31) | (4 * (sdram->emc_pmacro_cmd_pad_tx_ctrl << 21 >> 31) | (2 * (sdram->emc_pmacro_cmd_pad_tx_ctrl << 25 >> 31) | ((sdram->emc_pmacro_cmd_pad_tx_ctrl << 26 >> 31) | 2 * (pmc->scratch216 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF) & 0xFFFFFFBF) & 0xFFFFFF7F) & 0xFFFFFEFF) & 0xFFFFFDFF) & 0xFFFFFBFF) & 0xFFFFF7FF) & 0xFFFFEFFF) & 0xFFFFDFFF) & 0xFFFFBFFF) & 0xFFFF7FFF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFFBFFFF) & 0xFFF7FFFF) & 0xFFEFFFFF) & 0xFFDFFFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF; - - s(emc_pin_gpio, 1:0, scratch9, 31:30); - s(emc_pin_gpio_enable, 1:0, scratch10, 31:30); - s(emc_dev_select, 1:0, scratch11, 31:30); - s(emc_zcal_warm_cold_boot_enables, 1:0, scratch12, 31:30); - s(emc_cfg_dig_dll_period_warm_boot, 1:0, scratch13, 31:30); - s32(emc_bct_spare13, scratch45); - s32(emc_bct_spare12, scratch46); - s32(emc_bct_spare7, scratch47); - s32(emc_bct_spare6, scratch48); - s32(emc_bct_spare5, scratch50); - s32(emc_bct_spare4, scratch51); - s32(emc_bct_spare3, scratch56); - s32(emc_bct_spare2, scratch57); - s32(emc_bct_spare1, scratch58); - s32(emc_bct_spare0, scratch59); - s32(emc_bct_spare9, scratch60); - s32(emc_bct_spare8, scratch61); - s32(boot_rom_patch_data, scratch62); - s32(boot_rom_patch_control, scratch63); - s(mc_clken_override_allwarm_boot, 0:0, scratch65, 31:31); - pmc->scratch66 = pmc->scratch66 & 0x1FFFFFFF | ((u8)(sdram->emc_extra_refresh_num) << 29); - pmc->scratch72 = pmc->scratch72 & 0x8FFFFFFF | ((u16)(sdram->pmc_io_dpd3_req_wait) << 28) & 0x70000000; - pmc->scratch72 = ((2 * pmc->scratch72) >> 1) | ((u16)(sdram->emc_clken_override_allwarm_boot) << 31); - pmc->scratch73 = pmc->scratch73 & 0x8FFFFFFF | ((u8)(sdram->memory_type) << 28) & 0x70000000; - pmc->scratch73 = ((2 * pmc->scratch73) >> 1) | (sdram->emc_mrs_warm_boot_enable << 31); - pmc->scratch74 = pmc->scratch74 & 0x8FFFFFFF | (sdram->pmc_io_dpd4_req_wait << 28) & 0x70000000; - pmc->scratch74 = ((2 * pmc->scratch74) >> 1) | (sdram->clear_clock2_mc1 << 31); - pmc->scratch75 = pmc->scratch75 & 0xEFFFFFFF | (sdram->emc_warm_boot_extramode_reg_write_enable << 28) & 0x10000000; - pmc->scratch75 = pmc->scratch75 & 0xDFFFFFFF | (sdram->clk_rst_pllm_misc20_override_enable << 29) & 0x20000000; - pmc->scratch75 = pmc->scratch75 & 0xBFFFFFFF | ((u16)(sdram->emc_dbg_write_mux) << 30) & 0x40000000; - pmc->scratch75 = ((2 * pmc->scratch75) >> 1) | ((u16)(sdram->ahb_arbitration_xbar_ctrl_meminit_done) << 31); - pmc->scratch90 = pmc->scratch90 & 0xFFFFFF | (sdram->emc_timing_control_wait << 24); - pmc->scratch91 = pmc->scratch91 & 0xFFFFFF | (sdram->emc_zcal_warm_boot_wait << 24); - pmc->scratch92 = pmc->scratch92 & 0xFFFFFF | (sdram->warm_boot_wait << 24); - pmc->scratch93 = pmc->scratch93 & 0xFFFFFF | ((u16)(sdram->emc_pin_program_wait) << 24); - pmc->scratch114 = pmc->scratch114 & 0x3FFFFF | ((u16)(sdram->emc_auto_cal_wait) << 22); - pmc->scratch215 = (u16)pmc->scratch215 | ((u16)(sdram->swizzle_rank_byte_encode) << 16); - pmc->scratch216 = (2 * sdram->emc_pmacro_data_pad_tx_ctrl >> 31 << 30) | ((4 * sdram->emc_pmacro_data_pad_tx_ctrl >> 31 << 29) | ((8 * sdram->emc_pmacro_data_pad_tx_ctrl >> 31 << 28) | ((16 * sdram->emc_pmacro_data_pad_tx_ctrl >> 31 << 27) | ((32 * sdram->emc_pmacro_data_pad_tx_ctrl >> 31 << 26) | ((sdram->emc_pmacro_data_pad_tx_ctrl << 6 >> 31 << 25) | tmp & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF; - s(emc_mrw_lpddr2zcal_warm_boot, 23:16, scratch5, 7:0); - s(emc_mrw_lpddr2zcal_warm_boot, 7:0, scratch5, 15:8); - s(emc_warm_boot_mrw_extra, 23:16, scratch5, 23:16); - s(emc_warm_boot_mrw_extra, 7:0, scratch5, 31:24); - s(emc_mrw_lpddr2zcal_warm_boot, 31:30, scratch6, 1:0); - s(emc_warm_boot_mrw_extra, 31:30, scratch6, 3:2); - s(emc_mrw_lpddr2zcal_warm_boot, 27:26, scratch6, 5:4); - s(emc_warm_boot_mrw_extra, 27:26, scratch6, 7:6); - s(emc_mrw6, 27:0, scratch8, 27:0); - s(emc_mrw6, 31:30, scratch8, 29:28); - s(emc_mrw8, 27:0, scratch9, 27:0); - s(emc_mrw8, 31:30, scratch9, 29:28); - s(emc_mrw9, 27:0, scratch10, 27:0); - s(emc_mrw9, 31:30, scratch10, 29:28); - s(emc_mrw10, 27:0, scratch11, 27:0); - s(emc_mrw10, 31:30, scratch11, 29:28); - s(emc_mrw12, 27:0, scratch12, 27:0); - s(emc_mrw12, 31:30, scratch12, 29:28); - s(emc_mrw13, 27:0, scratch13, 27:0); - s(emc_mrw13, 31:30, scratch13, 29:28); - s(emc_mrw14, 27:0, scratch14, 27:0); - s(emc_mrw14, 31:30, scratch14, 29:28); - s(emc_mrw1, 7:0, scratch15, 7:0); - s(emc_mrw1, 23:16, scratch15, 15:8); - s(emc_mrw1, 27:26, scratch15, 17:16); - s(emc_mrw1, 31:30, scratch15, 19:18); - s(emc_warm_boot_mrw_extra, 7:0, scratch16, 7:0); - s(emc_warm_boot_mrw_extra, 23:16, scratch16, 15:8); - s(emc_warm_boot_mrw_extra, 27:26, scratch16, 17:16); - s(emc_warm_boot_mrw_extra, 31:30, scratch16, 19:18); - s(emc_mrw2, 7:0, scratch17, 7:0); - s(emc_mrw2, 23:16, scratch17, 15:8); - s(emc_mrw2, 27:26, scratch17, 17:16); - s(emc_mrw2, 31:30, scratch17, 19:18); - pmc->scratch18 = (sdram->emc_mrw3 >> 30 << 18) | ((16 * sdram->emc_mrw3 >> 31 << 17) | ((32 * sdram->emc_mrw3 >> 31 << 16) | ((sdram->emc_mrw3 << 8 >> 24 << 8) | ((u8)sdram->emc_mrw3 | (pmc->scratch18 >> 8 << 8)) & 0xFFFF00FF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFF3FFFF; - pmc->scratch19 = (sdram->emc_mrw4 >> 30 << 18) | ((16 * sdram->emc_mrw4 >> 31 << 17) | ((32 * sdram->emc_mrw4 >> 31 << 16) | ((sdram->emc_mrw4 << 8 >> 24 << 8) | ((u8)sdram->emc_mrw4 | (pmc->scratch19 >> 8 << 8)) & 0xFFFF00FF) & 0xFFFEFFFF) & 0xFFFDFFFF) & 0xFFF3FFFF; - s32(emc_cmd_mapping_byte, secure_scratch8); - s32(emc_pmacro_brick_mapping0, secure_scratch9); - s32(emc_pmacro_brick_mapping1, secure_scratch10); - s32(emc_pmacro_brick_mapping2, secure_scratch11); - s32(mc_video_protect_gpu_override0, secure_scratch12); - pmc->secure_scratch13 = ((u16)(sdram->emc_adr_cfg) << 31) | (2 * ((((u16)(sdram->mc_untranslated_region_check) << 22) >> 31 << 30) | ((((u16)(sdram->mc_untranslated_region_check) << 23) >> 31 << 29) | (((u16)(sdram->mc_untranslated_region_check) << 28) & 0x1FFFFFFF | ((2 * sdram->emc_cmd_mapping_cmd0_0 >> 25 << 21) | ((sdram->emc_cmd_mapping_cmd0_0 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd0_0 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd0_0 & 0x7F | (pmc->secure_scratch13 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->secure_scratch14 = (sdram->mc_video_protect_write_access << 30 >> 31 << 31) | (2 * ((sdram->mc_video_protect_write_access << 30) | ((sdram->mc_video_protect_bom_adr_hi << 30 >> 2) | ((2 * sdram->emc_cmd_mapping_cmd0_1 >> 25 << 21) | ((sdram->emc_cmd_mapping_cmd0_1 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd0_1 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd0_1 & 0x7F | (pmc->secure_scratch14 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xCFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->secure_scratch15 = ((u16)(sdram->mc_mts_carveout_adr_hi) << 30) | (4 * ((sdram->mc_sec_carveout_adr_hi << 28) | ((2 * sdram->emc_cmd_mapping_cmd1_0 >> 25 << 21) | ((sdram->emc_cmd_mapping_cmd1_0 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd1_0 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd1_0 & 0x7F | (pmc->secure_scratch15 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xCFFFFFFF) >> 2); - pmc->secure_scratch16 = (sdram->mc_generalized_carveout3_bom_hi << 30) | (4 * ((sdram->mc_generalized_carveout5_bom_hi << 28) | ((2 * sdram->emc_cmd_mapping_cmd1_1 >> 25 << 21) | ((sdram->emc_cmd_mapping_cmd1_1 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd1_1 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd1_1 & 0x7F | (pmc->secure_scratch16 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xCFFFFFFF) >> 2); - pmc->secure_scratch17 = ((u16)(sdram->mc_generalized_carveout4_bom_hi) << 30) | (4 * (((u16)(sdram->mc_generalized_carveout2_bom_hi) << 28) | ((2 * sdram->emc_cmd_mapping_cmd2_0 >> 25 << 21) | ((sdram->emc_cmd_mapping_cmd2_0 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd2_0 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd2_0 & 0x7F | (pmc->secure_scratch17 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xCFFFFFFF) >> 2); - pmc->secure_scratch18 = (sdram->emc_fbio_cfg8 << 16 >> 31 << 31) | (2 * (((u16)(sdram->emc_fbio_spare) << 30 >> 31 << 30) | ((sdram->mc_generalized_carveout1_bom_hi << 30 >> 2) | ((2 * sdram->emc_cmd_mapping_cmd2_1 >> 25 << 21) | ((sdram->emc_cmd_mapping_cmd2_1 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd2_1 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd2_1 & 0x7F | (pmc->secure_scratch18 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xCFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->secure_scratch19 = (sdram->mc_video_protect_vpr_override << 31) | (2 * (((u16)(sdram->mc_mts_carveout_reg_ctrl) << 30) | ((sdram->mc_sec_carveout_protect_write_access << 31 >> 2) | (((u16)(sdram->mc_emem_adr_cfg) << 28) & 0x1FFFFFFF | ((2 * sdram->emc_cmd_mapping_cmd3_0 >> 25 << 21) | ((sdram->emc_cmd_mapping_cmd3_0 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd3_0 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd3_0 & 0x7F | (pmc->secure_scratch19 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->secure_scratch20 = (sdram->mc_generalized_carveout2_cfg0 << 25 >> 28 << 28) | ((2 * sdram->emc_cmd_mapping_cmd3_1 >> 25 << 21) | ((sdram->emc_cmd_mapping_cmd3_1 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd3_1 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd3_1 & 0x7F | (pmc->secure_scratch20 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xF01FFFFF) & 0xFFFFFFF; - pmc->secure_scratch39 = (sdram->mc_video_protect_vpr_override << 30 >> 31 << 31) | (2 * ((sdram->mc_generalized_carveout2_cfg0 << 21 >> 28 << 27) | ((32 * sdram->mc_generalized_carveout4_cfg0 >> 31 << 26) | ((sdram->mc_generalized_carveout4_cfg0 << 6 >> 31 << 25) | ((sdram->mc_generalized_carveout4_cfg0 << 7 >> 31 << 24) | ((sdram->mc_generalized_carveout4_cfg0 << 8 >> 31 << 23) | ((sdram->mc_generalized_carveout4_cfg0 << 9 >> 31 << 22) | ((sdram->mc_generalized_carveout4_cfg0 << 10 >> 28 << 18) | ((sdram->mc_generalized_carveout4_cfg0 << 14 >> 28 << 14) | ((sdram->mc_generalized_carveout4_cfg0 << 18 >> 29 << 11) | ((sdram->mc_generalized_carveout4_cfg0 << 21 >> 28 << 7) | (8 * (sdram->mc_generalized_carveout4_cfg0 << 25 >> 28) | (4 * (sdram->mc_generalized_carveout4_cfg0 << 29 >> 31) | (2 * (sdram->mc_generalized_carveout4_cfg0 << 30 >> 31) | (sdram->mc_generalized_carveout4_cfg0 & 1 | 2 * (pmc->secure_scratch39 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFF87) & 0xFFFFF87F) & 0xFFFFC7FF) & 0xFFFC3FFF) & 0xFFC3FFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0x87FFFFFF) >> 1); - pmc->secure_scratch40 = (sdram->mc_video_protect_vpr_override << 29 >> 31 << 31) | (2 * ((sdram->mc_generalized_carveout2_cfg0 << 14 >> 28 << 27) | ((32 * sdram->mc_generalized_carveout5_cfg0 >> 31 << 26) | ((sdram->mc_generalized_carveout5_cfg0 << 6 >> 31 << 25) | ((sdram->mc_generalized_carveout5_cfg0 << 7 >> 31 << 24) | ((sdram->mc_generalized_carveout5_cfg0 << 8 >> 31 << 23) | ((sdram->mc_generalized_carveout5_cfg0 << 9 >> 31 << 22) | ((sdram->mc_generalized_carveout5_cfg0 << 10 >> 28 << 18) | ((sdram->mc_generalized_carveout5_cfg0 << 14 >> 28 << 14) | ((sdram->mc_generalized_carveout5_cfg0 << 18 >> 29 << 11) | ((sdram->mc_generalized_carveout5_cfg0 << 21 >> 28 << 7) | (8 * (sdram->mc_generalized_carveout5_cfg0 << 25 >> 28) | (4 * (sdram->mc_generalized_carveout5_cfg0 << 29 >> 31) | (2 * (sdram->mc_generalized_carveout5_cfg0 << 30 >> 31) | (sdram->mc_generalized_carveout5_cfg0 & 1 | 2 * (pmc->secure_scratch40 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFF87) & 0xFFFFF87F) & 0xFFFFC7FF) & 0xFFFC3FFF) & 0xFFC3FFFF) & 0xFFBFFFFF) & 0xFF7FFFFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0x87FFFFFF) >> 1); - pmc->secure_scratch41 = (sdram->mc_generalized_carveout2_cfg0 << 18 >> 29 << 29) | ((sdram->mc_generalized_carveout2_cfg0 << 10 >> 28 << 25) | ((16 * sdram->emc_cmd_mapping_cmd0_2 >> 28 << 21) | ((sdram->emc_cmd_mapping_cmd0_2 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd0_2 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd0_2 & 0x7F | (pmc->secure_scratch41 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xFE1FFFFF) & 0xE1FFFFFF) & 0x1FFFFFFF; - pmc->secure_scratch42 = ((u16)(sdram->mc_generalized_carveout1_cfg0) << 18 >> 29 << 29) | (((u16)(sdram->mc_generalized_carveout1_cfg0) << 25 >> 28 << 25) | ((16 * sdram->emc_cmd_mapping_cmd1_2 >> 28 << 21) | ((sdram->emc_cmd_mapping_cmd1_2 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd1_2 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd1_2 & 0x7F | (pmc->secure_scratch42 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xFE1FFFFF) & 0xE1FFFFFF) & 0x1FFFFFFF; - pmc->secure_scratch43 = ((u16)(sdram->mc_generalized_carveout3_cfg0) << 18 >> 29 << 29) | (((u16)(sdram->mc_generalized_carveout1_cfg0) << 21 >> 28 << 25) | ((16 * sdram->emc_cmd_mapping_cmd2_2 >> 28 << 21) | ((sdram->emc_cmd_mapping_cmd2_2 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd2_2 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd2_2 & 0x7F | (pmc->secure_scratch43 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xFE1FFFFF) & 0xE1FFFFFF) & 0x1FFFFFFF; - pmc->secure_scratch44 = (sdram->mc_video_protect_vpr_override << 24 >> 31 << 31) | (2 * ((sdram->mc_video_protect_vpr_override << 25 >> 31 << 30) | ((sdram->mc_video_protect_vpr_override << 28 >> 31 << 29) | ((sdram->mc_generalized_carveout1_cfg0 << 14 >> 28 << 25) | ((16 * sdram->emc_cmd_mapping_cmd3_2 >> 28 << 21) | ((sdram->emc_cmd_mapping_cmd3_2 << 9 >> 25 << 14) | ((sdram->emc_cmd_mapping_cmd3_2 << 17 >> 25 << 7) | (sdram->emc_cmd_mapping_cmd3_2 & 0x7F | (pmc->secure_scratch44 >> 7 << 7)) & 0xFFFFC07F) & 0xFFE03FFF) & 0xFE1FFFFF) & 0xE1FFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - s(mc_emem_adr_cfg_channel_mask, 31:9, secure_scratch45, 22:0); - s(mc_emem_adr_cfg_dev0, 2:0, secure_scratch45, 25:23); - s(mc_emem_adr_cfg_dev0, 9:8, secure_scratch45, 27:26); - s(mc_emem_adr_cfg_dev0, 19:16, secure_scratch45, 31:28); - pmc->secure_scratch46 = (sdram->mc_video_protect_vpr_override << 23 >> 31 << 31) | (2 * ((sdram->mc_emem_adr_cfg_dev1 << 12 >> 28 << 27) | ((sdram->mc_emem_adr_cfg_dev1 << 22 >> 30 << 25) | ((sdram->mc_emem_adr_cfg_dev1 << 22) & 0x1FFFFFF | ((sdram->mc_emem_adr_cfg_bank_mask0 >> 10) | (pmc->secure_scratch46 >> 22 << 22)) & 0xFE3FFFFF) & 0xF9FFFFFF) & 0x87FFFFFF) >> 1); - pmc->secure_scratch47 = (sdram->mc_video_protect_vpr_override << 20 >> 31 << 31) | (2 * ((sdram->mc_video_protect_vpr_override << 22 >> 31 << 30) | (((u8)(sdram->mc_generalized_carveout3_cfg0) << 25 >> 28 << 26) | ((sdram->mc_generalized_carveout1_cfg0 << 10 >> 28 << 22) | ((sdram->mc_emem_adr_cfg_bank_mask1 >> 10) | (pmc->secure_scratch47 >> 22 << 22)) & 0xFC3FFFFF) & 0xC3FFFFFF) & 0xBFFFFFFF) >> 1); - pmc->secure_scratch48 = (sdram->mc_video_protect_vpr_override << 16 >> 31 << 31) | (2 * ((sdram->mc_video_protect_vpr_override << 17 >> 31 << 30) | ((sdram->mc_generalized_carveout3_cfg0 << 14 >> 28 << 26) | ((sdram->mc_generalized_carveout3_cfg0 << 21 >> 28 << 22) | ((sdram->mc_emem_adr_cfg_bank_mask2 >> 10) | (pmc->secure_scratch48 >> 22 << 22)) & 0xFC3FFFFF) & 0xC3FFFFFF) & 0xBFFFFFFF) >> 1); - pmc->secure_scratch49 = (sdram->mc_video_protect_vpr_override << 14 >> 31 << 31) | (2 * ((sdram->mc_emem_cfg >> 31 << 30) | ((sdram->mc_emem_cfg << 18 >> 2) | (sdram->mc_video_protect_gpu_override1 & 0xFFFF | (pmc->secure_scratch49 >> 16 << 16)) & 0xC000FFFF) & 0xBFFFFFFF) >> 1); - pmc->secure_scratch50 = (sdram->mc_video_protect_vpr_override << 12 >> 31 << 31) | (2 * ((sdram->mc_video_protect_vpr_override << 13 >> 31 << 30) | ((sdram->mc_generalized_carveout1_bom >> 17 << 15) | ((sdram->mc_generalized_carveout3_bom >> 17) | (pmc->secure_scratch50 >> 15 << 15)) & 0xC0007FFF) & 0xBFFFFFFF) >> 1); - pmc->secure_scratch51 = (sdram->mc_video_protect_vpr_override << 10 >> 31 << 31) | (2 * ((sdram->mc_video_protect_vpr_override << 11 >> 31 << 30) | ((sdram->mc_generalized_carveout2_bom >> 17 << 15) | ((sdram->mc_generalized_carveout4_bom >> 17) | (pmc->secure_scratch51 >> 15 << 15)) & 0xC0007FFF) & 0xBFFFFFFF) >> 1); - pmc->secure_scratch52 = (sdram->mc_video_protect_vpr_override << 9 >> 31 << 31) | (2 * ((sdram->mc_generalized_carveout3_cfg0 << 10 >> 28 << 27) | ((sdram->mc_video_protect_bom >> 20 << 15) | ((sdram->mc_generalized_carveout5_bom >> 17) | (pmc->secure_scratch52 >> 15 << 15)) & 0xF8007FFF) & 0x87FFFFFF) >> 1); - pmc->secure_scratch53 = (sdram->mc_video_protect_vpr_override1 << 27 >> 31 << 31) | (2 * ((sdram->mc_video_protect_vpr_override1 << 30 >> 31 << 30) | ((sdram->mc_video_protect_vpr_override1 << 31 >> 2) | ((sdram->mc_video_protect_vpr_override >> 31 << 28) | ((2 * sdram->mc_video_protect_vpr_override >> 31 << 27) | ((4 * sdram->mc_video_protect_vpr_override >> 31 << 26) | ((32 * sdram->mc_video_protect_vpr_override >> 31 << 25) | ((sdram->mc_video_protect_vpr_override << 8 >> 31 << 24) | ((sdram->mc_sec_carveout_bom >> 20 << 12) | (sdram->mc_video_protect_size_mb & 0xFFF | (pmc->secure_scratch53 >> 12 << 12)) & 0xFF000FFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->secure_scratch54 = (sdram->mc_video_protect_vpr_override1 << 19 >> 31 << 31) | (2 * ((sdram->mc_video_protect_vpr_override1 << 20 >> 31 << 30) | ((sdram->mc_video_protect_vpr_override1 << 21 >> 31 << 29) | ((sdram->mc_video_protect_vpr_override1 << 22 >> 31 << 28) | ((sdram->mc_video_protect_vpr_override1 << 23 >> 31 << 27) | ((sdram->mc_video_protect_vpr_override1 << 24 >> 31 << 26) | ((sdram->mc_video_protect_vpr_override1 << 25 >> 31 << 25) | ((sdram->mc_video_protect_vpr_override1 << 26 >> 31 << 24) | ((sdram->mc_mts_carveout_bom >> 20 << 12) | (sdram->mc_sec_carveout_size_mb & 0xFFF | (pmc->secure_scratch54 >> 12 << 12)) & 0xFF000FFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->secure_scratch55 = (sdram->mc_generalized_carveout2_cfg0 << 30 >> 31 << 31) | (2 * ((sdram->mc_generalized_carveout2_cfg0 << 30) | ((32 * sdram->mc_video_protect_vpr_override1 >> 31 << 29) | ((sdram->mc_video_protect_vpr_override1 << 6 >> 31 << 28) | ((sdram->mc_video_protect_vpr_override1 << 15 >> 31 << 27) | ((sdram->mc_video_protect_vpr_override1 << 16 >> 31 << 26) | ((sdram->mc_video_protect_vpr_override1 << 17 >> 31 << 25) | ((sdram->mc_video_protect_vpr_override1 << 18 >> 31 << 24) | (((u16)(sdram->mc_generalized_carveout4_size_128kb) << 12) & 0xFFFFFF | (sdram->mc_mts_carveout_size_mb & 0xFFF | (pmc->secure_scratch55 >> 12 << 12)) & 0xFF000FFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->secure_scratch56 = ((u16)(sdram->mc_generalized_carveout1_cfg0) << 30 >> 31 << 31) | (2 * (((u16)(sdram->mc_generalized_carveout1_cfg0) << 30) | ((32 * sdram->mc_generalized_carveout2_cfg0 >> 31 << 29) | ((sdram->mc_generalized_carveout2_cfg0 << 6 >> 31 << 28) | ((sdram->mc_generalized_carveout2_cfg0 << 7 >> 31 << 27) | ((sdram->mc_generalized_carveout2_cfg0 << 8 >> 31 << 26) | ((sdram->mc_generalized_carveout2_cfg0 << 9 >> 31 << 25) | ((sdram->mc_generalized_carveout2_cfg0 << 29 >> 31 << 24) | (((u16)(sdram->mc_generalized_carveout2_size_128kb) << 12) & 0xFFFFFF | (sdram->mc_generalized_carveout3_size_128kb & 0xFFF | (pmc->secure_scratch56 >> 12 << 12)) & 0xFF000FFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - pmc->secure_scratch57 = ((u8)(sdram->mc_generalized_carveout3_cfg0) << 30 >> 31 << 31) | (2 * (((u8)(sdram->mc_generalized_carveout3_cfg0) << 30) | ((32 * sdram->mc_generalized_carveout1_cfg0 >> 31 << 29) | ((sdram->mc_generalized_carveout1_cfg0 << 6 >> 31 << 28) | ((sdram->mc_generalized_carveout1_cfg0 << 7 >> 31 << 27) | ((sdram->mc_generalized_carveout1_cfg0 << 8 >> 31 << 26) | ((sdram->mc_generalized_carveout1_cfg0 << 9 >> 31 << 25) | ((sdram->mc_generalized_carveout1_cfg0 << 29 >> 31 << 24) | ((sdram->mc_generalized_carveout5_size_128kb << 12) & 0xFFFFFF | (sdram->mc_generalized_carveout1_size_128kb & 0xFFF | (pmc->secure_scratch57 >> 12 << 12)) & 0xFF000FFF) & 0xFEFFFFFF) & 0xFDFFFFFF) & 0xFBFFFFFF) & 0xF7FFFFFF) & 0xEFFFFFFF) & 0xDFFFFFFF) & 0xBFFFFFFF) >> 1); - - s32(mc_generalized_carveout1_access0, secure_scratch59); - s32(mc_generalized_carveout1_access1, secure_scratch60); - s32(mc_generalized_carveout1_access2, secure_scratch61); - s32(mc_generalized_carveout1_access3, secure_scratch62); - s32(mc_generalized_carveout1_access4, secure_scratch63); - s32(mc_generalized_carveout2_access0, secure_scratch64); - s32(mc_generalized_carveout2_access1, secure_scratch65); - s32(mc_generalized_carveout2_access2, secure_scratch66); - s32(mc_generalized_carveout2_access3, secure_scratch67); - s32(mc_generalized_carveout2_access4, secure_scratch68); - s32(mc_generalized_carveout3_access0, secure_scratch69); - s32(mc_generalized_carveout3_access1, secure_scratch70); - s32(mc_generalized_carveout3_access2, secure_scratch71); - s32(mc_generalized_carveout3_access3, secure_scratch72); - s32(mc_generalized_carveout3_access4, secure_scratch73); - s32(mc_generalized_carveout4_access0, secure_scratch74); - s32(mc_generalized_carveout4_access1, secure_scratch75); - s32(mc_generalized_carveout4_access2, secure_scratch76); - s32(mc_generalized_carveout4_access3, secure_scratch77); - s32(mc_generalized_carveout4_access4, secure_scratch78); - s32(mc_generalized_carveout5_access0, secure_scratch79); - s32(mc_generalized_carveout5_access1, secure_scratch80); - s32(mc_generalized_carveout5_access2, secure_scratch81); - s32(mc_generalized_carveout5_access3, secure_scratch82); - s32(mc_generalized_carveout1_force_internal_access0, secure_scratch84); - s32(mc_generalized_carveout1_force_internal_access1, secure_scratch85); - s32(mc_generalized_carveout1_force_internal_access2, secure_scratch86); - s32(mc_generalized_carveout1_force_internal_access3, secure_scratch87); - s32(mc_generalized_carveout1_force_internal_access4, secure_scratch88); - s32(mc_generalized_carveout2_force_internal_access0, secure_scratch89); - s32(mc_generalized_carveout2_force_internal_access1, secure_scratch90); - s32(mc_generalized_carveout2_force_internal_access2, secure_scratch91); - s32(mc_generalized_carveout2_force_internal_access3, secure_scratch92); - s32(mc_generalized_carveout2_force_internal_access4, secure_scratch93); - s32(mc_generalized_carveout3_force_internal_access0, secure_scratch94); - s32(mc_generalized_carveout3_force_internal_access1, secure_scratch95); - s32(mc_generalized_carveout3_force_internal_access2, secure_scratch96); - s32(mc_generalized_carveout3_force_internal_access3, secure_scratch97); - s32(mc_generalized_carveout3_force_internal_access4, secure_scratch98); - s32(mc_generalized_carveout4_force_internal_access0, secure_scratch99); - s32(mc_generalized_carveout4_force_internal_access1, secure_scratch100); - s32(mc_generalized_carveout4_force_internal_access2, secure_scratch101); - s32(mc_generalized_carveout4_force_internal_access3, secure_scratch102); - s32(mc_generalized_carveout4_force_internal_access4, secure_scratch103); - s32(mc_generalized_carveout5_force_internal_access0, secure_scratch104); - s32(mc_generalized_carveout5_force_internal_access1, secure_scratch105); - s32(mc_generalized_carveout5_force_internal_access2, secure_scratch106); - s32(mc_generalized_carveout5_force_internal_access3, secure_scratch107); - - pmc->secure_scratch58 = 32 * (32 * sdram->mc_generalized_carveout3_cfg0 >> 31) | (16 * (sdram->mc_generalized_carveout3_cfg0 << 6 >> 31) | (8 * (sdram->mc_generalized_carveout3_cfg0 << 7 >> 31) | (4 * (sdram->mc_generalized_carveout3_cfg0 << 8 >> 31) | (2 * (sdram->mc_generalized_carveout3_cfg0 << 9 >> 31) | ((sdram->mc_generalized_carveout3_cfg0 << 29 >> 31) | 2 * (pmc->secure_scratch58 >> 1)) & 0xFFFFFFFD) & 0xFFFFFFFB) & 0xFFFFFFF7) & 0xFFFFFFEF) & 0xFFFFFFDF; - - c32(0, scratch2); - s(pllm_input_divider, 7:0, scratch2, 7:0); - s(pllm_feedback_divider, 7:0, scratch2, 15:8); - s(pllm_post_divider, 4:0, scratch2, 20:16); - s(pllm_kvco, 0:0, scratch2, 17:17); - s(pllm_kcp, 1:0, scratch2, 19:18); - - c32(0, scratch35); - s(pllm_setup_control, 15:0, scratch35, 15:0); - - c32(0, scratch3); - s(pllm_input_divider, 7:0, scratch3, 7:0); - c(0x3e, scratch3, 15:8); - c(0, scratch3, 20:16); - s(pllm_kvco, 0:0, scratch3, 21:21); - s(pllm_kcp, 1:0, scratch3, 23:22); - - c32(0, scratch36); - s(pllm_setup_control, 23:0, scratch36, 23:0); - - c32(0, scratch4); - s(pllm_stable_time, 9:0, scratch4, 9:0); // s32(pllm_stable_time, scratch4);, s(pllm_stable_time, 31:0, scratch4, 31:10); - s(pllm_stable_time, 31:0, scratch4, 31:10); -} - -#pragma GCC diagnostic pop - -void sdram_lp0_save_params(const void *params) -{ - u32 chip_id = (APB_MISC(APB_MISC_GP_HIDREV) >> 4) & 0xF; - - if (chip_id != GP_HIDREV_MAJOR_T210B01) - _sdram_lp0_save_params_t210(params); - else - _sdram_lp0_save_params_t210b01(params); -} diff --git a/bdk/mem/sdram_lp0_param_t210.h b/bdk/mem/sdram_lp0_param_t210.h deleted file mode 100644 index 09e960e..0000000 --- a/bdk/mem/sdram_lp0_param_t210.h +++ /dev/null @@ -1,964 +0,0 @@ -/* - * Copyright (c) 2013-2015, NVIDIA CORPORATION. All rights reserved. - * Copyright 2014 Google Inc. - * Copyright (c) 2018 CTCaer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -/** - * Defines the SDRAM parameter structure. - * - * Note that PLLM is used by EMC. The field names are in camel case to ease - * directly converting BCT config files (*.cfg) into C structure. - */ - -#ifndef __TEGRA210_SDRAM_PARAM_H__ -#define __TEGRA210_SDRAM_PARAM_H__ - -#include - -enum -{ - /* Specifies the memory type to be undefined */ - NvBootMemoryType_None = 0, - - /* Specifies the memory type to be DDR SDRAM */ - NvBootMemoryType_Ddr = 0, - - /* Specifies the memory type to be LPDDR SDRAM */ - NvBootMemoryType_LpDdr = 0, - - /* Specifies the memory type to be DDR2 SDRAM */ - NvBootMemoryType_Ddr2 = 0, - - /* Specifies the memory type to be LPDDR2 SDRAM */ - NvBootMemoryType_LpDdr2, - - /* Specifies the memory type to be DDR3 SDRAM */ - NvBootMemoryType_Ddr3, - - /* Specifies the memory type to be LPDDR4 SDRAM */ - NvBootMemoryType_LpDdr4, - - NvBootMemoryType_Num, - - /* Specifies an entry in the ram_code table that's not in use */ - NvBootMemoryType_Unused = 0X7FFFFFF, -}; - -/** - * Defines the SDRAM parameter structure - */ -struct sdram_params_t210 -{ - - /* Specifies the type of memory device */ - u32 MemoryType; - - /* MC/EMC clock source configuration */ - - /* Specifies the M value for PllM */ - u32 PllMInputDivider; - /* Specifies the N value for PllM */ - u32 PllMFeedbackDivider; - /* Specifies the time to wait for PLLM to lock (in microseconds) */ - u32 PllMStableTime; - /* Specifies misc. control bits */ - u32 PllMSetupControl; - /* Specifies the P value for PLLM */ - u32 PllMPostDivider; - /* Specifies value for Charge Pump Gain Control */ - u32 PllMKCP; - /* Specifies VCO gain */ - u32 PllMKVCO; - /* Spare BCT param */ - u32 EmcBctSpare0; - /* Spare BCT param */ - u32 EmcBctSpare1; - /* Spare BCT param */ - u32 EmcBctSpare2; - /* Spare BCT param */ - u32 EmcBctSpare3; - /* Spare BCT param */ - u32 EmcBctSpare4; - /* Spare BCT param */ - u32 EmcBctSpare5; - /* Spare BCT param */ - u32 EmcBctSpare6; - /* Spare BCT param */ - u32 EmcBctSpare7; - /* Spare BCT param */ - u32 EmcBctSpare8; - /* Spare BCT param */ - u32 EmcBctSpare9; - /* Spare BCT param */ - u32 EmcBctSpare10; - /* Spare BCT param */ - u32 EmcBctSpare11; - /* Spare BCT param */ - u32 EmcBctSpare12; - /* Spare BCT param */ - u32 EmcBctSpare13; - - /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ - u32 EmcClockSource; - u32 EmcClockSourceDll; - - /* Defines possible override for PLLLM_MISC2 */ - u32 ClkRstControllerPllmMisc2Override; - /* enables override for PLLLM_MISC2 */ - u32 ClkRstControllerPllmMisc2OverrideEnable; - /* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */ - u32 ClearClk2Mc1; - - /* Auto-calibration of EMC pads */ - - /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ - u32 EmcAutoCalInterval; - /* - * Specifies the value for EMC_AUTO_CAL_CONFIG - * Note: Trigger bits are set by the SDRAM code. - */ - u32 EmcAutoCalConfig; - - /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ - u32 EmcAutoCalConfig2; - - /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ - u32 EmcAutoCalConfig3; - - /* Specifies the values for EMC_AUTO_CAL_CONFIG4-8 */ - u32 EmcAutoCalConfig4; - u32 EmcAutoCalConfig5; - u32 EmcAutoCalConfig6; - u32 EmcAutoCalConfig7; - u32 EmcAutoCalConfig8; - - /* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */ - u32 EmcAutoCalVrefSel0; - u32 EmcAutoCalVrefSel1; - - /* Specifies the value for EMC_AUTO_CAL_CHANNEL */ - u32 EmcAutoCalChannel; - - /* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */ - u32 EmcPmacroAutocalCfg0; - u32 EmcPmacroAutocalCfg1; - u32 EmcPmacroAutocalCfg2; - u32 EmcPmacroRxTerm; - u32 EmcPmacroDqTxDrv; - u32 EmcPmacroCaTxDrv; - u32 EmcPmacroCmdTxDrv; - u32 EmcPmacroAutocalCfgCommon; - u32 EmcPmacroZctrl; - - /* - * Specifies the time for the calibration - * to stabilize (in microseconds) - */ - u32 EmcAutoCalWait; - - u32 EmcXm2CompPadCtrl; - u32 EmcXm2CompPadCtrl2; - u32 EmcXm2CompPadCtrl3; - - /* - * DRAM size information - * Specifies the value for EMC_ADR_CFG - */ - u32 EmcAdrCfg; - - /* - * Specifies the time to wait after asserting pin - * CKE (in microseconds) - */ - u32 EmcPinProgramWait; - /* Specifies the extra delay before/after pin RESET/CKE command */ - u32 EmcPinExtraWait; - - u32 EmcPinGpioEn; - u32 EmcPinGpio; - - /* - * Specifies the extra delay after the first writing - * of EMC_TIMING_CONTROL - */ - u32 EmcTimingControlWait; - - /* Timing parameters required for the SDRAM */ - - /* Specifies the value for EMC_RC */ - u32 EmcRc; - /* Specifies the value for EMC_RFC */ - u32 EmcRfc; - /* Specifies the value for EMC_RFC_PB */ - u32 EmcRfcPb; - /* Specifies the value for EMC_RFC_CTRL2 */ - u32 EmcRefctrl2; - /* Specifies the value for EMC_RFC_SLR */ - u32 EmcRfcSlr; - /* Specifies the value for EMC_RAS */ - u32 EmcRas; - /* Specifies the value for EMC_RP */ - u32 EmcRp; - /* Specifies the value for EMC_R2R */ - u32 EmcR2r; - /* Specifies the value for EMC_W2W */ - u32 EmcW2w; - /* Specifies the value for EMC_R2W */ - u32 EmcR2w; - /* Specifies the value for EMC_W2R */ - u32 EmcW2r; - /* Specifies the value for EMC_R2P */ - u32 EmcR2p; - /* Specifies the value for EMC_W2P */ - u32 EmcW2p; - - u32 EmcTppd; - u32 EmcCcdmw; - - /* Specifies the value for EMC_RD_RCD */ - u32 EmcRdRcd; - /* Specifies the value for EMC_WR_RCD */ - u32 EmcWrRcd; - /* Specifies the value for EMC_RRD */ - u32 EmcRrd; - /* Specifies the value for EMC_REXT */ - u32 EmcRext; - /* Specifies the value for EMC_WEXT */ - u32 EmcWext; - /* Specifies the value for EMC_WDV */ - u32 EmcWdv; - - u32 EmcWdvChk; - u32 EmcWsv; - u32 EmcWev; - - /* Specifies the value for EMC_WDV_MASK */ - u32 EmcWdvMask; - - u32 EmcWsDuration; - u32 EmcWeDuration; - - /* Specifies the value for EMC_QUSE */ - u32 EmcQUse; - /* Specifies the value for EMC_QUSE_WIDTH */ - u32 EmcQuseWidth; - /* Specifies the value for EMC_IBDLY */ - u32 EmcIbdly; - /* Specifies the value for EMC_OBDLY */ - u32 EmcObdly; - /* Specifies the value for EMC_EINPUT */ - u32 EmcEInput; - /* Specifies the value for EMC_EINPUT_DURATION */ - u32 EmcEInputDuration; - /* Specifies the value for EMC_PUTERM_EXTRA */ - u32 EmcPutermExtra; - /* Specifies the value for EMC_PUTERM_WIDTH */ - u32 EmcPutermWidth; - /* Specifies the value for EMC_PUTERM_ADJ */ - ////u32 EmcPutermAdj; - - /* Specifies the value for EMC_QRST */ - u32 EmcQRst; - /* Specifies the value for EMC_QSAFE */ - u32 EmcQSafe; - /* Specifies the value for EMC_RDV */ - u32 EmcRdv; - /* Specifies the value for EMC_RDV_MASK */ - u32 EmcRdvMask; - /* Specifies the value for EMC_RDV_EARLY */ - u32 EmcRdvEarly; - /* Specifies the value for EMC_RDV_EARLY_MASK */ - u32 EmcRdvEarlyMask; - /* Specifies the value for EMC_QPOP */ - u32 EmcQpop; - - /* Specifies the value for EMC_REFRESH */ - u32 EmcRefresh; - /* Specifies the value for EMC_BURST_REFRESH_NUM */ - u32 EmcBurstRefreshNum; - /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ - u32 EmcPreRefreshReqCnt; - /* Specifies the value for EMC_PDEX2WR */ - u32 EmcPdEx2Wr; - /* Specifies the value for EMC_PDEX2RD */ - u32 EmcPdEx2Rd; - /* Specifies the value for EMC_PCHG2PDEN */ - u32 EmcPChg2Pden; - /* Specifies the value for EMC_ACT2PDEN */ - u32 EmcAct2Pden; - /* Specifies the value for EMC_AR2PDEN */ - u32 EmcAr2Pden; - /* Specifies the value for EMC_RW2PDEN */ - u32 EmcRw2Pden; - /* Specifies the value for EMC_CKE2PDEN */ - u32 EmcCke2Pden; - /* Specifies the value for EMC_PDEX2CKE */ - u32 EmcPdex2Cke; - /* Specifies the value for EMC_PDEX2MRR */ - u32 EmcPdex2Mrr; - /* Specifies the value for EMC_TXSR */ - u32 EmcTxsr; - /* Specifies the value for EMC_TXSRDLL */ - u32 EmcTxsrDll; - /* Specifies the value for EMC_TCKE */ - u32 EmcTcke; - /* Specifies the value for EMC_TCKESR */ - u32 EmcTckesr; - /* Specifies the value for EMC_TPD */ - u32 EmcTpd; - /* Specifies the value for EMC_TFAW */ - u32 EmcTfaw; - /* Specifies the value for EMC_TRPAB */ - u32 EmcTrpab; - /* Specifies the value for EMC_TCLKSTABLE */ - u32 EmcTClkStable; - /* Specifies the value for EMC_TCLKSTOP */ - u32 EmcTClkStop; - /* Specifies the value for EMC_TREFBW */ - u32 EmcTRefBw; - - /* FBIO configuration values */ - - /* Specifies the value for EMC_FBIO_CFG5 */ - u32 EmcFbioCfg5; - /* Specifies the value for EMC_FBIO_CFG7 */ - u32 EmcFbioCfg7; - /* Specifies the value for EMC_FBIO_CFG8 */ - u32 EmcFbioCfg8; - - /* Command mapping for CMD brick 0 */ - u32 EmcCmdMappingCmd0_0; - u32 EmcCmdMappingCmd0_1; - u32 EmcCmdMappingCmd0_2; - u32 EmcCmdMappingCmd1_0; - u32 EmcCmdMappingCmd1_1; - u32 EmcCmdMappingCmd1_2; - u32 EmcCmdMappingCmd2_0; - u32 EmcCmdMappingCmd2_1; - u32 EmcCmdMappingCmd2_2; - u32 EmcCmdMappingCmd3_0; - u32 EmcCmdMappingCmd3_1; - u32 EmcCmdMappingCmd3_2; - u32 EmcCmdMappingByte; - - /* Specifies the value for EMC_FBIO_SPARE */ - u32 EmcFbioSpare; - - /* Specifies the value for EMC_CFG_RSV */ - u32 EmcCfgRsv; - - /* MRS command values */ - - /* Specifies the value for EMC_MRS */ - u32 EmcMrs; - /* Specifies the MP0 command to initialize mode registers */ - u32 EmcEmrs; - /* Specifies the MP2 command to initialize mode registers */ - u32 EmcEmrs2; - /* Specifies the MP3 command to initialize mode registers */ - u32 EmcEmrs3; - /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ - u32 EmcMrw1; - /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ - u32 EmcMrw2; - /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ - u32 EmcMrw3; - /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ - u32 EmcMrw4; - /* Specifies the programming to LPDDR2 Mode Register 3? at cold boot */ - u32 EmcMrw6; - /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ - u32 EmcMrw8; - /* Specifies the programming to LPDDR2 Mode Register 11? at cold boot */ - u32 EmcMrw9; - /* Specifies the programming to LPDDR2 Mode Register 12 at cold boot */ - u32 EmcMrw10; - /* Specifies the programming to LPDDR2 Mode Register 14 at cold boot */ - u32 EmcMrw12; - /* Specifies the programming to LPDDR2 Mode Register 14? at cold boot */ - u32 EmcMrw13; - /* Specifies the programming to LPDDR2 Mode Register 22 at cold boot */ - u32 EmcMrw14; - /* - * Specifies the programming to extra LPDDR2 Mode Register - * at cold boot - */ - u32 EmcMrwExtra; - /* - * Specifies the programming to extra LPDDR2 Mode Register - * at warm boot - */ - u32 EmcWarmBootMrwExtra; - /* - * Specify the enable of extra Mode Register programming at - * warm boot - */ - u32 EmcWarmBootExtraModeRegWriteEnable; - /* - * Specify the enable of extra Mode Register programming at - * cold boot - */ - u32 EmcExtraModeRegWriteEnable; - - /* Specifies the EMC_MRW reset command value */ - u32 EmcMrwResetCommand; - /* Specifies the EMC Reset wait time (in microseconds) */ - u32 EmcMrwResetNInitWait; - /* Specifies the value for EMC_MRS_WAIT_CNT */ - u32 EmcMrsWaitCnt; - /* Specifies the value for EMC_MRS_WAIT_CNT2 */ - u32 EmcMrsWaitCnt2; - - /* EMC miscellaneous configurations */ - - /* Specifies the value for EMC_CFG */ - u32 EmcCfg; - /* Specifies the value for EMC_CFG_2 */ - u32 EmcCfg2; - /* Specifies the pipe bypass controls */ - u32 EmcCfgPipe; - u32 EmcCfgPipeClk; - u32 EmcFdpdCtrlCmdNoRamp; - u32 EmcCfgUpdate; - - /* Specifies the value for EMC_DBG */ - u32 EmcDbg; - u32 EmcDbgWriteMux; - - /* Specifies the value for EMC_CMDQ */ - u32 EmcCmdQ; - /* Specifies the value for EMC_MC2EMCQ */ - u32 EmcMc2EmcQ; - /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ - u32 EmcDynSelfRefControl; - - /* Specifies the value for MEM_INIT_DONE */ - u32 AhbArbitrationXbarCtrlMemInitDone; - - /* Specifies the value for EMC_CFG_DIG_DLL */ - u32 EmcCfgDigDll; - u32 EmcCfgDigDll_1; - /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ - u32 EmcCfgDigDllPeriod; - /* Specifies the value of *DEV_SELECTN of various EMC registers */ - u32 EmcDevSelect; - - /* Specifies the value for EMC_SEL_DPD_CTRL */ - u32 EmcSelDpdCtrl; - - /* Pads trimmer delays */ - u32 EmcFdpdCtrlDq; - u32 EmcFdpdCtrlCmd; - u32 EmcPmacroIbVrefDq_0; - u32 EmcPmacroIbVrefDq_1; - u32 EmcPmacroIbVrefDqs_0; - u32 EmcPmacroIbVrefDqs_1; - u32 EmcPmacroIbRxrt; - u32 EmcCfgPipe1; - u32 EmcCfgPipe2; - - /* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */ - u32 EmcPmacroQuseDdllRank0_0; - u32 EmcPmacroQuseDdllRank0_1; - u32 EmcPmacroQuseDdllRank0_2; - u32 EmcPmacroQuseDdllRank0_3; - u32 EmcPmacroQuseDdllRank0_4; - u32 EmcPmacroQuseDdllRank0_5; - u32 EmcPmacroQuseDdllRank1_0; - u32 EmcPmacroQuseDdllRank1_1; - u32 EmcPmacroQuseDdllRank1_2; - u32 EmcPmacroQuseDdllRank1_3; - u32 EmcPmacroQuseDdllRank1_4; - u32 EmcPmacroQuseDdllRank1_5; - - u32 EmcPmacroObDdllLongDqRank0_0; - u32 EmcPmacroObDdllLongDqRank0_1; - u32 EmcPmacroObDdllLongDqRank0_2; - u32 EmcPmacroObDdllLongDqRank0_3; - u32 EmcPmacroObDdllLongDqRank0_4; - u32 EmcPmacroObDdllLongDqRank0_5; - u32 EmcPmacroObDdllLongDqRank1_0; - u32 EmcPmacroObDdllLongDqRank1_1; - u32 EmcPmacroObDdllLongDqRank1_2; - u32 EmcPmacroObDdllLongDqRank1_3; - u32 EmcPmacroObDdllLongDqRank1_4; - u32 EmcPmacroObDdllLongDqRank1_5; - - u32 EmcPmacroObDdllLongDqsRank0_0; - u32 EmcPmacroObDdllLongDqsRank0_1; - u32 EmcPmacroObDdllLongDqsRank0_2; - u32 EmcPmacroObDdllLongDqsRank0_3; - u32 EmcPmacroObDdllLongDqsRank0_4; - u32 EmcPmacroObDdllLongDqsRank0_5; - u32 EmcPmacroObDdllLongDqsRank1_0; - u32 EmcPmacroObDdllLongDqsRank1_1; - u32 EmcPmacroObDdllLongDqsRank1_2; - u32 EmcPmacroObDdllLongDqsRank1_3; - u32 EmcPmacroObDdllLongDqsRank1_4; - u32 EmcPmacroObDdllLongDqsRank1_5; - - u32 EmcPmacroIbDdllLongDqsRank0_0; - u32 EmcPmacroIbDdllLongDqsRank0_1; - u32 EmcPmacroIbDdllLongDqsRank0_2; - u32 EmcPmacroIbDdllLongDqsRank0_3; - u32 EmcPmacroIbDdllLongDqsRank1_0; - u32 EmcPmacroIbDdllLongDqsRank1_1; - u32 EmcPmacroIbDdllLongDqsRank1_2; - u32 EmcPmacroIbDdllLongDqsRank1_3; - - u32 EmcPmacroDdllLongCmd_0; - u32 EmcPmacroDdllLongCmd_1; - u32 EmcPmacroDdllLongCmd_2; - u32 EmcPmacroDdllLongCmd_3; - u32 EmcPmacroDdllLongCmd_4; - u32 EmcPmacroDdllShortCmd_0; - u32 EmcPmacroDdllShortCmd_1; - u32 EmcPmacroDdllShortCmd_2; - - /* - * Specifies the delay after asserting CKE pin during a WarmBoot0 - * sequence (in microseconds) - */ - u32 WarmBootWait; - - /* Specifies the value for EMC_ODT_WRITE */ - u32 EmcOdtWrite; - - /* Periodic ZQ calibration */ - - /* - * Specifies the value for EMC_ZCAL_INTERVAL - * Value 0 disables ZQ calibration - */ - u32 EmcZcalInterval; - /* Specifies the value for EMC_ZCAL_WAIT_CNT */ - u32 EmcZcalWaitCnt; - /* Specifies the value for EMC_ZCAL_MRW_CMD */ - u32 EmcZcalMrwCmd; - - /* DRAM initialization sequence flow control */ - - /* Specifies the MRS command value for resetting DLL */ - u32 EmcMrsResetDll; - /* Specifies the command for ZQ initialization of device 0 */ - u32 EmcZcalInitDev0; - /* Specifies the command for ZQ initialization of device 1 */ - u32 EmcZcalInitDev1; - /* - * Specifies the wait time after programming a ZQ initialization - * command (in microseconds) - */ - u32 EmcZcalInitWait; - /* - * Specifies the enable for ZQ calibration at cold boot [bit 0] - * and warm boot [bit 1] - */ - u32 EmcZcalWarmColdBootEnables; - - /* - * Specifies the MRW command to LPDDR2 for ZQ calibration - * on warmboot - */ - /* Is issued to both devices separately */ - u32 EmcMrwLpddr2ZcalWarmBoot; - /* - * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot - * Is issued to both devices separately - */ - u32 EmcZqCalDdr3WarmBoot; - u32 EmcZqCalLpDdr4WarmBoot; - /* - * Specifies the wait time for ZQ calibration on warmboot - * (in microseconds) - */ - u32 EmcZcalWarmBootWait; - /* - * Specifies the enable for DRAM Mode Register programming - * at warm boot - */ - u32 EmcMrsWarmBootEnable; - /* - * Specifies the wait time after sending an MRS DLL reset command - * in microseconds) - */ - u32 EmcMrsResetDllWait; - /* Specifies the extra MRS command to initialize mode registers */ - u32 EmcMrsExtra; - /* Specifies the extra MRS command at warm boot */ - u32 EmcWarmBootMrsExtra; - /* Specifies the EMRS command to enable the DDR2 DLL */ - u32 EmcEmrsDdr2DllEnable; - /* Specifies the MRS command to reset the DDR2 DLL */ - u32 EmcMrsDdr2DllReset; - /* Specifies the EMRS command to set OCD calibration */ - u32 EmcEmrsDdr2OcdCalib; - /* - * Specifies the wait between initializing DDR and setting OCD - * calibration (in microseconds) - */ - u32 EmcDdr2Wait; - /* Specifies the value for EMC_CLKEN_OVERRIDE */ - u32 EmcClkenOverride; - - /* - * Specifies LOG2 of the extra refresh numbers after booting - * Program 0 to disable - */ - u32 EmcExtraRefreshNum; - /* Specifies the master override for all EMC clocks */ - u32 EmcClkenOverrideAllWarmBoot; - /* Specifies the master override for all MC clocks */ - u32 McClkenOverrideAllWarmBoot; - /* Specifies digital dll period, choosing between 4 to 64 ms */ - u32 EmcCfgDigDllPeriodWarmBoot; - - /* Pad controls */ - - /* Specifies the value for PMC_VDDP_SEL */ - u32 PmcVddpSel; - /* Specifies the wait time after programming PMC_VDDP_SEL */ - u32 PmcVddpSelWait; - /* Specifies the value for PMC_DDR_PWR */ - u32 PmcDdrPwr; - /* Specifies the value for PMC_DDR_CFG */ - u32 PmcDdrCfg; - /* Specifies the value for PMC_IO_DPD3_REQ */ - u32 PmcIoDpd3Req; - /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ - u32 PmcIoDpd3ReqWait; - u32 PmcIoDpd4ReqWait; - - /* Specifies the value for PMC_REG_SHORT */ - u32 PmcRegShort; - /* Specifies the value for PMC_NO_IOPOWER */ - u32 PmcNoIoPower; - - u32 PmcDdrCntrlWait; - u32 PmcDdrCntrl; - - /* Specifies the value for EMC_ACPD_CONTROL */ - u32 EmcAcpdControl; - - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE_CFG */ - ////u32 EmcSwizzleRank0ByteCfg; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ - u32 EmcSwizzleRank0Byte0; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ - u32 EmcSwizzleRank0Byte1; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ - u32 EmcSwizzleRank0Byte2; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ - u32 EmcSwizzleRank0Byte3; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE_CFG */ - ////u32 EmcSwizzleRank1ByteCfg; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ - u32 EmcSwizzleRank1Byte0; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ - u32 EmcSwizzleRank1Byte1; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ - u32 EmcSwizzleRank1Byte2; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ - u32 EmcSwizzleRank1Byte3; - - /* Specifies the value for EMC_TXDSRVTTGEN */ - u32 EmcTxdsrvttgen; - - /* Specifies the value for EMC_DATA_BRLSHFT_0 */ - u32 EmcDataBrlshft0; - u32 EmcDataBrlshft1; - - u32 EmcDqsBrlshft0; - u32 EmcDqsBrlshft1; - - u32 EmcCmdBrlshft0; - u32 EmcCmdBrlshft1; - u32 EmcCmdBrlshft2; - u32 EmcCmdBrlshft3; - - u32 EmcQuseBrlshft0; - u32 EmcQuseBrlshft1; - u32 EmcQuseBrlshft2; - u32 EmcQuseBrlshft3; - - u32 EmcDllCfg0; - u32 EmcDllCfg1; - - u32 EmcPmcScratch1; - u32 EmcPmcScratch2; - u32 EmcPmcScratch3; - - u32 EmcPmacroPadCfgCtrl; - - u32 EmcPmacroVttgenCtrl0; - u32 EmcPmacroVttgenCtrl1; - u32 EmcPmacroVttgenCtrl2; - - u32 EmcPmacroBrickCtrlRfu1; - u32 EmcPmacroCmdBrickCtrlFdpd; - u32 EmcPmacroBrickCtrlRfu2; - u32 EmcPmacroDataBrickCtrlFdpd; - u32 EmcPmacroBgBiasCtrl0; - u32 EmcPmacroDataPadRxCtrl; - u32 EmcPmacroCmdPadRxCtrl; - u32 EmcPmacroDataRxTermMode; - u32 EmcPmacroCmdRxTermMode; - u32 EmcPmacroDataPadTxCtrl; - u32 EmcPmacroCommonPadTxCtrl; - u32 EmcPmacroCmdPadTxCtrl; - u32 EmcCfg3; - - u32 EmcPmacroTxPwrd0; - u32 EmcPmacroTxPwrd1; - u32 EmcPmacroTxPwrd2; - u32 EmcPmacroTxPwrd3; - u32 EmcPmacroTxPwrd4; - u32 EmcPmacroTxPwrd5; - - u32 EmcConfigSampleDelay; - - u32 EmcPmacroBrickMapping0; - u32 EmcPmacroBrickMapping1; - u32 EmcPmacroBrickMapping2; - - u32 EmcPmacroTxSelClkSrc0; - u32 EmcPmacroTxSelClkSrc1; - u32 EmcPmacroTxSelClkSrc2; - u32 EmcPmacroTxSelClkSrc3; - u32 EmcPmacroTxSelClkSrc4; - u32 EmcPmacroTxSelClkSrc5; - - u32 EmcPmacroDdllBypass; - - u32 EmcPmacroDdllPwrd0; - u32 EmcPmacroDdllPwrd1; - u32 EmcPmacroDdllPwrd2; - - u32 EmcPmacroCmdCtrl0; - u32 EmcPmacroCmdCtrl1; - u32 EmcPmacroCmdCtrl2; - - /* DRAM size information */ - - /* Specifies the value for MC_EMEM_ADR_CFG */ - u32 McEmemAdrCfg; - /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ - u32 McEmemAdrCfgDev0; - /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ - u32 McEmemAdrCfgDev1; - u32 McEmemAdrCfgChannelMask; - - /* Specifies the value for MC_EMEM_BANK_SWIZZLECfg0 */ - u32 McEmemAdrCfgBankMask0; - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ - u32 McEmemAdrCfgBankMask1; - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ - u32 McEmemAdrCfgBankMask2; - - /* - * Specifies the value for MC_EMEM_CFG which holds the external memory - * size (in KBytes) - */ - u32 McEmemCfg; - - /* MC arbitration configuration */ - - /* Specifies the value for MC_EMEM_ARB_CFG */ - u32 McEmemArbCfg; - /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ - u32 McEmemArbOutstandingReq; - - u32 McEmemArbRefpbHpCtrl; - u32 McEmemArbRefpbBankCtrl; - - /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ - u32 McEmemArbTimingRcd; - /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ - u32 McEmemArbTimingRp; - /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ - u32 McEmemArbTimingRc; - /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ - u32 McEmemArbTimingRas; - /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ - u32 McEmemArbTimingFaw; - /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ - u32 McEmemArbTimingRrd; - /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ - u32 McEmemArbTimingRap2Pre; - /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ - u32 McEmemArbTimingWap2Pre; - /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ - u32 McEmemArbTimingR2R; - /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ - u32 McEmemArbTimingW2W; - /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ - u32 McEmemArbTimingR2W; - /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ - u32 McEmemArbTimingW2R; - - u32 McEmemArbTimingRFCPB; - - /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ - u32 McEmemArbDaTurns; - /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ - u32 McEmemArbDaCovers; - /* Specifies the value for MC_EMEM_ARB_MISC0 */ - u32 McEmemArbMisc0; - /* Specifies the value for MC_EMEM_ARB_MISC1 */ - u32 McEmemArbMisc1; - u32 McEmemArbMisc2; - - /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ - u32 McEmemArbRing1Throttle; - /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ - u32 McEmemArbOverride; - /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ - u32 McEmemArbOverride1; - /* Specifies the value for MC_EMEM_ARB_RSV */ - u32 McEmemArbRsv; - - u32 McDaCfg0; - u32 McEmemArbTimingCcdmw; - - /* Specifies the value for MC_CLKEN_OVERRIDE */ - u32 McClkenOverride; - - /* Specifies the value for MC_STAT_CONTROL */ - u32 McStatControl; - - /* Specifies the value for MC_VIDEO_PROTECT_BOM */ - u32 McVideoProtectBom; - /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ - u32 McVideoProtectBomAdrHi; - /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ - u32 McVideoProtectSizeMb; - /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ - u32 McVideoProtectVprOverride; - /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ - u32 McVideoProtectVprOverride1; - /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ - u32 McVideoProtectGpuOverride0; - /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ - u32 McVideoProtectGpuOverride1; - /* Specifies the value for MC_SEC_CARVEOUT_BOM */ - u32 McSecCarveoutBom; - /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ - u32 McSecCarveoutAdrHi; - /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ - u32 McSecCarveoutSizeMb; - /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL. - VIDEO_PROTECT_WRITEAccess */ - u32 McVideoProtectWriteAccess; - /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL. - SEC_CARVEOUT_WRITEAccess */ - u32 McSecCarveoutProtectWriteAccess; - - /* Write-Protect Regions (WPR) */ - u32 McGeneralizedCarveout1Bom; - u32 McGeneralizedCarveout1BomHi; - u32 McGeneralizedCarveout1Size128kb; - u32 McGeneralizedCarveout1Access0; - u32 McGeneralizedCarveout1Access1; - u32 McGeneralizedCarveout1Access2; - u32 McGeneralizedCarveout1Access3; - u32 McGeneralizedCarveout1Access4; - u32 McGeneralizedCarveout1ForceInternalAccess0; - u32 McGeneralizedCarveout1ForceInternalAccess1; - u32 McGeneralizedCarveout1ForceInternalAccess2; - u32 McGeneralizedCarveout1ForceInternalAccess3; - u32 McGeneralizedCarveout1ForceInternalAccess4; - u32 McGeneralizedCarveout1Cfg0; - - u32 McGeneralizedCarveout2Bom; - u32 McGeneralizedCarveout2BomHi; - u32 McGeneralizedCarveout2Size128kb; - u32 McGeneralizedCarveout2Access0; - u32 McGeneralizedCarveout2Access1; - u32 McGeneralizedCarveout2Access2; - u32 McGeneralizedCarveout2Access3; - u32 McGeneralizedCarveout2Access4; - u32 McGeneralizedCarveout2ForceInternalAccess0; - u32 McGeneralizedCarveout2ForceInternalAccess1; - u32 McGeneralizedCarveout2ForceInternalAccess2; - u32 McGeneralizedCarveout2ForceInternalAccess3; - u32 McGeneralizedCarveout2ForceInternalAccess4; - u32 McGeneralizedCarveout2Cfg0; - - u32 McGeneralizedCarveout3Bom; - u32 McGeneralizedCarveout3BomHi; - u32 McGeneralizedCarveout3Size128kb; - u32 McGeneralizedCarveout3Access0; - u32 McGeneralizedCarveout3Access1; - u32 McGeneralizedCarveout3Access2; - u32 McGeneralizedCarveout3Access3; - u32 McGeneralizedCarveout3Access4; - u32 McGeneralizedCarveout3ForceInternalAccess0; - u32 McGeneralizedCarveout3ForceInternalAccess1; - u32 McGeneralizedCarveout3ForceInternalAccess2; - u32 McGeneralizedCarveout3ForceInternalAccess3; - u32 McGeneralizedCarveout3ForceInternalAccess4; - u32 McGeneralizedCarveout3Cfg0; - - u32 McGeneralizedCarveout4Bom; - u32 McGeneralizedCarveout4BomHi; - u32 McGeneralizedCarveout4Size128kb; - u32 McGeneralizedCarveout4Access0; - u32 McGeneralizedCarveout4Access1; - u32 McGeneralizedCarveout4Access2; - u32 McGeneralizedCarveout4Access3; - u32 McGeneralizedCarveout4Access4; - u32 McGeneralizedCarveout4ForceInternalAccess0; - u32 McGeneralizedCarveout4ForceInternalAccess1; - u32 McGeneralizedCarveout4ForceInternalAccess2; - u32 McGeneralizedCarveout4ForceInternalAccess3; - u32 McGeneralizedCarveout4ForceInternalAccess4; - u32 McGeneralizedCarveout4Cfg0; - - u32 McGeneralizedCarveout5Bom; - u32 McGeneralizedCarveout5BomHi; - u32 McGeneralizedCarveout5Size128kb; - u32 McGeneralizedCarveout5Access0; - u32 McGeneralizedCarveout5Access1; - u32 McGeneralizedCarveout5Access2; - u32 McGeneralizedCarveout5Access3; - u32 McGeneralizedCarveout5Access4; - u32 McGeneralizedCarveout5ForceInternalAccess0; - u32 McGeneralizedCarveout5ForceInternalAccess1; - u32 McGeneralizedCarveout5ForceInternalAccess2; - u32 McGeneralizedCarveout5ForceInternalAccess3; - u32 McGeneralizedCarveout5ForceInternalAccess4; - u32 McGeneralizedCarveout5Cfg0; - - /* Specifies enable for CA training */ - u32 EmcCaTrainingEnable; - - /* Set if bit 6 select is greater than bit 7 select; uses aremc. - spec packet SWIZZLE_BIT6_GT_BIT7 */ - u32 SwizzleRankByteEncode; - /* Specifies enable and offset for patched boot ROM write */ - u32 BootRomPatchControl; - /* Specifies data for patched boot ROM write */ - u32 BootRomPatchData; - - /* Specifies the value for MC_MTS_CARVEOUT_BOM */ - u32 McMtsCarveoutBom; - /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ - u32 McMtsCarveoutAdrHi; - /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ - u32 McMtsCarveoutSizeMb; - /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ - u32 McMtsCarveoutRegCtrl; - - /* End */ -}; - -#endif /* __SOC_NVIDIA_TEGRA210_SDRAM_PARAM_H__ */ diff --git a/bdk/mem/sdram_lp0_param_t210b01.h b/bdk/mem/sdram_lp0_param_t210b01.h deleted file mode 100644 index f987a1e..0000000 --- a/bdk/mem/sdram_lp0_param_t210b01.h +++ /dev/null @@ -1,990 +0,0 @@ -/* - * Copyright (c) 2020 CTCaer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef __TEGRA210B01_SDRAM_PARAM_H__ -#define __TEGRA210B01_SDRAM_PARAM_H__ - -#include - -struct sdram_params_t210b01 -{ - /* Specifies the type of memory device */ - u32 memory_type; - - /* MC/EMC clock source configuration */ - - /* Specifies the M value for PllM */ - u32 pllm_input_divider; - /* Specifies the N value for PllM */ - u32 pllm_feedback_divider; - /* Specifies the time to wait for PLLM to lock (in microseconds) */ - u32 pllm_stable_time; - /* Specifies misc. control bits */ - u32 pllm_setup_control; - /* Specifies the P value for PLLM */ - u32 pllm_post_divider; - /* Specifies value for Charge Pump Gain Control */ - u32 pllm_kcp; - /* Specifies VCO gain */ - u32 pllm_kvco; - /* Spare BCT param */ - u32 emc_bct_spare0; - /* Spare BCT param */ - u32 emc_bct_spare1; - /* Spare BCT param */ - u32 emc_bct_spare2; - /* Spare BCT param */ - u32 emc_bct_spare3; - /* Spare BCT param */ - u32 emc_bct_spare4; - /* Spare BCT param */ - u32 emc_bct_spare5; - /* Spare BCT param */ - u32 emc_bct_spare6; - /* Spare BCT param */ - u32 emc_bct_spare7; - /* Spare BCT param */ - u32 emc_bct_spare8; - /* Spare BCT param */ - u32 emc_bct_spare9; - /* Spare BCT param */ - u32 emc_bct_spare10; - /* Spare BCT param */ - u32 emc_bct_spare11; - /* Spare BCT param */ - u32 emc_bct_spare12; - /* Spare BCT param */ - u32 emc_bct_spare13; - /* Spare BCT param */ - u32 emc_bct_spare_secure0; - /* Spare BCT param */ - u32 emc_bct_spare_secure1; - /* Spare BCT param */ - u32 emc_bct_spare_secure2; - /* Spare BCT param */ - u32 emc_bct_spare_secure3; - /* Spare BCT param */ - u32 emc_bct_spare_secure4; - /* Spare BCT param */ - u32 emc_bct_spare_secure5; - /* Spare BCT param */ - u32 emc_bct_spare_secure6; - /* Spare BCT param */ - u32 emc_bct_spare_secure7; - /* Spare BCT param */ - u32 emc_bct_spare_secure8; - /* Spare BCT param */ - u32 emc_bct_spare_secure9; - /* Spare BCT param */ - u32 emc_bct_spare_secure10; - /* Spare BCT param */ - u32 emc_bct_spare_secure11; - /* Spare BCT param */ - u32 emc_bct_spare_secure12; - /* Spare BCT param */ - u32 emc_bct_spare_secure13; - /* Spare BCT param */ - u32 emc_bct_spare_secure14; - /* Spare BCT param */ - u32 emc_bct_spare_secure15; - /* Spare BCT param */ - u32 emc_bct_spare_secure16; - /* Spare BCT param */ - u32 emc_bct_spare_secure17; - /* Spare BCT param */ - u32 emc_bct_spare_secure18; - /* Spare BCT param */ - u32 emc_bct_spare_secure19; - /* Spare BCT param */ - u32 emc_bct_spare_secure20; - /* Spare BCT param */ - u32 emc_bct_spare_secure21; - /* Spare BCT param */ - u32 emc_bct_spare_secure22; - /* Spare BCT param */ - u32 emc_bct_spare_secure23; - - /* Defines EMC_2X_CLK_SRC, EMC_2X_CLK_DIVISOR, EMC_INVERT_DCD */ - u32 emc_clock_source; - u32 emc_clock_source_dll; - - /* Defines possible override for PLLLM_MISC2 */ - u32 clk_rst_pllm_misc20_override; - /* enables override for PLLLM_MISC2 */ - u32 clk_rst_pllm_misc20_override_enable; - /* defines CLK_ENB_MC1 in register clk_rst_controller_clk_enb_w_clr */ - u32 clear_clock2_mc1; - - /* Auto-calibration of EMC pads */ - - /* Specifies the value for EMC_AUTO_CAL_INTERVAL */ - u32 emc_auto_cal_interval; - /* - * Specifies the value for EMC_AUTO_CAL_CONFIG - * Note: Trigger bits are set by the SDRAM code. - */ - u32 emc_auto_cal_config; - - /* Specifies the value for EMC_AUTO_CAL_CONFIG2 */ - u32 emc_auto_cal_config2; - - /* Specifies the value for EMC_AUTO_CAL_CONFIG3 */ - u32 emc_auto_cal_config3; - u32 emc_auto_cal_config4; - u32 emc_auto_cal_config5; - u32 emc_auto_cal_config6; - u32 emc_auto_cal_config7; - u32 emc_auto_cal_config8; - u32 emc_auto_cal_config9; - - /* Specifies the value for EMC_AUTO_CAL_VREF_SEL_0 */ - u32 emc_auto_cal_vref_sel0; - u32 emc_auto_cal_vref_sel1; - - /* Specifies the value for EMC_AUTO_CAL_CHANNEL */ - u32 emc_auto_cal_channel; - - /* Specifies the value for EMC_PMACRO_AUTOCAL_CFG_0 */ - u32 emc_pmacro_auto_cal_cfg0; - u32 emc_pmacro_auto_cal_cfg1; - u32 emc_pmacro_auto_cal_cfg2; - - u32 emc_pmacro_rx_term; - u32 emc_pmacro_dq_tx_drive; - u32 emc_pmacro_ca_tx_drive; - u32 emc_pmacro_cmd_tx_drive; - u32 emc_pmacro_auto_cal_common; - u32 emc_pmacro_zcrtl; - - /* - * Specifies the time for the calibration - * to stabilize (in microseconds) - */ - u32 emc_auto_cal_wait; - - u32 emc_xm2_comp_pad_ctrl; - u32 emc_xm2_comp_pad_ctrl2; - u32 emc_xm2_comp_pad_ctrl3; - - /* - * DRAM size information - * Specifies the value for EMC_ADR_CFG - */ - u32 emc_adr_cfg; - - /* - * Specifies the time to wait after asserting pin - * CKE (in microseconds) - */ - u32 emc_pin_program_wait; - /* Specifies the extra delay before/after pin RESET/CKE command */ - u32 emc_pin_extra_wait; - - u32 emc_pin_gpio_enable; - u32 emc_pin_gpio; - - /* - * Specifies the extra delay after the first writing - * of EMC_TIMING_CONTROL - */ - u32 emc_timing_control_wait; - - /* Timing parameters required for the SDRAM */ - - /* Specifies the value for EMC_RC */ - u32 emc_rc; - /* Specifies the value for EMC_RFC */ - u32 emc_rfc; - - u32 emc_rfc_pb; - u32 emc_ref_ctrl2; - - /* Specifies the value for EMC_RFC_SLR */ - u32 emc_rfc_slr; - /* Specifies the value for EMC_RAS */ - u32 emc_ras; - /* Specifies the value for EMC_RP */ - u32 emc_rp; - /* Specifies the value for EMC_R2R */ - u32 emc_r2r; - /* Specifies the value for EMC_W2W */ - u32 emc_w2w; - /* Specifies the value for EMC_R2W */ - u32 emc_r2w; - /* Specifies the value for EMC_W2R */ - u32 emc_w2r; - /* Specifies the value for EMC_R2P */ - u32 emc_r2p; - /* Specifies the value for EMC_W2P */ - u32 emc_w2p; - /* Specifies the value for EMC_RD_RCD */ - - u32 emc_tppd; - u32 emc_trtm; - u32 emc_twtm; - u32 emc_tratm; - u32 emc_twatm; - u32 emc_tr2ref; - u32 emc_ccdmw; - - u32 emc_rd_rcd; - /* Specifies the value for EMC_WR_RCD */ - u32 emc_wr_rcd; - /* Specifies the value for EMC_RRD */ - u32 emc_rrd; - /* Specifies the value for EMC_REXT */ - u32 emc_rext; - /* Specifies the value for EMC_WEXT */ - u32 emc_wext; - /* Specifies the value for EMC_WDV */ - u32 emc_wdv; - - u32 emc_wdv_chk; - u32 emc_wsv; - u32 emc_wev; - - /* Specifies the value for EMC_WDV_MASK */ - u32 emc_wdv_mask; - - u32 emc_ws_duration; - u32 emc_we_duration; - - /* Specifies the value for EMC_QUSE */ - u32 emc_quse; - /* Specifies the value for EMC_QUSE_WIDTH */ - u32 emc_quse_width; - /* Specifies the value for EMC_IBDLY */ - u32 emc_ibdly; - - u32 emc_obdly; - - /* Specifies the value for EMC_EINPUT */ - u32 emc_einput; - /* Specifies the value for EMC_EINPUT_DURATION */ - u32 emc_einput_duration; - /* Specifies the value for EMC_PUTERM_EXTRA */ - u32 emc_puterm_extra; - /* Specifies the value for EMC_PUTERM_WIDTH */ - u32 emc_puterm_width; - - u32 emc_qrst; - u32 emc_qsafe; - u32 emc_rdv; - u32 emc_rdv_mask; - - u32 emc_rdv_early; - u32 emc_rdv_early_mask; - - /* Specifies the value for EMC_QPOP */ - u32 emc_qpop; - - /* Specifies the value for EMC_REFRESH */ - u32 emc_refresh; - /* Specifies the value for EMC_BURST_REFRESH_NUM */ - u32 emc_burst_refresh_num; - /* Specifies the value for EMC_PRE_REFRESH_REQ_CNT */ - u32 emc_prerefresh_req_cnt; - /* Specifies the value for EMC_PDEX2WR */ - u32 emc_pdex2wr; - /* Specifies the value for EMC_PDEX2RD */ - u32 emc_pdex2rd; - /* Specifies the value for EMC_PCHG2PDEN */ - u32 emc_pchg2pden; - /* Specifies the value for EMC_ACT2PDEN */ - u32 emc_act2pden; - /* Specifies the value for EMC_AR2PDEN */ - u32 emc_ar2pden; - /* Specifies the value for EMC_RW2PDEN */ - u32 emc_rw2pden; - - u32 emc_cke2pden; - u32 emc_pdex2che; - u32 emc_pdex2mrr; - - /* Specifies the value for EMC_TXSR */ - u32 emc_txsr; - /* Specifies the value for EMC_TXSRDLL */ - u32 emc_txsr_dll; - /* Specifies the value for EMC_TCKE */ - u32 emc_tcke; - /* Specifies the value for EMC_TCKESR */ - u32 emc_tckesr; - /* Specifies the value for EMC_TPD */ - u32 emc_tpd; - /* Specifies the value for EMC_TFAW */ - u32 emc_tfaw; - /* Specifies the value for EMC_TRPAB */ - u32 emc_trpab; - /* Specifies the value for EMC_TCLKSTABLE */ - u32 emc_tclkstable; - /* Specifies the value for EMC_TCLKSTOP */ - u32 emc_tclkstop; - /* Specifies the value for EMC_TREFBW */ - u32 emc_trefbw; - - /* FBIO configuration values */ - - /* Specifies the value for EMC_FBIO_CFG5 */ - u32 emc_fbio_cfg5; - /* Specifies the value for EMC_FBIO_CFG7 */ - u32 emc_fbio_cfg7; - u32 emc_fbio_cfg8; - - /* Command mapping for CMD brick 0 */ - u32 emc_cmd_mapping_cmd0_0; - u32 emc_cmd_mapping_cmd0_1; - u32 emc_cmd_mapping_cmd0_2; - u32 emc_cmd_mapping_cmd1_0; - u32 emc_cmd_mapping_cmd1_1; - u32 emc_cmd_mapping_cmd1_2; - u32 emc_cmd_mapping_cmd2_0; - u32 emc_cmd_mapping_cmd2_1; - u32 emc_cmd_mapping_cmd2_2; - u32 emc_cmd_mapping_cmd3_0; - u32 emc_cmd_mapping_cmd3_1; - u32 emc_cmd_mapping_cmd3_2; - u32 emc_cmd_mapping_byte; - - /* Specifies the value for EMC_FBIO_SPARE */ - u32 emc_fbio_spare; - - /* Specifies the value for EMC_CFG_RSV */ - u32 emc_cfg_rsv; - - /* MRS command values */ - - /* Specifies the value for EMC_MRS */ - u32 emc_mrs; - /* Specifies the MP0 command to initialize mode registers */ - u32 emc_emrs; - /* Specifies the MP2 command to initialize mode registers */ - u32 emc_emrs2; - /* Specifies the MP3 command to initialize mode registers */ - u32 emc_emrs3; - /* Specifies the programming to LPDDR2 Mode Register 1 at cold boot */ - u32 emc_mrw1; - /* Specifies the programming to LPDDR2 Mode Register 2 at cold boot */ - u32 emc_mrw2; - /* Specifies the programming to LPDDR2 Mode Register 3 at cold boot */ - u32 emc_mrw3; - /* Specifies the programming to LPDDR2 Mode Register 11 at cold boot */ - u32 emc_mrw4; - - /* Specifies the programming to LPDDR4 Mode Register 3 at cold boot */ - u32 emc_mrw6; - /* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */ - u32 emc_mrw8; - /* Specifies the programming to LPDDR4 Mode Register 11 at cold boot */ - u32 emc_mrw9; - /* Specifies the programming to LPDDR4 Mode Register 12 at cold boot */ - u32 emc_mrw10; - /* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */ - u32 emc_mrw12; - /* Specifies the programming to LPDDR4 Mode Register 14 at cold boot */ - u32 emc_mrw13; - /* Specifies the programming to LPDDR4 Mode Register 22 at cold boot */ - u32 emc_mrw14; - - /* - * Specifies the programming to extra LPDDR2 Mode Register - * at cold boot - */ - u32 emc_mrw_extra; - /* - * Specifies the programming to extra LPDDR2 Mode Register - * at warm boot - */ - u32 emc_warm_boot_mrw_extra; - /* - * Specify the enable of extra Mode Register programming at - * warm boot - */ - u32 emc_warm_boot_extramode_reg_write_enable; - /* - * Specify the enable of extra Mode Register programming at - * cold boot - */ - u32 emc_extramode_reg_write_enable; - - /* Specifies the EMC_MRW reset command value */ - u32 emc_mrw_reset_command; - /* Specifies the EMC Reset wait time (in microseconds) */ - u32 emc_mrw_reset_ninit_wait; - /* Specifies the value for EMC_MRS_WAIT_CNT */ - u32 emc_mrs_wait_cnt; - /* Specifies the value for EMC_MRS_WAIT_CNT2 */ - u32 emc_mrs_wait_cnt2; - - /* EMC miscellaneous configurations */ - - /* Specifies the value for EMC_CFG */ - u32 emc_cfg; - /* Specifies the value for EMC_CFG_2 */ - u32 emc_cfg2; - /* Specifies the pipe bypass controls */ - u32 emc_cfg_pipe; - - u32 emc_cfg_pipe_clk; - u32 emc_fdpd_ctrl_cmd_no_ramp; - u32 emc_cfg_update; - - /* Specifies the value for EMC_DBG */ - u32 emc_dbg; - - u32 emc_dbg_write_mux; - - /* Specifies the value for EMC_CMDQ */ - u32 emc_cmd_q; - /* Specifies the value for EMC_MC2EMCQ */ - u32 emc_mc2emc_q; - /* Specifies the value for EMC_DYN_SELF_REF_CONTROL */ - u32 emc_dyn_self_ref_control; - - /* Specifies the value for MEM_INIT_DONE */ - u32 ahb_arbitration_xbar_ctrl_meminit_done; - - /* Specifies the value for EMC_CFG_DIG_DLL */ - u32 emc_cfg_dig_dll; - u32 emc_cfg_dig_dll_1; - - /* Specifies the value for EMC_CFG_DIG_DLL_PERIOD */ - u32 emc_cfg_dig_dll_period; - /* Specifies the value of *DEV_SELECTN of various EMC registers */ - u32 emc_dev_select; - - /* Specifies the value for EMC_SEL_DPD_CTRL */ - u32 emc_sel_dpd_ctrl; - - /* Pads trimmer delays */ - u32 emc_fdpd_ctrl_dq; - u32 emc_fdpd_ctrl_cmd; - u32 emc_pmacro_ib_vref_dq_0; - u32 emc_pmacro_ib_vref_dq_1; - u32 emc_pmacro_ib_vref_dqs_0; - u32 emc_pmacro_ib_vref_dqs_1; - u32 emc_pmacro_ib_rxrt; - u32 emc_cfg_pipe1; - u32 emc_cfg_pipe2; - - /* Specifies the value for EMC_PMACRO_QUSE_DDLL_RANK0_0 */ - u32 emc_pmacro_quse_ddll_rank0_0; - u32 emc_pmacro_quse_ddll_rank0_1; - u32 emc_pmacro_quse_ddll_rank0_2; - u32 emc_pmacro_quse_ddll_rank0_3; - u32 emc_pmacro_quse_ddll_rank0_4; - u32 emc_pmacro_quse_ddll_rank0_5; - u32 emc_pmacro_quse_ddll_rank1_0; - u32 emc_pmacro_quse_ddll_rank1_1; - u32 emc_pmacro_quse_ddll_rank1_2; - u32 emc_pmacro_quse_ddll_rank1_3; - u32 emc_pmacro_quse_ddll_rank1_4; - u32 emc_pmacro_quse_ddll_rank1_5; - - u32 emc_pmacro_ob_ddll_long_dq_rank0_0; - u32 emc_pmacro_ob_ddll_long_dq_rank0_1; - u32 emc_pmacro_ob_ddll_long_dq_rank0_2; - u32 emc_pmacro_ob_ddll_long_dq_rank0_3; - u32 emc_pmacro_ob_ddll_long_dq_rank0_4; - u32 emc_pmacro_ob_ddll_long_dq_rank0_5; - u32 emc_pmacro_ob_ddll_long_dq_rank1_0; - u32 emc_pmacro_ob_ddll_long_dq_rank1_1; - u32 emc_pmacro_ob_ddll_long_dq_rank1_2; - u32 emc_pmacro_ob_ddll_long_dq_rank1_3; - u32 emc_pmacro_ob_ddll_long_dq_rank1_4; - u32 emc_pmacro_ob_ddll_long_dq_rank1_5; - - u32 emc_pmacro_ob_ddll_long_dqs_rank0_0; - u32 emc_pmacro_ob_ddll_long_dqs_rank0_1; - u32 emc_pmacro_ob_ddll_long_dqs_rank0_2; - u32 emc_pmacro_ob_ddll_long_dqs_rank0_3; - u32 emc_pmacro_ob_ddll_long_dqs_rank0_4; - u32 emc_pmacro_ob_ddll_long_dqs_rank0_5; - u32 emc_pmacro_ob_ddll_long_dqs_rank1_0; - u32 emc_pmacro_ob_ddll_long_dqs_rank1_1; - u32 emc_pmacro_ob_ddll_long_dqs_rank1_2; - u32 emc_pmacro_ob_ddll_long_dqs_rank1_3; - u32 emc_pmacro_ob_ddll_long_dqs_rank1_4; - u32 emc_pmacro_ob_ddll_long_dqs_rank1_5; - - u32 emc_pmacro_ib_ddll_long_dqs_rank0_0; - u32 emc_pmacro_ib_ddll_long_dqs_rank0_1; - u32 emc_pmacro_ib_ddll_long_dqs_rank0_2; - u32 emc_pmacro_ib_ddll_long_dqs_rank0_3; - u32 emc_pmacro_ib_ddll_long_dqs_rank1_0; - u32 emc_pmacro_ib_ddll_long_dqs_rank1_1; - u32 emc_pmacro_ib_ddll_long_dqs_rank1_2; - u32 emc_pmacro_ib_ddll_long_dqs_rank1_3; - - u32 emc_pmacro_ddll_long_cmd_0; - u32 emc_pmacro_ddll_long_cmd_1; - u32 emc_pmacro_ddll_long_cmd_2; - u32 emc_pmacro_ddll_long_cmd_3; - u32 emc_pmacro_ddll_long_cmd_4; - u32 emc_pmacro_ddll_short_cmd_0; - u32 emc_pmacro_ddll_short_cmd_1; - u32 emc_pmacro_ddll_short_cmd_2; - - u32 emc_pmacro_ddll_periodic_offset; - - /* - * Specifies the delay after asserting CKE pin during a WarmBoot0 - * sequence (in microseconds) - */ - u32 warm_boot_wait; - - /* Specifies the value for EMC_ODT_WRITE */ - u32 emc_odt_write; - - /* Periodic ZQ calibration */ - - /* - * Specifies the value for EMC_ZCAL_INTERVAL - * Value 0 disables ZQ calibration - */ - u32 emc_zcal_interval; - /* Specifies the value for EMC_ZCAL_WAIT_CNT */ - u32 emc_zcal_wait_cnt; - /* Specifies the value for EMC_ZCAL_MRW_CMD */ - u32 emc_zcal_mrw_cmd; - - /* DRAM initialization sequence flow control */ - - /* Specifies the MRS command value for resetting DLL */ - u32 emc_mrs_reset_dll; - /* Specifies the command for ZQ initialization of device 0 */ - u32 emc_zcal_init_dev0; - /* Specifies the command for ZQ initialization of device 1 */ - u32 emc_zcal_init_dev1; - /* - * Specifies the wait time after programming a ZQ initialization - * command (in microseconds) - */ - u32 emc_zcal_init_wait; - /* - * Specifies the enable for ZQ calibration at cold boot [bit 0] - * and warm boot [bit 1] - */ - u32 emc_zcal_warm_cold_boot_enables; - - /* - * Specifies the MRW command to LPDDR2 for ZQ calibration - * on warmboot - */ - /* Is issued to both devices separately */ - u32 emc_mrw_lpddr2zcal_warm_boot; - /* - * Specifies the ZQ command to DDR3 for ZQ calibration on warmboot - * Is issued to both devices separately - */ - u32 emc_zqcal_ddr3_warm_boot; - - u32 emc_zqcal_lpddr4_warm_boot; - - /* - * Specifies the wait time for ZQ calibration on warmboot - * (in microseconds) - */ - u32 emc_zcal_warm_boot_wait; - /* - * Specifies the enable for DRAM Mode Register programming - * at warm boot - */ - u32 emc_mrs_warm_boot_enable; - /* - * Specifies the wait time after sending an MRS DLL reset command - * in microseconds) - */ - u32 emc_mrs_reset_dll_wait; - /* Specifies the extra MRS command to initialize mode registers */ - u32 emc_mrs_extra; - /* Specifies the extra MRS command at warm boot */ - u32 emc_warm_boot_mrs_extra; - /* Specifies the EMRS command to enable the DDR2 DLL */ - u32 emc_emrs_ddr2_dll_enable; - /* Specifies the MRS command to reset the DDR2 DLL */ - u32 emc_mrs_ddr2_dll_reset; - /* Specifies the EMRS command to set OCD calibration */ - u32 emc_emrs_ddr2_ocd_calib; - /* - * Specifies the wait between initializing DDR and setting OCD - * calibration (in microseconds) - */ - u32 emc_ddr2_wait; - /* Specifies the value for EMC_CLKEN_OVERRIDE */ - u32 emc_clken_override; - /* - * Specifies LOG2 of the extra refresh numbers after booting - * Program 0 to disable - */ - u32 emc_extra_refresh_num; - /* Specifies the master override for all EMC clocks */ - u32 emc_clken_override_allwarm_boot; - /* Specifies the master override for all MC clocks */ - u32 mc_clken_override_allwarm_boot; - /* Specifies digital dll period, choosing between 4 to 64 ms */ - u32 emc_cfg_dig_dll_period_warm_boot; - - /* Pad controls */ - - /* Specifies the value for PMC_VDDP_SEL */ - u32 pmc_vddp_sel; - /* Specifies the wait time after programming PMC_VDDP_SEL */ - u32 pmc_vddp_sel_wait; - /* Specifies the value for PMC_DDR_CFG */ - u32 pmc_ddr_cfg; - /* Specifies the value for PMC_IO_DPD3_REQ */ - u32 pmc_io_dpd3_req; - /* Specifies the wait time after programming PMC_IO_DPD3_REQ */ - u32 pmc_io_dpd3_req_wait; - - u32 pmc_io_dpd4_req_wait; - - /* Specifies the value for PMC_REG_SHORT */ - u32 pmc_reg_short; - /* Specifies the value for PMC_NO_IOPOWER */ - u32 pmc_no_io_power; - - u32 pmc_ddr_ctrl_wait; - u32 pmc_ddr_ctrl; - - /* Specifies the value for EMC_ACPD_CONTROL */ - u32 emc_acpd_control; - - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE0 */ - u32 emc_swizzle_rank0_byte0; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE1 */ - u32 emc_swizzle_rank0_byte1; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE2 */ - u32 emc_swizzle_rank0_byte2; - /* Specifies the value for EMC_SWIZZLE_RANK0_BYTE3 */ - u32 emc_swizzle_rank0_byte3; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE0 */ - u32 emc_swizzle_rank1_byte0; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE1 */ - u32 emc_swizzle_rank1_byte1; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE2 */ - u32 emc_swizzle_rank1_byte2; - /* Specifies the value for EMC_SWIZZLE_RANK1_BYTE3 */ - u32 emc_swizzle_rank1_byte3; - - /* Specifies the value for EMC_TXDSRVTTGEN */ - u32 emc_txdsrvttgen; - - /* Specifies the value for EMC_DATA_BRLSHFT_0 */ - u32 emc_data_brlshft0; - u32 emc_data_brlshft1; - - u32 emc_dqs_brlshft0; - u32 emc_dqs_brlshft1; - - u32 emc_cmd_brlshft0; - u32 emc_cmd_brlshft1; - u32 emc_cmd_brlshft2; - u32 emc_cmd_brlshft3; - - u32 emc_quse_brlshft0; - u32 emc_quse_brlshft1; - u32 emc_quse_brlshft2; - u32 emc_quse_brlshft3; - - u32 emc_dll_cfg0; - u32 emc_dll_cfg1; - - u32 emc_pmc_scratch1; - u32 emc_pmc_scratch2; - u32 emc_pmc_scratch3; - - u32 emc_pmacro_pad_cfg_ctrl; - - u32 emc_pmacro_vttgen_ctrl0; - u32 emc_pmacro_vttgen_ctrl1; - u32 emc_pmacro_vttgen_ctrl2; - u32 emc_pmacro_dsr_vttgen_ctrl0; - u32 emc_pmacro_brick_ctrl_rfu1; - u32 emc_pmacro_cmd_brick_ctrl_fdpd; - u32 emc_pmacro_brick_ctrl_rfu2; - u32 emc_pmacro_data_brick_ctrl_fdpd; - u32 emc_pmacro_bg_bias_ctrl0; - u32 emc_pmacro_data_pad_rx_ctrl; - u32 emc_pmacro_cmd_pad_rx_ctrl; - u32 emc_pmacro_data_rx_term_mode; - u32 emc_pmacro_cmd_rx_term_mode; - u32 emc_pmacro_data_pad_tx_ctrl; - u32 emc_pmacro_cmd_pad_tx_ctrl; - u32 emc_cfg3; - - u32 emc_pmacro_tx_pwrd0; - u32 emc_pmacro_tx_pwrd1; - u32 emc_pmacro_tx_pwrd2; - u32 emc_pmacro_tx_pwrd3; - u32 emc_pmacro_tx_pwrd4; - u32 emc_pmacro_tx_pwrd5; - - u32 emc_config_sample_delay; - - u32 emc_pmacro_brick_mapping0; - u32 emc_pmacro_brick_mapping1; - u32 emc_pmacro_brick_mapping2; - - u32 emc_pmacro_tx_sel_clk_src0; - u32 emc_pmacro_tx_sel_clk_src1; - u32 emc_pmacro_tx_sel_clk_src2; - u32 emc_pmacro_tx_sel_clk_src3; - u32 emc_pmacro_tx_sel_clk_src4; - u32 emc_pmacro_tx_sel_clk_src5; - - u32 emc_pmacro_perbit_fgcg_ctrl0; - u32 emc_pmacro_perbit_fgcg_ctrl1; - u32 emc_pmacro_perbit_fgcg_ctrl2; - u32 emc_pmacro_perbit_fgcg_ctrl3; - u32 emc_pmacro_perbit_fgcg_ctrl4; - u32 emc_pmacro_perbit_fgcg_ctrl5; - u32 emc_pmacro_perbit_rfu_ctrl0; - u32 emc_pmacro_perbit_rfu_ctrl1; - u32 emc_pmacro_perbit_rfu_ctrl2; - u32 emc_pmacro_perbit_rfu_ctrl3; - u32 emc_pmacro_perbit_rfu_ctrl4; - u32 emc_pmacro_perbit_rfu_ctrl5; - u32 emc_pmacro_perbit_rfu1_ctrl0; - u32 emc_pmacro_perbit_rfu1_ctrl1; - u32 emc_pmacro_perbit_rfu1_ctrl2; - u32 emc_pmacro_perbit_rfu1_ctrl3; - u32 emc_pmacro_perbit_rfu1_ctrl4; - u32 emc_pmacro_perbit_rfu1_ctrl5; - - u32 emc_pmacro_data_pi_ctrl; - u32 emc_pmacro_cmd_pi_ctrl; - - u32 emc_pmacro_ddll_bypass; - - u32 emc_pmacro_ddll_pwrd0; - u32 emc_pmacro_ddll_pwrd1; - u32 emc_pmacro_ddll_pwrd2; - - u32 emc_pmacro_cmd_ctrl0; - u32 emc_pmacro_cmd_ctrl1; - u32 emc_pmacro_cmd_ctrl2; - - /* DRAM size information */ - - /* Specifies the value for MC_EMEM_ADR_CFG */ - u32 mc_emem_adr_cfg; - /* Specifies the value for MC_EMEM_ADR_CFG_DEV0 */ - u32 mc_emem_adr_cfg_dev0; - /* Specifies the value for MC_EMEM_ADR_CFG_DEV1 */ - u32 mc_emem_adr_cfg_dev1; - - u32 mc_emem_adr_cfg_channel_mask; - - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG0 */ - u32 mc_emem_adr_cfg_bank_mask0; - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG1 */ - u32 mc_emem_adr_cfg_bank_mask1; - /* Specifies the value for MC_EMEM_BANK_SWIZZLE_CFG2 */ - u32 mc_emem_adr_cfg_bank_mask2; - - /* - * Specifies the value for MC_EMEM_CFG which holds the external memory - * size (in KBytes) - */ - u32 mc_emem_cfg; - - /* MC arbitration configuration */ - - /* Specifies the value for MC_EMEM_ARB_CFG */ - u32 mc_emem_arb_cfg; - /* Specifies the value for MC_EMEM_ARB_OUTSTANDING_REQ */ - u32 mc_emem_arb_outstanding_req; - - u32 emc_emem_arb_refpb_hp_ctrl; - u32 emc_emem_arb_refpb_bank_ctrl; - - /* Specifies the value for MC_EMEM_ARB_TIMING_RCD */ - u32 mc_emem_arb_timing_rcd; - /* Specifies the value for MC_EMEM_ARB_TIMING_RP */ - u32 mc_emem_arb_timing_rp; - /* Specifies the value for MC_EMEM_ARB_TIMING_RC */ - u32 mc_emem_arb_timing_rc; - /* Specifies the value for MC_EMEM_ARB_TIMING_RAS */ - u32 mc_emem_arb_timing_ras; - /* Specifies the value for MC_EMEM_ARB_TIMING_FAW */ - u32 mc_emem_arb_timing_faw; - /* Specifies the value for MC_EMEM_ARB_TIMING_RRD */ - u32 mc_emem_arb_timing_rrd; - /* Specifies the value for MC_EMEM_ARB_TIMING_RAP2PRE */ - u32 mc_emem_arb_timing_rap2pre; - /* Specifies the value for MC_EMEM_ARB_TIMING_WAP2PRE */ - u32 mc_emem_arb_timing_wap2pre; - /* Specifies the value for MC_EMEM_ARB_TIMING_R2R */ - u32 mc_emem_arb_timing_r2r; - /* Specifies the value for MC_EMEM_ARB_TIMING_W2W */ - u32 mc_emem_arb_timing_w2w; - /* Specifies the value for MC_EMEM_ARB_TIMING_R2W */ - u32 mc_emem_arb_timing_r2w; - /* Specifies the value for MC_EMEM_ARB_TIMING_W2R */ - u32 mc_emem_arb_timing_w2r; - - u32 mc_emem_arb_timing_rfcpb; - - /* Specifies the value for MC_EMEM_ARB_DA_TURNS */ - u32 mc_emem_arb_da_turns; - /* Specifies the value for MC_EMEM_ARB_DA_COVERS */ - u32 mc_emem_arb_da_covers; - /* Specifies the value for MC_EMEM_ARB_MISC0 */ - u32 mc_emem_arb_misc0; - /* Specifies the value for MC_EMEM_ARB_MISC1 */ - u32 mc_emem_arb_misc1; - u32 mc_emem_arb_misc2; - - /* Specifies the value for MC_EMEM_ARB_RING1_THROTTLE */ - u32 mc_emem_arb_ring1_throttle; - /* Specifies the value for MC_EMEM_ARB_OVERRIDE */ - u32 mc_emem_arb_override; - /* Specifies the value for MC_EMEM_ARB_OVERRIDE_1 */ - u32 mc_emem_arb_override1; - /* Specifies the value for MC_EMEM_ARB_RSV */ - u32 mc_emem_arb_rsv; - - u32 mc_da_cfg0; - u32 mc_emem_arb_timing_ccdmw; - - /* Specifies the value for MC_CLKEN_OVERRIDE */ - u32 mc_clken_override; - - /* Specifies the value for MC_STAT_CONTROL */ - u32 mc_stat_control; - /* Specifies the value for MC_VIDEO_PROTECT_BOM */ - u32 mc_video_protect_bom; - /* Specifies the value for MC_VIDEO_PROTECT_BOM_ADR_HI */ - u32 mc_video_protect_bom_adr_hi; - /* Specifies the value for MC_VIDEO_PROTECT_SIZE_MB */ - u32 mc_video_protect_size_mb; - /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE */ - u32 mc_video_protect_vpr_override; - /* Specifies the value for MC_VIDEO_PROTECT_VPR_OVERRIDE1 */ - u32 mc_video_protect_vpr_override1; - /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_0 */ - u32 mc_video_protect_gpu_override0; - /* Specifies the value for MC_VIDEO_PROTECT_GPU_OVERRIDE_1 */ - u32 mc_video_protect_gpu_override1; - /* Specifies the value for MC_SEC_CARVEOUT_BOM */ - u32 mc_sec_carveout_bom; - /* Specifies the value for MC_SEC_CARVEOUT_ADR_HI */ - u32 mc_sec_carveout_adr_hi; - /* Specifies the value for MC_SEC_CARVEOUT_SIZE_MB */ - u32 mc_sec_carveout_size_mb; - /* Specifies the value for MC_VIDEO_PROTECT_REG_CTRL.VIDEO_PROTECT_WRITE_ACCESS */ - u32 mc_video_protect_write_access; - /* Specifies the value for MC_SEC_CARVEOUT_REG_CTRL.SEC_CARVEOUT_WRITE_ACCESS */ - u32 mc_sec_carveout_protect_write_access; - - u32 mc_generalized_carveout1_bom; - u32 mc_generalized_carveout1_bom_hi; - u32 mc_generalized_carveout1_size_128kb; - u32 mc_generalized_carveout1_access0; - u32 mc_generalized_carveout1_access1; - u32 mc_generalized_carveout1_access2; - u32 mc_generalized_carveout1_access3; - u32 mc_generalized_carveout1_access4; - u32 mc_generalized_carveout1_force_internal_access0; - u32 mc_generalized_carveout1_force_internal_access1; - u32 mc_generalized_carveout1_force_internal_access2; - u32 mc_generalized_carveout1_force_internal_access3; - u32 mc_generalized_carveout1_force_internal_access4; - u32 mc_generalized_carveout1_cfg0; - - u32 mc_generalized_carveout2_bom; - u32 mc_generalized_carveout2_bom_hi; - u32 mc_generalized_carveout2_size_128kb; - u32 mc_generalized_carveout2_access0; - u32 mc_generalized_carveout2_access1; - u32 mc_generalized_carveout2_access2; - u32 mc_generalized_carveout2_access3; - u32 mc_generalized_carveout2_access4; - u32 mc_generalized_carveout2_force_internal_access0; - u32 mc_generalized_carveout2_force_internal_access1; - u32 mc_generalized_carveout2_force_internal_access2; - u32 mc_generalized_carveout2_force_internal_access3; - u32 mc_generalized_carveout2_force_internal_access4; - u32 mc_generalized_carveout2_cfg0; - - u32 mc_generalized_carveout3_bom; - u32 mc_generalized_carveout3_bom_hi; - u32 mc_generalized_carveout3_size_128kb; - u32 mc_generalized_carveout3_access0; - u32 mc_generalized_carveout3_access1; - u32 mc_generalized_carveout3_access2; - u32 mc_generalized_carveout3_access3; - u32 mc_generalized_carveout3_access4; - u32 mc_generalized_carveout3_force_internal_access0; - u32 mc_generalized_carveout3_force_internal_access1; - u32 mc_generalized_carveout3_force_internal_access2; - u32 mc_generalized_carveout3_force_internal_access3; - u32 mc_generalized_carveout3_force_internal_access4; - u32 mc_generalized_carveout3_cfg0; - - u32 mc_generalized_carveout4_bom; - u32 mc_generalized_carveout4_bom_hi; - u32 mc_generalized_carveout4_size_128kb; - u32 mc_generalized_carveout4_access0; - u32 mc_generalized_carveout4_access1; - u32 mc_generalized_carveout4_access2; - u32 mc_generalized_carveout4_access3; - u32 mc_generalized_carveout4_access4; - u32 mc_generalized_carveout4_force_internal_access0; - u32 mc_generalized_carveout4_force_internal_access1; - u32 mc_generalized_carveout4_force_internal_access2; - u32 mc_generalized_carveout4_force_internal_access3; - u32 mc_generalized_carveout4_force_internal_access4; - u32 mc_generalized_carveout4_cfg0; - - u32 mc_generalized_carveout5_bom; - u32 mc_generalized_carveout5_bom_hi; - u32 mc_generalized_carveout5_size_128kb; - u32 mc_generalized_carveout5_access0; - u32 mc_generalized_carveout5_access1; - u32 mc_generalized_carveout5_access2; - u32 mc_generalized_carveout5_access3; - u32 mc_generalized_carveout5_access4; - u32 mc_generalized_carveout5_force_internal_access0; - u32 mc_generalized_carveout5_force_internal_access1; - u32 mc_generalized_carveout5_force_internal_access2; - u32 mc_generalized_carveout5_force_internal_access3; - u32 mc_generalized_carveout5_force_internal_access4; - u32 mc_generalized_carveout5_cfg0; - - /* Specifies enable for CA training */ - u32 emc_ca_training_enable; - /* Set if bit 6 select is greater than bit 7 select; uses aremc.spec packet SWIZZLE_BIT6_GT_BIT7 */ - u32 swizzle_rank_byte_encode; - /* Specifies enable and offset for patched boot rom write */ - u32 boot_rom_patch_control; - /* Specifies data for patched boot rom write */ - u32 boot_rom_patch_data; - - /* Specifies the value for MC_MTS_CARVEOUT_BOM */ - u32 mc_mts_carveout_bom; - /* Specifies the value for MC_MTS_CARVEOUT_ADR_HI */ - u32 mc_mts_carveout_adr_hi; - /* Specifies the value for MC_MTS_CARVEOUT_SIZE_MB */ - u32 mc_mts_carveout_size_mb; - /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ - u32 mc_mts_carveout_reg_ctrl; - - u32 mc_untranslated_region_check; - - /* Just a place holder for special usage when there is no BCT for certain registers */ - u32 bct_na; -}; - -#endif diff --git a/bdk/mem/sdram_param_t210b01.h b/bdk/mem/sdram_param_t210b01.h index 8bcbed3..f7b956c 100644 --- a/bdk/mem/sdram_param_t210b01.h +++ b/bdk/mem/sdram_param_t210b01.h @@ -225,7 +225,6 @@ typedef struct _sdram_params_t210b01_t u32 emc_r2p; /* Specifies the value for EMC_W2P */ u32 emc_w2p; - /* Specifies the value for EMC_RD_RCD */ u32 emc_tppd; u32 emc_trtm; @@ -235,6 +234,7 @@ typedef struct _sdram_params_t210b01_t u32 emc_tr2ref; u32 emc_ccdmw; + /* Specifies the value for EMC_RD_RCD */ u32 emc_rd_rcd; /* Specifies the value for EMC_WR_RCD */ u32 emc_wr_rcd; diff --git a/bdk/mem/smmu.c b/bdk/mem/smmu.c index 6ee99b9..65b85aa 100644 --- a/bdk/mem/smmu.c +++ b/bdk/mem/smmu.c @@ -1,6 +1,7 @@ /* * Copyright (c) 2018 naehrwert * Copyright (c) 2018 balika011 + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,155 +18,228 @@ #include +#include #include +#include #include #include #include -#include -#include +#include -bool smmu_used = false; -u8 *_pageheap = (u8 *)SMMU_HEAP_ADDR; +/*! SMMU register defines */ +#define SMMU_ASID(asid) (((asid) << 24u) | ((asid) << 16u) | ((asid) << 8u) | (asid)) +#define SMMU_ENABLE BIT(31) +#define SMMU_TLB_ACTIVE_LINES(l) ((l) << 0u) +#define SMMU_TLB_RR_ARBITRATION BIT(28) +#define SMMU_TLB_HIT_UNDER_MISS BIT(29) +#define SMMU_TLB_STATS_ENABLE BIT(31) +#define SMUU_PTC_INDEX_MAP(m) ((m) << 0u) +#define SMUU_PTC_LINE_MASK(m) ((m) << 8u) +#define SMUU_PTC_REQ_LIMIT(l) ((l) << 24u) +#define SMUU_PTC_CACHE_ENABLE BIT(29) +#define SMUU_PTC_STATS_ENABLE BIT(31) -//Enabling SMMU requires a TZ secure write: MC(MC_SMMU_CONFIG) = 1; -u8 smmu_payload[] __attribute__((aligned(16))) = { - 0x41, 0x01, 0x00, 0x58, // 0x00: LDR X1, =0x70019010 +/*! Page table defines */ +#define SMMU_4MB_REGION 0 +#define SMMU_PAGE_TABLE 1 +#define SMMU_PDIR_COUNT 1024 +#define SMMU_PTBL_COUNT 1024 +#define SMMU_PAGE_SHIFT 12u +#define SMMU_PTN_SHIFT SMMU_PAGE_SHIFT +#define SMMU_PDN_SHIFT 22u +#define SMMU_ADDR_TO_PFN(addr) ((addr) >> SMMU_PAGE_SHIFT) +#define SMMU_ADDR_TO_PTN(addr) ((addr) >> SMMU_PTN_SHIFT) +#define SMMU_ADDR_TO_PDN(addr) ((addr) >> SMMU_PDN_SHIFT) +#define SMMU_PTN_TO_ADDR(ptn) ((ptn) << SMMU_PTN_SHIFT) +#define SMMU_PDN_TO_ADDR(pdn) ((pdn) << SMMU_PDN_SHIFT) +#define SMMU_PTB(page, attr) (((attr) << 29u) | ((page) >> SMMU_PAGE_SHIFT)) + +static void *smmu_heap = (void *)SMMU_HEAP_ADDR; + +// Enabling SMMU requires a TZ (EL3) secure write. MC(MC_SMMU_CONFIG) = 1; +static const u8 smmu_enable_payload[] = { + 0xC1, 0x00, 0x00, 0x18, // 0x00: LDR W1, =0x70019010 0x20, 0x00, 0x80, 0xD2, // 0x04: MOV X0, #0x1 0x20, 0x00, 0x00, 0xB9, // 0x08: STR W0, [X1] 0x1F, 0x71, 0x08, 0xD5, // 0x0C: IC IALLUIS 0x9F, 0x3B, 0x03, 0xD5, // 0x10: DSB ISH 0xFE, 0xFF, 0xFF, 0x17, // 0x14: B loop - 0x00, 0x00, 0x80, 0xD2, // 0x18: MOV X0, #0x0 - 0x20, 0x00, 0x00, 0xB9, // 0x1C: STR W0, [X1] - 0x80, 0x00, 0x00, 0x58, // 0x20: LDR X0, =0x4002B000 - 0x00, 0x00, 0x1F, 0xD6, // 0x28: BR X0 - 0x10, 0x90, 0x01, 0x70, // 0x28: MC_SMMU_CONFIG - 0x00, 0x00, 0x00, 0x00, // 0x2C: - 0x00, 0x00, 0x00, 0x00, // 0x30: secmon address - 0x00, 0x00, 0x00, 0x00 // 0x34: + 0x10, 0x90, 0x01, 0x70, // 0x18: MC_SMMU_CONFIG }; -void *page_alloc(u32 num) +void *smmu_page_zalloc(u32 num) { - u8 *res = _pageheap; - _pageheap += 0x1000 * num; - memset(res, 0, 0x1000 * num); - return res; + void *page = smmu_heap; + memset(page, 0, SZ_PAGE * num); + + smmu_heap += SZ_PAGE * num; + + return page; } -u32 *smmu_alloc_pdir() +static pde_t *_smmu_pdir_alloc() { - u32 *pdir = (u32 *)page_alloc(1); - for (int pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++) - pdir[pdn] = _PDE_VACANT(pdn); + pde_t *pdir = (pde_t *)smmu_page_zalloc(1); + + // Initialize pdes with no permissions. + for (u32 pdn = 0; pdn < SMMU_PDIR_COUNT; pdn++) + pdir[pdn].huge.page = pdn; + return pdir; } -void smmu_flush_regs() +static void _smmu_flush_regs() { (void)MC(MC_SMMU_PTB_DATA); } void smmu_flush_all() { + + // Flush the entire page table cache. MC(MC_SMMU_PTC_FLUSH) = 0; - smmu_flush_regs(); + _smmu_flush_regs(); + + // Flush the entire table. MC(MC_SMMU_TLB_FLUSH) = 0; - smmu_flush_regs(); + _smmu_flush_regs(); } -void smmu_init(u32 secmon_base) +void smmu_init() { - MC(MC_SMMU_PTB_ASID) = 0; - MC(MC_SMMU_PTB_DATA) = 0; - MC(MC_SMMU_TLB_CONFIG) = 0x30000030; - MC(MC_SMMU_PTC_CONFIG) = 0x28000F3F; - MC(MC_SMMU_PTC_FLUSH) = 0; - MC(MC_SMMU_TLB_FLUSH) = 0; - - // Set the secmon address - *(u32 *)(smmu_payload + 0x30) = secmon_base; + MC(MC_SMMU_PTB_ASID) = 0; + MC(MC_SMMU_PTB_DATA) = 0; + MC(MC_SMMU_TLB_CONFIG) = SMMU_TLB_HIT_UNDER_MISS | SMMU_TLB_RR_ARBITRATION | SMMU_TLB_ACTIVE_LINES(48); + MC(MC_SMMU_PTC_CONFIG) = SMUU_PTC_CACHE_ENABLE | SMUU_PTC_REQ_LIMIT(8) | SMUU_PTC_LINE_MASK(0xF) | SMUU_PTC_INDEX_MAP(0x3F); + MC(MC_SMMU_PTC_FLUSH) = 0; + MC(MC_SMMU_TLB_FLUSH) = 0; } void smmu_enable() { - if (smmu_used) + static bool enabled = false; + + if (enabled) return; - ccplex_boot_cpu0((u32)smmu_payload); - smmu_used = true; - msleep(150); + // Launch payload on CCPLEX in order to set SMMU enable bit. + ccplex_boot_cpu0((u32)smmu_enable_payload, false); + msleep(100); + ccplex_powergate_cpu0(); smmu_flush_all(); + + enabled = true; } -bool smmu_is_used() +void smmu_reset_heap() { - return smmu_used; + smmu_heap = (void *)SMMU_HEAP_ADDR; } -void smmu_exit() +void *smmu_init_domain(u32 dev_base, u32 asid) { - *(u32 *)(smmu_payload + 0x14) = _NOP(); -} - -u32 *smmu_init_domain4(u32 dev_base, u32 asid) -{ - u32 *pdir = smmu_alloc_pdir(); + void *ptb = _smmu_pdir_alloc(); MC(MC_SMMU_PTB_ASID) = asid; - MC(MC_SMMU_PTB_DATA) = SMMU_MK_PDIR((u32)pdir, _PDIR_ATTR); - smmu_flush_regs(); + MC(MC_SMMU_PTB_DATA) = SMMU_PTB((u32)ptb, SMMU_ATTR_ALL); + _smmu_flush_regs(); - MC(dev_base) = 0x80000000 | (asid << 24) | (asid << 16) | (asid << 8) | (asid); - smmu_flush_regs(); + // Use the same macro for both quad and single domains. Reserved bits are not set anyway. + MC(dev_base) = SMMU_ENABLE | SMMU_ASID(asid); + _smmu_flush_regs(); - return pdir; + return ptb; } -u32 *smmu_get_pte(u32 *pdir, u32 iova) +void smmu_deinit_domain(u32 dev_base, u32 asid) { - u32 ptn = SMMU_ADDR_TO_PFN(iova); - u32 pdn = SMMU_ADDR_TO_PDN(iova); - u32 *ptbl; + MC(MC_SMMU_PTB_ASID) = asid; + MC(MC_SMMU_PTB_DATA) = 0; + MC(dev_base) = 0; + _smmu_flush_regs(); +} - if (pdir[pdn] != _PDE_VACANT(pdn)) - ptbl = (u32 *)((pdir[pdn] & SMMU_PFN_MASK) << SMMU_PDIR_SHIFT); +void smmu_domain_bypass(u32 dev_base, bool bypass) +{ + if (bypass) + { + smmu_flush_all(); + bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false); + MC(dev_base) &= ~SMMU_ENABLE; + } else { - ptbl = (u32 *)page_alloc(1); + bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false); + MC(dev_base) |= SMMU_ENABLE; + smmu_flush_all(); + } + _smmu_flush_regs(); +} + +static pte_t *_smmu_get_pte(pde_t *pdir, u32 iova) +{ + u32 pdn = SMMU_ADDR_TO_PDN(iova); + pte_t *ptbl; + + // Get 4MB page table or initialize one. + if (pdir[pdn].tbl.attr) + ptbl = (pte_t *)(SMMU_PTN_TO_ADDR(pdir[pdn].tbl.table)); + else + { + // Allocate page table. + ptbl = (pte_t *)smmu_page_zalloc(1); + + // Get address. u32 addr = SMMU_PDN_TO_ADDR(pdn); - for (int pn = 0; pn < SMMU_PTBL_COUNT; pn++, addr += SMMU_PAGE_SIZE) - ptbl[pn] = _PTE_VACANT(addr); - pdir[pdn] = SMMU_MK_PDE((u32)ptbl, _PDE_ATTR | _PDE_NEXT); + + // Initialize page table with no permissions. + for (u32 pn = 0; pn < SMMU_PTBL_COUNT; pn++, addr += SZ_PAGE) + ptbl[pn].page = SMMU_ADDR_TO_PFN(addr); + + // Set page table to the page directory. + pdir[pdn].tbl.table = SMMU_ADDR_TO_PTN((u32)ptbl); + pdir[pdn].tbl.next = SMMU_PAGE_TABLE; + pdir[pdn].tbl.attr = SMMU_ATTR_ALL; + smmu_flush_all(); } - return &ptbl[ptn % SMMU_PTBL_COUNT]; + return &ptbl[SMMU_ADDR_TO_PTN(iova) % SMMU_PTBL_COUNT]; } -void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr) +void smmu_map(void *ptb, u32 iova, u64 iopa, u32 pages, u32 attr) { - for (int i = 0; i < cnt; i++) + // Map pages to page table entries. VA/PA should be aligned to 4KB. + for (u32 i = 0; i < pages; i++) { - u32 *pte = smmu_get_pte(pdir, addr); - *pte = SMMU_ADDR_TO_PFN(page) | attr; - addr += 0x1000; - page += 0x1000; + pte_t *pte = _smmu_get_pte((pde_t *)ptb, iova); + + pte->page = SMMU_ADDR_TO_PFN(iopa); + pte->attr = attr; + + iova += SZ_PAGE; + iopa += SZ_PAGE; } + smmu_flush_all(); } -u32 *smmu_init_for_tsec() +void smmu_map_huge(void *ptb, u32 iova, u64 iopa, u32 regions, u32 attr) { - return smmu_init_domain4(MC_SMMU_TSEC_ASID, 1); -} + pde_t *pdir = (pde_t *)ptb; -void smmu_deinit_for_tsec() -{ - MC(MC_SMMU_PTB_ASID) = 1; - MC(MC_SMMU_PTB_DATA) = 0; - MC(MC_SMMU_TSEC_ASID) = 0; - smmu_flush_regs(); -} + // Map 4MB regions to page directory entries. VA/PA should be aligned to 4MB. + for (u32 i = 0; i < regions; i++) + { + u32 pdn = SMMU_ADDR_TO_PDN(iova); + pdir[pdn].huge.page = SMMU_ADDR_TO_PDN(iopa); + pdir[pdn].huge.next = SMMU_4MB_REGION; + pdir[pdn].huge.attr = attr; + iova += SZ_4M; + iopa += SZ_4M; + } + + smmu_flush_all(); +} diff --git a/bdk/mem/smmu.h b/bdk/mem/smmu.h index 7846253..e45a672 100644 --- a/bdk/mem/smmu.h +++ b/bdk/mem/smmu.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2018 naehrwert + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,69 +15,57 @@ * along with this program. If not, see . */ +#include + #include -#define SMMU_HEAP_ADDR 0xA0000000 - -#define MC_INTSTATUS 0x0 -#define MC_INTMASK 0x4 -#define MC_ERR_STATUS 0x8 -#define MC_ERR_ADR 0xc -#define MC_SMMU_CONFIG 0x10 -#define MC_SMMU_TLB_CONFIG 0x14 -#define MC_SMMU_PTC_CONFIG 0x18 -#define MC_SMMU_PTB_ASID 0x1c -#define MC_SMMU_PTB_DATA 0x20 -#define MC_SMMU_TLB_FLUSH 0x30 -#define MC_SMMU_PTC_FLUSH 0x34 -#define MC_SMMU_ASID_SECURITY 0x38 +#define MC_SMMU_AVPC_ASID 0x23C #define MC_SMMU_TSEC_ASID 0x294 -#define MC_SMMU_TRANSLATION_ENABLE_0 0x228 -#define MC_SMMU_TRANSLATION_ENABLE_1 0x22c -#define MC_SMMU_TRANSLATION_ENABLE_2 0x230 -#define MC_SMMU_TRANSLATION_ENABLE_3 0x234 -#define MC_SMMU_TRANSLATION_ENABLE_4 0xb98 -#define SMMU_PDE_NEXT_SHIFT 28 -#define MC_SMMU_PTB_DATA_0_ASID_NONSECURE_SHIFT 29 -#define MC_SMMU_PTB_DATA_0_ASID_WRITABLE_SHIFT 30 -#define MC_SMMU_PTB_DATA_0_ASID_READABLE_SHIFT 31 -#define SMMU_PAGE_SHIFT 12 -#define SMMU_PAGE_SIZE (1 << SMMU_PAGE_SHIFT) -#define SMMU_PDIR_COUNT 1024 -#define SMMU_PDIR_SIZE (sizeof(u32) * SMMU_PDIR_COUNT) -#define SMMU_PTBL_COUNT 1024 -#define SMMU_PTBL_SIZE (sizeof(u32) * SMMU_PTBL_COUNT) -#define SMMU_PDIR_SHIFT 12 -#define SMMU_PDE_SHIFT 12 -#define SMMU_PTE_SHIFT 12 -#define SMMU_PFN_MASK 0x000FFFFF -#define SMMU_ADDR_TO_PFN(addr) ((addr) >> 12) -#define SMMU_ADDR_TO_PDN(addr) ((addr) >> 22) -#define SMMU_PDN_TO_ADDR(addr) ((pdn) << 22) -#define _READABLE (1 << MC_SMMU_PTB_DATA_0_ASID_READABLE_SHIFT) -#define _WRITABLE (1 << MC_SMMU_PTB_DATA_0_ASID_WRITABLE_SHIFT) -#define _NONSECURE (1 << MC_SMMU_PTB_DATA_0_ASID_NONSECURE_SHIFT) -#define _PDE_NEXT (1 << SMMU_PDE_NEXT_SHIFT) -#define _MASK_ATTR (_READABLE | _WRITABLE | _NONSECURE) -#define _PDIR_ATTR (_READABLE | _WRITABLE | _NONSECURE) -#define _PDE_ATTR (_READABLE | _WRITABLE | _NONSECURE) -#define _PDE_VACANT(pdn) (((pdn) << 10) | _PDE_ATTR) -#define _PTE_ATTR (_READABLE | _WRITABLE | _NONSECURE) -#define _PTE_VACANT(addr) (((addr) >> SMMU_PAGE_SHIFT) | _PTE_ATTR) -#define SMMU_MK_PDIR(page, attr) (((page) >> SMMU_PDIR_SHIFT) | (attr)) -#define SMMU_MK_PDE(page, attr) (((page) >> SMMU_PDE_SHIFT) | (attr)) +#define SMMU_NS BIT(0) +#define SMMU_WRITE BIT(1) +#define SMMU_READ BIT(2) +#define SMMU_ATTR_ALL (SMMU_READ | SMMU_WRITE | SMMU_NS) -void *page_alloc(u32 num); -u32 *smmu_alloc_pdir(); -void smmu_flush_regs(); -void smmu_flush_all(); -void smmu_init(u32 secmon_base); -void smmu_enable(); -bool smmu_is_used(); -void smmu_exit(); -u32 *smmu_init_domain4(u32 dev_base, u32 asid); -u32 *smmu_get_pte(u32 *pdir, u32 iova); -void smmu_map(u32 *pdir, u32 addr, u32 page, int cnt, u32 attr); -u32 *smmu_init_for_tsec(); -void smmu_deinit_for_tsec(); +typedef struct _pde_t { + union { + union { + struct { + u32 table:22; + u32 rsvd:6; + u32 next:1; + u32 attr:3; + } tbl; + + struct { + u32 rsvd_:10; + u32 page:12; + u32 rsvd:6; + u32 next:1; + u32 attr:3; + } huge; + }; + + u32 pde; + }; +} pde_t; + +typedef struct _pte_t { + u32 page:22; + u32 rsvd:7; + u32 attr:3; +} pte_t; + +static_assert(sizeof(pde_t) == sizeof(u32), "pde_t size is wrong!"); +static_assert(sizeof(pte_t) == sizeof(u32), "pte_t size is wrong!"); + +void *smmu_page_zalloc(u32 num); +void smmu_flush_all(); +void smmu_init(); +void smmu_enable(); +void smmu_reset_heap(); +void *smmu_init_domain(u32 dev_base, u32 asid); +void smmu_deinit_domain(u32 dev_base, u32 asid); +void smmu_domain_bypass(u32 dev_base, bool bypass); +void smmu_map(void *ptb, u32 iova, u64 iopa, u32 pages, u32 attr); +void smmu_map_huge(void *ptb, u32 iova, u64 iopa, u32 regions, u32 attr); diff --git a/bdk/memory_map.h b/bdk/memory_map.h index 848fc1c..c687f2c 100644 --- a/bdk/memory_map.h +++ b/bdk/memory_map.h @@ -17,34 +17,42 @@ #ifndef _MEMORY_MAP_H_ #define _MEMORY_MAP_H_ -//#define IPL_STACK_TOP 0x4003FF00 /* --- BIT/BCT: 0x40000000 - 0x40003000 --- */ /* --- IPL: 0x40008000 - 0x40028000 --- */ #define LDR_LOAD_ADDR 0x40007000 #define IPL_LOAD_ADDR 0x40008000 -#define IPL_SZ_MAX 0x20000 // 128KB. +#define IPL_SZ_MAX SZ_128K -/* --- XUSB EP context and TRB ring buffers --- */ -#define XUSB_RING_ADDR 0x40020000 +#define XUSB_RING_ADDR 0x40020000 // XUSB EP context and TRB ring buffers. -#define SECMON_MIN_START 0x4002B000 +#define SECMON_MIN_START 0x4002B000 // Minimum reserved address for secmon. #define SDRAM_PARAMS_ADDR 0x40030000 // SDRAM extraction buffer during sdram init. -#define CBFS_DRAM_EN_ADDR 0x4003e000 // u32. + +/* start.S / exception_handlers.S */ +#define SYS_STACK_TOP_INIT 0x4003FF00 +#define FIQ_STACK_TOP 0x40040000 +#define IRQ_STACK_TOP 0x40040000 +#define IPL_RELOC_ADDR 0x4003FF00 +#define IPL_RELOC_SZ 0x10 +#define EXCP_STORAGE_ADDR 0x4003FFF0 +#define EXCP_STORAGE_SZ 0x10 /* --- DRAM START --- */ #define DRAM_START 0x80000000 -#define HOS_RSVD 0x1000000 // Do not write anything in this area. +#define HOS_RSVD SZ_16M // Do not write anything in this area. #define NYX_LOAD_ADDR 0x81000000 -#define NYX_SZ_MAX 0x1000000 // 16MB +#define NYX_SZ_MAX SZ_16M /* --- Gap: 0x82000000 - 0x82FFFFFF --- */ /* Stack theoretical max: 33MB */ #define IPL_STACK_TOP 0x83100000 #define IPL_HEAP_START 0x84000000 -#define IPL_HEAP_SZ 0x20000000 // 512MB. +#define IPL_HEAP_SZ (SZ_512M - SZ_64M) + +#define SMMU_HEAP_ADDR 0xA0000000 /* --- Gap: 1040MB 0xA4000000 - 0xE4FFFFFF --- */ // Virtual disk / Chainloader buffers. @@ -60,25 +68,25 @@ // L4T Kernel Panic Storage (PSTORE). #define PSTORE_ADDR 0xB0000000 -#define PSTORE_SZ 0x200000 // 2MB. +#define PSTORE_SZ SZ_2M //#define DRAM_LIB_ADDR 0xE0000000 /* --- Chnldr: 252MB 0xC03C0000 - 0xCFFFFFFF --- */ //! Only used when chainloading. // SDMMC DMA buffers 1 #define SDMMC_UPPER_BUFFER 0xE5000000 -#define SDMMC_UP_BUF_SZ 0x8000000 // 128MB. +#define SDMMC_UP_BUF_SZ SZ_128M // Nyx buffers. #define NYX_STORAGE_ADDR 0xED000000 #define NYX_RES_ADDR 0xEE000000 -#define NYX_RES_SZ 0x1000000 // 16MB. +#define NYX_RES_SZ SZ_16M // SDMMC DMA buffers 2 #define SDXC_BUF_ALIGNED 0xEF000000 #define MIXD_BUF_ALIGNED 0xF0000000 #define EMMC_BUF_ALIGNED MIXD_BUF_ALIGNED -#define SDMMC_DMA_BUF_SZ 0x1000000 // 16MB (4MB currently used). +#define SDMMC_DMA_BUF_SZ SZ_16M // 4MB currently used. // Nyx LvGL buffers. #define NYX_LV_VDB_ADR 0xF1000000 @@ -95,6 +103,7 @@ #define NYX_FB2_ADDRESS 0xF6600000 #define NYX_FB_SZ 0x384000 // 1280 x 720 x 4. +/* OBSOLETE: Very old hwinit based payloads were setting a carveout here. */ #define DRAM_MEM_HOLE_ADR 0xF6A00000 #define DRAM_MEM_HOLE_SZ 0x8140000 /* --- Hole: 129MB 0xF6A00000 - 0xFEB3FFFF --- */ @@ -106,7 +115,7 @@ #define USB_EP_CONTROL_BUF_ADDR 0xFEF80000 #define USB_EP_BULK_IN_BUF_ADDR 0xFF000000 #define USB_EP_BULK_OUT_BUF_ADDR 0xFF800000 -#define USB_EP_BULK_OUT_MAX_XFER 0x800000 +#define USB_EP_BULK_OUT_MAX_XFER SZ_8M // #define EXT_PAYLOAD_ADDR 0xC0000000 // #define RCM_PAYLOAD_ADDR (EXT_PAYLOAD_ADDR + ALIGN(PATCHED_RELOC_SZ, 0x10)) diff --git a/bdk/power/bm92t36.c b/bdk/power/bm92t36.c index d1496f7..371ed04 100644 --- a/bdk/power/bm92t36.c +++ b/bdk/power/bm92t36.c @@ -1,7 +1,7 @@ /* * USB-PD driver for Nintendo Switch's TI BM92T36 * - * Copyright (c) 2020 CTCaer + * Copyright (c) 2020-2023 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -73,18 +73,23 @@ void bm92t36_get_sink_info(bool *inserted, usb_pd_objects_t *usb_pd) if (inserted) { + memset(buf, 0, sizeof(buf)); _bm92t36_read_reg(buf, 2, STATUS1_REG); - *inserted = buf[0] & STATUS1_INSERT ? true : false; + *inserted = (buf[0] & STATUS1_INSERT) ? true : false; } if (usb_pd) { + memset(buf, 0, sizeof(buf)); _bm92t36_read_reg(buf, 29, READ_PDOS_SRC_REG); memcpy(pdos, &buf[1], 28); memset(usb_pd, 0, sizeof(usb_pd_objects_t)); usb_pd->pdo_no = buf[0] / sizeof(pd_object_t); + if (usb_pd->pdo_no > 7) + usb_pd->pdo_no = 7; + for (u32 i = 0; i < usb_pd->pdo_no; i++) { usb_pd->pdos[i].amperage = pdos[i].amp * 10; diff --git a/bdk/power/bq24193.c b/bdk/power/bq24193.c index 2b2e744..5194279 100644 --- a/bdk/power/bq24193.c +++ b/bdk/power/bq24193.c @@ -29,127 +29,128 @@ int bq24193_get_property(enum BQ24193_reg_prop prop, int *value) { u8 data; - switch (prop) { - case BQ24193_InputVoltageLimit: // Input voltage limit (mV). - data = bq24193_get_reg(BQ24193_InputSource); - data = (data & BQ24193_INCONFIG_VINDPM_MASK) >> 3; - *value = 0; - *value += ((data >> 0) & 1) ? 80 : 0; - *value += ((data >> 1) & 1) ? 160 : 0; - *value += ((data >> 2) & 1) ? 320 : 0; - *value += ((data >> 3) & 1) ? 640 : 0; - *value += 3880; + switch (prop) + { + case BQ24193_InputVoltageLimit: // Input voltage limit (mV). + data = bq24193_get_reg(BQ24193_InputSource); + data = (data & BQ24193_INCONFIG_VINDPM_MASK) >> 3; + *value = 0; + *value += ((data >> 0) & 1) ? 80 : 0; + *value += ((data >> 1) & 1) ? 160 : 0; + *value += ((data >> 2) & 1) ? 320 : 0; + *value += ((data >> 3) & 1) ? 640 : 0; + *value += 3880; + break; + case BQ24193_InputCurrentLimit: // Input current limit (mA). + data = bq24193_get_reg(BQ24193_InputSource); + data &= BQ24193_INCONFIG_INLIMIT_MASK; + switch (data) + { + case 0: + *value = 100; break; - case BQ24193_InputCurrentLimit: // Input current limit (mA). - data = bq24193_get_reg(BQ24193_InputSource); - data &= BQ24193_INCONFIG_INLIMIT_MASK; - switch (data) - { - case 0: - *value = 100; - break; - case 1: - *value = 150; - break; - case 2: - *value = 500; - break; - case 3: - *value = 900; - break; - case 4: - *value = 1200; - break; - case 5: - *value = 1500; - break; - case 6: - *value = 2000; - break; - case 7: - *value = 3000; - break; - } + case 1: + *value = 150; break; - case BQ24193_SystemMinimumVoltage: // Minimum system voltage limit (mV). - data = bq24193_get_reg(BQ24193_PORConfig); - *value = (data & BQ24193_PORCONFIG_SYSMIN_MASK) >> 1; - *value *= 100; - *value += 3000; + case 2: + *value = 500; break; - case BQ24193_FastChargeCurrentLimit: // Fast charge current limit (mA). - data = bq24193_get_reg(BQ24193_ChrgCurr); - data = (data & BQ24193_CHRGCURR_ICHG_MASK) >> 2; - *value = 0; - *value += ((data >> 0) & 1) ? 64 : 0; - *value += ((data >> 1) & 1) ? 128 : 0; - *value += ((data >> 2) & 1) ? 256 : 0; - *value += ((data >> 3) & 1) ? 512 : 0; - *value += ((data >> 4) & 1) ? 1024 : 0; - *value += ((data >> 5) & 1) ? 2048 : 0; - *value += 512; - data = bq24193_get_reg(BQ24193_ChrgCurr); - data &= BQ24193_CHRGCURR_20PCT_MASK; - if (data) - *value = *value * 20 / 100; // Fast charge current limit is 20%. + case 3: + *value = 900; break; - case BQ24193_ChargeVoltageLimit: // Charge voltage limit (mV). - data = bq24193_get_reg(BQ24193_ChrgVolt); - data = (data & BQ24193_CHRGVOLT_VREG) >> 2; - *value = 0; - *value += ((data >> 0) & 1) ? 16 : 0; - *value += ((data >> 1) & 1) ? 32 : 0; - *value += ((data >> 2) & 1) ? 64 : 0; - *value += ((data >> 3) & 1) ? 128 : 0; - *value += ((data >> 4) & 1) ? 256 : 0; - *value += ((data >> 5) & 1) ? 512 : 0; - *value += 3504; + case 4: + *value = 1200; break; - case BQ24193_RechargeThreshold: // Recharge voltage threshold less than voltage limit (mV). - data = bq24193_get_reg(BQ24193_ChrgVolt); - data &= BQ24193_IRTHERMAL_THERM_MASK; - if (data) - *value = 300; - else - *value = 100; + case 5: + *value = 1500; break; - case BQ24193_ThermalRegulation: // Thermal regulation threshold (oC). - data = bq24193_get_reg(BQ24193_IRCompThermal); - data &= BQ24193_IRTHERMAL_THERM_MASK; - switch (data) - { - case 0: - *value = 60; - break; - case 1: - *value = 80; - break; - case 2: - *value = 100; - break; - case 3: - *value = 120; - break; - } + case 6: + *value = 2000; break; - case BQ24193_ChargeStatus: // 0: Not charging, 1: Pre-charge, 2: Fast charging, 3: Charge termination done - data = bq24193_get_reg(BQ24193_Status); - *value = (data & BQ24193_STATUS_CHRG_MASK) >> 4; + case 7: + *value = 3000; break; - case BQ24193_TempStatus: // 0: Normal, 2: Warm, 3: Cool, 5: Cold, 6: Hot. - data = bq24193_get_reg(BQ24193_FaultReg); - *value = data & BQ24193_FAULT_THERM_MASK; + } + break; + case BQ24193_SystemMinimumVoltage: // Minimum system voltage limit (mV). + data = bq24193_get_reg(BQ24193_PORConfig); + *value = (data & BQ24193_PORCONFIG_SYSMIN_MASK) >> 1; + *value *= 100; + *value += 3000; + break; + case BQ24193_FastChargeCurrentLimit: // Fast charge current limit (mA). + data = bq24193_get_reg(BQ24193_ChrgCurr); + data = (data & BQ24193_CHRGCURR_ICHG_MASK) >> 2; + *value = 0; + *value += ((data >> 0) & 1) ? 64 : 0; + *value += ((data >> 1) & 1) ? 128 : 0; + *value += ((data >> 2) & 1) ? 256 : 0; + *value += ((data >> 3) & 1) ? 512 : 0; + *value += ((data >> 4) & 1) ? 1024 : 0; + *value += ((data >> 5) & 1) ? 2048 : 0; + *value += 512; + data = bq24193_get_reg(BQ24193_ChrgCurr); + data &= BQ24193_CHRGCURR_20PCT_MASK; + if (data) + *value = *value * 20 / 100; // Fast charge current limit is 20%. + break; + case BQ24193_ChargeVoltageLimit: // Charge voltage limit (mV). + data = bq24193_get_reg(BQ24193_ChrgVolt); + data = (data & BQ24193_CHRGVOLT_VREG) >> 2; + *value = 0; + *value += ((data >> 0) & 1) ? 16 : 0; + *value += ((data >> 1) & 1) ? 32 : 0; + *value += ((data >> 2) & 1) ? 64 : 0; + *value += ((data >> 3) & 1) ? 128 : 0; + *value += ((data >> 4) & 1) ? 256 : 0; + *value += ((data >> 5) & 1) ? 512 : 0; + *value += 3504; + break; + case BQ24193_RechargeThreshold: // Recharge voltage threshold less than voltage limit (mV). + data = bq24193_get_reg(BQ24193_ChrgVolt); + data &= BQ24193_IRTHERMAL_THERM_MASK; + if (data) + *value = 300; + else + *value = 100; + break; + case BQ24193_ThermalRegulation: // Thermal regulation threshold (oC). + data = bq24193_get_reg(BQ24193_IRCompThermal); + data &= BQ24193_IRTHERMAL_THERM_MASK; + switch (data) + { + case 0: + *value = 60; break; - case BQ24193_DevID: // Dev ID. - data = bq24193_get_reg(BQ24193_VendorPart); - *value = data & BQ24193_VENDORPART_DEV_MASK; + case 1: + *value = 80; break; - case BQ24193_ProductNumber: // Product number. - data = bq24193_get_reg(BQ24193_VendorPart); - *value = (data & BQ24193_VENDORPART_PN_MASK) >> 3; + case 2: + *value = 100; break; - default: - return -1; + case 3: + *value = 120; + break; + } + break; + case BQ24193_ChargeStatus: // 0: Not charging, 1: Pre-charge, 2: Fast charging, 3: Charge termination done + data = bq24193_get_reg(BQ24193_Status); + *value = (data & BQ24193_STATUS_CHRG_MASK) >> 4; + break; + case BQ24193_TempStatus: // 0: Normal, 2: Warm, 3: Cool, 5: Cold, 6: Hot. + data = bq24193_get_reg(BQ24193_FaultReg); + *value = data & BQ24193_FAULT_THERM_MASK; + break; + case BQ24193_DevID: // Dev ID. + data = bq24193_get_reg(BQ24193_VendorPart); + *value = data & BQ24193_VENDORPART_DEV_MASK; + break; + case BQ24193_ProductNumber: // Product number. + data = bq24193_get_reg(BQ24193_VendorPart); + *value = (data & BQ24193_VENDORPART_PN_MASK) >> 3; + break; + default: + return -1; } return 0; } diff --git a/bdk/power/bq24193.h b/bdk/power/bq24193.h index 1b6e717..399e225 100644 --- a/bdk/power/bq24193.h +++ b/bdk/power/bq24193.h @@ -28,7 +28,7 @@ // REG 1 masks. #define BQ24193_PORCONFIG_BOOST_MASK (1<<0) -#define BQ24193_PORCONFIG_SYSMIN_MASK (7<<1) +#define BQ24193_PORCONFIG_SYSMIN_MASK (7<<1) // 3000uV HOS default. #define BQ24193_PORCONFIG_CHGCONFIG_MASK (3<<4) #define BQ24193_PORCONFIG_CHGCONFIG_CHARGER_EN (1<<4) #define BQ24193_PORCONFIG_I2CWATCHDOG_MASK (1<<6) diff --git a/bdk/power/max17050.c b/bdk/power/max17050.c index a561724..8c4f658 100644 --- a/bdk/power/max17050.c +++ b/bdk/power/max17050.c @@ -24,7 +24,7 @@ #include "max17050.h" #include -#include +#include #define BASE_SNS_UOHM 5000 @@ -279,3 +279,26 @@ int max17050_fix_configuration() return 0; } + +void max17050_dump_regs(void *buf) +{ + u16 *buff = (u16 *)buf; + + // Unlock model table. + u16 unlock = 0x59; + i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_MODELEnable1, (u8 *)&unlock, 2); + unlock = 0xC4; + i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_MODELEnable2, (u8 *)&unlock, 2); + + // Dump all battery fuel gauge registers. + for (u32 i = 0; i < 0x100; i++) + { + buff[i] = max17050_get_reg(i); + msleep(1); + } + + // Lock model table. + unlock = 0; + i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_MODELEnable1, (u8 *)&unlock, 2); + i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_MODELEnable2, (u8 *)&unlock, 2); +} diff --git a/bdk/power/max17050.h b/bdk/power/max17050.h index a9b3d37..438f55a 100644 --- a/bdk/power/max17050.h +++ b/bdk/power/max17050.h @@ -130,8 +130,9 @@ enum MAX17050_reg { MAX17050_VFSOC = 0xFF, }; -int max17050_get_property(enum MAX17050_reg reg, int *value); -int max17050_fix_configuration(); -u32 max17050_get_cached_batt_volt(); +int max17050_get_property(enum MAX17050_reg reg, int *value); +int max17050_fix_configuration(); +void max17050_dump_regs(void *buf); +u32 max17050_get_cached_batt_volt(); #endif /* __MAX17050_H_ */ diff --git a/bdk/power/max77620.h b/bdk/power/max77620.h index d54909f..3d41459 100644 --- a/bdk/power/max77620.h +++ b/bdk/power/max77620.h @@ -95,9 +95,9 @@ #define MAX77620_IRQSD_PFI_SD1 BIT(6) #define MAX77620_IRQSD_PFI_SD0 BIT(7) -#define MAX77620_REG_IRQ_LVL2_L0_7 0x08 // LDO number that irq occured. +#define MAX77620_REG_IRQ_LVL2_L0_7 0x08 // LDO number that irq occurred. #define MAX77620_REG_IRQ_MSK_L0_7 0x10 -#define MAX77620_REG_IRQ_LVL2_L8 0x09 // LDO number that irq occured. Only bit0: LDO8 is valid. +#define MAX77620_REG_IRQ_LVL2_L8 0x09 // LDO number that irq occurred. Only bit0: LDO8 is valid. #define MAX77620_REG_IRQ_MSK_L8 0x11 #define MAX77620_REG_IRQ_LVL2_GPIO 0x0A // Edge detection interrupt. @@ -139,8 +139,8 @@ #define MAX77620_REG_DVSSD0 0x1B #define MAX77620_REG_DVSSD1 0x1C #define MAX77620_SDX_VOLT_MASK 0xFF -#define MAX77620_SD0_VOLT_MASK 0x3F -#define MAX77620_SD1_VOLT_MASK 0x7F +#define MAX77620_SD0_VOLT_MASK 0x7F // Max is 0x40. +#define MAX77620_SD1_VOLT_MASK 0x7F // Max is 0x4C. #define MAX77620_LDO_VOLT_MASK 0x3F #define MAX77620_REG_SD0_CFG 0x1D @@ -318,7 +318,7 @@ #define MAX77620_REG_CID2 0x5A #define MAX77620_REG_CID3 0x5B #define MAX77620_REG_CID4 0x5C // OTP version. -#define MAX77620_REG_CID5 0x5D +#define MAX77620_REG_CID5 0x5D // ES version. #define MAX77620_CID_DIDO_MASK 0xF #define MAX77620_CID_DIDO_SHIFT 0 #define MAX77620_CID_DIDM_MASK 0xF0 diff --git a/bdk/power/max7762x.c b/bdk/power/max7762x.c index a7d30ce..f0aefb5 100644 --- a/bdk/power/max7762x.c +++ b/bdk/power/max7762x.c @@ -20,8 +20,8 @@ #include #include #include +#include #include -#include #define REGULATOR_SD 0 #define REGULATOR_LDO 1 @@ -75,7 +75,7 @@ typedef struct _max77620_regulator_t static const max77620_regulator_t _pmic_regulators[] = { { "sd0", 12500, 600000, 625000, 1400000, REGULATOR_SD, MAX77620_REG_SD0, MAX77620_REG_SD0_CFG, MAX77620_SD0_VOLT_MASK, {{ MAX77620_REG_FPS_SD0, 1, 7, 1 }} }, - { "sd1", 12500, 600000, 1125000, 1250000, REGULATOR_SD, MAX77620_REG_SD1, MAX77620_REG_SD1_CFG, MAX77620_SD1_VOLT_MASK, {{ MAX77620_REG_FPS_SD1, 0, 1, 5 }} }, + { "sd1", 12500, 600000, 1125000, 1237500, REGULATOR_SD, MAX77620_REG_SD1, MAX77620_REG_SD1_CFG, MAX77620_SD1_VOLT_MASK, {{ MAX77620_REG_FPS_SD1, 0, 1, 5 }} }, { "sd2", 12500, 600000, 1325000, 1350000, REGULATOR_SD, MAX77620_REG_SD2, MAX77620_REG_SD2_CFG, MAX77620_SDX_VOLT_MASK, {{ MAX77620_REG_FPS_SD2, 1, 5, 2 }} }, { "sd3", 12500, 600000, 1800000, 1800000, REGULATOR_SD, MAX77620_REG_SD3, MAX77620_REG_SD3_CFG, MAX77620_SDX_VOLT_MASK, {{ MAX77620_REG_FPS_SD3, 0, 3, 3 }} }, { "ldo0", 25000, 800000, 1200000, 1200000, REGULATOR_LDO, MAX77620_REG_LDO0_CFG, MAX77620_REG_LDO0_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO0, 3, 7, 0 }} }, @@ -88,11 +88,11 @@ static const max77620_regulator_t _pmic_regulators[] = { { "ldo7", 50000, 800000, 1050000, 1050000, REGULATOR_LDO, MAX77620_REG_LDO7_CFG, MAX77620_REG_LDO7_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO7, 1, 4, 3 }} }, { "ldo8", 50000, 800000, 1050000, 2800000, REGULATOR_LDO, MAX77620_REG_LDO8_CFG, MAX77620_REG_LDO8_CFG2, MAX77620_LDO_VOLT_MASK, {{ MAX77620_REG_FPS_LDO8, 3, 7, 0 }} }, - { "max77621_CPU", 6250, 606250, 1000000, 1400000, REGULATOR_BC0, MAX77621_VOUT_REG, MAX77621_VOUT_DVS_REG, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} }, - { "max77621_GPU", 6250, 606250, 1200000, 1400000, REGULATOR_BC0, MAX77621_VOUT_REG, MAX77621_VOUT_DVS_REG, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} }, + { "max77621_CPU", 6250, 606250, 1000000, 1400000, REGULATOR_BC0, MAX77621_REG_VOUT, MAX77621_REG_VOUT_DVS, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} }, + { "max77621_GPU", 6250, 606250, 1200000, 1400000, REGULATOR_BC0, MAX77621_REG_VOUT, MAX77621_REG_VOUT_DVS, MAX77621_DVC_DVS_VOLT_MASK, {{ MAX77621_CPU_CTRL1_POR_DEFAULT, MAX77621_CPU_CTRL1_HOS_DEFAULT, MAX77621_CPU_CTRL2_POR_DEFAULT, MAX77621_CPU_CTRL2_HOS_DEFAULT }} }, { "max77812_CPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M4_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M4_MASK, MAX77812_EN_CTRL_EN_M4_SHIFT, 0, 0 }} }, + { "max77812_RAM", 5000, 250000, 600000, 650000, REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration. //{ "max77812_GPU", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M1_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M1_MASK, MAX77812_EN_CTRL_EN_M1_SHIFT, 0, 0 }} }, - //{ "max77812_RAM", 5000, 250000, 600000, 1525000, REGULATOR_BC1, MAX77812_REG_M3_VOUT, MAX77812_REG_EN_CTRL, MAX77812_BUCK_VOLT_MASK, {{ MAX77812_EN_CTRL_EN_M3_MASK, MAX77812_EN_CTRL_EN_M3_SHIFT, 0, 0 }} } // Only on PHASE211 configuration. }; static u8 _max77812_get_address() @@ -103,7 +103,7 @@ static u8 _max77812_get_address() return max77812_i2c_addr; max77812_i2c_addr = - !(FUSE(FUSE_RESERVED_ODM28_T210B01) & 1) ? MAX77812_PHASE31_CPU_I2C_ADDR : MAX77812_PHASE211_CPU_I2C_ADDR; + !(FUSE(FUSE_RESERVED_ODM28_B01) & 1) ? MAX77812_PHASE31_CPU_I2C_ADDR : MAX77812_PHASE211_CPU_I2C_ADDR; return max77812_i2c_addr; } @@ -121,7 +121,12 @@ static u8 _max7762x_get_i2c_address(u32 id) case REGULATOR_BC0: return (id == REGULATOR_CPU0 ? MAX77621_CPU_I2C_ADDR : MAX77621_GPU_I2C_ADDR); case REGULATOR_BC1: - return _max77812_get_address(); + { + u8 reg_addr = _max77812_get_address(); + if (id == REGULATOR_RAM0 && reg_addr == MAX77812_PHASE31_CPU_I2C_ADDR) + reg_addr = 0; + return reg_addr; + } default: return 0; } @@ -175,20 +180,22 @@ int max77620_regulator_config_fps(u32 id) return 1; } -int max7762x_regulator_set_voltage(u32 id, u32 mv) +int max7762x_regulator_set_voltage(u32 id, u32 uv) { if (id > REGULATOR_MAX) return 0; const max77620_regulator_t *reg = &_pmic_regulators[id]; - if (mv < reg->uv_min || mv > reg->uv_max) + if (uv < reg->uv_min || uv > reg->uv_max) return 0; u8 addr = _max7762x_get_i2c_address(id); + if (!addr) + return 0; // Calculate voltage multiplier. - u32 mult = (mv + reg->uv_step - 1 - reg->uv_min) / reg->uv_step; + u32 mult = (uv + reg->uv_step - 1 - reg->uv_min) / reg->uv_step; u8 val = i2c_recv_byte(I2C_5, addr, reg->volt_addr); val = (val & ~reg->volt_mask) | (mult & reg->volt_mask); @@ -249,6 +256,8 @@ int max7762x_regulator_enable(u32 id, bool enable) } u8 addr = _max7762x_get_i2c_address(id); + if (!addr) + return 0; // Read and enable/disable. u8 val = i2c_recv_byte(I2C_5, addr, reg_addr); @@ -291,6 +300,8 @@ void max77621_config_default(u32 id, bool por) return; u8 addr = _max7762x_get_i2c_address(id); + if (!addr) + return; if (por) { @@ -299,13 +310,13 @@ void max77621_config_default(u32 id, bool por) max7762x_regulator_enable(id, false); // Configure to default. - i2c_send_byte(I2C_5, addr, MAX77621_CONTROL1_REG, reg->ctrl.ctrl1_por); - i2c_send_byte(I2C_5, addr, MAX77621_CONTROL2_REG, reg->ctrl.ctrl2_por); + i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL1, reg->ctrl.ctrl1_por); + i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL2, reg->ctrl.ctrl2_por); } else { - i2c_send_byte(I2C_5, addr, MAX77621_CONTROL1_REG, reg->ctrl.ctrl1_hos); - i2c_send_byte(I2C_5, addr, MAX77621_CONTROL2_REG, reg->ctrl.ctrl2_hos); + i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL1, reg->ctrl.ctrl1_hos); + i2c_send_byte(I2C_5, addr, MAX77621_REG_CONTROL2, reg->ctrl.ctrl2_hos); } } @@ -316,7 +327,7 @@ void max77620_config_default() return; // Set default voltages and enable regulators. - for (u32 i = 1; i <= REGULATOR_LDO8; i++) + for (u32 i = REGULATOR_SD1; i <= REGULATOR_LDO8; i++) { max77620_regulator_config_fps(i); max7762x_regulator_set_voltage(i, _pmic_regulators[i].uv_default); diff --git a/bdk/power/max7762x.h b/bdk/power/max7762x.h index 3478530..342f40b 100644 --- a/bdk/power/max7762x.h +++ b/bdk/power/max7762x.h @@ -20,6 +20,14 @@ #include +/* + * SDx actual min is 625 mV. Multipliers 0/1 reserved. + * SD0 max is 1400 mV + * SD1 max is 1550 mV + * SD2 max is 3787.5 mV + * SD3 max is 3787.5 mV + */ + /* * Switch Power domains (max77620): * Name | Usage | uV step | uV min | uV default | uV max | Init @@ -39,6 +47,27 @@ * ldo8 | XUSB, DP, MCU | 50000 | 800000 | 1050000 | 2800000 | 1.05V/2.8V (pcv) */ + +// GPIOs T210: 3: 3.3V, 5: CPU PMIC, 6: GPU PMIC, 7: DSI/VI 1.2V powered by ldo0. + +/* + * OTP: T210 - T210B01: + * SD0: 1.0V 1.05V - SoC. EN Based on FPSSRC. + * SD1: 1.15V 1.1V - DRAM for T210. EN Based on FPSSRC. + * SD2: 1.35V 1.35V + * SD3: 1.8V 1.8V + * All powered off? + * LDO0: -- -- - Display + * LDO1: 1.05V 1.05V + * LDO2: -- -- - SD + * LDO3: 3.1V 3.1V - GC ASIC + * LDO4: 1.0V 0.8V - Needed for RTC domain on T210. + * LDO5: 3.1V 3.1V + * LDO6: 2.8V 2.9V - Touch. + * LDO7: 1.05V 1.0V + * LDO8: 1.05V 1.0V + */ + /* * MAX77620_AME_GPIO: control GPIO modes (bits 0 - 7 correspond to GPIO0 - GPIO7); 0 -> GPIO, 1 -> alt-mode * MAX77620_REG_GPIOx: 0x9 sets output and enable @@ -58,22 +87,22 @@ #define REGULATOR_LDO6 10 #define REGULATOR_LDO7 11 #define REGULATOR_LDO8 12 -#define REGULATOR_CPU0 13 -#define REGULATOR_GPU0 14 -#define REGULATOR_CPU1 15 -//#define REGULATOR_GPU1 16 -//#define REGULATOR_GPU1 17 -#define REGULATOR_MAX 15 +#define REGULATOR_CPU0 13 // T210 CPU. +#define REGULATOR_GPU0 14 // T210 CPU. +#define REGULATOR_CPU1 15 // T210B01 CPU. +#define REGULATOR_RAM0 16 // T210B01 RAM for PHASE211. +//#define REGULATOR_GPU1 17 // T210B01 CPU. +#define REGULATOR_MAX REGULATOR_RAM0 #define MAX77621_CPU_I2C_ADDR 0x1B #define MAX77621_GPU_I2C_ADDR 0x1C -#define MAX77621_VOUT_REG 0x00 -#define MAX77621_VOUT_DVS_REG 0x01 -#define MAX77621_CONTROL1_REG 0x02 -#define MAX77621_CONTROL2_REG 0x03 -#define MAX77621_CHIPID1_REG 0x04 -#define MAX77621_CHIPID2_REG 0x05 +#define MAX77621_REG_VOUT 0x00 +#define MAX77621_REG_VOUT_DVS 0x01 +#define MAX77621_REG_CONTROL1 0x02 +#define MAX77621_REG_CONTROL2 0x03 +#define MAX77621_REG_CHIPID1 0x04 +#define MAX77621_REG_CHIPID2 0x05 /* MAX77621_VOUT_DVC_DVS */ #define MAX77621_DVC_DVS_VOLT_MASK 0x7F @@ -106,11 +135,10 @@ #define MAX77621_INDUCTOR_PLUS_60_PER 3 #define MAX77621_INDUCTOR_MASK 3 -#define MAX77621_CKKADV_TRIP_75mV_PER_US 0x0 -#define MAX77621_CKKADV_TRIP_150mV_PER_US BIT(2) -#define MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS BIT(3) -#define MAX77621_CKKADV_TRIP_DISABLE (BIT(2) | BIT(3)) -#define MAX77621_CKKADV_TRIP_MASK (BIT(2) | BIT(3)) +#define MAX77621_CKKADV_TRIP_75mV_PER_US (0 << 2) +#define MAX77621_CKKADV_TRIP_150mV_PER_US (1u << 2) +#define MAX77621_CKKADV_TRIP_DISABLE (3u << 2) +#define MAX77621_CKKADV_TRIP_MASK (3u << 2) #define MAX77621_FT_ENABLE BIT(4) #define MAX77621_DISCH_ENABLE BIT(5) @@ -118,18 +146,17 @@ #define MAX77621_T_JUNCTION_120 BIT(7) #define MAX77621_CPU_CTRL1_POR_DEFAULT (MAX77621_RAMP_50mV_PER_US) -#define MAX77621_CPU_CTRL1_HOS_DEFAULT (MAX77621_AD_ENABLE | \ - MAX77621_NFSR_ENABLE | \ - MAX77621_SNS_ENABLE | \ +#define MAX77621_CPU_CTRL1_HOS_DEFAULT (MAX77621_AD_ENABLE | \ + MAX77621_NFSR_ENABLE | \ + MAX77621_SNS_ENABLE | \ MAX77621_RAMP_12mV_PER_US) -#define MAX77621_CPU_CTRL2_POR_DEFAULT (MAX77621_T_JUNCTION_120 | \ - MAX77621_FT_ENABLE | \ - MAX77621_CKKADV_TRIP_75mV_PER_US_HIST_DIS | \ - MAX77621_CKKADV_TRIP_150mV_PER_US | \ +#define MAX77621_CPU_CTRL2_POR_DEFAULT (MAX77621_T_JUNCTION_120 | \ + MAX77621_FT_ENABLE | \ + MAX77621_CKKADV_TRIP_DISABLE | \ MAX77621_INDUCTOR_NOMINAL) -#define MAX77621_CPU_CTRL2_HOS_DEFAULT (MAX77621_T_JUNCTION_120 | \ - MAX77621_WDTMR_ENABLE | \ - MAX77621_CKKADV_TRIP_75mV_PER_US | \ +#define MAX77621_CPU_CTRL2_HOS_DEFAULT (MAX77621_T_JUNCTION_120 | \ + MAX77621_WDTMR_ENABLE | \ + MAX77621_CKKADV_TRIP_75mV_PER_US | \ MAX77621_INDUCTOR_NOMINAL) #define MAX77621_CTRL_HOS_CFG 0 @@ -137,7 +164,7 @@ int max77620_regulator_get_status(u32 id); int max77620_regulator_config_fps(u32 id); -int max7762x_regulator_set_voltage(u32 id, u32 mv); +int max7762x_regulator_set_voltage(u32 id, u32 uv); int max7762x_regulator_enable(u32 id, bool enable); void max77620_config_gpio(u32 id, bool enable); void max77620_config_default(); diff --git a/bdk/power/max77812.h b/bdk/power/max77812.h index 89c3baf..b58e3ae 100644 --- a/bdk/power/max77812.h +++ b/bdk/power/max77812.h @@ -17,8 +17,8 @@ #ifndef _MAX77812_H_ #define _MAX77812_H_ -#define MAX77812_PHASE31_CPU_I2C_ADDR 0x31 // 2 Outputs: 3-phase M1 + 1-phase M4. -#define MAX77812_PHASE211_CPU_I2C_ADDR 0x33 // 3 Outputs: 2-phase M1 + 1-phase M3 + 1-phase M4. +#define MAX77812_PHASE31_CPU_I2C_ADDR 0x31 // High power GPU. 2 Outputs: 3-phase M1 + 1-phase M4. +#define MAX77812_PHASE211_CPU_I2C_ADDR 0x33 // Low power GPU. 3 Outputs: 2-phase M1 + 1-phase M3 + 1-phase M4. #define MAX77812_REG_RSET 0x00 #define MAX77812_REG_INT_SRC 0x01 @@ -66,22 +66,23 @@ #define MAX77812_REG_M2_VOUT_S 0x2C #define MAX77812_REG_M3_VOUT_S 0x2D #define MAX77812_REG_M4_VOUT_S 0x2E -#define MAX77812_REG_M1_CFG 0x2F -#define MAX77812_REG_M2_CFG 0x30 -#define MAX77812_REG_M3_CFG 0x31 -#define MAX77812_REG_M4_CFG 0x32 -#define MAX77812_REG_GLB_CFG1 0x33 -#define MAX77812_REG_GLB_CFG2 0x34 +#define MAX77812_REG_M1_CFG 0x2F // HOS: M1_ILIM - 7.2A/4.8A. +#define MAX77812_REG_M2_CFG 0x30 // HOS: M2_ILIM - 7.2A/4.8A. +#define MAX77812_REG_M3_CFG 0x31 // HOS: M3_ILIM - 7.2A/4.8A. +#define MAX77812_REG_M4_CFG 0x32 // HOS: M4_ILIM - 7.2A/4.8A. +#define MAX77812_REG_GLB_CFG1 0x33 // HOS: B_SD_SR/B_SS_SR - 5mV/us. +#define MAX77812_REG_GLB_CFG2 0x34 // HOS: B_RD_SR/B_RU_SR - 5mV/us #define MAX77812_REG_GLB_CFG3 0x35 -/*! Protected area and settings only for MAX77812_REG_VERSION 4 */ -#define MAX77812_REG_GLB_CFG4 0x36 -#define MAX77812_REG_GLB_CFG5 0x37 -#define MAX77812_REG_GLB_CFG6 0x38 -#define MAX77812_REG_GLB_CFG7 0x39 -#define MAX77812_REG_GLB_CFG8 0x3A -#define MAX77812_REG_PROT_ACCESS 0xFD -#define MAX77812_REG_MAX 0xFE +/*! Protected area and settings only for MAX77812_ES2_VERSION */ +#define MAX77812_REG_GLB_CFG4 0x36 // QS: 0xBB. +#define MAX77812_REG_GLB_CFG5 0x37 // QS: 0x39. ES2: Set to 0x3E. +#define MAX77812_REG_GLB_CFG6 0x38 // QS: 0x88. ES2: Set to 0x90. +#define MAX77812_REG_GLB_CFG7 0x39 // QS: 0x04. +#define MAX77812_REG_GLB_CFG8 0x3A // QS: 0x3A. ES2: Set to 0x3A. + +#define MAX77812_REG_PROT_ACCESS 0xFD // 0x00: Lock, 0x5A: Unlock. +#define MAX77812_REG_UNKNOWN 0xFE #define MAX77812_REG_EN_CTRL_MASK(n) BIT(n) #define MAX77812_START_SLEW_RATE_MASK 0x07 diff --git a/bdk/power/regulator_5v.c b/bdk/power/regulator_5v.c index 7b8924b..55f81f7 100644 --- a/bdk/power/regulator_5v.c +++ b/bdk/power/regulator_5v.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 CTCaer + * Copyright (c) 2019-2023 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,7 +14,9 @@ * along with this program. If not, see . */ +#include #include +#include #include #include #include @@ -25,51 +27,55 @@ static bool usb_src = false; void regulator_5v_enable(u8 dev) { + bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210; + // The power supply selection from battery or USB is automatic. if (!reg_5v_dev) { - // Fan and Rail power from battery 5V regulator. + // Fan and Rail power from battery 5V regulator EN. PINMUX_AUX(PINMUX_AUX_SATA_LED_ACTIVE) = 1; - gpio_config(GPIO_PORT_A, GPIO_PIN_5, GPIO_MODE_GPIO); - gpio_output_enable(GPIO_PORT_A, GPIO_PIN_5, GPIO_OUTPUT_ENABLE); - gpio_write(GPIO_PORT_A, GPIO_PIN_5, GPIO_HIGH); + gpio_direction_output(GPIO_PORT_A, GPIO_PIN_5, GPIO_HIGH); + + // Only Icosa has USB 5V VBUS rails. + if (tegra_t210) + { + // Fan and Rail power from USB 5V VBUS EN. + PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN0) = PINMUX_LPDR | 1; + gpio_direction_output(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW); + } + + // Make sure GPIO IO power is enabled. + PMC(APBDEV_PMC_NO_IOPOWER) &= ~PMC_NO_IOPOWER_GPIO; + (void)PMC(APBDEV_PMC_NO_IOPOWER); // Commit write. + + // Inform GPIO IO pads that we switched to 1.8V. + PMC(APBDEV_PMC_PWR_DET_VAL) &= ~PMC_PWR_DET_33V_GPIO; + (void)PMC(APBDEV_PMC_PWR_DET_VAL); // Commit write. - // Fan and Rail power from USB 5V VBUS. - PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN0) = PINMUX_LPDR | 1; - gpio_config(GPIO_PORT_CC, GPIO_PIN_4, GPIO_MODE_GPIO); - gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_4, GPIO_OUTPUT_ENABLE); - gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW); usb_src = false; - - // Make sure GPIO power is enabled. - PMC(APBDEV_PMC_NO_IOPOWER) &= ~PMC_NO_IOPOWER_GPIO_IO_EN; - // Override power detect for GPIO AO IO rails. - PMC(APBDEV_PMC_PWR_DET_VAL) &= ~PMC_PWR_DET_GPIO_IO_EN; } reg_5v_dev |= dev; } void regulator_5v_disable(u8 dev) { + bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210; + reg_5v_dev &= ~dev; if (!reg_5v_dev) { // Rail power from battery 5V regulator. gpio_write(GPIO_PORT_A, GPIO_PIN_5, GPIO_LOW); - gpio_output_enable(GPIO_PORT_A, GPIO_PIN_5, GPIO_OUTPUT_DISABLE); - gpio_config(GPIO_PORT_A, GPIO_PIN_5, GPIO_MODE_SPIO); - PINMUX_AUX(PINMUX_AUX_SATA_LED_ACTIVE) = PINMUX_PARKED | PINMUX_INPUT_ENABLE; - // Rail power from USB 5V VBUS. - gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW); - gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_4, GPIO_OUTPUT_DISABLE); - gpio_config(GPIO_PORT_CC, GPIO_PIN_4, GPIO_MODE_SPIO); - PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN0) = PINMUX_IO_HV | PINMUX_LPDR | PINMUX_PARKED | PINMUX_INPUT_ENABLE; - usb_src = false; + // Only Icosa has USB 5V VBUS rails. + if (tegra_t210) + { + // Rail power from USB 5V VBUS. + gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_LOW); + usb_src = false; - // GPIO AO IO rails. - PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_GPIO_IO_EN; + } } } @@ -80,6 +86,10 @@ bool regulator_5v_get_dev_enabled(u8 dev) void regulator_5v_usb_src_enable(bool enable) { + // Only for Icosa. + if (hw_get_chip_id() != GP_HIDREV_MAJOR_T210) + return; + if (enable && !usb_src) { gpio_write(GPIO_PORT_CC, GPIO_PIN_4, GPIO_HIGH); diff --git a/bdk/rtc/max77620-rtc.c b/bdk/rtc/max77620-rtc.c index 164df75..6f813c0 100644 --- a/bdk/rtc/max77620-rtc.c +++ b/bdk/rtc/max77620-rtc.c @@ -1,7 +1,7 @@ /* * PMIC Real Time Clock driver for Nintendo Switch's MAX77620-RTC * - * Copyright (c) 2018-2019 CTCaer + * Copyright (c) 2018-2022 CTCaer * Copyright (c) 2019 shchmue * * This program is free software; you can redistribute it and/or modify it @@ -19,7 +19,16 @@ #include #include -#include +#include +#include +#include + +int epoch_offset = 0; + +void max77620_rtc_prep_read() +{ + i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_READ_UPDATE); +} void max77620_rtc_get_time(rtc_time_t *time) { @@ -35,7 +44,7 @@ void max77620_rtc_get_time(rtc_time_t *time) // Get time. time->sec = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_SEC_REG) & 0x7F; time->min = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_MIN_REG) & 0x7F; - u8 hour = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_HOUR_REG); + u8 hour = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_HOUR_REG); time->hour = hour & 0x1F; if (!(val & MAX77620_RTC_24H) && (hour & MAX77620_RTC_HOUR_PM_MASK)) @@ -53,7 +62,7 @@ void max77620_rtc_get_time(rtc_time_t *time) } // Get date. - time->day = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_DATE_REG) & 0x1f; + time->day = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_DATE_REG) & 0x1f; time->month = (i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_MONTH_REG) & 0xF) - 1; time->year = (i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_YEAR_REG) & 0x7F) + 2000; } @@ -64,6 +73,7 @@ void max77620_rtc_stop_alarm() // Update RTC regs from RTC clock. i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_READ_UPDATE); + msleep(16); // Stop alarm for both ALARM1 and ALARM2. Horizon uses ALARM2. for (int i = 0; i < (MAX77620_RTC_NR_TIME_REGS * 2); i++) @@ -82,9 +92,9 @@ void max77620_rtc_epoch_to_date(u32 epoch, rtc_time_t *time) u32 tmp, edays, year, month, day; // Set time. - time->sec = epoch % 60; + time->sec = epoch % 60; epoch /= 60; - time->min = epoch % 60; + time->min = epoch % 60; epoch /= 60; time->hour = epoch % 24; epoch /= 24; @@ -99,14 +109,14 @@ void max77620_rtc_epoch_to_date(u32 epoch, rtc_time_t *time) day = edays - month * 30 - month * 601 / 1000; // Month/Year offset. - if(month < 14) + if (month < 14) { year -= 4716; month--; } else { - year -= 4715; + year -= 4715; month -= 13; } @@ -129,13 +139,13 @@ u32 max77620_rtc_date_to_epoch(const rtc_time_t *time) month = time->month; // Month/Year offset. - if(month < 3) + if (month < 3) { month += 12; year--; } - epoch = (365 * year) + (year >> 2) - (year / 100) + (year / 400); // Years to days. + epoch = (365 * year) + (year >> 2) - (year / 100) + (year / 400); // Years to days. epoch += (30 * month) + (3 * (month + 1) / 5) + time->day; // Months to days. epoch -= 719561; // Epoch time is 1/1/1970. @@ -145,3 +155,60 @@ u32 max77620_rtc_date_to_epoch(const rtc_time_t *time) return epoch; } + +void max77620_rtc_get_time_adjusted(rtc_time_t *time) +{ + max77620_rtc_get_time(time); + if (epoch_offset) + { + u32 epoch = (u32)((s64)max77620_rtc_date_to_epoch(time) + epoch_offset); + max77620_rtc_epoch_to_date(epoch, time); + } +} + +void max77620_rtc_set_epoch_offset(int offset) +{ + epoch_offset = offset; +} + +void max77620_rtc_set_reboot_reason(rtc_reboot_reason_t *rr) +{ + max77620_rtc_stop_alarm(); + + // Set reboot reason. + i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_YEAR_REG, rr->enc.val1); + i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM2_YEAR_REG, rr->enc.val2); + + // Set reboot reason magic. + i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_WEEKDAY_REG, RTC_REBOOT_REASON_MAGIC); + i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM2_WEEKDAY_REG, RTC_REBOOT_REASON_MAGIC); + + // Update RTC clock from RTC regs. + i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_WRITE_UPDATE); + msleep(16); +} + +bool max77620_rtc_get_reboot_reason(rtc_reboot_reason_t *rr) +{ + u8 magic[2]; + + // Get reboot reason magic. + magic[0] = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_WEEKDAY_REG); + magic[1] = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM2_WEEKDAY_REG); + + // Magic must be correct and match on both registers. + if (magic[0] != RTC_REBOOT_REASON_MAGIC || magic[0] != magic[1]) + return false; + + // Reboot reason setter is expected to have updated the actual regs already. + rr->enc.val1 = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_YEAR_REG); + rr->enc.val2 = i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM2_YEAR_REG); + + // Clear magic and update actual regs. + i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM1_WEEKDAY_REG, 0); + i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_ALARM2_WEEKDAY_REG, 0); + i2c_send_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_UPDATE0_REG, MAX77620_RTC_WRITE_UPDATE); + + // Return reboot reason. False if [config] was selected. + return true; +} diff --git a/bdk/rtc/max77620-rtc.h b/bdk/rtc/max77620-rtc.h index 93b24c4..b82c3e6 100644 --- a/bdk/rtc/max77620-rtc.h +++ b/bdk/rtc/max77620-rtc.h @@ -1,7 +1,7 @@ /* * PMIC Real Time Clock driver for Nintendo Switch's MAX77620-RTC * - * Copyright (c) 2018 CTCaer + * Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -25,6 +25,8 @@ #define MAX77620_RTC_NR_TIME_REGS 7 +#define MAX77620_RTC_RTCINT_REG 0x00 +#define MAX77620_RTC_RTCINTM_REG 0x01 #define MAX77620_RTC_CONTROLM_REG 0x02 #define MAX77620_RTC_CONTROL_REG 0x03 #define MAX77620_RTC_BIN_FORMAT BIT(0) @@ -34,6 +36,9 @@ #define MAX77620_RTC_WRITE_UPDATE BIT(0) #define MAX77620_RTC_READ_UPDATE BIT(4) +#define MAX77620_RTC_UPDATE1_REG 0x05 +#define MAX77620_RTC_RTCSMPL_REG 0x06 + #define MAX77620_RTC_SEC_REG 0x07 #define MAX77620_RTC_MIN_REG 0x08 #define MAX77620_RTC_HOUR_REG 0x09 @@ -69,9 +74,47 @@ typedef struct _rtc_time_t { u16 year; } rtc_time_t; +#define RTC_REBOOT_REASON_MAGIC 0x77 // 7-bit reg. + +enum { + REBOOT_REASON_NOP = 0, // Use [config]. + REBOOT_REASON_SELF = 1, // Use autoboot_idx/autoboot_list. + REBOOT_REASON_MENU = 2, // Force menu. + REBOOT_REASON_UMS = 3, // Force selected UMS partition. + REBOOT_REASON_REC = 4, // Set PMC_SCRATCH0_MODE_RECOVERY and reboot to self. + REBOOT_REASON_PANIC = 5 // Inform bootloader that panic occured if T210B01. +}; + +typedef struct _rtc_rr_decoded_t +{ + u16 reason:4; + u16 autoboot_idx:4; + u16 autoboot_list:1; + u16 ums_idx:3; +} rtc_rr_decoded_t; + +typedef struct _rtc_rr_encoded_t +{ + u16 val1:6; // 6-bit reg. + u16 val2:6; // 6-bit reg. +} rtc_rr_encoded_t; + +typedef struct _rtc_reboot_reason_t +{ + union { + rtc_rr_decoded_t dec; + rtc_rr_encoded_t enc; + }; +} rtc_reboot_reason_t; + +void max77620_rtc_prep_read(); void max77620_rtc_get_time(rtc_time_t *time); +void max77620_rtc_get_time_adjusted(rtc_time_t *time); +void max77620_rtc_set_epoch_offset(int offset); void max77620_rtc_stop_alarm(); void max77620_rtc_epoch_to_date(u32 epoch, rtc_time_t *time); -u32 max77620_rtc_date_to_epoch(const rtc_time_t *time); +u32 max77620_rtc_date_to_epoch(const rtc_time_t *time); +void max77620_rtc_set_reboot_reason(rtc_reboot_reason_t *rr); +bool max77620_rtc_get_reboot_reason(rtc_reboot_reason_t *rr); #endif /* _MFD_MAX77620_RTC_H_ */ diff --git a/bdk/sec/se.c b/bdk/sec/se.c index fa20b0a..4ed04ec 100644 --- a/bdk/sec/se.c +++ b/bdk/sec/se.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2025 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,12 +18,12 @@ #include #include "se.h" -#include "se_t210.h" -#include +#include #include +#include #include +#include #include -#include typedef struct _se_ll_t { @@ -32,6 +32,9 @@ typedef struct _se_ll_t vu32 size; } se_ll_t; +se_ll_t ll_src, ll_dst; +se_ll_t *ll_src_ptr, *ll_dst_ptr; // Must be u32 aligned. + static void _gf256_mul_x(void *block) { u8 *pdata = (u8 *)block; @@ -48,14 +51,30 @@ static void _gf256_mul_x(void *block) pdata[0xF] ^= 0x87; } +static void _gf256_mul_x_le(void *block) +{ + u32 *pdata = (u32 *)block; + u32 carry = 0; + + for (u32 i = 0; i < 4; i++) + { + u32 b = pdata[i]; + pdata[i] = (b << 1) | carry; + carry = b >> 31; + } + + if (carry) + pdata[0x0] ^= 0x87; +} + static void _se_ll_init(se_ll_t *ll, u32 addr, u32 size) { - ll->num = 0; + ll->num = 0; ll->addr = addr; ll->size = size; } -static void _se_ll_set(se_ll_t *dst, se_ll_t *src) +static void _se_ll_set(se_ll_t *src, se_ll_t *dst) { SE(SE_IN_LL_ADDR_REG) = (u32)src; SE(SE_OUT_LL_ADDR_REG) = (u32)dst; @@ -63,54 +82,44 @@ static void _se_ll_set(se_ll_t *dst, se_ll_t *src) static int _se_wait() { + bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210; + + // Wait for operation to be done. while (!(SE(SE_INT_STATUS_REG) & SE_INT_OP_DONE)) ; - if (SE(SE_INT_STATUS_REG) & SE_INT_ERR_STAT || - (SE(SE_STATUS_REG) & SE_STATUS_STATE_MASK) != SE_STATUS_STATE_IDLE || - SE(SE_ERR_STATUS_REG) != 0) + + // Check for errors. + if ((SE(SE_INT_STATUS_REG) & SE_INT_ERR_STAT) || + (SE(SE_STATUS_REG) & SE_STATUS_STATE_MASK) != SE_STATUS_STATE_IDLE || + (SE(SE_ERR_STATUS_REG) != 0) + ) + { return 0; - return 1; -} - -se_ll_t *ll_dst, *ll_src; -static int _se_execute(u32 op, void *dst, u32 dst_size, const void *src, u32 src_size, bool is_oneshot) -{ - ll_dst = NULL; - ll_src = NULL; - - if (dst) - { - ll_dst = (se_ll_t *)malloc(sizeof(se_ll_t)); - _se_ll_init(ll_dst, (u32)dst, dst_size); } - if (src) + // T210B01: IRAM/TZRAM/DRAM AHB coherency WAR. + if (!tegra_t210 && ll_dst_ptr) { - ll_src = (se_ll_t *)malloc(sizeof(se_ll_t)); - _se_ll_init(ll_src, (u32)src, src_size); - } + u32 timeout = get_tmr_us() + 1000000; + // Ensure data is out from SE. + while (SE(SE_STATUS_REG) & SE_STATUS_MEM_IF_BUSY) + { + if (get_tmr_us() > timeout) + return 0; + usleep(1); + } - _se_ll_set(ll_dst, ll_src); - - SE(SE_ERR_STATUS_REG) = SE(SE_ERR_STATUS_REG); - SE(SE_INT_STATUS_REG) = SE(SE_INT_STATUS_REG); - - bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false); - - SE(SE_OPERATION_REG) = op; - - if (is_oneshot) - { - int res = _se_wait(); - - bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false); - - if (src) - free(ll_src); - if (dst) - free(ll_dst); - - return res; + // Ensure data is out from AHB. + if (ll_dst_ptr->addr >= DRAM_START) + { + timeout = get_tmr_us() + 200000; + while (AHB_GIZMO(AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID) & MEM_WRQUE_SE_MST_ID) + { + if (get_tmr_us() > timeout) + return 0; + usleep(1); + } + } } return 1; @@ -120,22 +129,48 @@ static int _se_execute_finalize() { int res = _se_wait(); - bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false); + // Invalidate data after OP is done. + bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, false); - if (ll_src) - { - free(ll_src); - ll_src = NULL; - } - if (ll_dst) - { - free(ll_dst); - ll_dst = NULL; - } + ll_src_ptr = NULL; + ll_dst_ptr = NULL; return res; } +static int _se_execute(u32 op, void *dst, u32 dst_size, const void *src, u32 src_size, bool is_oneshot) +{ + ll_src_ptr = NULL; + ll_dst_ptr = NULL; + + if (src) + { + ll_src_ptr = &ll_src; + _se_ll_init(ll_src_ptr, (u32)src, src_size); + } + + if (dst) + { + ll_dst_ptr = &ll_dst; + _se_ll_init(ll_dst_ptr, (u32)dst, dst_size); + } + + _se_ll_set(ll_src_ptr, ll_dst_ptr); + + SE(SE_ERR_STATUS_REG) = SE(SE_ERR_STATUS_REG); + SE(SE_INT_STATUS_REG) = SE(SE_INT_STATUS_REG); + + // Flush data before starting OP. + bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLEAN_WAY, false); + + SE(SE_OPERATION_REG) = op; + + if (is_oneshot) + return _se_execute_finalize(); + + return 1; +} + static int _se_execute_oneshot(u32 op, void *dst, u32 dst_size, const void *src, u32 src_size) { return _se_execute(op, dst, dst_size, src, src_size, true); @@ -146,8 +181,7 @@ static int _se_execute_one_block(u32 op, void *dst, u32 dst_size, const void *sr if (!src || !dst) return 0; - u8 *block = (u8 *)malloc(SE_AES_BLOCK_SIZE); - memset(block, 0, SE_AES_BLOCK_SIZE); + u32 block[SE_AES_BLOCK_SIZE / sizeof(u32)] = {0}; SE(SE_CRYPTO_BLOCK_COUNT_REG) = 1 - 1; @@ -155,11 +189,10 @@ static int _se_execute_one_block(u32 op, void *dst, u32 dst_size, const void *sr int res = _se_execute_oneshot(op, block, SE_AES_BLOCK_SIZE, block, SE_AES_BLOCK_SIZE); memcpy(dst, block, dst_size); - free(block); return res; } -static void _se_aes_ctr_set(void *ctr) +static void _se_aes_ctr_set(const void *ctr) { u32 data[SE_AES_IV_SIZE / 4]; memcpy(data, ctr, SE_AES_IV_SIZE); @@ -172,7 +205,7 @@ void se_rsa_acc_ctrl(u32 rs, u32 flags) { if (flags & SE_RSA_KEY_TBL_DIS_KEY_ACCESS_FLAG) SE(SE_RSA_KEYTABLE_ACCESS_REG + 4 * rs) = - (((flags >> 4) & SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG) |(flags & SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_FLAG)) ^ + (((flags >> 4) & SE_RSA_KEY_TBL_DIS_KEYUSE_FLAG) | (flags & SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_FLAG)) ^ SE_RSA_KEY_TBL_DIS_KEY_READ_UPDATE_USE_FLAG; if (flags & SE_RSA_KEY_LOCK_FLAG) SE(SE_RSA_SECURITY_PERKEY_REG) &= ~BIT(rs); @@ -191,7 +224,7 @@ u32 se_key_acc_ctrl_get(u32 ks) return SE(SE_CRYPTO_KEYTABLE_ACCESS_REG + 4 * ks); } -void se_aes_key_set(u32 ks, void *key, u32 size) +void se_aes_key_set(u32 ks, const void *key, u32 size) { u32 data[SE_AES_MAX_KEY_SIZE / 4]; memcpy(data, key, size); @@ -203,7 +236,7 @@ void se_aes_key_set(u32 ks, void *key, u32 size) } } -void se_aes_iv_set(u32 ks, void *iv) +void se_aes_iv_set(u32 ks, const void *iv) { u32 data[SE_AES_IV_SIZE / 4]; memcpy(data, iv, SE_AES_IV_SIZE); @@ -246,17 +279,45 @@ void se_aes_iv_clear(u32 ks) } } +void se_aes_iv_updated_clear(u32 ks) +{ + for (u32 i = 0; i < (SE_AES_IV_SIZE / 4); i++) + { + SE(SE_CRYPTO_KEYTABLE_ADDR_REG) = SE_KEYTABLE_SLOT(ks) | SE_KEYTABLE_QUAD(UPDATED_IV) | SE_KEYTABLE_PKT(i); + SE(SE_CRYPTO_KEYTABLE_DATA_REG) = 0; + } +} int se_aes_unwrap_key(u32 ks_dst, u32 ks_src, const void *input) { - SE(SE_CONFIG_REG) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_KEYTABLE); - SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks_src) | SE_CRYPTO_CORE_SEL(CORE_DECRYPT); + SE(SE_CONFIG_REG) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_KEYTABLE); + SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks_src) | SE_CRYPTO_CORE_SEL(CORE_DECRYPT); SE(SE_CRYPTO_BLOCK_COUNT_REG) = 1 - 1; SE(SE_CRYPTO_KEYTABLE_DST_REG) = SE_KEYTABLE_DST_KEY_INDEX(ks_dst) | SE_KEYTABLE_DST_WORD_QUAD(KEYS_0_3); return _se_execute_oneshot(SE_OP_START, NULL, 0, input, SE_KEY_128_SIZE); } +int se_aes_crypt_hash(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size) +{ + if (enc) + { + SE(SE_CONFIG_REG) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY); + SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_AESOUT) | + SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_XOR_POS(XOR_TOP) | + SE_CRYPTO_HASH(HASH_ENABLE); + } + else + { + SE(SE_CONFIG_REG) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_MEMORY); + SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_PREVMEM) | + SE_CRYPTO_CORE_SEL(CORE_DECRYPT) | SE_CRYPTO_XOR_POS(XOR_BOTTOM) | + SE_CRYPTO_HASH(HASH_ENABLE); + } + SE(SE_CRYPTO_BLOCK_COUNT_REG) = (src_size >> 4) - 1; + return _se_execute_oneshot(SE_OP_START, dst, dst_size, src, src_size); +} + int se_aes_crypt_ecb(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size) { if (enc) @@ -278,14 +339,14 @@ int se_aes_crypt_cbc(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, if (enc) { SE(SE_CONFIG_REG) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY); - SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_AESOUT) | - SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_XOR_POS(XOR_TOP); + SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_AESOUT) | + SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_XOR_POS(XOR_TOP); } else { SE(SE_CONFIG_REG) = SE_CONFIG_DEC_ALG(ALG_AES_DEC) | SE_CONFIG_DST(DST_MEMORY); - SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_PREVMEM) | - SE_CRYPTO_CORE_SEL(CORE_DECRYPT) | SE_CRYPTO_XOR_POS(XOR_BOTTOM); + SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_PREVMEM) | + SE_CRYPTO_CORE_SEL(CORE_DECRYPT) | SE_CRYPTO_XOR_POS(XOR_BOTTOM); } SE(SE_CRYPTO_BLOCK_COUNT_REG) = (src_size >> 4) - 1; return _se_execute_oneshot(SE_OP_START, dst, dst_size, src, src_size); @@ -300,8 +361,9 @@ int se_aes_crypt_ctr(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_s { SE(SE_SPARE_REG) = SE_ECO(SE_ERRATA_FIX_ENABLE); SE(SE_CONFIG_REG) = SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_MEMORY); - SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | - SE_CRYPTO_XOR_POS(XOR_BOTTOM) | SE_CRYPTO_INPUT_SEL(INPUT_LNR_CTR) | SE_CRYPTO_CTR_CNTN(1); + SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | + SE_CRYPTO_XOR_POS(XOR_BOTTOM) | SE_CRYPTO_INPUT_SEL(INPUT_LNR_CTR) | + SE_CRYPTO_CTR_CNTN(1); _se_aes_ctr_set(ctr); u32 src_size_aligned = src_size & 0xFFFFFFF0; @@ -322,10 +384,11 @@ int se_aes_crypt_ctr(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_s return 1; } -int se_aes_xts_crypt_sec(u32 ks1, u32 ks2, u32 enc, u64 sec, void *dst, void *src, u32 secsize) +int se_aes_xts_crypt_sec(u32 tweak_ks, u32 crypt_ks, u32 enc, u64 sec, void *dst, void *src, u32 secsize) { int res = 0; - u8 *tweak = (u8 *)malloc(SE_AES_BLOCK_SIZE); + u32 tmp[SE_AES_BLOCK_SIZE / sizeof(u32)]; + u8 *tweak = (u8 *)tmp; u8 *pdst = (u8 *)dst; u8 *psrc = (u8 *)src; @@ -335,7 +398,7 @@ int se_aes_xts_crypt_sec(u32 ks1, u32 ks2, u32 enc, u64 sec, void *dst, void *sr tweak[i] = sec & 0xFF; sec >>= 8; } - if (!se_aes_crypt_block_ecb(ks1, ENCRYPT, tweak, tweak)) + if (!se_aes_crypt_block_ecb(tweak_ks, ENCRYPT, tweak, tweak)) goto out; // We are assuming a 0x10-aligned sector size in this implementation. @@ -343,7 +406,7 @@ int se_aes_xts_crypt_sec(u32 ks1, u32 ks2, u32 enc, u64 sec, void *dst, void *sr { for (u32 j = 0; j < SE_AES_BLOCK_SIZE; j++) pdst[j] = psrc[j] ^ tweak[j]; - if (!se_aes_crypt_block_ecb(ks2, enc, pdst, pdst)) + if (!se_aes_crypt_block_ecb(crypt_ks, enc, pdst, pdst)) goto out; for (u32 j = 0; j < SE_AES_BLOCK_SIZE; j++) pdst[j] = pdst[j] ^ tweak[j]; @@ -354,23 +417,91 @@ int se_aes_xts_crypt_sec(u32 ks1, u32 ks2, u32 enc, u64 sec, void *dst, void *sr res = 1; -out:; - free(tweak); +out: return res; } -int se_aes_xts_crypt(u32 ks1, u32 ks2, u32 enc, u64 sec, void *dst, void *src, u32 secsize, u32 num_secs) +int se_aes_xts_crypt_sec_nx(u32 tweak_ks, u32 crypt_ks, u32 enc, u64 sec, u8 *tweak, bool regen_tweak, u32 tweak_exp, void *dst, void *src, u32 sec_size) +{ + u32 *pdst = (u32 *)dst; + u32 *psrc = (u32 *)src; + u32 *ptweak = (u32 *)tweak; + + if (regen_tweak) + { + for (int i = 0xF; i >= 0; i--) + { + tweak[i] = sec & 0xFF; + sec >>= 8; + } + if (!se_aes_crypt_block_ecb(tweak_ks, ENCRYPT, tweak, tweak)) + return 0; + } + + // tweak_exp allows using a saved tweak to reduce _gf256_mul_x_le calls. + for (u32 i = 0; i < (tweak_exp << 5); i++) + _gf256_mul_x_le(tweak); + + u8 orig_tweak[SE_KEY_128_SIZE] __attribute__((aligned(4))); + memcpy(orig_tweak, tweak, SE_KEY_128_SIZE); + + // We are assuming a 16 sector aligned size in this implementation. + for (u32 i = 0; i < (sec_size >> 4); i++) + { + for (u32 j = 0; j < 4; j++) + pdst[j] = psrc[j] ^ ptweak[j]; + + _gf256_mul_x_le(tweak); + psrc += 4; + pdst += 4; + } + + if (!se_aes_crypt_ecb(crypt_ks, enc, dst, sec_size, dst, sec_size)) + return 0; + + pdst = (u32 *)dst; + ptweak = (u32 *)orig_tweak; + for (u32 i = 0; i < (sec_size >> 4); i++) + { + for (u32 j = 0; j < 4; j++) + pdst[j] = pdst[j] ^ ptweak[j]; + + _gf256_mul_x_le(orig_tweak); + pdst += 4; + } + + return 1; +} + +int se_aes_xts_crypt(u32 tweak_ks, u32 crypt_ks, u32 enc, u64 sec, void *dst, void *src, u32 secsize, u32 num_secs) { u8 *pdst = (u8 *)dst; u8 *psrc = (u8 *)src; for (u32 i = 0; i < num_secs; i++) - if (!se_aes_xts_crypt_sec(ks1, ks2, enc, sec + i, pdst + secsize * i, psrc + secsize * i, secsize)) + if (!se_aes_xts_crypt_sec(tweak_ks, crypt_ks, enc, sec + i, pdst + secsize * i, psrc + secsize * i, secsize)) return 0; return 1; } +static void se_calc_sha256_get_hash(void *hash, u32 *msg_left) +{ + u32 hash32[SE_SHA_256_SIZE / 4]; + + // Backup message left. + if (msg_left) + { + msg_left[0] = SE(SE_SHA_MSG_LEFT_0_REG); + msg_left[1] = SE(SE_SHA_MSG_LEFT_1_REG); + } + + // Copy output hash. + for (u32 i = 0; i < (SE_SHA_256_SIZE / 4); i++) + hash32[i] = byte_swap_32(SE(SE_HASH_RESULT_REG + (i * 4))); + memcpy(hash, hash32, SE_SHA_256_SIZE); +} + int se_calc_sha256(void *hash, u32 *msg_left, const void *src, u32 src_size, u64 total_size, u32 sha_cfg, bool is_oneshot) { int res; @@ -380,6 +511,17 @@ int se_calc_sha256(void *hash, u32 *msg_left, const void *src, u32 src_size, u64 if (src_size > 0xFFFFFF || !hash) // Max 16MB - 1 chunks and aligned x4 hash buffer. return 0; + // Src size of 0 is not supported, so return null string sha256. + if (!src_size) + { + const u8 null_hash[SE_SHA_256_SIZE] = { + 0xE3, 0xB0, 0xC4, 0x42, 0x98, 0xFC, 0x1C, 0x14, 0x9A, 0xFB, 0xF4, 0xC8, 0x99, 0x6F, 0xB9, 0x24, + 0x27, 0xAE, 0x41, 0xE4, 0x64, 0x9B, 0x93, 0x4C, 0xA4, 0x95, 0x99, 0x1B, 0x78, 0x52, 0xB8, 0x55 + }; + memcpy(hash, null_hash, SE_SHA_256_SIZE); + return 1; + } + // Setup config for SHA256. SE(SE_CONFIG_REG) = SE_CONFIG_ENC_MODE(MODE_SHA256) | SE_CONFIG_ENC_ALG(ALG_SHA) | SE_CONFIG_DST(DST_HASHREG); SE(SE_SHA_CONFIG_REG) = sha_cfg; @@ -418,19 +560,7 @@ int se_calc_sha256(void *hash, u32 *msg_left, const void *src, u32 src_size, u64 res = _se_execute(SE_OP_START, NULL, 0, src, src_size, is_oneshot); if (is_oneshot) - { - // Backup message left. - if (msg_left) - { - msg_left[0] = SE(SE_SHA_MSG_LEFT_0_REG); - msg_left[1] = SE(SE_SHA_MSG_LEFT_1_REG); - } - - // Copy output hash. - for (u32 i = 0; i < (SE_SHA_256_SIZE / 4); i++) - hash32[i] = byte_swap_32(SE(SE_HASH_RESULT_REG + (i * 4))); - memcpy(hash, hash32, SE_SHA_256_SIZE); - } + se_calc_sha256_get_hash(hash, msg_left); return res; } @@ -442,20 +572,9 @@ int se_calc_sha256_oneshot(void *hash, const void *src, u32 src_size) int se_calc_sha256_finalize(void *hash, u32 *msg_left) { - u32 hash32[SE_SHA_256_SIZE / 4]; int res = _se_execute_finalize(); - // Backup message left. - if (msg_left) - { - msg_left[0] = SE(SE_SHA_MSG_LEFT_0_REG); - msg_left[1] = SE(SE_SHA_MSG_LEFT_1_REG); - } - - // Copy output hash. - for (u32 i = 0; i < (SE_SHA_256_SIZE / 4); i++) - hash32[i] = byte_swap_32(SE(SE_HASH_RESULT_REG + (i * 4))); - memcpy(hash, hash32, SE_SHA_256_SIZE); + se_calc_sha256_get_hash(hash, msg_left); return res; } @@ -463,9 +582,9 @@ int se_calc_sha256_finalize(void *hash, u32 *msg_left) int se_gen_prng128(void *dst) { // Setup config for X931 PRNG. - SE(SE_CONFIG_REG) = SE_CONFIG_ENC_MODE(MODE_KEY128) | SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_MEMORY); - SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_HASH(HASH_DISABLE) | SE_CRYPTO_XOR_POS(XOR_BYPASS) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM); - SE(SE_RNG_CONFIG_REG) = SE_RNG_CONFIG_SRC(SRC_ENTROPY) | SE_RNG_CONFIG_MODE(MODE_NORMAL); + SE(SE_CONFIG_REG) = SE_CONFIG_ENC_MODE(MODE_KEY128) | SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_MEMORY); + SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_HASH(HASH_DISABLE) | SE_CRYPTO_XOR_POS(XOR_BYPASS) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM); + SE(SE_RNG_CONFIG_REG) = SE_RNG_CONFIG_SRC(SRC_ENTROPY) | SE_RNG_CONFIG_MODE(MODE_NORMAL); //SE(SE_RNG_SRC_CONFIG_REG) = // SE_RNG_SRC_CONFIG_ENTR_SRC(RO_ENTR_ENABLE) | SE_RNG_SRC_CONFIG_ENTR_SRC_LOCK(RO_ENTR_LOCK_ENABLE); SE(SE_RNG_RESEED_INTERVAL_REG) = 1; @@ -481,9 +600,9 @@ void se_get_aes_keys(u8 *buf, u8 *keys, u32 keysize) u8 *aligned_buf = (u8 *)ALIGN((u32)buf, 0x40); // Set Secure Random Key. - SE(SE_CONFIG_REG) = SE_CONFIG_ENC_MODE(MODE_KEY128) | SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_SRK); - SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(0) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM); - SE(SE_RNG_CONFIG_REG) = SE_RNG_CONFIG_SRC(SRC_ENTROPY) | SE_RNG_CONFIG_MODE(MODE_FORCE_RESEED); + SE(SE_CONFIG_REG) = SE_CONFIG_ENC_MODE(MODE_KEY128) | SE_CONFIG_ENC_ALG(ALG_RNG) | SE_CONFIG_DST(DST_SRK); + SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(0) | SE_CRYPTO_CORE_SEL(CORE_ENCRYPT) | SE_CRYPTO_INPUT_SEL(INPUT_RANDOM); + SE(SE_RNG_CONFIG_REG) = SE_RNG_CONFIG_SRC(SRC_ENTROPY) | SE_RNG_CONFIG_MODE(MODE_FORCE_RESEED); SE(SE_CRYPTO_LAST_BLOCK) = 0; _se_execute_oneshot(SE_OP_START, NULL, 0, NULL, 0); @@ -493,7 +612,7 @@ void se_get_aes_keys(u8 *buf, u8 *keys, u32 keysize) for (u32 i = 0; i < SE_AES_KEYSLOT_COUNT; i++) { SE(SE_CONTEXT_SAVE_CONFIG_REG) = SE_CONTEXT_SRC(AES_KEYTABLE) | SE_KEYTABLE_DST_KEY_INDEX(i) | - SE_CONTEXT_AES_KEY_INDEX(0) | SE_CONTEXT_AES_WORD_QUAD(KEYS_0_3); + SE_CONTEXT_AES_KEY_INDEX(0) | SE_CONTEXT_AES_WORD_QUAD(KEYS_0_3); SE(SE_CRYPTO_LAST_BLOCK) = 0; _se_execute_oneshot(SE_OP_CTX_SAVE, aligned_buf, SE_AES_BLOCK_SIZE, NULL, 0); @@ -502,7 +621,7 @@ void se_get_aes_keys(u8 *buf, u8 *keys, u32 keysize) if (keysize > SE_KEY_128_SIZE) { SE(SE_CONTEXT_SAVE_CONFIG_REG) = SE_CONTEXT_SRC(AES_KEYTABLE) | SE_KEYTABLE_DST_KEY_INDEX(i) | - SE_CONTEXT_AES_KEY_INDEX(0) | SE_CONTEXT_AES_WORD_QUAD(KEYS_4_7); + SE_CONTEXT_AES_KEY_INDEX(0) | SE_CONTEXT_AES_WORD_QUAD(KEYS_4_7); SE(SE_CRYPTO_LAST_BLOCK) = 0; _se_execute_oneshot(SE_OP_CTX_SAVE, aligned_buf, SE_AES_BLOCK_SIZE, NULL, 0); @@ -532,3 +651,63 @@ void se_get_aes_keys(u8 *buf, u8 *keys, u32 keysize) se_aes_crypt_cbc(3, DECRYPT, keys, SE_AES_KEYSLOT_COUNT * keysize, keys, SE_AES_KEYSLOT_COUNT * keysize); se_aes_key_clear(3); } + +int se_aes_cmac_128(u32 ks, void *dst, const void *src, u32 src_size) +{ + int res = 0; + + u32 tmp1[SE_KEY_128_SIZE / sizeof(u32)] = {0}; + u32 tmp2[SE_AES_BLOCK_SIZE / sizeof(u32)] = {0}; + u8 *key = (u8 *)tmp1; + u8 *last_block = (u8 *)tmp2; + + se_aes_iv_clear(ks); + se_aes_iv_updated_clear(ks); + + // Generate sub key + if (!se_aes_crypt_hash(ks, ENCRYPT, key, SE_KEY_128_SIZE, key, SE_KEY_128_SIZE)) + goto out; + + _gf256_mul_x(key); + if (src_size & 0xF) + _gf256_mul_x(key); + + SE(SE_CONFIG_REG) = SE_CONFIG_ENC_MODE(MODE_KEY128) | SE_CONFIG_ENC_ALG(ALG_AES_ENC) | SE_CONFIG_DST(DST_HASHREG); + SE(SE_CRYPTO_CONFIG_REG) = SE_CRYPTO_KEY_INDEX(ks) | SE_CRYPTO_INPUT_SEL(INPUT_MEMORY) | + SE_CRYPTO_XOR_POS(XOR_TOP) | SE_CRYPTO_VCTRAM_SEL(VCTRAM_AESOUT) | SE_CRYPTO_HASH(HASH_ENABLE) | + SE_CRYPTO_CORE_SEL(CORE_ENCRYPT); + se_aes_iv_clear(ks); + se_aes_iv_updated_clear(ks); + + u32 num_blocks = (src_size + 0xf) >> 4; + if (num_blocks > 1) + { + SE(SE_CRYPTO_BLOCK_COUNT_REG) = num_blocks - 2; + if (!_se_execute_oneshot(SE_OP_START, NULL, 0, src, src_size)) + goto out; + SE(SE_CRYPTO_CONFIG_REG) |= SE_CRYPTO_IV_SEL(IV_UPDATED); + } + + if (src_size & 0xf) + { + memcpy(last_block, src + (src_size & ~0xf), src_size & 0xf); + last_block[src_size & 0xf] = 0x80; + } + else if (src_size >= SE_AES_BLOCK_SIZE) + { + memcpy(last_block, src + src_size - SE_AES_BLOCK_SIZE, SE_AES_BLOCK_SIZE); + } + + for (u32 i = 0; i < SE_KEY_128_SIZE; i++) + last_block[i] ^= key[i]; + + SE(SE_CRYPTO_BLOCK_COUNT_REG) = 0; + res = _se_execute_oneshot(SE_OP_START, NULL, 0, last_block, SE_AES_BLOCK_SIZE); + + u32 *dst32 = (u32 *)dst; + for (u32 i = 0; i < (SE_KEY_128_SIZE / 4); i++) + dst32[i] = SE(SE_HASH_RESULT_REG + (i * 4)); + +out: + return res; +} diff --git a/bdk/sec/se.h b/bdk/sec/se.h index 3dd8df3..36b057b 100644 --- a/bdk/sec/se.h +++ b/bdk/sec/se.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2019-2021 CTCaer + * Copyright (c) 2019-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,25 +18,32 @@ #ifndef _SE_H_ #define _SE_H_ +#include "se_t210.h" #include void se_rsa_acc_ctrl(u32 rs, u32 flags); void se_key_acc_ctrl(u32 ks, u32 flags); u32 se_key_acc_ctrl_get(u32 ks); void se_get_aes_keys(u8 *buf, u8 *keys, u32 keysize); -void se_aes_key_set(u32 ks, void *key, u32 size); -void se_aes_iv_set(u32 ks, void *iv); +void se_aes_key_set(u32 ks, const void *key, u32 size); +void se_aes_iv_set(u32 ks, const void *iv); void se_aes_key_get(u32 ks, void *key, u32 size); void se_aes_key_clear(u32 ks); void se_aes_iv_clear(u32 ks); +void se_aes_iv_updated_clear(u32 ks); int se_aes_unwrap_key(u32 ks_dst, u32 ks_src, const void *input); +int se_aes_crypt_hash(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size); int se_aes_crypt_cbc(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size); int se_aes_crypt_ecb(u32 ks, u32 enc, void *dst, u32 dst_size, const void *src, u32 src_size); int se_aes_crypt_block_ecb(u32 ks, u32 enc, void *dst, const void *src); +int se_aes_xts_crypt_sec(u32 tweak_ks, u32 crypt_ks, u32 enc, u64 sec, void *dst, void *src, u32 secsize); +int se_aes_xts_crypt_sec_nx(u32 tweak_ks, u32 crypt_ks, u32 enc, u64 sec, u8 *tweak, bool regen_tweak, u32 tweak_exp, void *dst, void *src, u32 sec_size); +int se_aes_xts_crypt(u32 tweak_ks, u32 crypt_ks, u32 enc, u64 sec, void *dst, void *src, u32 secsize, u32 num_secs); int se_aes_crypt_ctr(u32 ks, void *dst, u32 dst_size, const void *src, u32 src_size, void *ctr); int se_calc_sha256(void *hash, u32 *msg_left, const void *src, u32 src_size, u64 total_size, u32 sha_cfg, bool is_oneshot); int se_calc_sha256_oneshot(void *hash, const void *src, u32 src_size); int se_calc_sha256_finalize(void *hash, u32 *msg_left); int se_gen_prng128(void *dst); +int se_aes_cmac_128(u32 ks, void *dst, const void *src, u32 src_size); #endif diff --git a/bdk/sec/se_t210.h b/bdk/sec/se_t210.h index 350bc15..317c4fa 100644 --- a/bdk/sec/se_t210.h +++ b/bdk/sec/se_t210.h @@ -304,6 +304,8 @@ #define SE_STATUS_STATE_WAIT_OUT 2 #define SE_STATUS_STATE_WAIT_IN 3 #define SE_STATUS_STATE_MASK 3 +#define SE_STATUS_MEM_IF_IDLE (0 << 2) +#define SE_STATUS_MEM_IF_BUSY BIT(2) #define SE_ERR_STATUS_REG 0x804 #define SE_ERR_STATUS_SE_NS_ACCESS BIT(0) diff --git a/bdk/sec/tsec.c b/bdk/sec/tsec.c index 1e9d01f..de2dbbb 100644 --- a/bdk/sec/tsec.c +++ b/bdk/sec/tsec.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2024 CTCaer * Copyright (c) 2018 balika011 * * This program is free software; you can redistribute it and/or modify it @@ -20,16 +20,17 @@ #include "tsec.h" #include "tsec_t210.h" +#include +#include +#include +#include #include #include #include #include #include #include -#include -#include -#include -#include +#include // #include @@ -57,9 +58,9 @@ static int _tsec_dma_pa_to_internal_100(int not_imem, int i_offset, int pa_offse else cmd = TSEC_DMATRFCMD_IMEM; // DMA IMEM (Instruction memmory) - TSEC(TSEC_DMATRFMOFFS) = i_offset; + TSEC(TSEC_DMATRFMOFFS) = i_offset; TSEC(TSEC_DMATRFFBOFFS) = pa_offset; - TSEC(TSEC_DMATRFCMD) = cmd; + TSEC(TSEC_DMATRFCMD) = cmd; return _tsec_dma_wait_idle(); } @@ -69,23 +70,24 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) int res = 0; u8 *fwbuf = NULL; u32 type = tsec_ctxt->type; - u32 *pdir, *car, *fuse, *pmc, *flowctrl, *se, *mc, *iram, *evec; + u32 *car, *fuse, *pmc, *flowctrl, *se, *mc, *iram, *evec; u32 *pkg11_magic_off; + void *ptb; bpmp_mmu_disable(); - bpmp_freq_t prev_fid = bpmp_clk_rate_set(BPMP_CLK_NORMAL); + bpmp_clk_rate_relaxed(true); // Enable clocks. - clock_enable_host1x(); - usleep(2); clock_enable_tsec(); clock_enable_sor_safe(); clock_enable_sor0(); clock_enable_sor1(); clock_enable_kfuse(); - kfuse_wait_ready(); + // Disable AHB aperture. + mc_disable_ahb_redirect(); + if (type == TSEC_FW_TYPE_NEW) { // Disable all CCPLEX core rails. @@ -95,23 +97,23 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) pmc_enable_partition(POWER_RAIL_CE3, DISABLE); // Enable AHB aperture and set it to full mmio. - mc_enable_ahb_redirect(true); + mc_enable_ahb_redirect(); } // Configure Falcon. TSEC(TSEC_DMACTL) = 0; TSEC(TSEC_IRQMSET) = TSEC_IRQMSET_EXT(0xFF) | - TSEC_IRQMSET_WDTMR | - TSEC_IRQMSET_HALT | - TSEC_IRQMSET_EXTERR | - TSEC_IRQMSET_SWGEN0 | + TSEC_IRQMSET_WDTMR | + TSEC_IRQMSET_HALT | + TSEC_IRQMSET_EXTERR | + TSEC_IRQMSET_SWGEN0 | TSEC_IRQMSET_SWGEN1; TSEC(TSEC_IRQDEST) = TSEC_IRQDEST_EXT(0xFF) | - TSEC_IRQDEST_HALT | - TSEC_IRQDEST_EXTERR | - TSEC_IRQDEST_SWGEN0 | + TSEC_IRQDEST_HALT | + TSEC_IRQDEST_EXTERR | + TSEC_IRQDEST_SWGEN0 | TSEC_IRQDEST_SWGEN1; TSEC(TSEC_ITFEN) = TSEC_ITFEN_CTXEN | TSEC_ITFEN_MTHDEN; if (!_tsec_dma_wait_idle()) @@ -125,9 +127,10 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) TSEC(TSEC_DMATRFBASE) = (u32)tsec_ctxt->fw >> 8; else { - fwbuf = (u8 *)malloc(0x4000); + fwbuf = (u8 *)malloc(SZ_16K); u8 *fwbuf_aligned = (u8 *)ALIGN((u32)fwbuf, 0x100); memcpy(fwbuf_aligned, tsec_ctxt->fw, tsec_ctxt->size); + TSEC(TSEC_DMATRFBASE) = (u32)fwbuf_aligned >> 8; } @@ -143,69 +146,69 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) if (type == TSEC_FW_TYPE_EMU) { // Init SMMU translation for TSEC. - pdir = smmu_init_for_tsec(); - smmu_init(tsec_ctxt->secmon_base); - // Enable SMMU - if (!smmu_is_used()) - smmu_enable(); + ptb = smmu_init_domain(MC_SMMU_TSEC_ASID, 1); + smmu_init(); + + // Enable SMMU. + smmu_enable(); // Clock reset controller. - car = page_alloc(1); - memcpy(car, (void *)CLOCK_BASE, 0x1000); - car[CLK_RST_CONTROLLER_CLK_SOURCE_TSEC / 4] = 2; - smmu_map(pdir, CLOCK_BASE, (u32)car, 1, _WRITABLE | _READABLE | _NONSECURE); + car = smmu_page_zalloc(1); + memcpy(car, (void *)CLOCK_BASE, SZ_PAGE); + car[CLK_RST_CONTROLLER_CLK_SOURCE_TSEC / 4] = CLK_SRC_DIV(2); + smmu_map(ptb, CLOCK_BASE, (u32)car, 1, SMMU_WRITE | SMMU_READ | SMMU_NS); // Fuse driver. - fuse = page_alloc(1); - memcpy((void *)&fuse[0x800/4], (void *)FUSE_BASE, 0x400); + fuse = smmu_page_zalloc(1); + memcpy((void *)&fuse[0x800/4], (void *)FUSE_BASE, SZ_1K); fuse[0x82C / 4] = 0; fuse[0x9E0 / 4] = (1 << (TSEC_HOS_KB_620 + 2)) - 1; fuse[0x9E4 / 4] = (1 << (TSEC_HOS_KB_620 + 2)) - 1; - smmu_map(pdir, (FUSE_BASE - 0x800), (u32)fuse, 1, _READABLE | _NONSECURE); + smmu_map(ptb, (FUSE_BASE - 0x800), (u32)fuse, 1, SMMU_READ | SMMU_NS); // Power management controller. - pmc = page_alloc(1); - smmu_map(pdir, RTC_BASE, (u32)pmc, 1, _READABLE | _NONSECURE); + pmc = smmu_page_zalloc(1); + smmu_map(ptb, RTC_BASE, (u32)pmc, 1, SMMU_READ | SMMU_NS); // Flow control. - flowctrl = page_alloc(1); - smmu_map(pdir, FLOW_CTLR_BASE, (u32)flowctrl, 1, _WRITABLE | _NONSECURE); + flowctrl = smmu_page_zalloc(1); + smmu_map(ptb, FLOW_CTLR_BASE, (u32)flowctrl, 1, SMMU_WRITE | SMMU_NS); // Security engine. - se = page_alloc(1); - memcpy(se, (void *)SE_BASE, 0x1000); - smmu_map(pdir, SE_BASE, (u32)se, 1, _READABLE | _WRITABLE | _NONSECURE); + se = smmu_page_zalloc(1); + memcpy(se, (void *)SE_BASE, SZ_PAGE); + smmu_map(ptb, SE_BASE, (u32)se, 1, SMMU_READ | SMMU_WRITE | SMMU_NS); // Memory controller. - mc = page_alloc(1); - memcpy(mc, (void *)MC_BASE, 0x1000); + mc = smmu_page_zalloc(1); + memcpy(mc, (void *)MC_BASE, SZ_PAGE); mc[MC_IRAM_BOM / 4] = 0; - mc[MC_IRAM_TOM / 4] = 0x80000000; - smmu_map(pdir, MC_BASE, (u32)mc, 1, _READABLE | _NONSECURE); + mc[MC_IRAM_TOM / 4] = DRAM_START; + smmu_map(ptb, MC_BASE, (u32)mc, 1, SMMU_READ | SMMU_NS); // IRAM - iram = page_alloc(0x30); + iram = smmu_page_zalloc(0x30); memcpy(iram, tsec_ctxt->pkg1, 0x30000); // PKG1.1 magic offset. - pkg11_magic_off = (u32 *)(iram + ((tsec_ctxt->pkg11_off + 0x20) / 4)); - smmu_map(pdir, 0x40010000, (u32)iram, 0x30, _READABLE | _WRITABLE | _NONSECURE); + pkg11_magic_off = (u32 *)(iram + ((tsec_ctxt->pkg11_off + 0x20) / sizeof(u32))); + smmu_map(ptb, 0x40010000, (u32)iram, 0x30, SMMU_READ | SMMU_WRITE | SMMU_NS); // Exception vectors - evec = page_alloc(1); - smmu_map(pdir, EXCP_VEC_BASE, (u32)evec, 1, _READABLE | _WRITABLE | _NONSECURE); + evec = smmu_page_zalloc(1); + smmu_map(ptb, EXCP_VEC_BASE, (u32)evec, 1, SMMU_READ | SMMU_WRITE | SMMU_NS); } // Execute firmware. HOST1X(HOST1X_CH0_SYNC_SYNCPT_160) = 0x34C2E1DA; - TSEC(TSEC_STATUS) = 0; - TSEC(TSEC_BOOTKEYVER) = 1; // HOS uses key version 1. - TSEC(TSEC_BOOTVEC) = 0; - TSEC(TSEC_CPUCTL) = TSEC_CPUCTL_STARTCPU; + TSEC(TSEC_MAILBOX1) = 0; + TSEC(TSEC_MAILBOX0) = 1; // Set HOS key version. + TSEC(TSEC_BOOTVEC) = 0; + TSEC(TSEC_CPUCTL) = TSEC_CPUCTL_STARTCPU; if (type == TSEC_FW_TYPE_EMU) { - u32 start = get_tmr_us(); u32 k = se[SE_CRYPTO_KEYTABLE_DATA_REG / 4]; + u32 timeout = get_tmr_us() + 125000; u32 key[16] = {0}; u32 kidx = 0; @@ -220,14 +223,14 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) } // Failsafe. - if ((u32)get_tmr_us() - start > 125000) + if ((u32)get_tmr_us() > timeout) break; } if (kidx != 8) { res = -6; - smmu_deinit_for_tsec(); + smmu_deinit_domain(MC_SMMU_TSEC_ASID, 1); goto out_free; } @@ -238,12 +241,12 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) memcpy(tsec_keys, &key, 0x20); memcpy(tsec_ctxt->pkg1, iram, 0x30000); - smmu_deinit_for_tsec(); + smmu_deinit_domain(MC_SMMU_TSEC_ASID, 1); // for (int i = 0; i < kidx; i++) // gfx_printf("key %08X\n", key[i]); - // gfx_printf("cpuctl (%08X) mbox (%08X)\n", TSEC(TSEC_CPUCTL), TSEC(TSEC_STATUS)); + // gfx_printf("cpuctl (%08X) mbox (%08X)\n", TSEC(TSEC_CPUCTL), TSEC(TSEC_MAILBOX1)); // u32 errst = MC(MC_ERR_STATUS); // gfx_printf(" MC %08X %08X %08X\n", MC(MC_INTSTATUS), errst, MC(MC_ERR_ADR)); @@ -259,14 +262,18 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) res = -3; goto out_free; } + u32 timeout = get_tmr_ms() + 2000; - while (!TSEC(TSEC_STATUS)) + while (!TSEC(TSEC_MAILBOX1)) + { if (get_tmr_ms() > timeout) { res = -4; goto out_free; } - if (TSEC(TSEC_STATUS) != 0xB0B0B0B0) + } + + if (TSEC(TSEC_MAILBOX1) != 0xB0B0B0B0) { res = -5; goto out_free; @@ -275,23 +282,22 @@ int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt) // Fetch result. HOST1X(HOST1X_CH0_SYNC_SYNCPT_160) = 0; u32 buf[4]; - buf[0] = SOR1(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB); - buf[1] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB); - buf[2] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB); - buf[3] = SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB); - SOR1(SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB) = 0; - SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB) = 0; - SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB) = 0; - SOR1(SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB) = 0; + buf[0] = SOR1(SOR_DP_HDCP_BKSV_LSB); + buf[1] = SOR1(SOR_TMDS_HDCP_BKSV_LSB); + buf[2] = SOR1(SOR_TMDS_HDCP_CN_MSB); + buf[3] = SOR1(SOR_TMDS_HDCP_CN_LSB); + SOR1(SOR_DP_HDCP_BKSV_LSB) = 0; + SOR1(SOR_TMDS_HDCP_BKSV_LSB) = 0; + SOR1(SOR_TMDS_HDCP_CN_MSB) = 0; + SOR1(SOR_TMDS_HDCP_CN_LSB) = 0; memcpy(tsec_keys, &buf, SE_KEY_128_SIZE); } -out_free:; +out_free: free(fwbuf); -out:; - +out: // Disable clocks. clock_disable_kfuse(); clock_disable_sor1(); @@ -299,11 +305,12 @@ out:; clock_disable_sor_safe(); clock_disable_tsec(); bpmp_mmu_enable(); - bpmp_clk_rate_set(prev_fid); + bpmp_clk_rate_relaxed(false); - // Disable AHB aperture. - if (type == TSEC_FW_TYPE_NEW) - mc_disable_ahb_redirect(); +#ifdef BDK_MC_ENABLE_AHB_REDIRECT + // Re-enable AHB aperture. + mc_enable_ahb_redirect(); +#endif return res; } diff --git a/bdk/sec/tsec.h b/bdk/sec/tsec.h index 7456e44..16aa4b7 100644 --- a/bdk/sec/tsec.h +++ b/bdk/sec/tsec.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert -* Copyright (c) 2018-2021 CTCaer +* Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -24,7 +24,7 @@ enum tsec_fw_type { // Retail Hovi Keygen. TSEC_FW_TYPE_OLD = 0, // 1.0.0 - 6.1.0. - TSEC_FW_TYPE_EMU = 1, // 6.2.0 emulated enviroment. + TSEC_FW_TYPE_EMU = 1, // 6.2.0 emulated environment. TSEC_FW_TYPE_NEW = 2, // 7.0.0+. }; @@ -35,7 +35,6 @@ typedef struct _tsec_ctxt_t u32 type; void *pkg1; u32 pkg11_off; - u32 secmon_base; } tsec_ctxt_t; int tsec_query(void *tsec_keys, tsec_ctxt_t *tsec_ctxt); diff --git a/bdk/sec/tsec_t210.h b/bdk/sec/tsec_t210.h index 889d0d4..96624e2 100644 --- a/bdk/sec/tsec_t210.h +++ b/bdk/sec/tsec_t210.h @@ -1,5 +1,5 @@ /* -* Copyright (c) 2018 CTCaer +* Copyright (c) 2018-2023 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,8 +17,8 @@ #ifndef _TSEC_T210_H_ #define _TSEC_T210_H_ -#define TSEC_BOOTKEYVER 0x1040 -#define TSEC_STATUS 0x1044 +#define TSEC_MAILBOX0 0x1040 +#define TSEC_MAILBOX1 0x1044 #define TSEC_ITFEN 0x1048 #define TSEC_ITFEN_CTXEN BIT(0) #define TSEC_ITFEN_MTHDEN BIT(1) diff --git a/bdk/soc/actmon.c b/bdk/soc/actmon.c new file mode 100644 index 0000000..568f82e --- /dev/null +++ b/bdk/soc/actmon.c @@ -0,0 +1,172 @@ +/* + * Activity Monitor driver for Tegra X1 + * + * Copyright (c) 2021 CTCaer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include "actmon.h" +#include "clock.h" +#include "t210.h" + +/* Global registers */ +#define ACTMON_GLB_STATUS 0x0 +#define ACTMON_MCCPU_MON_ACT BIT(8) +#define ACTMON_MCALL_MON_ACT BIT(9) +#define ACTMON_CPU_FREQ_MON_ACT BIT(10) +#define ACTMON_APB_MON_ACT BIT(12) +#define ACTMON_AHB_MON_ACT BIT(13) +#define ACTMON_BPMP_MON_ACT BIT(14) +#define ACTMON_CPU_MON_ACT BIT(15) +#define ACTMON_MCCPU_INTR BIT(25) +#define ACTMON_MCALL_INTR BIT(26) +#define ACTMON_CPU_FREQ_INTR BIT(27) +#define ACTMON_APB_INTR BIT(28) +#define ACTMON_AHB_INTR BIT(29) +#define ACTMON_BPMP_INTR BIT(30) +#define ACTMON_CPU_INTR BIT(31) +#define ACTMON_GLB_PERIOD_CTRL 0x4 +#define ACTMON_GLB_PERIOD_USEC BIT(8) +#define ACTMON_GLB_PERIOD_SAMPLE(n) (((n) - 1) & 0xFF) + +/* Device Registers */ +#define ACTMON_DEV_BASE ACTMON_BASE + 0x80 +#define ACTMON_DEV_SIZE 0x40 +/* CTRL */ +#define ACTMON_DEV_CTRL_K_VAL(k) (((k) & 7) << 10) +#define ACTMON_DEV_CTRL_ENB_PERIODIC BIT(18) +#define ACTMON_DEV_CTRL_AT_END_EN BIT(19) +#define ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN BIT(20) +#define ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN BIT(21) +#define ACTMON_DEV_CTRL_WHEN_OVERFLOW_EN BIT(22) +#define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM(n) (((n) & 7) << 23) +#define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM(n) (((n) & 7) << 26) +#define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN BIT(29) +#define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN BIT(30) +#define ACTMON_DEV_CTRL_ENB BIT(31) +/* INTR_STATUS */ +#define ACTMON_DEV_ISTS_AVG_ABOVE_WMARK BIT(24) +#define ACTMON_DEV_ISTS_AVG_BELOW_WMARK BIT(25) +#define ACTMON_DEV_ISTS_WHEN_OVERFLOW BIT(26) +#define ACTMON_DEV_ISTS_AT_END BIT(29) +#define ACTMON_DEV_ISTS_CONSECUTIVE_LOWER BIT(30) +#define ACTMON_DEV_ISTS_CONSECUTIVE_UPPER BIT(31) + +/* Histogram Registers */ +#define ACTMON_HISTOGRAM_CONFIG 0x300 +#define ACTMON_HIST_CFG_ACTIVE BIT(0) +#define ACTMON_HIST_CFG_LINEAR_MODE BIT(1) +#define ACTMON_HIST_CFG_NO_UNDERFLOW_BUCKET BIT(2) +#define ACTMON_HIST_CFG_STALL_ON_SINGLE_SATURATE BIT(3) +#define ACTMON_HIST_CFG_SHIFT(s) (((s) & 0x1F) << 4) +#define ACTMON_HIST_CFG_SOURCE(s) (((s) & 0xF) << 12) +#define ACTMON_HISTOGRAM_CTRL 0x304 +#define ACTMON_HIST_CTRL_CLEAR_ALL BIT(0) +#define ACTMON_HISTOGRAM_DATA_BASE 0x380 +#define ACTMON_HISTOGRAM_DATA_NUM 32 + +#define ACTMON_FREQ 19200000 +#define ACTMON_PERIOD_MS 20 +#define DEV_COUNT_WEIGHT 5 + +typedef struct _actmon_dev_reg_t +{ + vu32 ctrl; + vu32 upper_wnark; + vu32 lower_wmark; + vu32 init_avg; + vu32 avg_upper_wmark; + vu32 avg_lower_wmark; + vu32 count_weight; + vu32 count; + vu32 avg_count; + vu32 intr_status; + vu32 ctrl2; + vu32 rsvd[5]; +} actmon_dev_reg_t; + +void actmon_hist_enable(actmon_hist_src_t src) +{ + ACTMON(ACTMON_HISTOGRAM_CONFIG) = ACTMON_HIST_CFG_SOURCE(src) | ACTMON_HIST_CFG_ACTIVE; + ACTMON(ACTMON_HISTOGRAM_CTRL) = ACTMON_HIST_CTRL_CLEAR_ALL; +} + +void actmon_hist_disable() +{ + ACTMON(ACTMON_HISTOGRAM_CONFIG) = 0; +} + +void actmon_hist_get(u32 *histogram) +{ + if (histogram) + { + for (u32 i = 0; i < ACTMON_HISTOGRAM_DATA_NUM; i++) + histogram[i] = ACTMON(ACTMON_HISTOGRAM_DATA_BASE + i * sizeof(u32)); + } +} + +void actmon_dev_enable(actmon_dev_t dev) +{ + actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE)); + + regs->init_avg = ACTMON_FREQ * ACTMON_PERIOD_MS * DEV_COUNT_WEIGHT / 100; + regs->count_weight = DEV_COUNT_WEIGHT; + + regs->ctrl = ACTMON_DEV_CTRL_ENB | ACTMON_DEV_CTRL_ENB_PERIODIC | ACTMON_DEV_CTRL_K_VAL(7); // 128 samples average. +} + +void actmon_dev_disable(actmon_dev_t dev) +{ + actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE)); + + regs->ctrl = 0; +} + +u32 actmon_dev_get_load(actmon_dev_t dev) +{ + actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE)); + + // Get load-based sampling. 1 decimal point precision. + u32 load = regs->count * 100 / (ACTMON_FREQ / (ACTMON_PERIOD_MS * DEV_COUNT_WEIGHT)); + + return load; +} + +u32 actmon_dev_get_load_avg(actmon_dev_t dev) +{ + actmon_dev_reg_t *regs = (actmon_dev_reg_t *)(ACTMON_DEV_BASE + (dev * ACTMON_DEV_SIZE)); + + // Get load-based sampling. 1 decimal point precision. + u32 avg_load = regs->avg_count * 100 / (ACTMON_FREQ / (ACTMON_PERIOD_MS * DEV_COUNT_WEIGHT)); + + return avg_load; +} + +void atmon_dev_all_disable() +{ + // TODO: do a global reset? +} + +void actmon_init() +{ + clock_enable_actmon(); + + // Set period. + ACTMON(ACTMON_GLB_PERIOD_CTRL) = ACTMON_GLB_PERIOD_SAMPLE(ACTMON_PERIOD_MS); +} + +void actmon_end() +{ + clock_disable_actmon(); +} \ No newline at end of file diff --git a/bdk/soc/actmon.h b/bdk/soc/actmon.h new file mode 100644 index 0000000..dc9d0c5 --- /dev/null +++ b/bdk/soc/actmon.h @@ -0,0 +1,62 @@ +/* + * Activity Monitor driver for Tegra X1 + * + * Copyright (c) 2021 CTCaer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __ACTMON_H_ +#define __ACTMON_H_ + +#include + +typedef enum _actmon_dev_t +{ + ACTMON_DEV_CPU, + ACTMON_DEV_BPMP, + ACTMON_DEV_AHB, + ACTMON_DEV_APB, + ACTMON_DEV_CPU_FREQ, + ACTMON_DEV_MC_ALL, + ACTMON_DEV_MC_CPU, + + ACTMON_DEV_NUM, +} actmon_dev_t; + +typedef enum _actmon_hist_src_t +{ + ACTMON_HIST_SRC_NONE = 0, + ACTMON_HIST_SRC_AHB = 1, + ACTMON_HIST_SRC_APB = 2, + ACTMON_HIST_SRC_BPMP = 3, + ACTMON_HIST_SRC_CPU = 4, + ACTMON_HIST_SRC_MC_ALL = 5, + ACTMON_HIST_SRC_MC_CPU = 6, + ACTMON_HIST_SRC_CPU_FREQ = 7, + ACTMON_HIST_SRC_NA = 8, + ACTMON_HIST_SRC_APB_MMIO = 9, +} actmon_hist_src_t; + +void actmon_hist_enable(actmon_hist_src_t src); +void actmon_hist_disable(); +void actmon_hist_get(u32 *histogram); +void actmon_dev_enable(actmon_dev_t dev); +void actmon_dev_disable(actmon_dev_t dev); +u32 actmon_dev_get_load(actmon_dev_t dev); +u32 actmon_dev_get_load_avg(actmon_dev_t dev); +void atmon_dev_all_disable(); +void actmon_init(); +void actmon_end(); + +#endif \ No newline at end of file diff --git a/bdk/soc/bpmp.c b/bdk/soc/bpmp.c index fc0e412..3979c2a 100644 --- a/bdk/soc/bpmp.c +++ b/bdk/soc/bpmp.c @@ -1,7 +1,7 @@ /* * BPMP-Lite Cache/MMU and Frequency driver for Tegra X1 * - * Copyright (c) 2019-2021 CTCaer + * Copyright (c) 2019-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,9 +18,9 @@ #include #include +#include #include #include -#include #define BPMP_MMU_CACHE_LINE_SIZE 0x20 @@ -118,7 +118,7 @@ #define MMU_EN_READ BIT(2) #define MMU_EN_WRITE BIT(3) -bpmp_mmu_entry_t mmu_entries[] = +static const bpmp_mmu_entry_t mmu_entries[] = { { DRAM_START, 0xFFFFFFFF, MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC | MMU_EN_CACHED, true }, { IRAM_BASE, 0x4003FFFF, MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC | MMU_EN_CACHED, true } @@ -134,13 +134,13 @@ void bpmp_mmu_maintenance(u32 op, bool force) // This is a blocking operation. BPMP_CACHE_CTRL(BPMP_CACHE_MAINT_REQ) = MAINT_REQ_WAY_BITMAP(0xF) | op; - while(!(BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT) & INT_MAINT_DONE)) + while (!(BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT) & INT_MAINT_DONE)) ; BPMP_CACHE_CTRL(BPMP_CACHE_INT_CLEAR) = BPMP_CACHE_CTRL(BPMP_CACHE_INT_RAW_EVENT); } -void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply) +void bpmp_mmu_set_entry(int idx, const bpmp_mmu_entry_t *entry, bool apply) { if (idx > 31) return; @@ -150,8 +150,8 @@ void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply) if (entry->enable) { mmu_entry->start_addr = ALIGN(entry->start_addr, BPMP_MMU_CACHE_LINE_SIZE); - mmu_entry->end_addr = ALIGN_DOWN(entry->end_addr, BPMP_MMU_CACHE_LINE_SIZE); - mmu_entry->attr = entry->attr; + mmu_entry->end_addr = ALIGN_DOWN(entry->end_addr, BPMP_MMU_CACHE_LINE_SIZE); + mmu_entry->attr = entry->attr; BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) |= BIT(idx); @@ -166,9 +166,9 @@ void bpmp_mmu_enable() return; // Init BPMP MMU. - BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_INIT; + BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CMD) = MMU_CMD_INIT; BPMP_CACHE_CTRL(BPMP_CACHE_MMU_FALLBACK_ENTRY) = MMU_EN_READ | MMU_EN_WRITE | MMU_EN_EXEC; // RWX for non-defined regions. - BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CFG) = MMU_CFG_SEQ_EN | MMU_CFG_TLB_EN | MMU_CFG_ABORT_STORE_LAST; + BPMP_CACHE_CTRL(BPMP_CACHE_MMU_CFG) = MMU_CFG_SEQ_EN | MMU_CFG_TLB_EN | MMU_CFG_ABORT_STORE_LAST; // Init BPMP MMU entries. BPMP_CACHE_CTRL(BPMP_CACHE_MMU_SHADOW_COPY_MASK) = 0; @@ -200,20 +200,54 @@ void bpmp_mmu_disable() BPMP_CACHE_CTRL(BPMP_CACHE_CONFIG) = 0; } + +/* + * CLK_RST_CONTROLLER_SCLK_BURST_POLICY: + * 0 = CLKM + * 1 = PLLC_OUT1 + * 2 = PLLC4_OUT3 + * 3 = PLLP_OUT0 + * 4 = PLLP_OUT2 + * 5 = PLLC4_OUT1 + * 6 = CLK_S + * 7 = PLLC4_OUT2 + */ + +bpmp_freq_t bpmp_fid_current = BPMP_CLK_NORMAL; + +void bpmp_clk_rate_relaxed(bool enable) +{ + // This is a glitch-free way to reduce the SCLK timings. + if (enable) + { + // Restore to PLLP source during PLLC configuration. + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003330; // PLLP_OUT. + usleep(100); // Wait a bit for clock source change. + CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // PCLK = HCLK / (2 + 1). HCLK == SCLK. + } + else if (bpmp_fid_current) + { + // Restore to PLLC_OUT1. + CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 3; // PCLK = HCLK / (3 + 1). HCLK == SCLK. + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003310; // PLLC_OUT1 and CLKM for idle. + usleep(100); // Wait a bit for clock source change. + } +} + // APB clock affects RTC, PWM, MEMFETCH, APE, USB, SOR PWM, // I2C host, DC/DSI/DISP. UART gives extra stress. // 92: 100% success ratio. 93-94: 595-602MHz has 99% success ratio. 95: 608MHz less. -const u8 pll_divn[] = { +// APB clock max is supposed to be 204 MHz though. +static const u8 pll_divn[] = { 0, // BPMP_CLK_NORMAL: 408MHz 0% - 136MHz APB. 85, // BPMP_CLK_HIGH_BOOST: 544MHz 33% - 136MHz APB. + 88, // BPMP_CLK_HIGH2_BOOST: 563MHz 38% - 141MHz APB. 90, // BPMP_CLK_SUPER_BOOST: 576MHz 41% - 144MHz APB. 92 // BPMP_CLK_HYPER_BOOST: 589MHz 44% - 147MHz APB. // Do not use for public releases! //95 // BPMP_CLK_DEV_BOOST: 608MHz 49% - 152MHz APB. }; -bpmp_freq_t bpmp_fid_current = BPMP_CLK_NORMAL; - void bpmp_clk_rate_get() { bool clk_src_is_pllp = ((CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) >> 4) & 7) == 3; @@ -236,45 +270,42 @@ void bpmp_clk_rate_get() } } -bpmp_freq_t bpmp_clk_rate_set(bpmp_freq_t fid) +void bpmp_clk_rate_set(bpmp_freq_t fid) { - bpmp_freq_t prev_fid = bpmp_fid_current; - if (fid > (BPMP_CLK_MAX - 1)) fid = BPMP_CLK_MAX - 1; - if (prev_fid == fid) - return prev_fid; + if (bpmp_fid_current == fid) + return; + + bpmp_fid_current = fid; if (fid) { - if (prev_fid) - { - // Restore to PLLP source during PLLC configuration. - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // PLLP_OUT. - msleep(1); // Wait a bit for clock source change. - } + // Use default SCLK / HCLK / PCLK clocks. + bpmp_clk_rate_relaxed(true); // Configure and enable PLLC. clock_enable_pllc(pll_divn[fid]); - // Set SCLK / HCLK / PCLK. - CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 3; // PCLK = HCLK / (3 + 1). HCLK == SCLK. - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003310; // PLLC_OUT1 for active and CLKM for idle. + // Set new source and SCLK / HCLK / PCLK dividers. + bpmp_clk_rate_relaxed(false); } else { - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003330; // PLLP_OUT for active and CLKM for idle. - msleep(1); // Wait a bit for clock source change. - CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // PCLK = HCLK / (2 + 1). HCLK == SCLK. + // Use default SCLK / HCLK / PCLK clocks. + bpmp_clk_rate_relaxed(true); // Disable PLLC to save power. clock_disable_pllc(); } - bpmp_fid_current = fid; +} - // Return old fid in case of temporary swap. - return prev_fid; +// State is reset to RUN on any clock or source set via SW. +void bpmp_state_set(bpmp_state_t state) +{ + u32 cfg = CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) & ~0xF0000000u; + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = cfg | (state << 28u); } // The following functions halt BPMP to reduce power while sleeping. @@ -286,10 +317,10 @@ void bpmp_usleep(u32 us) // Each iteration takes 1us. while (us) { - delay = (us > HALT_COP_MAX_CNT) ? HALT_COP_MAX_CNT : us; + delay = (us > HALT_MAX_CNT) ? HALT_MAX_CNT : us; us -= delay; - FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_USEC | delay; + FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_MODE_WAITEVENT | HALT_USEC | delay; } } @@ -300,14 +331,14 @@ void bpmp_msleep(u32 ms) // Iteration time is variable. ~200 - 1000us. while (ms) { - delay = (ms > HALT_COP_MAX_CNT) ? HALT_COP_MAX_CNT : ms; + delay = (ms > HALT_MAX_CNT) ? HALT_MAX_CNT : ms; ms -= delay; - FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_MSEC | delay; + FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_MODE_WAITEVENT | HALT_MSEC | delay; } } void bpmp_halt() { - FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_WAIT_EVENT | HALT_COP_JTAG; + FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_MODE_WAITEVENT | HALT_JTAG; } diff --git a/bdk/soc/bpmp.h b/bdk/soc/bpmp.h index 0f80150..ace1290 100644 --- a/bdk/soc/bpmp.h +++ b/bdk/soc/bpmp.h @@ -1,7 +1,7 @@ /* * BPMP-Lite Cache/MMU and Frequency driver for Tegra X1 * - * Copyright (c) 2019-2021 CTCaer + * Copyright (c) 2019-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -47,21 +47,35 @@ typedef enum { BPMP_CLK_NORMAL, // 408MHz 0% - 136MHz APB. BPMP_CLK_HIGH_BOOST, // 544MHz 33% - 136MHz APB. + BPMP_CLK_HIGH2_BOOST, // 563MHz 38% - 141MHz APB. BPMP_CLK_SUPER_BOOST, // 576MHz 41% - 144MHz APB. BPMP_CLK_HYPER_BOOST, // 589MHz 44% - 147MHz APB. //BPMP_CLK_DEV_BOOST, // 608MHz 49% - 152MHz APB. BPMP_CLK_MAX } bpmp_freq_t; +typedef enum +{ + BPMP_STATE_STANDBY = 0, // 32KHz. + BPMP_STATE_IDLE = 1, + BPMP_STATE_RUN = 2, + + BPMP_STATE_IRQ = BIT(2), + BPMP_STATE_FIQ = BIT(3), +} bpmp_state_t; + +#define BPMP_CLK_LOWEST_BOOST BPMP_CLK_HIGH2_BOOST #define BPMP_CLK_LOWER_BOOST BPMP_CLK_SUPER_BOOST #define BPMP_CLK_DEFAULT_BOOST BPMP_CLK_HYPER_BOOST void bpmp_mmu_maintenance(u32 op, bool force); -void bpmp_mmu_set_entry(int idx, bpmp_mmu_entry_t *entry, bool apply); +void bpmp_mmu_set_entry(int idx, const bpmp_mmu_entry_t *entry, bool apply); void bpmp_mmu_enable(); void bpmp_mmu_disable(); +void bpmp_clk_rate_relaxed(bool enable); void bpmp_clk_rate_get(); -bpmp_freq_t bpmp_clk_rate_set(bpmp_freq_t fid); +void bpmp_clk_rate_set(bpmp_freq_t fid); +void bpmp_state_set(bpmp_state_t state); void bpmp_usleep(u32 us); void bpmp_msleep(u32 ms); void bpmp_halt(); diff --git a/bdk/soc/ccplex.c b/bdk/soc/ccplex.c index 7d2f4b6..c01a892 100644 --- a/bdk/soc/ccplex.c +++ b/bdk/soc/ccplex.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,6 +15,7 @@ * along with this program. If not, see . */ +#include #include #include #include @@ -26,7 +27,9 @@ #include #include -void _ccplex_enable_power_t210() +#define CCPLEX_FLOWCTRL_POWERGATING 0 + +static void _ccplex_enable_power_t210() { // Configure GPIO5 and enable output in order to power CPU pmic. max77620_config_gpio(5, MAX77620_GPIO_OUTPUT_ENABLE); @@ -36,22 +39,34 @@ void _ccplex_enable_power_t210() // 1.0.0-3.x: MAX77621_T_JUNCTION_120 | MAX77621_CKKADV_TRIP_DISABLE | MAX77621_INDUCTOR_NOMINAL. max77621_config_default(REGULATOR_CPU0, MAX77621_CTRL_HOS_CFG); - // Set voltage and enable cores power. + // Set voltage and enable cluster power. max7762x_regulator_set_voltage(REGULATOR_CPU0, 950000); max7762x_regulator_enable(REGULATOR_CPU0, true); } -void _ccplex_enable_power_t210b01() +static void _ccplex_enable_power_t210b01() { - // Set voltage and enable cores power. + // Set voltage and enable cluster power. max7762x_regulator_set_voltage(REGULATOR_CPU1, 800000); max7762x_regulator_enable(REGULATOR_CPU1, true); } -void ccplex_boot_cpu0(u32 entry) +static void _ccplex_disable_power() +{ + // Disable cluster power. + if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210) + { + max7762x_regulator_enable(REGULATOR_CPU0, false); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_GPIO5, 0); + } + else + max7762x_regulator_enable(REGULATOR_CPU1, false); +} + +void ccplex_boot_cpu0(u32 entry, bool lock) { // Set ACTIVE_CLUSER to FAST. - FLOW_CTLR(FLOW_CTLR_BPMP_CLUSTER_CONTROL) &= 0xFFFFFFFE; + FLOW_CTLR(FLOW_CTLR_BPMP_CLUSTER_CONTROL) &= ~CLUSTER_CTRL_ACTIVE_SLOW; if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210) _ccplex_enable_power_t210(); @@ -61,13 +76,13 @@ void ccplex_boot_cpu0(u32 entry) clock_enable_pllx(); // Configure MSELECT source and enable clock to 102MHz. - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) & 0x1FFFFF00) | 6; - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = BIT(CLK_V_MSELECT); + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT) = (0 << 29) | CLK_SRC_DIV(4); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = BIT(CLK_V_MSELECT); // Configure initial CPU clock frequency and enable clock. CLOCK(CLK_RST_CONTROLLER_CCLK_BURST_POLICY) = 0x20008888; // PLLX_OUT0_LJ. - CLOCK(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER) = 0x80000000; - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = BIT(CLK_V_CPUG); + CLOCK(CLK_RST_CONTROLLER_SUPER_CCLK_DIVIDER) = BIT(31); // SUPER_CDIV_ENB. + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_SET) = BIT(CLK_V_CPUG); clock_enable_coresight(); @@ -81,28 +96,70 @@ void ccplex_boot_cpu0(u32 entry) // Enable CPU0 rail. pmc_enable_partition(POWER_RAIL_CE0, ENABLE); - // Request and wait for RAM repair. - FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) = 1; - while (!(FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) & 2)) + // Request and wait for RAM repair. Needed for the Fast cluster. + FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) = RAM_REPAIR_REQ; + while (!(FLOW_CTLR(FLOW_CTLR_RAM_REPAIR) & RAM_REPAIR_STS)) ; EXCP_VEC(EVP_CPU_RESET_VECTOR) = 0; // Set reset vector. - SB(SB_AA64_RESET_LOW) = entry | SB_AA64_RST_AARCH64_MODE_EN; + SB(SB_AA64_RESET_LOW) = entry | SB_AA64_RST_AARCH64_MODE_EN; SB(SB_AA64_RESET_HIGH) = 0; + // Non-secure reset vector write disable. - SB(SB_CSR) = SB_CSR_NS_RST_VEC_WR_DIS; - (void)SB(SB_CSR); + if (lock) + { + SB(SB_CSR) = SB_CSR_NS_RST_VEC_WR_DIS; + (void)SB(SB_CSR); + } // Tighten up the security aperture. // MC(MC_TZ_SECURITY_CTRL) = 1; // Clear MSELECT reset. - CLOCK(CLK_RST_CONTROLLER_RST_DEV_V_CLR) = BIT(CLK_V_MSELECT); + CLOCK(CLK_RST_CONTROLLER_RST_DEV_V_CLR) = BIT(CLK_V_MSELECT); // Clear NONCPU reset. - CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x20000000; + CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = BIT(29); // CLR_NONCPURESET. // Clear CPU0 reset. // < 5.x: 0x411F000F, Clear CPU{0,1,2,3} POR and CORE, CX0, L2, and DBG reset. - CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = 0x41010001; + CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR) = BIT(30) | BIT(24) | BIT(16) | BIT(0); +} + +void ccplex_powergate_cpu0() +{ +#if CCPLEX_FLOWCTRL_POWERGATING + // Halt CPU0. + FLOW_CTLR(FLOW_CTLR_HALT_CPU0_EVENTS) = HALT_MODE_STOP_UNTIL_IRQ; + + // Powergate cluster via flow control without waiting for WFI. + FLOW_CTLR(FLOW_CTLR_CPU0_CSR) = CSR_INTR_FLAG | CSR_EVENT_FLAG | CSR_ENABLE_EXT_CPU_RAIL | CSR_WAIT_WFI_NONE | CSR_ENABLE; + + // Wait for the rail power off to finish. + while((FLOW_CTLR(FLOW_CTLR_CPU_PWR_CSR) & CPU_PWR_RAIL_STS_MASK) != CPU_PWR_RAIL_OFF); + + // Set CPU0 to waitevent. + FLOW_CTLR(FLOW_CTLR_HALT_CPU0_EVENTS) = HALT_MODE_WAITEVENT; +#endif + + // Set CPU0 POR and CORE, CX0, L2, and DBG reset. + CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET) = BIT(30) | BIT(24) | BIT(16) | BIT(0); + // Set NONCPU reset. + CLOCK(CLK_RST_CONTROLLER_RST_CPUG_CMPLX_SET) = BIT(29); + // Set MSELECT reset. + CLOCK(CLK_RST_CONTROLLER_RST_DEV_V_SET) = BIT(CLK_V_MSELECT); + + // Disable CE0. + pmc_enable_partition(POWER_RAIL_CE0, DISABLE); + // Disable cluster 0 non-CPU. + pmc_enable_partition(POWER_RAIL_C0NC, DISABLE); + // Disable CPU rail. + pmc_enable_partition(POWER_RAIL_CRAIL, DISABLE); + + clock_disable_coresight(); + + // Clear out MSELECT and CPU clocks. + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_V_CLR) = BIT(CLK_V_MSELECT) | BIT(CLK_V_CPUG); + + _ccplex_disable_power(); } diff --git a/bdk/soc/ccplex.h b/bdk/soc/ccplex.h index fb5be92..496da43 100644 --- a/bdk/soc/ccplex.h +++ b/bdk/soc/ccplex.h @@ -19,6 +19,7 @@ #include -void ccplex_boot_cpu0(u32 entry); +void ccplex_boot_cpu0(u32 entry, bool lock); +void ccplex_powergate_cpu0(); #endif diff --git a/bdk/soc/clock.c b/bdk/soc/clock.c index f4d9e92..b3a48fa 100644 --- a/bdk/soc/clock.c +++ b/bdk/soc/clock.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,11 +15,13 @@ * along with this program. If not, see . */ +#include #include #include +#include +#include #include #include -#include typedef struct _clock_osc_t { @@ -38,69 +40,88 @@ static const clock_osc_t _clock_osc_cnt[] = { { 48000, 2836, 3023 } }; -/* clock_t: reset, enable, source, index, clk_src, clk_div */ +/* clk_rst_t: reset, enable, source, index, clk_src, clk_div */ -static const clock_t _clock_uart[] = { - { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA, CLK_L_UARTA, 0, 2 }, - { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB, CLK_L_UARTB, 0, 2 }, - { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC, CLK_H_UARTC, 0, 2 }, - { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_UARTD, CLK_U_UARTD, 0, 2 }, - { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE, CLK_Y_UARTAPE, 0, 2 } +static const clk_rst_t _clock_uart[] = { + { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA, CLK_L_UARTA, 0, CLK_SRC_DIV(2) }, + { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB, CLK_L_UARTB, 0, CLK_SRC_DIV(2) }, + { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC, CLK_H_UARTC, 0, CLK_SRC_DIV(2) }, + { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_UARTD, CLK_U_UARTD, 0, CLK_SRC_DIV(2) }, + { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE, CLK_Y_UARTAPE, 0, CLK_SRC_DIV(2) } }; //I2C default parameters - TLOW: 4, THIGH: 2, DEBOUNCE: 0, FM_DIV: 26. -static const clock_t _clock_i2c[] = { - { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, CLK_L_I2C1, 0, 19 }, //20.4MHz -> 100KHz - { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2, CLK_H_I2C2, 0, 4 }, //81.6MHz -> 400KHz - { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_I2C3, CLK_U_I2C3, 0, 4 }, //81.6MHz -> 400KHz - { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_I2C4, CLK_V_I2C4, 0, 19 }, //20.4MHz -> 100KHz - { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, CLK_H_I2C5, 0, 4 }, //81.6MHz -> 400KHz - { CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_I2C6, CLK_X_I2C6, 0, 19 } //20.4MHz -> 100KHz +static const clk_rst_t _clock_i2c[] = { + { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, CLK_L_I2C1, 0, CLK_SRC_DIV(10.5) }, //20.4MHz -> 100KHz + { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C2, CLK_H_I2C2, 0, CLK_SRC_DIV(3) }, //81.6MHz -> 400KHz + { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_I2C3, CLK_U_I2C3, 0, CLK_SRC_DIV(3) }, //81.6MHz -> 400KHz + { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_I2C4, CLK_V_I2C4, 0, CLK_SRC_DIV(10.5) }, //20.4MHz -> 100KHz + { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, CLK_H_I2C5, 0, CLK_SRC_DIV(3) }, //81.6MHz -> 400KHz + { CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_I2C6, CLK_X_I2C6, 0, CLK_SRC_DIV(10.5) } //20.4MHz -> 100KHz }; -static clock_t _clock_se = { - CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, CLK_V_SE, 0, 0 // 408MHz. +static clk_rst_t _clock_se = { + CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_SE, CLK_V_SE, 0, CLK_SRC_DIV(1) // 408MHz. Default: 408MHz. Max: 627.2 MHz. +}; +static clk_rst_t _clock_tzram = { + CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE, CLK_V_TZRAM, 0, CLK_SRC_DIV(1) +}; +static clk_rst_t _clock_host1x = { + CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, CLK_L_HOST1X, 4, CLK_SRC_DIV(2.5) // 163.2MHz. Max: 408MHz. +}; +static clk_rst_t _clock_tsec = { + CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, CLK_U_TSEC, 0, CLK_SRC_DIV(2) // 204MHz. Max: 408MHz. +}; +static clk_rst_t _clock_nvdec = { + CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC, CLK_Y_NVDEC, 4, CLK_SRC_DIV(1) // 408 MHz. Max: 716.8/979.2MHz. +}; +static clk_rst_t _clock_nvjpg = { + CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG, CLK_Y_NVJPG, 4, CLK_SRC_DIV(1) // 408 MHz. Max: 627.2/652.8MHz. +}; +static clk_rst_t _clock_vic = { + CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_VIC, CLK_X_VIC, 2, CLK_SRC_DIV(1) // 408 MHz. Max: 627.2/652.8MHz. +}; +static clk_rst_t _clock_sor_safe = { + CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE, CLK_Y_SOR_SAFE, 0, CLK_SRC_DIV(1) +}; +static clk_rst_t _clock_sor0 = { + CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NOT_USED, CLK_X_SOR0, 0, CLK_SRC_DIV(1) +}; +static clk_rst_t _clock_sor1 = { + CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, CLK_X_SOR1, 0, CLK_SRC_DIV(2) // 204MHz. +}; +static clk_rst_t _clock_kfuse = { + CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_KFUSE, 0, CLK_SRC_DIV(1) +}; +static clk_rst_t _clock_cl_dvfs = { + CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE, CLK_W_DVFS, 0, CLK_SRC_DIV(1) +}; +static clk_rst_t _clock_coresight = { + CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, CLK_U_CSITE, 0, CLK_SRC_DIV(3) // 136MHz. +}; +static clk_rst_t _clock_pwm = { + CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, CLK_L_PWM, 6, CLK_SRC_DIV(3) // Fref: 6.4MHz. HOS: PLLP / 54 = 7.55MHz. +}; +static clk_rst_t _clock_sdmmc_legacy_tm = { + CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM, CLK_Y_SDMMC_LEGACY_TM, 4, CLK_SRC_DIV(34) // 12MHz. +}; +static clk_rst_t _clock_apbdma = { + CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_APBDMA, 0, CLK_SRC_DIV(1) // Max: 204MHz. +}; +static clk_rst_t _clock_ahbdma = { + CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_AHBDMA, 0, CLK_SRC_DIV(1) +}; +static clk_rst_t _clock_actmon = { + CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON, CLK_V_ACTMON, 6, CLK_SRC_DIV(1) // 19.2MHz. +}; +static clk_rst_t _clock_extperiph1 = { + CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1, CLK_V_EXTPERIPH1, 0, CLK_SRC_DIV(1) +}; +static clk_rst_t _clock_extperiph2 = { + CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2, CLK_V_EXTPERIPH2, 2, CLK_SRC_DIV(102) // 4.0MHz }; -static clock_t _clock_tzram = { - CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, CLK_NO_SOURCE, CLK_V_TZRAM, 0, 0 -}; - -static clock_t _clock_host1x = { - CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, CLK_L_HOST1X, 4, 3 // 163.2MHz. -}; -static clock_t _clock_tsec = { - CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, CLK_U_TSEC, 0, 2 // 204MHz. -}; -static clock_t _clock_sor_safe = { - CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_NO_SOURCE, CLK_Y_SOR_SAFE, 0, 0 -}; -static clock_t _clock_sor0 = { - CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_NOT_USED, CLK_X_SOR0, 0, 0 -}; -static clock_t _clock_sor1 = { - CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, CLK_X_SOR1, 0, 2 //204MHz. -}; -static clock_t _clock_kfuse = { - CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_NO_SOURCE, CLK_H_KFUSE, 0, 0 -}; - -static clock_t _clock_cl_dvfs = { - CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_NO_SOURCE, CLK_W_DVFS, 0, 0 -}; -static clock_t _clock_coresight = { - CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, CLK_U_CSITE, 0, 4 // 136MHz. -}; - -static clock_t _clock_pwm = { - CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_PWM, CLK_L_PWM, 6, 4 // Fref: 6.4MHz. HOS: PLLP / 54 = 7.55MHz. -}; - -static clock_t _clock_sdmmc_legacy_tm = { - CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM, CLK_Y_SDMMC_LEGACY_TM, 4, 66 -}; - -void clock_enable(const clock_t *clk) +void clock_enable(const clk_rst_t *clk) { // Put clock into reset. CLOCK(clk->reset) = (CLOCK(clk->reset) & ~BIT(clk->index)) | BIT(clk->index); @@ -108,7 +129,7 @@ void clock_enable(const clock_t *clk) CLOCK(clk->enable) &= ~BIT(clk->index); // Configure clock source if required. if (clk->source) - CLOCK(clk->source) = clk->clk_div | (clk->clk_src << 29); + CLOCK(clk->source) = clk->clk_div | (clk->clk_src << 29u); // Enable. CLOCK(clk->enable) = (CLOCK(clk->enable) & ~BIT(clk->index)) | BIT(clk->index); usleep(2); @@ -117,7 +138,7 @@ void clock_enable(const clock_t *clk) CLOCK(clk->reset) &= ~BIT(clk->index); } -void clock_disable(const clock_t *clk) +void clock_disable(const clk_rst_t *clk) { // Put clock into reset. CLOCK(clk->reset) = (CLOCK(clk->reset) & ~BIT(clk->index)) | BIT(clk->index); @@ -133,7 +154,13 @@ void clock_enable_fuse(bool enable) void clock_enable_uart(u32 idx) { + // Ease the stress to APB. + bpmp_clk_rate_relaxed(true); + clock_enable(&_clock_uart[idx]); + + // Restore OC. + bpmp_clk_rate_relaxed(false); } void clock_disable_uart(u32 idx) @@ -147,11 +174,13 @@ int clock_uart_use_src_div(u32 idx, u32 baud) { u32 clk_src_div = CLOCK(_clock_uart[idx].source) & 0xE0000000; - if (baud == 1000000) - CLOCK(_clock_uart[idx].source) = clk_src_div | UART_SRC_CLK_DIV_EN | 49; + if (baud == 3000000) + CLOCK(_clock_uart[idx].source) = clk_src_div | UART_SRC_CLK_DIV_EN | CLK_SRC_DIV(8.5); + else if (baud == 1000000) + CLOCK(_clock_uart[idx].source) = clk_src_div | UART_SRC_CLK_DIV_EN | CLK_SRC_DIV(25.5); else { - CLOCK(_clock_uart[idx].source) = clk_src_div | 2; + CLOCK(_clock_uart[idx].source) = clk_src_div | CLK_SRC_DIV(2); return 1; } @@ -203,6 +232,42 @@ void clock_disable_tsec() clock_disable(&_clock_tsec); } +void clock_enable_nvdec() +{ + clock_enable(&_clock_nvdec); +} + +void clock_disable_nvdec() +{ + clock_disable(&_clock_nvdec); +} + +void clock_enable_nvjpg() +{ + clock_enable(&_clock_nvjpg); +} + +void clock_disable_nvjpg() +{ + clock_disable(&_clock_nvjpg); +} + +void clock_enable_vic() +{ + // Ease the stress to APB. + bpmp_clk_rate_relaxed(true); + + clock_enable(&_clock_vic); + + // Restore sys clock. + bpmp_clk_rate_relaxed(false); +} + +void clock_disable_vic() +{ + clock_disable(&_clock_vic); +} + void clock_enable_sor_safe() { clock_enable(&_clock_sor_safe); @@ -271,7 +336,13 @@ void clock_disable_coresight() void clock_enable_pwm() { + // Ease the stress to APB. + bpmp_clk_rate_relaxed(true); + clock_enable(&_clock_pwm); + + // Restore OC. + bpmp_clk_rate_relaxed(false); } void clock_disable_pwm() @@ -279,6 +350,84 @@ void clock_disable_pwm() clock_disable(&_clock_pwm); } +void clock_enable_apbdma() +{ + clock_enable(&_clock_apbdma); +} + +void clock_disable_apbdma() +{ + clock_disable(&_clock_apbdma); +} + +void clock_enable_ahbdma() +{ + clock_enable(&_clock_ahbdma); +} + +void clock_disable_ahbdma() +{ + clock_disable(&_clock_ahbdma); +} + +void clock_enable_actmon() +{ + clock_enable(&_clock_actmon); +} + +void clock_disable_actmon() +{ + clock_disable(&_clock_actmon); +} + +void clock_enable_extperiph1() +{ + clock_enable(&_clock_extperiph1); + + PMC(APBDEV_PMC_CLK_OUT_CNTRL) |= PMC_CLK_OUT_CNTRL_CLK1_SRC_SEL(OSC_CAR) | PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN; + usleep(5); +} + +void clock_disable_extperiph1() +{ + PMC(APBDEV_PMC_CLK_OUT_CNTRL) &= ~((PMC_CLK_OUT_CNTRL_CLK1_SRC_SEL(OSC_CAR)) | PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN); + clock_disable(&_clock_extperiph1); +} + +void clock_enable_extperiph2() +{ + clock_enable(&_clock_extperiph2); + + PMC(APBDEV_PMC_CLK_OUT_CNTRL) |= PMC_CLK_OUT_CNTRL_CLK2_SRC_SEL(OSC_CAR) | PMC_CLK_OUT_CNTRL_CLK2_FORCE_EN; + usleep(5); +} + +void clock_disable_extperiph2() +{ + PMC(APBDEV_PMC_CLK_OUT_CNTRL) &= ~((PMC_CLK_OUT_CNTRL_CLK2_SRC_SEL(OSC_CAR)) | PMC_CLK_OUT_CNTRL_CLK2_FORCE_EN); + clock_disable(&_clock_extperiph2); +} + +void clock_enable_plld(u32 divp, u32 divn, bool lowpower, bool tegra_t210) +{ + u32 plld_div = (divp << 20) | (divn << 11) | 1; + + // N divider is fractional, so N = DIVN + 1/2 + PLLD_SDM_DIN/8192. + u32 misc = 0x2D0000 | 0xFC00; // Clock enable and PLLD_SDM_DIN: -1024 -> DIVN + 0.375. + if (lowpower && tegra_t210) + misc = 0x2D0000 | 0x0AAA; // Clock enable and PLLD_SDM_DIN: 2730 -> DIVN + 0.833. + + // Set DISP1 clock source. + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_DISP1) = 2 << 29u; // PLLD_OUT0. + + // Set dividers and enable PLLD. + CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) = PLLCX_BASE_ENABLE | PLLCX_BASE_LOCK | plld_div; + CLOCK(CLK_RST_CONTROLLER_PLLD_MISC1) = tegra_t210 ? 0x20 : 0; // Keep default PLLD_SETUP. + + // Set PLLD_SDM_DIN and enable PLLD to DSI pads. + CLOCK(CLK_RST_CONTROLLER_PLLD_MISC) = misc; +} + void clock_enable_pllx() { // Configure and enable PLLX if disabled. @@ -315,7 +464,7 @@ void clock_enable_pllc(u32 divn) // Take PLLC out of reset and set basic misc parameters. CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) = - ((CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) & 0xFFF0000F) & ~PLLC_MISC_RESET) | (0x80000 << 4); // PLLC_EXT_FRU. + ((CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) & 0xFFF0000F) & ~PLLC_MISC_RESET) | (0x8000 << 4); // PLLC_EXT_FRU. CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_2) |= 0xF0 << 8; // PLLC_FLL_LD_MEM. // Disable PLL and IDDQ in case they are on. @@ -332,21 +481,21 @@ void clock_enable_pllc(u32 divn) ; // Disable PLLC_OUT1, enable reset and set div to 1.5. - CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) = BIT(8); + CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) = 1 << 8; // Enable PLLC_OUT1 and bring it out of reset. - CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) |= (PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR); + CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) |= PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR; msleep(1); // Wait a bit for PLL to stabilize. } void clock_disable_pllc() { // Disable PLLC and PLLC_OUT1. - CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) &= ~(PLLC_OUT1_CLKEN | PLLC_OUT1_RSTN_CLR); + CLOCK(CLK_RST_CONTROLLER_PLLC_OUT) &= ~PLLC_OUT1_RSTN_CLR; + CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) = PLLC_MISC_RESET; CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) &= ~PLLCX_BASE_ENABLE; - CLOCK(CLK_RST_CONTROLLER_PLLC_BASE) |= PLLCX_BASE_REF_DIS; CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_1) |= PLLC_MISC1_IDDQ; - CLOCK(CLK_RST_CONTROLLER_PLLC_MISC) |= PLLC_MISC_RESET; + CLOCK(CLK_RST_CONTROLLER_PLLC_MISC_2) &= ~(0xFF << 8); // PLLC_FLL_LD_MEM. usleep(10); } @@ -371,7 +520,7 @@ static void _clock_enable_pllc4(u32 mask) usleep(10); // Set PLLC4 dividers. - CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) = (104 << 8) | 4; // DIVM: 4, DIVP: 1. + CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) = (0 << 19) | (104 << 8) | 4; // DIVP: 1, DIVN: 104, DIVM: 4. 998MHz OUT0, 199MHz OUT2. // Enable PLLC4 and wait for Phase and Frequency lock. CLOCK(CLK_RST_CONTROLLER_PLLC4_BASE) |= PLLCX_BASE_ENABLE; @@ -409,9 +558,9 @@ void clock_enable_pllu() CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) = pllu_cfg | PLLCX_BASE_ENABLE; // Enable. // Wait for PLL to stabilize. - u32 timeout = (u32)TMR(TIMERUS_CNTR_1US) + 1300; + u32 timeout = get_tmr_us() + 1300; while (!(CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) & PLLCX_BASE_LOCK)) // PLL_LOCK. - if ((u32)TMR(TIMERUS_CNTR_1US) > timeout) + if (get_tmr_us() > timeout) break; usleep(10); @@ -421,9 +570,9 @@ void clock_enable_pllu() void clock_disable_pllu() { - CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) &= ~0x2E00000; // Disable PLLU USB/HSIC/ICUSB/48M. - CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) &= ~0x40000000; // Disable PLLU. - CLOCK(CLK_RST_CONTROLLER_PLLU_MISC) &= ~0x20000000; // Enable reference clock. + CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) &= ~0x2E00000; // Disable PLLU USB/HSIC/ICUSB/48M. + CLOCK(CLK_RST_CONTROLLER_PLLU_BASE) &= ~BIT(30); // Disable PLLU. + CLOCK(CLK_RST_CONTROLLER_PLLU_MISC) &= ~BIT(29); // Enable reference clock. } void clock_enable_utmipll() @@ -552,7 +701,7 @@ static void _clock_sdmmc_clear_enable(u32 id) static void _clock_sdmmc_config_legacy_tm() { - clock_t *clk = &_clock_sdmmc_legacy_tm; + const clk_rst_t *clk = &_clock_sdmmc_legacy_tm; if (!(CLOCK(clk->enable) & BIT(clk->index))) clock_enable(clk); } @@ -567,6 +716,7 @@ static clock_sdmmc_t _clock_sdmmc_table[4] = { 0 }; #define SDMMC_CLOCK_SRC_PLLP_OUT0 0x0 #define SDMMC_CLOCK_SRC_PLLC4_OUT2 0x3 +#define SDMMC_CLOCK_SRC_PLLC4_OUT0 0x7 #define SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ 0x1 static int _clock_sdmmc_config_clock_host(u32 *pclock, u32 id, u32 val) @@ -582,81 +732,90 @@ static int _clock_sdmmc_config_clock_host(u32 *pclock, u32 id, u32 val) { case 25000: *pclock = 24728; - divisor = 31; // 16.5 div. + divisor = CLK_SRC_DIV(16.5); break; + case 26000: *pclock = 25500; - divisor = 30; // 16 div. - break; - case 40800: - *pclock = 40800; - divisor = 18; // 10 div. + divisor = CLK_SRC_DIV(16); break; + case 50000: *pclock = 48000; - divisor = 15; // 8.5 div. + divisor = CLK_SRC_DIV(8.5); break; + case 52000: *pclock = 51000; - divisor = 14; // 8 div. + divisor = CLK_SRC_DIV(8); break; + + case 82000: + *pclock = 81600; + divisor = CLK_SRC_DIV(5); + break; + case 100000: source = SDMMC_CLOCK_SRC_PLLC4_OUT2; *pclock = 99840; - divisor = 2; // 2 div. + divisor = CLK_SRC_DIV(2); break; + case 164000: *pclock = 163200; - divisor = 3; // 2.5 div. + divisor = CLK_SRC_DIV(2.5); break; - case 200000: // 240MHz evo+. + + case 200000: switch (id) { case SDMMC_1: - source = SDMMC_CLOCK_SRC_PLLC4_OUT2; - break; - case SDMMC_2: - source = SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ; - break; case SDMMC_3: source = SDMMC_CLOCK_SRC_PLLC4_OUT2; break; + case SDMMC_2: case SDMMC_4: - source = SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ; + source = SDMMC4_CLOCK_SRC_PLLC4_OUT2_LJ; // div is ignored. break; } *pclock = 199680; - divisor = 0; // 1 div. + divisor = CLK_SRC_DIV(1); break; - default: - *pclock = 24728; - divisor = 31; // 16.5 div. + +#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT + case 400000: + source = SDMMC_CLOCK_SRC_PLLC4_OUT0; + *pclock = 399360; + divisor = CLK_SRC_DIV(2.5); + break; +#endif } _clock_sdmmc_table[id].clock = val; _clock_sdmmc_table[id].real_clock = *pclock; // Enable PLLC4 if in use by any SDMMC. - if (source) + if (source != SDMMC_CLOCK_SRC_PLLP_OUT0) _clock_enable_pllc4(BIT(id)); // Set SDMMC legacy timeout clock. _clock_sdmmc_config_legacy_tm(); // Set SDMMC clock. + u32 src_div = (source << 29u) | divisor; switch (id) { case SDMMC_1: - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1) = (source << 29) | divisor; + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1) = src_div; break; case SDMMC_2: - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2) = (source << 29) | divisor; + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2) = src_div; break; case SDMMC_3: - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3) = (source << 29) | divisor; + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3) = src_div; break; case SDMMC_4: - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4) = (source << 29) | divisor; + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4) = src_div; break; } @@ -686,54 +845,71 @@ void clock_sdmmc_get_card_clock_div(u32 *pclock, u16 *pdivisor, u32 type) // Get Card clock divisor. switch (type) { - case SDHCI_TIMING_MMC_ID: // Actual IO Freq: 380.59 KHz. + case SDHCI_TIMING_MMC_ID: // Actual card clock: 386.36 KHz. *pclock = 26000; *pdivisor = 66; break; + case SDHCI_TIMING_MMC_LS26: *pclock = 26000; *pdivisor = 1; break; + case SDHCI_TIMING_MMC_HS52: *pclock = 52000; *pdivisor = 1; break; + case SDHCI_TIMING_MMC_HS200: case SDHCI_TIMING_MMC_HS400: case SDHCI_TIMING_UHS_SDR104: *pclock = 200000; *pdivisor = 1; break; - case SDHCI_TIMING_SD_ID: // Actual IO Freq: 380.43 KHz. + + case SDHCI_TIMING_SD_ID: // Actual card clock: 386.38 KHz. *pclock = 25000; *pdivisor = 64; break; + case SDHCI_TIMING_SD_DS12: case SDHCI_TIMING_UHS_SDR12: *pclock = 25000; *pdivisor = 1; break; + case SDHCI_TIMING_SD_HS25: case SDHCI_TIMING_UHS_SDR25: *pclock = 50000; *pdivisor = 1; break; + case SDHCI_TIMING_UHS_SDR50: *pclock = 100000; *pdivisor = 1; break; + case SDHCI_TIMING_UHS_SDR82: *pclock = 164000; *pdivisor = 1; break; - case SDHCI_TIMING_UHS_DDR50: - *pclock = 40800; - *pdivisor = 1; + + case SDHCI_TIMING_UHS_DDR50: // Actual card clock: 40.80 MHz. + *pclock = 82000; + *pdivisor = 2; break; - case SDHCI_TIMING_MMC_HS102: // Actual IO Freq: 99.84 MHz. + + case SDHCI_TIMING_MMC_HS100: // Actual card clock: 99.84 MHz. *pclock = 200000; *pdivisor = 2; break; + +#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT + case SDHCI_TIMING_UHS_DDR200: // Actual card clock: 199.68 KHz. + *pclock = 400000; + *pdivisor = 2; + break; +#endif } } @@ -752,7 +928,8 @@ void clock_sdmmc_enable(u32 id, u32 val) _clock_sdmmc_config_clock_host(&clock, id, val); _clock_sdmmc_set_enable(id); _clock_sdmmc_is_reset(id); - usleep((100000 + clock - 1) / clock); + // Wait 100 cycles for reset and for clocks to stabilize. + usleep((100 * 1000 + clock - 1) / clock); _clock_sdmmc_clear_reset(id); _clock_sdmmc_is_reset(id); } diff --git a/bdk/soc/clock.h b/bdk/soc/clock.h index 32afe8d..14d1df7 100644 --- a/bdk/soc/clock.h +++ b/bdk/soc/clock.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -47,6 +47,7 @@ #define CLK_RST_CONTROLLER_PLLM_MISC1 0x98 #define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C #define CLK_RST_CONTROLLER_PLLP_BASE 0xA0 +#define CLK_RST_CONTROLLER_PLLP_OUTB 0xA8 #define CLK_RST_CONTROLLER_PLLA_BASE 0xB0 #define CLK_RST_CONTROLLER_PLLA_OUT 0xB4 #define CLK_RST_CONTROLLER_PLLA_MISC1 0xB8 @@ -117,7 +118,10 @@ #define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3A4 #define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT 0x3B4 #define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 0x3C4 +#define CLK_RST_CONTROLLER_CLK_SOURCE_AHUB 0x3D0 +#define CLK_RST_CONTROLLER_CLK_SOURCE_ACTMON 0x3E8 #define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 0x3EC +#define CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 0x3F0 #define CLK_RST_CONTROLLER_CLK_SOURCE_SYS 0x400 #define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410 #define CLK_RST_CONTROLLER_CLK_SOURCE_SE 0x42C @@ -146,6 +150,7 @@ #define CLK_RST_CONTROLLER_PLLC_MISC_2 0x5D0 #define CLK_RST_CONTROLLER_PLLC4_OUT 0x5E4 #define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8 +#define CLK_RST_CONTROLLER_PLLMB_MISC1 0x5EC #define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS 0x608 #define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_CORE_DEV 0x60C #define CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS 0x610 @@ -153,8 +158,12 @@ #define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 0x65C #define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664 #define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL 0x66C +#define CLK_RST_CONTROLLER_CLK_SOURCE_VIC 0x678 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM 0x694 +#define CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC 0x698 +#define CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG 0x69C #define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC 0x6A0 +#define CLK_RST_CONTROLLER_CLK_SOURCE_APE 0x6C0 #define CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK 0x6CC #define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER 0x704 #define CLK_RST_CONTROLLER_CLK_SOURCE_UARTAPE 0x710 @@ -191,6 +200,9 @@ #define UTMIPLL_LOCK BIT(31) +/*! Clock source */ +#define CLK_SRC_DIV(d) ((d) ? ((u32)(((d) - 1) * 2)) : 0) + /*! PTO_CLK_CNT */ #define PTO_REF_CLK_WIN_CFG_MASK 0xF #define PTO_REF_CLK_WIN_CFG_16P 0xF @@ -220,138 +232,232 @@ /*! PTO IDs. */ typedef enum _clock_pto_id_t { - CLK_PTO_PCLK_SYS = 0x06, - CLK_PTO_HCLK_SYS = 0x07, + CLK_PTO_PCLK_SYS = 0x06, + CLK_PTO_HCLK_SYS = 0x07, + CLK_PTO_DMIC1 = 0x08, + CLK_PTO_DMIC2 = 0x09, + CLK_PTO_HDMI_SLOWCLK_DIV2 = 0x0A, + CLK_PTO_JTAG_REG = 0x0B, + CLK_PTO_UTMIP_240_A = 0x0C, + CLK_PTO_UTMIP_240_B = 0x0D, - CLK_PTO_UTMIP_240 = 0x0C, + CLK_PTO_CCLK_G = 0x12, + CLK_PTO_CCLK_G_DIV2 = 0x13, + CLK_PTO_MIPIBIF = 0x14, - CLK_PTO_CCLK_G = 0x12, - CLK_PTO_CCLK_G_DIV2 = 0x13, + CLK_PTO_SPI1 = 0x17, + CLK_PTO_SPI2 = 0x18, + CLK_PTO_SPI3 = 0x19, + CLK_PTO_SPI4 = 0x1A, + CLK_PTO_MAUD = 0x1B, + CLK_PTO_SCLK = 0x1C, - CLK_PTO_SPI1 = 0x17, - CLK_PTO_SPI2 = 0x18, - CLK_PTO_SPI3 = 0x19, - CLK_PTO_SPI4 = 0x1A, - CLK_PTO_MAUD = 0x1B, - CLK_PTO_SCLK = 0x1C, + CLK_PTO_SDMMC1 = 0x20, + CLK_PTO_SDMMC2 = 0x21, + CLK_PTO_SDMMC3 = 0x22, + CLK_PTO_SDMMC4 = 0x23, + CLK_PTO_EMC = 0x24, - CLK_PTO_SDMMC1 = 0x20, - CLK_PTO_SDMMC2 = 0x21, - CLK_PTO_SDMMC3 = 0x22, - CLK_PTO_SDMMC4 = 0x23, - CLK_PTO_EMC = 0x24, + CLK_PTO_DMIC3 = 0x2A, + CLK_PTO_CCLK_LP = 0x2B, + CLK_PTO_CCLK_LP_DIV2 = 0x2C, - CLK_PTO_CCLK_LP = 0x2B, - CLK_PTO_CCLK_LP_DIV2 = 0x2C, + CLK_PTO_MSELECT = 0x2F, - CLK_PTO_MSELECT = 0x2F, + CLK_PTO_VI_SENSOR2 = 0x33, + CLK_PTO_VI_SENSOR = 0x34, + CLK_PTO_VIC = 0x35, + CLK_PTO_VIC_SKIP = 0x36, + CLK_PTO_ISP_SKIP = 0x37, + CLK_PTO_ISPB_SE2_SKIP = 0x38, + CLK_PTO_NVDEC_SKIP = 0x39, + CLK_PTO_NVENC_SKIP = 0x3A, + CLK_PTO_NVJPG_SKIP = 0x3B, + CLK_PTO_TSEC_SKIP = 0x3C, + CLK_PTO_TSECB_SKIP = 0x3D, + CLK_PTO_SE_SKIP = 0x3E, + CLK_PTO_VI_SKIP = 0x3F, - CLK_PTO_VIC = 0x36, + CLK_PTO_PLLX_OBS = 0x40, + CLK_PTO_PLLC_OBS = 0x41, + CLK_PTO_PLLM_OBS = 0x42, + CLK_PTO_PLLP_OBS = 0x43, + CLK_PTO_PLLA_OBS = 0x44, + CLK_PTO_PLLMB_OBS = 0x45, + CLK_PTO_SATA_OOB = 0x46, - CLK_PTO_NVDEC = 0x39, + CLK_PTO_FCPU_DVFS_DIV12_CPU = 0x48, - CLK_PTO_NVENC = 0x3A, - CLK_PTO_NVJPG = 0x3B, - CLK_PTO_TSEC = 0x3C, - CLK_PTO_TSECB = 0x3D, - CLK_PTO_SE = 0x3E, + CLK_PTO_EQOS_AXI = 0x4C, + CLK_PTO_EQOS_PTP_REF = 0x4D, + CLK_PTO_EQOS_TX = 0x4E, + CLK_PTO_EQOS_RX = 0x4F, - CLK_PTO_DSIA_LP = 0x62, + CLK_PTO_CILAB = 0x52, + CLK_PTO_CILCD = 0x53, - CLK_PTO_ISP = 0x64, - CLK_PTO_MC = 0x6A, + CLK_PTO_CILEF = 0x55, + CLK_PTO_PLLA1_PTO_OBS = 0x56, + CLK_PTO_PLLC4_PTO_OBS = 0x57, - CLK_PTO_ACTMON = 0x6B, - CLK_PTO_CSITE = 0x6C, + CLK_PTO_PLLC2_PTO_OBS = 0x59, + CLK_PTO_PLLC3_PTO_OBS = 0x5B, - CLK_PTO_HOST1X = 0x6F, + CLK_PTO_DSIA_LP = 0x62, + CLK_PTO_DSIB_LP = 0x63, + CLK_PTO_ISP = 0x64, + CLK_PTO_PEX_PAD = 0x65, - CLK_PTO_SE_2 = 0x74, // Same as CLK_PTO_SE. - CLK_PTO_SOC_THERM = 0x75, + CLK_PTO_MC = 0x6A, - CLK_PTO_TSEC_2 = 0x77, // Same as CLK_PTO_TSEC. + CLK_PTO_ACTMON = 0x6B, + CLK_PTO_CSITE = 0x6C, + CLK_PTO_VI_I2C = 0x6D, - CLK_PTO_ACLK = 0x7C, - CLK_PTO_QSPI = 0x7D, + CLK_PTO_HOST1X = 0x6F, - CLK_PTO_I2S1 = 0x80, - CLK_PTO_I2S2 = 0x81, - CLK_PTO_I2S3 = 0x82, - CLK_PTO_I2S4 = 0x83, - CLK_PTO_I2S5 = 0x84, - CLK_PTO_AHUB = 0x85, - CLK_PTO_APE = 0x86, + CLK_PTO_QSPI_2X = 0x71, + CLK_PTO_NVDEC = 0x72, + CLK_PTO_NVJPG = 0x73, + CLK_PTO_SE = 0x74, + CLK_PTO_SOC_THERM = 0x75, - CLK_PTO_DVFS_SOC = 0x88, - CLK_PTO_DVFS_REF = 0x89, + CLK_PTO_TSEC = 0x77, + CLK_PTO_TSECB = 0x78, + CLK_PTO_VI = 0x79, + CLK_PTO_LA = 0x7A, + CLK_PTO_SCLK_SKIP = 0x7B, - CLK_PTO_SPDIF = 0x8F, - CLK_PTO_SPDIF_IN = 0x90, + CLK_PTO_ADSP_SKIP = 0x7C, + CLK_PTO_QSPI = 0x7D, + + CLK_PTO_SDMMC2_SHAPER = 0x7E, + CLK_PTO_SDMMC4_SHAPER = 0x7F, + CLK_PTO_I2S1 = 0x80, + CLK_PTO_I2S2 = 0x81, + CLK_PTO_I2S3 = 0x82, + CLK_PTO_I2S4 = 0x83, + CLK_PTO_I2S5 = 0x84, + CLK_PTO_AHUB = 0x85, + CLK_PTO_APE = 0x86, + + CLK_PTO_DVFS_SOC = 0x88, + CLK_PTO_DVFS_REF = 0x89, + CLK_PTO_ADSP_CLK = 0x8A, + CLK_PTO_ADSP_DIV2_CLK = 0x8B, + + CLK_PTO_SPDIF_OUT = 0x8F, + CLK_PTO_SPDIF_IN = 0x90, CLK_PTO_UART_FST_MIPI_CAL = 0x91, + CLK_PTO_SYS2HSIO_SATA_CLK = 0x92, + CLK_PTO_PWM = 0x93, + CLK_PTO_I2C1 = 0x94, + CLK_PTO_I2C2 = 0x95, + CLK_PTO_I2C3 = 0x96, + CLK_PTO_I2C4 = 0x97, + CLK_PTO_I2C5 = 0x98, + CLK_PTO_I2C6 = 0x99, + CLK_PTO_I2C_SLOW = 0x9A, + CLK_PTO_UARTAPE = 0x9B, - CLK_PTO_PWM = 0x93, - CLK_PTO_I2C1 = 0x94, - CLK_PTO_I2C2 = 0x95, - CLK_PTO_I2C3 = 0x96, - CLK_PTO_I2C4 = 0x97, - CLK_PTO_I2C5 = 0x98, - CLK_PTO_I2C6 = 0x99, - CLK_PTO_I2C_SLOW = 0x9A, - CLK_PTO_UARTAPE = 0x9B, + CLK_PTO_EXTPERIPH1 = 0x9D, + CLK_PTO_EXTPERIPH2 = 0x9E, + CLK_PTO_EXTPERIPH3 = 0x9F, + CLK_PTO_ENTROPY = 0xA0, + CLK_PTO_UARTA = 0xA1, + CLK_PTO_UARTB = 0xA2, + CLK_PTO_UARTC = 0xA3, + CLK_PTO_UARTD = 0xA4, + CLK_PTO_OWR = 0xA5, + CLK_PTO_TSENSOR = 0xA6, + CLK_PTO_HDA2CODEC_2X = 0xA7, + CLK_PTO_HDA = 0xA8, + CLK_PTO_EMC_LATENCY = 0xA9, + CLK_PTO_EMC_DLL = 0xAA, + CLK_PTO_SDMMC_LEGACY_TM = 0xAB, + CLK_PTO_DBGAPB = 0xAC, - CLK_PTO_EXTPERIPH1 = 0x9D, - CLK_PTO_EXTPERIPH2 = 0x9E, + CLK_PTO_SOR0 = 0xC0, + CLK_PTO_SOR1 = 0xC1, + CLK_PTO_HDMI = 0xC2, - CLK_PTO_ENTROPY = 0xA0, - CLK_PTO_UARTA = 0xA1, - CLK_PTO_UARTB = 0xA2, - CLK_PTO_UARTC = 0xA3, - CLK_PTO_UARTD = 0xA4, - CLK_PTO_OWR = 0xA5, + CLK_PTO_DISP2 = 0xC4, + CLK_PTO_DISP1 = 0xC5, - CLK_PTO_HDA2CODEC_2X = 0xA7, - CLK_PTO_HDA = 0xA8, + CLK_PTO_PLLD_OBS = 0xCA, + CLK_PTO_PLLD2_PTO_OBS = 0xCC, + CLK_PTO_PLLDP_OBS = 0xCE, + CLK_PTO_PLLE_OBS = 0x10A, + CLK_PTO_PLLU_OBS = 0x10C, + CLK_PTO_PLLREFE_OBS = 0x10E, - CLK_PTO_SDMMC_LEGACY_TM = 0xAB, + CLK_PTO_XUSB_FALCON = 0x110, + CLK_PTO_XUSB_CLK480M_HSIC = 0x111, + CLK_PTO_USB_L0_RX = 0x112, + CLK_PTO_USB_L3_RX = 0x113, + CLK_PTO_USB_RX = 0x114, + CLK_PTO_USB3_L0_TXCLKREF = 0x115, + CLK_PTO_PEX_TXCLKREF_SWITCH_TMS = 0x116, + CLK_PTO_PEX_TXCLKREF_SWITCH_GRP0 = 0x117, + CLK_PTO_PEX_TXCLKREF_SWITCH_GRP1 = 0x118, + CLK_PTO_PEX_TXCLKREF_SWITCH_GRP2 = 0x119, + CLK_PTO_PEX_L4_RX = 0x11A, + CLK_PTO_PEX_TXCLKREF = 0x11B, + CLK_PTO_PEX_TXCLKREF_DIV2 = 0x11C, + CLK_PTO_PEX_TXCLKREF2 = 0x11D, + CLK_PTO_PEX_L0_RX = 0x11E, + CLK_PTO_PEX_L1_RX = 0x11F, + CLK_PTO_PEX_L2_RX = 0x120, + CLK_PTO_PEX_L3_RX = 0x121, + CLK_PTO_SATA_TXCLKREF = 0x122, + CLK_PTO_SATA_TXCLKREF_DIV2 = 0x123, + CLK_PTO_USB_L5_RX = 0x124, + CLK_PTO_SATA_TX = 0x125, + CLK_PTO_SATA_L0_RX = 0x126, - CLK_PTO_SOR0 = 0xC0, - CLK_PTO_SOR1 = 0xC1, + CLK_PTO_USB3_L1_TXCLKREF = 0x129, + CLK_PTO_USB3_L7_TXCLKREF = 0x12A, + CLK_PTO_USB3_L7_RX = 0x12B, + CLK_PTO_USB3_TX = 0x12C, + CLK_PTO_UTMIP_PLL_PAD = 0x12D, - CLK_PTO_DISP2 = 0xC4, - CLK_PTO_DISP1 = 0xC5, + CLK_PTO_XUSB_FS = 0x136, + CLK_PTO_XUSB_SS_HOST_DEV = 0x137, + CLK_PTO_XUSB_CORE_HOST = 0x138, + CLK_PTO_XUSB_CORE_DEV = 0x139, - CLK_PTO_XUSB_FALCON = 0x110, - - CLK_PTO_XUSB_FS = 0x136, - CLK_PTO_XUSB_SS_HOST_DEV = 0x137, - CLK_PTO_XUSB_CORE_HOST = 0x138, - CLK_PTO_XUSB_CORE_DEV = 0x139, + CLK_PTO_USB3_L2_TXCLKREF = 0x13C, + CLK_PTO_USB3_L3_TXCLKREF = 0x13D, + CLK_PTO_USB_L4_RX = 0x13E, + CLK_PTO_USB_L6_RX = 0x13F, /* * PLL need PTO enabled in MISC registers. * Normal div is 2 so result is multiplied with it. */ - CLK_PTO_PLLC_DIV2 = 0x01, - CLK_PTO_PLLM_DIV2 = 0x02, - CLK_PTO_PLLP_DIV2 = 0x03, - CLK_PTO_PLLA_DIV2 = 0x04, - CLK_PTO_PLLX_DIV2 = 0x05, + CLK_PTO_PLLC_DIV2 = 0x01, + CLK_PTO_PLLM_DIV2 = 0x02, + CLK_PTO_PLLP_DIV2 = 0x03, + CLK_PTO_PLLA_DIV2 = 0x04, + CLK_PTO_PLLX_DIV2 = 0x05, - CLK_PTO_PLLMB_DIV2 = 0x25, + CLK_PTO_PLLMB_DIV2 = 0x25, - CLK_PTO_PLLC4_DIV2 = 0x51, + CLK_PTO_PLLC4_DIV2 = 0x51, - CLK_PTO_PLLA1_DIV2 = 0x55, - CLK_PTO_PLLC2_DIV2 = 0x58, - CLK_PTO_PLLC3_DIV2 = 0x5A, + CLK_PTO_PLLA1_DIV2 = 0x55, + CLK_PTO_PLLC2_DIV2 = 0x58, + CLK_PTO_PLLC3_DIV2 = 0x5A, - CLK_PTO_PLLD_DIV2 = 0xCB, - CLK_PTO_PLLD2_DIV2 = 0xCD, - CLK_PTO_PLLDP_DIV2 = 0xCF, + CLK_PTO_PLLD_DIV2 = 0xCB, + CLK_PTO_PLLD2_DIV2 = 0xCD, + CLK_PTO_PLLDP_DIV2 = 0xCF, - CLK_PTO_PLLU_DIV2 = 0x10D, + CLK_PTO_PLLE_DIV2 = 0x10B, - CLK_PTO_PLLREFE_DIV2 = 0x10F, + CLK_PTO_PLLU_DIV2 = 0x10D, + + CLK_PTO_PLLREFE_DIV2 = 0x10F, } clock_pto_id_t; /* @@ -618,7 +724,7 @@ enum CLK_Y_DEV }; /*! Generic clock descriptor. */ -typedef struct _clock_t +typedef struct _clk_rst_t { u16 reset; u16 enable; @@ -626,11 +732,11 @@ typedef struct _clock_t u8 index; u8 clk_src; u8 clk_div; -} clock_t; +} clk_rst_t; /*! Generic clock enable/disable. */ -void clock_enable(const clock_t *clk); -void clock_disable(const clock_t *clk); +void clock_enable(const clk_rst_t *clk); +void clock_disable(const clk_rst_t *clk); /*! Clock control for specific hardware portions. */ void clock_enable_fuse(bool enable); @@ -645,6 +751,12 @@ void clock_enable_host1x(); void clock_disable_host1x(); void clock_enable_tsec(); void clock_disable_tsec(); +void clock_enable_nvdec(); +void clock_disable_nvdec(); +void clock_enable_nvjpg(); +void clock_disable_nvjpg(); +void clock_enable_vic(); +void clock_disable_vic(); void clock_enable_sor_safe(); void clock_disable_sor_safe(); void clock_enable_sor0(); @@ -659,12 +771,25 @@ void clock_enable_coresight(); void clock_disable_coresight(); void clock_enable_pwm(); void clock_disable_pwm(); +void clock_enable_apbdma(); +void clock_disable_apbdma(); +void clock_enable_ahbdma(); +void clock_disable_ahbdma(); +void clock_enable_actmon(); +void clock_disable_actmon(); +void clock_enable_extperiph1(); +void clock_disable_extperiph1(); +void clock_enable_extperiph2(); +void clock_disable_extperiph2(); + +void clock_enable_plld(u32 divp, u32 divn, bool lowpower, bool tegra_t210); void clock_enable_pllx(); void clock_enable_pllc(u32 divn); void clock_disable_pllc(); void clock_enable_pllu(); void clock_disable_pllu(); void clock_enable_utmipll(); + void clock_sdmmc_config_clock_source(u32 *pclock, u32 id, u32 val); void clock_sdmmc_get_card_clock_div(u32 *pclock, u16 *pdivisor, u32 type); int clock_sdmmc_is_not_reset_and_enabled(u32 id); diff --git a/bdk/soc/fuse.c b/bdk/soc/fuse.c index 63037e9..9668196 100644 --- a/bdk/soc/fuse.c +++ b/bdk/soc/fuse.c @@ -2,7 +2,7 @@ * Copyright (c) 2018 naehrwert * Copyright (c) 2018 shuffle2 * Copyright (c) 2018 balika011 - * Copyright (c) 2019-2021 CTCaer + * Copyright (c) 2019-2023 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,11 +19,14 @@ #include +#include #include #include #include #include +#include #include +#include #include static const u32 evp_thunk_template[] = { @@ -42,12 +45,19 @@ static const u32 evp_thunk_template[] = { 0xe3822001, // ORR R2, R2, #1 0xe8bd0003, // LDMFD SP!, {R0,R1} 0xe12fff12, // BX R2 + // idx: 15: 0x001007b0, // off_1007EC DCD evp_thunk_template 0x001007f8, // off_1007F0 DCD thunk_end 0x40004c30, // off_1007F4 DCD iram_evp_thunks // thunk_end is here }; -static const u32 evp_thunk_template_len = sizeof(evp_thunk_template); + +static const u32 evp_thunk_func_offsets_t210b01[] = { + 0x0010022c, // off_100268 DCD evp_thunk_template + 0x00100174, // off_10026C DCD thunk_end + 0x40004164, // off_100270 DCD iram_evp_thunks + // thunk_end is here +}; // treated as 12bit values static const u32 hash_vals[] = {1, 2, 4, 8, 0, 3, 5, 6, 7, 9, 10, 11}; @@ -80,19 +90,26 @@ u32 fuse_read_odm_keygen_rev() u32 fuse_read_dramid(bool raw_id) { - u32 dramid = (fuse_read_odm(4) & 0xF8) >> 3; + bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210; + u32 odm4 = fuse_read_odm(4); + + u32 dramid = (odm4 & 0xF8) >> 3; + + // Get extended dram id info. + if (!tegra_t210) + dramid |= (odm4 & 0x7000) >> 7; if (raw_id) return dramid; - if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210) + if (tegra_t210) { - if (dramid > 6) + if (dramid > 7) dramid = 0; } else { - if (dramid > 28) + if (dramid > 34) dramid = 8; } @@ -152,11 +169,8 @@ int fuse_set_sbk() void fuse_wait_idle() { - u32 ctrl; - do - { - ctrl = FUSE(FUSE_CTRL); - } while (((ctrl >> 16) & 0x1f) != 4); + while (((FUSE(FUSE_CTRL) >> 16) & 0x1F) != FUSE_STATUS_IDLE) + ; } u32 fuse_read(u32 addr) @@ -170,19 +184,19 @@ u32 fuse_read(u32 addr) void fuse_read_array(u32 *words) { - u32 array_size = (hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01) ? 256 : 192; + u32 array_size = (hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01) ? + FUSE_ARRAY_WORDS_NUM_B01 : FUSE_ARRAY_WORDS_NUM; for (u32 i = 0; i < array_size; i++) words[i] = fuse_read(i); } -static u32 _parity32_even(u32 *words, u32 count) +static u32 _parity32_even(const u32 *words, u32 count) { u32 acc = words[0]; for (u32 i = 1; i < count; i++) - { acc ^= words[i]; - } + u32 lo = ((acc & 0xffff) ^ (acc >> 16)) & 0xff; u32 hi = ((acc & 0xffff) ^ (acc >> 16)) >> 8; u32 x = hi ^ lo; @@ -198,26 +212,26 @@ static int _patch_hash_one(u32 *word) u32 bits20_31 = *word & 0xfff00000; u32 parity_bit = _parity32_even(&bits20_31, 1); u32 hash = 0; + for (u32 i = 0; i < 12; i++) { if (*word & (1 << (20 + i))) - { hash ^= hash_vals[i]; - } } + if (hash == 0) { if (parity_bit == 0) - { return 0; - } + *word ^= 1 << 24; + return 1; } + if (parity_bit == 0) - { return 3; - } + for (u32 i = 0; i < ARRAY_SIZE(hash_vals); i++) { if (hash_vals[i] == hash) @@ -226,6 +240,7 @@ static int _patch_hash_one(u32 *word) return 1; } } + return 2; } @@ -246,9 +261,7 @@ static int _patch_hash_multi(u32 *words, u32 count) for (u32 bitpos = 0; bitpos < 32; bitpos++) { if ((w >> bitpos) & 1) - { hash ^= 0x4000 + i * 32 + bitpos; - } } } } @@ -260,16 +273,14 @@ static int _patch_hash_multi(u32 *words, u32 count) if (hash == 0) { if (parity_bit == 0) - { return 0; - } + words[0] ^= 0x8000; return 1; } if (parity_bit == 0) - { return 3; - } + u32 bitcount = hash - 0x4000; if (bitcount < 16 || bitcount >= count * 32) { @@ -277,14 +288,11 @@ static int _patch_hash_multi(u32 *words, u32 count) for (u32 bitpos = 0; bitpos < 15; bitpos++) { if ((hash >> bitpos) & 1) - { num_set++; - } } if (num_set != 1) - { return 2; - } + words[0] ^= hash; return 1; } @@ -297,29 +305,35 @@ int fuse_read_ipatch(void (*ipatch)(u32 offset, u32 value)) u32 words[80]; u32 word_count; u32 word_addr; - u32 word0 = 0; + u32 word0; u32 total_read = 0; word_count = FUSE(FUSE_FIRST_BOOTROM_PATCH_SIZE); word_count &= 0x7F; - word_addr = 191; + word_addr = FUSE_ARRAY_WORDS_NUM - 1; while (word_count) { total_read += word_count; if (total_read >= ARRAY_SIZE(words)) - { break; - } for (u32 i = 0; i < word_count; i++) + { words[i] = fuse_read(word_addr--); + // Parse extra T210B01 fuses when the difference is reached. + if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01 && + word_addr == ((FUSE_ARRAY_WORDS_NUM - 1) - + (FUSE_ARRAY_WORDS_NUM_B01 - FUSE_ARRAY_WORDS_NUM) / sizeof(u32))) + { + word_addr = FUSE_ARRAY_WORDS_NUM_B01 - 1; + } + } word0 = words[0]; if (_patch_hash_multi(words, word_count) >= 2) - { return 1; - } + u32 ipatch_count = (words[0] >> 16) & 0xF; if (ipatch_count) { @@ -332,13 +346,14 @@ int fuse_read_ipatch(void (*ipatch)(u32 offset, u32 value)) ipatch(addr, data); } } + words[0] = word0; if ((word0 >> 25) == 0) break; + if (_patch_hash_one(&word0) >= 2) - { return 3; - } + word_count = word0 >> 25; } @@ -350,33 +365,48 @@ int fuse_read_evp_thunk(u32 *iram_evp_thunks, u32 *iram_evp_thunks_len) u32 words[80]; u32 word_count; u32 word_addr; - u32 word0 = 0; + u32 word0; u32 total_read = 0; int evp_thunk_written = 0; void *evp_thunk_dst_addr = 0; + bool t210b01 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01; + u32 *evp_thunk_tmp = (u32 *)malloc(sizeof(evp_thunk_template)); + memcpy(evp_thunk_tmp, evp_thunk_template, sizeof(evp_thunk_template)); memset(iram_evp_thunks, 0, *iram_evp_thunks_len); + if (t210b01) + memcpy(&evp_thunk_tmp[15], evp_thunk_func_offsets_t210b01, sizeof(evp_thunk_func_offsets_t210b01)); + word_count = FUSE(FUSE_FIRST_BOOTROM_PATCH_SIZE); word_count &= 0x7F; - word_addr = 191; + word_addr = FUSE_ARRAY_WORDS_NUM - 1; while (word_count) { total_read += word_count; if (total_read >= ARRAY_SIZE(words)) - { break; - } for (u32 i = 0; i < word_count; i++) + { words[i] = fuse_read(word_addr--); + // Parse extra T210B01 fuses when the difference is reached. + if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01 && + word_addr == ((FUSE_ARRAY_WORDS_NUM - 1) - + (FUSE_ARRAY_WORDS_NUM_B01 - FUSE_ARRAY_WORDS_NUM) / sizeof(u32))) + { + word_addr = FUSE_ARRAY_WORDS_NUM_B01 - 1; + } + } word0 = words[0]; if (_patch_hash_multi(words, word_count) >= 2) { + free(evp_thunk_tmp); return 1; } + u32 ipatch_count = (words[0] >> 16) & 0xF; u32 insn_count = word_count - ipatch_count - 1; if (insn_count) @@ -385,10 +415,10 @@ int fuse_read_evp_thunk(u32 *iram_evp_thunks, u32 *iram_evp_thunks_len) { evp_thunk_dst_addr = (void *)iram_evp_thunks; - memcpy(evp_thunk_dst_addr, (void *)evp_thunk_template, evp_thunk_template_len); - evp_thunk_dst_addr += evp_thunk_template_len; + memcpy(evp_thunk_dst_addr, (void *)evp_thunk_tmp, sizeof(evp_thunk_template)); + evp_thunk_dst_addr += sizeof(evp_thunk_template); evp_thunk_written = 1; - *iram_evp_thunks_len = evp_thunk_template_len; + *iram_evp_thunks_len = sizeof(evp_thunk_template); //write32(TEGRA_EXCEPTION_VECTORS_BASE + 0x208, iram_evp_thunks); } @@ -398,16 +428,22 @@ int fuse_read_evp_thunk(u32 *iram_evp_thunks, u32 *iram_evp_thunks_len) evp_thunk_dst_addr += thunk_patch_len; *iram_evp_thunks_len += thunk_patch_len; } + words[0] = word0; if ((word0 >> 25) == 0) break; + if (_patch_hash_one(&word0) >= 2) { + free(evp_thunk_tmp); return 3; } + word_count = word0 >> 25; } + free(evp_thunk_tmp); + return 0; } @@ -419,7 +455,7 @@ bool fuse_check_patched_rcm() // Check if RCM is ipatched. u32 word_count = FUSE(FUSE_FIRST_BOOTROM_PATCH_SIZE) & 0x7F; - u32 word_addr = 191; + u32 word_addr = FUSE_ARRAY_WORDS_NUM - 1; while (word_count) { diff --git a/bdk/soc/fuse.h b/bdk/soc/fuse.h index 62fa1ff..48a2c7f 100644 --- a/bdk/soc/fuse.h +++ b/bdk/soc/fuse.h @@ -2,7 +2,7 @@ * Copyright (c) 2018 naehrwert * Copyright (c) 2018 shuffle2 * Copyright (c) 2018 balika011 - * Copyright (c) 2019-2021 CTCaer + * Copyright (c) 2019-2023 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -23,67 +23,276 @@ #include /*! Fuse registers. */ -#define FUSE_CTRL 0x0 -#define FUSE_ADDR 0x4 -#define FUSE_RDATA 0x8 -#define FUSE_WDATA 0xC -#define FUSE_TIME_RD1 0x10 -#define FUSE_TIME_RD2 0x14 -#define FUSE_TIME_PGM1 0x18 -#define FUSE_TIME_PGM2 0x1C -#define FUSE_PRIV2INTFC 0x20 -#define FUSE_FUSEBYPASS 0x24 -#define FUSE_PRIVATEKEYDISABLE 0x28 -#define FUSE_DISABLEREGPROGRAM 0x2C -#define FUSE_WRITE_ACCESS_SW 0x30 -#define FUSE_PWR_GOOD_SW 0x34 -#define FUSE_SKU_INFO 0x110 -#define FUSE_CPU_SPEEDO_0_CALIB 0x114 -#define FUSE_CPU_IDDQ_CALIB 0x118 -#define FUSE_OPT_FT_REV 0x128 -#define FUSE_CPU_SPEEDO_1_CALIB 0x12C -#define FUSE_CPU_SPEEDO_2_CALIB 0x130 -#define FUSE_SOC_SPEEDO_0_CALIB 0x134 -#define FUSE_SOC_SPEEDO_1_CALIB 0x138 -#define FUSE_SOC_SPEEDO_2_CALIB 0x13C -#define FUSE_SOC_IDDQ_CALIB 0x140 -#define FUSE_OPT_CP_REV 0x190 -#define FUSE_FIRST_BOOTROM_PATCH_SIZE 0x19c -#define FUSE_PRIVATE_KEY0 0x1A4 -#define FUSE_PRIVATE_KEY1 0x1A8 -#define FUSE_PRIVATE_KEY2 0x1AC -#define FUSE_PRIVATE_KEY3 0x1B0 -#define FUSE_PRIVATE_KEY4 0x1B4 -#define FUSE_RESERVED_SW 0x1C0 -#define FUSE_USB_CALIB 0x1F0 -#define FUSE_SKU_DIRECT_CONFIG 0x1F4 -#define FUSE_OPT_VENDOR_CODE 0x200 -#define FUSE_OPT_FAB_CODE 0x204 -#define FUSE_OPT_LOT_CODE_0 0x208 -#define FUSE_OPT_LOT_CODE_1 0x20C -#define FUSE_OPT_WAFER_ID 0x210 -#define FUSE_OPT_X_COORDINATE 0x214 -#define FUSE_OPT_Y_COORDINATE 0x218 -#define FUSE_GPU_IDDQ_CALIB 0x228 -#define FUSE_USB_CALIB_EXT 0x350 +#define FUSE_CTRL 0x0 +#define FUSE_ADDR 0x4 +#define FUSE_RDATA 0x8 +#define FUSE_WDATA 0xC +#define FUSE_TIME_RD1 0x10 +#define FUSE_TIME_RD2 0x14 +#define FUSE_TIME_PGM1 0x18 +#define FUSE_TIME_PGM2 0x1C +#define FUSE_PRIV2INTFC 0x20 +#define FUSE_FUSEBYPASS 0x24 +#define FUSE_PRIVATEKEYDISABLE 0x28 +#define FUSE_DISABLEREGPROGRAM 0x2C +#define FUSE_WRITE_ACCESS_SW 0x30 +#define FUSE_PWR_GOOD_SW 0x34 +#define FUSE_PRIV2RESHIFT 0x3C +#define FUSE_FUSETIME_RD0 0x40 +#define FUSE_FUSETIME_RD1 0x44 +#define FUSE_FUSETIME_RD2 0x48 +#define FUSE_FUSETIME_RD3 0x4C +#define FUSE_PRIVATE_KEY0_NONZERO 0x80 +#define FUSE_PRIVATE_KEY1_NONZERO 0x84 +#define FUSE_PRIVATE_KEY2_NONZERO 0x88 +#define FUSE_PRIVATE_KEY3_NONZERO 0x8C +#define FUSE_PRIVATE_KEY4_NONZERO 0x90 -#define FUSE_RESERVED_ODM28_T210B01 0x240 +/*! Fuse Cached registers */ +#define FUSE_RESERVED_ODM8_B01 0x98 +#define FUSE_RESERVED_ODM9_B01 0x9C +#define FUSE_RESERVED_ODM10_B01 0xA0 +#define FUSE_RESERVED_ODM11_B01 0xA4 +#define FUSE_RESERVED_ODM12_B01 0xA8 +#define FUSE_RESERVED_ODM13_B01 0xAC +#define FUSE_RESERVED_ODM14_B01 0xB0 +#define FUSE_RESERVED_ODM15_B01 0xB4 +#define FUSE_RESERVED_ODM16_B01 0xB8 +#define FUSE_RESERVED_ODM17_B01 0xBC +#define FUSE_RESERVED_ODM18_B01 0xC0 +#define FUSE_RESERVED_ODM19_B01 0xC4 +#define FUSE_RESERVED_ODM20_B01 0xC8 +#define FUSE_RESERVED_ODM21_B01 0xCC +#define FUSE_KEK00_B01 0xD0 +#define FUSE_KEK01_B01 0xD4 +#define FUSE_KEK02_B01 0xD8 +#define FUSE_KEK03_B01 0xDC +#define FUSE_BEK00_B01 0xE0 +#define FUSE_BEK01_B01 0xE4 +#define FUSE_BEK02_B01 0xE8 +#define FUSE_BEK03_B01 0xEC +#define FUSE_OPT_RAM_RTSEL_TSMCSP_PO4SVT_B01 0xF0 +#define FUSE_OPT_RAM_WTSEL_TSMCSP_PO4SVT_B01 0xF4 +#define FUSE_OPT_RAM_RTSEL_TSMCPDP_PO4SVT_B01 0xF8 +#define FUSE_OPT_RAM_MTSEL_TSMCPDP_PO4SVT_B01 0xFC + +#define FUSE_PRODUCTION_MODE 0x100 +#define FUSE_JTAG_SECUREID_VALID 0x104 +#define FUSE_ODM_LOCK 0x108 +#define FUSE_OPT_OPENGL_EN 0x10C +#define FUSE_SKU_INFO 0x110 +#define FUSE_CPU_SPEEDO_0_CALIB 0x114 +#define FUSE_CPU_IDDQ_CALIB 0x118 + +#define FUSE_RESERVED_ODM22_B01 0x11C +#define FUSE_RESERVED_ODM23_B01 0x120 +#define FUSE_RESERVED_ODM24_B01 0x124 + +#define FUSE_OPT_FT_REV 0x128 +#define FUSE_CPU_SPEEDO_1_CALIB 0x12C +#define FUSE_CPU_SPEEDO_2_CALIB 0x130 +#define FUSE_SOC_SPEEDO_0_CALIB 0x134 +#define FUSE_SOC_SPEEDO_1_CALIB 0x138 +#define FUSE_SOC_SPEEDO_2_CALIB 0x13C +#define FUSE_SOC_IDDQ_CALIB 0x140 + +#define FUSE_RESERVED_ODM25_B01 0x144 + +#define FUSE_FA 0x148 +#define FUSE_RESERVED_PRODUCTION 0x14C +#define FUSE_HDMI_LANE0_CALIB 0x150 +#define FUSE_HDMI_LANE1_CALIB 0x154 +#define FUSE_HDMI_LANE2_CALIB 0x158 +#define FUSE_HDMI_LANE3_CALIB 0x15C +#define FUSE_ENCRYPTION_RATE 0x160 +#define FUSE_PUBLIC_KEY0 0x164 +#define FUSE_PUBLIC_KEY1 0x168 +#define FUSE_PUBLIC_KEY2 0x16C +#define FUSE_PUBLIC_KEY3 0x170 +#define FUSE_PUBLIC_KEY4 0x174 +#define FUSE_PUBLIC_KEY5 0x178 +#define FUSE_PUBLIC_KEY6 0x17C +#define FUSE_PUBLIC_KEY7 0x180 +#define FUSE_TSENSOR1_CALIB 0x184 +#define FUSE_TSENSOR2_CALIB 0x188 + +#define FUSE_OPT_SECURE_SCC_DIS_B01 0x18C + +#define FUSE_OPT_CP_REV 0x190 +#define FUSE_OPT_PFG 0x194 +#define FUSE_TSENSOR0_CALIB 0x198 +#define FUSE_FIRST_BOOTROM_PATCH_SIZE 0x19C +#define FUSE_SECURITY_MODE 0x1A0 +#define FUSE_PRIVATE_KEY0 0x1A4 +#define FUSE_PRIVATE_KEY1 0x1A8 +#define FUSE_PRIVATE_KEY2 0x1AC +#define FUSE_PRIVATE_KEY3 0x1B0 +#define FUSE_PRIVATE_KEY4 0x1B4 +#define FUSE_ARM_JTAG_DIS 0x1B8 +#define FUSE_BOOT_DEVICE_INFO 0x1BC +#define FUSE_RESERVED_SW 0x1C0 +#define FUSE_OPT_VP9_DISABLE 0x1C4 + +#define FUSE_RESERVED_ODM0 0x1C8 +#define FUSE_RESERVED_ODM1 0x1CC +#define FUSE_RESERVED_ODM2 0x1D0 +#define FUSE_RESERVED_ODM3 0x1D4 +#define FUSE_RESERVED_ODM4 0x1D8 +#define FUSE_RESERVED_ODM5 0x1DC +#define FUSE_RESERVED_ODM6 0x1E0 +#define FUSE_RESERVED_ODM7 0x1E4 + +#define FUSE_OBS_DIS 0x1E8 + +#define FUSE_OPT_NVJTAG_PROTECTION_ENABLE_B01 0x1EC + +#define FUSE_USB_CALIB 0x1F0 +#define FUSE_SKU_DIRECT_CONFIG 0x1F4 +#define FUSE_KFUSE_PRIVKEY_CTRL 0x1F8 +#define FUSE_PACKAGE_INFO 0x1FC +#define FUSE_OPT_VENDOR_CODE 0x200 +#define FUSE_OPT_FAB_CODE 0x204 +#define FUSE_OPT_LOT_CODE_0 0x208 +#define FUSE_OPT_LOT_CODE_1 0x20C +#define FUSE_OPT_WAFER_ID 0x210 +#define FUSE_OPT_X_COORDINATE 0x214 +#define FUSE_OPT_Y_COORDINATE 0x218 +#define FUSE_OPT_SEC_DEBUG_EN 0x21C +#define FUSE_OPT_OPS_RESERVED 0x220 +#define FUSE_SATA_CALIB 0x224 + +#define FUSE_SPARE_REGISTER_ODM_B01 0x224 + +#define FUSE_GPU_IDDQ_CALIB 0x228 +#define FUSE_TSENSOR3_CALIB 0x22C +#define FUSE_CLOCK_BONDOUT0 0x230 +#define FUSE_CLOCK_BONDOUT1 0x234 + +#define FUSE_RESERVED_ODM26_B01 0x238 +#define FUSE_RESERVED_ODM27_B01 0x23C +#define FUSE_RESERVED_ODM28_B01 0x240 + +#define FUSE_OPT_SAMPLE_TYPE 0x244 +#define FUSE_OPT_SUBREVISION 0x248 +#define FUSE_OPT_SW_RESERVED_0 0x24C +#define FUSE_OPT_SW_RESERVED_1 0x250 +#define FUSE_TSENSOR4_CALIB 0x254 +#define FUSE_TSENSOR5_CALIB 0x258 +#define FUSE_TSENSOR6_CALIB 0x25C +#define FUSE_TSENSOR7_CALIB 0x260 +#define FUSE_OPT_PRIV_SEC_DIS 0x264 +#define FUSE_PKC_DISABLE 0x268 + +#define FUSE_BOOT_SECURITY_INFO_B01 0x268 +#define FUSE_OPT_RAM_RTSEL_TSMCSP_PO4HVT_B01 0x26C +#define FUSE_OPT_RAM_WTSEL_TSMCSP_PO4HVT_B01 0x270 +#define FUSE_OPT_RAM_RTSEL_TSMCPDP_PO4HVT_B01 0x274 +#define FUSE_OPT_RAM_MTSEL_TSMCPDP_PO4HVT_B01 0x278 + +#define FUSE_FUSE2TSEC_DEBUG_DISABLE 0x27C +#define FUSE_TSENSOR_COMMON 0x280 +#define FUSE_OPT_CP_BIN 0x284 +#define FUSE_OPT_GPU_DISABLE 0x288 +#define FUSE_OPT_FT_BIN 0x28C +#define FUSE_OPT_DONE_MAP 0x290 + +#define FUSE_RESERVED_ODM29_B01 0x294 + +#define FUSE_APB2JTAG_DISABLE 0x298 +#define FUSE_ODM_INFO 0x29C +#define FUSE_ARM_CRYPT_DE_FEATURE 0x2A8 + +#define FUSE_OPT_RAM_WTSEL_TSMCPDP_PO4SVT_B01 0x2B0 +#define FUSE_OPT_RAM_RCT_TSMCDP_PO4SVT_B01 0x2B4 +#define FUSE_OPT_RAM_WCT_TSMCDP_PO4SVT_B01 0x2B8 +#define FUSE_OPT_RAM_KP_TSMCDP_PO4SVT_B01 0x2BC + +#define FUSE_WOA_SKU_FLAG 0x2C0 +#define FUSE_ECO_RESERVE_1 0x2C4 +#define FUSE_GCPLEX_CONFIG_FUSE 0x2C8 +#define FUSE_PRODUCTION_MONTH 0x2CC +#define FUSE_RAM_REPAIR_INDICATOR 0x2D0 +#define FUSE_TSENSOR9_CALIB 0x2D4 +#define FUSE_VMIN_CALIBRATION 0x2DC +#define FUSE_AGING_SENSOR_CALIBRATION 0x2E0 +#define FUSE_DEBUG_AUTHENTICATION 0x2E4 +#define FUSE_SECURE_PROVISION_INDEX 0x2E8 +#define FUSE_SECURE_PROVISION_INFO 0x2EC +#define FUSE_OPT_GPU_DISABLE_CP1 0x2F0 +#define FUSE_SPARE_ENDIS 0x2F4 +#define FUSE_ECO_RESERVE_0 0x2F8 +#define FUSE_RESERVED_CALIB0 0x304 +#define FUSE_RESERVED_CALIB1 0x308 +#define FUSE_OPT_GPU_TPC0_DISABLE 0x30C +#define FUSE_OPT_GPU_TPC0_DISABLE_CP1 0x310 +#define FUSE_OPT_CPU_DISABLE 0x314 +#define FUSE_OPT_CPU_DISABLE_CP1 0x318 +#define FUSE_TSENSOR10_CALIB 0x31C +#define FUSE_TSENSOR10_CALIB_AUX 0x320 +#define FUSE_OPT_RAM_SVOP_DP 0x324 +#define FUSE_OPT_RAM_SVOP_PDP 0x328 +#define FUSE_OPT_RAM_SVOP_REG 0x32C +#define FUSE_OPT_RAM_SVOP_SP 0x330 +#define FUSE_OPT_RAM_SVOP_SMPDP 0x334 + +#define FUSE_OPT_RAM_WTSEL_TSMCPDP_PO4HVT_B01 0x324 +#define FUSE_OPT_RAM_RCT_TSMCDP_PO4HVT_B01 0x328 +#define FUSE_OPT_RAM_WCT_TSMCDP_PO4HVT_B01 0x32c +#define FUSE_OPT_RAM_KP_TSMCDP_PO4HVT_B01 0x330 +#define FUSE_OPT_ROM_SVOP_SP_B01 0x334 + +#define FUSE_OPT_GPU_TPC0_DISABLE_CP2 0x338 +#define FUSE_OPT_GPU_TPC1_DISABLE 0x33C +#define FUSE_OPT_GPU_TPC1_DISABLE_CP1 0x340 +#define FUSE_OPT_GPU_TPC1_DISABLE_CP2 0x344 +#define FUSE_OPT_CPU_DISABLE_CP2 0x348 +#define FUSE_OPT_GPU_DISABLE_CP2 0x34C +#define FUSE_USB_CALIB_EXT 0x350 +#define FUSE_RESERVED_FIELD 0x354 +#define FUSE_SPARE_REALIGNMENT_REG 0x37C +#define FUSE_SPARE_BIT_0 0x380 +//... +#define FUSE_SPARE_BIT_31 0x3FC /*! Fuse commands. */ -#define FUSE_READ 0x1 -#define FUSE_WRITE 0x2 -#define FUSE_SENSE 0x3 +#define FUSE_IDLE 0x0 +#define FUSE_READ 0x1 +#define FUSE_WRITE 0x2 +#define FUSE_SENSE 0x3 #define FUSE_CMD_MASK 0x3 +/*! Fuse status. */ +#define FUSE_STATUS_RESET 0 +#define FUSE_STATUS_POST_RESET 1 +#define FUSE_STATUS_LOAD_ROW0 2 +#define FUSE_STATUS_LOAD_ROW1 3 +#define FUSE_STATUS_IDLE 4 +#define FUSE_STATUS_READ_SETUP 5 +#define FUSE_STATUS_READ_STROBE 6 +#define FUSE_STATUS_SAMPLE_FUSES 7 +#define FUSE_STATUS_READ_HOLD 8 +#define FUSE_STATUS_FUSE_SRC_SETUP 9 +#define FUSE_STATUS_WRITE_SETUP 10 +#define FUSE_STATUS_WRITE_ADDR_SETUP 11 +#define FUSE_STATUS_WRITE_PROGRAM 12 +#define FUSE_STATUS_WRITE_ADDR_HOLD 13 +#define FUSE_STATUS_FUSE_SRC_HOLD 14 +#define FUSE_STATUS_LOAD_RIR 15 +#define FUSE_STATUS_READ_BEFORE_WRITE_SETUP 16 +#define FUSE_STATUS_READ_DEASSERT_PD 17 + /*! Fuse cache registers. */ #define FUSE_RESERVED_ODMX(x) (0x1C8 + 4 * (x)) +#define FUSE_ARRAY_WORDS_NUM 192 +#define FUSE_ARRAY_WORDS_NUM_B01 256 + enum { FUSE_NX_HW_TYPE_ICOSA, FUSE_NX_HW_TYPE_IOWA, FUSE_NX_HW_TYPE_HOAG, - FUSE_NX_HW_TYPE_AULA + FUSE_NX_HW_TYPE_AULA }; enum diff --git a/bdk/soc/gpio.c b/bdk/soc/gpio.c index 5cd2ccd..8575333 100644 --- a/bdk/soc/gpio.c +++ b/bdk/soc/gpio.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2019 CTCaer + * Copyright (c) 2019-2023 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,23 +18,27 @@ #include #include -#define GPIO_BANK_IDX(port) ((port) >> 2) +#define GPIO_BANK_IDX(port) ((port) >> 2) +#define GPIO_PORT_OFFSET(port) ((GPIO_BANK_IDX(port) << 8) + (((port) % 4) << 2)) -#define GPIO_CNF_OFFSET(port) (0x00 + (((port) >> 2) << 8) + (((port) % 4) << 2)) -#define GPIO_OE_OFFSET(port) (0x10 + (((port) >> 2) << 8) + (((port) % 4) << 2)) -#define GPIO_OUT_OFFSET(port) (0x20 + (((port) >> 2) << 8) + (((port) % 4) << 2)) -#define GPIO_IN_OFFSET(port) (0x30 + (((port) >> 2) << 8) + (((port) % 4) << 2)) -#define GPIO_INT_STA_OFFSET(port) (0x40 + (((port) >> 2) << 8) + (((port) % 4) << 2)) -#define GPIO_INT_ENB_OFFSET(port) (0x50 + (((port) >> 2) << 8) + (((port) % 4) << 2)) -#define GPIO_INT_LVL_OFFSET(port) (0x60 + (((port) >> 2) << 8) + (((port) % 4) << 2)) -#define GPIO_INT_CLR_OFFSET(port) (0x70 + (((port) >> 2) << 8) + (((port) % 4) << 2)) +#define GPIO_CNF_OFFSET(port) (0x00 + GPIO_PORT_OFFSET(port)) +#define GPIO_OE_OFFSET(port) (0x10 + GPIO_PORT_OFFSET(port)) +#define GPIO_OUT_OFFSET(port) (0x20 + GPIO_PORT_OFFSET(port)) +#define GPIO_IN_OFFSET(port) (0x30 + GPIO_PORT_OFFSET(port)) +#define GPIO_INT_STA_OFFSET(port) (0x40 + GPIO_PORT_OFFSET(port)) +#define GPIO_INT_ENB_OFFSET(port) (0x50 + GPIO_PORT_OFFSET(port)) +#define GPIO_INT_LVL_OFFSET(port) (0x60 + GPIO_PORT_OFFSET(port)) +#define GPIO_INT_CLR_OFFSET(port) (0x70 + GPIO_PORT_OFFSET(port)) -#define GPIO_CNF_MASKED_OFFSET(port) (0x80 + (((port) >> 2) << 8) + (((port) % 4) << 2)) -#define GPIO_OE_MASKED_OFFSET(port) (0x90 + (((port) >> 2) << 8) + (((port) % 4) << 2)) -#define GPIO_OUT_MASKED_OFFSET(port) (0xA0 + (((port) >> 2) << 8) + (((port) % 4) << 2)) -#define GPIO_INT_STA_MASKED_OFFSET(port) (0xC0 + (((port) >> 2) << 8) + (((port) % 4) << 2)) -#define GPIO_INT_ENB_MASKED_OFFSET(port) (0xD0 + (((port) >> 2) << 8) + (((port) % 4) << 2)) -#define GPIO_INT_LVL_MASKED_OFFSET(port) (0xE0 + (((port) >> 2) << 8) + (((port) % 4) << 2)) +#define GPIO_CNF_MASKED_OFFSET(port) (0x80 + GPIO_PORT_OFFSET(port)) +#define GPIO_OE_MASKED_OFFSET(port) (0x90 + GPIO_PORT_OFFSET(port)) +#define GPIO_OUT_MASKED_OFFSET(port) (0xA0 + GPIO_PORT_OFFSET(port)) +#define GPIO_INT_STA_MASKED_OFFSET(port) (0xC0 + GPIO_PORT_OFFSET(port)) +#define GPIO_INT_ENB_MASKED_OFFSET(port) (0xD0 + GPIO_PORT_OFFSET(port)) +#define GPIO_INT_LVL_MASKED_OFFSET(port) (0xE0 + GPIO_PORT_OFFSET(port)) + +#define GPIO_DB_CTRL_OFFSET(port) (0xB0 + GPIO_PORT_OFFSET(port)) +#define GPIO_DB_CNT_OFFSET(port) (0xF0 + GPIO_PORT_OFFSET(port)) #define GPIO_IRQ_BANK1 32 #define GPIO_IRQ_BANK2 33 @@ -52,7 +56,7 @@ static u8 gpio_bank_irq_ids[8] = { void gpio_config(u32 port, u32 pins, int mode) { - u32 offset = GPIO_CNF_OFFSET(port); + const u32 offset = GPIO_CNF_OFFSET(port); if (mode) GPIO(offset) |= pins; @@ -64,7 +68,7 @@ void gpio_config(u32 port, u32 pins, int mode) void gpio_output_enable(u32 port, u32 pins, int enable) { - u32 port_offset = GPIO_OE_OFFSET(port); + const u32 port_offset = GPIO_OE_OFFSET(port); if (enable) GPIO(port_offset) |= pins; @@ -76,7 +80,7 @@ void gpio_output_enable(u32 port, u32 pins, int enable) void gpio_write(u32 port, u32 pins, int high) { - u32 port_offset = GPIO_OUT_OFFSET(port); + const u32 port_offset = GPIO_OUT_OFFSET(port); if (high) GPIO(port_offset) |= pins; @@ -86,16 +90,49 @@ void gpio_write(u32 port, u32 pins, int high) (void)GPIO(port_offset); // Commit the write. } +void gpio_direction_input(u32 port, u32 pins) +{ + gpio_config(port, pins, GPIO_MODE_GPIO); + gpio_output_enable(port, pins, GPIO_OUTPUT_DISABLE); +} + +void gpio_direction_output(u32 port, u32 pins, int high) +{ + gpio_config(port, pins, GPIO_MODE_GPIO); + gpio_write(port, pins, high); + gpio_output_enable(port, pins, GPIO_OUTPUT_ENABLE); +} + int gpio_read(u32 port, u32 pins) { - u32 port_offset = GPIO_IN_OFFSET(port); + const u32 port_offset = GPIO_IN_OFFSET(port); return (GPIO(port_offset) & pins) ? 1 : 0; } +void gpio_set_debounce(u32 port, u32 pins, u32 ms) +{ + const u32 db_ctrl_offset = GPIO_DB_CTRL_OFFSET(port); + const u32 db_cnt_offset = GPIO_DB_CNT_OFFSET(port); + + if (ms) + { + if (ms > 255) + ms = 255; + + // Debounce time affects all pins of the same port. + GPIO(db_cnt_offset) = ms; + GPIO(db_ctrl_offset) = (pins << 8) | pins; + } + else + GPIO(db_ctrl_offset) = (pins << 8) | 0; + + (void)GPIO(db_ctrl_offset); // Commit the write. +} + static void _gpio_interrupt_clear(u32 port, u32 pins) { - u32 port_offset = GPIO_INT_CLR_OFFSET(port); + const u32 port_offset = GPIO_INT_CLR_OFFSET(port); GPIO(port_offset) |= pins; @@ -104,10 +141,10 @@ static void _gpio_interrupt_clear(u32 port, u32 pins) int gpio_interrupt_status(u32 port, u32 pins) { - u32 port_offset = GPIO_INT_STA_OFFSET(port); - u32 enabled = GPIO(GPIO_INT_ENB_OFFSET(port)) & pins; + const u32 port_offset = GPIO_INT_STA_OFFSET(port); + const u32 enabled_mask = GPIO(GPIO_INT_ENB_OFFSET(port)) & pins; - int status = ((GPIO(port_offset) & pins) && enabled) ? 1 : 0; + int status = ((GPIO(port_offset) & pins) && enabled_mask) ? 1 : 0; // Clear the interrupt status. if (status) @@ -118,7 +155,7 @@ int gpio_interrupt_status(u32 port, u32 pins) void gpio_interrupt_enable(u32 port, u32 pins, int enable) { - u32 port_offset = GPIO_INT_ENB_OFFSET(port); + const u32 port_offset = GPIO_INT_ENB_OFFSET(port); // Clear any possible stray interrupt. _gpio_interrupt_clear(port, pins); @@ -133,7 +170,7 @@ void gpio_interrupt_enable(u32 port, u32 pins, int enable) void gpio_interrupt_level(u32 port, u32 pins, int high, int edge, int delta) { - u32 port_offset = GPIO_INT_LVL_OFFSET(port); + const u32 port_offset = GPIO_INT_LVL_OFFSET(port); u32 val = GPIO(port_offset); @@ -162,7 +199,7 @@ void gpio_interrupt_level(u32 port, u32 pins, int high, int edge, int delta) u32 gpio_get_bank_irq_id(u32 port) { - u32 bank_idx = GPIO_BANK_IDX(port); + const u32 bank_idx = GPIO_BANK_IDX(port); return gpio_bank_irq_ids[bank_idx]; -} \ No newline at end of file +} diff --git a/bdk/soc/gpio.h b/bdk/soc/gpio.h index 0c92b14..7f94de5 100644 --- a/bdk/soc/gpio.h +++ b/bdk/soc/gpio.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2019 CTCaer + * Copyright (c) 2019-2023 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -85,8 +85,11 @@ void gpio_config(u32 port, u32 pins, int mode); void gpio_output_enable(u32 port, u32 pins, int enable); +void gpio_direction_input(u32 port, u32 pins); +void gpio_direction_output(u32 port, u32 pins, int high); void gpio_write(u32 port, u32 pins, int high); int gpio_read(u32 port, u32 pins); +void gpio_set_debounce(u32 port, u32 pins, u32 ms); int gpio_interrupt_status(u32 port, u32 pins); void gpio_interrupt_enable(u32 port, u32 pins, int enable); void gpio_interrupt_level(u32 port, u32 pins, int high, int edge, int delta); diff --git a/bdk/soc/hw_init.c b/bdk/soc/hw_init.c index 5efe5df..7bfa599 100644 --- a/bdk/soc/hw_init.c +++ b/bdk/soc/hw_init.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,6 +19,7 @@ #include #include +#include #include #include #include @@ -31,6 +32,7 @@ #include #include #include +#include #include #include #include @@ -39,7 +41,7 @@ #include #include #include -#include +#include #include #include #include @@ -48,6 +50,17 @@ extern boot_cfg_t b_cfg; extern volatile nyx_storage_t *nyx_str; +u32 hw_rst_status; +u32 hw_rst_reason; + +u32 hw_get_chip_id() +{ + if (((APB_MISC(APB_MISC_GP_HIDREV) >> 4) & 0xF) >= GP_HIDREV_MAJOR_T210B01) + return GP_HIDREV_MAJOR_T210B01; + else + return GP_HIDREV_MAJOR_T210; +} + /* * CLK_OSC - 38.4 MHz crystal. * CLK_M - 19.2 MHz (osc/2). @@ -57,35 +70,45 @@ extern volatile nyx_storage_t *nyx_str; * PCLK - 68MHz init (-> 136MHz -> OC/4). */ -u32 hw_get_chip_id() -{ - if (((APB_MISC(APB_MISC_GP_HIDREV) >> 4) & 0xF) >= GP_HIDREV_MAJOR_T210B01) - return GP_HIDREV_MAJOR_T210B01; - else - return GP_HIDREV_MAJOR_T210; -} - static void _config_oscillators() { CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) = (CLOCK(CLK_RST_CONTROLLER_SPARE_REG0) & 0xFFFFFFF3) | 4; // Set CLK_M_DIVISOR to 2. - SYSCTR0(SYSCTR0_CNTFID0) = 19200000; // Set counter frequency. - TMR(TIMERUS_USEC_CFG) = 0x45F; // For 19.2MHz clk_m. - CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x50000071; // Set OSC to 38.4MHz and drive strength. + SYSCTR0(SYSCTR0_CNTFID0) = 19200000; // Set counter frequency. + TMR(TIMERUS_USEC_CFG) = 0x45F; // For 19.2MHz clk_m. + CLOCK(CLK_RST_CONTROLLER_OSC_CTRL) = 0x50000071; // Set OSC to 38.4MHz and drive strength. PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFFFFF81) | 0xE; // Set LP0 OSC drive strength. PMC(APBDEV_PMC_OSC_EDPD_OVER) = (PMC(APBDEV_PMC_OSC_EDPD_OVER) & 0xFFBFFFFF) | PMC_OSC_EDPD_OVER_OSC_CTRL_OVER; - PMC(APBDEV_PMC_CNTRL2) = (PMC(APBDEV_PMC_CNTRL2) & 0xFFFFEFFF) | PMC_CNTRL2_HOLD_CKE_LOW_EN; - PMC(APBDEV_PMC_SCRATCH188) = (PMC(APBDEV_PMC_SCRATCH188) & 0xFCFFFFFF) | (4 << 23); // LP0 EMC2TMC_CFG_XM2COMP_PU_VREF_SEL_RANGE. + PMC(APBDEV_PMC_CNTRL2) = (PMC(APBDEV_PMC_CNTRL2) & 0xFFFFEFFF) | PMC_CNTRL2_HOLD_CKE_LOW_EN; + PMC(APB_MISC_GP_ASDBGREG) = (PMC(APB_MISC_GP_ASDBGREG) & 0xFCFFFFFF) | (2 << 24); // CFG2TMC_RAM_SVOP_PDP. - CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x10; // Set HCLK div to 2 and PCLK div to 1. - CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) &= 0xBFFFFFFF; // PLLMB disable. + CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x10; // Set HCLK div to 2 and PCLK div to 1. + CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) &= 0xBFFFFFFF; // PLLMB disable. - PMC(APBDEV_PMC_TSC_MULT) = (PMC(APBDEV_PMC_TSC_MULT) & 0xFFFF0000) | 0x249F; //0x249F = 19200000 * (16 / 32.768 kHz) + PMC(APBDEV_PMC_TSC_MULT) = (PMC(APBDEV_PMC_TSC_MULT) & 0xFFFF0000) | 0x249F; // 0x249F = 19200000 * (16 / 32.768 kHz). - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0; // Set BPMP/SCLK div to 1. - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; // Set BPMP/SCLK source to Run and PLLP_OUT2 (204MHz). + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0; // Set BPMP/SCLK div to 1. + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; // Set BPMP/SCLK source to Run and PLLP_OUT2 (204MHz). CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000; // Enable SUPER_SDIV to 1. - CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3. + CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3. +} + +void hw_config_arbiter(bool reset) +{ + if (reset) + { + ARB_PRI(ARB_PRIO_CPU_PRIORITY) = 0x0040090; + ARB_PRI(ARB_PRIO_COP_PRIORITY) = 0x12024C2; + ARB_PRI(ARB_PRIO_VCP_PRIORITY) = 0x2201209; + ARB_PRI(ARB_PRIO_DMA_PRIORITY) = 0x320365B; + } + else + { + ARB_PRI(ARB_PRIO_CPU_PRIORITY) = 0x12412D1; + ARB_PRI(ARB_PRIO_COP_PRIORITY) = 0x0000000; + ARB_PRI(ARB_PRIO_VCP_PRIORITY) = 0x220244A; + ARB_PRI(ARB_PRIO_DMA_PRIORITY) = 0x320369B; + } } // The uart is skipped for Copper, Hoag and Calcio. Used in Icosa, Iowa and Aula. @@ -96,53 +119,39 @@ static void _config_gpios(bool nx_hoag) if (!nx_hoag) { + // Turn Joy-Con detect on. (GPIO mode and input logic for UARTB/C TX pins.) PINMUX_AUX(PINMUX_AUX_UART2_TX) = 0; PINMUX_AUX(PINMUX_AUX_UART3_TX) = 0; - - // Set pin mode for UARTB/C TX pins. -#if !defined (DEBUG_UART_PORT) || DEBUG_UART_PORT != UART_B - gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO); -#endif -#if !defined (DEBUG_UART_PORT) || DEBUG_UART_PORT != UART_C - gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO); -#endif - - // Enable input logic for UARTB/C TX pins. - gpio_output_enable(GPIO_PORT_G, GPIO_PIN_0, GPIO_OUTPUT_DISABLE); - gpio_output_enable(GPIO_PORT_D, GPIO_PIN_1, GPIO_OUTPUT_DISABLE); + gpio_direction_input(GPIO_PORT_G, GPIO_PIN_0); + gpio_direction_input(GPIO_PORT_D, GPIO_PIN_1); } - // Set Joy-Con IsAttached direction. + // Set Joy-Con IsAttached pinmux. Shared with UARTB/UARTC TX. PINMUX_AUX(PINMUX_AUX_GPIO_PE6) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE; PINMUX_AUX(PINMUX_AUX_GPIO_PH6) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE; - // Set Joy-Con IsAttached mode. - gpio_config(GPIO_PORT_E, GPIO_PIN_6, GPIO_MODE_GPIO); - gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_GPIO); - - // Enable input logic for Joy-Con IsAttached pins. - gpio_output_enable(GPIO_PORT_E, GPIO_PIN_6, GPIO_OUTPUT_DISABLE); - gpio_output_enable(GPIO_PORT_H, GPIO_PIN_6, GPIO_OUTPUT_DISABLE); + // Configure Joy-Con IsAttached pins. Shared with UARTB/UARTC TX. + gpio_direction_input(GPIO_PORT_E, GPIO_PIN_6); + gpio_direction_input(GPIO_PORT_H, GPIO_PIN_6); pinmux_config_i2c(I2C_1); pinmux_config_i2c(I2C_5); pinmux_config_uart(UART_A); // Configure volume up/down as inputs. - gpio_config(GPIO_PORT_X, GPIO_PIN_6, GPIO_MODE_GPIO); - gpio_config(GPIO_PORT_X, GPIO_PIN_7, GPIO_MODE_GPIO); - gpio_output_enable(GPIO_PORT_X, GPIO_PIN_6, GPIO_OUTPUT_DISABLE); - gpio_output_enable(GPIO_PORT_X, GPIO_PIN_7, GPIO_OUTPUT_DISABLE); + gpio_direction_input(GPIO_PORT_X, GPIO_PIN_6 | GPIO_PIN_7); - // Configure HOME as inputs. - // PINMUX_AUX(PINMUX_AUX_BUTTON_HOME) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE; - // gpio_config(GPIO_PORT_Y, GPIO_PIN_1, GPIO_MODE_GPIO); + // Configure HOME as input. (Shared with UARTB RTS). + PINMUX_AUX(PINMUX_AUX_BUTTON_HOME) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE; + gpio_direction_input(GPIO_PORT_Y, GPIO_PIN_1); + + // Power button can be configured for hoag here. Only SKU where it's connected. } static void _config_pmc_scratch() { PMC(APBDEV_PMC_SCRATCH20) &= 0xFFF3FFFF; // Unset Debug console from Customer Option. - PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; // Unset DATA_DQ_E_IVREF EMC_PMACRO_DATA_PAD_TX_CTRL + PMC(APBDEV_PMC_SCRATCH190) &= 0xFFFFFFFE; // Unset WDT_DURING_BR. PMC(APBDEV_PMC_SECURE_SCRATCH21) |= PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT; } @@ -175,8 +184,9 @@ static void _mbist_workaround() I2S(I2S5_CTRL) |= I2S_CTRL_MASTER_EN; I2S(I2S5_CG) &= ~I2S_CG_SLCG_ENABLE; + // Set SLCG overrides. DISPLAY_A(_DIREG(DC_COM_DSC_TOP_CTL)) |= 4; // DSC_SLCG_OVERRIDE. - VIC(0x8C) = 0xFFFFFFFF; + VIC(VIC_THI_SLCG_OVERRIDE_LOW_A) = 0xFFFFFFFF; usleep(2); // Set per-clock reset for APE/VIC/HOST1X/DISP1. @@ -243,9 +253,9 @@ static void _mbist_workaround() // Set child clock sources. CLOCK(CLK_RST_CONTROLLER_PLLD_BASE) &= 0x1F7FFFFF; // Disable PLLD and set reference clock and csi clock. CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SOR1) &= 0xFFFF3FFF; // Set SOR1 to automatic muxing of safe clock (24MHz) or SOR1 clk switch. - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT. + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_VI) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT. CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT. - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT. + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_NVENC) & 0x1FFFFFFF) | 0x80000000; // Set clock source to PLLP_OUT. } static void _config_se_brom() @@ -260,17 +270,23 @@ static void _config_se_brom() // se_key_acc_ctrl(15, SE_KEY_TBL_DIS_KEYREAD_FLAG); // This memset needs to happen here, else TZRAM will behave weirdly later on. - memset((void *)TZRAM_BASE, 0, 0x10000); + memset((void *)TZRAM_BASE, 0, TZRAM_SIZE); PMC(APBDEV_PMC_CRYPTO_OP) = PMC_CRYPTO_OP_SE_ENABLE; - SE(SE_INT_STATUS_REG) = 0x1F; // Clear all SE interrupts. - // Clear the boot reason to avoid problems later - PMC(APBDEV_PMC_SCRATCH200) = 0x0; - PMC(APBDEV_PMC_RST_STATUS) = 0x0; + // Clear SE interrupts. + SE(SE_INT_STATUS_REG) = SE_INT_OP_DONE | SE_INT_OUT_DONE | SE_INT_OUT_LL_BUF_WR | SE_INT_IN_DONE | SE_INT_IN_LL_BUF_RD; + + // Save reset reason. + hw_rst_status = PMC(APBDEV_PMC_SCRATCH200); + hw_rst_reason = PMC(APBDEV_PMC_RST_STATUS) & PMC_RST_STATUS_MASK; + + // Clear the boot reason to avoid problems later. + PMC(APBDEV_PMC_SCRATCH200) = 0; + PMC(APBDEV_PMC_RST_STATUS) = PMC_RST_STATUS_POR; APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) = (APB_MISC(APB_MISC_PP_STRAPPING_OPT_A) & 0xF0) | (7 << 10); } -static void _config_regulators(bool tegra_t210) +static void _config_regulators(bool tegra_t210, bool nx_hoag) { // Set RTC/AO domain to POR voltage. if (tegra_t210) @@ -279,19 +295,26 @@ static void _config_regulators(bool tegra_t210) // Disable low battery shutdown monitor. max77620_low_battery_monitor_config(false); - // Disable SDMMC1 IO power. - gpio_write(GPIO_PORT_E, GPIO_PIN_4, GPIO_LOW); + // Power on all relevant rails in case we came out of warmboot. Only keep MEM/MEM_COMP and SDMMC1 states. + PMC(APBDEV_PMC_NO_IOPOWER) &= PMC_NO_IOPOWER_MEM_COMP | PMC_NO_IOPOWER_SDMMC1 | PMC_NO_IOPOWER_MEM; + + // Make sure SDMMC1 IO/Core are powered off. max7762x_regulator_enable(REGULATOR_LDO2, false); + gpio_write(GPIO_PORT_E, GPIO_PIN_4, GPIO_LOW); + PMC(APBDEV_PMC_NO_IOPOWER) |= PMC_NO_IOPOWER_SDMMC1; + (void)PMC(APBDEV_PMC_NO_IOPOWER); sd_power_cycle_time_start = get_tmr_ms(); + // Disable backup battery charger. i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CNFGBBC, MAX77620_CNFGBBC_RESISTOR_1K); - i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, - MAX77620_ONOFFCNFG1_RSVD | (3 << MAX77620_ONOFFCNFG1_MRT_SHIFT)); // PWR delay for forced shutdown off. + + // Set PWR delay for forced shutdown off to 6s. + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, MAX77620_ONOFFCNFG1_RSVD | (3 << MAX77620_ONOFFCNFG1_MRT_SHIFT)); if (tegra_t210) { // Configure all Flexible Power Sequencers for MAX77620. - i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG0, (7 << MAX77620_FPS_TIME_PERIOD_SHIFT)); + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG0, (7 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (0 << MAX77620_FPS_EN_SRC_SHIFT)); i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG1, (7 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (1 << MAX77620_FPS_EN_SRC_SHIFT)); i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_CFG2, (7 << MAX77620_FPS_TIME_PERIOD_SHIFT)); max77620_regulator_config_fps(REGULATOR_LDO4); @@ -300,13 +323,13 @@ static void _config_regulators(bool tegra_t210) max77620_regulator_config_fps(REGULATOR_SD1); max77620_regulator_config_fps(REGULATOR_SD3); - i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_GPIO3, - (4 << MAX77620_FPS_TIME_PERIOD_SHIFT) | (2 << MAX77620_FPS_PD_PERIOD_SHIFT)); // 3.x+ + // Set GPIO3 to FPS0 for SYS 3V3 EN. Enabled when FPS0 is enabled. + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_FPS_GPIO3, (4 << MAX77620_FPS_PU_PERIOD_SHIFT) | (2 << MAX77620_FPS_PD_PERIOD_SHIFT)); // Set vdd_core voltage to 1.125V. max7762x_regulator_set_voltage(REGULATOR_SD0, 1125000); - // Fix CPU/GPU after L4T warmboot. + // Power down CPU/GPU regulators after L4T warmboot. max77620_config_gpio(5, MAX77620_GPIO_OUTPUT_DISABLE); max77620_config_gpio(6, MAX77620_GPIO_OUTPUT_DISABLE); @@ -314,26 +337,49 @@ static void _config_regulators(bool tegra_t210) max77621_config_default(REGULATOR_CPU0, MAX77621_CTRL_POR_CFG); max77621_config_default(REGULATOR_GPU0, MAX77621_CTRL_POR_CFG); } - else // Tegra X1+ set vdd_core voltage to 1.05V. + else + { + // Tegra X1+ set vdd_core voltage to 1.05V. max7762x_regulator_set_voltage(REGULATOR_SD0, 1050000); + + // Power on SD2 regulator for supplying LDO0/1/8. + max7762x_regulator_set_voltage(REGULATOR_SD2, 1325000); + + // Set slew rate and enable SD2 regulator. + i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_SD2_CFG, (1 << MAX77620_SD_SR_SHIFT) | + (MAX77620_POWER_MODE_NORMAL << MAX77620_SD_POWER_MODE_SHIFT) | + MAX77620_SD_CFG1_FSRADE_SD_ENABLE); + + // Enable LDO8 on HOAG as it also powers I2C1 IO pads. + if (nx_hoag) + { + max7762x_regulator_set_voltage(REGULATOR_LDO8, 2800000); + max7762x_regulator_enable(REGULATOR_LDO8, true); + } + } } void hw_init() { - // Get Chip ID. + // Get Chip ID and SKU. bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210; bool nx_hoag = fuse_read_hw_type() == FUSE_NX_HW_TYPE_HOAG; // Bootrom stuff we skipped by going through rcm. _config_se_brom(); //FUSE(FUSE_PRIVATEKEYDISABLE) = 0x11; - SYSREG(AHB_AHB_SPARE_REG) &= 0xFFFFFF9F; // Unset APB2JTAG_OVERRIDE_EN and OBS_OVERRIDE_EN. - PMC(APBDEV_PMC_SCRATCH49) = PMC(APBDEV_PMC_SCRATCH49) & 0xFFFFFFFC; + + // Unset APB2JTAG_OVERRIDE_EN and OBS_OVERRIDE_EN. + SYSREG(AHB_AHB_SPARE_REG) &= 0xFFFFFF9F; + PMC(APBDEV_PMC_SCRATCH49) &= 0xFFFFFFFC; // Perform Memory Built-In Self Test WAR if T210. if (tegra_t210) _mbist_workaround(); + // Make sure PLLP_OUT3/4 is set to 408 MHz and enabled. + CLOCK(CLK_RST_CONTROLLER_PLLP_OUTB) = 0x30003; + // Enable Security Engine clock. clock_enable_se(); @@ -352,13 +398,7 @@ void hw_init() // Initialize pin configuration. _config_gpios(nx_hoag); -#ifdef DEBUG_UART_PORT - clock_enable_uart(DEBUG_UART_PORT); - uart_init(DEBUG_UART_PORT, DEBUG_UART_BAUDRATE); - uart_invert(DEBUG_UART_PORT, DEBUG_UART_INVERT, UART_INVERT_TXD); -#endif - - // Enable Dynamic Voltage and Frequency Scaling device clock. + // Enable CL-DVFS clock unconditionally to avoid issues with I2C5 sharing. clock_enable_cl_dvfs(); // Enable clocks to I2C1 and I2CPWR. @@ -371,63 +411,83 @@ void hw_init() // Initialize I2C5, mandatory for PMIC. i2c_init(I2C_5); - //! TODO: Why? Device is NFC MCU on Lite. - if (nx_hoag) - { - max7762x_regulator_set_voltage(REGULATOR_LDO8, 2800000); - max7762x_regulator_enable(REGULATOR_LDO8, true); - } + // Initialize various regulators based on Erista/Mariko platform. + _config_regulators(tegra_t210, nx_hoag); // Initialize I2C1 for various power related devices. i2c_init(I2C_1); - // Initialize various regulators based on Erista/Mariko platform. - _config_regulators(tegra_t210); - - // Enable charger in case it's disabled. - bq24193_enable_charger(); - _config_pmc_scratch(); // Missing from 4.x+ // Set BPMP/SCLK to PLLP_OUT (408MHz). CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; - // Disable TZRAM shutdown control and lock the regs. + // Power on T210B01 shadow TZRAM and lock the reg. if (!tegra_t210) { - PMC(APBDEV_PMC_TZRAM_PWR_CNTRL) &= 0xFFFFFFFE; - PMC(APBDEV_PMC_TZRAM_NON_SEC_DISABLE) = 3; - PMC(APBDEV_PMC_TZRAM_SEC_DISABLE) = 3; + PMC(APBDEV_PMC_TZRAM_PWR_CNTRL) &= ~PMC_TZRAM_PWR_CNTRL_SD; + PMC(APBDEV_PMC_TZRAM_NON_SEC_DISABLE) = PMC_TZRAM_DISABLE_REG_WRITE | PMC_TZRAM_DISABLE_REG_READ; + PMC(APBDEV_PMC_TZRAM_SEC_DISABLE) = PMC_TZRAM_DISABLE_REG_WRITE | PMC_TZRAM_DISABLE_REG_READ; } + // Set arbiter. + hw_config_arbiter(false); + // Initialize External memory controller and configure DRAM parameters. sdram_init(); bpmp_mmu_enable(); + + // Enable HOST1X used by every display module (DC, VIC, NVDEC, NVENC, TSEC, etc). + clock_enable_host1x(); + +#ifdef DEBUG_UART_PORT + // Setup debug uart port. + #if (DEBUG_UART_PORT == UART_B) + gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO); + #elif (DEBUG_UART_PORT == UART_C) + gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO); + #endif + pinmux_config_uart(DEBUG_UART_PORT); + clock_enable_uart(DEBUG_UART_PORT); + uart_init(DEBUG_UART_PORT, DEBUG_UART_BAUDRATE, UART_AO_TX_AO_RX); + uart_invert(DEBUG_UART_PORT, DEBUG_UART_INVERT, UART_INVERT_TXD); +#endif } -void hw_reinit_workaround(bool coreboot, u32 bl_magic) +void hw_deinit(bool coreboot, u32 bl_magic) { - // Disable BPMP max clock. + bool tegra_t210 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210; + + // Scale down BPMP clock. bpmp_clk_rate_set(BPMP_CLK_NORMAL); -#ifdef NYX - // Disable temperature sensor, touchscreen, 5V regulators and Joy-Con. +#ifdef BDK_HW_EXTRA_DEINIT + // Disable temperature sensor, touchscreen, 5V regulators, Joy-Con and VIC. + vic_end(); tmp451_end(); - set_fan_duty(0); + fan_set_duty(0); touch_power_off(); jc_deinit(); regulator_5v_disable(REGULATOR_5V_ALL); #endif - // Flush/disable MMU cache and set DRAM clock to 204MHz. - bpmp_mmu_disable(); + // set DRAM clock to 204MHz. minerva_change_freq(FREQ_204); nyx_str->mtc_cfg.init_done = 0; + // Flush/disable MMU cache. + bpmp_mmu_disable(); + + // Reset arbiter. + hw_config_arbiter(true); + // Re-enable clocks to Audio Processing Engine as a workaround to hanging. - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= BIT(CLK_V_AHUB); - CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= BIT(CLK_Y_APE); + if (tegra_t210) + { + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_V) |= BIT(CLK_V_AHUB); + CLOCK(CLK_RST_CONTROLLER_CLK_OUT_ENB_Y) |= BIT(CLK_Y_APE); + } // Do coreboot mitigations. if (coreboot) @@ -436,14 +496,12 @@ void hw_reinit_workaround(bool coreboot, u32 bl_magic) clock_disable_cl_dvfs(); - // Disable Joy-con GPIOs. + // Disable Joy-con detect in order to restore UART TX. gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO); gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO); - gpio_config(GPIO_PORT_E, GPIO_PIN_6, GPIO_MODE_SPIO); - gpio_config(GPIO_PORT_H, GPIO_PIN_6, GPIO_MODE_SPIO); // Reinstate SD controller power. - PMC(APBDEV_PMC_NO_IOPOWER) &= ~(PMC_NO_IOPOWER_SDMMC1_IO_EN); + PMC(APBDEV_PMC_NO_IOPOWER) &= ~PMC_NO_IOPOWER_SDMMC1; } // Seamless display or display power off. @@ -456,17 +514,11 @@ void hw_reinit_workaround(bool coreboot, u32 bl_magic) gpio_config(GPIO_PORT_V, GPIO_PIN_0, GPIO_MODE_GPIO); display_backlight_brightness(brightness, 0); break; + case BL_MAGIC_L4TLDR_SLD: + // Do not disable display or backlight at all. + break; default: display_end(); - } - - // Enable clock to USBD and init SDMMC1 to avoid hangs with bad hw inits. - if (bl_magic == BL_MAGIC_BROKEN_HWI) - { - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_SET) = BIT(CLK_L_USBD); - sdmmc_init(&sd_sdmmc, SDMMC_1, SDMMC_POWER_3_3, SDMMC_BUS_WIDTH_1, SDHCI_TIMING_SD_ID, 0); - clock_disable_cl_dvfs(); - - msleep(200); + clock_disable_host1x(); } } diff --git a/bdk/soc/hw_init.h b/bdk/soc/hw_init.h index a1b2dfc..fcd8d10 100644 --- a/bdk/soc/hw_init.h +++ b/bdk/soc/hw_init.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -21,10 +21,14 @@ #include #define BL_MAGIC_CRBOOT_SLD 0x30444C53 // SLD0, seamless display type 0. -#define BL_MAGIC_BROKEN_HWI 0xBAADF00D // Broken hwinit. +#define BL_MAGIC_L4TLDR_SLD 0x31444C53 // SLD1, seamless display type 1. + +extern u32 hw_rst_status; +extern u32 hw_rst_reason; void hw_init(); -void hw_reinit_workaround(bool coreboot, u32 magic); +void hw_deinit(bool coreboot, u32 magic); +void hw_config_arbiter(bool reset); u32 hw_get_chip_id(); #endif diff --git a/bdk/soc/i2c.c b/bdk/soc/i2c.c index 0906adc..c38e952 100644 --- a/bdk/soc/i2c.c +++ b/bdk/soc/i2c.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 CTCaer + * Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,7 +18,8 @@ #include #include -#include +#include +#include #define I2C_PACKET_PROT_I2C BIT(4) #define I2C_HEADER_CONT_XFER BIT(15) @@ -81,34 +82,28 @@ #define MSTR_CONFIG_LOAD BIT(0) #define TIMEOUT_CONFIG_LOAD BIT(2) -static const u32 i2c_addrs[] = { - 0x7000C000, // I2C_1. - 0x7000C400, // I2C_2. - 0x7000C500, // I2C_3. - 0x7000C700, // I2C_4. - 0x7000D000, // I2C_5. - 0x7000D100 // I2C_6. -}; +/* I2C_1, 2, 3, 4, 5 and 6. */ +static const u16 _i2c_base_offsets[6] = { 0x0, 0x400, 0x500, 0x700, 0x1000, 0x1100 }; static void _i2c_load_cfg_wait(vu32 *base) { base[I2C_CONFIG_LOAD] = BIT(5) | TIMEOUT_CONFIG_LOAD | MSTR_CONFIG_LOAD; for (u32 i = 0; i < 20; i++) { - usleep(1); if (!(base[I2C_CONFIG_LOAD] & MSTR_CONFIG_LOAD)) break; + usleep(1); } } -static int _i2c_send_single(u32 i2c_idx, u32 dev_addr, u8 *buf, u32 size) +static int _i2c_send_single(u32 i2c_idx, u32 dev_addr, const u8 *buf, u32 size) { if (size > 8) return 0; u32 tmp = 0; - vu32 *base = (vu32 *)i2c_addrs[i2c_idx]; + vu32 *base = (vu32 *)(I2C_BASE + (u32)_i2c_base_offsets[i2c_idx]); // Set device address and send mode. base[I2C_CMD_ADDR0] = dev_addr << 1 | ADDR0_WRITE; @@ -154,7 +149,7 @@ static int _i2c_recv_single(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr) if (size > 8) return 0; - vu32 *base = (vu32 *)i2c_addrs[i2c_idx]; + vu32 *base = (vu32 *)(I2C_BASE + (u32)_i2c_base_offsets[i2c_idx]); // Set device address and recv mode. base[I2C_CMD_ADDR0] = (dev_addr << 1) | ADDR0_READ; @@ -198,15 +193,15 @@ static int _i2c_send_pkt(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr) int res = 0; - vu32 *base = (vu32 *)i2c_addrs[i2c_idx]; + vu32 *base = (vu32 *)(I2C_BASE + (u32)_i2c_base_offsets[i2c_idx]); // Enable interrupts. base[I2C_INT_EN] = ALL_PACKETS_COMPLETE | PACKET_COMPLETE | NO_ACK | ARB_LOST | TX_FIFO_OVER | RX_FIFO_UNDER | TX_FIFO_DATA_REQ; base[I2C_INT_STATUS] = base[I2C_INT_STATUS]; - // Set device address and recv mode. - base[I2C_CMD_ADDR0] = (dev_addr << 1) | ADDR0_READ; + // Set device address and send mode. + base[I2C_CMD_ADDR0] = (dev_addr << 1) | ADDR0_WRITE; // Set recv mode. base[I2C_CNFG] = DEBOUNCE_CNT_4T | NEW_MASTER_FSM | CMD1_WRITE; @@ -270,7 +265,7 @@ static int _i2c_recv_pkt(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr, u32 reg) int res = 0; - vu32 *base = (vu32 *)i2c_addrs[i2c_idx]; + vu32 *base = (vu32 *)(I2C_BASE + (u32)_i2c_base_offsets[i2c_idx]); // Enable interrupts. base[I2C_INT_EN] = ALL_PACKETS_COMPLETE | PACKET_COMPLETE | NO_ACK | @@ -352,7 +347,7 @@ static int _i2c_recv_pkt(u32 i2c_idx, u8 *buf, u32 size, u32 dev_addr, u32 reg) void i2c_init(u32 i2c_idx) { - vu32 *base = (vu32 *)i2c_addrs[i2c_idx]; + vu32 *base = (vu32 *)(I2C_BASE + (u32)_i2c_base_offsets[i2c_idx]); base[I2C_CLK_DIVISOR] = (5 << 16) | 1; // SF mode Div: 6, HS mode div: 2. base[I2C_BUS_CLEAR_CONFIG] = (9 << 16) | BC_TERMINATE | BC_ENABLE; @@ -362,9 +357,9 @@ void i2c_init(u32 i2c_idx) for (u32 i = 0; i < 10; i++) { - usleep(20000); if (base[I2C_INT_STATUS] & BUS_CLEAR_DONE) break; + usleep(25); } (vu32)base[I2C_BUS_CLEAR_STATUS]; @@ -389,9 +384,9 @@ int i2c_recv_buf_big(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr, u32 reg) return _i2c_recv_pkt(i2c_idx, buf, size, dev_addr, reg); } -int i2c_send_buf_small(u32 i2c_idx, u32 dev_addr, u32 reg, u8 *buf, u32 size) +int i2c_send_buf_small(u32 i2c_idx, u32 dev_addr, u32 reg, const u8 *buf, u32 size) { - u8 tmp[4]; + u8 tmp[8]; if (size > 7) return 0; diff --git a/bdk/soc/i2c.h b/bdk/soc/i2c.h index a04eec1..ab3078e 100644 --- a/bdk/soc/i2c.h +++ b/bdk/soc/i2c.h @@ -31,7 +31,7 @@ void i2c_init(u32 i2c_idx); int i2c_recv_buf(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr); int i2c_send_buf_big(u32 i2c_idx, u32 dev_addr, u8 *buf, u32 size); int i2c_recv_buf_big(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr, u32 reg); -int i2c_send_buf_small(u32 i2c_idx, u32 dev_addr, u32 reg, u8 *buf, u32 size); +int i2c_send_buf_small(u32 i2c_idx, u32 dev_addr, u32 reg, const u8 *buf, u32 size); int i2c_recv_buf_small(u8 *buf, u32 size, u32 i2c_idx, u32 dev_addr, u32 reg); int i2c_send_byte(u32 i2c_idx, u32 dev_addr, u32 reg, u8 val); u8 i2c_recv_byte(u32 i2c_idx, u32 dev_addr, u32 reg); diff --git a/bdk/soc/irq.c b/bdk/soc/irq.c index e2f925c..f39774e 100644 --- a/bdk/soc/irq.c +++ b/bdk/soc/irq.c @@ -1,7 +1,7 @@ /* * BPMP-Lite IRQ driver for Tegra X1 * - * Copyright (c) 2019 CTCaer + * Copyright (c) 2019-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,6 +19,7 @@ #include #include "irq.h" +#include #include #include #include @@ -26,6 +27,7 @@ //#define DPRINTF(...) gfx_printf(__VA_ARGS__) #define DPRINTF(...) +extern void excp_reset(); extern void irq_disable(); extern void irq_enable_cpu_irq_exceptions(); extern void irq_disable_cpu_irq_exceptions(); @@ -69,29 +71,19 @@ static void _irq_disable_and_ack_all() { u32 enabled_irqs = ICTLR(ctrl_idx, PRI_ICTLR_COP_IER); ICTLR(ctrl_idx, PRI_ICTLR_COP_IER_CLR) = enabled_irqs; - ICTLR(ctrl_idx, PRI_ICTLR_FIR_CLR) = enabled_irqs; } } -static void _irq_ack_source(u32 irq) -{ - u32 ctrl_idx = irq >> 5; - u32 bit = irq % 32; - - // Force stop the interrupt as it's serviced here. - ICTLR(ctrl_idx, PRI_ICTLR_FIR_CLR) = BIT(bit); -} - void irq_free(u32 irq) { for (u32 idx = 0; idx < IRQ_MAX_HANDLERS; idx++) { if (irqs[idx].irq == irq && irqs[idx].handler) { - irqs[idx].irq = 0; + irqs[idx].irq = 0; irqs[idx].handler = NULL; - irqs[idx].data = NULL; - irqs[idx].flags = 0; + irqs[idx].data = NULL; + irqs[idx].flags = 0; _irq_disable_source(irq); } @@ -106,10 +98,10 @@ static void _irq_free_all() { _irq_disable_source(irqs[idx].irq); - irqs[idx].irq = 0; + irqs[idx].irq = 0; irqs[idx].handler = NULL; - irqs[idx].data = NULL; - irqs[idx].flags = 0; + irqs[idx].data = NULL; + irqs[idx].flags = 0; } } } @@ -119,7 +111,6 @@ static irq_status_t _irq_handle_source(u32 irq) int status = IRQ_NONE; _irq_disable_source(irq); - _irq_ack_source(irq); u32 idx; for (idx = 0; idx < IRQ_MAX_HANDLERS; idx++) @@ -133,8 +124,8 @@ static irq_status_t _irq_handle_source(u32 irq) } } - // Do not re-enable if not handled. - if (status == IRQ_NONE) + // Do not re-enable if not handled or error. + if (status != IRQ_HANDLED) return status; if (irqs[idx].flags & IRQ_FLAG_ONE_OFF) @@ -153,7 +144,6 @@ void irq_handler() if (!irq_init_done) { _irq_disable_source(irq); - _irq_ack_source(irq); return; } @@ -192,10 +182,9 @@ void irq_wait_event(u32 irq) _irq_enable_source(irq); // Halt BPMP and wait for the IRQ. No need to use WAIT_EVENT + LIC_IRQ when BPMP serves the IRQ. - FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_COP_STOP_UNTIL_IRQ; + FLOW_CTLR(FLOW_CTLR_HALT_COP_EVENTS) = HALT_MODE_STOP_UNTIL_IRQ; _irq_disable_source(irq); - _irq_ack_source(irq); irq_enable_cpu_irq_exceptions(); } @@ -218,10 +207,10 @@ irq_status_t irq_request(u32 irq, irq_handler_t handler, void *data, irq_flags_t DPRINTF("Registered handler, IRQ: %d, Slot: %d\n", irq, idx); DPRINTF("Handler: %08p, Flags: %x\n", (u32)handler, flags); - irqs[idx].irq = irq; + irqs[idx].irq = irq; irqs[idx].handler = handler; - irqs[idx].data = data; - irqs[idx].flags = flags; + irqs[idx].data = data; + irqs[idx].flags = flags; _irq_enable_source(irq); @@ -270,4 +259,14 @@ void __attribute__ ((target("arm"), interrupt ("FIQ"))) fiq_handler() len--; } */ +#ifdef BDK_WATCHDOG_FIQ_ENABLE + // Set watchdog timeout status and disable WDT and its FIQ signal. + watchdog_handle(); + +#ifdef BDK_RESTART_BL_ON_WDT + // Restart bootloader. + excp_reset(); +#endif + +#endif } diff --git a/bdk/soc/irq.h b/bdk/soc/irq.h index dbd5ee2..54dc12a 100644 --- a/bdk/soc/irq.h +++ b/bdk/soc/irq.h @@ -180,6 +180,7 @@ #define IRQ_EVENT_GPIO_A 162 #define IRQ_EVENT_GPIO_B 163 #define IRQ_EVENT_GPIO_C 164 +#define IRQ_EVENT_GPIO_D_T210B01 165 #define IRQ_FLOW_RSM_CPU 168 #define IRQ_FLOW_RSM_COP 169 #define IRQ_TMR_SHARED 170 diff --git a/bdk/soc/pinmux.c b/bdk/soc/pinmux.c index 2601cdf..84969c6 100644 --- a/bdk/soc/pinmux.c +++ b/bdk/soc/pinmux.c @@ -1,5 +1,6 @@ /* * Copyright (c) 2018 naehrwert + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,10 +20,10 @@ void pinmux_config_uart(u32 idx) { - PINMUX_AUX(PINMUX_AUX_UARTX_TX(idx)) = 0; - PINMUX_AUX(PINMUX_AUX_UARTX_RX(idx)) = PINMUX_INPUT_ENABLE | PINMUX_PULL_UP; + PINMUX_AUX(PINMUX_AUX_UARTX_TX(idx)) = 0; + PINMUX_AUX(PINMUX_AUX_UARTX_RX(idx)) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE; PINMUX_AUX(PINMUX_AUX_UARTX_RTS(idx)) = 0; - PINMUX_AUX(PINMUX_AUX_UARTX_CTS(idx)) = PINMUX_INPUT_ENABLE | PINMUX_PULL_DOWN; + PINMUX_AUX(PINMUX_AUX_UARTX_CTS(idx)) = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE; } void pinmux_config_i2c(u32 idx) @@ -30,3 +31,11 @@ void pinmux_config_i2c(u32 idx) PINMUX_AUX(PINMUX_AUX_X_I2C_SCL(idx)) = PINMUX_INPUT_ENABLE; PINMUX_AUX(PINMUX_AUX_X_I2C_SDA(idx)) = PINMUX_INPUT_ENABLE; } + +void pinmux_config_i2s(u32 idx) +{ + PINMUX_AUX(PINMUX_AUX_X_I2S_LRCK(idx)) = PINMUX_DRIVE_4X | PINMUX_PULL_DOWN; + PINMUX_AUX(PINMUX_AUX_X_I2C_DIN(idx)) = PINMUX_DRIVE_4X | PINMUX_INPUT_ENABLE | PINMUX_TRISTATE | PINMUX_PULL_DOWN; + PINMUX_AUX(PINMUX_AUX_X_I2C_DOUT(idx)) = PINMUX_DRIVE_4X | PINMUX_PULL_DOWN; + PINMUX_AUX(PINMUX_AUX_X_I2C_BCLK(idx)) = PINMUX_DRIVE_4X | PINMUX_PULL_DOWN; +} diff --git a/bdk/soc/pinmux.h b/bdk/soc/pinmux.h index 48fcab3..f9ad5af 100644 --- a/bdk/soc/pinmux.h +++ b/bdk/soc/pinmux.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2018 naehrwert + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -39,6 +40,7 @@ #define PINMUX_AUX_SDMMC3_DAT2 0x2C #define PINMUX_AUX_SDMMC3_DAT3 0x30 #define PINMUX_AUX_SATA_LED_ACTIVE 0x4C +#define PINMUX_AUX_GPIO_PA5_T210B01 PINMUX_AUX_SATA_LED_ACTIVE #define PINMUX_AUX_DMIC3_CLK 0xB4 #define PINMUX_AUX_DMIC3_DAT 0xB8 #define PINMUX_AUX_CAM_I2C_SCL 0xD4 @@ -46,7 +48,10 @@ #define PINMUX_AUX_UART2_TX 0xF4 #define PINMUX_AUX_UART3_TX 0x104 #define PINMUX_AUX_DAP4_DIN 0x148 +#define PINMUX_AUX_DAP4_DOUT 0x14C #define PINMUX_AUX_DAP4_SCLK 0x150 +#define PINMUX_AUX_CLK_32K_OUT 0x164 +#define PINMUX_AUX_AUD_MCLK 0x180 #define PINMUX_AUX_GPIO_X1_AUD 0x18C #define PINMUX_AUX_GPIO_X3_AUD 0x190 #define PINMUX_AUX_SPDIF_IN 0x1A4 @@ -57,20 +62,29 @@ #define PINMUX_AUX_AP_WAKE_NFC 0x1CC #define PINMUX_AUX_NFC_EN 0x1D0 #define PINMUX_AUX_NFC_INT 0x1D4 +#define PINMUX_AUX_CAM_RST 0x1E0 #define PINMUX_AUX_CAM1_PWDN 0x1EC #define PINMUX_AUX_CAM2_PWDN 0x1F0 +#define PINMUX_AUX_CAM1_STROBE 0x1F4 #define PINMUX_AUX_LCD_BL_PWM 0x1FC #define PINMUX_AUX_LCD_BL_EN 0x200 #define PINMUX_AUX_LCD_RST 0x204 #define PINMUX_AUX_LCD_GPIO1 0x208 #define PINMUX_AUX_LCD_GPIO2 0x20C +#define PINMUX_AUX_TOUCH_RST 0x214 +#define PINMUX_AUX_TOUCH_CLK 0x218 #define PINMUX_AUX_TOUCH_INT 0x220 #define PINMUX_AUX_MOTION_INT 0x224 +#define PINMUX_AUX_ALS_PROX_INT 0x228 +#define PINMUX_AUX_BUTTON_POWER_ON 0x230 #define PINMUX_AUX_BUTTON_HOME 0x240 #define PINMUX_AUX_GPIO_PE6 0x248 +#define PINMUX_AUX_GPIO_PE7 0x24C #define PINMUX_AUX_GPIO_PH6 0x250 #define PINMUX_AUX_GPIO_PK3 0x260 +#define PINMUX_AUX_GPIO_PK7 0x270 #define PINMUX_AUX_GPIO_PZ1 0x280 +#define PINMUX_AUX_GPIO_PZ4 0x28C /* Only in T210B01 */ #define PINMUX_AUX_SDMMC2_DAT0 0x294 #define PINMUX_AUX_SDMMC2_DAT1 0x298 @@ -91,6 +105,11 @@ /*! 0:GEN1, 1:GEN2, 2:GEN3, 3:CAM, 4:PWR */ #define PINMUX_AUX_X_I2C_SCL(x) (0xBC + 8 * (x)) #define PINMUX_AUX_X_I2C_SDA(x) (0xC0 + 8 * (x)) +/*! 0:I2S1, 1:I2S2 */ +#define PINMUX_AUX_X_I2S_LRCK(x) (0x124 + 0x10 * (x)) +#define PINMUX_AUX_X_I2C_DIN(x) (0x128 + 0x10 * (x)) +#define PINMUX_AUX_X_I2C_DOUT(x) (0x12c + 0x10 * (x)) +#define PINMUX_AUX_X_I2C_BCLK(x) (0x130 + 0x10 * (x)) #define PINMUX_FUNC_MASK (3 << 0) @@ -116,7 +135,10 @@ #define PINMUX_DRIVE_3X (2 << 13) #define PINMUX_DRIVE_4X (3 << 13) +#define PINMUX_PREEMP BIT(15) + void pinmux_config_uart(u32 idx); void pinmux_config_i2c(u32 idx); +void pinmux_config_i2s(u32 idx); #endif diff --git a/bdk/soc/pmc.c b/bdk/soc/pmc.c index aa86cb7..472b22c 100644 --- a/bdk/soc/pmc.c +++ b/bdk/soc/pmc.c @@ -16,31 +16,28 @@ #include #include +#include #include -#include void pmc_scratch_lock(pmc_sec_lock_t lock_mask) { // Lock Private key disable, Fuse write enable, MC carveout, Warmboot PA id and Warmboot address. + + // Happens on T210B01 LP0 always. if (lock_mask & PMC_SEC_LOCK_MISC) { PMC(APBDEV_PMC_SEC_DISABLE) |= 0x700FF0; // RW lock: 0-3. PMC(APBDEV_PMC_SEC_DISABLE2) |= 0xFC000000; // RW lock: 21-23. PMC(APBDEV_PMC_SEC_DISABLE3) |= 0x3F0FFF00; // RW lock: 28-33, 36-38. PMC(APBDEV_PMC_SEC_DISABLE6) |= 0xC000000; // RW lock: 85. - PMC(APBDEV_PMC_SEC_DISABLE8) |= 0xFF00FF00; // RW lock: 108-111, 116-119. - - // SE2 context. - if (hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01) - { - PMC(APBDEV_PMC_SEC_DISABLE9) |= 0x3FF; // RW lock: 120-124. (0xB38) - PMC(APBDEV_PMC_SEC_DISABLE10) = 0xFFFFFFFF; // RW lock: 135-150. - } + // Default: 0xFF00FF00: RW lock: 108-111, 116-119. Gets locked in LP0. + PMC(APBDEV_PMC_SEC_DISABLE8) |= 0xFF005500; // W lock: 108-111, RW lock: 116-119. } + // Happens on T210B01 LP0 always. if (lock_mask & PMC_SEC_LOCK_LP0_PARAMS) { - PMC(APBDEV_PMC_SEC_DISABLE2) |= 0x3FCFFFF; // RW lock: 8-15, 17-20. + PMC(APBDEV_PMC_SEC_DISABLE2) |= 0x3FCFFFF; // RW lock: 8-15, 17-20. L4T expects 8-15 as write locked only. PMC(APBDEV_PMC_SEC_DISABLE4) |= 0x3F3FFFFF; // RW lock: 40-50, 52-54. PMC(APBDEV_PMC_SEC_DISABLE5) = 0xFFFFFFFF; // RW lock: 56-71. PMC(APBDEV_PMC_SEC_DISABLE6) |= 0xF3FFC00F; // RW lock: 72-73, 79-84, 86-87. @@ -60,6 +57,7 @@ void pmc_scratch_lock(pmc_sec_lock_t lock_mask) PMC(APBDEV_PMC_SEC_DISABLE7) |= 0xFFC00000; // RW lock: 99-103. } + // HOS specific. if (lock_mask & PMC_SEC_LOCK_TZ_CMAC_W) PMC(APBDEV_PMC_SEC_DISABLE8) |= 0x550000; // W lock: 112-115. @@ -71,9 +69,34 @@ void pmc_scratch_lock(pmc_sec_lock_t lock_mask) if (lock_mask & PMC_SEC_LOCK_TZ_KEK_R) PMC(APBDEV_PMC_SEC_DISABLE3) |= 0xAA; // R lock: 24-27. + // End of HOS specific. if (lock_mask & PMC_SEC_LOCK_SE_SRK) PMC(APBDEV_PMC_SEC_DISABLE) |= 0xFF000; // RW lock: 4-7 + + if (lock_mask & PMC_SEC_LOCK_SE2_SRK_B01) + PMC(APBDEV_PMC_SEC_DISABLE9) |= 0x3FC; // RW lock: 120-123 (T210B01). LP0 also sets global bits (b0-1). + + if (lock_mask & PMC_SEC_LOCK_MISC_B01) + PMC(APBDEV_PMC_SEC_DISABLE10) = 0xFFFFFFFF; // RW lock: 135-150. Happens on T210B01 LP0 always. + + if (lock_mask & PMC_SEC_LOCK_CARVEOUTS_L4T) + PMC(APBDEV_PMC_SEC_DISABLE2) |= 0x5555; // W: 8-15 LP0 and Carveouts. Superseded by LP0 lock. + + // NVTBOOT misses APBDEV_PMC_SCRATCH_WRITE_LOCK_DISABLE_STICKY. bit0: SCRATCH_WR_DIS_ON. + // They could also use the NS write disable registers instead. + if (lock_mask & PMC_SEC_LOCK_LP0_PARAMS_B01) + { + PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE0) |= 0xCBCFE0; // W lock: 5-11, 14-17, 19, 22-23. + PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE1) |= 0x583FF; // W lock: 24-33, 39-40, 42. + PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE2) |= 0x1BE; // W lock: 44-48, 50-51. + PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE3) = 0xFFFFFFFF; // W lock: 56-87. + PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE4) |= 0xFFFFFFF; // W lock: 88-115. + PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE5) |= 0xFFFFFFF8; // W lock: 123-151. + PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE6) = 0xFFFFFFFF; // W lock: 152-183. + PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE7) |= 0xFC00FFFF; // W lock: 184-199, 210-215. + PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE8) |= 0xF; // W lock: 216-219. + } } int pmc_enable_partition(pmc_power_rail_t part, u32 enable) diff --git a/bdk/soc/pmc.h b/bdk/soc/pmc.h index 42bd869..5721895 100644 --- a/bdk/soc/pmc.h +++ b/bdk/soc/pmc.h @@ -1,7 +1,7 @@ /* * Copyright (c) 2018 naehrwert * Copyright (c) 2018 st4rk - * Copyright (c) 2018-2020 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -22,95 +22,196 @@ #include /*! PMC registers. */ -#define APBDEV_PMC_CNTRL 0x0 -#define PMC_CNTRL_MAIN_RST BIT(4) -#define APBDEV_PMC_SEC_DISABLE 0x4 -#define APBDEV_PMC_PWRGATE_TOGGLE 0x30 -#define APBDEV_PMC_PWRGATE_STATUS 0x38 -#define APBDEV_PMC_NO_IOPOWER 0x44 -#define PMC_NO_IOPOWER_SDMMC1_IO_EN BIT(12) -#define PMC_NO_IOPOWER_AUDIO_HV BIT(18) -#define PMC_NO_IOPOWER_GPIO_IO_EN BIT(21) -#define APBDEV_PMC_SCRATCH0 0x50 -#define PMC_SCRATCH0_MODE_WARMBOOT BIT(0) -#define PMC_SCRATCH0_MODE_RCM BIT(1) -#define PMC_SCRATCH0_MODE_PAYLOAD BIT(29) -#define PMC_SCRATCH0_MODE_FASTBOOT BIT(30) -#define PMC_SCRATCH0_MODE_RECOVERY BIT(31) -#define PMC_SCRATCH0_MODE_CUSTOM_ALL (PMC_SCRATCH0_MODE_RECOVERY | PMC_SCRATCH0_MODE_FASTBOOT | PMC_SCRATCH0_MODE_PAYLOAD) -#define APBDEV_PMC_SCRATCH1 0x54 -#define APBDEV_PMC_SCRATCH20 0xA0 -#define APBDEV_PMC_SECURE_SCRATCH4 0xC0 -#define APBDEV_PMC_SECURE_SCRATCH5 0xC4 -#define APBDEV_PMC_PWR_DET_VAL 0xE4 -#define PMC_PWR_DET_SDMMC1_IO_EN BIT(12) -#define PMC_PWR_DET_AUDIO_HV BIT(18) -#define PMC_PWR_DET_GPIO_IO_EN BIT(21) -#define APBDEV_PMC_DDR_PWR 0xE8 -#define APBDEV_PMC_USB_AO 0xF0 -#define APBDEV_PMC_CRYPTO_OP 0xF4 -#define PMC_CRYPTO_OP_SE_ENABLE 0 -#define PMC_CRYPTO_OP_SE_DISABLE 1 -#define APBDEV_PMC_SCRATCH33 0x120 -#define APBDEV_PMC_SCRATCH37 0x130 -#define PMC_SCRATCH37_KERNEL_PANIC_FLAG BIT(24) -#define APBDEV_PMC_SCRATCH40 0x13C -#define APBDEV_PMC_OSC_EDPD_OVER 0x1A4 -#define PMC_OSC_EDPD_OVER_OSC_CTRL_OVER 0x400000 -#define APBDEV_PMC_CLK_OUT_CNTRL 0x1A8 -#define PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN BIT(2) -#define APBDEV_PMC_RST_STATUS 0x1B4 -#define APBDEV_PMC_IO_DPD_REQ 0x1B8 -#define PMC_IO_DPD_REQ_DPD_OFF BIT(30) -#define APBDEV_PMC_IO_DPD2_REQ 0x1C0 -#define APBDEV_PMC_VDDP_SEL 0x1CC -#define APBDEV_PMC_DDR_CFG 0x1D0 -#define APBDEV_PMC_SECURE_SCRATCH6 0x224 -#define APBDEV_PMC_SECURE_SCRATCH7 0x228 -#define APBDEV_PMC_SCRATCH45 0x234 -#define APBDEV_PMC_SCRATCH46 0x238 -#define APBDEV_PMC_SCRATCH49 0x244 -#define APBDEV_PMC_TSC_MULT 0x2B4 -#define APBDEV_PMC_SEC_DISABLE2 0x2C4 -#define APBDEV_PMC_WEAK_BIAS 0x2C8 -#define APBDEV_PMC_REG_SHORT 0x2CC -#define APBDEV_PMC_SEC_DISABLE3 0x2D8 -#define APBDEV_PMC_SECURE_SCRATCH21 0x334 -#define PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT 0x10 -#define APBDEV_PMC_SECURE_SCRATCH32 0x360 -#define APBDEV_PMC_SECURE_SCRATCH49 0x3A4 -#define APBDEV_PMC_CNTRL2 0x440 -#define PMC_CNTRL2_HOLD_CKE_LOW_EN 0x1000 -#define APBDEV_PMC_IO_DPD3_REQ 0x45C -#define APBDEV_PMC_IO_DPD4_REQ 0x464 -#define APBDEV_PMC_UTMIP_PAD_CFG1 0x4C4 -#define APBDEV_PMC_UTMIP_PAD_CFG3 0x4CC -#define APBDEV_PMC_DDR_CNTRL 0x4E4 -#define APBDEV_PMC_SEC_DISABLE4 0x5B0 -#define APBDEV_PMC_SEC_DISABLE5 0x5B4 -#define APBDEV_PMC_SEC_DISABLE6 0x5B8 -#define APBDEV_PMC_SEC_DISABLE7 0x5BC -#define APBDEV_PMC_SEC_DISABLE8 0x5C0 -#define APBDEV_PMC_SEC_DISABLE9 0x5C4 -#define APBDEV_PMC_SEC_DISABLE10 0x5C8 -#define APBDEV_PMC_SCRATCH188 0x810 -#define APBDEV_PMC_SCRATCH190 0x818 -#define APBDEV_PMC_SCRATCH200 0x840 -#define APBDEV_PMC_TZRAM_PWR_CNTRL 0xBE8 -#define APBDEV_PMC_TZRAM_SEC_DISABLE 0xBEC -#define APBDEV_PMC_TZRAM_NON_SEC_DISABLE 0xBF0 +#define APBDEV_PMC_CNTRL 0x0 +#define PMC_CNTRL_RTC_CLK_DIS BIT(1) +#define PMC_CNTRL_RTC_RST BIT(2) +#define PMC_CNTRL_MAIN_RST BIT(4) +#define PMC_CNTRL_LATCHWAKE_EN BIT(5) +#define PMC_CNTRL_BLINK_EN BIT(7) +#define PMC_CNTRL_PWRREQ_OE BIT(9) +#define PMC_CNTRL_SYSCLK_OE BIT(11) +#define PMC_CNTRL_PWRGATE_DIS BIT(12) +#define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) +#define PMC_CNTRL_CPUPWRREQ_OE BIT(16) +#define PMC_CNTRL_FUSE_OVERRIDE BIT(18) +#define PMC_CNTRL_SHUTDOWN_OE BIT(22) +#define APBDEV_PMC_SEC_DISABLE 0x4 +#define APBDEV_PMC_PWRGATE_TOGGLE 0x30 +#define APBDEV_PMC_PWRGATE_STATUS 0x38 +#define APBDEV_PMC_NO_IOPOWER 0x44 +#define PMC_NO_IOPOWER_MEM BIT(7) +#define PMC_NO_IOPOWER_SDMMC1 BIT(12) +#define PMC_NO_IOPOWER_SDMMC4 BIT(14) +#define PMC_NO_IOPOWER_MEM_COMP BIT(16) +#define PMC_NO_IOPOWER_AUDIO_HV BIT(18) +#define PMC_NO_IOPOWER_GPIO BIT(21) +#define APBDEV_PMC_SCRATCH0 0x50 +#define PMC_SCRATCH0_MODE_WARMBOOT BIT(0) +#define PMC_SCRATCH0_MODE_RCM BIT(1) +#define PMC_SCRATCH0_MODE_PAYLOAD BIT(29) +#define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30) +#define PMC_SCRATCH0_MODE_RECOVERY BIT(31) +#define PMC_SCRATCH0_MODE_CUSTOM_ALL (PMC_SCRATCH0_MODE_RECOVERY | \ + PMC_SCRATCH0_MODE_BOOTLOADER | \ + PMC_SCRATCH0_MODE_PAYLOAD) +#define APBDEV_PMC_BLINK_TIMER 0x40 +#define PMC_BLINK_ON(n) ((n & 0x7FFF)) +#define PMC_BLINK_FORCE BIT(15) +#define PMC_BLINK_OFF(n) ((u32)(n & 0xFFFF) << 16) +#define APBDEV_PMC_SCRATCH1 0x54 +#define APBDEV_PMC_SCRATCH20 0xA0 // ODM data/config scratch. +#define APBDEV_PMC_SECURE_SCRATCH4 0xC0 +#define APBDEV_PMC_SECURE_SCRATCH5 0xC4 +#define APBDEV_PMC_PWR_DET_VAL 0xE4 +#define PMC_PWR_DET_33V_SDMMC1 BIT(12) +#define PMC_PWR_DET_33V_AUDIO_HV BIT(18) +#define PMC_PWR_DET_33V_GPIO BIT(21) +#define APBDEV_PMC_DDR_PWR 0xE8 +#define APBDEV_PMC_USB_AO 0xF0 +#define APBDEV_PMC_CRYPTO_OP 0xF4 +#define PMC_CRYPTO_OP_SE_ENABLE 0 +#define PMC_CRYPTO_OP_SE_DISABLE 1 +#define APBDEV_PMC_PLLP_WB0_OVERRIDE 0xF8 +#define PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE_ENABLE BIT(11) +#define PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE BIT(12) +#define APBDEV_PMC_SCRATCH33 0x120 +#define APBDEV_PMC_SCRATCH37 0x130 +#define PMC_SCRATCH37_KERNEL_PANIC_MAGIC 0x4E415054 // "TPAN" +#define APBDEV_PMC_SCRATCH39 0x138 +#define APBDEV_PMC_SCRATCH40 0x13C +#define APBDEV_PMC_OSC_EDPD_OVER 0x1A4 +#define PMC_OSC_EDPD_OVER_OSC_CTRL_OVER BIT(22) +#define APBDEV_PMC_CLK_OUT_CNTRL 0x1A8 +#define PMC_CLK_OUT_CNTRL_CLK1_FORCE_EN BIT(2) +#define PMC_CLK_OUT_CNTRL_CLK2_FORCE_EN BIT(10) +#define PMC_CLK_OUT_CNTRL_CLK3_FORCE_EN BIT(18) +#define PMC_CLK_OUT_CNTRL_CLK1_SRC_SEL(src) (((src) & 3) << 6) +#define PMC_CLK_OUT_CNTRL_CLK2_SRC_SEL(src) (((src) & 3) << 14) +#define PMC_CLK_OUT_CNTRL_CLK3_SRC_SEL(src) (((src) & 3) << 22) +#define OSC_DIV1 0 +#define OSC_DIV2 1 +#define OSC_DIV4 2 +#define OSC_CAR 3 +#define APBDEV_PMC_RST_STATUS 0x1B4 +#define PMC_RST_STATUS_MASK 7 +#define PMC_RST_STATUS_POR 0 +#define PMC_RST_STATUS_WATCHDOG 1 +#define PMC_RST_STATUS_SENSOR 2 +#define PMC_RST_STATUS_SW_MAIN 3 +#define PMC_RST_STATUS_LP0 4 +#define PMC_RST_STATUS_AOTAG 5 +#define APBDEV_PMC_IO_DPD_REQ 0x1B8 +#define PMC_IO_DPD_REQ_DPD_IDLE (0 << 30u) +#define PMC_IO_DPD_REQ_DPD_OFF (1 << 30u) +#define PMC_IO_DPD_REQ_DPD_ON (2 << 30u) +#define APBDEV_PMC_IO_DPD2_REQ 0x1C0 +#define APBDEV_PMC_VDDP_SEL 0x1CC +#define APBDEV_PMC_DDR_CFG 0x1D0 +#define APBDEV_PMC_SECURE_SCRATCH6 0x224 +#define APBDEV_PMC_SECURE_SCRATCH7 0x228 +#define APBDEV_PMC_SCRATCH45 0x234 +#define APBDEV_PMC_SCRATCH46 0x238 +#define APBDEV_PMC_SCRATCH49 0x244 +#define APBDEV_PMC_SCRATCH52 0x250 +#define APBDEV_PMC_SCRATCH53 0x254 +#define APBDEV_PMC_SCRATCH54 0x258 +#define APBDEV_PMC_SCRATCH55 0x25C +#define APBDEV_PMC_TSC_MULT 0x2B4 +#define APBDEV_PMC_STICKY_BITS 0x2C0 +#define PMC_STICKY_BITS_HDA_LPBK_DIS BIT(0) +#define APBDEV_PMC_SEC_DISABLE2 0x2C4 +#define APBDEV_PMC_WEAK_BIAS 0x2C8 +#define APBDEV_PMC_REG_SHORT 0x2CC +#define APBDEV_PMC_SEC_DISABLE3 0x2D8 +#define APBDEV_PMC_SECURE_SCRATCH21 0x334 +#define PMC_FUSE_PRIVATEKEYDISABLE_TZ_STICKY_BIT BIT(4) +#define APBDEV_PMC_SECURE_SCRATCH22 0x338 // AArch32 reset address. +#define APBDEV_PMC_SECURE_SCRATCH32 0x360 +#define APBDEV_PMC_SECURE_SCRATCH34 0x368 // AArch64 reset address. +#define APBDEV_PMC_SECURE_SCRATCH35 0x36C // AArch64 reset hi-address. +#define APBDEV_PMC_SECURE_SCRATCH49 0x3A4 +#define APBDEV_PMC_CNTRL2 0x440 +#define PMC_CNTRL2_WAKE_INT_EN BIT(0) +#define PMC_CNTRL2_WAKE_DET_EN BIT(9) +#define PMC_CNTRL2_SYSCLK_ORRIDE BIT(10) +#define PMC_CNTRL2_HOLD_CKE_LOW_EN BIT(12) +#define PMC_CNTRL2_ALLOW_PULSE_WAKE BIT(14) +#define APBDEV_PMC_FUSE_CONTROL 0x450 +#define PMC_FUSE_CONTROL_PS18_LATCH_SET BIT(8) +#define PMC_FUSE_CONTROL_PS18_LATCH_CLR BIT(9) +#define APBDEV_PMC_IO_DPD3_REQ 0x45C +#define APBDEV_PMC_IO_DPD4_REQ 0x464 +#define APBDEV_PMC_UTMIP_PAD_CFG1 0x4C4 +#define APBDEV_PMC_UTMIP_PAD_CFG3 0x4CC +#define APBDEV_PMC_DDR_CNTRL 0x4E4 +#define APBDEV_PMC_SEC_DISABLE4 0x5B0 +#define APBDEV_PMC_SEC_DISABLE5 0x5B4 +#define APBDEV_PMC_SEC_DISABLE6 0x5B8 +#define APBDEV_PMC_SEC_DISABLE7 0x5BC +#define APBDEV_PMC_SEC_DISABLE8 0x5C0 +#define APBDEV_PMC_SEC_DISABLE9 0x5C4 +#define APBDEV_PMC_SEC_DISABLE10 0x5C8 +#define APBDEV_PMC_SCRATCH188 0x810 +#define APBDEV_PMC_SCRATCH190 0x818 +#define APBDEV_PMC_SCRATCH200 0x840 +#define APBDEV_PMC_SCRATCH201 0x844 +#define APBDEV_PMC_SCRATCH250 0x908 +#define APBDEV_PMC_SECURE_SCRATCH108 0xB08 +#define APBDEV_PMC_SECURE_SCRATCH109 0xB0C +#define APBDEV_PMC_SECURE_SCRATCH110 0xB10 +#define APBDEV_PMC_SECURE_SCRATCH112 0xB18 +#define APBDEV_PMC_SECURE_SCRATCH113 0xB1C +#define APBDEV_PMC_SECURE_SCRATCH114 0xB20 +#define APBDEV_PMC_SECURE_SCRATCH119 0xB34 + +// Only in T210B01. +#define APBDEV_PMC_SCRATCH_WRITE_DISABLE0 0xA48 +#define APBDEV_PMC_SCRATCH_WRITE_DISABLE1 0xA4C +#define APBDEV_PMC_SCRATCH_WRITE_DISABLE2 0xA50 +#define APBDEV_PMC_SCRATCH_WRITE_DISABLE3 0xA54 +#define APBDEV_PMC_SCRATCH_WRITE_DISABLE4 0xA58 +#define APBDEV_PMC_SCRATCH_WRITE_DISABLE5 0xA5C +#define APBDEV_PMC_SCRATCH_WRITE_DISABLE6 0xA60 +#define APBDEV_PMC_SCRATCH_WRITE_DISABLE7 0xA64 +#define APBDEV_PMC_SCRATCH_WRITE_DISABLE8 0xA68 +#define APBDEV_PMC_LED_BREATHING_CTRL 0xB48 +#define PMC_LED_BREATHING_CTRL_ENABLE BIT(0) +#define PMC_LED_BREATHING_CTRL_COUNTER1_EN BIT(1) +#define APBDEV_PMC_LED_BREATHING_SLOPE_STEPS 0xB4C +#define APBDEV_PMC_LED_BREATHING_ON_COUNTER 0xB50 +#define APBDEV_PMC_LED_BREATHING_OFF_COUNTER1 0xB54 +#define APBDEV_PMC_LED_BREATHING_OFF_COUNTER0 0xB58 +#define PMC_LED_BREATHING_COUNTER_HZ 32768 +#define APBDEV_PMC_LED_BREATHING_STATUS 0xB5C +#define PMC_LED_BREATHING_FSM_STATUS_MASK 0x7 +#define PMC_LED_BREATHING_FSM_STS_IDLE 0 +#define PMC_LED_BREATHING_FSM_STS_UP_RAMP 1 +#define PMC_LED_BREATHING_FSM_STS_PLATEAU 2 +#define PMC_LED_BREATHING_FSM_STS_DOWN_RAMP 3 +#define PMC_LED_BREATHING_FSM_STS_SHORT_LOW_PERIOD 4 +#define PMC_LED_BREATHING_FSM_STS_LONG_LOW_PERIOD 5 +#define APBDEV_PMC_TZRAM_PWR_CNTRL 0xBE8 +#define PMC_TZRAM_PWR_CNTRL_SD BIT(0) +#define APBDEV_PMC_TZRAM_SEC_DISABLE 0xBEC +#define APBDEV_PMC_TZRAM_NON_SEC_DISABLE 0xBF0 +#define PMC_TZRAM_DISABLE_REG_WRITE BIT(0) +#define PMC_TZRAM_DISABLE_REG_READ BIT(1) typedef enum _pmc_sec_lock_t { - PMC_SEC_LOCK_MISC = BIT(0), - PMC_SEC_LOCK_LP0_PARAMS = BIT(1), - PMC_SEC_LOCK_RST_VECTOR = BIT(2), - PMC_SEC_LOCK_CARVEOUTS = BIT(3), - PMC_SEC_LOCK_TZ_CMAC_W = BIT(4), - PMC_SEC_LOCK_TZ_CMAC_R = BIT(5), - PMC_SEC_LOCK_TZ_KEK_W = BIT(6), - PMC_SEC_LOCK_TZ_KEK_R = BIT(7), - PMC_SEC_LOCK_SE_SRK = BIT(8), + PMC_SEC_LOCK_MISC = BIT(0), + PMC_SEC_LOCK_LP0_PARAMS = BIT(1), + PMC_SEC_LOCK_RST_VECTOR = BIT(2), + PMC_SEC_LOCK_CARVEOUTS = BIT(3), + PMC_SEC_LOCK_TZ_CMAC_W = BIT(4), + PMC_SEC_LOCK_TZ_CMAC_R = BIT(5), + PMC_SEC_LOCK_TZ_KEK_W = BIT(6), + PMC_SEC_LOCK_TZ_KEK_R = BIT(7), + PMC_SEC_LOCK_SE_SRK = BIT(8), + PMC_SEC_LOCK_SE2_SRK_B01 = BIT(9), + PMC_SEC_LOCK_MISC_B01 = BIT(10), + PMC_SEC_LOCK_CARVEOUTS_L4T = BIT(11), + PMC_SEC_LOCK_LP0_PARAMS_B01 = BIT(12), } pmc_sec_lock_t; typedef enum _pmc_power_rail_t diff --git a/bdk/soc/t210.h b/bdk/soc/t210.h index ac703ef..eaf59df 100644 --- a/bdk/soc/t210.h +++ b/bdk/soc/t210.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2018 naehrwert +* Copyright (c) 2018-2023 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,202 +20,252 @@ #include -#define BOOTROM_BASE 0x100000 -#define IRAM_BASE 0x40000000 -#define HOST1X_BASE 0x50000000 -#define BPMP_CACHE_BASE 0x50040000 -#define DISPLAY_A_BASE 0x54200000 -#define DSI_BASE 0x54300000 -#define VIC_BASE 0x54340000 -#define TSEC_BASE 0x54500000 -#define SOR1_BASE 0x54580000 -#define ICTLR_BASE 0x60004000 -#define TMR_BASE 0x60005000 -#define CLOCK_BASE 0x60006000 -#define FLOW_CTLR_BASE 0x60007000 -#define AHBDMA_BASE 0x60008000 -#define SYSREG_BASE 0x6000C000 -#define SB_BASE (SYSREG_BASE + 0x200) -#define GPIO_BASE 0x6000D000 -#define GPIO_1_BASE (GPIO_BASE) -#define GPIO_2_BASE (GPIO_BASE + 0x100) -#define GPIO_3_BASE (GPIO_BASE + 0x200) -#define GPIO_4_BASE (GPIO_BASE + 0x300) -#define GPIO_5_BASE (GPIO_BASE + 0x400) -#define GPIO_6_BASE (GPIO_BASE + 0x500) -#define GPIO_7_BASE (GPIO_BASE + 0x600) -#define GPIO_8_BASE (GPIO_BASE + 0x700) -#define EXCP_VEC_BASE 0x6000F000 -#define IPATCH_BASE 0x6001DC00 -#define APBDMA_BASE 0x60020000 -#define APB_MISC_BASE 0x70000000 -#define PINMUX_AUX_BASE 0x70003000 -#define UART_BASE 0x70006000 -#define PWM_BASE 0x7000A000 -#define RTC_BASE 0x7000E000 -#define PMC_BASE 0x7000E400 -#define SYSCTR0_BASE 0x700F0000 -#define FUSE_BASE 0x7000F800 -#define KFUSE_BASE 0x7000FC00 -#define SE_BASE 0x70012000 -#define MC_BASE 0x70019000 -#define EMC_BASE 0x7001B000 -#define EMC0_BASE 0x7001E000 -#define EMC1_BASE 0x7001F000 -#define XUSB_HOST_BASE 0x70090000 +#define IROM_BASE 0x100000 +#define IRAM_BASE 0x40000000 +#define HOST1X_BASE 0x50000000 +#define BPMP_CACHE_BASE 0x50040000 +#define MSELECT_BASE 0x50060000 +#define DPAUX1_BASE 0x54040000 +#define TSEC2_BASE 0x54100000 +#define DISPLAY_A_BASE 0x54200000 +#define DISPLAY_B_BASE 0x54240000 +#define DSI_BASE 0x54300000 +#define VIC_BASE 0x54340000 +#define NVJPG_BASE 0x54380000 +#define NVDEC_BASE 0x54480000 +#define NVENC_BASE 0x544C0000 +#define TSEC_BASE 0x54500000 +#define SOR1_BASE 0x54580000 +#define GPU_BASE 0x57000000 +#define GPU_USER_BASE 0x58000000 +#define RES_SEMAPH_BASE 0x60001000 +#define ARB_SEMAPH_BASE 0x60002000 +#define ARB_PRI_BASE 0x60003000 +#define ICTLR_BASE 0x60004000 +#define TMR_BASE 0x60005000 +#define CLOCK_BASE 0x60006000 +#define FLOW_CTLR_BASE 0x60007000 +#define AHBDMA_BASE 0x60008000 +#define SYSREG_BASE 0x6000C000 +#define SB_BASE (SYSREG_BASE + 0x200) +#define ACTMON_BASE 0x6000C800 +#define GPIO_BASE 0x6000D000 +#define EXCP_VEC_BASE 0x6000F000 +#define IPATCH_BASE 0x6001DC00 +#define APBDMA_BASE 0x60020000 +#define VGPIO_BASE 0x60024000 +#define APB_MISC_BASE 0x70000000 +#define PINMUX_AUX_BASE 0x70003000 +#define UART_BASE 0x70006000 +#define PWM_BASE 0x7000A000 +#define I2C_BASE 0x7000C000 +#define RTC_BASE 0x7000E000 +#define PMC_BASE 0x7000E400 +#define FUSE_BASE 0x7000F800 +#define KFUSE_BASE 0x7000FC00 +#define SE_BASE 0x70012000 +#define TSENSOR_BASE 0x70014000 +#define ATOMICS_BASE 0x70016000 +#define MC_BASE 0x70019000 +#define EMC_BASE 0x7001B000 +#define EMC0_BASE 0x7001E000 +#define EMC1_BASE 0x7001F000 +#define XUSB_HOST_BASE 0x70090000 #define XUSB_PADCTL_BASE 0x7009F000 -#define XUSB_DEV_BASE 0x700D0000 -#define MIPI_CAL_BASE 0x700E3000 -#define CL_DVFS_BASE 0x70110000 -#define I2S_BASE 0x702D1000 -#define ADMA_BASE 0x702E2000 -#define TZRAM_BASE 0x7C010000 -#define USB_BASE 0x7D000000 -#define USB_OTG_BASE USB_BASE -#define USB1_BASE 0x7D004000 +#define XUSB_DEV_BASE 0x700D0000 +#define SDMMC_BASE 0x700B0000 +#define SOC_THERM_BASE 0x700E2000 +#define MIPI_CAL_BASE 0x700E3000 +#define SYSCTR0_BASE 0x700F0000 +#define SYSCTR1_BASE 0x70100000 +#define CL_DVFS_BASE 0x70110000 +#define APE_BASE 0x702C0000 +#define AHUB_BASE 0x702D0000 +#define ADMAIF_BASE 0x702D0000 +#define AXBAR_BASE 0x702D0800 +#define I2S_BASE 0x702D1000 +#define ADMA_BASE 0x702E2000 +#define AMC_BASE 0x702EF000 +#define SE2_BASE 0x70412000 +#define SE_PKA1_BASE 0x70420000 +#define TZRAM_BASE 0x7C010000 +#define TZRAM_SIZE 0x10000 +#define TZRAM_T210B01_SIZE 0x3C000 +#define USB_BASE 0x7D000000 +#define USB_OTG_BASE USB_BASE +#define USB1_BASE 0x7D004000 +#define EMEM_BASE 0x80000000 -#define _REG(base, off) *(vu32 *)((base) + (off)) +#define MMIO_REG32(base, off) *(vu32 *)((base) + (off)) -#define HOST1X(off) _REG(HOST1X_BASE, off) -#define BPMP_CACHE_CTRL(off) _REG(BPMP_CACHE_BASE, off) -#define DISPLAY_A(off) _REG(DISPLAY_A_BASE, off) -#define DSI(off) _REG(DSI_BASE, off) -#define VIC(off) _REG(VIC_BASE, off) -#define TSEC(off) _REG(TSEC_BASE, off) -#define SOR1(off) _REG(SOR1_BASE, off) -#define ICTLR(cidx, off) _REG(ICTLR_BASE + (0x100 * (cidx)), off) -#define TMR(off) _REG(TMR_BASE, off) -#define CLOCK(off) _REG(CLOCK_BASE, off) -#define FLOW_CTLR(off) _REG(FLOW_CTLR_BASE, off) -#define SYSREG(off) _REG(SYSREG_BASE, off) -#define AHB_GIZMO(off) _REG(SYSREG_BASE, off) -#define SB(off) _REG(SB_BASE, off) -#define GPIO(off) _REG(GPIO_BASE, off) -#define GPIO_1(off) _REG(GPIO_1_BASE, off) -#define GPIO_2(off) _REG(GPIO_2_BASE, off) -#define GPIO_3(off) _REG(GPIO_3_BASE, off) -#define GPIO_4(off) _REG(GPIO_4_BASE, off) -#define GPIO_5(off) _REG(GPIO_5_BASE, off) -#define GPIO_6(off) _REG(GPIO_6_BASE, off) -#define GPIO_7(off) _REG(GPIO_7_BASE, off) -#define GPIO_8(off) _REG(GPIO_8_BASE, off) -#define EXCP_VEC(off) _REG(EXCP_VEC_BASE, off) -#define APB_MISC(off) _REG(APB_MISC_BASE, off) -#define PINMUX_AUX(off) _REG(PINMUX_AUX_BASE, off) -#define PWM(off) _REG(PWM_BASE, off) -#define RTC(off) _REG(RTC_BASE, off) -#define PMC(off) _REG(PMC_BASE, off) -#define SYSCTR0(off) _REG(SYSCTR0_BASE, off) -#define FUSE(off) _REG(FUSE_BASE, off) -#define KFUSE(off) _REG(KFUSE_BASE, off) -#define SE(off) _REG(SE_BASE, off) -#define MC(off) _REG(MC_BASE, off) -#define EMC(off) _REG(EMC_BASE, off) -#define EMC_CH0(off) _REG(EMC0_BASE, off) -#define EMC_CH1(off) _REG(EMC1_BASE, off) -#define XUSB_HOST(off) _REG(XUSB_HOST_BASE, off) -#define XUSB_PADCTL(off) _REG(XUSB_PADCTL_BASE, off) -#define XUSB_DEV(off) _REG(XUSB_DEV_BASE, off) -#define XUSB_DEV_XHCI(off) _REG(XUSB_DEV_BASE, off) -#define XUSB_DEV_PCI(off) _REG(XUSB_DEV_BASE + 0x8000, off) -#define XUSB_DEV_DEV(off) _REG(XUSB_DEV_BASE + 0x9000, off) -#define MIPI_CAL(off) _REG(MIPI_CAL_BASE, off) -#define CL_DVFS(off) _REG(CL_DVFS_BASE, off) -#define I2S(off) _REG(I2S_BASE, off) -#define ADMA(off) _REG(ADMA_BASE, off) -#define USB(off) _REG(USB_BASE, off) -#define USB1(off) _REG(USB1_BASE, off) -#define TEST_REG(off) _REG(0x0, off) +#define HOST1X(off) MMIO_REG32(HOST1X_BASE, off) +#define BPMP_CACHE_CTRL(off) MMIO_REG32(BPMP_CACHE_BASE, off) +#define MSELECT(off) MMIO_REG32(MSELECT_BASE, off) +#define DPAUX1(off) MMIO_REG32(DPAUX1_BASE, off) +#define TSEC2(off) MMIO_REG32(TSEC2_BASE, off) +#define DISPLAY_A(off) MMIO_REG32(DISPLAY_A_BASE, off) +#define DISPLAY_B(off) MMIO_REG32(DISPLAY_B_BASE, off) +#define DSI(off) MMIO_REG32(DSI_BASE, off) +#define VIC(off) MMIO_REG32(VIC_BASE, off) +#define NVJPG(off) MMIO_REG32(NVJPG_BASE, off) +#define NVDEC(off) MMIO_REG32(NVDEC_BASE, off) +#define NVENC(off) MMIO_REG32(NVENC_BASE, off) +#define TSEC(off) MMIO_REG32(TSEC_BASE, off) +#define SOR1(off) MMIO_REG32(SOR1_BASE, off) +#define GPU(off) MMIO_REG32(GPU_BASE, off) +#define GPU_USER(off) MMIO_REG32(GPU_USER_BASE, off) +#define ARB_PRI(off) MMIO_REG32(ARB_PRI_BASE, off) +#define ICTLR(cidx, off) MMIO_REG32(ICTLR_BASE + (0x100 * (cidx)), off) +#define TMR(off) MMIO_REG32(TMR_BASE, off) +#define CLOCK(off) MMIO_REG32(CLOCK_BASE, off) +#define FLOW_CTLR(off) MMIO_REG32(FLOW_CTLR_BASE, off) +#define AHBDMA(off) MMIO_REG32(AHBDMA_BASE, off) +#define SYSREG(off) MMIO_REG32(SYSREG_BASE, off) +#define AHB_GIZMO(off) MMIO_REG32(SYSREG_BASE, off) +#define SB(off) MMIO_REG32(SB_BASE, off) +#define ACTMON(off) MMIO_REG32(ACTMON_BASE, off) +#define GPIO(off) MMIO_REG32(GPIO_BASE, off) +#define EXCP_VEC(off) MMIO_REG32(EXCP_VEC_BASE, off) +#define APBDMA(off) MMIO_REG32(APBDMA_BASE, off) +#define VGPIO(off) MMIO_REG32(VGPIO_BASE, off) +#define APB_MISC(off) MMIO_REG32(APB_MISC_BASE, off) +#define PINMUX_AUX(off) MMIO_REG32(PINMUX_AUX_BASE, off) +#define PWM(off) MMIO_REG32(PWM_BASE, off) +#define RTC(off) MMIO_REG32(RTC_BASE, off) +#define PMC(off) MMIO_REG32(PMC_BASE, off) +#define SYSCTR0(off) MMIO_REG32(SYSCTR0_BASE, off) +#define SYSCTR1(off) MMIO_REG32(SYSCTR1_BASE, off) +#define FUSE(off) MMIO_REG32(FUSE_BASE, off) +#define KFUSE(off) MMIO_REG32(KFUSE_BASE, off) +#define SE(off) MMIO_REG32(SE_BASE, off) +#define MC(off) MMIO_REG32(MC_BASE, off) +#define EMC(off) MMIO_REG32(EMC_BASE, off) +#define EMC_CH0(off) MMIO_REG32(EMC0_BASE, off) +#define EMC_CH1(off) MMIO_REG32(EMC1_BASE, off) +#define XUSB_HOST(off) MMIO_REG32(XUSB_HOST_BASE, off) +#define XUSB_PADCTL(off) MMIO_REG32(XUSB_PADCTL_BASE, off) +#define XUSB_DEV(off) MMIO_REG32(XUSB_DEV_BASE, off) +#define XUSB_DEV_XHCI(off) MMIO_REG32(XUSB_DEV_BASE, off) +#define XUSB_DEV_PCI(off) MMIO_REG32(XUSB_DEV_BASE + 0x8000, off) +#define XUSB_DEV_DEV(off) MMIO_REG32(XUSB_DEV_BASE + 0x9000, off) +#define MIPI_CAL(off) MMIO_REG32(MIPI_CAL_BASE, off) +#define CL_DVFS(off) MMIO_REG32(CL_DVFS_BASE, off) +#define I2S(off) MMIO_REG32(I2S_BASE, off) +#define ADMA(off) MMIO_REG32(ADMA_BASE, off) +#define AMC(off) MMIO_REG32(AMC_BASE, off) +#define SE2(off) MMIO_REG32(SE2_BASE, off) +#define SE_PKA1(off) MMIO_REG32(SE_PKA1_BASE, off) +#define USB(off) MMIO_REG32(USB_BASE, off) +#define USB1(off) MMIO_REG32(USB1_BASE, off) +#define TEST_REG(off) MMIO_REG32(0x0, off) -/* HOST1X registers. */ -#define HOST1X_CH0_SYNC_BASE 0x2100 -#define HOST1X_CH0_SYNC_SYNCPT_9 (HOST1X_CH0_SYNC_BASE + 0xFA4) -#define HOST1X_CH0_SYNC_SYNCPT_160 (HOST1X_CH0_SYNC_BASE + 0x1200) +/* HOST1X v3 registers. */ +#define HOST1X_CH0_SYNC_BASE 0x2100 +#define HOST1X_CH0_SYNC_SYNCPT_BASE (HOST1X_CH0_SYNC_BASE + 0xF80) +#define HOST1X_CH0_SYNC_SYNCPT_9 (HOST1X_CH0_SYNC_SYNCPT_BASE + 0x24) +#define HOST1X_CH0_SYNC_SYNCPT_160 (HOST1X_CH0_SYNC_SYNCPT_BASE + 0x280) /*! EVP registers. */ -#define EVP_CPU_RESET_VECTOR 0x100 -#define EVP_COP_RESET_VECTOR 0x200 -#define EVP_COP_UNDEF_VECTOR 0x204 -#define EVP_COP_SWI_VECTOR 0x208 +#define EVP_CPU_RESET_VECTOR 0x100 +#define EVP_COP_RESET_VECTOR 0x200 +#define EVP_COP_UNDEF_VECTOR 0x204 +#define EVP_COP_SWI_VECTOR 0x208 #define EVP_COP_PREFETCH_ABORT_VECTOR 0x20C -#define EVP_COP_DATA_ABORT_VECTOR 0x210 -#define EVP_COP_RSVD_VECTOR 0x214 -#define EVP_COP_IRQ_VECTOR 0x218 -#define EVP_COP_FIQ_VECTOR 0x21C -#define EVP_COP_IRQ_STS 0x220 +#define EVP_COP_DATA_ABORT_VECTOR 0x210 +#define EVP_COP_RSVD_VECTOR 0x214 +#define EVP_COP_IRQ_VECTOR 0x218 +#define EVP_COP_FIQ_VECTOR 0x21C +#define EVP_COP_IRQ_STS 0x220 /*! Primary Interrupt Controller registers. */ -#define PRI_ICTLR_FIR 0x14 -#define PRI_ICTLR_FIR_SET 0x18 -#define PRI_ICTLR_FIR_CLR 0x1C -#define PRI_ICTLR_CPU_IER 0x20 -#define PRI_ICTLR_CPU_IER_SET 0x24 -#define PRI_ICTLR_CPU_IER_CLR 0x28 +#define PRI_ICTLR_ISR 0x10 +#define PRI_ICTLR_FIR 0x14 +#define PRI_ICTLR_FIR_SET 0x18 +#define PRI_ICTLR_FIR_CLR 0x1C +#define PRI_ICTLR_CPU_IER 0x20 +#define PRI_ICTLR_CPU_IER_SET 0x24 +#define PRI_ICTLR_CPU_IER_CLR 0x28 #define PRI_ICTLR_CPU_IEP_CLASS 0x2C -#define PRI_ICTLR_COP_IER 0x30 -#define PRI_ICTLR_COP_IER_SET 0x34 -#define PRI_ICTLR_COP_IER_CLR 0x38 +#define PRI_ICTLR_COP_IER 0x30 +#define PRI_ICTLR_COP_IER_SET 0x34 +#define PRI_ICTLR_COP_IER_CLR 0x38 #define PRI_ICTLR_COP_IEP_CLASS 0x3C +/* Arbiter registers */ +#define ARB_PRIO_CPU_PRIORITY 0x0 +#define ARB_PRIO_COP_PRIORITY 0x4 +#define ARB_PRIO_VCP_PRIORITY 0x8 +#define ARB_PRIO_DMA_PRIORITY 0xC +#define ARB_PRIO_UCQ_PRIORITY 0x10 + /*! AHB Gizmo registers. */ -#define AHB_ARBITRATION_PRIORITY_CTRL 0x8 -#define PRIORITY_CTRL_WEIGHT(x) (((x) & 7) << 29) -#define PRIORITY_SELECT_USB BIT(6) // USB-OTG. -#define PRIORITY_SELECT_USB2 BIT(18) // USB-HSIC. -#define PRIORITY_SELECT_USB3 BIT(17) // XUSB. -#define AHB_GIZMO_AHB_MEM 0x10 -#define AHB_MEM_ENB_FAST_REARBITRATE BIT(2) -#define AHB_MEM_DONT_SPLIT_AHB_WR BIT(7) -#define AHB_MEM_IMMEDIATE BIT(18) -#define AHB_GIZMO_APB_DMA 0x14 -#define AHB_GIZMO_USB 0x20 -#define AHB_GIZMO_SDMMC4 0x48 -#define AHB_GIZMO_USB2 0x7C -#define AHB_GIZMO_USB3 0x80 -#define AHB_GIZMO_IMMEDIATE BIT(18) -#define AHB_ARBITRATION_XBAR_CTRL 0xE0 -#define AHB_AHB_MEM_PREFETCH_CFG3 0xE4 -#define AHB_AHB_MEM_PREFETCH_CFG4 0xE8 -#define AHB_AHB_MEM_PREFETCH_CFG1 0xF0 -#define AHB_AHB_MEM_PREFETCH_CFG2 0xF4 -#define MST_ID(x) (((x) & 0x1F) << 26) -#define MEM_PREFETCH_AHBDMA_MST_ID MST_ID(5) -#define MEM_PREFETCH_USB_MST_ID MST_ID(6) // USB-OTG. -#define MEM_PREFETCH_USB2_MST_ID MST_ID(18) // USB-HSIC. -#define MEM_PREFETCH_USB3_MST_ID MST_ID(17) // XUSB. -#define MEM_PREFETCH_ADDR_BNDRY(x) (((x) & 0xF) << 21) -#define MEM_PREFETCH_ENABLE BIT(31) -#define AHB_AHB_SPARE_REG 0x110 +#define AHB_ARBITRATION_PRIORITY_CTRL 0x8 +#define PRIORITY_CTRL_WEIGHT(x) (((x) & 7) << 29) +#define PRIORITY_SELECT_USB BIT(6) // USB-OTG. +#define PRIORITY_SELECT_USB2 BIT(18) // USB-HSIC. +#define PRIORITY_SELECT_USB3 BIT(17) // XUSB. +#define AHB_GIZMO_AHB_MEM 0x10 +#define AHB_MEM_ENB_FAST_REARBITRATE BIT(2) +#define AHB_MEM_DONT_SPLIT_AHB_WR BIT(7) +#define AHB_MEM_IMMEDIATE BIT(18) +#define AHB_GIZMO_APB_DMA 0x14 +#define AHB_GIZMO_USB 0x20 +#define AHB_GIZMO_SDMMC4 0x48 +#define AHB_GIZMO_USB2 0x7C +#define AHB_GIZMO_USB3 0x80 // Doesn't exist on T21x?? +#define AHB_GIZMO_IMMEDIATE BIT(18) +#define AHB_ARBITRATION_XBAR_CTRL 0xE0 +#define AHB_AHB_MEM_PREFETCH_CFG3 0xE4 +#define AHB_AHB_MEM_PREFETCH_CFG4 0xE8 +#define AHB_AHB_MEM_PREFETCH_CFG1 0xF0 +#define AHB_AHB_MEM_PREFETCH_CFG2 0xF4 +#define MST_ID(x) (((x) & 0x1F) << 26) +#define MEM_PREFETCH_AHBDMA_MST_ID MST_ID(5) +#define MEM_PREFETCH_USB_MST_ID MST_ID(6) // USB-OTG. Doesn't exist on T210B01. +#define MEM_PREFETCH_USB2_MST_ID MST_ID(18) // USB-HSIC. Doesn't exist on T210B01. +#define MEM_PREFETCH_USB3_MST_ID MST_ID(17) // XUSB. Doesn't exist on T210B01. +#define MEM_PREFETCH_ADDR_BNDRY(x) (((x) & 0xF) << 21) +#define MEM_PREFETCH_ENABLE BIT(31) +#define AHB_ARBITRATION_AHB_MEM_WRQUE_MST_ID 0xFC +#define MEM_WRQUE_SE_MST_ID BIT(14) +#define AHB_AHB_SPARE_REG 0x110 /*! Misc registers. */ -#define APB_MISC_PP_STRAPPING_OPT_A 0x08 -#define APB_MISC_PP_PINMUX_GLOBAL 0x40 -#define APB_MISC_GP_HIDREV 0x804 -#define GP_HIDREV_MAJOR_T210 0x1 -#define GP_HIDREV_MAJOR_T210B01 0x2 -#define APB_MISC_GP_AUD_MCLK_CFGPADCTRL 0x8F4 -#define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34 -#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98 -#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL 0xA9C -#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL 0xAB4 +#define APB_MISC_PP_STRAPPING_OPT_A 0x8 +#define APB_MISC_PP_PINMUX_GLOBAL 0x40 +#define APB_MISC_GP_HIDREV 0x804 +#define GP_HIDREV_MAJOR_T210 0x1 +#define GP_HIDREV_MAJOR_T210B01 0x2 +#define APB_MISC_GP_ASDBGREG 0x810 +#define APB_MISC_GP_TRANSACTOR_SCRATCH 0x864 +#define APB_MISC_GP_AVP_TRANSACTOR_SCRATCH 0x880 +#define APB_MISC_GP_CPU0_TRANSACTOR_SCRATCH 0x884 +#define APB_MISC_GP_CPU1_TRANSACTOR_SCRATCH 0x888 +#define APB_MISC_GP_CPU2_TRANSACTOR_SCRATCH 0x88C +#define APB_MISC_GP_CPU3_TRANSACTOR_SCRATCH 0x890 +#define APB_MISC_GP_AUD_MCLK_CFGPADCTRL 0x8F4 +#define APB_MISC_GP_LCD_BL_PWM_CFGPADCTRL 0xA34 +#define APB_MISC_GP_SDMMC1_PAD_CFGPADCTRL 0xA98 +#define APB_MISC_GP_EMMC2_PAD_CFGPADCTRL 0xA9C +#define APB_MISC_GP_EMMC4_PAD_CFGPADCTRL 0xAB4 #define APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL 0xABC -#define APB_MISC_GP_DSI_PAD_CONTROL 0xAC0 -#define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64 -#define APB_MISC_GP_WIFI_RST_CFGPADCTRL 0xB68 +#define APB_MISC_GP_DSI_PAD_CONTROL 0xAC0 +#define APB_MISC_GP_WIFI_EN_CFGPADCTRL 0xB64 +#define APB_MISC_GP_WIFI_RST_CFGPADCTRL 0xB68 /*! Secure boot registers. */ -#define SB_CSR 0x0 -#define SB_CSR_NS_RST_VEC_WR_DIS BIT(1) -#define SB_CSR_PIROM_DISABLE BIT(4) -#define SB_AA64_RESET_LOW 0x30 -#define SB_AA64_RST_AARCH64_MODE_EN BIT(0) -#define SB_AA64_RESET_HIGH 0x34 +#define SB_CSR 0x0 +#define SB_CSR_NS_RST_VEC_WR_DIS BIT(1) +#define SB_CSR_PIROM_DISABLE BIT(4) +#define SB_AA64_RESET_LOW 0x30 +#define SB_AA64_RST_AARCH64_MODE_EN BIT(0) +#define SB_AA64_RESET_HIGH 0x34 /*! SOR registers. */ -#define SOR_NV_PDISP_SOR_DP_HDCP_BKSV_LSB 0x1E8 -#define SOR_NV_PDISP_SOR_TMDS_HDCP_BKSV_LSB 0x21C -#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_MSB 0x208 -#define SOR_NV_PDISP_SOR_TMDS_HDCP_CN_LSB 0x20C +#define SOR_DP_HDCP_BKSV_LSB 0x1E8 +#define SOR_TMDS_HDCP_BKSV_LSB 0x21C +#define SOR_TMDS_HDCP_CN_MSB 0x208 +#define SOR_TMDS_HDCP_CN_LSB 0x20C /*! RTC registers. */ #define APBDEV_RTC_SECONDS 0x8 @@ -222,42 +273,28 @@ #define APBDEV_RTC_MILLI_SECONDS 0x10 /*! SYSCTR0 registers. */ -#define SYSCTR0_CNTFID0 0x20 -#define SYSCTR0_CNTCR 0x00 -#define SYSCTR0_COUNTERID0 0xFE0 -#define SYSCTR0_COUNTERID1 0xFE4 -#define SYSCTR0_COUNTERID2 0xFE8 -#define SYSCTR0_COUNTERID3 0xFEC -#define SYSCTR0_COUNTERID4 0xFD0 -#define SYSCTR0_COUNTERID5 0xFD4 -#define SYSCTR0_COUNTERID6 0xFD8 -#define SYSCTR0_COUNTERID7 0xFDC -#define SYSCTR0_COUNTERID8 0xFF0 -#define SYSCTR0_COUNTERID9 0xFF4 -#define SYSCTR0_COUNTERID10 0xFF8 -#define SYSCTR0_COUNTERID11 0xFFC +#define SYSCTR0_CNTCR 0x00 +#define SYSCTR0_CNTFID0 0x20 +#define SYSCTR0_COUNTERS_BASE 0xFD0 +#define SYSCTR0_COUNTERS 12 +#define SYSCTR0_COUNTERID0 0xFE0 +#define SYSCTR0_COUNTERID1 0xFE4 +#define SYSCTR0_COUNTERID2 0xFE8 +#define SYSCTR0_COUNTERID3 0xFEC +#define SYSCTR0_COUNTERID4 0xFD0 +#define SYSCTR0_COUNTERID5 0xFD4 +#define SYSCTR0_COUNTERID6 0xFD8 +#define SYSCTR0_COUNTERID7 0xFDC +#define SYSCTR0_COUNTERID8 0xFF0 +#define SYSCTR0_COUNTERID9 0xFF4 +#define SYSCTR0_COUNTERID10 0xFF8 +#define SYSCTR0_COUNTERID11 0xFFC -/*! TMR registers. */ -#define TIMERUS_CNTR_1US (0x10 + 0x0) -#define TIMERUS_USEC_CFG (0x10 + 0x4) -#define TIMER_TMR8_TMR_PTV 0x78 -#define TIMER_TMR9_TMR_PTV 0x80 -#define TIMER_PER_EN BIT(30) -#define TIMER_EN BIT(31) -#define TIMER_TMR8_TMR_PCR 0x7C -#define TIMER_TMR9_TMR_PCR 0x8C -#define TIMER_INTR_CLR BIT(30) - -#define TIMER_WDT4_CONFIG (0x100 + 0x80) -#define TIMER_SRC(TMR) ((TMR) & 0xF) -#define TIMER_PER(PER) (((PER) & 0xFF) << 4) -#define TIMER_SYSRESET_EN BIT(14) -#define TIMER_PMCRESET_EN BIT(15) -#define TIMER_WDT4_COMMAND (0x108 + 0x80) -#define TIMER_START_CNT BIT(0) -#define TIMER_CNT_DISABLE BIT(1) -#define TIMER_WDT4_UNLOCK_PATTERN (0x10C + 0x80) -#define TIMER_MAGIC_PTRN 0xC45A +/*! IPATCH registers. */ +#define IPATCH_CAM_VALID 0x0 +#define IPATCH_CAM_BASE 0x4 +#define IPATCH_CAM(i) (IPATCH_CAM_BASE + (i) * 4) +#define IPATCH_CAM_ENTRIES 12 /*! I2S registers. */ #define I2S1_CG 0x88 @@ -283,25 +320,60 @@ #define EMC_HEKA_UPD BIT(30) /*! Flow controller registers. */ -#define FLOW_CTLR_HALT_COP_EVENTS 0x4 -#define HALT_COP_GIC_IRQ BIT(9) -#define HALT_COP_LIC_IRQ BIT(11) -#define HALT_COP_SEC BIT(23) -#define HALT_COP_MSEC BIT(24) -#define HALT_COP_USEC BIT(25) -#define HALT_COP_JTAG BIT(28) -#define HALT_COP_WAIT_EVENT BIT(30) -#define HALT_COP_STOP_UNTIL_IRQ BIT(31) -#define HALT_COP_MAX_CNT 0xFF -#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0 -#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14 -#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C -#define FLOW_CTLR_HALT_CPU3_EVENTS 0x24 -#define FLOW_CTLR_CPU0_CSR 0x8 -#define FLOW_CTLR_CPU1_CSR 0x18 -#define FLOW_CTLR_CPU2_CSR 0x20 -#define FLOW_CTLR_CPU3_CSR 0x28 -#define FLOW_CTLR_RAM_REPAIR 0x40 -#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98 +#define FLOW_CTLR_HALT_COP_EVENTS 0x4 +#define FLOW_CTLR_HALT_CPU0_EVENTS 0x0 +#define FLOW_CTLR_HALT_CPU1_EVENTS 0x14 +#define FLOW_CTLR_HALT_CPU2_EVENTS 0x1C +#define FLOW_CTLR_HALT_CPU3_EVENTS 0x24 +#define HALT_GIC_IRQ BIT(9) +#define HALT_LIC_IRQ BIT(11) +#define HALT_SEC BIT(23) +#define HALT_MSEC BIT(24) +#define HALT_USEC BIT(25) +#define HALT_JTAG BIT(28) +#define HALT_MODE_NONE (0 << 29u) +#define HALT_MODE_RUN_AND_INT (1 << 29u) +#define HALT_MODE_WAITEVENT (2 << 29u) +#define HALT_MODE_WAITEVENT_AND_INT (3 << 29u) +#define HALT_MODE_STOP_UNTIL_IRQ (4 << 29u) +#define HALT_MODE_STOP_UNTIL_IRQ_AND_INT (5 << 29u) +#define HALT_MODE_STOP_UNTIL_EVENT_AND_IRQ (6 << 29u) +#define HALT_MAX_CNT 0xFF +#define FLOW_CTLR_COP_CSR 0xC +#define FLOW_CTLR_CPU0_CSR 0x8 +#define FLOW_CTLR_CPU1_CSR 0x18 +#define FLOW_CTLR_CPU2_CSR 0x20 +#define FLOW_CTLR_CPU3_CSR 0x28 +#define CSR_ENABLE BIT(0) +#define CSR_WAIT_WFI_NONE (0 << 8u) +#define CSR_WAIT_WFI_CPU0 (BIT(0) << 8u) +#define CSR_ENABLE_EXT_CPU_ONLY (0 << 12u) +#define CSR_ENABLE_EXT_CPU_NCPU (1 << 12u) +#define CSR_ENABLE_EXT_CPU_RAIL (2 << 12u) +#define CSR_EVENT_FLAG BIT(14) +#define CSR_INTR_FLAG BIT(15) +#define CSR_HALT BIT(22) +#define FLOW_CTLR_CPU_PWR_CSR 0x38 +#define CPU_PWR_RAIL_STS_MASK (3 << 1u) +#define CPU_PWR_RAIL_OFF 0 +#define FLOW_CTLR_RAM_REPAIR 0x40 +#define RAM_REPAIR_REQ BIT(0) +#define RAM_REPAIR_STS BIT(1) +#define FLOW_CTLR_BPMP_CLUSTER_CONTROL 0x98 +#define CLUSTER_CTRL_ACTIVE_SLOW BIT(0) +/* MSelect registers */ +#define MSELECT_CONFIG 0x00 +#define MSELECT_CFG_ERR_RESP_EN_PCIE BIT(24) +#define MSELECT_CFG_ERR_RESP_EN_GPU BIT(25) +#define MSELECT_CFG_WRAP_TO_INCR_BPMP BIT(27) +#define MSELECT_CFG_WRAP_TO_INCR_PCIE BIT(28) +#define MSELECT_CFG_WRAP_TO_INCR_GPU BIT(29) + +/* NVDEC registers */ +#define NVDEC_SA_KEYSLOT_FALCON 0x2100 +#define NVDEC_SA_KEYSLOT_TZ 0x2104 +#define NVDEC_SA_KEYSLOT_OTF 0x210C +#define NVDEC_SA_KEYSLOT_GLOBAL_RW 0x2118 +#define NVDEC_VPR_ALL_OTF_GOTO_VPR 0x211C #endif diff --git a/bdk/soc/timer.c b/bdk/soc/timer.c new file mode 100644 index 0000000..786f123 --- /dev/null +++ b/bdk/soc/timer.c @@ -0,0 +1,123 @@ +/* + * Timer/Watchdog driver for Tegra X1 + * + * Copyright (c) 2019 CTCaer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include +#include +#include +#include +#include + +#define EXCP_TYPE_ADDR 0x4003FFF8 +#define EXCP_TYPE_WDT 0x544457 // "WDT". + +#define USE_RTC_TIMER + +u32 get_tmr_s() +{ + (void)RTC(APBDEV_RTC_MILLI_SECONDS); + return (u32)RTC(APBDEV_RTC_SECONDS); +} + +u32 get_tmr_ms() +{ + // The registers must be read with the following order: + // RTC_MILLI_SECONDS (0x10) -> RTC_SHADOW_SECONDS (0xC) + return (u32)(RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000)); +} + +u32 get_tmr_us() +{ + return (u32)TMR(TIMERUS_CNTR_1US); +} + +void msleep(u32 ms) +{ +#ifdef USE_RTC_TIMER + u32 start = (u32)RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000); + // Casting to u32 is important! + while (((u32)(RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000)) - start) <= ms) + ; +#else + bpmp_msleep(ms); +#endif +} + +void usleep(u32 us) +{ +#ifdef USE_RTC_TIMER + u32 start = (u32)TMR(TIMERUS_CNTR_1US); + + // Check if timer is at upper limits and use BPMP sleep so it doesn't wake up immediately. + if ((start + us) < start) + bpmp_usleep(us); + else + while ((u32)(TMR(TIMERUS_CNTR_1US) - start) <= us) // Casting to u32 is important! + ; +#else + bpmp_usleep(us); +#endif +} + +// Instruction wait loop. Each loop is 3 cycles (SUBS+BGT). Usage: isleep(ILOOP(instr)). Base 408MHz: 7.35ns. +void __attribute__((target("arm"))) isleep(u32 is) +{ + asm volatile( "0:" "SUBS %[is_cnt], #1;" "BGT 0b;" : [is_cnt] "+r" (is)); +} + +void timer_usleep(u32 us) +{ + TMR(TIMER_TMR8_TMR_PTV) = TIMER_EN | us; + + irq_wait_event(IRQ_TMR8); + + TMR(TIMER_TMR8_TMR_PCR) = TIMER_INTR_CLR; +} + +void watchdog_start(u32 us, u32 mode) +{ + // WDT4 is for BPMP. + TMR(TIMER_WDT4_UNLOCK_PATTERN) = TIMER_MAGIC_PTRN; + TMR(TIMER_TMR9_TMR_PTV) = TIMER_EN | TIMER_PER_EN | us; + TMR(TIMER_WDT4_CONFIG) = TIMER_SRC(9) | TIMER_PER(1) | mode; + TMR(TIMER_WDT4_COMMAND) = TIMER_START_CNT; +} + +void watchdog_end() +{ + // WDT4 is for BPMP. + TMR(TIMER_TMR9_TMR_PTV) = 0; + TMR(TIMER_WDT4_UNLOCK_PATTERN) = TIMER_MAGIC_PTRN; + TMR(TIMER_WDT4_COMMAND) = TIMER_START_CNT; // Re-arm to clear any interrupts. + TMR(TIMER_WDT4_COMMAND) = TIMER_CNT_DISABLE; + TMR(TIMER_TMR9_TMR_PCR) = TIMER_INTR_CLR; +} + +void watchdog_handle() +{ + // Disable watchdog and clear its interrupts. + watchdog_end(); + + // Set watchdog magic. + *(u32 *)EXCP_TYPE_ADDR = EXCP_TYPE_WDT; +} + +bool watchdog_fired() +{ + // Return if watchdog got fired. User handles clearing. + return (*(u32 *)EXCP_TYPE_ADDR == EXCP_TYPE_WDT); +} diff --git a/bdk/soc/timer.h b/bdk/soc/timer.h new file mode 100644 index 0000000..800eaac --- /dev/null +++ b/bdk/soc/timer.h @@ -0,0 +1,64 @@ +/* + * Timer/Watchdog driver for Tegra X1 + * + * Copyright (c) 2019 CTCaer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef _TIMER_H_ +#define _TIMER_H_ + +#include + +// TMR registers. +#define TIMERUS_CNTR_1US (0x10 + 0x0) +#define TIMERUS_USEC_CFG (0x10 + 0x4) +#define TIMER_TMR8_TMR_PTV 0x78 +#define TIMER_TMR9_TMR_PTV 0x80 +#define TIMER_PER_EN BIT(30) +#define TIMER_EN BIT(31) +#define TIMER_TMR8_TMR_PCR 0x7C +#define TIMER_TMR9_TMR_PCR 0x8C +#define TIMER_INTR_CLR BIT(30) + +// WDT registers. +#define TIMER_WDT4_CONFIG (0x100 + 0x80) +#define TIMER_SRC(TMR) ((TMR) & 0xF) +#define TIMER_PER(PER) (((PER) & 0xFF) << 4) +#define TIMER_IRQENABL_EN BIT(12) +#define TIMER_FIQENABL_EN BIT(13) +#define TIMER_SYSRESET_EN BIT(14) +#define TIMER_PMCRESET_EN BIT(15) +#define TIMER_WDT4_COMMAND (0x108 + 0x80) +#define TIMER_START_CNT BIT(0) +#define TIMER_CNT_DISABLE BIT(1) +#define TIMER_WDT4_UNLOCK_PATTERN (0x10C + 0x80) +#define TIMER_MAGIC_PTRN 0xC45A + +u32 get_tmr_us(); +u32 get_tmr_ms(); +u32 get_tmr_s(); +void usleep(u32 us); +void msleep(u32 ms); +#define ILOOP(is) ((is) / 3) +void isleep(u32 is); + +void timer_usleep(u32 us); + +void watchdog_start(u32 us, u32 mode); +void watchdog_end(); +void watchdog_handle(); +bool watchdog_fired(); + +#endif diff --git a/bdk/soc/uart.c b/bdk/soc/uart.c index 582bca1..c76c66e 100644 --- a/bdk/soc/uart.c +++ b/bdk/soc/uart.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert -* Copyright (c) 2019-2020 CTCaer +* Copyright (c) 2019-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,62 +17,75 @@ #include #include +#include #include -#include /* UART A, B, C, D and E. */ -static const u32 uart_baseoff[5] = { 0, 0x40, 0x200, 0x300, 0x400 }; +static const u16 _uart_base_offsets[5] = { 0, 0x40, 0x200, 0x300, 0x400 }; -void uart_init(u32 idx, u32 baud) +void uart_init(u32 idx, u32 baud, u32 mode) { - uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]); + uart_t *uart = (uart_t *)(UART_BASE + (u32)_uart_base_offsets[idx]); // Make sure no data is being sent. - uart_wait_idle(idx, UART_TX_IDLE); + if (!(mode & (UART_MCR_CTS_EN | UART_MCR_DTR))) + uart_wait_xfer(idx, UART_TX_IDLE); // Set clock. bool clk_type = clock_uart_use_src_div(idx, baud); + // 2 STOP bits for rates > 1M. (Reduced efficiency but less errors on high baudrates). + u32 uart_lcr_stop = baud > 1000000 ? UART_LCR_STOP : 0; + // Misc settings. u32 div = clk_type ? ((8 * baud + 408000000) / (16 * baud)) : 1; // DIV_ROUND_CLOSEST. uart->UART_IER_DLAB = 0; // Disable interrupts. - uart->UART_LCR = UART_LCR_DLAB | UART_LCR_WORD_LENGTH_8; // Enable DLAB & set 8n1 mode. - uart->UART_THR_DLAB = (u8)div; // Divisor latch LSB. + uart->UART_LCR = UART_LCR_DLAB | UART_LCR_WORD_LENGTH_8; // Enable DLAB & set 8n1 mode. + uart->UART_THR_DLAB = (u8)div; // Divisor latch LSB. uart->UART_IER_DLAB = (u8)(div >> 8); // Divisor latch MSB. - uart->UART_LCR = UART_LCR_WORD_LENGTH_8; // Disable DLAB. + + // Disable DLAB and set STOP bits setting if applicable. + uart->UART_LCR = uart_lcr_stop | UART_LCR_WORD_LENGTH_8; (void)uart->UART_SPR; - // Setup and flush fifo. + // Enable fifo. uart->UART_IIR_FCR = UART_IIR_FCR_EN_FIFO; (void)uart->UART_SPR; usleep(20); - uart->UART_MCR = 0; // Disable hardware flow control. + + // Disable hardware flow control. + uart->UART_MCR = 0; usleep(96); + + // Clear tx/rx fifos. uart->UART_IIR_FCR = UART_IIR_FCR_EN_FIFO | UART_IIR_FCR_TX_CLR | UART_IIR_FCR_RX_CLR; + // Set hardware flow control. + uart->UART_MCR = mode; + // Wait 3 symbols for baudrate change. usleep(3 * ((baud + 999999) / baud)); - uart_wait_idle(idx, UART_TX_IDLE | UART_RX_IDLE); + uart_wait_xfer(idx, UART_TX_IDLE | UART_RX_RDYR); } -void uart_wait_idle(u32 idx, u32 which) +void uart_wait_xfer(u32 idx, u32 which) { - uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]); + uart_t *uart = (uart_t *)(UART_BASE + (u32)_uart_base_offsets[idx]); if (UART_TX_IDLE & which) { while (!(uart->UART_LSR & UART_LSR_TMTY)) ; } - if (UART_RX_IDLE & which) + if (UART_RX_RDYR & which) { while (uart->UART_LSR & UART_LSR_RDR) - ; + (void)uart->UART_THR_DLAB; } } void uart_send(u32 idx, const u8 *buf, u32 len) { - uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]); + uart_t *uart = (uart_t *)(UART_BASE + (u32)_uart_base_offsets[idx]); for (u32 i = 0; i != len; i++) { @@ -84,32 +97,37 @@ void uart_send(u32 idx, const u8 *buf, u32 len) u32 uart_recv(u32 idx, u8 *buf, u32 len) { - uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]); + uart_t *uart = (uart_t *)(UART_BASE + (u32)_uart_base_offsets[idx]); + bool manual_mode = uart->UART_MCR & UART_MCR_RTS; u32 timeout = get_tmr_us() + 250; u32 i; + if (manual_mode) + uart->UART_MCR &= ~UART_MCR_RTS; + for (i = 0; ; i++) { - while (!(uart->UART_LSR & UART_LSR_RDR)) - { - if (timeout < get_tmr_us()) - break; - if (len && len < i) - break; - } - if (timeout < get_tmr_us()) + if (len && len <= i) break; + while (!(uart->UART_LSR & UART_LSR_RDR)) + if (timeout < get_tmr_us()) + goto out; + buf[i] = uart->UART_THR_DLAB; timeout = get_tmr_us() + 250; } - return i ? (len ? (i - 1) : i) : 0; +out: + if (manual_mode) + uart->UART_MCR |= UART_MCR_RTS; + + return i; } void uart_invert(u32 idx, bool enable, u32 invert_mask) { - uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]); + uart_t *uart = (uart_t *)(UART_BASE + (u32)_uart_base_offsets[idx]); if (enable) uart->UART_IRDA_CSR |= invert_mask; @@ -118,9 +136,17 @@ void uart_invert(u32 idx, bool enable, u32 invert_mask) (void)uart->UART_SPR; } +void uart_set_mode(u32 idx, u32 mode) +{ + uart_t *uart = (uart_t *)(UART_BASE + (u32)_uart_base_offsets[idx]); + + uart->UART_MCR = mode; + (void)uart->UART_SPR; +} + u32 uart_get_IIR(u32 idx) { - uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]); + uart_t *uart = (uart_t *)(UART_BASE + (u32)_uart_base_offsets[idx]); u32 iir = uart->UART_IIR_FCR & UART_IIR_INT_MASK; @@ -132,7 +158,7 @@ u32 uart_get_IIR(u32 idx) void uart_set_IIR(u32 idx) { - uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]); + uart_t *uart = (uart_t *)(UART_BASE + (u32)_uart_base_offsets[idx]); uart->UART_IER_DLAB &= ~UART_IER_DLAB_IE_EORD; (void)uart->UART_SPR; @@ -142,20 +168,20 @@ void uart_set_IIR(u32 idx) void uart_empty_fifo(u32 idx, u32 which) { - uart_t *uart = (uart_t *)(UART_BASE + uart_baseoff[idx]); + uart_t *uart = (uart_t *)(UART_BASE + (u32)_uart_base_offsets[idx]); uart->UART_MCR = 0; (void)uart->UART_SPR; usleep(96); - uart->UART_IIR_FCR = UART_IIR_FCR_EN_FIFO | UART_IIR_FCR_TX_CLR | UART_IIR_FCR_RX_CLR; + uart->UART_IIR_FCR = UART_IIR_FCR_EN_FIFO | which; (void)uart->UART_SPR; usleep(18); u32 tries = 0; if (UART_IIR_FCR_TX_CLR & which) { - while (tries < 10 && uart->UART_LSR & UART_LSR_TMTY) + while (tries < 10 && !(uart->UART_LSR & UART_LSR_TMTY)) { tries++; usleep(100); @@ -165,10 +191,31 @@ void uart_empty_fifo(u32 idx, u32 which) if (UART_IIR_FCR_RX_CLR & which) { - while (tries < 10 && !uart->UART_LSR & UART_LSR_RDR) + while (tries < 10 && (uart->UART_LSR & UART_LSR_RDR)) { tries++; usleep(100); } } } + +#ifdef DEBUG_UART_PORT +#include +#include + +#include + +void uart_printf(const char *fmt, ...) +{ + va_list ap; + + //! NOTE: Anything more and it will hang. Heap usage is out of the question. + char text[256]; + + va_start(ap, fmt); + s_vprintf(text, fmt, ap); + va_end(ap); + + uart_send(DEBUG_UART_PORT, (u8 *)text, strlen(text)); +} +#endif diff --git a/bdk/soc/uart.h b/bdk/soc/uart.h index 6a4c073..a24d5c9 100644 --- a/bdk/soc/uart.h +++ b/bdk/soc/uart.h @@ -28,33 +28,33 @@ #define BAUD_115200 115200 -#define UART_TX_IDLE 0x1 -#define UART_RX_IDLE 0x2 +#define UART_TX_IDLE BIT(0) +#define UART_RX_RDYR BIT(1) -#define UART_TX_FIFO_FULL 0x100 -#define UART_RX_FIFO_EMPTY 0x200 +#define UART_TX_FIFO_FULL BIT(8) +#define UART_RX_FIFO_EMPTY BIT(9) -#define UART_INVERT_RXD 0x01 -#define UART_INVERT_TXD 0x02 -#define UART_INVERT_CTS 0x04 -#define UART_INVERT_RTS 0x08 +#define UART_INVERT_RXD BIT(0) +#define UART_INVERT_TXD BIT(1) +#define UART_INVERT_CTS BIT(2) +#define UART_INVERT_RTS BIT(3) -#define UART_IER_DLAB_IE_EORD 0x20 +#define UART_IER_DLAB_IE_EORD BIT(5) -#define UART_LCR_DLAB 0x80 -#define UART_LCR_STOP 0x4 #define UART_LCR_WORD_LENGTH_8 0x3 +#define UART_LCR_STOP BIT(2) +#define UART_LCR_DLAB BIT(7) -#define UART_LSR_RDR 0x1 -#define UART_LSR_THRE 0x20 -#define UART_LSR_TMTY 0x40 -#define UART_LSR_FIFOE 0x80 +#define UART_LSR_RDR BIT(0) +#define UART_LSR_THRE BIT(5) +#define UART_LSR_TMTY BIT(6) +#define UART_LSR_FIFOE BIT(7) -#define UART_IIR_FCR_TX_CLR 0x4 -#define UART_IIR_FCR_RX_CLR 0x2 -#define UART_IIR_FCR_EN_FIFO 0x1 +#define UART_IIR_FCR_EN_FIFO BIT(0) +#define UART_IIR_FCR_RX_CLR BIT(1) +#define UART_IIR_FCR_TX_CLR BIT(2) -#define UART_IIR_NO_INT BIT(0) +#define UART_IIR_NO_INT BIT(0) #define UART_IIR_INT_MASK 0xF /* Custom returned interrupt results. Actual interrupts are -1 */ #define UART_IIR_NOI 0 // No interrupt. @@ -65,8 +65,12 @@ #define UART_IIR_REDI 5 // Receiver end of data interrupt. #define UART_IIR_RDTI 7 // Receiver data timeout interrupt. -#define UART_MCR_RTS 0x2 -#define UART_MCR_DTR 0x1 +#define UART_MCR_DTR BIT(0) +#define UART_MCR_RTS BIT(1) +#define UART_MCR_CTS_EN BIT(5) +#define UART_MCR_RTS_EN BIT(6) + +#define UART_FIFO_SIZE 36 typedef struct _uart_t { @@ -86,13 +90,29 @@ typedef struct _uart_t /* 0x3C */ vu32 UART_ASR; } uart_t; -void uart_init(u32 idx, u32 baud); -void uart_wait_idle(u32 idx, u32 which); +//! TODO: Commented out modes are not supported yet. +typedef enum _uart_mode_t +{ + UART_AO_TX_AO_RX = 0, + //UART_MN_TX_AO_RX = UART_MCR_RTS | UART_MCR_DTR, + UART_AO_TX_MN_RX = UART_MCR_RTS, // Up to 36 bytes read. + //UART_MN_TX_AO_RX = UART_MCR_DTR, + //UART_HW_TX_HW_RX = UART_MCR_RTS_EN | UART_MCR_CTS_EN, + UART_AO_TX_HW_RX = UART_MCR_RTS_EN, + //UART_HW_TX_AO_RX = UART_MCR_CTS_EN, +} uart_mode_t; + +void uart_init(u32 idx, u32 baud, u32 mode); +void uart_wait_xfer(u32 idx, u32 which); void uart_send(u32 idx, const u8 *buf, u32 len); u32 uart_recv(u32 idx, u8 *buf, u32 len); void uart_invert(u32 idx, bool enable, u32 invert_mask); +void uart_set_mode(u32 idx, u32 mode); u32 uart_get_IIR(u32 idx); void uart_set_IIR(u32 idx); void uart_empty_fifo(u32 idx, u32 which); +#ifdef DEBUG_UART_PORT +void uart_printf(const char *fmt, ...); +#endif #endif diff --git a/bdk/storage/emmc.c b/bdk/storage/emmc.c new file mode 100644 index 0000000..b1ab03d --- /dev/null +++ b/bdk/storage/emmc.c @@ -0,0 +1,227 @@ +/* + * Copyright (c) 2018 naehrwert + * Copyright (c) 2019-2024 CTCaer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +#include "emmc.h" +#include +#include +#include +#include + +static u16 emmc_errors[3] = { 0 }; // Init and Read/Write errors. +static u32 emmc_mode = EMMC_MMC_HS400; + +sdmmc_t emmc_sdmmc; +sdmmc_storage_t emmc_storage; +FATFS emmc_fs; + +#ifdef BDK_EMUMMC_ENABLE +int emummc_storage_read(u32 sector, u32 num_sectors, void *buf); +int emummc_storage_write(u32 sector, u32 num_sectors, void *buf); +#endif + +void emmc_error_count_increment(u8 type) +{ + switch (type) + { + case EMMC_ERROR_INIT_FAIL: + emmc_errors[0]++; + break; + case EMMC_ERROR_RW_FAIL: + emmc_errors[1]++; + break; + case EMMC_ERROR_RW_RETRY: + emmc_errors[2]++; + break; + } +} + +u16 *emmc_get_error_count() +{ + return emmc_errors; +} + +u32 emmc_get_mode() +{ + return emmc_mode; +} + +void emmc_end() { sdmmc_storage_end(&emmc_storage); } + +int emmc_init_retry(bool power_cycle) +{ + u32 bus_width = SDMMC_BUS_WIDTH_8; + u32 type = SDHCI_TIMING_MMC_HS400; + + // Power cycle SD eMMC. + if (power_cycle) + { + emmc_mode--; + emmc_end(); + } + + // Get init parameters. + switch (emmc_mode) + { + case EMMC_INIT_FAIL: // Reset to max. + return 0; + case EMMC_1BIT_HS52: + bus_width = SDMMC_BUS_WIDTH_1; + type = SDHCI_TIMING_MMC_HS52; + break; + case EMMC_8BIT_HS52: + type = SDHCI_TIMING_MMC_HS52; + break; + case EMMC_MMC_HS200: + type = SDHCI_TIMING_MMC_HS200; + break; + case EMMC_MMC_HS400: + type = SDHCI_TIMING_MMC_HS400; + break; + default: + emmc_mode = EMMC_MMC_HS400; + } + + return sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, bus_width, type); +} + +bool emmc_initialize(bool power_cycle) +{ + // Reset mode in case of previous failure. + if (emmc_mode == EMMC_INIT_FAIL) + emmc_mode = EMMC_MMC_HS400; + + if (power_cycle) + emmc_end(); + + int res = !emmc_init_retry(false); + + while (true) + { + if (!res) + return true; + else + { + emmc_errors[EMMC_ERROR_INIT_FAIL]++; + + if (emmc_mode == EMMC_INIT_FAIL) + break; + else + res = !emmc_init_retry(true); + } + } + + emmc_end(); + + return false; +} + +int emmc_set_partition(u32 partition) { return sdmmc_storage_set_mmc_partition(&emmc_storage, partition); } + +void emmc_gpt_parse(link_t *gpt) +{ + gpt_t *gpt_buf = (gpt_t *)zalloc(GPT_NUM_BLOCKS * EMMC_BLOCKSIZE); + +#ifdef BDK_EMUMMC_ENABLE + emummc_storage_read(GPT_FIRST_LBA, GPT_NUM_BLOCKS, gpt_buf); +#else + sdmmc_storage_read(&emmc_storage, GPT_FIRST_LBA, GPT_NUM_BLOCKS, gpt_buf); +#endif + + // Check if no GPT or more than max allowed entries. + if (memcmp(&gpt_buf->header.signature, "EFI PART", 8) || gpt_buf->header.num_part_ents > 128) + goto out; + + for (u32 i = 0; i < gpt_buf->header.num_part_ents; i++) + { + emmc_part_t *part = (emmc_part_t *)zalloc(sizeof(emmc_part_t)); + + if (gpt_buf->entries[i].lba_start < gpt_buf->header.first_use_lba) + continue; + + part->index = i; + part->lba_start = gpt_buf->entries[i].lba_start; + part->lba_end = gpt_buf->entries[i].lba_end; + part->attrs = gpt_buf->entries[i].attrs; + + // ASCII conversion. Copy only the LSByte of the UTF-16LE name. + for (u32 j = 0; j < 36; j++) + part->name[j] = gpt_buf->entries[i].name[j]; + part->name[35] = 0; + + list_append(gpt, &part->link); + } + +out: + free(gpt_buf); +} + +void emmc_gpt_free(link_t *gpt) +{ + LIST_FOREACH_SAFE(iter, gpt) + free(CONTAINER_OF(iter, emmc_part_t, link)); +} + +emmc_part_t *emmc_part_find(link_t *gpt, const char *name) +{ + LIST_FOREACH_ENTRY(emmc_part_t, part, gpt, link) + if (!strcmp(part->name, name)) + return part; + + return NULL; +} + +int emmc_part_read(emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf) +{ + // The last LBA is inclusive. + if (part->lba_start + sector_off > part->lba_end) + return 0; + +#ifdef BDK_EMUMMC_ENABLE + return emummc_storage_read(part->lba_start + sector_off, num_sectors, buf); +#else + return sdmmc_storage_read(&emmc_storage, part->lba_start + sector_off, num_sectors, buf); +#endif +} + +int emmc_part_write(emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf) +{ + // The last LBA is inclusive. + if (part->lba_start + sector_off > part->lba_end) + return 0; + +#ifdef BDK_EMUMMC_ENABLE + return emummc_storage_write(part->lba_start + sector_off, num_sectors, buf); +#else + return sdmmc_storage_write(&emmc_storage, part->lba_start + sector_off, num_sectors, buf); +#endif +} + +void nx_emmc_get_autorcm_masks(u8 *mod0, u8 *mod1) +{ + if (fuse_read_hw_state() == FUSE_NX_HW_STATE_PROD) + { + *mod0 = 0xF7; + *mod1 = 0x86; + } + else + { + *mod0 = 0x37; + *mod1 = 0x84; + } +} diff --git a/nyx/nyx_gui/storage/nx_emmc.h b/bdk/storage/emmc.h similarity index 53% rename from nyx/nyx_gui/storage/nx_emmc.h rename to bdk/storage/emmc.h index f89f526..904852d 100644 --- a/nyx/nyx_gui/storage/nx_emmc.h +++ b/bdk/storage/emmc.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2019-2020 CTCaer + * Copyright (c) 2019-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,17 +15,34 @@ * along with this program. If not, see . */ -#ifndef _NX_EMMC_H_ -#define _NX_EMMC_H_ +#ifndef _EMMC_H_ +#define _EMMC_H_ #include -#include #include #include -#define NX_GPT_FIRST_LBA 1 -#define NX_GPT_NUM_BLOCKS 33 -#define NX_EMMC_BLOCKSIZE 512 +#include + +#define GPT_FIRST_LBA 1 +#define GPT_NUM_BLOCKS 33 +#define EMMC_BLOCKSIZE SDMMC_DAT_BLOCKSIZE + +enum +{ + EMMC_INIT_FAIL = 0, + EMMC_1BIT_HS52 = 1, + EMMC_8BIT_HS52 = 2, + EMMC_MMC_HS200 = 3, + EMMC_MMC_HS400 = 4, +}; + +enum +{ + EMMC_ERROR_INIT_FAIL = 0, + EMMC_ERROR_RW_FAIL = 1, + EMMC_ERROR_RW_RETRY = 2 +}; typedef struct _emmc_part_t { @@ -41,11 +58,19 @@ extern sdmmc_t emmc_sdmmc; extern sdmmc_storage_t emmc_storage; extern FATFS emmc_fs; -void nx_emmc_gpt_parse(link_t *gpt, sdmmc_storage_t *storage); -void nx_emmc_gpt_free(link_t *gpt); -emmc_part_t *nx_emmc_part_find(link_t *gpt, const char *name); -int nx_emmc_part_read(sdmmc_storage_t *storage, emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf); -int nx_emmc_part_write(sdmmc_storage_t *storage, emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf); +void emmc_error_count_increment(u8 type); +u16 *emmc_get_error_count(); +u32 emmc_get_mode(); +int emmc_init_retry(bool power_cycle); +bool emmc_initialize(bool power_cycle); +int emmc_set_partition(u32 partition); +void emmc_end(); + +void emmc_gpt_parse(link_t *gpt); +void emmc_gpt_free(link_t *gpt); +emmc_part_t *emmc_part_find(link_t *gpt, const char *name); +int emmc_part_read(emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf); +int emmc_part_write(emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf); void nx_emmc_get_autorcm_masks(u8 *mod0, u8 *mod1); diff --git a/bdk/storage/mbr_gpt.h b/bdk/storage/mbr_gpt.h index 9e0e97d..7f38108 100644 --- a/bdk/storage/mbr_gpt.h +++ b/bdk/storage/mbr_gpt.h @@ -39,40 +39,40 @@ typedef struct _mbr_part_t typedef struct _mbr_t { - u8 bootstrap[440]; - u32 signature; - u16 copy_protected; - mbr_part_t partitions[4]; - u16 boot_signature; +/* 0x000 */ u8 bootstrap[440]; +/* 0x1B8 */ u32 signature; +/* 0x1BC */ u16 copy_protected; +/* 0x1BE */ mbr_part_t partitions[4]; +/* 0x1FE */ u16 boot_signature; } __attribute__((packed)) mbr_t; typedef struct _gpt_entry_t { - u8 type_guid[0x10]; - u8 part_guid[0x10]; - u64 lba_start; - u64 lba_end; - u64 attrs; - u16 name[36]; +/* 0x00 */ u8 type_guid[0x10]; +/* 0x10 */ u8 part_guid[0x10]; +/* 0x20 */ u64 lba_start; +/* 0x28 */ u64 lba_end; +/* 0x30 */ u64 attrs; +/* 0x38 */ u16 name[36]; } gpt_entry_t; typedef struct _gpt_header_t { - u64 signature; // "EFI PART" - u32 revision; - u32 size; - u32 crc32; - u32 res1; - u64 my_lba; - u64 alt_lba; - u64 first_use_lba; - u64 last_use_lba; - u8 disk_guid[0x10]; - u64 part_ent_lba; - u32 num_part_ents; - u32 part_ent_size; - u32 part_ents_crc32; - u8 res2[420]; // Used as first 3 partition entries backup for HOS. +/* 0x00 */ u64 signature; // "EFI PART" +/* 0x08 */ u32 revision; +/* 0x0C */ u32 size; +/* 0x10 */ u32 crc32; +/* 0x14 */ u32 res1; +/* 0x18 */ u64 my_lba; +/* 0x20 */ u64 alt_lba; +/* 0x28 */ u64 first_use_lba; +/* 0x30 */ u64 last_use_lba; +/* 0x38 */ u8 disk_guid[0x10]; +/* 0x48 */ u64 part_ent_lba; +/* 0x50 */ u32 num_part_ents; +/* 0x54 */ u32 part_ent_size; +/* 0x58 */ u32 part_ents_crc32; +/* 0x5C */ u8 res2[420]; // Used as first 3 partition entries backup for HOS. } gpt_header_t; typedef struct _gpt_t diff --git a/bdk/storage/mmc.h b/bdk/storage/mmc.h index ee81e69..c7d6106 100644 --- a/bdk/storage/mmc.h +++ b/bdk/storage/mmc.h @@ -408,7 +408,10 @@ /* * BKOPS status level */ -#define EXT_CSD_BKOPS_LEVEL_2 0x2 +#define EXT_CSD_BKOPS_OK 0x0 +#define EXT_CSD_BKOPS_NON_CRITICAL 0x1 +#define EXT_CSD_BKOPS_PERF_IMPACTED 0x2 +#define EXT_CSD_BKOPS_CRITICAL 0x3 /* * BKOPS modes diff --git a/nyx/nyx_gui/storage/nx_emmc_bis.c b/bdk/storage/nx_emmc_bis.c similarity index 73% rename from nyx/nyx_gui/storage/nx_emmc_bis.c rename to bdk/storage/nx_emmc_bis.c index fae5d00..28bdc6f 100644 --- a/nyx/nyx_gui/storage/nx_emmc_bis.c +++ b/bdk/storage/nx_emmc_bis.c @@ -2,7 +2,7 @@ * eMMC BIS driver for Nintendo Switch * * Copyright (c) 2019-2020 shchmue - * Copyright (c) 2019-2021 CTCaer + * Copyright (c) 2019-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -23,9 +23,8 @@ #include #include -#include -#include "../storage/nx_emmc.h" -#include +#include +#include #include #include @@ -58,74 +57,6 @@ static emmc_part_t *system_part = NULL; static u32 *cache_lookup_tbl = (u32 *)NX_BIS_LOOKUP_ADDR; static bis_cache_t *bis_cache = (bis_cache_t *)NX_BIS_CACHE_ADDR; -static void _gf256_mul_x_le(void *block) -{ - u32 *pdata = (u32 *)block; - u32 carry = 0; - - for (u32 i = 0; i < 4; i++) - { - u32 b = pdata[i]; - pdata[i] = (b << 1) | carry; - carry = b >> 31; - } - - if (carry) - pdata[0x0] ^= 0x87; -} - -static int _nx_aes_xts_crypt_sec(u32 tweak_ks, u32 crypt_ks, u32 enc, u8 *tweak, bool regen_tweak, u32 tweak_exp, u64 sec, void *dst, void *src, u32 sec_size) -{ - u32 *pdst = (u32 *)dst; - u32 *psrc = (u32 *)src; - u32 *ptweak = (u32 *)tweak; - - if (regen_tweak) - { - for (int i = 0xF; i >= 0; i--) - { - tweak[i] = sec & 0xFF; - sec >>= 8; - } - if (!se_aes_crypt_block_ecb(tweak_ks, ENCRYPT, tweak, tweak)) - return 0; - } - - // tweak_exp allows us to use a saved tweak to reduce _gf256_mul_x_le calls. - for (u32 i = 0; i < (tweak_exp << 5); i++) - _gf256_mul_x_le(tweak); - - u8 orig_tweak[SE_KEY_128_SIZE] __attribute__((aligned(4))); - memcpy(orig_tweak, tweak, SE_KEY_128_SIZE); - - // We are assuming a 16 sector aligned size in this implementation. - for (u32 i = 0; i < (sec_size >> 4); i++) - { - for (u32 j = 0; j < 4; j++) - pdst[j] = psrc[j] ^ ptweak[j]; - - _gf256_mul_x_le(tweak); - psrc += 4; - pdst += 4; - } - - if (!se_aes_crypt_ecb(crypt_ks, enc, dst, sec_size, dst, sec_size)) - return 0; - - pdst = (u32 *)dst; - ptweak = (u32 *)orig_tweak; - for (u32 i = 0; i < (sec_size >> 4); i++) - { - for (u32 j = 0; j < 4; j++) - pdst[j] = pdst[j] ^ ptweak[j]; - - _gf256_mul_x_le(orig_tweak); - pdst += 4; - } - - return 1; -} - static int nx_emmc_bis_write_block(u32 sector, u32 count, void *buff, bool flush) { if (!system_part) @@ -137,13 +68,13 @@ static int nx_emmc_bis_write_block(u32 sector, u32 count, void *buff, bool flush u32 aligned_sector = cluster * BIS_CLUSTER_SECTORS; u32 sector_in_cluster = sector % BIS_CLUSTER_SECTORS; u32 lookup_idx = cache_lookup_tbl[cluster]; - bool is_cached = lookup_idx != BIS_CACHE_LOOKUP_TBL_EMPTY_ENTRY; + bool is_cached = lookup_idx != (u32)BIS_CACHE_LOOKUP_TBL_EMPTY_ENTRY; // Write to cached cluster. if (is_cached) { if (buff) - memcpy(bis_cache->clusters[lookup_idx].data + sector_in_cluster * NX_EMMC_BLOCKSIZE, buff, count * NX_EMMC_BLOCKSIZE); + memcpy(bis_cache->clusters[lookup_idx].data + sector_in_cluster * EMMC_BLOCKSIZE, buff, count * EMMC_BLOCKSIZE); else buff = bis_cache->clusters[lookup_idx].data; if (!bis_cache->clusters[lookup_idx].dirty) @@ -160,12 +91,12 @@ static int nx_emmc_bis_write_block(u32 sector, u32 count, void *buff, bool flush } // Encrypt cluster. - if (!_nx_aes_xts_crypt_sec(ks_tweak, ks_crypt, 1, tweak, true, sector_in_cluster, cluster, bis_cache->dma_buff, buff, count * NX_EMMC_BLOCKSIZE)) + if (!se_aes_xts_crypt_sec_nx(ks_tweak, ks_crypt, ENCRYPT, cluster, tweak, true, sector_in_cluster, bis_cache->dma_buff, buff, count * EMMC_BLOCKSIZE)) return 1; // Encryption error. // If not reading from cache, do a regular read and decrypt. if (!emu_offset) - res = nx_emmc_part_write(&emmc_storage, system_part, sector, count, bis_cache->dma_buff); + res = emmc_part_write(system_part, sector, count, bis_cache->dma_buff); else res = sdmmc_storage_write(&sd_storage, emu_offset + system_part->lba_start + sector, count, bis_cache->dma_buff); if (!res) @@ -225,7 +156,7 @@ static int nx_emmc_bis_read_block_normal(u32 sector, u32 count, void *buff) // If not reading from cache, do a regular read and decrypt. if (!emu_offset) - res = nx_emmc_part_read(&emmc_storage, system_part, sector, count, bis_cache->dma_buff); + res = emmc_part_read(system_part, sector, count, bis_cache->dma_buff); else res = sdmmc_storage_read(&sd_storage, emu_offset + system_part->lba_start + sector, count, bis_cache->dma_buff); if (!res) @@ -246,7 +177,7 @@ static int nx_emmc_bis_read_block_normal(u32 sector, u32 count, void *buff) tweak_exp = sector_in_cluster; // Maximum one cluster (1 XTS crypto block 16KB). - if (!_nx_aes_xts_crypt_sec(ks_tweak, ks_crypt, 0, tweak, regen_tweak, tweak_exp, prev_cluster, buff, bis_cache->dma_buff, count * NX_EMMC_BLOCKSIZE)) + if (!se_aes_xts_crypt_sec_nx(ks_tweak, ks_crypt, DECRYPT, prev_cluster, tweak, regen_tweak, tweak_exp, buff, bis_cache->dma_buff, count * EMMC_BLOCKSIZE)) return 1; // R/W error. prev_sector = sector + count - 1; @@ -264,9 +195,9 @@ static int nx_emmc_bis_read_block_cached(u32 sector, u32 count, void *buff) u32 lookup_idx = cache_lookup_tbl[cluster]; // Read from cached cluster. - if (lookup_idx != BIS_CACHE_LOOKUP_TBL_EMPTY_ENTRY) + if (lookup_idx != (u32)BIS_CACHE_LOOKUP_TBL_EMPTY_ENTRY) { - memcpy(buff, bis_cache->clusters[lookup_idx].data + sector_in_cluster * NX_EMMC_BLOCKSIZE, count * NX_EMMC_BLOCKSIZE); + memcpy(buff, bis_cache->clusters[lookup_idx].data + sector_in_cluster * EMMC_BLOCKSIZE, count * EMMC_BLOCKSIZE); return 0; // Success. } @@ -282,19 +213,19 @@ static int nx_emmc_bis_read_block_cached(u32 sector, u32 count, void *buff) // Read the whole cluster the sector resides in. if (!emu_offset) - res = nx_emmc_part_read(&emmc_storage, system_part, cluster_sector, BIS_CLUSTER_SECTORS, bis_cache->dma_buff); + res = emmc_part_read(system_part, cluster_sector, BIS_CLUSTER_SECTORS, bis_cache->dma_buff); else res = sdmmc_storage_read(&sd_storage, emu_offset + system_part->lba_start + cluster_sector, BIS_CLUSTER_SECTORS, bis_cache->dma_buff); if (!res) return 1; // R/W error. // Decrypt cluster. - if (!_nx_aes_xts_crypt_sec(ks_tweak, ks_crypt, 0, cache_tweak, true, 0, cluster, bis_cache->dma_buff, bis_cache->dma_buff, BIS_CLUSTER_SIZE)) + if (!se_aes_xts_crypt_sec_nx(ks_tweak, ks_crypt, DECRYPT, cluster, cache_tweak, true, 0, bis_cache->dma_buff, bis_cache->dma_buff, BIS_CLUSTER_SIZE)) return 1; // Decryption error. // Copy to cluster cache. memcpy(bis_cache->clusters[bis_cache->top_idx].data, bis_cache->dma_buff, BIS_CLUSTER_SIZE); - memcpy(buff, bis_cache->dma_buff + sector_in_cluster * NX_EMMC_BLOCKSIZE, count * NX_EMMC_BLOCKSIZE); + memcpy(buff, bis_cache->dma_buff + sector_in_cluster * EMMC_BLOCKSIZE, count * EMMC_BLOCKSIZE); // Increment cache count. bis_cache->top_idx++; @@ -320,13 +251,18 @@ int nx_emmc_bis_read(u32 sector, u32 count, void *buff) while (count) { - u32 sct_cnt = MIN(count, BIS_CLUSTER_SECTORS); + // Get sector index in cluster and use it as boundary check. + u32 cnt_max = (curr_sct % BIS_CLUSTER_SECTORS); + cnt_max = BIS_CLUSTER_SECTORS - cnt_max; + + u32 sct_cnt = MIN(count, cnt_max); // Only allow cluster sized access. + if (nx_emmc_bis_read_block(curr_sct, sct_cnt, buf)) return 0; count -= sct_cnt; curr_sct += sct_cnt; - buf += sct_cnt * NX_EMMC_BLOCKSIZE; + buf += sct_cnt * EMMC_BLOCKSIZE; } return 1; @@ -339,13 +275,18 @@ int nx_emmc_bis_write(u32 sector, u32 count, void *buff) while (count) { - u32 sct_cnt = MIN(count, BIS_CLUSTER_SECTORS); + // Get sector index in cluster and use it as boundary check. + u32 cnt_max = (curr_sct % BIS_CLUSTER_SECTORS); + cnt_max = BIS_CLUSTER_SECTORS - cnt_max; + + u32 sct_cnt = MIN(count, cnt_max); // Only allow cluster sized access. + if (nx_emmc_bis_write_block(curr_sct, sct_cnt, buf, false)) return 0; count -= sct_cnt; curr_sct += sct_cnt; - buf += sct_cnt * NX_EMMC_BLOCKSIZE; + buf += sct_cnt * EMMC_BLOCKSIZE; } return 1; diff --git a/nyx/nyx_gui/storage/nx_emmc_bis.h b/bdk/storage/nx_emmc_bis.h similarity index 94% rename from nyx/nyx_gui/storage/nx_emmc_bis.h rename to bdk/storage/nx_emmc_bis.h index 1a137fa..7cdacfc 100644 --- a/nyx/nyx_gui/storage/nx_emmc_bis.h +++ b/bdk/storage/nx_emmc_bis.h @@ -18,7 +18,7 @@ #ifndef NX_EMMC_BIS_H #define NX_EMMC_BIS_H -#include "../storage/nx_emmc.h" +#include #include typedef struct _nx_emmc_cal0_spk_t @@ -85,13 +85,13 @@ typedef struct _nx_emmc_cal0_t u8 bd_mac[6]; u8 crc16_pad4[2]; u8 rsvd2[8]; - u8 acc_offset[6]; + u16 acc_offset[3]; u8 crc16_pad5[2]; - u8 acc_scale[6]; + u16 acc_scale[3]; u8 crc16_pad6[2]; - u8 gyro_offset[6]; + u16 gyro_offset[3]; u8 crc16_pad7[2]; - u8 gyro_scale[6]; + u16 gyro_scale[3]; u8 crc16_pad8[2]; char serial_number[0x18]; u8 crc16_pad9[8]; @@ -213,19 +213,23 @@ typedef struct _nx_emmc_cal0_t // 6.0.0 and up. u8 battery_ver; - u8 crc16_pad58[0x1F]; + u8 crc16_pad58[0xF]; + + // 10.0.0 and up. + u8 touch_ic_vendor_id; + u8 crc16_pad59[0xF]; // 9.0.0 and up. - u32 home_menu_scheme_model; - u8 crc16_pad59[0xC]; + u32 color_model; + u8 crc16_pad60[0xC]; // 10.0.0 and up. u8 console_6axis_sensor_mount_type; } __attribute__((packed)) nx_emmc_cal0_t; int nx_emmc_bis_read(u32 sector, u32 count, void *buff); -int nx_emmc_bis_write(u32 sector, u32 count, void *buff); +int nx_emmc_bis_write(u32 sector, u32 count, void *buff); void nx_emmc_bis_init(emmc_part_t *part, bool enable_cache, u32 emummc_offset); void nx_emmc_bis_end(); -#endif \ No newline at end of file +#endif diff --git a/bdk/storage/nx_sd.h b/bdk/storage/nx_sd.h deleted file mode 100644 index e2b703f..0000000 --- a/bdk/storage/nx_sd.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef NX_SD_H -#define NX_SD_H - -#include -#include -#include - -enum -{ - SD_INIT_FAIL = 0, - SD_1BIT_HS25 = 1, - SD_4BIT_HS25 = 2, - SD_UHS_SDR82 = 3, - SD_UHS_SDR104 = 4 -}; - -enum -{ - SD_ERROR_INIT_FAIL = 0, - SD_ERROR_RW_FAIL = 1, - SD_ERROR_RW_RETRY = 2 -}; - -extern sdmmc_t sd_sdmmc; -extern sdmmc_storage_t sd_storage; -extern FATFS sd_fs; - -void sd_error_count_increment(u8 type); -u16 *sd_get_error_count(); -bool sd_get_card_removed(); -bool sd_get_card_initialized(); -bool sd_get_card_mounted(); -u32 sd_get_mode(); -int sd_init_retry(bool power_cycle); -bool sd_initialize(bool power_cycle); -bool sd_mount(); -void sd_unmount(); -void sd_end(); -bool sd_is_gpt(); -void *sd_file_read(const char *path, u32 *fsize); -int sd_save_to_file(void *buf, u32 size, const char *filename); - -#endif \ No newline at end of file diff --git a/bdk/storage/ramdisk.c b/bdk/storage/ramdisk.c index 315075d..3a86ebf 100644 --- a/bdk/storage/ramdisk.c +++ b/bdk/storage/ramdisk.c @@ -20,6 +20,7 @@ #include "ramdisk.h" #include +#include #include #include @@ -27,10 +28,11 @@ static u32 disk_size = 0; -int ram_disk_init(FATFS *ram_fs, u32 ramdisk_size) +int ram_disk_init(void *ram_fs, u32 ramdisk_size) { int res = 0; disk_size = ramdisk_size; + FATFS *ram_fatfs = (FATFS *)ram_fs; // If ramdisk is not raw, format it. if (ram_fs) @@ -49,7 +51,7 @@ int ram_disk_init(FATFS *ram_fs, u32 ramdisk_size) // Mount ramdisk. if (!res) - res = f_mount(ram_fs, "ram:", 1); + res = f_mount(ram_fatfs, "ram:", 1); free(buf); } diff --git a/bdk/storage/ramdisk.h b/bdk/storage/ramdisk.h index e625235..67bc0a5 100644 --- a/bdk/storage/ramdisk.h +++ b/bdk/storage/ramdisk.h @@ -19,11 +19,11 @@ #ifndef RAM_DISK_H #define RAM_DISK_H -#include +#include #define RAMDISK_CLUSTER_SZ 32768 -int ram_disk_init(FATFS *ram_fs, u32 ramdisk_size); +int ram_disk_init(void *ram_fs, u32 ramdisk_size); int ram_disk_read(u32 sector, u32 sector_count, void *buf); int ram_disk_write(u32 sector, u32 sector_count, const void *buf); diff --git a/nyx/nyx_gui/storage/nx_sd.c b/bdk/storage/sd.c similarity index 75% rename from nyx/nyx_gui/storage/nx_sd.c rename to bdk/storage/sd.c index 5037df1..3ad31fa 100644 --- a/nyx/nyx_gui/storage/nx_sd.c +++ b/bdk/storage/sd.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2023 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,17 +15,25 @@ * along with this program. If not, see . */ -#include +#include #include #include #include #include #include +#ifndef BDK_SDMMC_UHS_DDR200_SUPPORT +#define SD_DEFAULT_SPEED SD_UHS_SDR104 +#else +#define SD_DEFAULT_SPEED SD_UHS_DDR208 +#endif + static bool sd_mounted = false; static bool sd_init_done = false; +static bool insertion_event = false; static u16 sd_errors[3] = { 0 }; // Init and Read/Write errors. -static u32 sd_mode = SD_UHS_SDR104; +static u32 sd_mode = SD_DEFAULT_SPEED; + sdmmc_t sd_sdmmc; sdmmc_storage_t sd_storage; @@ -54,7 +62,7 @@ u16 *sd_get_error_count() bool sd_get_card_removed() { - if (sd_init_done && !sdmmc_get_sd_inserted()) + if (insertion_event && !sdmmc_get_sd_inserted()) return true; return false; @@ -78,7 +86,11 @@ u32 sd_get_mode() int sd_init_retry(bool power_cycle) { u32 bus_width = SDMMC_BUS_WIDTH_4; +#ifndef BDK_SDMMC_UHS_DDR200_SUPPORT u32 type = SDHCI_TIMING_UHS_SDR104; +#else + u32 type = SDHCI_TIMING_UHS_DDR200; +#endif // Power cycle SD card. if (power_cycle) @@ -92,24 +104,45 @@ int sd_init_retry(bool power_cycle) { case SD_INIT_FAIL: // Reset to max. return 0; + case SD_1BIT_HS25: bus_width = SDMMC_BUS_WIDTH_1; type = SDHCI_TIMING_SD_HS25; break; + case SD_4BIT_HS25: type = SDHCI_TIMING_SD_HS25; break; + case SD_UHS_SDR82: type = SDHCI_TIMING_UHS_SDR82; break; + case SD_UHS_SDR104: type = SDHCI_TIMING_UHS_SDR104; break; + +#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT + case SD_UHS_DDR208: + type = SDHCI_TIMING_UHS_DDR200; + break; +#endif + default: - sd_mode = SD_UHS_SDR104; + sd_mode = SD_DEFAULT_SPEED; + break; } - return sdmmc_storage_init_sd(&sd_storage, &sd_sdmmc, bus_width, type); + int res = sdmmc_storage_init_sd(&sd_storage, &sd_sdmmc, bus_width, type); + if (res) + { + sd_init_done = true; + insertion_event = true; + } + else + sd_init_done = false; + + return res; } bool sd_initialize(bool power_cycle) @@ -125,7 +158,7 @@ bool sd_initialize(bool power_cycle) return true; else if (!sdmmc_get_sd_inserted()) // SD Card is not inserted. { - sd_mode = SD_UHS_SDR104; + sd_mode = SD_DEFAULT_SPEED; break; } else @@ -146,7 +179,7 @@ bool sd_initialize(bool power_cycle) bool sd_mount() { - if (sd_mounted) + if (sd_init_done && sd_mounted) return true; int res = 0; @@ -165,8 +198,8 @@ bool sd_mount() } else { - sd_init_done = true; - res = f_mount(&sd_fs, "sd:", 1); + if (!sd_mounted) + res = f_mount(&sd_fs, "0:", 1); // Volume 0 is SD. if (res == FR_OK) { sd_mounted = true; @@ -184,19 +217,25 @@ bool sd_mount() static void _sd_deinit(bool deinit) { - if (deinit && sd_mode == SD_INIT_FAIL) - sd_mode = SD_UHS_SDR104; + if (deinit) + { + insertion_event = false; + if (sd_mode == SD_INIT_FAIL) + sd_mode = SD_DEFAULT_SPEED; + } - if (sd_init_done && sd_mounted) + if (sd_init_done) { - f_mount(NULL, "sd:", 1); - sd_mounted = false; - } - if (sd_init_done && deinit) - { - sdmmc_storage_end(&sd_storage); - sd_init_done = false; + if (sd_mounted) + f_mount(NULL, "0:", 1); // Volume 0 is SD. + + if (deinit) + { + sdmmc_storage_end(&sd_storage); + sd_init_done = false; + } } + sd_mounted = false; } void sd_unmount() { _sd_deinit(false); } @@ -210,6 +249,9 @@ bool sd_is_gpt() void *sd_file_read(const char *path, u32 *fsize) { FIL fp; + if (!sd_get_card_mounted()) + return NULL; + if (f_open(&fp, path, FA_READ) != FR_OK) return NULL; @@ -232,10 +274,13 @@ void *sd_file_read(const char *path, u32 *fsize) return buf; } -int sd_save_to_file(void *buf, u32 size, const char *filename) +int sd_save_to_file(const void *buf, u32 size, const char *filename) { FIL fp; u32 res = 0; + if (!sd_get_card_mounted()) + return FR_DISK_ERR; + res = f_open(&fp, filename, FA_CREATE_ALWAYS | FA_WRITE); if (res) { diff --git a/bdk/storage/sd.h b/bdk/storage/sd.h index 22d3359..1153996 100644 --- a/bdk/storage/sd.h +++ b/bdk/storage/sd.h @@ -1,150 +1,66 @@ /* - * Copyright (c) 2005-2007 Pierre Ossman, All Rights Reserved. - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018 naehrwert + * Copyright (c) 2018-2023 CTCaer * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or (at - * your option) any later version. - */ - -#ifndef MMC_SD_H -#define MMC_SD_H - -/* SD commands type argument response */ -/* class 0 */ -/* This is basically the same command as for MMC with some quirks. */ -#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */ -#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */ -#define SD_SWITCH_VOLTAGE 11 /* ac R1 */ -/* class 10 */ -#define SD_SWITCH 6 /* adtc [31:0] See below R1 */ -/* class 5 */ -#define SD_ERASE_WR_BLK_START 32 /* ac [31:0] data addr R1 */ -#define SD_ERASE_WR_BLK_END 33 /* ac [31:0] data addr R1 */ - -/* Application commands */ -#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */ -#define SD_APP_SD_STATUS 13 /* adtc R1 */ -#define SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */ -#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */ -#define SD_APP_SET_CLR_CARD_DETECT 42 /* adtc R1 */ -#define SD_APP_SEND_SCR 51 /* adtc R1 */ - -/* Application secure commands */ -#define SD_APP_SECURE_READ_MULTI_BLOCK 18 /* adtc R1 */ -#define SD_APP_SECURE_WRITE_MULTI_BLOCK 25 /* adtc R1 */ -#define SD_APP_SECURE_WRITE_MKB 26 /* adtc R1 */ -#define SD_APP_SECURE_ERASE 38 /* adtc R1b */ -#define SD_APP_GET_MKB 43 /* adtc [31:0] See below R1 */ -#define SD_APP_GET_MID 44 /* adtc R1 */ -#define SD_APP_SET_CER_RN1 45 /* adtc R1 */ -#define SD_APP_GET_CER_RN2 46 /* adtc R1 */ -#define SD_APP_SET_CER_RES2 47 /* adtc R1 */ -#define SD_APP_GET_CER_RES1 48 /* adtc R1 */ -#define SD_APP_CHANGE_SECURE_AREA 49 /* adtc R1b */ - -/* OCR bit definitions */ -#define SD_OCR_VDD_18 (1 << 7) /* VDD voltage 1.8 */ -#define SD_VHD_27_36 (1 << 8) /* VDD voltage 2.7 ~ 3.6 */ -#define SD_OCR_VDD_27_34 (0x7F << 15) /* VDD voltage 2.7 ~ 3.4 */ -#define SD_OCR_VDD_32_33 (1 << 20) /* VDD voltage 3.2 ~ 3.3 */ -#define SD_OCR_S18R (1 << 24) /* 1.8V switching request */ -#define SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */ -#define SD_OCR_XPC (1 << 28) /* SDXC power control */ -#define SD_OCR_CCS (1 << 30) /* Card Capacity Status */ -#define SD_OCR_BUSY (1 << 31) /* Card Power up Status */ - -/* - * SD_SWITCH argument format: + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. * - * [31] Check (0) or switch (1) - * [30:24] Reserved (0) - * [23:20] Function group 6 - * [19:16] Function group 5 - * [15:12] Function group 4 - * [11:8] Function group 3 - * [7:4] Function group 2 - * [3:0] Function group 1 - */ - -/* - * SD_SEND_IF_COND argument format: + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. * - * [31:12] Reserved (0) - * [11:8] Host Voltage Supply Flags - * [7:0] Check Pattern (0xAA) + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . */ -/* - * SD_APP_GET_MKB argument format: - * - * [31:24] Number of blocks to read (512 block size) - * [23:16] MKB ID - * [15:0] Block offset - */ +#ifndef SD_H +#define SD_H -/* - * SCR field definitions - */ -#define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */ -#define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */ -#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00-3.0X */ -#define SD_SCR_BUS_WIDTH_1 (1<<0) -#define SD_SCR_BUS_WIDTH_4 (1<<2) +#include +#include +#include -/* - * SD bus widths - */ -#define SD_BUS_WIDTH_1 0 -#define SD_BUS_WIDTH_4 2 +#define SD_BLOCKSIZE SDMMC_DAT_BLOCKSIZE -/* - * SD bus speeds - */ -#define UHS_SDR12_BUS_SPEED 0 -#define HIGH_SPEED_BUS_SPEED 1 -#define UHS_SDR25_BUS_SPEED 1 -#define UHS_SDR50_BUS_SPEED 2 -#define UHS_SDR104_BUS_SPEED 3 -#define UHS_DDR50_BUS_SPEED 4 -#define HS400_BUS_SPEED 5 +enum +{ + SD_INIT_FAIL = 0, + SD_1BIT_HS25 = 1, + SD_4BIT_HS25 = 2, + SD_UHS_SDR82 = 3, + SD_UHS_SDR104 = 4, +#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT + SD_UHS_DDR208 = 5 +#endif -#define SD_MODE_HIGH_SPEED (1 << HIGH_SPEED_BUS_SPEED) -#define SD_MODE_UHS_SDR12 (1 << UHS_SDR12_BUS_SPEED) -#define SD_MODE_UHS_SDR25 (1 << UHS_SDR25_BUS_SPEED) -#define SD_MODE_UHS_SDR50 (1 << UHS_SDR50_BUS_SPEED) -#define SD_MODE_UHS_SDR104 (1 << UHS_SDR104_BUS_SPEED) -#define SD_MODE_UHS_DDR50 (1 << UHS_DDR50_BUS_SPEED) +}; -#define SD_DRIVER_TYPE_B 0x01 -#define SD_DRIVER_TYPE_A 0x02 +enum +{ + SD_ERROR_INIT_FAIL = 0, + SD_ERROR_RW_FAIL = 1, + SD_ERROR_RW_RETRY = 2 +}; -#define SD_SET_CURRENT_LIMIT_200 0 -#define SD_SET_CURRENT_LIMIT_400 1 -#define SD_SET_CURRENT_LIMIT_600 2 -#define SD_SET_CURRENT_LIMIT_800 3 +extern sdmmc_t sd_sdmmc; +extern sdmmc_storage_t sd_storage; +extern FATFS sd_fs; -#define SD_MAX_CURRENT_200 (1 << SD_SET_CURRENT_LIMIT_200) -#define SD_MAX_CURRENT_400 (1 << SD_SET_CURRENT_LIMIT_400) -#define SD_MAX_CURRENT_600 (1 << SD_SET_CURRENT_LIMIT_600) -#define SD_MAX_CURRENT_800 (1 << SD_SET_CURRENT_LIMIT_800) +void sd_error_count_increment(u8 type); +u16 *sd_get_error_count(); +bool sd_get_card_removed(); +bool sd_get_card_initialized(); +bool sd_get_card_mounted(); +u32 sd_get_mode(); +int sd_init_retry(bool power_cycle); +bool sd_initialize(bool power_cycle); +bool sd_mount(); +void sd_unmount(); +void sd_end(); +bool sd_is_gpt(); +void *sd_file_read(const char *path, u32 *fsize); +int sd_save_to_file(const void *buf, u32 size, const char *filename); -/* - * SD_SWITCH mode - */ -#define SD_SWITCH_CHECK 0 -#define SD_SWITCH_SET 1 - -/* - * SD_SWITCH function groups - */ -#define SD_SWITCH_GRP_ACCESS 0 - -/* - * SD_SWITCH access modes - */ -#define SD_SWITCH_ACCESS_DEF 0 -#define SD_SWITCH_ACCESS_HS 1 - -#endif /* LINUX_MMC_SD_H */ +#endif \ No newline at end of file diff --git a/bdk/storage/sd_def.h b/bdk/storage/sd_def.h new file mode 100644 index 0000000..898ac46 --- /dev/null +++ b/bdk/storage/sd_def.h @@ -0,0 +1,179 @@ +/* + * Copyright (c) 2005-2007 Pierre Ossman, All Rights Reserved. + * Copyright (c) 2018-2025 CTCaer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or (at + * your option) any later version. + */ + +#ifndef SD_DEF_H +#define SD_DEF_H + +/* SD commands type argument response */ +/* class 0 */ +/* This is basically the same command as for MMC with some quirks. */ +#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */ +#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */ +#define SD_SWITCH_VOLTAGE 11 /* ac R1 */ +/* Class 2 */ +#define SD_ADDR_EXT 22 /* ac [5:0] R1 */ +/* class 10 */ +#define SD_SWITCH 6 /* adtc [31:0] See below R1 */ +/* class 5 */ +#define SD_ERASE_WR_BLK_START 32 /* ac [31:0] data addr R1 */ +#define SD_ERASE_WR_BLK_END 33 /* ac [31:0] data addr R1 */ + /* class 11 */ +#define SD_READ_EXTR_SINGLE 48 /* adtc [31:0] R1 */ +#define SD_WRITE_EXTR_SINGLE 49 /* adtc [31:0] R1 */ + +/* Application commands */ +#define SD_APP_SET_BUS_WIDTH 6 /* ac [1:0] bus width R1 */ +#define SD_APP_SD_STATUS 13 /* adtc R1 */ +#define SD_APP_SEND_NUM_WR_BLKS 22 /* adtc R1 */ +#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */ +#define SD_APP_SET_CLR_CARD_DETECT 42 /* adtc R1 */ +#define SD_APP_SEND_SCR 51 /* adtc R1 */ + +/* Application secure commands */ +#define SD_APP_SECURE_READ_MULTI_BLOCK 18 /* adtc R1 */ +#define SD_APP_SECURE_WRITE_MULTI_BLOCK 25 /* adtc R1 */ +#define SD_APP_SECURE_WRITE_MKB 26 /* adtc R1 */ +#define SD_APP_SECURE_ERASE 38 /* adtc R1b */ +#define SD_APP_GET_MKB 43 /* adtc [31:0] See below R1 */ +#define SD_APP_GET_MID 44 /* adtc R1 */ +#define SD_APP_SET_CER_RN1 45 /* adtc R1 */ +#define SD_APP_GET_CER_RN2 46 /* adtc R1 */ +#define SD_APP_SET_CER_RES2 47 /* adtc R1 */ +#define SD_APP_GET_CER_RES1 48 /* adtc R1 */ +#define SD_APP_CHANGE_SECURE_AREA 49 /* adtc R1b */ + +/* OCR bit definitions */ +#define SD_OCR_VDD_18 (1U << 7) /* VDD voltage 1.8 */ +#define SD_VHS_27_36 (1U << 8) /* VDD voltage 2.7 ~ 3.6 */ +#define SD_OCR_VDD_32_33 (1U << 20) /* VDD voltage 3.2 ~ 3.3 */ +#define SD_OCR_S18R (1U << 24) /* 1.8V switching request */ +#define SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */ +#define SD_OCR_XPC (1U << 28) /* SDXC power control */ +#define SD_OCR_CCS (1U << 30) /* Card Capacity Status */ +#define SD_OCR_BUSY (1U << 31) /* Card Power up Status */ + +/* + * SD_SWITCH argument format: + * + * [31] Check (0) or switch (1) + * [30:24] Reserved (0) + * [23:20] Function group 6 + * [19:16] Function group 5 + * [15:12] Function group 4 + * [11:8] Function group 3 + * [7:4] Function group 2 + * [3:0] Function group 1 + */ + +/* + * SD_SEND_IF_COND argument format: + * + * [31:12] Reserved (0) + * [11:8] Host Voltage Supply Flags + * [7:0] Check Pattern (0xAA) + */ + +/* + * SD_APP_GET_MKB argument format: + * + * [31:24] Number of blocks to read (512 block size) + * [23:16] MKB ID + * [15:0] Block offset + */ + +/* + * SCR field definitions + */ +#define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */ +#define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */ +#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00-3.0X */ +#define SD_SCR_BUS_WIDTH_1 (1U << 0) +#define SD_SCR_BUS_WIDTH_4 (1U << 2) + +/* + * SD bus widths + */ +#define SD_BUS_WIDTH_1 0 +#define SD_BUS_WIDTH_4 2 + +/* + * SD bus speeds + */ +#define UHS_SDR12_BUS_SPEED 0 +#define HIGH_SPEED_BUS_SPEED 1 +#define UHS_SDR25_BUS_SPEED 1 +#define UHS_SDR50_BUS_SPEED 2 +#define UHS_SDR104_BUS_SPEED 3 +#define UHS_DDR50_BUS_SPEED 4 +#define HS400_BUS_SPEED 5 + +#define SD_MODE_HIGH_SPEED (1U << HIGH_SPEED_BUS_SPEED) +#define SD_MODE_UHS_SDR12 (1U << UHS_SDR12_BUS_SPEED) +#define SD_MODE_UHS_SDR25 (1U << UHS_SDR25_BUS_SPEED) +#define SD_MODE_UHS_SDR50 (1U << UHS_SDR50_BUS_SPEED) +#define SD_MODE_UHS_SDR104 (1U << UHS_SDR104_BUS_SPEED) +#define SD_MODE_UHS_DDR50 (1U << UHS_DDR50_BUS_SPEED) + + +#define SD_SET_DRIVER_TYPE_B 0 +#define SD_SET_DRIVER_TYPE_A 1 +#define SD_SET_DRIVER_TYPE_C 2 +#define SD_SET_DRIVER_TYPE_D 3 + +#define SD_DRIVER_TYPE_B (1U << SD_SET_DRIVER_TYPE_B) +#define SD_DRIVER_TYPE_A (1U << SD_SET_DRIVER_TYPE_A) +#define SD_DRIVER_TYPE_C (1U << SD_SET_DRIVER_TYPE_C) +#define SD_DRIVER_TYPE_D (1U << SD_SET_DRIVER_TYPE_D) + +#define SD_SET_POWER_LIMIT_0_72 0 +#define SD_SET_POWER_LIMIT_1_44 1 +#define SD_SET_POWER_LIMIT_2_16 2 +#define SD_SET_POWER_LIMIT_2_88 3 + +#define SD_MAX_POWER_0_72 (1U << SD_SET_POWER_LIMIT_0_72) +#define SD_MAX_POWER_1_44 (1U << SD_SET_POWER_LIMIT_1_44) +#define SD_MAX_POWER_2_16 (1U << SD_SET_POWER_LIMIT_2_16) +#define SD_MAX_POWER_2_88 (1U << SD_SET_POWER_LIMIT_2_88) + +#define SD_SET_CMD_SYSTEM_DEF 0 +#define SD_SET_CMD_SYSTEM_MEC 1 +#define SD_SET_CMD_SYSTEM_OTP 3 +#define SD_SET_CMD_SYSTEM_OSD 3 +#define SD_SET_CMD_SYSTEM_VND 14 +#define UHS_DDR200_BUS_SPEED SD_SET_CMD_SYSTEM_VND + +#define SD_CMD_SYSTEM_DEF (1U << SD_SET_CMD_SYSTEM_DEF) +#define SD_CMD_SYSTEM_MEC (1U << SD_SET_CMD_SYSTEM_MEC) +#define SD_CMD_SYSTEM_OTP (1U << SD_SET_CMD_SYSTEM_OTP) +#define SD_CMD_SYSTEM_OSD (1U << SD_SET_CMD_SYSTEM_OSD) +#define SD_CMD_SYSTEM_VND (1U << SD_SET_CMD_SYSTEM_VND) +#define SD_MODE_UHS_DDR200 SD_CMD_SYSTEM_VND + +/* + * SD_SWITCH mode + */ +#define SD_SWITCH_CHECK 0 +#define SD_SWITCH_SET 1 + +/* + * SD_SWITCH function groups + */ +#define SD_SWITCH_GRP_ACCESS 0 +#define SD_SWITCH_GRP_CMDSYS 1 +#define SD_SWITCH_GRP_DRVSTR 2 +#define SD_SWITCH_GRP_PWRLIM 3 + +/* + * SD_SWITCH access modes + */ +#define SD_SWITCH_ACCESS_DEF 0 +#define SD_SWITCH_ACCESS_HS 1 + +#endif /* SD_DEF_H */ diff --git a/bdk/storage/sdmmc.c b/bdk/storage/sdmmc.c index c87db83..747c28d 100644 --- a/bdk/storage/sdmmc.c +++ b/bdk/storage/sdmmc.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2025 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,25 +16,42 @@ */ #include + +#include +#include +#include +#include #include #include -#include #include +#include #include #include -#include -#include //#define DPRINTF(...) gfx_printf(__VA_ARGS__) #define DPRINTF(...) +//#define SDMMC_DEBUG_PRINT_SD_REGS +#ifdef SDMMC_DEBUG_PRINT_SD_REGS +#define DREGPRINTF(...) gfx_printf(__VA_ARGS__) +#else +#define DREGPRINTF(...) +#endif + +#ifdef BDK_SDMMC_EXTRA_PRINT +#define ERROR_EXTRA_PRINTING +#endif + u32 sd_power_cycle_time_start; -static inline u32 unstuff_bits(u32 *resp, u32 start, u32 size) +static inline u32 unstuff_bits(const u32 *resp, u32 start, u32 size) { + start %= 128; + const u32 mask = (size < 32 ? 1 << size : 0) - 1; - const u32 off = 3 - ((start) / 32); + const u32 off = 3 - ((start) / 32); const u32 shft = (start) & 31; + u32 res = resp[off] >> shft; if (size + shft > 32) res |= resp[off - 1] << ((32 - shft) % 32); @@ -48,7 +65,7 @@ static inline u32 unstuff_bits(u32 *resp, u32 start, u32 size) static int _sdmmc_storage_check_card_status(u32 res) { //Error mask: - //TODO: R1_SWITCH_ERROR can be skipped for certain card types. + //!WARN: R1_SWITCH_ERROR is reserved on SD. The card isn't supposed to use it. if (res & (R1_OUT_OF_RANGE | R1_ADDRESS_ERROR | R1_BLOCK_LEN_ERROR | R1_ERASE_SEQ_ERROR | R1_ERASE_PARAM | R1_WP_VIOLATION | @@ -69,7 +86,7 @@ static int _sdmmc_storage_execute_cmd_type1_ex(sdmmc_storage_t *storage, u32 *re if (!sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, NULL, NULL)) return 0; - sdmmc_get_rsp(storage->sdmmc, resp, 4, SDMMC_RSP_TYPE_1); + sdmmc_get_cached_rsp(storage->sdmmc, resp, SDMMC_RSP_TYPE_1); if (mask) *resp &= ~mask; @@ -101,7 +118,7 @@ static int _sdmmc_storage_get_cid(sdmmc_storage_t *storage) if (!sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, NULL, NULL)) return 0; - sdmmc_get_rsp(storage->sdmmc, (u32 *)storage->raw_cid, 16, SDMMC_RSP_TYPE_2); + sdmmc_get_cached_rsp(storage->sdmmc, (u32 *)storage->raw_cid, SDMMC_RSP_TYPE_2); return 1; } @@ -118,7 +135,7 @@ static int _sdmmc_storage_get_csd(sdmmc_storage_t *storage) if (!sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, NULL, NULL)) return 0; - sdmmc_get_rsp(storage->sdmmc, (u32 *)storage->raw_csd, 16, SDMMC_RSP_TYPE_2); + sdmmc_get_cached_rsp(storage->sdmmc, (u32 *)storage->raw_csd, SDMMC_RSP_TYPE_2); return 1; } @@ -147,16 +164,20 @@ int sdmmc_storage_execute_vendor_cmd(sdmmc_storage_t *storage, u32 arg) return 0; u32 resp; - sdmmc_get_rsp(storage->sdmmc, &resp, 4, SDMMC_RSP_TYPE_1); + sdmmc_get_cached_rsp(storage->sdmmc, &resp, SDMMC_RSP_TYPE_1); resp = -1; u32 timeout = get_tmr_ms() + 1500; - while (resp != (R1_READY_FOR_DATA | R1_STATE(R1_STATE_TRAN))) + while (true) { _sdmmc_storage_get_status(storage, &resp, 0); + if (resp == (R1_READY_FOR_DATA | R1_STATE(R1_STATE_TRAN))) + break; + if (get_tmr_ms() > timeout) break; + msleep(10); } return _sdmmc_storage_check_card_status(resp); @@ -174,11 +195,11 @@ int sdmmc_storage_vendor_sandisk_report(sdmmc_storage_t *storage, void *buf) sdmmc_init_cmd(&cmdbuf, MMC_VENDOR_63_CMD, 0, SDMMC_RSP_TYPE_1, 0); // similar to CMD17 with arg 0x0. - reqbuf.buf = buf; - reqbuf.num_sectors = 1; - reqbuf.blksize = 512; - reqbuf.is_write = 0; - reqbuf.is_multi_block = 0; + reqbuf.buf = buf; + reqbuf.num_sectors = 1; + reqbuf.blksize = SDMMC_DAT_BLOCKSIZE; + reqbuf.is_write = 0; + reqbuf.is_multi_block = 0; reqbuf.is_auto_stop_trn = 0; u32 blkcnt_out; @@ -205,11 +226,11 @@ static int _sdmmc_storage_readwrite_ex(sdmmc_storage_t *storage, u32 *blkcnt_out sdmmc_init_cmd(&cmdbuf, is_write ? MMC_WRITE_MULTIPLE_BLOCK : MMC_READ_MULTIPLE_BLOCK, sector, SDMMC_RSP_TYPE_1, 0); - reqbuf.buf = buf; - reqbuf.num_sectors = num_sectors; - reqbuf.blksize = 512; - reqbuf.is_write = is_write; - reqbuf.is_multi_block = 1; + reqbuf.buf = buf; + reqbuf.num_sectors = num_sectors; + reqbuf.blksize = SDMMC_DAT_BLOCKSIZE; + reqbuf.is_write = is_write; + reqbuf.is_multi_block = 1; reqbuf.is_auto_stop_trn = 1; if (!sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, &reqbuf, blkcnt_out)) @@ -220,11 +241,17 @@ static int _sdmmc_storage_readwrite_ex(sdmmc_storage_t *storage, u32 *blkcnt_out return 0; } + sdmmc_get_cached_rsp(storage->sdmmc, &tmp, SDMMC_RSP_TYPE_1); + if (!_sdmmc_storage_check_card_status(tmp)) + return 0; + return 1; } int sdmmc_storage_end(sdmmc_storage_t *storage) { + DPRINTF("[SDMMC%d] end\n", storage->sdmmc->id); + if (!_sdmmc_storage_go_idle_state(storage)) return 0; @@ -235,6 +262,43 @@ int sdmmc_storage_end(sdmmc_storage_t *storage) return 1; } +static int _sdmmc_storage_handle_io_error(sdmmc_storage_t *storage, bool first_reinit) +{ + int res = 0; + + if (storage->sdmmc->id == SDMMC_1 || storage->sdmmc->id == SDMMC_4) + { + if (storage->sdmmc->id == SDMMC_1) + { + sd_error_count_increment(SD_ERROR_RW_FAIL); + + if (first_reinit) + res = sd_initialize(true); + else + { + res = sd_init_retry(true); + if (!res) + sd_error_count_increment(SD_ERROR_INIT_FAIL); + } + } + else if (storage->sdmmc->id == SDMMC_4) + { + emmc_error_count_increment(EMMC_ERROR_RW_FAIL); + + if (first_reinit) + res = emmc_initialize(true); + else + { + res = emmc_init_retry(true); + if (!res) + emmc_error_count_increment(EMMC_ERROR_INIT_FAIL); + } + } + } + + return res; +} + static int _sdmmc_storage_readwrite(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, void *buf, u32 is_write) { u8 *bbuf = (u8 *)buf; @@ -246,6 +310,15 @@ static int _sdmmc_storage_readwrite(sdmmc_storage_t *storage, u32 sector, u32 nu if (!storage->initialized) return 0; + // Check if out of bounds. + if (((u64)sector + num_sectors) > storage->sec_cnt) + { +#ifdef ERROR_EXTRA_PRINTING + EPRINTFARGS("SDMMC%d: Out of bounds!", storage->sdmmc->id + 1); +#endif + return 0; + } + while (sct_total) { u32 blkcnt = 0; @@ -264,36 +337,19 @@ reinit_try: msleep(50); } while (retries); - // Disk IO failure! Reinit SD Card to a lower speed. - if (storage->sdmmc->id == SDMMC_1) + // Disk IO failure! Reinit SD/EMMC to a lower speed. + if (_sdmmc_storage_handle_io_error(storage, first_reinit)) { - int res; - - sd_error_count_increment(SD_ERROR_RW_FAIL); - - if (first_reinit) - res = sd_initialize(true); - else - { - res = sd_init_retry(true); - if (!res) - sd_error_count_increment(SD_ERROR_INIT_FAIL); - } - // Reset values for a retry. blkcnt = 0; retries = 3; first_reinit = false; - // If succesful reinit, restart xfer. - if (res) - { - bbuf = (u8 *)buf; - sct_off = sector; - sct_total = num_sectors; + bbuf = (u8 *)buf; + sct_off = sector; + sct_total = num_sectors; - goto reinit_try; - } + goto reinit_try; } // Failed. @@ -302,7 +358,7 @@ reinit_try: out: sct_off += blkcnt; sct_total -= blkcnt; - bbuf += 512 * blkcnt; + bbuf += SDMMC_DAT_BLOCKSIZE * blkcnt; } return 1; @@ -310,17 +366,17 @@ out: int sdmmc_storage_read(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, void *buf) { - // Ensure that buffer resides in DRAM and it's DMA aligned. - if (((u32)buf >= DRAM_START) && !((u32)buf % 8)) + // Ensure that SDMMC has access to buffer and it's SDMMC DMA aligned. + if (mc_client_has_access(buf) && !((u32)buf % 8)) return _sdmmc_storage_readwrite(storage, sector, num_sectors, buf, 0); - if (num_sectors > (SDMMC_UP_BUF_SZ / 512)) + if (num_sectors > (SDMMC_UP_BUF_SZ / SDMMC_DAT_BLOCKSIZE)) return 0; u8 *tmp_buf = (u8 *)SDMMC_UPPER_BUFFER; if (_sdmmc_storage_readwrite(storage, sector, num_sectors, tmp_buf, 0)) { - memcpy(buf, tmp_buf, 512 * num_sectors); + memcpy(buf, tmp_buf, SDMMC_DAT_BLOCKSIZE * num_sectors); return 1; } return 0; @@ -328,15 +384,15 @@ int sdmmc_storage_read(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, vo int sdmmc_storage_write(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, void *buf) { - // Ensure that buffer resides in DRAM and it's DMA aligned. - if (((u32)buf >= DRAM_START) && !((u32)buf % 8)) + // Ensure that SDMMC has access to buffer and it's SDMMC DMA aligned. + if (mc_client_has_access(buf) && !((u32)buf % 8)) return _sdmmc_storage_readwrite(storage, sector, num_sectors, buf, 1); - if (num_sectors > (SDMMC_UP_BUF_SZ / 512)) + if (num_sectors > (SDMMC_UP_BUF_SZ / SDMMC_DAT_BLOCKSIZE)) return 0; u8 *tmp_buf = (u8 *)SDMMC_UPPER_BUFFER; - memcpy(tmp_buf, buf, 512 * num_sectors); + memcpy(tmp_buf, buf, SDMMC_DAT_BLOCKSIZE * num_sectors); return _sdmmc_storage_readwrite(storage, sector, num_sectors, tmp_buf, 1); } @@ -367,7 +423,7 @@ static int _mmc_storage_get_op_cond_inner(sdmmc_storage_t *storage, u32 *pout, u if (!sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, NULL, NULL)) return 0; - return sdmmc_get_rsp(storage->sdmmc, pout, 4, SDMMC_RSP_TYPE_3); + return sdmmc_get_cached_rsp(storage->sdmmc, pout, SDMMC_RSP_TYPE_3); } static int _mmc_storage_get_op_cond(sdmmc_storage_t *storage, u32 power) @@ -412,19 +468,19 @@ static void _mmc_storage_parse_cid(sdmmc_storage_t *storage) case 0: /* MMC v1.0 - v1.2 */ case 1: /* MMC v1.4 */ storage->cid.prod_name[6] = unstuff_bits(raw_cid, 48, 8); - storage->cid.manfid = unstuff_bits(raw_cid, 104, 24); - storage->cid.hwrev = unstuff_bits(raw_cid, 44, 4); - storage->cid.fwrev = unstuff_bits(raw_cid, 40, 4); - storage->cid.serial = unstuff_bits(raw_cid, 16, 24); + storage->cid.manfid = unstuff_bits(raw_cid, 104, 24); + storage->cid.hwrev = unstuff_bits(raw_cid, 44, 4); + storage->cid.fwrev = unstuff_bits(raw_cid, 40, 4); + storage->cid.serial = unstuff_bits(raw_cid, 16, 24); break; case 2: /* MMC v2.0 - v2.2 */ case 3: /* MMC v3.1 - v3.3 */ case 4: /* MMC v4 */ - storage->cid.manfid = unstuff_bits(raw_cid, 120, 8); - storage->cid.oemid = unstuff_bits(raw_cid, 104, 8); - storage->cid.prv = unstuff_bits(raw_cid, 48, 8); - storage->cid.serial = unstuff_bits(raw_cid, 16, 32); + storage->cid.manfid = unstuff_bits(raw_cid, 120, 8); + storage->cid.oemid = unstuff_bits(raw_cid, 104, 8); + storage->cid.prv = unstuff_bits(raw_cid, 48, 8); + storage->cid.serial = unstuff_bits(raw_cid, 16, 32); break; default: @@ -451,52 +507,51 @@ static void _mmc_storage_parse_csd(sdmmc_storage_t *storage) { u32 *raw_csd = (u32 *)storage->raw_csd; - storage->csd.mmca_vsn = unstuff_bits(raw_csd, 122, 4); - storage->csd.structure = unstuff_bits(raw_csd, 126, 2); - storage->csd.cmdclass = unstuff_bits(raw_csd, 84, 12); + storage->csd.mmca_vsn = unstuff_bits(raw_csd, 122, 4); + storage->csd.structure = unstuff_bits(raw_csd, 126, 2); + storage->csd.cmdclass = unstuff_bits(raw_csd, 84, 12); storage->csd.read_blkbits = unstuff_bits(raw_csd, 80, 4); - storage->csd.capacity = (1 + unstuff_bits(raw_csd, 62, 12)) << (unstuff_bits(raw_csd, 47, 3) + 2); - storage->sec_cnt = storage->csd.capacity; + storage->csd.capacity = (1 + unstuff_bits(raw_csd, 62, 12)) << (unstuff_bits(raw_csd, 47, 3) + 2); + storage->sec_cnt = storage->csd.capacity; } static void _mmc_storage_parse_ext_csd(sdmmc_storage_t *storage, u8 *buf) { - storage->ext_csd.rev = buf[EXT_CSD_REV]; - storage->ext_csd.ext_struct = buf[EXT_CSD_STRUCTURE]; - storage->ext_csd.card_type = buf[EXT_CSD_CARD_TYPE]; - storage->ext_csd.dev_version = *(u16 *)&buf[EXT_CSD_DEVICE_VERSION]; - storage->ext_csd.boot_mult = buf[EXT_CSD_BOOT_MULT]; - storage->ext_csd.rpmb_mult = buf[EXT_CSD_RPMB_MULT]; - //storage->ext_csd.bkops = buf[EXT_CSD_BKOPS_SUPPORT]; - //storage->ext_csd.bkops_en = buf[EXT_CSD_BKOPS_EN]; + storage->ext_csd.rev = buf[EXT_CSD_REV]; + storage->ext_csd.ext_struct = buf[EXT_CSD_STRUCTURE]; + storage->ext_csd.card_type = buf[EXT_CSD_CARD_TYPE]; + storage->ext_csd.dev_version = *(u16 *)&buf[EXT_CSD_DEVICE_VERSION]; + storage->ext_csd.boot_mult = buf[EXT_CSD_BOOT_MULT]; + storage->ext_csd.rpmb_mult = buf[EXT_CSD_RPMB_MULT]; + //storage->ext_csd.bkops = buf[EXT_CSD_BKOPS_SUPPORT]; + //storage->ext_csd.bkops_en = buf[EXT_CSD_BKOPS_EN]; //storage->ext_csd.bkops_status = buf[EXT_CSD_BKOPS_STATUS]; - storage->ext_csd.pre_eol_info = buf[EXT_CSD_PRE_EOL_INFO]; + storage->ext_csd.pre_eol_info = buf[EXT_CSD_PRE_EOL_INFO]; storage->ext_csd.dev_life_est_a = buf[EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A]; storage->ext_csd.dev_life_est_b = buf[EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B]; - storage->ext_csd.cache_size = - buf[EXT_CSD_CACHE_SIZE] | - (buf[EXT_CSD_CACHE_SIZE + 1] << 8) | - (buf[EXT_CSD_CACHE_SIZE + 2] << 16) | - (buf[EXT_CSD_CACHE_SIZE + 3] << 24); - storage->ext_csd.max_enh_mult = - (buf[EXT_CSD_MAX_ENH_SIZE_MULT] | - (buf[EXT_CSD_MAX_ENH_SIZE_MULT + 1] << 8) | - (buf[EXT_CSD_MAX_ENH_SIZE_MULT + 2] << 16)) * - buf[EXT_CSD_HC_WP_GRP_SIZE] * buf[EXT_CSD_HC_ERASE_GRP_SIZE]; + storage->ext_csd.cache_size = buf[EXT_CSD_CACHE_SIZE] | + (buf[EXT_CSD_CACHE_SIZE + 1] << 8) | + (buf[EXT_CSD_CACHE_SIZE + 2] << 16) | + (buf[EXT_CSD_CACHE_SIZE + 3] << 24); + + storage->ext_csd.max_enh_mult = (buf[EXT_CSD_MAX_ENH_SIZE_MULT] | + (buf[EXT_CSD_MAX_ENH_SIZE_MULT + 1] << 8) | + (buf[EXT_CSD_MAX_ENH_SIZE_MULT + 2] << 16)) * + buf[EXT_CSD_HC_WP_GRP_SIZE] * buf[EXT_CSD_HC_ERASE_GRP_SIZE]; storage->sec_cnt = *(u32 *)&buf[EXT_CSD_SEC_CNT]; } -static int _mmc_storage_get_ext_csd(sdmmc_storage_t *storage, void *buf) +int mmc_storage_get_ext_csd(sdmmc_storage_t *storage, void *buf) { sdmmc_cmd_t cmdbuf; sdmmc_init_cmd(&cmdbuf, MMC_SEND_EXT_CSD, 0, SDMMC_RSP_TYPE_1, 0); sdmmc_req_t reqbuf; reqbuf.buf = buf; - reqbuf.blksize = 512; + reqbuf.blksize = SDMMC_DAT_BLOCKSIZE; reqbuf.num_sectors = 1; reqbuf.is_write = 0; reqbuf.is_multi_block = 0; @@ -506,12 +561,40 @@ static int _mmc_storage_get_ext_csd(sdmmc_storage_t *storage, void *buf) return 0; u32 tmp = 0; - sdmmc_get_rsp(storage->sdmmc, &tmp, 4, SDMMC_RSP_TYPE_1); + sdmmc_get_cached_rsp(storage->sdmmc, &tmp, SDMMC_RSP_TYPE_1); _mmc_storage_parse_ext_csd(storage, buf); return _sdmmc_storage_check_card_status(tmp); } +int sd_storage_get_ext_reg(sdmmc_storage_t *storage, u8 fno, u8 page, u16 address, u32 len, void *buf) +{ + if (!(storage->scr.cmds & BIT(2))) + return 0; + + sdmmc_cmd_t cmdbuf; + + u32 arg = fno << 27 | page << 18 | address << 9 | (len - 1); + + sdmmc_init_cmd(&cmdbuf, SD_READ_EXTR_SINGLE, arg, SDMMC_RSP_TYPE_1, 0); + + sdmmc_req_t reqbuf; + reqbuf.buf = buf; + reqbuf.blksize = SDMMC_DAT_BLOCKSIZE; + reqbuf.num_sectors = 1; + reqbuf.is_write = 0; + reqbuf.is_multi_block = 0; + reqbuf.is_auto_stop_trn = 0; + + if (!sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, &reqbuf, NULL)) + return 0; + + u32 tmp = 0; + sdmmc_get_cached_rsp(storage->sdmmc, &tmp, SDMMC_RSP_TYPE_1); + + return _sdmmc_storage_check_card_status(tmp); +} + static int _mmc_storage_switch(sdmmc_storage_t *storage, u32 arg) { return _sdmmc_storage_execute_cmd_type1(storage, MMC_SWITCH, arg, 1, R1_SKIP_STATE_CHECK); @@ -545,21 +628,21 @@ static int _mmc_storage_switch_buswidth(sdmmc_storage_t *storage, u32 bus_width) return 0; } -static int _mmc_storage_enable_HS(sdmmc_storage_t *storage, int check) +static int _mmc_storage_enable_HS(sdmmc_storage_t *storage, bool check_sts_before_clk_setup) { if (!_mmc_storage_switch(storage, SDMMC_SWITCH(MMC_SWITCH_MODE_WRITE_BYTE, EXT_CSD_HS_TIMING, EXT_CSD_TIMING_HS))) return 0; - if (check && !_sdmmc_storage_check_status(storage)) + if (check_sts_before_clk_setup && !_sdmmc_storage_check_status(storage)) return 0; if (!sdmmc_setup_clock(storage->sdmmc, SDHCI_TIMING_MMC_HS52)) return 0; -DPRINTF("[MMC] switched to HS\n"); + DPRINTF("[MMC] switched to HS52\n"); storage->csd.busspeed = 52; - if (check || _sdmmc_storage_check_status(storage)) + if (check_sts_before_clk_setup || _sdmmc_storage_check_status(storage)) return 1; return 0; @@ -576,7 +659,7 @@ static int _mmc_storage_enable_HS200(sdmmc_storage_t *storage) if (!sdmmc_tuning_execute(storage->sdmmc, SDHCI_TIMING_MMC_HS200, MMC_SEND_TUNING_BLOCK_HS200)) return 0; -DPRINTF("[MMC] switched to HS200\n"); + DPRINTF("[MMC] switched to HS200\n"); storage->csd.busspeed = 200; return _sdmmc_storage_check_status(storage); @@ -589,7 +672,7 @@ static int _mmc_storage_enable_HS400(sdmmc_storage_t *storage) sdmmc_save_tap_value(storage->sdmmc); - if (!_mmc_storage_enable_HS(storage, 0)) + if (!_mmc_storage_enable_HS(storage, false)) return 0; if (!_mmc_storage_switch(storage, SDMMC_SWITCH(MMC_SWITCH_MODE_WRITE_BYTE, EXT_CSD_BUS_WIDTH, EXT_CSD_DDR_BUS_WIDTH_8))) @@ -601,7 +684,7 @@ static int _mmc_storage_enable_HS400(sdmmc_storage_t *storage) if (!sdmmc_setup_clock(storage->sdmmc, SDHCI_TIMING_MMC_HS400)) return 0; -DPRINTF("[MMC] switched to HS400\n"); + DPRINTF("[MMC] switched to HS400\n"); storage->csd.busspeed = 400; return _sdmmc_storage_check_status(storage); @@ -610,27 +693,29 @@ DPRINTF("[MMC] switched to HS400\n"); static int _mmc_storage_enable_highspeed(sdmmc_storage_t *storage, u32 card_type, u32 type) { if (sdmmc_get_io_power(storage->sdmmc) != SDMMC_POWER_1_8) - goto out; + goto hs52_mode; + // HS400 needs 8-bit bus width mode. if (sdmmc_get_bus_width(storage->sdmmc) == SDMMC_BUS_WIDTH_8 && card_type & EXT_CSD_CARD_TYPE_HS400_1_8V && type == SDHCI_TIMING_MMC_HS400) return _mmc_storage_enable_HS400(storage); - if (sdmmc_get_bus_width(storage->sdmmc) == SDMMC_BUS_WIDTH_8 || - (sdmmc_get_bus_width(storage->sdmmc) == SDMMC_BUS_WIDTH_4 - && card_type & EXT_CSD_CARD_TYPE_HS200_1_8V - && (type == SDHCI_TIMING_MMC_HS400 || type == SDHCI_TIMING_MMC_HS200))) + // Try HS200 if HS400 and 4-bit width bus or just HS200. + if ((sdmmc_get_bus_width(storage->sdmmc) == SDMMC_BUS_WIDTH_8 || + sdmmc_get_bus_width(storage->sdmmc) == SDMMC_BUS_WIDTH_4) && + card_type & EXT_CSD_CARD_TYPE_HS200_1_8V && + (type == SDHCI_TIMING_MMC_HS400 || type == SDHCI_TIMING_MMC_HS200)) return _mmc_storage_enable_HS200(storage); -out: +hs52_mode: if (card_type & EXT_CSD_CARD_TYPE_HS_52) - return _mmc_storage_enable_HS(storage, 1); + return _mmc_storage_enable_HS(storage, true); return 1; } /* -static int _mmc_storage_enable_bkops(sdmmc_storage_t *storage) +static int _mmc_storage_enable_auto_bkops(sdmmc_storage_t *storage) { if (!_mmc_storage_switch(storage, SDMMC_SWITCH(MMC_SWITCH_MODE_SET_BITS, EXT_CSD_BKOPS_EN, EXT_CSD_AUTO_BKOPS_MASK))) return 0; @@ -645,74 +730,77 @@ int sdmmc_storage_init_mmc(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 bus_wid storage->sdmmc = sdmmc; storage->rca = 2; // Set default device address. This could be a config item. - if (!sdmmc_init(sdmmc, SDMMC_4, SDMMC_POWER_1_8, SDMMC_BUS_WIDTH_1, SDHCI_TIMING_MMC_ID, SDMMC_POWER_SAVE_DISABLE)) - return 0; -DPRINTF("[MMC] after init\n"); + DPRINTF("[MMC]-[init: bus: %d, type: %d]\n", bus_width, type); - usleep(1000 + (74000 + sdmmc->divisor - 1) / sdmmc->divisor); + if (!sdmmc_init(sdmmc, SDMMC_4, SDMMC_POWER_1_8, SDMMC_BUS_WIDTH_1, SDHCI_TIMING_MMC_ID)) + return 0; + DPRINTF("[MMC] after init\n"); + + // Wait 1ms + 74 cycles. + usleep(1000 + (74 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); if (!_sdmmc_storage_go_idle_state(storage)) return 0; -DPRINTF("[MMC] went to idle state\n"); + DPRINTF("[MMC] went to idle state\n"); if (!_mmc_storage_get_op_cond(storage, SDMMC_POWER_1_8)) return 0; -DPRINTF("[MMC] got op cond\n"); + DPRINTF("[MMC] got op cond\n"); if (!_sdmmc_storage_get_cid(storage)) return 0; -DPRINTF("[MMC] got cid\n"); + DPRINTF("[MMC] got cid\n"); if (!_mmc_storage_set_relative_addr(storage)) return 0; -DPRINTF("[MMC] set relative addr\n"); + DPRINTF("[MMC] set relative addr\n"); if (!_sdmmc_storage_get_csd(storage)) return 0; -DPRINTF("[MMC] got csd\n"); + DPRINTF("[MMC] got csd\n"); _mmc_storage_parse_csd(storage); if (!sdmmc_setup_clock(storage->sdmmc, SDHCI_TIMING_MMC_LS26)) return 0; -DPRINTF("[MMC] after setup clock\n"); + DPRINTF("[MMC] after setup clock\n"); if (!_sdmmc_storage_select_card(storage)) return 0; -DPRINTF("[MMC] card selected\n"); + DPRINTF("[MMC] card selected\n"); - if (!_sdmmc_storage_set_blocklen(storage, 512)) + if (!_sdmmc_storage_set_blocklen(storage, EMMC_BLOCKSIZE)) return 0; -DPRINTF("[MMC] set blocklen to 512\n"); + DPRINTF("[MMC] set blocklen to EMMC_BLOCKSIZE\n"); // Check system specification version, only version 4.0 and later support below features. if (storage->csd.mmca_vsn < CSD_SPEC_VER_4) - return 1; + goto done; if (!_mmc_storage_switch_buswidth(storage, bus_width)) return 0; -DPRINTF("[MMC] switched buswidth\n"); + DPRINTF("[MMC] switched buswidth\n"); - if (!_mmc_storage_get_ext_csd(storage, (u8 *)SDMMC_UPPER_BUFFER)) + if (!mmc_storage_get_ext_csd(storage, (u8 *)SDMMC_UPPER_BUFFER)) return 0; -DPRINTF("[MMC] got ext_csd\n"); + DPRINTF("[MMC] got ext_csd\n"); _mmc_storage_parse_cid(storage); // This needs to be after csd and ext_csd. - //gfx_hexdump(0, ext_csd, 512); /* if (storage->ext_csd.bkops & 0x1 && !(storage->ext_csd.bkops_en & EXT_CSD_AUTO_BKOPS_MASK)) { - _mmc_storage_enable_bkops(storage); -DPRINTF("[MMC] BKOPS enabled\n"); + _mmc_storage_enable_auto_bkops(storage); + DPRINTF("[MMC] BKOPS enabled\n"); } */ if (!_mmc_storage_enable_highspeed(storage, storage->ext_csd.card_type, type)) return 0; -DPRINTF("[MMC] successfully switched to HS mode\n"); + DPRINTF("[MMC] successfully switched to HS mode\n"); sdmmc_card_clock_powersave(storage->sdmmc, SDMMC_POWER_SAVE_ENABLE); +done: storage->initialized = 1; return 1; @@ -752,20 +840,153 @@ static int _sd_storage_execute_app_cmd_type1(sdmmc_storage_t *storage, u32 *resp return _sdmmc_storage_execute_cmd_type1_ex(storage, resp, cmd, arg, check_busy, expected_state, 0); } +#ifdef SDMMC_DEBUG_PRINT_SD_REGS +void _sd_storage_debug_print_cid(const u32 *raw_cid) +{ + gfx_printf("Card Identification\n"); + + gfx_printf("MID: %02X\n", unstuff_bits(raw_cid, 120, 8)); + gfx_printf("OID %04X\n", unstuff_bits(raw_cid, 104, 16)); + gfx_printf("PNM: %02X %02X %02X %02X %02X\n", + unstuff_bits(raw_cid, 96, 8), unstuff_bits(raw_cid, 88, 8), + unstuff_bits(raw_cid, 80, 8), unstuff_bits(raw_cid, 72, 8), + unstuff_bits(raw_cid, 64, 8)); + gfx_printf("PRV: %02X\n", unstuff_bits(raw_cid, 56, 8)); + gfx_printf("PSN: %08X\n", unstuff_bits(raw_cid, 24, 32)); + gfx_printf("MDT: %03X\n", unstuff_bits(raw_cid, 8, 12)); + gfx_printf("--RSVD-- %X\n", unstuff_bits(raw_cid, 20, 4)); +} + +void _sd_storage_debug_print_csd(const u32 *raw_csd) +{ + gfx_printf("\n"); + + gfx_printf("\nCSD_STRUCTURE: %X\n", unstuff_bits(raw_csd, 126, 2)); + gfx_printf("TAAC: %02X\n", unstuff_bits(raw_csd, 112, 8)); + gfx_printf("NSAC: %02X\n", unstuff_bits(raw_csd, 104, 8)); + gfx_printf("TRAN_SPEED: %02X\n", unstuff_bits(raw_csd, 96, 8)); + gfx_printf("CCC: %03X\n", unstuff_bits(raw_csd, 84, 12)); + gfx_printf("READ_BL_LEN: %X\n", unstuff_bits(raw_csd, 80, 4)); + gfx_printf("READ_BL_PARTIAL: %X\n", unstuff_bits(raw_csd, 79, 1)); + gfx_printf("WRITE_BLK_MISALIGN: %X\n", unstuff_bits(raw_csd, 78, 1)); + gfx_printf("READ_BLK_MISALIGN: %X\n", unstuff_bits(raw_csd, 77, 1)); + gfx_printf("DSR_IMP: %X\n", unstuff_bits(raw_csd, 76, 1)); + gfx_printf("C_SIZE: %06X\n", unstuff_bits(raw_csd, 48, 28)); // CSD 3 (SDUC). + + gfx_printf("ERASE_BLK_LEN: %X\n", unstuff_bits(raw_csd, 46, 1)); + gfx_printf("SECTOR_SIZE: %02X\n", unstuff_bits(raw_csd, 39, 6)); + gfx_printf("WP_GRP_SIZE: %02X\n", unstuff_bits(raw_csd, 32, 6)); + gfx_printf("WP_GRP_ENABLE: %X\n", unstuff_bits(raw_csd, 31, 1)); + + gfx_printf("R2W_FACTOR: %X\n", unstuff_bits(raw_csd, 26, 3)); + gfx_printf("WRITE_BL_LEN: %X\n", unstuff_bits(raw_csd, 22, 4)); + gfx_printf("WRITE_BL_PARTIAL: %X\n", unstuff_bits(raw_csd, 21, 1)); + + gfx_printf("FILE_FORMAT_GRP: %X\n", unstuff_bits(raw_csd, 15, 1)); + gfx_printf("COPY: %X\n", unstuff_bits(raw_csd, 14, 1)); + gfx_printf("PERM_WRITE_PROTECT: %X\n", unstuff_bits(raw_csd, 13, 1)); + gfx_printf("TMP_WRITE_PROTECT: %X\n", unstuff_bits(raw_csd, 12, 1)); + gfx_printf("FILE_FORMAT: %X\n", unstuff_bits(raw_csd, 10, 2)); + + gfx_printf("--RSVD-- %02X %X %X %02X %X\n", + unstuff_bits(raw_csd, 120, 6), + unstuff_bits(raw_csd, 47, 1), unstuff_bits(raw_csd, 29, 2), + unstuff_bits(raw_csd, 16, 5), unstuff_bits(raw_csd, 8, 2)); +} + +void _sd_storage_debug_print_scr(const u32 *raw_scr) +{ + u32 resp[4]; + memcpy(&resp[2], raw_scr, 8); + + gfx_printf("\n"); + + gfx_printf("SCR_STRUCTURE: %X\n", unstuff_bits(resp, 60, 4)); + gfx_printf("SD_SPEC: %X\n", unstuff_bits(resp, 56, 4)); + gfx_printf("DATA_STAT_AFTER_ERASE: %X\n", unstuff_bits(resp, 55, 1)); + gfx_printf("SD_SECURITY: %X\n", unstuff_bits(resp, 52, 3)); + gfx_printf("SD_BUS widths: %X\n", unstuff_bits(resp, 48, 4)); + gfx_printf("SD_SPEC3: %X\n", unstuff_bits(resp, 47, 1)); + gfx_printf("EX_SECURITY: %X\n", unstuff_bits(resp, 43, 4)); + gfx_printf("SD_SPEC4: %X\n", unstuff_bits(resp, 42, 1)); + gfx_printf("SD_SPECX: %X\n", unstuff_bits(resp, 38, 4)); + gfx_printf("CMD_SUPPORT: %X\n", unstuff_bits(resp, 32, 4)); + gfx_printf("VENDOR: %08X\n", unstuff_bits(resp, 0, 32)); + gfx_printf("--RSVD-- %X\n", unstuff_bits(resp, 36, 2)); +} + +void _sd_storage_debug_print_ssr(const u8 *raw_ssr) +{ + u32 raw_ssr0[4]; // 511:384. + u32 raw_ssr1[4]; // 383:256. + u32 raw_ssr2[4]; // 255:128. + u32 raw_ssr3[4]; // 127:0. + memcpy(raw_ssr0, &raw_ssr[0], 16); + memcpy(raw_ssr1, &raw_ssr[16], 16); + memcpy(raw_ssr2, &raw_ssr[32], 16); + memcpy(raw_ssr3, &raw_ssr[48], 16); + + gfx_printf("\nSD Status:\n"); + + gfx_printf("DAT_BUS_WIDTH: %X\n", unstuff_bits(raw_ssr0, 510, 2)); + gfx_printf("SECURED_MODE: %X\n", unstuff_bits(raw_ssr0, 509, 1)); + gfx_printf("SECURITY_FUNCTIONS: %02X\n", unstuff_bits(raw_ssr0, 502, 6)); + gfx_printf("SD_CARD_TYPE: %04X\n", unstuff_bits(raw_ssr0, 480, 16)); + gfx_printf("SZ_OF_PROTECTED_AREA: %08X\n", unstuff_bits(raw_ssr0, 448, 32)); + gfx_printf("SPEED_CLASS: %02X\n", unstuff_bits(raw_ssr0, 440, 8)); + gfx_printf("PERFORMANCE_MOVE: %02X\n", unstuff_bits(raw_ssr0, 432, 8)); + gfx_printf("AU_SIZE: %X\n", unstuff_bits(raw_ssr0, 428, 4)); + gfx_printf("ERAZE_SIZE: %04X\n", unstuff_bits(raw_ssr0, 408, 16)); + gfx_printf("ERASE_TIMEOUT: %02X\n", unstuff_bits(raw_ssr0, 402, 6)); + gfx_printf("ERASE_OFFSET: %X\n", unstuff_bits(raw_ssr0, 400, 2)); + gfx_printf("UHS_SPEED_GRADE: %X\n", unstuff_bits(raw_ssr0, 396, 4)); + gfx_printf("UHS_AU_SIZE: %X\n", unstuff_bits(raw_ssr0, 392, 4)); + gfx_printf("VIDEO_SPEED_CLASS: %02X\n", unstuff_bits(raw_ssr0, 384, 8)); + + gfx_printf("VSC_AU_SIZE: %03X\n", unstuff_bits(raw_ssr1, 368, 10)); + gfx_printf("SUS_ADDR: %06X\n", unstuff_bits(raw_ssr1, 346, 22)); + gfx_printf("APP_PERF_CLASS: %X\n", unstuff_bits(raw_ssr1, 336, 4)); + gfx_printf("PERFORMANCE_ENHANCE: %02X\n", unstuff_bits(raw_ssr1, 328, 8)); + gfx_printf("DISCARD_SUPPORT: %X\n", unstuff_bits(raw_ssr1, 313, 1)); + gfx_printf("FULE_SUPPORT: %X\n", unstuff_bits(raw_ssr1, 312, 1)); + + gfx_printf("--RSVD-- %02X %X %02X %02X %04X\n", + unstuff_bits(raw_ssr0, 496, 6), unstuff_bits(raw_ssr0, 424, 4), + unstuff_bits(raw_ssr1, 378, 6), unstuff_bits(raw_ssr1, 340, 6), + unstuff_bits(raw_ssr1, 314, 14)); + + gfx_printf("VENDOR_1: %06X %08X\n", + unstuff_bits(raw_ssr1, 288, 24), unstuff_bits(raw_ssr1, 256, 32)); + + gfx_printf("VENDOR_2: %08X %08X %08X %08X\n", + unstuff_bits(raw_ssr2, 224, 32), unstuff_bits(raw_ssr2, 192, 32), + unstuff_bits(raw_ssr2, 160, 32), unstuff_bits(raw_ssr2, 128, 32)); + gfx_printf("VENDOR_3: %08X %08X %08X %08X\n", + unstuff_bits(raw_ssr3, 96 - 0, 32), unstuff_bits(raw_ssr3, 64, 32), + unstuff_bits(raw_ssr3, 32 - 0, 32), unstuff_bits(raw_ssr3, 0, 32)); +} +#endif + static int _sd_storage_send_if_cond(sdmmc_storage_t *storage, bool *is_sdsc) { sdmmc_cmd_t cmdbuf; - u16 vhd_pattern = SD_VHD_27_36 | 0xAA; + u16 vhd_pattern = SD_VHS_27_36 | 0xAA; sdmmc_init_cmd(&cmdbuf, SD_SEND_IF_COND, vhd_pattern, SDMMC_RSP_TYPE_5, 0); if (!sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, NULL, NULL)) { - *is_sdsc = 1; // The SD Card is version 1.X - return 1; + // The SD Card is version 1.X (SDSC) if there is no response. + if (storage->sdmmc->error_sts == SDHCI_ERR_INT_CMD_TIMEOUT) + { + *is_sdsc = 1; + return 1; + } + + return 0; } // For Card version >= 2.0, parse results. u32 resp = 0; - sdmmc_get_rsp(storage->sdmmc, &resp, 4, SDMMC_RSP_TYPE_5); + sdmmc_get_cached_rsp(storage->sdmmc, &resp, SDMMC_RSP_TYPE_5); // Check if VHD was accepted and pattern was properly returned. if ((resp & 0xFFF) == vhd_pattern) @@ -777,19 +998,21 @@ static int _sd_storage_send_if_cond(sdmmc_storage_t *storage, bool *is_sdsc) static int _sd_storage_get_op_cond_once(sdmmc_storage_t *storage, u32 *cond, bool is_sdsc, int bus_uhs_support) { sdmmc_cmd_t cmdbuf; - // Support for Current > 150mA + // Support for Current > 150mA. u32 arg = !is_sdsc ? SD_OCR_XPC : 0; - // Support for handling block-addressed SDHC cards + // Support for handling block-addressed SDHC cards. arg |= !is_sdsc ? SD_OCR_CCS : 0; - // Support for 1.8V + // Support for 1.8V signaling. arg |= (bus_uhs_support && !is_sdsc) ? SD_OCR_S18R : 0; - // This is needed for most cards. Do not set bit7 even if 1.8V is supported. + // Support for 3.3V power supply (VDD1). arg |= SD_OCR_VDD_32_33; + sdmmc_init_cmd(&cmdbuf, SD_APP_OP_COND, arg, SDMMC_RSP_TYPE_3, 0); + if (!_sd_storage_execute_app_cmd(storage, R1_SKIP_STATE_CHECK, is_sdsc ? R1_ILLEGAL_COMMAND : 0, &cmdbuf, NULL, NULL)) return 0; - return sdmmc_get_rsp(storage->sdmmc, cond, 4, SDMMC_RSP_TYPE_3); + return sdmmc_get_cached_rsp(storage->sdmmc, cond, SDMMC_RSP_TYPE_3); } static int _sd_storage_get_op_cond(sdmmc_storage_t *storage, bool is_sdsc, int bus_uhs_support) @@ -805,28 +1028,32 @@ static int _sd_storage_get_op_cond(sdmmc_storage_t *storage, bool is_sdsc, int b // Check if power up is done. if (cond & SD_OCR_BUSY) { -DPRINTF("[SD] op cond: %08X, lv: %d\n", cond, bus_uhs_support); + DPRINTF("[SD] op cond: %08X, lv: %d\n", cond, bus_uhs_support); // Check if card is high capacity. if (cond & SD_OCR_CCS) storage->has_sector_access = 1; // Check if card supports 1.8V signaling. - if (cond & SD_ROCR_S18A && bus_uhs_support) + if (cond & SD_ROCR_S18A && bus_uhs_support && !storage->is_low_voltage) { // Switch to 1.8V signaling. if (_sdmmc_storage_execute_cmd_type1(storage, SD_SWITCH_VOLTAGE, 0, 0, R1_STATE_READY)) { + if (!sdmmc_setup_clock(storage->sdmmc, SDHCI_TIMING_UHS_SDR12)) + return 0; + if (!sdmmc_enable_low_voltage(storage->sdmmc)) return 0; + storage->is_low_voltage = 1; -DPRINTF("-> switched to low voltage\n"); + DPRINTF("-> switched to low voltage\n"); } } else { -DPRINTF("[SD] no low voltage support\n"); + DPRINTF("[SD] no low voltage support\n"); } return 1; @@ -852,7 +1079,7 @@ static int _sd_storage_get_rca(sdmmc_storage_t *storage) break; u32 resp = 0; - if (!sdmmc_get_rsp(storage->sdmmc, &resp, 4, SDMMC_RSP_TYPE_4)) + if (!sdmmc_get_cached_rsp(storage->sdmmc, &resp, SDMMC_RSP_TYPE_4)) break; if (resp >> 16) @@ -874,39 +1101,48 @@ static void _sd_storage_parse_scr(sdmmc_storage_t *storage) // unstuff_bits can parse only 4 u32 u32 resp[4]; - resp[3] = *(u32 *)&storage->raw_scr[4]; - resp[2] = *(u32 *)&storage->raw_scr[0]; + memcpy(&resp[2], storage->raw_scr, 8); + +#ifdef SDMMC_DEBUG_PRINT_SD_REGS + _sd_storage_debug_print_scr((u32 *)storage->raw_scr); +#endif storage->scr.sda_vsn = unstuff_bits(resp, 56, 4); storage->scr.bus_widths = unstuff_bits(resp, 48, 4); - /* If v2.0 is supported, check if Physical Layer Spec v3.0 is supported */ + // If v2.0 is supported, check if Physical Layer Spec v3.0 is supported. if (storage->scr.sda_vsn == SCR_SPEC_VER_2) storage->scr.sda_spec3 = unstuff_bits(resp, 47, 1); if (storage->scr.sda_spec3) - storage->scr.cmds = unstuff_bits(resp, 32, 2); + { + u8 sda_spec4 = unstuff_bits(resp, 42, 1); + if (sda_spec4) + storage->scr.cmds = unstuff_bits(resp, 32, 4); + else + storage->scr.cmds = unstuff_bits(resp, 32, 2); + } } -int _sd_storage_get_scr(sdmmc_storage_t *storage, u8 *buf) +int sd_storage_get_scr(sdmmc_storage_t *storage, u8 *buf) { sdmmc_cmd_t cmdbuf; sdmmc_init_cmd(&cmdbuf, SD_APP_SEND_SCR, 0, SDMMC_RSP_TYPE_1, 0); sdmmc_req_t reqbuf; - reqbuf.buf = buf; - reqbuf.blksize = 8; - reqbuf.num_sectors = 1; - reqbuf.is_write = 0; - reqbuf.is_multi_block = 0; + reqbuf.buf = buf; + reqbuf.blksize = 8; + reqbuf.num_sectors = 1; + reqbuf.is_write = 0; + reqbuf.is_multi_block = 0; reqbuf.is_auto_stop_trn = 0; if (!_sd_storage_execute_app_cmd(storage, R1_STATE_TRAN, 0, &cmdbuf, &reqbuf, NULL)) return 0; u32 tmp = 0; - sdmmc_get_rsp(storage->sdmmc, &tmp, 4, SDMMC_RSP_TYPE_1); + sdmmc_get_cached_rsp(storage->sdmmc, &tmp, SDMMC_RSP_TYPE_1); //Prepare buffer for unstuff_bits - for (int i = 0; i < 8; i+=4) + for (u32 i = 0; i < 8; i+=4) { storage->raw_scr[i + 3] = buf[i]; storage->raw_scr[i + 2] = buf[i + 1]; @@ -914,33 +1150,32 @@ int _sd_storage_get_scr(sdmmc_storage_t *storage, u8 *buf) storage->raw_scr[i] = buf[i + 3]; } _sd_storage_parse_scr(storage); - //gfx_hexdump(0, storage->raw_scr, 8); return _sdmmc_storage_check_card_status(tmp); } -int _sd_storage_switch_get(sdmmc_storage_t *storage, void *buf) +static int _sd_storage_switch_get(sdmmc_storage_t *storage, void *buf) { sdmmc_cmd_t cmdbuf; sdmmc_init_cmd(&cmdbuf, SD_SWITCH, 0xFFFFFF, SDMMC_RSP_TYPE_1, 0); sdmmc_req_t reqbuf; - reqbuf.buf = buf; - reqbuf.blksize = 64; - reqbuf.num_sectors = 1; - reqbuf.is_write = 0; - reqbuf.is_multi_block = 0; + reqbuf.buf = buf; + reqbuf.blksize = SDMMC_CMD_BLOCKSIZE; + reqbuf.num_sectors = 1; + reqbuf.is_write = 0; + reqbuf.is_multi_block = 0; reqbuf.is_auto_stop_trn = 0; if (!sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, &reqbuf, NULL)) return 0; u32 tmp = 0; - sdmmc_get_rsp(storage->sdmmc, &tmp, 4, SDMMC_RSP_TYPE_1); + sdmmc_get_cached_rsp(storage->sdmmc, &tmp, SDMMC_RSP_TYPE_1); return _sdmmc_storage_check_card_status(tmp); } -int _sd_storage_switch(sdmmc_storage_t *storage, void *buf, int mode, int group, u32 arg) +static int _sd_storage_switch(sdmmc_storage_t *storage, void *buf, int mode, int group, u32 arg) { sdmmc_cmd_t cmdbuf; u32 switchcmd = mode << 31 | 0x00FFFFFF; @@ -949,75 +1184,177 @@ int _sd_storage_switch(sdmmc_storage_t *storage, void *buf, int mode, int group, sdmmc_init_cmd(&cmdbuf, SD_SWITCH, switchcmd, SDMMC_RSP_TYPE_1, 0); sdmmc_req_t reqbuf; - reqbuf.buf = buf; - reqbuf.blksize = 64; - reqbuf.num_sectors = 1; - reqbuf.is_write = 0; - reqbuf.is_multi_block = 0; + reqbuf.buf = buf; + reqbuf.blksize = SDMMC_CMD_BLOCKSIZE; + reqbuf.num_sectors = 1; + reqbuf.is_write = 0; + reqbuf.is_multi_block = 0; reqbuf.is_auto_stop_trn = 0; if (!sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, &reqbuf, NULL)) return 0; u32 tmp = 0; - sdmmc_get_rsp(storage->sdmmc, &tmp, 4, SDMMC_RSP_TYPE_1); + sdmmc_get_cached_rsp(storage->sdmmc, &tmp, SDMMC_RSP_TYPE_1); return _sdmmc_storage_check_card_status(tmp); } -void _sd_storage_set_current_limit(sdmmc_storage_t *storage, u16 current_limit, u8 *buf) +static void _sd_storage_set_power_limit(sdmmc_storage_t *storage, u16 power_limit, u8 *buf) { - u32 pwr = SD_SET_CURRENT_LIMIT_200; + u32 pwr = SD_SET_POWER_LIMIT_0_72; - if (current_limit & SD_MAX_CURRENT_800) - pwr = SD_SET_CURRENT_LIMIT_800; - else if (current_limit & SD_MAX_CURRENT_600) - pwr = SD_SET_CURRENT_LIMIT_600; - else if (current_limit & SD_MAX_CURRENT_400) - pwr = SD_SET_CURRENT_LIMIT_400; + // If UHS-I only, anything above 1.44W defaults to 1.44W. + /* + if (power_limit & SD_MAX_POWER_2_88) + pwr = SD_SET_POWER_LIMIT_2_88; + else if (power_limit & SD_MAX_POWER_2_16) + pwr = SD_SET_POWER_LIMIT_2_16; + */ + if (power_limit & SD_MAX_POWER_1_44) + pwr = SD_SET_POWER_LIMIT_1_44; - _sd_storage_switch(storage, buf, SD_SWITCH_SET, 3, pwr); + _sd_storage_switch(storage, buf, SD_SWITCH_SET, SD_SWITCH_GRP_PWRLIM, pwr); - if (((buf[15] >> 4) & 0x0F) == pwr) + switch ((buf[15] >> 4) & 0x0F) { - switch (pwr) - { - case SD_SET_CURRENT_LIMIT_800: -DPRINTF("[SD] power limit raised to 800mA\n"); - break; + /* + case SD_SET_POWER_LIMIT_2_88: + DPRINTF("[SD] power limit raised to 2880 mW\n"); + break; - case SD_SET_CURRENT_LIMIT_600: -DPRINTF("[SD] power limit raised to 600mA\n"); - break; + case SD_SET_POWER_LIMIT_2_16: + DPRINTF("[SD] power limit raised to 2160 mW\n"); + break; + */ + case SD_SET_POWER_LIMIT_1_44: + DPRINTF("[SD] power limit raised to 1440 mW\n"); + break; - case SD_SET_CURRENT_LIMIT_400: -DPRINTF("[SD] power limit raised to 400mA\n"); - break; - - default: - case SD_SET_CURRENT_LIMIT_200: -DPRINTF("[SD] power limit defaulted to 200mA\n"); - break; - } + default: + case SD_SET_POWER_LIMIT_0_72: + DPRINTF("[SD] power limit defaulted to 720 mW\n"); + break; } } -int _sd_storage_enable_highspeed(sdmmc_storage_t *storage, u32 hs_type, u8 *buf) +int _sd_storage_set_driver_type(sdmmc_storage_t *storage, u32 driver, u8 *buf) { - if (!_sd_storage_switch(storage, buf, SD_SWITCH_CHECK, 0, hs_type)) + if (!_sd_storage_switch(storage, buf, SD_SWITCH_CHECK, SD_SWITCH_GRP_DRVSTR, driver)) + return 0; + + u32 driver_out = buf[15] & 0xF; + if (driver_out != driver) + return 0; + DPRINTF("[SD] supports Driver Strength %d\n", driver); + + if (!_sd_storage_switch(storage, buf, SD_SWITCH_SET, SD_SWITCH_GRP_DRVSTR, driver)) + return 0; + + if (driver_out != (buf[15] & 0xF)) + return 0; + DPRINTF("[SD] card accepted Driver Strength %d\n", driver); + + sdmmc_setup_drv_type(storage->sdmmc, driver); + + return 1; +} + +/* + * SD Card DDR200 (DDR208) support + * + * DLL Tuning (a) or Tuning Window (b) procedure: + * 1. Check that Vendor Specific Command System is supported. + * Used as Enable DDR200 Bus. + * 2. Enable DDR200 bus mode via setting 14 to Group 2 via CMD6. + * Access Mode group is left to default 0 (SDR12). + * 3. Setup clock to 200 or 208 MHz. + * 4a. Set host to DDR200/HS400 bus mode that enables DLL syncing. + * Actual implementation supported by all DDR200 cards. + * -- + * 4b. Set host to DDR50 bus mode that supports such high clocks. + * Execute Manual Tuning. + * Limited to non-Sandisk cards. + * + * On Tegra SoCs, that can be done with DDR50 host mode. + * That's because HS400 4-bit or HS400 generally, is not supported on SD SDMMC. + * And also, tuning can't be done automatically on any DDR mode. + * So it needs to be done manually and selected tap will be applied from the + * biggest sampling window. + * That allows DDR200 support on every DDR200 SD card, other than the original + * maker of DDR200, Sandisk. + * + * On the original implementation of DDR200 from Sandisk, a DLL mechanism, + * like the one in eMMC HS400 is mandatory. + * So the card can start data signals whenever it wants, and the host should + * synchronize to the first DAT signal edge change. + * Every single other vendor that implemented that, always starts data transfers + * aligned to clock. That basically makes DDR200 in such SD cards a SDR104 but + * sampled on both edges. So effectively, it's an in-spec signal with DDR50, + * only that is clocked at 200MHz, instead of 50MHz. + * So the extra needed thing is using a tuning window, which is absent from the + * original implementation, since DDL syncing does not use that. + * + * On DLL tuning method expected cards, the tuning window is tiny. + * So check against a minimum of 8 taps window, to disallow DDR200. + */ +#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT +static int _sd_storage_enable_DDR200(sdmmc_storage_t *storage, u8 *buf) +{ + u32 cmd_system = UHS_DDR200_BUS_SPEED; + if (!_sd_storage_switch(storage, buf, SD_SWITCH_CHECK, SD_SWITCH_GRP_CMDSYS, cmd_system)) + return 0; + + u32 system_out = (buf[16] >> 4) & 0xF; + if (system_out != cmd_system) + return 0; + DPRINTF("[SD] supports DDR200 mode\n"); + + u16 total_pwr_consumption = ((u16)buf[0] << 8) | buf[1]; + DPRINTF("[SD] max power: %d mW\n", total_pwr_consumption * 3600 / 1000); + storage->max_power = total_pwr_consumption; + + if (total_pwr_consumption <= 800) + { + if (!_sd_storage_switch(storage, buf, SD_SWITCH_SET, SD_SWITCH_GRP_CMDSYS, cmd_system)) + return 0; + + if (system_out != ((buf[16] >> 4) & 0xF)) + return 0; + DPRINTF("[SD] card accepted DDR200\n"); + + if (!sdmmc_setup_clock(storage->sdmmc, SDHCI_TIMING_UHS_DDR200)) + return 0; + DPRINTF("[SD] after setup clock DDR200\n"); + + if (!sdmmc_tuning_execute(storage->sdmmc, SDHCI_TIMING_UHS_DDR200, MMC_SEND_TUNING_BLOCK)) + return 0; + DPRINTF("[SD] after tuning DDR200\n"); + + return _sdmmc_storage_check_status(storage); + } + + DPRINTF("[SD] card max power over limit\n"); + return 0; +} +#endif + +static int _sd_storage_set_card_bus_speed(sdmmc_storage_t *storage, u32 hs_type, u8 *buf) +{ + if (!_sd_storage_switch(storage, buf, SD_SWITCH_CHECK, SD_SWITCH_GRP_ACCESS, hs_type)) return 0; -DPRINTF("[SD] supports (U)HS mode: %d\n", buf[16] & 0xF); u32 type_out = buf[16] & 0xF; if (type_out != hs_type) return 0; -DPRINTF("[SD] supports selected (U)HS mode\n"); + DPRINTF("[SD] supports selected (U)HS mode %d\n", buf[16] & 0xF); u16 total_pwr_consumption = ((u16)buf[0] << 8) | buf[1]; -DPRINTF("[SD] total max current: %d\n", total_pwr_consumption); + DPRINTF("[SD] max power: %d mW\n", total_pwr_consumption * 3600 / 1000); + storage->max_power = total_pwr_consumption; if (total_pwr_consumption <= 800) { - if (!_sd_storage_switch(storage, buf, SD_SWITCH_SET, 0, hs_type)) + if (!_sd_storage_switch(storage, buf, SD_SWITCH_SET, SD_SWITCH_GRP_ACCESS, hs_type)) return 0; if (type_out != (buf[16] & 0xF)) @@ -1025,37 +1362,66 @@ DPRINTF("[SD] total max current: %d\n", total_pwr_consumption); return 1; } -DPRINTF("[SD] card max current over limit\n"); + DPRINTF("[SD] card max power over limit\n"); return 0; } -int _sd_storage_enable_uhs_low_volt(sdmmc_storage_t *storage, u32 type, u8 *buf) +int sd_storage_get_fmodes(sdmmc_storage_t *storage, u8 *buf, sd_func_modes_t *fmodes) { - if (sdmmc_get_bus_width(storage->sdmmc) != SDMMC_BUS_WIDTH_4) - return 0; + if (!buf) + buf = (u8 *)SDMMC_UPPER_BUFFER; if (!_sd_storage_switch_get(storage, buf)) return 0; - //gfx_hexdump(0, (u8 *)buf, 64); - u8 access_mode = buf[13]; - u16 current_limit = buf[7] | buf[6] << 8; -DPRINTF("[SD] access: %02X, current: %02X\n", access_mode, current_limit); + fmodes->access_mode = buf[13] | (buf[12] << 8); + fmodes->cmd_system = buf[11] | (buf[10] << 8); + fmodes->driver_strength = buf[9] | (buf[8] << 8); + fmodes->power_limit = buf[7] | (buf[6] << 8); - // Try to raise the current limit to let the card perform better. - _sd_storage_set_current_limit(storage, current_limit, buf); + return 1; +} + +static int _sd_storage_enable_uhs_low_volt(sdmmc_storage_t *storage, u32 type, u8 *buf) +{ + sd_func_modes_t fmodes; + + if (sdmmc_get_bus_width(storage->sdmmc) != SDMMC_BUS_WIDTH_4) + return 0; + + if (!sd_storage_get_fmodes(storage, buf, &fmodes)) + return 0; + +#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT + DPRINTF("[SD] access: %02X, power: %02X, cmd: %02X\n", fmodes.access_mode, fmodes.power_limit, fmodes.cmd_system); +#else + DPRINTF("[SD] access: %02X, power: %02X\n", fmodes.access_mode, fmodes.power_limit); +#endif u32 hs_type = 0; switch (type) { +#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT + case SDHCI_TIMING_UHS_DDR200: + // Fall through if DDR200 is not supported. + if (fmodes.cmd_system & SD_MODE_UHS_DDR200) + { + DPRINTF("[SD] setting bus speed to DDR200\n"); + storage->csd.busspeed = 200; + _sd_storage_set_power_limit(storage, fmodes.power_limit, buf); + return _sd_storage_enable_DDR200(storage, buf); + } +#endif + case SDHCI_TIMING_UHS_SDR104: case SDHCI_TIMING_UHS_SDR82: // Fall through if not supported. - if (access_mode & SD_MODE_UHS_SDR104) + if (fmodes.access_mode & SD_MODE_UHS_SDR104) { + type = SDHCI_TIMING_UHS_SDR104; hs_type = UHS_SDR104_BUS_SPEED; -DPRINTF("[SD] bus speed set to SDR104\n"); + DPRINTF("[SD] setting bus speed to SDR104\n"); switch (type) { case SDHCI_TIMING_UHS_SDR104: @@ -1067,66 +1433,76 @@ DPRINTF("[SD] bus speed set to SDR104\n"); } break; } + case SDHCI_TIMING_UHS_SDR50: - if (access_mode & SD_MODE_UHS_SDR50) + if (fmodes.access_mode & SD_MODE_UHS_SDR50) { - type = SDHCI_TIMING_UHS_SDR50; + type = SDHCI_TIMING_UHS_SDR50; hs_type = UHS_SDR50_BUS_SPEED; -DPRINTF("[SD] bus speed set to SDR50\n"); + DPRINTF("[SD] setting bus speed to SDR50\n"); storage->csd.busspeed = 50; break; } +/* + case SDHCI_TIMING_UHS_DDR50: + if (fmodes.access_mode & SD_MODE_UHS_DDR50) + { + type = SDHCI_TIMING_UHS_DDR50; + hs_type = UHS_DDR50_BUS_SPEED; + DPRINTF("[SD] setting bus speed to DDR50\n"); + storage->csd.busspeed = 50; + break; + } +*/ case SDHCI_TIMING_UHS_SDR25: - if (access_mode & SD_MODE_UHS_SDR25) + if (fmodes.access_mode & SD_MODE_UHS_SDR25) { type = SDHCI_TIMING_UHS_SDR25; hs_type = UHS_SDR25_BUS_SPEED; -DPRINTF("[SD] bus speed set to SDR25\n"); + DPRINTF("[SD] setting bus speed to SDR25\n"); storage->csd.busspeed = 25; break; } - case SDHCI_TIMING_UHS_SDR12: - if (!(access_mode & SD_MODE_UHS_SDR12)) - return 0; - type = SDHCI_TIMING_UHS_SDR12; - hs_type = UHS_SDR12_BUS_SPEED; -DPRINTF("[SD] bus speed set to SDR12\n"); - storage->csd.busspeed = 12; - break; default: - return 0; - break; + DPRINTF("[SD] bus speed defaulted to SDR12\n"); + storage->csd.busspeed = 12; + return 1; } - if (!_sd_storage_enable_highspeed(storage, hs_type, buf)) + // Try to raise the power limit to let the card perform better. + if (hs_type != UHS_SDR25_BUS_SPEED) // Not applicable for SDR12/SDR25. + _sd_storage_set_power_limit(storage, fmodes.power_limit, buf); + + // Setup and set selected card and bus speed. + if (!_sd_storage_set_card_bus_speed(storage, hs_type, buf)) return 0; -DPRINTF("[SD] card accepted UHS\n"); + DPRINTF("[SD] card accepted UHS\n"); + if (!sdmmc_setup_clock(storage->sdmmc, type)) return 0; -DPRINTF("[SD] after setup clock\n"); + DPRINTF("[SD] after setup clock\n"); + if (!sdmmc_tuning_execute(storage->sdmmc, type, MMC_SEND_TUNING_BLOCK)) return 0; -DPRINTF("[SD] after tuning\n"); + DPRINTF("[SD] after tuning\n"); + return _sdmmc_storage_check_status(storage); } -int _sd_storage_enable_hs_high_volt(sdmmc_storage_t *storage, u8 *buf) +static int _sd_storage_enable_hs_high_volt(sdmmc_storage_t *storage, u8 *buf) { - if (!_sd_storage_switch_get(storage, buf)) + sd_func_modes_t fmodes; + + if (!sd_storage_get_fmodes(storage, buf, &fmodes)) return 0; - //gfx_hexdump(0, (u8 *)buf, 64); - u8 access_mode = buf[13]; - u16 current_limit = buf[7] | buf[6] << 8; + DPRINTF("[SD] access: %02X, power: %02X\n", fmodes.access_mode, fmodes.power_limit); - // Try to raise the current limit to let the card perform better. - _sd_storage_set_current_limit(storage, current_limit, buf); - - if (!(access_mode & SD_MODE_HIGH_SPEED)) + if (!(fmodes.access_mode & SD_MODE_HIGH_SPEED)) return 1; - if (!_sd_storage_enable_highspeed(storage, HIGH_SPEED_BUS_SPEED, buf)) + if (!_sd_storage_set_card_bus_speed(storage, HIGH_SPEED_BUS_SPEED, buf)) return 0; if (!_sdmmc_storage_check_status(storage)) @@ -1146,7 +1522,7 @@ u32 sd_storage_get_ssr_au(sdmmc_storage_t *storage) { u32 shift = au_size; au_size = shift ? 8 : 0; - au_size <<= shift; + au_size <<= shift; } else { @@ -1176,16 +1552,20 @@ u32 sd_storage_get_ssr_au(sdmmc_storage_t *storage) static void _sd_storage_parse_ssr(sdmmc_storage_t *storage) { // unstuff_bits supports only 4 u32 so break into 2 x u32x4 groups. - u32 raw_ssr1[4]; - u32 raw_ssr2[4]; + u32 raw_ssr1[4]; // 511:384. + u32 raw_ssr2[4]; // 383:256. memcpy(raw_ssr1, &storage->raw_ssr[0], 16); memcpy(raw_ssr2, &storage->raw_ssr[16], 16); - storage->ssr.bus_width = (unstuff_bits(raw_ssr1, 510 - 384, 2) & SD_BUS_WIDTH_4) ? 4 : 1; - storage->ssr.protected_size = unstuff_bits(raw_ssr1, 448 - 384, 32); +#ifdef SDMMC_DEBUG_PRINT_SD_REGS + _sd_storage_debug_print_ssr(storage->raw_ssr); +#endif - u32 speed_class = unstuff_bits(raw_ssr1, 440 - 384, 8); + storage->ssr.bus_width = (unstuff_bits(raw_ssr1, 510, 2) & SD_BUS_WIDTH_4) ? 4 : 1; + storage->ssr.protected_size = unstuff_bits(raw_ssr1, 448, 32); + + u32 speed_class = unstuff_bits(raw_ssr1, 440, 8); switch(speed_class) { case 0: @@ -1203,12 +1583,94 @@ static void _sd_storage_parse_ssr(sdmmc_storage_t *storage) storage->ssr.speed_class = speed_class; break; } - storage->ssr.uhs_grade = unstuff_bits(raw_ssr1, 396 - 384, 4); - storage->ssr.video_class = unstuff_bits(raw_ssr1, 384 - 384, 8); - storage->ssr.app_class = unstuff_bits(raw_ssr2, 336 - 256, 4); + storage->ssr.uhs_grade = unstuff_bits(raw_ssr1, 396, 4); + storage->ssr.video_class = unstuff_bits(raw_ssr1, 384, 8); + storage->ssr.app_class = unstuff_bits(raw_ssr2, 336, 4); - storage->ssr.au_size = unstuff_bits(raw_ssr1, 428 - 384, 4); - storage->ssr.uhs_au_size = unstuff_bits(raw_ssr1, 392 - 384, 4); + storage->ssr.au_size = unstuff_bits(raw_ssr1, 428, 4); + storage->ssr.uhs_au_size = unstuff_bits(raw_ssr1, 392, 4); + + storage->ssr.perf_enhance = unstuff_bits(raw_ssr2, 328, 8); +} + +int sd_storage_parse_perf_enhance(sdmmc_storage_t *storage, u8 fno, u8 page, u16 offset, u8 *buf) +{ + // Check status reg for support. + storage->ser.cache = (storage->ssr.perf_enhance >> 2) & BIT(0); + storage->ser.cmdq = (storage->ssr.perf_enhance >> 3) & 0x1F; + + if (!sd_storage_get_ext_reg(storage, fno, page, offset, 512, buf)) + { + storage->ser.cache_ext = 0; + storage->ser.cmdq_ext = 0; + + return 0; + } + + storage->ser.cache_ext = buf[4] & BIT(0); + storage->ser.cmdq_ext = buf[6] & 0x1F; + + return 1; +} + +static void _sd_storage_parse_ext_reg(sdmmc_storage_t *storage, u8 *buf, u16 *addr_next) +{ + u16 addr = *addr_next; + + // Address to the next extension. + *addr_next = (buf[addr + 41] << 8) | buf[addr + 40]; + + u16 sfc = (buf[addr + 1] << 8) | buf[addr]; + + u32 reg_sets = buf[addr + 42]; + +#ifdef SDMMC_DEBUG_PRINT_SD_REGS + for (u32 i = 0; i < reg_sets; i++) + { + u32 reg_set_addr; + memcpy(®_set_addr, &buf[addr + 44 + 4 * i], 4); + u16 off = reg_set_addr & 0x1FF; + u8 page = reg_set_addr >> 9 & 0xFF; + u8 fno = reg_set_addr >> 18 & 0xFF; + gfx_printf("Addr: %04X sfc:%02X - fno:%02X, page:%02X, off:%04X\n", addr, sfc, fno, page, off); + } +#endif + + // Parse Performance Enhance. + if (sfc == 2 && reg_sets == 1) + { + u32 reg_set0_addr; + memcpy(®_set0_addr, &buf[addr + 44], 4); + u16 off = reg_set0_addr & 0x1FF; + u8 page = reg_set0_addr >> 9 & 0xFF; + u8 fno = reg_set0_addr >> 18 & 0xFF; + + if (sd_storage_parse_perf_enhance(storage, fno, page, off, buf)) + storage->ser.valid = 1; + } +} + +void sd_storage_get_ext_regs(sdmmc_storage_t *storage, u8 *buf) +{ + DREGPRINTF("SD Extension Registers:\n\n"); + + if (!(storage->scr.cmds & BIT(2))) + { + DREGPRINTF("Not Supported!\n"); + return; + } + + if (!sd_storage_get_ext_reg(storage, 0, 0, 0, 512, buf)) + { + DREGPRINTF("Failed to get general info!\n"); + return; + } + + u16 size = (buf[3] << 8) | buf[2]; + u16 addr_next = 16; + u32 num_ext = buf[4]; + for (u32 i = 0; i < num_ext && addr_next < size; i++) + _sd_storage_parse_ext_reg(storage, buf, &addr_next); } int sd_storage_get_ssr(sdmmc_storage_t *storage, u8 *buf) @@ -1217,16 +1679,16 @@ int sd_storage_get_ssr(sdmmc_storage_t *storage, u8 *buf) sdmmc_init_cmd(&cmdbuf, SD_APP_SD_STATUS, 0, SDMMC_RSP_TYPE_1, 0); sdmmc_req_t reqbuf; - reqbuf.buf = buf; - reqbuf.blksize = 64; - reqbuf.num_sectors = 1; - reqbuf.is_write = 0; - reqbuf.is_multi_block = 0; + reqbuf.buf = buf; + reqbuf.blksize = SDMMC_CMD_BLOCKSIZE; + reqbuf.num_sectors = 1; + reqbuf.is_write = 0; + reqbuf.is_multi_block = 0; reqbuf.is_auto_stop_trn = 0; if (!(storage->csd.cmdclass & CCC_APP_SPEC)) { -DPRINTF("[SD] ssr: Not supported\n"); + DPRINTF("[SD] ssr: Not supported\n"); return 0; } @@ -1234,10 +1696,10 @@ DPRINTF("[SD] ssr: Not supported\n"); return 0; u32 tmp = 0; - sdmmc_get_rsp(storage->sdmmc, &tmp, 4, SDMMC_RSP_TYPE_1); + sdmmc_get_cached_rsp(storage->sdmmc, &tmp, SDMMC_RSP_TYPE_1); // Convert buffer to LE. - for (int i = 0; i < 64; i += 4) + for (u32 i = 0; i < SDMMC_CMD_BLOCKSIZE; i += 4) { storage->raw_ssr[i + 3] = buf[i]; storage->raw_ssr[i + 2] = buf[i + 1]; @@ -1246,7 +1708,6 @@ DPRINTF("[SD] ssr: Not supported\n"); } _sd_storage_parse_ssr(storage); - //gfx_hexdump(0, storage->raw_ssr, 64); return _sdmmc_storage_check_card_status(tmp); } @@ -1255,43 +1716,51 @@ static void _sd_storage_parse_cid(sdmmc_storage_t *storage) { u32 *raw_cid = (u32 *)&(storage->raw_cid); - storage->cid.manfid = unstuff_bits(raw_cid, 120, 8); - storage->cid.oemid = unstuff_bits(raw_cid, 104, 16); +#ifdef SDMMC_DEBUG_PRINT_SD_REGS + _sd_storage_debug_print_cid(raw_cid); +#endif + + storage->cid.manfid = unstuff_bits(raw_cid, 120, 8); + storage->cid.oemid = unstuff_bits(raw_cid, 104, 16); storage->cid.prod_name[0] = unstuff_bits(raw_cid, 96, 8); storage->cid.prod_name[1] = unstuff_bits(raw_cid, 88, 8); storage->cid.prod_name[2] = unstuff_bits(raw_cid, 80, 8); storage->cid.prod_name[3] = unstuff_bits(raw_cid, 72, 8); storage->cid.prod_name[4] = unstuff_bits(raw_cid, 64, 8); - storage->cid.hwrev = unstuff_bits(raw_cid, 60, 4); - storage->cid.fwrev = unstuff_bits(raw_cid, 56, 4); - storage->cid.serial = unstuff_bits(raw_cid, 24, 32); - storage->cid.year = unstuff_bits(raw_cid, 12, 8) + 2000; - storage->cid.month = unstuff_bits(raw_cid, 8, 4); + storage->cid.hwrev = unstuff_bits(raw_cid, 60, 4); + storage->cid.fwrev = unstuff_bits(raw_cid, 56, 4); + storage->cid.serial = unstuff_bits(raw_cid, 24, 32); + storage->cid.year = unstuff_bits(raw_cid, 12, 8) + 2000; + storage->cid.month = unstuff_bits(raw_cid, 8, 4); } static void _sd_storage_parse_csd(sdmmc_storage_t *storage) { u32 *raw_csd = (u32 *)&(storage->raw_csd); - storage->csd.structure = unstuff_bits(raw_csd, 126, 2); - storage->csd.cmdclass = unstuff_bits(raw_csd, 84, 12); +#ifdef SDMMC_DEBUG_PRINT_SD_REGS + _sd_storage_debug_print_csd(raw_csd); +#endif + + storage->csd.structure = unstuff_bits(raw_csd, 126, 2); + storage->csd.cmdclass = unstuff_bits(raw_csd, 84, 12); storage->csd.read_blkbits = unstuff_bits(raw_csd, 80, 4); storage->csd.write_protect = unstuff_bits(raw_csd, 12, 2); switch(storage->csd.structure) { case 0: storage->csd.capacity = (1 + unstuff_bits(raw_csd, 62, 12)) << (unstuff_bits(raw_csd, 47, 3) + 2); - storage->csd.capacity <<= unstuff_bits(raw_csd, 80, 4) - 9; // Convert native block size to LBA 512B. + storage->csd.capacity <<= unstuff_bits(raw_csd, 80, 4) - 9; // Convert native block size to LBA SDMMC_DAT_BLOCKSIZE. break; case 1: - storage->csd.c_size = (1 + unstuff_bits(raw_csd, 48, 22)); - storage->csd.capacity = storage->csd.c_size << 10; + storage->csd.c_size = (1 + unstuff_bits(raw_csd, 48, 22)); + storage->csd.capacity = storage->csd.c_size << 10; storage->csd.read_blkbits = 9; break; default: -DPRINTF("[SD] unknown CSD structure %d\n", storage->csd.structure); + DPRINTF("[SD] unknown CSD structure %d\n", storage->csd.structure); break; } @@ -1308,6 +1777,7 @@ static bool _sdmmc_storage_get_bus_uhs_support(u32 bus_width, u32 type) case SDHCI_TIMING_UHS_SDR104: case SDHCI_TIMING_UHS_SDR82: case SDHCI_TIMING_UHS_DDR50: + case SDHCI_TIMING_UHS_DDR200: if (bus_width == SDMMC_BUS_WIDTH_4) return true; default: @@ -1326,11 +1796,11 @@ void sdmmc_storage_init_wait_sd() int sdmmc_storage_init_sd(sdmmc_storage_t *storage, sdmmc_t *sdmmc, u32 bus_width, u32 type) { u32 tmp = 0; - int is_sdsc = 0; + bool is_sdsc = 0; u8 *buf = (u8 *)SDMMC_UPPER_BUFFER; bool bus_uhs_support = _sdmmc_storage_get_bus_uhs_support(bus_width, type); -DPRINTF("[SD] init: bus: %d, type: %d\n", bus_width, type); + DPRINTF("[SD]-[init: bus: %d, type: %d]\n", bus_width, type); // Some cards (SanDisk U1), do not like a fast power cycle. Wait min 100ms. sdmmc_storage_init_wait_sd(); @@ -1338,61 +1808,62 @@ DPRINTF("[SD] init: bus: %d, type: %d\n", bus_width, type); memset(storage, 0, sizeof(sdmmc_storage_t)); storage->sdmmc = sdmmc; - if (!sdmmc_init(sdmmc, SDMMC_1, SDMMC_POWER_3_3, SDMMC_BUS_WIDTH_1, SDHCI_TIMING_SD_ID, SDMMC_POWER_SAVE_DISABLE)) + if (!sdmmc_init(sdmmc, SDMMC_1, SDMMC_POWER_3_3, SDMMC_BUS_WIDTH_1, SDHCI_TIMING_SD_ID)) return 0; -DPRINTF("[SD] after init\n"); + DPRINTF("[SD] after init\n"); - usleep(1000 + (74000 + sdmmc->divisor - 1) / sdmmc->divisor); + // Wait 1ms + 74 cycles. + usleep(1000 + (74 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); if (!_sdmmc_storage_go_idle_state(storage)) return 0; -DPRINTF("[SD] went to idle state\n"); + DPRINTF("[SD] went to idle state\n"); if (!_sd_storage_send_if_cond(storage, &is_sdsc)) return 0; -DPRINTF("[SD] after send if cond\n"); + DPRINTF("[SD] after send if cond\n"); if (!_sd_storage_get_op_cond(storage, is_sdsc, bus_uhs_support)) return 0; -DPRINTF("[SD] got op cond\n"); + DPRINTF("[SD] got op cond\n"); if (!_sdmmc_storage_get_cid(storage)) return 0; -DPRINTF("[SD] got cid\n"); + DPRINTF("[SD] got cid\n"); _sd_storage_parse_cid(storage); if (!_sd_storage_get_rca(storage)) return 0; -DPRINTF("[SD] got rca (= %04X)\n", storage->rca); + DPRINTF("[SD] got rca (= %04X)\n", storage->rca); if (!_sdmmc_storage_get_csd(storage)) return 0; -DPRINTF("[SD] got csd\n"); + DPRINTF("[SD] got csd\n"); _sd_storage_parse_csd(storage); if (!storage->is_low_voltage) { if (!sdmmc_setup_clock(storage->sdmmc, SDHCI_TIMING_SD_DS12)) return 0; -DPRINTF("[SD] after setup default clock\n"); + DPRINTF("[SD] after setup default clock\n"); } if (!_sdmmc_storage_select_card(storage)) return 0; -DPRINTF("[SD] card selected\n"); + DPRINTF("[SD] card selected\n"); - if (!_sdmmc_storage_set_blocklen(storage, 512)) + if (!_sdmmc_storage_set_blocklen(storage, SD_BLOCKSIZE)) return 0; -DPRINTF("[SD] set blocklen to 512\n"); + DPRINTF("[SD] set blocklen to SD_BLOCKSIZE\n"); // Disconnect Card Detect resistor from DAT3. if (!_sd_storage_execute_app_cmd_type1(storage, &tmp, SD_APP_SET_CLR_CARD_DETECT, 0, 0, R1_STATE_TRAN)) return 0; -DPRINTF("[SD] cleared card detect\n"); + DPRINTF("[SD] cleared card detect\n"); - if (!_sd_storage_get_scr(storage, buf)) + if (!sd_storage_get_scr(storage, buf)) return 0; -DPRINTF("[SD] got scr\n"); + DPRINTF("[SD] got scr\n"); // If card supports a wider bus and if it's not SD Version 1.0 switch bus width. if (bus_width == SDMMC_BUS_WIDTH_4 && (storage->scr.bus_widths & BIT(SD_BUS_WIDTH_4)) && storage->scr.sda_vsn) @@ -1401,26 +1872,26 @@ DPRINTF("[SD] got scr\n"); return 0; sdmmc_set_bus_width(storage->sdmmc, SDMMC_BUS_WIDTH_4); -DPRINTF("[SD] switched to wide bus width\n"); + DPRINTF("[SD] switched to wide bus width\n"); } else { bus_width = SDMMC_BUS_WIDTH_1; -DPRINTF("[SD] SD does not support wide bus width\n"); + DPRINTF("[SD] SD does not support wide bus width\n"); } if (storage->is_low_voltage) { if (!_sd_storage_enable_uhs_low_volt(storage, type, buf)) return 0; -DPRINTF("[SD] enabled UHS\n"); + DPRINTF("[SD] enabled UHS\n"); } else if (type != SDHCI_TIMING_SD_DS12 && storage->scr.sda_vsn) // Not default speed and not SD Version 1.0. { if (!_sd_storage_enable_hs_high_volt(storage, buf)) return 0; -DPRINTF("[SD] enabled HS\n"); + DPRINTF("[SD] enabled HS\n"); switch (bus_width) { case SDMMC_BUS_WIDTH_4: @@ -1436,7 +1907,7 @@ DPRINTF("[SD] enabled HS\n"); // Parse additional card info from sd status. if (sd_storage_get_ssr(storage, buf)) { -DPRINTF("[SD] got sd status\n"); + DPRINTF("[SD] got sd status\n"); } sdmmc_card_clock_powersave(sdmmc, SDMMC_POWER_SAVE_ENABLE); @@ -1457,11 +1928,11 @@ int _gc_storage_custom_cmd(sdmmc_storage_t *storage, void *buf) sdmmc_init_cmd(&cmdbuf, MMC_VENDOR_60_CMD, 0, SDMMC_RSP_TYPE_1, 1); sdmmc_req_t reqbuf; - reqbuf.buf = buf; - reqbuf.blksize = 64; - reqbuf.num_sectors = 1; - reqbuf.is_write = 1; - reqbuf.is_multi_block = 0; + reqbuf.buf = buf; + reqbuf.blksize = SDMMC_CMD_BLOCKSIZE; + reqbuf.num_sectors = 1; + reqbuf.is_write = 1; + reqbuf.is_multi_block = 0; reqbuf.is_auto_stop_trn = 0; if (!sdmmc_execute_cmd(storage->sdmmc, &cmdbuf, &reqbuf, NULL)) @@ -1470,7 +1941,7 @@ int _gc_storage_custom_cmd(sdmmc_storage_t *storage, void *buf) return 0; } - if (!sdmmc_get_rsp(storage->sdmmc, &resp, 4, SDMMC_RSP_TYPE_1)) + if (!sdmmc_get_cached_rsp(storage->sdmmc, &resp, SDMMC_RSP_TYPE_1)) return 0; if (!_sdmmc_storage_check_card_status(resp)) return 0; @@ -1482,15 +1953,16 @@ int sdmmc_storage_init_gc(sdmmc_storage_t *storage, sdmmc_t *sdmmc) memset(storage, 0, sizeof(sdmmc_storage_t)); storage->sdmmc = sdmmc; - if (!sdmmc_init(sdmmc, SDMMC_2, SDMMC_POWER_1_8, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS102, SDMMC_POWER_SAVE_DISABLE)) + if (!sdmmc_init(sdmmc, SDMMC_2, SDMMC_POWER_1_8, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS100)) return 0; -DPRINTF("[gc] after init\n"); + DPRINTF("[GC] after init\n"); - usleep(1000 + (10000 + sdmmc->divisor - 1) / sdmmc->divisor); + // Wait 1ms + 10 clock cycles. + usleep(1000 + (10 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); - if (!sdmmc_tuning_execute(storage->sdmmc, SDHCI_TIMING_MMC_HS102, MMC_SEND_TUNING_BLOCK_HS200)) + if (!sdmmc_tuning_execute(storage->sdmmc, SDHCI_TIMING_MMC_HS100, MMC_SEND_TUNING_BLOCK_HS200)) return 0; -DPRINTF("[gc] after tuning\n"); + DPRINTF("[GC] after tuning\n"); sdmmc_card_clock_powersave(sdmmc, SDMMC_POWER_SAVE_ENABLE); diff --git a/bdk/storage/sdmmc.h b/bdk/storage/sdmmc.h index 5dcd10f..6da130a 100644 --- a/bdk/storage/sdmmc.h +++ b/bdk/storage/sdmmc.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2025 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,8 +19,12 @@ #define _SDMMC_H_ #include +#include #include +#define SDMMC_CMD_BLOCKSIZE 64 +#define SDMMC_DAT_BLOCKSIZE 512 + extern u32 sd_power_cycle_time_start; typedef enum _sdmmc_type @@ -129,10 +133,7 @@ typedef struct _mmc_csd u16 cmdclass; u32 c_size; u32 r2w_factor; - u32 max_dtr; - u32 erase_size; /* In sectors */ u32 read_blkbits; - u32 write_blkbits; u32 capacity; u8 write_protect; u16 busspeed; @@ -173,19 +174,30 @@ typedef struct _sd_ssr u8 app_class; u8 au_size; u8 uhs_au_size; + u8 perf_enhance; u32 protected_size; } sd_ssr_t; +typedef struct _sd_ext_reg_t +{ + u8 cmdq; + u8 cmdq_ext; + u8 cache; + u8 cache_ext; + int valid; +} sd_ext_reg_t; + /*! SDMMC storage context. */ typedef struct _sdmmc_storage_t { sdmmc_t *sdmmc; - u32 rca; - int has_sector_access; - u32 sec_cnt; - int is_low_voltage; - u32 partition; int initialized; + int is_low_voltage; + int has_sector_access; + u32 rca; + u32 sec_cnt; + u32 partition; + u32 max_power; u8 raw_cid[0x10]; u8 raw_csd[0x10]; u8 raw_scr[8]; @@ -195,8 +207,17 @@ typedef struct _sdmmc_storage_t mmc_ext_csd_t ext_csd; sd_scr_t scr; sd_ssr_t ssr; + sd_ext_reg_t ser; } sdmmc_storage_t; +typedef struct _sd_func_modes_t +{ + u16 access_mode; + u16 cmd_system; + u16 driver_strength; + u16 power_limit; +} sd_func_modes_t; + int sdmmc_storage_end(sdmmc_storage_t *storage); int sdmmc_storage_read(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, void *buf); int sdmmc_storage_write(sdmmc_storage_t *storage, u32 sector, u32 num_sectors, void *buf); @@ -209,7 +230,15 @@ int sdmmc_storage_init_gc(sdmmc_storage_t *storage, sdmmc_t *sdmmc); int sdmmc_storage_execute_vendor_cmd(sdmmc_storage_t *storage, u32 arg); int sdmmc_storage_vendor_sandisk_report(sdmmc_storage_t *storage, void *buf); +int mmc_storage_get_ext_csd(sdmmc_storage_t *storage, void *buf); + +int sd_storage_get_ext_reg(sdmmc_storage_t *storage, u8 fno, u8 page, u16 offset, u32 len, void *buf); +int sd_storage_get_fmodes(sdmmc_storage_t *storage, u8 *buf, sd_func_modes_t *functions); +int sd_storage_get_scr(sdmmc_storage_t *storage, u8 *buf); int sd_storage_get_ssr(sdmmc_storage_t *storage, u8 *buf); u32 sd_storage_get_ssr_au(sdmmc_storage_t *storage); +void sd_storage_get_ext_regs(sdmmc_storage_t *storage, u8 *buf); +int sd_storage_parse_perf_enhance(sdmmc_storage_t *storage, u8 fno, u8 page, u16 offset, u8 *buf); + #endif diff --git a/bdk/storage/sdmmc_driver.c b/bdk/storage/sdmmc_driver.c index 4e4ebc9..b6e3c8e 100644 --- a/bdk/storage/sdmmc_driver.c +++ b/bdk/storage/sdmmc_driver.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2025 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -27,25 +27,19 @@ #include #include #include +#include #include -#include //#define DPRINTF(...) gfx_printf(__VA_ARGS__) //#define ERROR_EXTRA_PRINTING #define DPRINTF(...) -#ifdef NYX +#ifdef BDK_SDMMC_EXTRA_PRINT #define ERROR_EXTRA_PRINTING -#define SDMMC_EMMC_OC #endif /*! SCMMC controller base addresses. */ -static const u32 _sdmmc_bases[4] = { - 0x700B0000, - 0x700B0200, - 0x700B0400, - 0x700B0600, -}; +static const u16 _sdmmc_base_offsets[4] = { 0x0, 0x200, 0x400, 0x600 }; int sdmmc_get_io_power(sdmmc_t *sdmmc) { @@ -88,9 +82,9 @@ static int _sdmmc_set_io_power(sdmmc_t *sdmmc, u32 power) u32 sdmmc_get_bus_width(sdmmc_t *sdmmc) { u32 h = sdmmc->regs->hostctl; - if (h & SDHCI_CTRL_8BITBUS) + if (h & SDHCI_CTRL_8BITBUS) // eMMC only (or UHS-II). return SDMMC_BUS_WIDTH_8; - if (h & SDHCI_CTRL_4BITBUS) + if (h & SDHCI_CTRL_4BITBUS) // SD only. return SDMMC_BUS_WIDTH_4; return SDMMC_BUS_WIDTH_1; } @@ -102,28 +96,28 @@ void sdmmc_set_bus_width(sdmmc_t *sdmmc, u32 bus_width) if (bus_width == SDMMC_BUS_WIDTH_1) sdmmc->regs->hostctl = host_control; else if (bus_width == SDMMC_BUS_WIDTH_4) - sdmmc->regs->hostctl = host_control | SDHCI_CTRL_4BITBUS; + sdmmc->regs->hostctl = host_control | SDHCI_CTRL_4BITBUS; // SD only. else if (bus_width == SDMMC_BUS_WIDTH_8) - sdmmc->regs->hostctl = host_control | SDHCI_CTRL_8BITBUS; + sdmmc->regs->hostctl = host_control | SDHCI_CTRL_8BITBUS; // eMMC only (or UHS-II). } void sdmmc_save_tap_value(sdmmc_t *sdmmc) { - sdmmc->venclkctl_tap = sdmmc->regs->venclkctl >> 16; + sdmmc->venclkctl_tap = (sdmmc->regs->venclkctl & 0xFF0000) >> 16; sdmmc->venclkctl_set = 1; } static int _sdmmc_config_tap_val(sdmmc_t *sdmmc, u32 type) { - const u32 dqs_trim_val = 0x28; - const u32 tap_values_t210[] = { 4, 0, 3, 0 }; + static const u32 dqs_trim_val = 40; // 24 if HS533/HS667. + static const u8 tap_values_t210[4] = { 4, 0, 3, 0 }; u32 tap_val = 0; if (type == SDHCI_TIMING_MMC_HS400) sdmmc->regs->vencapover = (sdmmc->regs->vencapover & 0xFFFFC0FF) | (dqs_trim_val << 8); - sdmmc->regs->ventunctl0 &= ~TEGRA_MMC_VNDR_TUN_CTRL0_TAP_VAL_UPDATED_BY_HW; + sdmmc->regs->ventunctl0 &= ~SDHCI_TEGRA_TUNING_TAP_HW_UPDATED; if (type == SDHCI_TIMING_MMC_HS400) { @@ -140,9 +134,9 @@ static int _sdmmc_config_tap_val(sdmmc_t *sdmmc, u32 type) return 1; } -static int _sdmmc_commit_changes(sdmmc_t *sdmmc) +static void _sdmmc_commit_changes(sdmmc_t *sdmmc) { - return sdmmc->regs->clkcon; + (void)sdmmc->regs->clkcon; } static void _sdmmc_pad_config_fallback(sdmmc_t *sdmmc, u32 power) @@ -173,8 +167,8 @@ static void _sdmmc_pad_config_fallback(sdmmc_t *sdmmc, u32 power) break; case SDMMC_4: // 50 Ohm 2X Driver. PU:16, PD:16, B01: PU:10, PD:10. - APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) = - (APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) & 0xFFFFC003) | (sdmmc->t210b01 ? 0xA28 : 0x1040); + APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) = (APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) & 0xFFFFC003) | + (sdmmc->t210b01 ? 0xA28 : 0x1040); (void)APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL); // Commit write. break; } @@ -189,21 +183,21 @@ static void _sdmmc_autocal_execute(sdmmc_t *sdmmc, u32 power) sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN; } - // Enable E_INPUT power. - if (!(sdmmc->regs->sdmemcmppadctl & TEGRA_MMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_PWRD)) + // Enable E_INPUT (SD) or Disable E_PWRD (eMMC) power. + if (!(sdmmc->regs->sdmemcmppadctl & SDHCI_TEGRA_PADCTRL_E_INPUT_PWRD)) { - sdmmc->regs->sdmemcmppadctl |= TEGRA_MMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_PWRD; + sdmmc->regs->sdmemcmppadctl |= SDHCI_TEGRA_PADCTRL_E_INPUT_PWRD; _sdmmc_commit_changes(sdmmc); usleep(1); } // Enable auto calibration and start auto configuration. - sdmmc->regs->autocalcfg |= TEGRA_MMC_AUTOCALCFG_AUTO_CAL_ENABLE | TEGRA_MMC_AUTOCALCFG_AUTO_CAL_START; + sdmmc->regs->autocalcfg |= SDHCI_TEGRA_AUTOCAL_ENABLE | SDHCI_TEGRA_AUTOCAL_START; _sdmmc_commit_changes(sdmmc); usleep(2); u32 timeout = get_tmr_ms() + 10; - while (sdmmc->regs->autocalsts & TEGRA_MMC_AUTOCALSTS_AUTO_CAL_ACTIVE) + while (sdmmc->regs->autocalsts & SDHCI_TEGRA_AUTOCAL_ACTIVE) { if (get_tmr_ms() > timeout) { @@ -215,33 +209,32 @@ static void _sdmmc_autocal_execute(sdmmc_t *sdmmc, u32 power) #ifdef ERROR_EXTRA_PRINTING // Check if Comp pad is open or short to ground. // SDMMC1: CZ pads - T210/T210B01: 7-bit/5-bit. SDMMC2/4: LV_CZ pads - 5-bit. - u8 code_mask = (sdmmc->t210b01 || sdmmc->id != SDMMC_1) ? 0x1F : 0x7F; - u8 autocal_pu_status = sdmmc->regs->autocalsts & code_mask; + // Use 0x1F mask for all. + u8 autocal_pu_status = sdmmc->regs->autocalsts & 0x1F; if (!autocal_pu_status) - EPRINTF("SDMMC: Comp Pad short to gnd!"); - else if (autocal_pu_status == code_mask) - EPRINTF("SDMMC: Comp Pad open!"); + EPRINTFARGS("SDMMC%d: Comp Pad open!", sdmmc->id + 1); // Or resistance is extreme. + else if (autocal_pu_status == 0x1F) + EPRINTFARGS("SDMMC%d: Comp Pad short to gnd!", sdmmc->id + 1); #endif // In case auto calibration fails, we load suggested standard values. if (!timeout) { + sdmmc->regs->autocalcfg &= ~SDHCI_TEGRA_AUTOCAL_ENABLE; _sdmmc_pad_config_fallback(sdmmc, power); - sdmmc->regs->autocalcfg &= ~TEGRA_MMC_AUTOCALCFG_AUTO_CAL_ENABLE; +#ifdef ERROR_EXTRA_PRINTING + EPRINTFARGS("SDMMC%d: Comp Pad cal timeout!", sdmmc->id + 1); +#endif } - // Disable E_INPUT to conserve power. - sdmmc->regs->sdmemcmppadctl &= ~TEGRA_MMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_PWRD; + // Disable E_INPUT (SD) or enable E_PWRD (eMMC) to conserve power. + sdmmc->regs->sdmemcmppadctl &= ~SDHCI_TEGRA_PADCTRL_E_INPUT_PWRD; - if(should_enable_sd_clock) + if (should_enable_sd_clock) sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN; } -#ifdef SDMMC_EMMC_OC -static int _sdmmc_dll_cal_execute(sdmmc_t *sdmmc, bool overclock) -#else static int _sdmmc_dll_cal_execute(sdmmc_t *sdmmc) -#endif { int result = 1, should_disable_sd_clock = 0; @@ -251,17 +244,15 @@ static int _sdmmc_dll_cal_execute(sdmmc_t *sdmmc) sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN; } -#ifdef SDMMC_EMMC_OC - // Add -4 TX_DLY_CODE_OFFSET if HS533. - if (sdmmc->id == SDMMC_4 && overclock) - sdmmc->regs->vendllcalcfg = sdmmc->regs->vendllcalcfg &= 0xFFFFC07F | (0x7C << 7); -#endif + // Add -4 TX_DLY_CODE_OFFSET if HS533/HS667. + // if (sdmmc->id == SDMMC_4 && sdmmc->card_clock > 208000) + // sdmmc->regs->vendllctl0 = sdmmc->regs->vendllctl0 &= 0xFFFFC07F | (0x7C << 7); - sdmmc->regs->vendllcalcfg |= TEGRA_MMC_DLLCAL_CFG_EN_CALIBRATE; + sdmmc->regs->vendllcalcfg |= SDHCI_TEGRA_DLLCAL_CALIBRATE; _sdmmc_commit_changes(sdmmc); u32 timeout = get_tmr_ms() + 5; - while (sdmmc->regs->vendllcalcfg & TEGRA_MMC_DLLCAL_CFG_EN_CALIBRATE) + while (sdmmc->regs->vendllcalcfg & SDHCI_TEGRA_DLLCAL_CALIBRATE) { if (get_tmr_ms() > timeout) { @@ -271,7 +262,7 @@ static int _sdmmc_dll_cal_execute(sdmmc_t *sdmmc) } timeout = get_tmr_ms() + 10; - while (sdmmc->regs->vendllcalcfgsts & TEGRA_MMC_DLLCAL_CFG_STATUS_DLL_ACTIVE) + while (sdmmc->regs->vendllcalcfgsts & SDHCI_TEGRA_DLLCAL_ACTIVE) { if (get_tmr_ms() > timeout) { @@ -286,7 +277,7 @@ out:; return result; } -static void _sdmmc_reset(sdmmc_t *sdmmc) +static void _sdmmc_reset_cmd_data(sdmmc_t *sdmmc) { sdmmc->regs->swrst |= SDHCI_RESET_CMD | SDHCI_RESET_DATA; _sdmmc_commit_changes(sdmmc); @@ -304,6 +295,13 @@ static void _sdmmc_reset_all(sdmmc_t *sdmmc) ; } +void sdmmc_setup_drv_type(sdmmc_t *sdmmc, u32 type) +{ + sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_DRV_TYPE_MASK)) | SDHCI_CTRL_DRV_TYPE(type); + + _sdmmc_commit_changes(sdmmc); +} + int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type) { // Disable the SD clock if it was enabled, and reenable it later. @@ -316,7 +314,7 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type) _sdmmc_config_tap_val(sdmmc, type); - _sdmmc_reset(sdmmc); + _sdmmc_reset_cmd_data(sdmmc); switch (type) { @@ -335,28 +333,35 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type) break; case SDHCI_TIMING_MMC_HS200: - case SDHCI_TIMING_UHS_SDR50: // T210 Errata for SDR50, the host must be set to SDR104. + case SDHCI_TIMING_UHS_SDR50: // T210 Errata: the host must be set to SDR104 to WAR a CRC issue. case SDHCI_TIMING_UHS_SDR104: case SDHCI_TIMING_UHS_SDR82: - case SDHCI_TIMING_UHS_DDR50: - case SDHCI_TIMING_MMC_HS102: - sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | UHS_SDR104_BUS_SPEED; + case SDHCI_TIMING_MMC_HS100: + sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_SDR104_BUS_SPEED; sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180; break; case SDHCI_TIMING_MMC_HS400: // Non standard. - sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | HS400_BUS_SPEED; + sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | HS400_BUS_SPEED; sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180; break; case SDHCI_TIMING_UHS_SDR25: - sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | UHS_SDR25_BUS_SPEED; + sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_SDR25_BUS_SPEED; sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180; break; case SDHCI_TIMING_UHS_SDR12: - sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & SDHCI_CTRL_UHS_MASK) | UHS_SDR12_BUS_SPEED; + sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_SDR12_BUS_SPEED; + sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180; + break; + + case SDHCI_TIMING_UHS_DDR50: +#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT + case SDHCI_TIMING_UHS_DDR200: +#endif + sdmmc->regs->hostctl2 = (sdmmc->regs->hostctl2 & (~SDHCI_CTRL_UHS_MASK)) | UHS_DDR50_BUS_SPEED; sdmmc->regs->hostctl2 |= SDHCI_CTRL_VDD_180; break; } @@ -367,39 +372,30 @@ int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type) u16 divisor; clock_sdmmc_get_card_clock_div(&clock, &divisor, type); clock_sdmmc_config_clock_source(&clock, sdmmc->id, clock); - sdmmc->divisor = (clock + divisor - 1) / divisor; + sdmmc->card_clock = (clock + divisor - 1) / divisor; - //if divisor != 1 && divisor << 31 -> error + // (divisor != 1) && (divisor & 1) -> error - u16 div = divisor >> 1; - divisor = 0; - if (div > 0xFF) - divisor = div >> SDHCI_DIVIDER_SHIFT; + u16 div_lo = divisor >> 1; + u16 div_hi = div_lo >> 8; - sdmmc->regs->clkcon = (sdmmc->regs->clkcon & ~(SDHCI_DIV_MASK | SDHCI_DIV_HI_MASK)) - | (div << SDHCI_DIVIDER_SHIFT) | (divisor << SDHCI_DIVIDER_HI_SHIFT); + sdmmc->regs->clkcon = (sdmmc->regs->clkcon & ~(SDHCI_DIV_MASK | SDHCI_DIV_HI_MASK)) | + (div_lo << SDHCI_DIV_LO_SHIFT) | (div_hi << SDHCI_DIV_HI_SHIFT); // Enable the SD clock again. if (should_enable_sd_clock) sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN; if (type == SDHCI_TIMING_MMC_HS400) - { -#ifdef SDMMC_EMMC_OC - bool overclock_en = clock > 208000; - return _sdmmc_dll_cal_execute(sdmmc, overclock_en); -#else return _sdmmc_dll_cal_execute(sdmmc); -#endif - } return 1; } static void _sdmmc_card_clock_enable(sdmmc_t *sdmmc) { - // Recalibrate conditionally. - if (sdmmc->manual_cal && !sdmmc->powersave_enabled) + // Recalibrate periodically if needed. + if (sdmmc->periodic_calibration && !sdmmc->powersave_enabled) _sdmmc_autocal_execute(sdmmc, sdmmc_get_io_power(sdmmc)); if (!sdmmc->powersave_enabled) @@ -410,7 +406,7 @@ static void _sdmmc_card_clock_enable(sdmmc_t *sdmmc) sdmmc->card_clock_enabled = 1; } -static void _sdmmc_sd_clock_disable(sdmmc_t *sdmmc) +static void _sdmmc_card_clock_disable(sdmmc_t *sdmmc) { sdmmc->card_clock_enabled = 0; sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN; @@ -418,8 +414,8 @@ static void _sdmmc_sd_clock_disable(sdmmc_t *sdmmc) void sdmmc_card_clock_powersave(sdmmc_t *sdmmc, int powersave_enable) { - // Recalibrate periodically for SDMMC1. - if (sdmmc->manual_cal && !powersave_enable && sdmmc->card_clock_enabled) + // Recalibrate periodically if needed. + if (sdmmc->periodic_calibration && !powersave_enable && sdmmc->card_clock_enabled) _sdmmc_autocal_execute(sdmmc, sdmmc_get_io_power(sdmmc)); sdmmc->powersave_enabled = powersave_enable; @@ -435,7 +431,7 @@ void sdmmc_card_clock_powersave(sdmmc_t *sdmmc, int powersave_enable) sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN; } -static int _sdmmc_cache_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 size, u32 type) +static int _sdmmc_cache_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 type) { switch (type) { @@ -443,33 +439,14 @@ static int _sdmmc_cache_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 size, u32 type) case SDMMC_RSP_TYPE_3: case SDMMC_RSP_TYPE_4: case SDMMC_RSP_TYPE_5: - if (size < 4) - return 0; - rsp[0] = sdmmc->regs->rspreg0; + rsp[0] = sdmmc->regs->rspreg[0]; break; case SDMMC_RSP_TYPE_2: - if (size < 0x10) - return 0; // CRC is stripped, so shifting is needed. - u32 tempreg; - for (int i = 0; i < 4; i++) + for (u32 i = 0; i < 4; i++) { - switch(i) - { - case 0: - tempreg = sdmmc->regs->rspreg3; - break; - case 1: - tempreg = sdmmc->regs->rspreg2; - break; - case 2: - tempreg = sdmmc->regs->rspreg1; - break; - case 3: - tempreg = sdmmc->regs->rspreg0; - break; - } + u32 tempreg = sdmmc->regs->rspreg[3 - i]; rsp[i] = tempreg << 8; if (i != 0) @@ -484,7 +461,7 @@ static int _sdmmc_cache_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 size, u32 type) return 1; } -int sdmmc_get_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 size, u32 type) +int sdmmc_get_cached_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 type) { if (!rsp || sdmmc->expected_rsp_type != type) return 0; @@ -495,18 +472,12 @@ int sdmmc_get_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 size, u32 type) case SDMMC_RSP_TYPE_3: case SDMMC_RSP_TYPE_4: case SDMMC_RSP_TYPE_5: - if (size < 4) - return 0; rsp[0] = sdmmc->rsp[0]; break; case SDMMC_RSP_TYPE_2: - if (size < 16) - return 0; - rsp[0] = sdmmc->rsp[0]; - rsp[1] = sdmmc->rsp[1]; - rsp[2] = sdmmc->rsp[2]; - rsp[3] = sdmmc->rsp[3]; + for (u32 i = 0; i < 4; i++) + rsp[i] = sdmmc->rsp[i]; break; default: @@ -521,10 +492,10 @@ static int _sdmmc_wait_cmd_data_inhibit(sdmmc_t *sdmmc, bool wait_dat) _sdmmc_commit_changes(sdmmc); u32 timeout = get_tmr_ms() + 2000; - while(sdmmc->regs->prnsts & SDHCI_CMD_INHIBIT) + while (sdmmc->regs->prnsts & SDHCI_CMD_INHIBIT) if (get_tmr_ms() > timeout) { - _sdmmc_reset(sdmmc); + _sdmmc_reset_cmd_data(sdmmc); return 0; } @@ -534,7 +505,7 @@ static int _sdmmc_wait_cmd_data_inhibit(sdmmc_t *sdmmc, bool wait_dat) while (sdmmc->regs->prnsts & SDHCI_DATA_INHIBIT) if (get_tmr_ms() > timeout) { - _sdmmc_reset(sdmmc); + _sdmmc_reset_cmd_data(sdmmc); return 0; } } @@ -547,10 +518,10 @@ static int _sdmmc_wait_card_busy(sdmmc_t *sdmmc) _sdmmc_commit_changes(sdmmc); u32 timeout = get_tmr_ms() + 2000; - while (!(sdmmc->regs->prnsts & SDHCI_DATA_0_LVL_MASK)) + while (!(sdmmc->regs->prnsts & SDHCI_DATA_0_LVL)) if (get_tmr_ms() > timeout) { - _sdmmc_reset(sdmmc); + _sdmmc_reset_cmd_data(sdmmc); return 0; } @@ -579,7 +550,7 @@ static int _sdmmc_setup_read_small_block(sdmmc_t *sdmmc) return 1; } -static int _sdmmc_send_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, bool is_data_present) +static int _sdmmc_send_cmd(sdmmc_t *sdmmc, const sdmmc_cmd_t *cmd, bool is_data_present) { u16 cmdflags = 0; @@ -594,7 +565,7 @@ static int _sdmmc_send_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, bool is_data_presen if (cmd->check_busy) cmdflags = SDHCI_CMD_RESP_LEN48_BUSY | SDHCI_CMD_INDEX | SDHCI_CMD_CRC; else - cmdflags = SDHCI_CMD_RESP_LEN48 | SDHCI_CMD_INDEX | SDHCI_CMD_CRC; + cmdflags = SDHCI_CMD_RESP_LEN48 | SDHCI_CMD_INDEX | SDHCI_CMD_CRC; break; case SDMMC_RSP_TYPE_2: @@ -611,8 +582,9 @@ static int _sdmmc_send_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, bool is_data_presen if (is_data_present) cmdflags |= SDHCI_CMD_DATA; + sdmmc->regs->argument = cmd->arg; - sdmmc->regs->cmdreg = (cmd->cmd << 8) | cmdflags; + sdmmc->regs->cmdreg = SDHCI_CMD_IDX(cmd->cmd) | cmdflags; return 1; } @@ -627,10 +599,8 @@ static void _sdmmc_send_tuning_cmd(sdmmc_t *sdmmc, u32 cmd) _sdmmc_send_cmd(sdmmc, &cmdbuf, true); } -static int _sdmmc_tuning_execute_once(sdmmc_t *sdmmc, u32 cmd) +static int _sdmmc_tuning_execute_once(sdmmc_t *sdmmc, u32 cmd, u32 tap) { - if (sdmmc->powersave_enabled) - return 0; if (!_sdmmc_wait_cmd_data_inhibit(sdmmc, true)) return 0; @@ -640,11 +610,21 @@ static int _sdmmc_tuning_execute_once(sdmmc_t *sdmmc, u32 cmd) sdmmc->regs->norintsts = sdmmc->regs->norintsts; sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN; +#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT + // Set tap if manual tuning. + if (tap != HW_TAP_TUNING) + { + sdmmc->regs->ventunctl0 &= ~SDHCI_TEGRA_TUNING_TAP_HW_UPDATED; + sdmmc->regs->venclkctl = (sdmmc->regs->venclkctl & 0xFF00FFFF) | (tap << 16); + sdmmc->regs->ventunctl0 |= SDHCI_TEGRA_TUNING_TAP_HW_UPDATED; + } +#endif + _sdmmc_send_tuning_cmd(sdmmc, cmd); _sdmmc_commit_changes(sdmmc); usleep(1); - _sdmmc_reset(sdmmc); + _sdmmc_reset_cmd_data(sdmmc); sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN; _sdmmc_commit_changes(sdmmc); @@ -657,59 +637,170 @@ static int _sdmmc_tuning_execute_once(sdmmc_t *sdmmc, u32 cmd) sdmmc->regs->norintsts = SDHCI_INT_DATA_AVAIL; sdmmc->regs->norintstsen &= ~SDHCI_INT_DATA_AVAIL; _sdmmc_commit_changes(sdmmc); - usleep((1000 * 8 + sdmmc->divisor - 1) / sdmmc->divisor); + usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles. return 1; } } - _sdmmc_reset(sdmmc); + _sdmmc_reset_cmd_data(sdmmc); sdmmc->regs->norintstsen &= ~SDHCI_INT_DATA_AVAIL; _sdmmc_commit_changes(sdmmc); - usleep((1000 * 8 + sdmmc->divisor - 1) / sdmmc->divisor); + usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles. return 0; } +#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT +typedef struct _sdmmc_manual_tuning_t +{ + u32 result[8]; + u32 num_iter; + u32 tap_start; + u32 tap_end; +} sdmmc_manual_tuning_t; + +static int _sdmmc_manual_tuning_set_tap(sdmmc_t *sdmmc, sdmmc_manual_tuning_t *tuning) +{ + u32 tap_start = INVALID_TAP; + u32 win_size = 0; + u32 best_tap = 0; + u32 best_size = 0; + + for (u32 i = 0; i < tuning->num_iter; i++) + { + u32 iter_end = i == (tuning->num_iter - 1) ? 1 : 0; + u32 stable = tuning->result[i / 32] & BIT(i % 32); + if (stable && !iter_end) + { + if (tap_start == INVALID_TAP) + tap_start = i; + + win_size++; + } + else + { + if (tap_start != INVALID_TAP) + { + u32 tap_end = !iter_end ? (i - 1) : i; + + // Check if window is wider. + if (win_size > best_size) + { + best_tap = (tap_start + tap_end) / 2; + best_size = win_size + iter_end; + } + + tap_start = INVALID_TAP; + win_size = 0; + } + } + } + + + // Check if failed or window too small. + if (!best_tap || best_size < SAMPLING_WINDOW_SIZE_MIN) + return 0; + + sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN; + sdmmc->regs->ventunctl0 &= ~SDHCI_TEGRA_TUNING_TAP_HW_UPDATED; + + // Set tap. + sdmmc->regs->venclkctl = (sdmmc->regs->venclkctl & 0xFF00FFFF) | (best_tap << 16); + + sdmmc->regs->ventunctl0 |= SDHCI_TEGRA_TUNING_TAP_HW_UPDATED; + sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN; + + return 1; +} + +/* + * SD Card DDR200 (DDR208) support + * + * On Tegra X1, that can be done with DDR50 host mode. + * That's because HS400 4-bit or HS400 generally, is not supported on SDMMC1/3. + * And also, tuning can't be done automatically on any DDR mode. + * So it needs to be done manually and selected tap will be applied from the biggest + * sampling window. + * That allows DDR200 support on every DDR200 sd card, other than the original maker + * of DDR200, Sandisk. Since Sandisk cards mandate DLL syncing. + */ +static int sdmmc_tuning_execute_ddr200(sdmmc_t *sdmmc) +{ + sdmmc_manual_tuning_t manual_tuning = { 0 }; + manual_tuning.num_iter = 128; + + sdmmc->regs->ventunctl1 = 0; // step_size 1. + sdmmc->regs->ventunctl0 = (sdmmc->regs->ventunctl0 & 0xFFFF1FFF) | (2 << 13); // 128 Tries. + sdmmc->regs->ventunctl0 = (sdmmc->regs->ventunctl0 & 0xFFFFE03F) | (1 << 6); // 1x Multiplier. + sdmmc->regs->ventunctl0 |= SDHCI_TEGRA_TUNING_TAP_HW_UPDATED; + + sdmmc->regs->hostctl2 |= SDHCI_CTRL_EXEC_TUNING; + + for (u32 i = 0; i < manual_tuning.num_iter; i++) + { + _sdmmc_tuning_execute_once(sdmmc, MMC_SEND_TUNING_BLOCK, i); + + // Save result for manual tuning. + int sampled = (sdmmc->regs->hostctl2 >> SDHCI_CTRL_TUNED_CLK_SHIFT) & 1; + manual_tuning.result[i / 32] |= sampled << (i % 32); + + if (!(sdmmc->regs->hostctl2 & SDHCI_CTRL_EXEC_TUNING)) + break; + } + + return _sdmmc_manual_tuning_set_tap(sdmmc, &manual_tuning); +} +#endif + int sdmmc_tuning_execute(sdmmc_t *sdmmc, u32 type, u32 cmd) { - u32 max = 0, flag = 0; + u32 num_iter, flag; + + if (sdmmc->powersave_enabled) + return 0; switch (type) { case SDHCI_TIMING_MMC_HS200: - case SDHCI_TIMING_MMC_HS400: case SDHCI_TIMING_UHS_SDR104: case SDHCI_TIMING_UHS_SDR82: - max = 128; + num_iter = 128; flag = (2 << 13); // 128 iterations. break; case SDHCI_TIMING_UHS_SDR50: - case SDHCI_TIMING_UHS_DDR50: - case SDHCI_TIMING_MMC_HS102: - max = 256; + case SDHCI_TIMING_UHS_DDR50: // HW tuning is not supported on DDR modes. But it sets tap to 0 which is proper. + case SDHCI_TIMING_MMC_HS100: + num_iter = 256; flag = (4 << 13); // 256 iterations. break; + case SDHCI_TIMING_MMC_HS400: case SDHCI_TIMING_UHS_SDR12: case SDHCI_TIMING_UHS_SDR25: return 1; +#ifdef BDK_SDMMC_UHS_DDR200_SUPPORT + case SDHCI_TIMING_UHS_DDR200: + return sdmmc_tuning_execute_ddr200(sdmmc); +#endif + default: return 0; } - sdmmc->regs->ventunctl1 = 0; // step_size 1. + sdmmc->regs->ventunctl1 = 0; // step_size 1. + sdmmc->regs->ventunctl0 = (sdmmc->regs->ventunctl0 & 0xFFFF1FFF) | flag; // Tries. + sdmmc->regs->ventunctl0 = (sdmmc->regs->ventunctl0 & 0xFFFFE03F) | (1 << 6); // 1x Multiplier. + sdmmc->regs->ventunctl0 |= SDHCI_TEGRA_TUNING_TAP_HW_UPDATED; - sdmmc->regs->ventunctl0 = (sdmmc->regs->ventunctl0 & 0xFFFF1FFF) | flag; // Tries. - sdmmc->regs->ventunctl0 = (sdmmc->regs->ventunctl0 & 0xFFFFE03F) | (1 << 6); // 1x Multiplier. - sdmmc->regs->ventunctl0 |= TEGRA_MMC_VNDR_TUN_CTRL0_TAP_VAL_UPDATED_BY_HW; sdmmc->regs->hostctl2 |= SDHCI_CTRL_EXEC_TUNING; - for (u32 i = 0; i < max; i++) + for (u32 i = 0; i < num_iter; i++) { - _sdmmc_tuning_execute_once(sdmmc, cmd); + _sdmmc_tuning_execute_once(sdmmc, cmd, HW_TAP_TUNING); + if (!(sdmmc->regs->hostctl2 & SDHCI_CTRL_EXEC_TUNING)) break; } @@ -734,14 +825,15 @@ static int _sdmmc_enable_internal_clock(sdmmc_t *sdmmc) sdmmc->regs->hostctl2 &= ~SDHCI_CTRL_PRESET_VAL_EN; sdmmc->regs->clkcon &= ~SDHCI_PROG_CLOCK_MODE; + // Enable 32/64bit addressing if used (sysad. if blkcnt it fallbacks to 16bit). sdmmc->regs->hostctl2 |= SDHCI_HOST_VERSION_4_EN; - if (!(sdmmc->regs->capareg & SDHCI_CAN_64BIT)) + if (!(sdmmc->regs->capareg & SDHCI_CAP_64BIT)) return 0; - sdmmc->regs->hostctl2 |= SDHCI_ADDRESSING_64BIT_EN; - sdmmc->regs->hostctl &= ~SDHCI_CTRL_DMA_MASK; - sdmmc->regs->timeoutcon = (sdmmc->regs->timeoutcon & 0xF0) | 0xE; + sdmmc->regs->hostctl2 |= SDHCI_ADDRESSING_64BIT_EN; + sdmmc->regs->hostctl &= ~SDHCI_CTRL_DMA_MASK; // Use SDMA. Host V4 enabled so adma address regs in use. + sdmmc->regs->timeoutcon = (sdmmc->regs->timeoutcon & 0xF0) | 14; // TMCLK * 2^27. return 1; } @@ -766,8 +858,8 @@ static int _sdmmc_autocal_config_offset(sdmmc_t *sdmmc, u32 power) { if (!sdmmc->t210b01) { - off_pd = 123; - off_pu = 123; + off_pd = 0x7B; // -5. + off_pu = 0x7B; // -5. } else { @@ -779,7 +871,7 @@ static int _sdmmc_autocal_config_offset(sdmmc_t *sdmmc, u32 power) { if (!sdmmc->t210b01) { - off_pd = 125; + off_pd = 0x7D; // -3. off_pu = 0; } } @@ -798,6 +890,7 @@ static void _sdmmc_enable_interrupts(sdmmc_t *sdmmc) sdmmc->regs->errintstsen |= SDHCI_ERR_INT_ALL_EXCEPT_ADMA_BUSPWR; sdmmc->regs->norintsts = sdmmc->regs->norintsts; sdmmc->regs->errintsts = sdmmc->regs->errintsts; + sdmmc->error_sts = 0; } static void _sdmmc_mask_interrupts(sdmmc_t *sdmmc) @@ -806,12 +899,12 @@ static void _sdmmc_mask_interrupts(sdmmc_t *sdmmc) sdmmc->regs->norintstsen &= ~(SDHCI_INT_DMA_END | SDHCI_INT_DATA_END | SDHCI_INT_RESPONSE); } -static int _sdmmc_check_mask_interrupt(sdmmc_t *sdmmc, u16 *pout, u16 mask) +static u32 _sdmmc_check_mask_interrupt(sdmmc_t *sdmmc, u16 *pout, u16 mask) { u16 norintsts = sdmmc->regs->norintsts; u16 errintsts = sdmmc->regs->errintsts; -DPRINTF("norintsts %08X, errintsts %08X\n", norintsts, errintsts); + DPRINTF("norintsts %08X, errintsts %08X\n", norintsts, errintsts); if (pout) *pout = norintsts; @@ -820,8 +913,9 @@ DPRINTF("norintsts %08X, errintsts %08X\n", norintsts, errintsts); if (norintsts & SDHCI_INT_ERROR) { #ifdef ERROR_EXTRA_PRINTING - EPRINTFARGS("SDMMC: norintsts %08X, errintsts %08X\n", norintsts, errintsts); + EPRINTFARGS("SDMMC%d: intsts %08X, errintsts %08X", sdmmc->id + 1, norintsts, errintsts); #endif + sdmmc->error_sts = errintsts; sdmmc->regs->errintsts = errintsts; return SDMMC_MASKINT_ERROR; } @@ -841,12 +935,12 @@ static int _sdmmc_wait_response(sdmmc_t *sdmmc) u32 timeout = get_tmr_ms() + 2000; while (true) { - int result = _sdmmc_check_mask_interrupt(sdmmc, NULL, SDHCI_INT_RESPONSE); + u32 result = _sdmmc_check_mask_interrupt(sdmmc, NULL, SDHCI_INT_RESPONSE); if (result == SDMMC_MASKINT_MASKED) break; if (result != SDMMC_MASKINT_NOERROR || get_tmr_ms() > timeout) { - _sdmmc_reset(sdmmc); + _sdmmc_reset_cmd_data(sdmmc); return 0; } } @@ -876,7 +970,7 @@ static int _sdmmc_stop_transmission_inner(sdmmc_t *sdmmc, u32 *rsp) if (!result) return 0; - _sdmmc_cache_rsp(sdmmc, rsp, 4, SDMMC_RSP_TYPE_1); + _sdmmc_cache_rsp(sdmmc, rsp, SDMMC_RSP_TYPE_1); return _sdmmc_wait_card_busy(sdmmc); } @@ -886,8 +980,8 @@ int sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp) if (!sdmmc->card_clock_enabled) return 0; - // Recalibrate periodically for SDMMC1. - if (sdmmc->manual_cal && sdmmc->powersave_enabled) + // Recalibrate periodically if needed. + if (sdmmc->periodic_calibration && sdmmc->powersave_enabled) _sdmmc_autocal_execute(sdmmc, sdmmc_get_io_power(sdmmc)); bool should_disable_sd_clock = false; @@ -896,11 +990,11 @@ int sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp) should_disable_sd_clock = true; sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN; _sdmmc_commit_changes(sdmmc); - usleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor); + usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles. } int result = _sdmmc_stop_transmission_inner(sdmmc, rsp); - usleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor); + usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles. if (should_disable_sd_clock) sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN; @@ -908,7 +1002,7 @@ int sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp) return result; } -static int _sdmmc_config_dma(sdmmc_t *sdmmc, u32 *blkcnt_out, sdmmc_req_t *req) +static int _sdmmc_config_sdma(sdmmc_t *sdmmc, u32 *blkcnt_out, const sdmmc_req_t *req) { if (!req->blksize || !req->num_sectors) return 0; @@ -925,19 +1019,19 @@ static int _sdmmc_config_dma(sdmmc_t *sdmmc, u32 *blkcnt_out, sdmmc_req_t *req) sdmmc->regs->admaaddr = admaaddr; sdmmc->regs->admaaddr_hi = 0; - sdmmc->dma_addr_next = (admaaddr + 0x80000) & 0xFFF80000; + sdmmc->dma_addr_next = ALIGN_DOWN((admaaddr + SZ_512K), SZ_512K); - sdmmc->regs->blksize = req->blksize | 0x7000; // DMA 512KB (Detects A18 carry out). - sdmmc->regs->blkcnt = blkcnt; + sdmmc->regs->blksize = req->blksize | (7u << 12); // SDMA DMA 512KB Boundary (Detects A18 carry out). + sdmmc->regs->blkcnt = blkcnt; if (blkcnt_out) *blkcnt_out = blkcnt; - u32 trnmode = SDHCI_TRNS_DMA; + u32 trnmode = SDHCI_TRNS_DMA | SDHCI_TRNS_RTYPE_R1; - // Set mulitblock request. + // Set multiblock request. if (req->is_multi_block) - trnmode = SDHCI_TRNS_MULTI | SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_DMA; + trnmode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_BLK_CNT_EN; // Set request direction. if (!req->is_write) @@ -954,7 +1048,7 @@ static int _sdmmc_config_dma(sdmmc_t *sdmmc, u32 *blkcnt_out, sdmmc_req_t *req) return 1; } -static int _sdmmc_update_dma(sdmmc_t *sdmmc) +static int _sdmmc_update_sdma(sdmmc_t *sdmmc) { u16 blkcnt = 0; do @@ -963,13 +1057,13 @@ static int _sdmmc_update_dma(sdmmc_t *sdmmc) u32 timeout = get_tmr_ms() + 1500; do { - int result = 0; + u32 result = SDMMC_MASKINT_MASKED; while (true) { u16 intr = 0; result = _sdmmc_check_mask_interrupt(sdmmc, &intr, SDHCI_INT_DATA_END | SDHCI_INT_DMA_END); - if (result < 0) + if (result != SDMMC_MASKINT_MASKED) break; if (intr & SDHCI_INT_DATA_END) @@ -980,27 +1074,30 @@ static int _sdmmc_update_dma(sdmmc_t *sdmmc) // Update DMA. sdmmc->regs->admaaddr = sdmmc->dma_addr_next; sdmmc->regs->admaaddr_hi = 0; - sdmmc->dma_addr_next += 0x80000; + sdmmc->dma_addr_next += SZ_512K; } } + if (result != SDMMC_MASKINT_NOERROR) { #ifdef ERROR_EXTRA_PRINTING - EPRINTFARGS("%08X!", result); + EPRINTFARGS("SDMMC%d: int error!", sdmmc->id + 1); #endif - _sdmmc_reset(sdmmc); + _sdmmc_reset_cmd_data(sdmmc); + return 0; } } while (get_tmr_ms() < timeout); } while (sdmmc->regs->blkcnt != blkcnt); - _sdmmc_reset(sdmmc); + _sdmmc_reset_cmd_data(sdmmc); + return 0; } static int _sdmmc_execute_cmd_inner(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *blkcnt_out) { - int has_req_or_check_busy = req || cmd->check_busy; + bool has_req_or_check_busy = req || cmd->check_busy; if (!_sdmmc_wait_cmd_data_inhibit(sdmmc, has_req_or_check_busy)) return 0; @@ -1008,16 +1105,16 @@ static int _sdmmc_execute_cmd_inner(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_ bool is_data_present = false; if (req) { - if (!_sdmmc_config_dma(sdmmc, &blkcnt, req)) + if (!_sdmmc_config_sdma(sdmmc, &blkcnt, req)) { #ifdef ERROR_EXTRA_PRINTING - EPRINTF("SDMMC: DMA Wrong cfg!"); + EPRINTFARGS("SDMMC%d: DMA Wrong cfg!", sdmmc->id + 1); #endif return 0; } // Flush cache before starting the transfer. - bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false); + bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLEAN_WAY, false); is_data_present = true; } @@ -1027,7 +1124,7 @@ static int _sdmmc_execute_cmd_inner(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_ if (!_sdmmc_send_cmd(sdmmc, cmd, is_data_present)) { #ifdef ERROR_EXTRA_PRINTING - EPRINTFARGS("SDMMC: Wrong Response type %08X!", cmd->rsp_type); + EPRINTFARGS("SDMMC%d: Wrong Response type %08X!", sdmmc->id + 1, cmd->rsp_type); #endif return 0; } @@ -1035,27 +1132,27 @@ static int _sdmmc_execute_cmd_inner(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_ int result = _sdmmc_wait_response(sdmmc); #ifdef ERROR_EXTRA_PRINTING if (!result) - EPRINTF("SDMMC: Transfer timeout!"); + EPRINTFARGS("SDMMC%d: Transfer error!", sdmmc->id + 1); #endif -DPRINTF("rsp(%d): %08X, %08X, %08X, %08X\n", result, - sdmmc->regs->rspreg0, sdmmc->regs->rspreg1, sdmmc->regs->rspreg2, sdmmc->regs->rspreg3); + DPRINTF("rsp(%d): %08X, %08X, %08X, %08X\n", result, + sdmmc->regs->rspreg[0], sdmmc->regs->rspreg[1], sdmmc->regs->rspreg[2], sdmmc->regs->rspreg[3]); if (result) { if (cmd->rsp_type) { sdmmc->expected_rsp_type = cmd->rsp_type; - result = _sdmmc_cache_rsp(sdmmc, sdmmc->rsp, 0x10, cmd->rsp_type); + result = _sdmmc_cache_rsp(sdmmc, sdmmc->rsp, cmd->rsp_type); #ifdef ERROR_EXTRA_PRINTING if (!result) - EPRINTF("SDMMC: Unknown response type!"); + EPRINTFARGS("SDMMC%d: Unknown response type!", sdmmc->id + 1); #endif } if (req && result) { - result = _sdmmc_update_dma(sdmmc); + result = _sdmmc_update_sdma(sdmmc); #ifdef ERROR_EXTRA_PRINTING if (!result) - EPRINTF("SDMMC: DMA Update failed!"); + EPRINTFARGS("SDMMC%d: DMA Update failed!", sdmmc->id + 1); #endif } } @@ -1066,22 +1163,22 @@ DPRINTF("rsp(%d): %08X, %08X, %08X, %08X\n", result, { if (req) { - // Flush cache after transfer. - bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false); + // Invalidate cache after transfer. + bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, false); if (blkcnt_out) *blkcnt_out = blkcnt; if (req->is_auto_stop_trn) - sdmmc->rsp3 = sdmmc->regs->rspreg3; + sdmmc->stop_trn_rsp = sdmmc->regs->rspreg[3]; } - if (cmd->check_busy || req) + if (has_req_or_check_busy) { result = _sdmmc_wait_card_busy(sdmmc); #ifdef ERROR_EXTRA_PRINTING if (!result) - EPRINTF("SDMMC: Busy timeout!"); + EPRINTFARGS("SDMMC%d: Busy timeout!", sdmmc->id + 1); #endif return result; } @@ -1128,7 +1225,7 @@ static void _sdmmc_config_sdmmc1_pads(bool discharge) u32 level = GPIO_LOW; u32 output = GPIO_OUTPUT_DISABLE; - // Set values for dicharging. + // Set values for discharging. if (discharge) { function = GPIO_MODE_GPIO; @@ -1149,27 +1246,18 @@ static int _sdmmc_config_sdmmc1(bool t210b01) // Configure SD card detect. PINMUX_AUX(PINMUX_AUX_GPIO_PZ1) = PINMUX_INPUT_ENABLE | PINMUX_PULL_UP | 2; // GPIO control, pull up. APB_MISC(APB_MISC_GP_VGPIO_GPIO_MUX_SEL) = 0; - gpio_config(GPIO_PORT_Z, GPIO_PIN_1, GPIO_MODE_GPIO); - gpio_output_enable(GPIO_PORT_Z, GPIO_PIN_1, GPIO_OUTPUT_DISABLE); + gpio_direction_input(GPIO_PORT_Z, GPIO_PIN_1); usleep(100); // Check if SD card is inserted. - if(!sdmmc_get_sd_inserted()) + if (!sdmmc_get_sd_inserted()) return 0; - /* - * Pinmux config: - * DRV_TYPE = DRIVE_2X (for 33 Ohm driver) - * E_SCHMT = ENABLE (for 1.8V), DISABLE (for 3.3V) - * E_INPUT = ENABLE - * TRISTATE = PASSTHROUGH - * APB_MISC_GP_SDMMCx_CLK_LPBK_CONTROL = SDMMCx_CLK_PAD_E_LPBK for CLK - */ - - // Enable deep loopback for SDMMC1 CLK pad. + // Enable deep loopback for SDMMC1 CLK pad so reads work. APB_MISC(APB_MISC_GP_SDMMC1_CLK_LPBK_CONTROL) = 1; // Configure SDMMC1 CLK pinmux, based on state and SoC type. + PINMUX_AUX(PINMUX_AUX_SDMMC1_CLK) &= ~PINMUX_SCHMT; if (PINMUX_AUX(PINMUX_AUX_SDMMC1_CLK) != (PINMUX_DRIVE_2X | PINMUX_INPUT_ENABLE | PINMUX_PULL_DOWN)) // Check if CLK pad is already configured. PINMUX_AUX(PINMUX_AUX_SDMMC1_CLK) = PINMUX_DRIVE_2X | PINMUX_INPUT_ENABLE | (t210b01 ? PINMUX_PULL_NONE : PINMUX_PULL_DOWN); @@ -1185,19 +1273,19 @@ static int _sdmmc_config_sdmmc1(bool t210b01) _sdmmc_config_sdmmc1_schmitt(); // Make sure the SDMMC1 controller is powered. - PMC(APBDEV_PMC_NO_IOPOWER) &= ~(PMC_NO_IOPOWER_SDMMC1_IO_EN); + PMC(APBDEV_PMC_NO_IOPOWER) |= PMC_NO_IOPOWER_SDMMC1; + usleep(1000); + PMC(APBDEV_PMC_NO_IOPOWER) &= ~PMC_NO_IOPOWER_SDMMC1; (void)PMC(APBDEV_PMC_NO_IOPOWER); // Commit write. - // Inform IO pads that voltage is gonna be 3.3V. - PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_SDMMC1_IO_EN; - (void)PMC(APBDEV_PMC_PWR_DET_VAL); // Commit write. + // Enable SD card power. Powers LDO2 also. + PINMUX_AUX(PINMUX_AUX_DMIC3_CLK) = PINMUX_PULL_DOWN | 2; + gpio_direction_output(GPIO_PORT_E, GPIO_PIN_4, GPIO_HIGH); + usleep(10000); // Minimum 3 to 10 ms. - // Set enable SD card power. - PINMUX_AUX(PINMUX_AUX_DMIC3_CLK) = PINMUX_PULL_DOWN | 2; // Pull down. - gpio_config(GPIO_PORT_E, GPIO_PIN_4, GPIO_MODE_GPIO); - gpio_write(GPIO_PORT_E, GPIO_PIN_4, GPIO_HIGH); - gpio_output_enable(GPIO_PORT_E, GPIO_PIN_4, GPIO_OUTPUT_ENABLE); - usleep(10000); + // Inform IO pads that voltage is gonna be 3.3V. + PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_33V_SDMMC1; + (void)PMC(APBDEV_PMC_PWR_DET_VAL); // Commit write. // Enable SD card IO power. max7762x_regulator_set_voltage(REGULATOR_LDO2, 3300000); @@ -1235,7 +1323,7 @@ static void _sdmmc_config_emmc(u32 id, bool t210b01) APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) &= 0xF8003FFF; // Set default pad cfg. if (t210b01) - APB_MISC(APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL) &= 0xFFBFFFF9; // Unset CMD/CLK/DQS powedown. + APB_MISC(APB_MISC_GP_EMMC4_PAD_PUPD_CFGPADCTRL) &= 0xFFBFFFF9; // Unset CMD/CLK/DQS weak pull up/down. // Enable schmitt trigger. APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL) |= 1; (void)APB_MISC(APB_MISC_GP_EMMC4_PAD_CFGPADCTRL); // Commit write. @@ -1243,26 +1331,28 @@ static void _sdmmc_config_emmc(u32 id, bool t210b01) } } -int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int powersave_enable) +int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type) { u32 clock; u16 divisor; u8 vref_sel = 7; - const u32 trim_values_t210[] = { 2, 8, 3, 8 }; - const u32 trim_values_t210b01[] = { 14, 13, 15, 13 }; - const u32 *trim_values = sdmmc->t210b01 ? trim_values_t210b01 : trim_values_t210; + static const u8 trim_values_t210[4] = { 2, 8, 3, 8 }; + static const u8 trim_values_t210b01[4] = { 14, 13, 15, 13 }; + const u8 *trim_values; if (id > SDMMC_4 || id == SDMMC_3) return 0; memset(sdmmc, 0, sizeof(sdmmc_t)); - sdmmc->regs = (t210_sdmmc_t *)_sdmmc_bases[id]; + sdmmc->regs = (t210_sdmmc_t *)(SDMMC_BASE + (u32)_sdmmc_base_offsets[id]); sdmmc->id = id; sdmmc->clock_stopped = 1; sdmmc->t210b01 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01; + trim_values = sdmmc->t210b01 ? trim_values_t210b01 : trim_values_t210; + // Do specific SDMMC HW configuration. switch (id) { @@ -1272,7 +1362,7 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int p if (sdmmc->t210b01) vref_sel = 0; else - sdmmc->manual_cal = 1; + sdmmc->periodic_calibration = 1; break; case SDMMC_2: @@ -1284,30 +1374,30 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int p // Disable clock if enabled. if (clock_sdmmc_is_not_reset_and_enabled(id)) { - _sdmmc_sd_clock_disable(sdmmc); + _sdmmc_card_clock_disable(sdmmc); _sdmmc_commit_changes(sdmmc); } // Configure and enable selected clock. clock_sdmmc_get_card_clock_div(&clock, &divisor, type); clock_sdmmc_enable(id, clock); + sdmmc->clock_stopped = 0; // Make sure all sdmmc registers are reset. _sdmmc_reset_all(sdmmc); - sdmmc->clock_stopped = 0; - // Set default pad IO trimming configuration. - sdmmc->regs->iospare |= 0x80000; // Enable muxing. - sdmmc->regs->veniotrimctl &= 0xFFFFFFFB; // Set Band Gap VREG to supply DLL. - sdmmc->regs->venclkctl = (sdmmc->regs->venclkctl & 0xE0FFFFFB) | (trim_values[sdmmc->id] << 24); - sdmmc->regs->sdmemcmppadctl = - (sdmmc->regs->sdmemcmppadctl & TEGRA_MMC_SDMEMCOMPPADCTRL_COMP_VREF_SEL_MASK) | vref_sel; + sdmmc->regs->iospare |= BIT(19); // Enable 1 cycle delayed cmd_oen. + sdmmc->regs->veniotrimctl &= ~BIT(2); // Set Band Gap VREG to supply DLL. + sdmmc->regs->venclkctl = (sdmmc->regs->venclkctl & 0xE0FFFFFB) | ((u32)trim_values[sdmmc->id] << 24); + sdmmc->regs->sdmemcmppadctl = (sdmmc->regs->sdmemcmppadctl & ~SDHCI_TEGRA_PADCTRL_VREF_SEL_MASK) | vref_sel; // Configure auto calibration values. if (!_sdmmc_autocal_config_offset(sdmmc, power)) return 0; + _sdmmc_commit_changes(sdmmc); + // Calibrate pads. _sdmmc_autocal_execute(sdmmc, power); @@ -1319,7 +1409,7 @@ int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int p if (sdmmc_setup_clock(sdmmc, type)) { - sdmmc_card_clock_powersave(sdmmc, powersave_enable); + sdmmc_card_clock_powersave(sdmmc, SDMMC_POWER_SAVE_DISABLE); _sdmmc_card_clock_enable(sdmmc); _sdmmc_commit_changes(sdmmc); @@ -1338,23 +1428,23 @@ void sdmmc1_disable_power() // T210B01 WAR: Set pads to discharge state. _sdmmc_config_sdmmc1_pads(true); - // Disable SD card IO power regulator. + // Disable SD card IO power. max7762x_regulator_enable(REGULATOR_LDO2, false); usleep(4000); - // Disable SD card IO power pin. + // Disable SD card power. gpio_write(GPIO_PORT_E, GPIO_PIN_4, GPIO_LOW); // T210/T210B01 WAR: Set start timer for IO and Controller power discharge. sd_power_cycle_time_start = get_tmr_ms(); - usleep(1000); // To power cycle, min 1ms without power is needed. + usleep(10000); // To power cycle, min 1ms without power is needed. // Disable SDMMC1 controller power. - PMC(APBDEV_PMC_NO_IOPOWER) |= PMC_NO_IOPOWER_SDMMC1_IO_EN; + PMC(APBDEV_PMC_NO_IOPOWER) |= PMC_NO_IOPOWER_SDMMC1; (void)PMC(APBDEV_PMC_NO_IOPOWER); // Commit write. // Inform IO pads that next voltage might be 3.3V. - PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_SDMMC1_IO_EN; + PMC(APBDEV_PMC_PWR_DET_VAL) |= PMC_PWR_DET_33V_SDMMC1; (void)PMC(APBDEV_PMC_PWR_DET_VAL); // Commit write. // T210B01 WAR: Restore pads to reset state. @@ -1368,7 +1458,7 @@ void sdmmc_end(sdmmc_t *sdmmc) { if (!sdmmc->clock_stopped) { - _sdmmc_sd_clock_disable(sdmmc); + _sdmmc_card_clock_disable(sdmmc); // Disable SDMMC power. _sdmmc_set_io_power(sdmmc, SDMMC_POWER_OFF); _sdmmc_commit_changes(sdmmc); @@ -1395,8 +1485,8 @@ int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *b if (!sdmmc->card_clock_enabled) return 0; - // Recalibrate periodically for SDMMC1. - if (sdmmc->manual_cal && sdmmc->powersave_enabled) + // Recalibrate periodically if needed. + if (sdmmc->periodic_calibration && sdmmc->powersave_enabled) _sdmmc_autocal_execute(sdmmc, sdmmc_get_io_power(sdmmc)); int should_disable_sd_clock = 0; @@ -1405,11 +1495,11 @@ int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *b should_disable_sd_clock = 1; sdmmc->regs->clkcon |= SDHCI_CLOCK_CARD_EN; _sdmmc_commit_changes(sdmmc); - usleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor); + usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles. } int result = _sdmmc_execute_cmd_inner(sdmmc, cmd, req, blkcnt_out); - usleep((8000 + sdmmc->divisor - 1) / sdmmc->divisor); + usleep((8 * 1000 + sdmmc->card_clock - 1) / sdmmc->card_clock); // Wait 8 cycles. if (should_disable_sd_clock) sdmmc->regs->clkcon &= ~SDHCI_CLOCK_CARD_EN; @@ -1419,10 +1509,7 @@ int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *b int sdmmc_enable_low_voltage(sdmmc_t *sdmmc) { - if(sdmmc->id != SDMMC_1) - return 0; - - if (!sdmmc_setup_clock(sdmmc, SDHCI_TIMING_UHS_SDR12)) + if (sdmmc->id != SDMMC_1) return 0; _sdmmc_commit_changes(sdmmc); @@ -1432,7 +1519,7 @@ int sdmmc_enable_low_voltage(sdmmc_t *sdmmc) usleep(150); // Inform IO pads that we switched to 1.8V. - PMC(APBDEV_PMC_PWR_DET_VAL) &= ~(PMC_PWR_DET_SDMMC1_IO_EN); + PMC(APBDEV_PMC_PWR_DET_VAL) &= ~PMC_PWR_DET_33V_SDMMC1; (void)PMC(APBDEV_PMC_PWR_DET_VAL); // Commit write. // Enable schmitt trigger for better duty cycle and low jitter clock. diff --git a/bdk/storage/sdmmc_driver.h b/bdk/storage/sdmmc_driver.h index 696ce4d..fe09c5a 100644 --- a/bdk/storage/sdmmc_driver.h +++ b/bdk/storage/sdmmc_driver.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2019 CTCaer + * Copyright (c) 2018-2025 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -22,21 +22,16 @@ #include /*! SDMMC controller IDs. */ -#define SDMMC_1 0 -#define SDMMC_2 1 -#define SDMMC_3 2 -#define SDMMC_4 3 +#define SDMMC_1 0 // Version 4.00. +#define SDMMC_2 1 // Version 5.0 + SW CQE + Enhanced Strobe. +#define SDMMC_3 2 // Version 4.00. +#define SDMMC_4 3 // Version 5.0 + SW CQE + Enhanced Strobe. /*! SDMMC power types. */ #define SDMMC_POWER_OFF 0 #define SDMMC_POWER_1_8 1 #define SDMMC_POWER_3_3 2 -/*! SDMMC bus widths. */ -#define SDMMC_BUS_WIDTH_1 0 -#define SDMMC_BUS_WIDTH_4 1 -#define SDMMC_BUS_WIDTH_8 2 - /*! SDMMC response types. */ #define SDMMC_RSP_TYPE_0 0 #define SDMMC_RSP_TYPE_1 1 @@ -45,131 +40,204 @@ #define SDMMC_RSP_TYPE_4 4 #define SDMMC_RSP_TYPE_5 5 +/*! SDMMC bus widths. */ +#define SDMMC_BUS_WIDTH_1 0 +#define SDMMC_BUS_WIDTH_4 1 +#define SDMMC_BUS_WIDTH_8 2 + /*! SDMMC mask interrupt status. */ #define SDMMC_MASKINT_MASKED 0 -#define SDMMC_MASKINT_NOERROR -1 -#define SDMMC_MASKINT_ERROR -2 +#define SDMMC_MASKINT_NOERROR 1 +#define SDMMC_MASKINT_ERROR 2 -/*! SDMMC present state. */ -#define SDHCI_CMD_INHIBIT 0x1 -#define SDHCI_DATA_INHIBIT 0x2 -#define SDHCI_DOING_WRITE 0x100 -#define SDHCI_DOING_READ 0x200 -#define SDHCI_SPACE_AVAILABLE 0x400 -#define SDHCI_DATA_AVAILABLE 0x800 -#define SDHCI_CARD_PRESENT 0x10000 -#define SDHCI_CD_STABLE 0x20000 -#define SDHCI_CD_LVL 0x40000 -#define SDHCI_WRITE_PROTECT 0x80000 +/*! SDMMC present state. 0x24. */ +#define SDHCI_CMD_INHIBIT BIT(0) +#define SDHCI_DATA_INHIBIT BIT(1) +#define SDHCI_DAT_LINE_ACTIVE BIT(2) +#define SDHCI_RETUNING_REQUEST BIT(3) +#define SDHCI_EMMC_LINE_LVL_MASK (0xFU << 4) +#define SDHCI_DATA_4_LVL BIT(4) // eMMC only. +#define SDHCI_DATA_5_LVL BIT(5) // eMMC only. +#define SDHCI_DATA_6_LVL BIT(6) // eMMC only. +#define SDHCI_DATA_7_LVL BIT(7) // eMMC only. +#define SDHCI_DOING_WRITE BIT(8) +#define SDHCI_DOING_READ BIT(9) // SD only. +#define SDHCI_SPACE_AVAILABLE BIT(10) // Write buffer empty. +#define SDHCI_DATA_AVAILABLE BIT(11) // Read buffer has data. +#define SDHCI_CARD_PRESENT BIT(16) +#define SDHCI_CD_STABLE BIT(17) +#define SDHCI_CD_LVL BIT(18) +#define SDHCI_WRITE_PROTECT BIT(19) #define SDHCI_DATA_LVL_MASK 0xF00000 -#define SDHCI_DATA_0_LVL_MASK 0x100000 -#define SDHCI_CMD_LVL 0x1000000 +#define SDHCI_DATA_0_LVL BIT(20) +#define SDHCI_DATA_1_LVL BIT(21) +#define SDHCI_DATA_2_LVL BIT(22) +#define SDHCI_DATA_3_LVL BIT(23) +#define SDHCI_CMD_LVL BIT(24) -/*! SDMMC transfer mode. */ -#define SDHCI_TRNS_DMA 0x01 -#define SDHCI_TRNS_BLK_CNT_EN 0x02 -#define SDHCI_TRNS_AUTO_CMD12 0x04 -#define SDHCI_TRNS_AUTO_CMD23 0x08 -#define SDHCI_TRNS_AUTO_SEL 0x0C -#define SDHCI_TRNS_WRITE 0x00 -#define SDHCI_TRNS_READ 0x10 -#define SDHCI_TRNS_MULTI 0x20 +/*! SDMMC transfer mode. 0x0C. */ +#define SDHCI_TRNS_DMA BIT(0) +#define SDHCI_TRNS_BLK_CNT_EN BIT(1) +#define SDHCI_TRNS_AUTO_CMD12 (1U << 2) +#define SDHCI_TRNS_AUTO_CMD23 (2U << 2) +#define SDHCI_TRNS_WRITE (0U << 4) +#define SDHCI_TRNS_READ BIT(4) +#define SDHCI_TRNS_MULTI BIT(5) +#define SDHCI_TRNS_RTYPE_R1 (0U << 6) +#define SDHCI_TRNS_RTYPE_R5 BIT(6) +#define SDHCI_TRNS_RSP_ERR_CHK BIT(7) +#define SDHCI_TRNS_RSP_INT_DIS BIT(8) -/*! SDMMC command. */ +/*! SDMMC command. 0x0E. */ #define SDHCI_CMD_RESP_MASK 0x3 #define SDHCI_CMD_RESP_NO_RESP 0x0 #define SDHCI_CMD_RESP_LEN136 0x1 #define SDHCI_CMD_RESP_LEN48 0x2 #define SDHCI_CMD_RESP_LEN48_BUSY 0x3 -#define SDHCI_CMD_CRC 0x08 -#define SDHCI_CMD_INDEX 0x10 -#define SDHCI_CMD_DATA 0x20 -#define SDHCI_CMD_ABORTCMD 0xC0 +#define SDHCI_CMD_CRC BIT(3) +#define SDHCI_CMD_INDEX BIT(4) +#define SDHCI_CMD_DATA BIT(5) +#define SDHCI_CMD_TYPE_NORMAL (0U << 6) +#define SDHCI_CMD_TYPE_SUSPEND (1U << 6) +#define SDHCI_CMD_TYPE_RESUME (2U << 6) +#define SDHCI_CMD_TYPE_ABORT (3U << 6) +#define SDHCI_CMD_SPI_CS_LOW BIT(7) +#define SDHCI_CMD_IDX(cmd) ((cmd) << 8) -/*! SDMMC host control. */ -#define SDHCI_CTRL_LED 0x01 -#define SDHCI_CTRL_4BITBUS 0x02 -#define SDHCI_CTRL_HISPD 0x04 -#define SDHCI_CTRL_DMA_MASK 0x18 -#define SDHCI_CTRL_SDMA 0x00 -#define SDHCI_CTRL_ADMA1 0x08 -#define SDHCI_CTRL_ADMA32 0x10 -#define SDHCI_CTRL_ADMA64 0x18 -#define SDHCI_CTRL_8BITBUS 0x20 -#define SDHCI_CTRL_CDTEST_INS 0x40 -#define SDHCI_CTRL_CDTEST_EN 0x80 -/*! SDMMC host control 2. */ -#define SDHCI_CTRL_UHS_MASK 0xFFF8 -#define SDHCI_CTRL_VDD_180 8 -#define SDHCI_CTRL_DRV_TYPE_B 0x00 -#define SDHCI_CTRL_DRV_TYPE_A 0x10 -#define SDHCI_CTRL_DRV_TYPE_C 0x20 -#define SDHCI_CTRL_DRV_TYPE_D 0x30 -#define SDHCI_CTRL_EXEC_TUNING 0x40 -#define SDHCI_CTRL_TUNED_CLK 0x80 -#define SDHCI_HOST_VERSION_4_EN 0x1000 -#define SDHCI_ADDRESSING_64BIT_EN 0x2000 -#define SDHCI_CTRL_PRESET_VAL_EN 0x8000 +/*! SDMMC host control. 0x28. */ +#define SDHCI_CTRL_LED BIT(0) +#define SDHCI_CTRL_4BITBUS BIT(1) // SD only. +#define SDHCI_CTRL_HISPD BIT(2) // SD only. +#define SDHCI_CTRL_DMA_MASK (3U << 3) +#define SDHCI_CTRL_SDMA (0U << 3) +#define SDHCI_CTRL_ADMA1 (1U << 3) +#define SDHCI_CTRL_ADMA32 (2U << 3) +#define SDHCI_CTRL_ADMA64 (3U << 3) +#define SDHCI_CTRL_8BITBUS BIT(5) // eMMC only (or UHS-II). +#define SDHCI_CTRL_CDTEST_INS BIT(6) +#define SDHCI_CTRL_CDTEST_EN BIT(7) -/*! SDMMC power control. */ -#define SDHCI_POWER_ON 0x01 -#define SDHCI_POWER_180 0x0A -#define SDHCI_POWER_300 0x0C -#define SDHCI_POWER_330 0x0E -#define SDHCI_POWER_MASK 0xF1 +/*! SDMMC host control 2. 0x3E. */ +#define SDHCI_CTRL_UHS_MASK 0x7 +#define SDHCI_CTRL_VDD_180 BIT(3) +#define SDHCI_CTRL_DRV_TYPE_MASK (3U << 4) +#define SDHCI_CTRL_DRV_TYPE_B (0U << 4) +#define SDHCI_CTRL_DRV_TYPE_A (1U << 4) +#define SDHCI_CTRL_DRV_TYPE_C (2U << 4) +#define SDHCI_CTRL_DRV_TYPE_D (3U << 4) +#define SDHCI_CTRL_DRV_TYPE(type) ((type) << 4) +#define SDHCI_CTRL_EXEC_TUNING BIT(6) +#define SDHCI_CTRL_TUNED_CLK_SHIFT 7 +#define SDHCI_CTRL_TUNED_CLK BIT(7) +#define SDHCI_HOST_VERSION_4_EN BIT(12) +#define SDHCI_ADDRESSING_64BIT_EN BIT(13) +#define SDHCI_CTRL_PRESET_VAL_EN BIT(15) -// /*! SDMMC max current. */ -// #define SDHCI_MAX_CURRENT_330_MASK 0xFF -// #define SDHCI_MAX_CURRENT_180_MASK 0xFF0000 -// #define SDHCI_MAX_CURRENT_MULTIPLIER 4 +/*! SDMMC power control. 0x29. */ +#define SDHCI_POWER_ON BIT(0) +#define SDHCI_POWER_180 (5U << 1) +#define SDHCI_POWER_300 (6U << 1) +#define SDHCI_POWER_330 (7U << 1) +#define SDHCI_POWER_MASK 0xF1 // UHS-II only. -/*! SDMMC clock control. */ -#define SDHCI_DIVIDER_SHIFT 8 -#define SDHCI_DIVIDER_HI_SHIFT 6 -#define SDHCI_DIV_MASK 0xFF00 -#define SDHCI_DIV_HI_MASK 0xC0 -#define SDHCI_PROG_CLOCK_MODE 0x20 -#define SDHCI_CLOCK_CARD_EN 0x4 -#define SDHCI_CLOCK_INT_STABLE 0x2 -#define SDHCI_CLOCK_INT_EN 0x1 +/*! SDMMC clock control. 0x2C. */ +#define SDHCI_CLOCK_INT_EN BIT(0) // Internal Clock. +#define SDHCI_CLOCK_INT_STABLE BIT(1) // Internal Clock Stable. +#define SDHCI_CLOCK_CARD_EN BIT(2) +#define SDHCI_PROG_CLOCK_MODE BIT(5) +#define SDHCI_DIV_HI_SHIFT 6 +#define SDHCI_DIV_HI_MASK (3U << SDHCI_DIV_HI_SHIFT) +#define SDHCI_DIV_LO_SHIFT 8 +#define SDHCI_DIV_MASK (0xFFU << SDHCI_DIV_LO_SHIFT) -/*! SDMMC software reset. */ -#define SDHCI_RESET_ALL 0x01 -#define SDHCI_RESET_CMD 0x02 -#define SDHCI_RESET_DATA 0x04 -/*! SDMMC interrupt status and control. */ -#define SDHCI_INT_RESPONSE 0x1 -#define SDHCI_INT_DATA_END 0x2 -#define SDHCI_INT_BLK_GAP 0x4 -#define SDHCI_INT_DMA_END 0x8 -#define SDHCI_INT_SPACE_AVAIL 0x10 -#define SDHCI_INT_DATA_AVAIL 0x20 -#define SDHCI_INT_CARD_INSERT 0x40 -#define SDHCI_INT_CARD_REMOVE 0x80 -#define SDHCI_INT_CARD_INT 0x100 -#define SDHCI_INT_RETUNE 0x1000 -#define SDHCI_INT_CQE 0x4000 -#define SDHCI_INT_ERROR 0x8000 +/*! SDMMC software reset. 0x2F. */ +#define SDHCI_RESET_ALL BIT(0) +#define SDHCI_RESET_CMD BIT(1) +#define SDHCI_RESET_DATA BIT(2) -/*! SDMMC error interrupt status and control. */ -#define SDHCI_ERR_INT_TIMEOUT 0x1 -#define SDHCI_ERR_INT_CRC 0x2 -#define SDHCI_ERR_INT_END_BIT 0x4 -#define SDHCI_ERR_INT_INDEX 0x8 -#define SDHCI_ERR_INT_DATA_TIMEOUT 0x10 -#define SDHCI_ERR_INT_DATA_CRC 0x20 -#define SDHCI_ERR_INT_DATA_END_BIT 0x40 -#define SDHCI_ERR_INT_BUS_POWER 0x80 -#define SDHCI_ERR_INT_AUTO_CMD_ERR 0x100 -#define SDHCI_ERR_INT_ADMA_ERROR 0x200 +/*! SDMMC interrupt status and control. 0x30/0x34. */ +#define SDHCI_INT_RESPONSE BIT(0) +#define SDHCI_INT_DATA_END BIT(1) +#define SDHCI_INT_BLK_GAP BIT(2) +#define SDHCI_INT_DMA_END BIT(3) +#define SDHCI_INT_SPACE_AVAIL BIT(4) // Write buffer empty. +#define SDHCI_INT_DATA_AVAIL BIT(5) // Read buffer has data. +#define SDHCI_INT_CARD_INSERT BIT(6) +#define SDHCI_INT_CARD_REMOVE BIT(7) +#define SDHCI_INT_CARD_INT BIT(8) +#define SDHCI_INT_RETUNE BIT(12) +#define SDHCI_INT_ERROR BIT(15) + +/*! SDMMC error interrupt status and control. 0x32/0x36. */ +#define SDHCI_ERR_INT_CMD_TIMEOUT BIT(0) +#define SDHCI_ERR_INT_CMD_CRC BIT(1) +#define SDHCI_ERR_INT_CMD_END_BIT BIT(2) +#define SDHCI_ERR_INT_CMD_INDEX BIT(3) +#define SDHCI_ERR_INT_DATA_TIMEOUT BIT(4) +#define SDHCI_ERR_INT_DATA_CRC BIT(5) +#define SDHCI_ERR_INT_DATA_END_BIT BIT(6) +#define SDHCI_ERR_INT_BUS_POWER BIT(7) +#define SDHCI_ERR_INT_AUTO_CMD12 BIT(8) +#define SDHCI_ERR_INT_ADMA BIT(9) +#define SDHCI_ERR_INT_TUNE BIT(10) +#define SDHCI_ERR_INT_RSP BIT(11) +#define SDHCI_ERR_INT_TARGET_RSP BIT(12) +#define SDHCI_ERR_INT_SPI BIT(13) +#define SDHCI_ERR_INT_VND_BOOT_TMO BIT(14) +#define SDHCI_ERR_INT_VND_BOOT_ACK BIT(15) #define SDHCI_ERR_INT_ALL_EXCEPT_ADMA_BUSPWR \ - (SDHCI_ERR_INT_AUTO_CMD_ERR | SDHCI_ERR_INT_DATA_END_BIT | \ - SDHCI_ERR_INT_DATA_CRC | SDHCI_ERR_INT_DATA_TIMEOUT | \ - SDHCI_ERR_INT_INDEX | SDHCI_ERR_INT_END_BIT | \ - SDHCI_ERR_INT_CRC | SDHCI_ERR_INT_TIMEOUT) + (SDHCI_ERR_INT_AUTO_CMD12 | SDHCI_ERR_INT_DATA_END_BIT | \ + SDHCI_ERR_INT_DATA_CRC | SDHCI_ERR_INT_DATA_TIMEOUT | \ + SDHCI_ERR_INT_CMD_INDEX | SDHCI_ERR_INT_CMD_END_BIT | \ + SDHCI_ERR_INT_CMD_CRC | SDHCI_ERR_INT_CMD_TIMEOUT) + +/*! Host Capability 1. 0x40. */ +#define SDHCI_CAP_TM_CLK_FREQ_MASK 0x3F +#define SDHCI_CAP_TM_UNIT_MHZ BIT(7) +#define SDHCI_CAP_BASE_CLK_FREQ_MASK (0xFFU << 8) +#define SDHCI_CAP_MAX_BLK_LEN_MASK (3U << 16) +#define SDHCI_CAP_EMMC_8BIT BIT(18) +#define SDHCI_CAP_ADMA2 BIT(19) +#define SDHCI_CAP_HISPD BIT(21) +#define SDHCI_CAP_SDMA BIT(22) +#define SDHCI_CAP_SUSPEND_RESUME BIT(23) +#define SDHCI_CAP_3_3_V BIT(24) +#define SDHCI_CAP_3_0_V BIT(25) +#define SDHCI_CAP_1_8_V BIT(26) +#define SDHCI_CAP_64BIT BIT(28) +#define SDHCI_CAP_ASYNC_INT BIT(29) +#define SDHCI_CAP_SLOT_TYPE_MASK (3U << 30) +#define SDHCI_CAP_SLOT_TYPE_REMOVABLE (0U << 30) +#define SDHCI_CAP_SLOT_TYPE_EMBEDDED (1U << 30) +#define SDHCI_CAP_SLOT_TYPE_SHARED (2U << 30) +#define SDHCI_CAP_SLOT_TYPE_UHS2 (3U << 30) + +/*! Host Capability 2. 0x44. */ +#define SDHCI_CAP_SDR50 BIT(0) +#define SDHCI_CAP_SDR5104 BIT(1) +#define SDHCI_CAP_DDR50 BIT(2) +#define SDHCI_CAP_UHS2 BIT(3) +#define SDHCI_CAP_DRV_TYPE_A BIT(4) +#define SDHCI_CAP_DRV_TYPE_C BIT(5) +#define SDHCI_CAP_DRV_TYPE_D BIT(6) +#define SDHCI_CAP_RSP_TIMER_CNT_MASK (0xFU << 8) +#define SDHCI_CAP_SDR50_TUNING BIT(13) +#define SDHCI_CAP_RSP_MODES_MASK (3U << 14) +#define SDHCI_CAP_CLK_MULT (0xFFU << 16) +#define SDHCI_CAP_ADMA3 BIT(27) +#define SDHCI_CAP_VDD2_1_8V BIT(28) + +/*! SDMMC max current. 0x48 */ +#define SDHCI_MAX_CURRENT_3_3_V_MASK (0xFFU << 0) +#define SDHCI_MAX_CURRENT_3_0_V_MASK (0xFFU << 8) +#define SDHCI_MAX_CURRENT_1_8_V_MASK (0xFFU << 16) +#define SDHCI_MAX_CURRENT_MULTIPLIER 4 + +/*! SDMMC max current. 0x4C */ +#define SDHCI_MAX_CURRENT_1_8_V_VDD2_MASK (0xFFU << 0) /*! SD bus speeds. */ #define UHS_SDR12_BUS_SPEED 0 @@ -193,11 +261,11 @@ #define SDHCI_TIMING_UHS_SDR25 9 #define SDHCI_TIMING_UHS_SDR50 10 #define SDHCI_TIMING_UHS_SDR104 11 -#define SDHCI_TIMING_UHS_SDR82 12 // SDR104 with a 163.2MHz -> 81.6MHz clock. -#define SDHCI_TIMING_UHS_DDR50 13 -#define SDHCI_TIMING_MMC_HS102 14 - -#define SDHCI_CAN_64BIT 0x10000000 +#define SDHCI_TIMING_UHS_DDR50 12 +// SDR104 with a 163.2MHz -> 81.6MHz clock. +#define SDHCI_TIMING_UHS_SDR82 13 // GC FPGA. Obsolete and Repurposed. MMC_HS50 -> SDR82. +#define SDHCI_TIMING_MMC_HS100 14 // GC ASIC. +#define SDHCI_TIMING_UHS_DDR200 15 /*! SDMMC Low power features. */ #define SDMMC_POWER_SAVE_DISABLE 0 @@ -206,22 +274,27 @@ /*! Helper for SWITCH command argument. */ #define SDMMC_SWITCH(mode, index, value) (((mode) << 24) | ((index) << 16) | ((value) << 8)) +#define HW_TAP_TUNING 0x100 +#define INVALID_TAP 0x100 +#define SAMPLING_WINDOW_SIZE_MIN 8 + /*! SDMMC controller context. */ typedef struct _sdmmc_t { t210_sdmmc_t *regs; u32 id; - u32 divisor; + u32 card_clock; u32 clock_stopped; int powersave_enabled; - int manual_cal; + int periodic_calibration; int card_clock_enabled; int venclkctl_set; u32 venclkctl_tap; u32 expected_rsp_type; u32 dma_addr_next; u32 rsp[4]; - u32 rsp3; + u32 stop_trn_rsp; + u32 error_sts; int t210b01; } sdmmc_t; @@ -249,13 +322,14 @@ int sdmmc_get_io_power(sdmmc_t *sdmmc); u32 sdmmc_get_bus_width(sdmmc_t *sdmmc); void sdmmc_set_bus_width(sdmmc_t *sdmmc, u32 bus_width); void sdmmc_save_tap_value(sdmmc_t *sdmmc); +void sdmmc_setup_drv_type(sdmmc_t *sdmmc, u32 type); int sdmmc_setup_clock(sdmmc_t *sdmmc, u32 type); void sdmmc_card_clock_powersave(sdmmc_t *sdmmc, int powersave_enable); -int sdmmc_get_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 size, u32 type); +int sdmmc_get_cached_rsp(sdmmc_t *sdmmc, u32 *rsp, u32 type); int sdmmc_tuning_execute(sdmmc_t *sdmmc, u32 type, u32 cmd); int sdmmc_stop_transmission(sdmmc_t *sdmmc, u32 *rsp); bool sdmmc_get_sd_inserted(); -int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type, int powersave_enable); +int sdmmc_init(sdmmc_t *sdmmc, u32 id, u32 power, u32 bus_width, u32 type); void sdmmc_end(sdmmc_t *sdmmc); void sdmmc_init_cmd(sdmmc_cmd_t *cmdbuf, u16 cmd, u32 arg, u32 rsp_type, u32 check_busy); int sdmmc_execute_cmd(sdmmc_t *sdmmc, sdmmc_cmd_t *cmd, sdmmc_req_t *req, u32 *blkcnt_out); diff --git a/bdk/storage/sdmmc_t210.h b/bdk/storage/sdmmc_t210.h index 2c1b3a5..26c1e49 100644 --- a/bdk/storage/sdmmc_t210.h +++ b/bdk/storage/sdmmc_t210.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2019 CTCaer + * Copyright (c) 2018-2025 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,92 +18,109 @@ #ifndef _SDMMC_T210_H_ #define _SDMMC_T210_H_ +#include #include -#define TEGRA_MMC_VNDR_TUN_CTRL0_TAP_VAL_UPDATED_BY_HW 0x20000 -#define TEGRA_MMC_DLLCAL_CFG_EN_CALIBRATE 0x80000000 -#define TEGRA_MMC_DLLCAL_CFG_STATUS_DLL_ACTIVE 0x80000000 -#define TEGRA_MMC_SDMEMCOMPPADCTRL_PAD_E_INPUT_PWRD 0x80000000 -#define TEGRA_MMC_SDMEMCOMPPADCTRL_COMP_VREF_SEL_MASK 0xFFFFFFF0 -#define TEGRA_MMC_AUTOCALCFG_AUTO_CAL_ENABLE 0x20000000 -#define TEGRA_MMC_AUTOCALCFG_AUTO_CAL_START 0x80000000 -#define TEGRA_MMC_AUTOCALSTS_AUTO_CAL_ACTIVE 0x80000000 +#define SDHCI_TEGRA_TUNING_TAP_HW_UPDATED BIT(17) +#define SDHCI_TEGRA_DLLCAL_CALIBRATE BIT(31) +#define SDHCI_TEGRA_DLLCAL_ACTIVE BIT(31) +#define SDHCI_TEGRA_PADCTRL_E_INPUT_PWRD BIT(31) +#define SDHCI_TEGRA_PADCTRL_VREF_SEL_MASK 0xF +#define SDHCI_TEGRA_AUTOCAL_SLW_OVERRIDE BIT(28) +#define SDHCI_TEGRA_AUTOCAL_ENABLE BIT(29) +#define SDHCI_TEGRA_AUTOCAL_START BIT(31) +#define SDHCI_TEGRA_AUTOCAL_ACTIVE BIT(31) typedef struct _t210_sdmmc_t { - vu32 sysad; - vu16 blksize; - vu16 blkcnt; - vu32 argument; - vu16 trnmod; - vu16 cmdreg; - vu32 rspreg0; - vu32 rspreg1; - vu32 rspreg2; - vu32 rspreg3; - vu32 bdata; - vu32 prnsts; - vu8 hostctl; - vu8 pwrcon; - vu8 blkgap; - vu8 wakcon; - vu16 clkcon; - vu8 timeoutcon; - vu8 swrst; - vu16 norintsts; - vu16 errintsts; - vu16 norintstsen; // Enable irq status. - vu16 errintstsen; // Enable irq status. - vu16 norintsigen; // Enable irq signal to LIC/GIC. - vu16 errintsigen; // Enable irq signal to LIC/GIC. - vu16 acmd12errsts; - vu16 hostctl2; - vu32 capareg; - vu32 capareg_1; - vu32 maxcurr; - vu8 rsvd0[4]; // 4C-4F reserved for more max current. - vu16 setacmd12err; - vu16 setinterr; - vu8 admaerr; - vu8 rsvd1[3]; // 55-57 reserved. - vu32 admaaddr; - vu32 admaaddr_hi; - vu8 rsvd2[156]; // 60-FB reserved. - vu16 slotintsts; - vu16 hcver; - vu32 venclkctl; - vu32 vensysswctl; - vu32 venerrintsts; - vu32 vencapover; - vu32 venbootctl; - vu32 venbootacktout; - vu32 venbootdattout; - vu32 vendebouncecnt; - vu32 venmiscctl; - vu32 maxcurrover; - vu32 maxcurrover_hi; - vu32 unk0[32]; // 0x12C - vu32 veniotrimctl; - vu32 vendllcalcfg; - vu32 vendllctl0; - vu32 vendllctl1; - vu32 vendllcalcfgsts; - vu32 ventunctl0; - vu32 ventunctl1; - vu32 ventunsts0; - vu32 ventunsts1; - vu32 venclkgatehystcnt; - vu32 venpresetval0; - vu32 venpresetval1; - vu32 venpresetval2; - vu32 sdmemcmppadctl; - vu32 autocalcfg; - vu32 autocalintval; - vu32 autocalsts; - vu32 iospare; - vu32 mcciffifoctl; - vu32 timeoutwcoal; - vu32 unk1; +/* 0x00 */ vu32 sysad; // sdma system address. +/* 0x04 */ vu16 blksize; +/* 0x06 */ vu16 blkcnt; +/* 0x08 */ vu32 argument; +/* 0x0C */ vu16 trnmod; +/* 0x0E */ vu16 cmdreg; +/* 0x10 */ vu32 rspreg[4]; +/* 0x20 */ vu32 bdata; // Buffer data port. +/* 0x24 */ vu32 prnsts; +/* 0x28 */ vu8 hostctl; +/* 0x29 */ vu8 pwrcon; +/* 0x2A */ vu8 blkgap; +/* 0x2B */ vu8 wakcon; +/* 0x2C */ vu16 clkcon; +/* 0x2E */ vu8 timeoutcon; +/* 0x2F */ vu8 swrst; +/* 0x30 */ vu16 norintsts; // Normal interrupt status. +/* 0x32 */ vu16 errintsts; // Error interrupt status. +/* 0x34 */ vu16 norintstsen; // Enable irq status. +/* 0x36 */ vu16 errintstsen; // Enable irq status. +/* 0x38 */ vu16 norintsigen; // Enable irq signal to LIC/GIC. +/* 0x3A */ vu16 errintsigen; // Enable irq signal to LIC/GIC. +/* 0x3C */ vu16 acmd12errsts; +/* 0x3E */ vu16 hostctl2; + +// CAP0: 0x376CD08C. +// 12 MHz timeout clock. 208 MHz max base clock. 512B max block length. 8-bit support. +// ADMA2 support. HS25 support. SDMA support. No suspend/resume support. 3.3/3.0/1.8V support. +// 64bit addressing for V3/V4 support. Async IRQ support. All report as removable. +/* 0x40 */ vu32 capareg; +// CAP1: 0x10002F73. +// SDR50/SDR104 support. No DDR50 support. Drive A/B/C/D support. +// Timer re-tuning info from other source. SDR50 requires re-tuning. +// Tuning uses timer and transfers should be 4MB limited. +// ADMA3 not supported. 1.8V VDD2 supported. +/* 0x44 */ vu32 capareg_hi; + +/* 0x48 */ vu32 maxcurr; // Get information by another method. Can be overriden via maxcurrover and maxcurrover_hi. +/* 0x4C */ vu32 maxcurr_hi; +/* 0x50 */ vu16 setacmd12err; // Force error in acmd12errsts. +/* 0x52 */ vu16 setinterr; +/* 0x54 */ vu8 admaerr; +/* 0x55 */ vu8 rsvd1[3]; // 55-57 reserved. +/* 0x58 */ vu32 admaaddr; +/* 0x5C */ vu32 admaaddr_hi; +/* 0x60 */ vu16 presets[11]; +/* 0x76 */ vu16 rsvd2; +/* 0x78 */ vu32 adma3addr; +/* 0x7C */ vu32 adma3addr_hi; +/* 0x80 */ vu8 uhs2[124]; // 80-FB UHS-II. +/* 0xFC */ vu16 slotintsts; +/* 0xFE */ vu16 hcver; // 0x303 (4.00). + +/* UHS-II range. Used for Vendor registers here */ +/* 0x100 */ vu32 venclkctl; +/* 0x104 */ vu32 vensysswctl; +/* 0x108 */ vu32 venerrintsts; +/* 0x10C */ vu32 vencapover; +/* 0x110 */ vu32 venbootctl; +/* 0x114 */ vu32 venbootacktout; +/* 0x118 */ vu32 venbootdattout; +/* 0x11C */ vu32 vendebouncecnt; +/* 0x120 */ vu32 venmiscctl; +/* 0x124 */ vu32 maxcurrover; +/* 0x128 */ vu32 maxcurrover_hi; +/* 0x12C */ vu32 unk0[32]; // 0x12C +/* 0x1AC */ vu32 veniotrimctl; +/* 0x1B0 */ vu32 vendllcalcfg; +/* 0x1B4 */ vu32 vendllctl0; +/* 0x1B8 */ vu32 vendllctl1; +/* 0x1BC */ vu32 vendllcalcfgsts; +/* 0x1C0 */ vu32 ventunctl0; +/* 0x1C4 */ vu32 ventunctl1; +/* 0x1C8 */ vu32 ventunsts0; +/* 0x1CC */ vu32 ventunsts1; +/* 0x1D0 */ vu32 venclkgatehystcnt; +/* 0x1D4 */ vu32 venpresetval0; +/* 0x1D8 */ vu32 venpresetval1; +/* 0x1DC */ vu32 venpresetval2; +/* 0x1E0 */ vu32 sdmemcmppadctl; +/* 0x1E4 */ vu32 autocalcfg; +/* 0x1E8 */ vu32 autocalintval; +/* 0x1EC */ vu32 autocalsts; +/* 0x1F0 */ vu32 iospare; +/* 0x1F4 */ vu32 mcciffifoctl; +/* 0x1F8 */ vu32 timeoutwcoal; } t210_sdmmc_t; +static_assert(sizeof(t210_sdmmc_t) == 0x1FC, "T210 SDMMC REG size is wrong!"); + #endif diff --git a/bdk/thermal/fan.c b/bdk/thermal/fan.c index 14379e3..22bddcc 100644 --- a/bdk/thermal/fan.c +++ b/bdk/thermal/fan.c @@ -1,7 +1,7 @@ /* * Fan driver for Nintendo Switch * - * Copyright (c) 2018-2020 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,25 +18,38 @@ #include #include +#include +#include +#include #include +#include #include +#include #include -#include -void set_fan_duty(u32 duty) +void fan_set_duty(u32 duty) { static bool fan_init = false; static u16 curr_duty = -1; + if (duty > 236) + duty = 236; + if (curr_duty == duty) return; + curr_duty = duty; + if (!fan_init) { // Fan tachometer. - PINMUX_AUX(PINMUX_AUX_CAM1_PWDN) = PINMUX_TRISTATE | PINMUX_INPUT_ENABLE | PINMUX_PULL_UP | 1; - gpio_config(GPIO_PORT_S, GPIO_PIN_7, GPIO_MODE_GPIO); - gpio_output_enable(GPIO_PORT_S, GPIO_PIN_7, GPIO_OUTPUT_DISABLE); + u32 pull_resistor = hw_get_chip_id() == GP_HIDREV_MAJOR_T210 ? PINMUX_PULL_UP : 0; + PINMUX_AUX(PINMUX_AUX_CAM1_PWDN) = PINMUX_TRISTATE | PINMUX_INPUT_ENABLE | pull_resistor | 1; + gpio_direction_input(GPIO_PORT_S, GPIO_PIN_7); + + // Enable PWM if disabled. + if (fuse_read_hw_type() == FUSE_NX_HW_TYPE_AULA) + clock_enable_pwm(); PWM(PWM_CONTROLLER_PWM_CSR_1) = PWM_CSR_EN | (0x100 << 16); // Max PWM to disable fan. @@ -46,9 +59,6 @@ void set_fan_duty(u32 duty) fan_init = true; } - if (duty > 236) - duty = 236; - // Inverted polarity. u32 inv_duty = 236 - duty; @@ -59,8 +69,8 @@ void set_fan_duty(u32 duty) regulator_5v_disable(REGULATOR_5V_FAN); // Disable fan. - PINMUX_AUX(PINMUX_AUX_LCD_GPIO2) = - PINMUX_INPUT_ENABLE | PINMUX_PARKED | PINMUX_TRISTATE | PINMUX_PULL_DOWN; // Set source to PWM1. + PINMUX_AUX(PINMUX_AUX_LCD_GPIO2) = PINMUX_INPUT_ENABLE | PINMUX_PARKED | + PINMUX_TRISTATE | PINMUX_PULL_DOWN; // Set source to PWM1. } else // Set PWM duty. { @@ -71,11 +81,9 @@ void set_fan_duty(u32 duty) // Enable fan. PINMUX_AUX(PINMUX_AUX_LCD_GPIO2) = 1; // Set source to PWM1. } - - curr_duty = duty; } -void get_fan_speed(u32 *duty, u32 *rpm) +void fan_get_speed(u32 *duty, u32 *rpm) { if (rpm) { @@ -106,3 +114,15 @@ void get_fan_speed(u32 *duty, u32 *rpm) if (duty) *duty = 236 - ((PWM(PWM_CONTROLLER_PWM_CSR_1) >> 16) & 0xFF); } + +void fan_set_from_temp(u32 temp) +{ + if (temp >= 52) + fan_set_duty(102); + else if (temp >= 47) + fan_set_duty(76); + else if (temp >= 42) + fan_set_duty(51); + else if (temp <= 39) + fan_set_duty(0); +} diff --git a/bdk/thermal/fan.h b/bdk/thermal/fan.h index e827975..3c70b30 100644 --- a/bdk/thermal/fan.h +++ b/bdk/thermal/fan.h @@ -1,7 +1,7 @@ /* * Fan driver for Nintendo Switch * - * Copyright (c) 2018 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -22,8 +22,10 @@ #include // Disable: 0 (0 RPM), min duty: 1 (960 RPM), max duty 235 (11000 RPM). -void set_fan_duty(u32 duty); -// Passing NULL ptr on either of the two, disables parsing of it. -void get_fan_speed(u32 *duty, u32 *rpm); +void fan_set_duty(u32 duty); +// Passing NULL ptr on either of the two, disables results. +void fan_get_speed(u32 *duty, u32 *rpm); + +void fan_set_from_temp(u32 temp); #endif /* __FAN_H_ */ diff --git a/bdk/usb/usb_descriptor_types.h b/bdk/usb/usb_descriptor_types.h index 9f86e9d..cb58abc 100644 --- a/bdk/usb/usb_descriptor_types.h +++ b/bdk/usb/usb_descriptor_types.h @@ -99,7 +99,7 @@ typedef struct _usb_cfg_descr_t u8 bConfigurationValue; // Value of this configuration (1 based). u8 iConfiguration; // Index of String Descriptor describing the configuration. u8 bmAttributes; // Configuration characteristics. - u8 bMaxPower; // Maximum power consumed by this configuration. + u8 bMaxPower; // Maximum power consumed by this configuration. In 2mA (usb2) or 8mA (usb3). } __attribute__((packed)) usb_cfg_descr_t; /* Interface descriptor structure */ diff --git a/bdk/usb/usb_gadget_hid.c b/bdk/usb/usb_gadget_hid.c index b7c2e24..dc7681a 100644 --- a/bdk/usb/usb_gadget_hid.c +++ b/bdk/usb/usb_gadget_hid.c @@ -1,7 +1,7 @@ /* * USB Gadget HID driver for Tegra X1 * - * Copyright (c) 2019-2020 CTCaer + * Copyright (c) 2019-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -23,8 +23,8 @@ #include #include #include +#include #include -#include #include @@ -56,52 +56,67 @@ typedef struct _gamepad_report_t typedef struct _jc_cal_t { - bool cl_done; - bool cr_done; - u16 clx_max; - u16 clx_min; - u16 cly_max; - u16 cly_min; - u16 crx_max; - u16 crx_min; - u16 cry_max; - u16 cry_min; +// 15ms * JC_CAL_MAX_STEPS = 240 ms. +#define JC_CAL_MAX_STEPS 16 + u32 cl_step; + u32 cr_step; + + u16 clx_max; + u16 clx_min; + u16 cly_max; + u16 cly_min; + u16 crx_max; + u16 crx_min; + u16 cry_max; + u16 cry_min; } jc_cal_t; +enum { + INPUT_POLL_HAS_PACKET, + INPUT_POLL_NO_PACKET, + INPUT_POLL_EXIT, +}; + static jc_cal_t jc_cal_ctx; static usb_ops_t usb_ops; -static bool _jc_calibration(jc_gamepad_rpt_t *jc_pad) +static bool _jc_calibration(const jc_gamepad_rpt_t *jc_pad) { // Calibrate left stick. - if (!jc_cal_ctx.cl_done) + if (jc_cal_ctx.cl_step != JC_CAL_MAX_STEPS) { if (jc_pad->conn_l && jc_pad->lstick_x > 0x400 && jc_pad->lstick_y > 0x400 && jc_pad->lstick_x < 0xC00 && jc_pad->lstick_y < 0xC00) { + jc_cal_ctx.cl_step++; jc_cal_ctx.clx_max = jc_pad->lstick_x + 0x72; jc_cal_ctx.clx_min = jc_pad->lstick_x - 0x72; jc_cal_ctx.cly_max = jc_pad->lstick_y + 0x72; jc_cal_ctx.cly_min = jc_pad->lstick_y - 0x72; - jc_cal_ctx.cl_done = true; + + if (jc_cal_ctx.cl_step != JC_CAL_MAX_STEPS) + return false; } else return false; } // Calibrate right stick. - if (!jc_cal_ctx.cr_done) + if (jc_cal_ctx.cr_step != JC_CAL_MAX_STEPS) { if (jc_pad->conn_r && jc_pad->rstick_x > 0x400 && jc_pad->rstick_y > 0x400 && jc_pad->rstick_x < 0xC00 && jc_pad->rstick_y < 0xC00) { + jc_cal_ctx.cr_step++; jc_cal_ctx.crx_max = jc_pad->rstick_x + 0x72; jc_cal_ctx.crx_min = jc_pad->rstick_x - 0x72; jc_cal_ctx.cry_max = jc_pad->rstick_y + 0x72; jc_cal_ctx.cry_min = jc_pad->rstick_y - 0x72; - jc_cal_ctx.cr_done = true; + + if (jc_cal_ctx.cr_step != JC_CAL_MAX_STEPS) + return false; } else return false; @@ -110,29 +125,31 @@ static bool _jc_calibration(jc_gamepad_rpt_t *jc_pad) return true; } -static bool _jc_poll(gamepad_report_t *rpt) +static int _jc_poll(gamepad_report_t *rpt) { + static gamepad_report_t prev_rpt = {0}; + // Poll Joy-Con. jc_gamepad_rpt_t *jc_pad = joycon_poll(); if (!jc_pad) - return false; + return INPUT_POLL_NO_PACKET; // Exit emulation if Left stick and Home are pressed. if (jc_pad->l3 && jc_pad->home) - return true; + return INPUT_POLL_EXIT; - if (!jc_cal_ctx.cl_done || !jc_cal_ctx.cr_done) + if (jc_cal_ctx.cl_step != JC_CAL_MAX_STEPS || jc_cal_ctx.cr_step != JC_CAL_MAX_STEPS) { if (!_jc_calibration(jc_pad)) - return false; + return INPUT_POLL_NO_PACKET; } // Re-calibrate on disconnection. if (!jc_pad->conn_l) - jc_cal_ctx.cl_done = false; + jc_cal_ctx.cl_step = 0; if (!jc_pad->conn_r) - jc_cal_ctx.cr_done = false; + jc_cal_ctx.cr_step = 0; // Calculate left analog stick. if (jc_pad->lstick_x <= jc_cal_ctx.clx_max && jc_pad->lstick_x >= jc_cal_ctx.clx_min) @@ -159,14 +176,22 @@ static bool _jc_poll(gamepad_report_t *rpt) u16 y_raw = (jc_pad->lstick_y - jc_cal_ctx.cly_max) / 7; if (y_raw > 0x7F) y_raw = 0x7F; - rpt->y = 0x7F - y_raw; + // Hoag has inverted Y axis. + if (!jc_pad->sio_mode) + rpt->y = 0x7F - y_raw; + else + rpt->y = 0x7F + y_raw; } else { u16 y_raw = (jc_cal_ctx.cly_min - jc_pad->lstick_y) / 7; if (y_raw > 0x7F) y_raw = 0x7F; - rpt->y = 0x7F + y_raw; + // Hoag has inverted Y axis. + if (!jc_pad->sio_mode) + rpt->y = 0x7F + y_raw; + else + rpt->y = 0x7F - y_raw; } // Calculate right analog stick. @@ -194,14 +219,22 @@ static bool _jc_poll(gamepad_report_t *rpt) u16 y_raw = (jc_pad->rstick_y - jc_cal_ctx.cry_max) / 7; if (y_raw > 0x7F) y_raw = 0x7F; - rpt->rz = 0x7F - y_raw; + // Hoag has inverted Y axis. + if (!jc_pad->sio_mode) + rpt->rz = 0x7F - y_raw; + else + rpt->rz = 0x7F + y_raw; } else { u16 y_raw = (jc_cal_ctx.cry_min - jc_pad->rstick_y) / 7; if (y_raw > 0x7F) y_raw = 0x7F; - rpt->rz = 0x7F + y_raw; + // Hoag has inverted Y axis. + if (!jc_pad->sio_mode) + rpt->rz = 0x7F + y_raw; + else + rpt->rz = 0x7F - y_raw; } // Set D-pad. @@ -257,7 +290,12 @@ static bool _jc_poll(gamepad_report_t *rpt) //rpt->btn13 = jc_pad->cap; //rpt->btn14 = jc_pad->home; - return false; + if (!memcmp(rpt, &prev_rpt, sizeof(gamepad_report_t))) + return INPUT_POLL_NO_PACKET; + + memcpy(&prev_rpt, rpt, sizeof(gamepad_report_t)); + + return INPUT_POLL_HAS_PACKET; } typedef struct _touchpad_report_t @@ -326,12 +364,14 @@ static u8 _hid_transfer_start(usb_ctxt_t *usbs, u32 len) static bool _hid_poll_jc(usb_ctxt_t *usbs) { - if (_jc_poll((gamepad_report_t *)USB_EP_BULK_IN_BUF_ADDR)) + int res = _jc_poll((gamepad_report_t *)USB_EP_BULK_IN_BUF_ADDR); + if (res == INPUT_POLL_EXIT) return true; // Send HID report. - if (_hid_transfer_start(usbs, sizeof(gamepad_report_t))) - return true; // EP Error. + if (res == INPUT_POLL_HAS_PACKET) + if (_hid_transfer_start(usbs, sizeof(gamepad_report_t))) + return true; // EP Error. return false; } @@ -361,7 +401,7 @@ int usb_device_gadget_hid(usb_ctxt_t *usbs) if (usbs->type == USB_HID_GAMEPAD) { - polling_time = 8000; + polling_time = 15000; gadget_type = USB_GADGET_HID_GAMEPAD; } else diff --git a/bdk/usb/usb_gadget_ums.c b/bdk/usb/usb_gadget_ums.c index 4be2436..1655bd5 100644 --- a/bdk/usb/usb_gadget_ums.c +++ b/bdk/usb/usb_gadget_ums.c @@ -4,7 +4,7 @@ * Copyright (c) 2003-2008 Alan Stern * Copyright (c) 2009 Samsung Electronics * Author: Michal Nazarewicz - * Copyright (c) 2019-2021 CTCaer + * Copyright (c) 2019-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -24,13 +24,13 @@ #include #include #include +#include #include -#include +#include #include #include #include #include -#include #include @@ -283,40 +283,40 @@ static void raise_exception(usbd_gadget_ums_t *ums, enum ums_state new_state) } } -static void ums_handle_ep0_ctrl(usbd_gadget_ums_t *ums) +static void _handle_ep0_ctrl(usbd_gadget_ums_t *ums) { if (usb_ops.usbd_handle_ep0_ctrl_setup()) raise_exception(ums, UMS_STATE_PROTOCOL_RESET); } -static int ums_wedge_bulk_in_endpoint(usbd_gadget_ums_t *ums) +static int _wedge_bulk_in_endpoint(usbd_gadget_ums_t *ums) { /* usbd_set_ep_wedge(bulk_ctxt->bulk_in); */ return UMS_RES_OK; } -static int ums_set_stall(u32 ep) +static int _set_ep_stall(u32 ep) { usb_ops.usbd_set_ep_stall(ep, USB_EP_CFG_STALL); return UMS_RES_OK; } -static int ums_clear_stall(u32 ep) +static int _clear_ep_stall(u32 ep) { usb_ops.usbd_set_ep_stall(ep, USB_EP_CFG_CLEAR); return UMS_RES_OK; } -static void ums_flush_endpoint(u32 ep) +static void _flush_endpoint(u32 ep) { if (usb_ops.usbd_flush_endpoint) usb_ops.usbd_flush_endpoint(ep); } -static void _ums_transfer_start(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt, u32 ep, u32 sync_timeout) +static void _transfer_start(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt, u32 ep, u32 sync_timeout) { if (ep == bulk_ctxt->bulk_in) { @@ -327,7 +327,7 @@ static void _ums_transfer_start(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt, if (bulk_ctxt->bulk_in_status == USB_ERROR_XFER_ERROR) { ums->set_text(ums->label, "#FFDD00 Error:# EP IN transfer!"); - ums_flush_endpoint(bulk_ctxt->bulk_in); + _flush_endpoint(bulk_ctxt->bulk_in); } else if (bulk_ctxt->bulk_in_status == USB2_ERROR_XFER_NOT_ALIGNED) ums->set_text(ums->label, "#FFDD00 Error:# EP IN Buffer not aligned!"); @@ -344,7 +344,7 @@ static void _ums_transfer_start(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt, if (bulk_ctxt->bulk_out_status == USB_ERROR_XFER_ERROR) { ums->set_text(ums->label, "#FFDD00 Error:# EP OUT transfer!"); - ums_flush_endpoint(bulk_ctxt->bulk_out); + _flush_endpoint(bulk_ctxt->bulk_out); } else if (bulk_ctxt->bulk_out_status == USB2_ERROR_XFER_NOT_ALIGNED) ums->set_text(ums->label, "#FFDD00 Error:# EP OUT Buffer not aligned!"); @@ -354,7 +354,7 @@ static void _ums_transfer_start(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt, } } -static void _ums_transfer_out_big_read(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) +static void _transfer_out_big_read(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) { bulk_ctxt->bulk_out_status = usb_ops.usb_device_ep1_out_read_big( bulk_ctxt->bulk_out_buf, bulk_ctxt->bulk_out_length, @@ -363,13 +363,13 @@ static void _ums_transfer_out_big_read(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk if (bulk_ctxt->bulk_out_status == USB_ERROR_XFER_ERROR) { ums->set_text(ums->label, "#FFDD00 Error:# EP OUT transfer!"); - ums_flush_endpoint(bulk_ctxt->bulk_out); + _flush_endpoint(bulk_ctxt->bulk_out); } bulk_ctxt->bulk_out_buf_state = BUF_STATE_FULL; } -static void _ums_transfer_finish(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt, u32 ep, u32 sync_timeout) +static void _transfer_finish(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt, u32 ep, u32 sync_timeout) { if (ep == bulk_ctxt->bulk_in) { @@ -379,7 +379,7 @@ static void _ums_transfer_finish(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt, if (bulk_ctxt->bulk_in_status == USB_ERROR_XFER_ERROR) { ums->set_text(ums->label, "#FFDD00 Error:# EP IN transfer!"); - ums_flush_endpoint(bulk_ctxt->bulk_in); + _flush_endpoint(bulk_ctxt->bulk_in); } bulk_ctxt->bulk_in_buf_state = BUF_STATE_EMPTY; @@ -392,14 +392,14 @@ static void _ums_transfer_finish(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt, if (bulk_ctxt->bulk_out_status == USB_ERROR_XFER_ERROR) { ums->set_text(ums->label, "#FFDD00 Error:# EP OUT transfer!"); - ums_flush_endpoint(bulk_ctxt->bulk_out); + _flush_endpoint(bulk_ctxt->bulk_out); } bulk_ctxt->bulk_out_buf_state = BUF_STATE_FULL; } } -static void _ums_reset_buffer(bulk_ctxt_t *bulk_ctxt, u32 ep) +static void _reset_buffer(bulk_ctxt_t *bulk_ctxt, u32 ep) { if (ep == bulk_ctxt->bulk_in) bulk_ctxt->bulk_in_buf = (u8 *)USB_EP_BULK_IN_BUF_ADDR; @@ -474,20 +474,21 @@ static int _scsi_read(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) // Limit IO transfers based on request for faster concurrent reads. u32 max_io_transfer = (amount_left >= UMS_SCSI_TRANSFER_512K) ? - UMS_DISK_MAX_IO_TRANSFER_64K : UMS_DISK_MAX_IO_TRANSFER_32K; + UMS_DISK_MAX_IO_TRANSFER_64K : UMS_DISK_MAX_IO_TRANSFER_32K; while (true) { // Max io size and end sector limits. u32 amount = MIN(amount_left, max_io_transfer); - amount = MIN(amount, ums->lun.num_sectors - lba_offset); + amount = MIN(amount, ums->lun.num_sectors - lba_offset); // Check if it is a read past the end sector. if (!amount) { - ums->lun.sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + ums->lun.sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ums->lun.sense_data_info = lba_offset; - ums->lun.info_valid = 1; + ums->lun.info_valid = 1; + bulk_ctxt->bulk_in_length = 0; bulk_ctxt->bulk_in_buf_state = BUF_STATE_FULL; break; @@ -499,7 +500,7 @@ static int _scsi_read(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) // Wait for the async USB transfer to finish. if (!first_read) - _ums_transfer_finish(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED); + _transfer_finish(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED); lba_offset += amount; amount_left -= amount; @@ -513,9 +514,9 @@ static int _scsi_read(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) if (!amount) { ums->set_text(ums->label, "#FFDD00 Error:# SDMMC Read!"); - ums->lun.sense_data = SS_UNRECOVERED_READ_ERROR; + ums->lun.sense_data = SS_UNRECOVERED_READ_ERROR; ums->lun.sense_data_info = lba_offset; - ums->lun.info_valid = 1; + ums->lun.info_valid = 1; break; } @@ -524,7 +525,7 @@ static int _scsi_read(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) break; // Start the USB transfer. - _ums_transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_START); + _transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_START); first_read = false; // Increment our buffer to read new data. @@ -581,8 +582,8 @@ static int _scsi_write(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) } // Carry out the file writes. - usb_lba_offset = lba_offset; - amount_left_to_req = ums->data_size_from_cmnd; + usb_lba_offset = lba_offset; + amount_left_to_req = ums->data_size_from_cmnd; amount_left_to_write = ums->data_size_from_cmnd; while (amount_left_to_write > 0) @@ -597,20 +598,20 @@ static int _scsi_write(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) if (usb_lba_offset >= ums->lun.num_sectors) { ums->set_text(ums->label, "#FFDD00 Error:# Write - Past last sector!"); - ums->lun.sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + ums->lun.sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ums->lun.sense_data_info = usb_lba_offset; - ums->lun.info_valid = 1; + ums->lun.info_valid = 1; break; } // Get the next buffer. - usb_lba_offset += amount >> UMS_DISK_LBA_SHIFT; + usb_lba_offset += amount >> UMS_DISK_LBA_SHIFT; ums->usb_amount_left -= amount; - amount_left_to_req -= amount; + amount_left_to_req -= amount; bulk_ctxt->bulk_out_length = amount; - _ums_transfer_out_big_read(ums, bulk_ctxt); + _transfer_out_big_read(ums, bulk_ctxt); } if (bulk_ctxt->bulk_out_buf_state == BUF_STATE_FULL) @@ -620,9 +621,10 @@ static int _scsi_write(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) // Did something go wrong with the transfer?. if (bulk_ctxt->bulk_out_status != 0) { - ums->lun.sense_data = SS_COMMUNICATION_FAILURE; + ums->lun.sense_data = SS_COMMUNICATION_FAILURE; ums->lun.sense_data_info = lba_offset; - ums->lun.info_valid = 1; + ums->lun.info_valid = 1; + s_printf(txt_buf, "#FFDD00 Error:# Write - Comm failure %d!", bulk_ctxt->bulk_out_status); ums->set_text(ums->label, txt_buf); break; @@ -662,9 +664,9 @@ DPRINTF("file write %X @ %X\n", amount, lba_offset); if (!amount) { ums->set_text(ums->label, "#FFDD00 Error:# SDMMC Write!"); - ums->lun.sense_data = SS_WRITE_ERROR; + ums->lun.sense_data = SS_WRITE_ERROR; ums->lun.sense_data_info = lba_offset; - ums->lun.info_valid = 1; + ums->lun.info_valid = 1; break; } @@ -714,9 +716,9 @@ static int _scsi_verify(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) amount = MIN(verification_length, USB_EP_BUFFER_MAX_SIZE >> UMS_DISK_LBA_SHIFT); amount = MIN(amount, ums->lun.num_sectors - lba_offset); if (amount == 0) { - ums->lun.sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; + ums->lun.sense_data = SS_LOGICAL_BLOCK_ADDRESS_OUT_OF_RANGE; ums->lun.sense_data_info = lba_offset; - ums->lun.info_valid = 1; + ums->lun.info_valid = 1; break; } @@ -728,9 +730,9 @@ DPRINTF("File read %X @ %X\n", amount, lba_offset); if (!amount) { ums->set_text(ums->label, "#FFDD00 Error:# File verify!"); - ums->lun.sense_data = SS_UNRECOVERED_READ_ERROR; + ums->lun.sense_data = SS_UNRECOVERED_READ_ERROR; ums->lun.sense_data_info = lba_offset; - ums->lun.info_valid = 1; + ums->lun.info_valid = 1; break; } lba_offset += amount; @@ -1092,8 +1094,7 @@ static int _scsi_prevent_allow_removal(usbd_gadget_ums_t *ums) // Notify for possible unmounting? // Normally we sync here but we do synced writes to SDMMC. - if (ums->lun.prevent_medium_removal && !prevent) - ; + if (ums->lun.prevent_medium_removal && !prevent) { /* Do nothing */ } ums->lun.prevent_medium_removal = prevent; @@ -1117,8 +1118,9 @@ static int _scsi_read_format_capacities(usbd_gadget_ums_t *ums, bulk_ctxt_t *bul // Check whether the command is properly formed and whether its data size // and direction agree with the values we already have. -static int _ums_check_scsi_cmd(usbd_gadget_ums_t *ums, u32 cmnd_size, - enum data_direction data_dir, u32 mask, int needs_medium) +static int _check_scsi_cmd(usbd_gadget_ums_t *ums, u32 cmnd_size, + enum data_direction data_dir, u32 mask, + int needs_medium) { //const char dirletter[4] = {'u', 'o', 'i', 'n'}; DPRINTF("SCSI command: %X; Dc=%d, D%c=%X; Hc=%d, H%c=%X\n", @@ -1166,9 +1168,9 @@ DPRINTF("SCSI command: %X; Dc=%d, D%c=%X; Hc=%d, H%c=%X\n", if (ums->cmnd[0] != SC_REQUEST_SENSE) { - ums->lun.sense_data = SS_NO_SENSE; + ums->lun.sense_data = SS_NO_SENSE; ums->lun.sense_data_info = 0; - ums->lun.info_valid = 0; + ums->lun.info_valid = 0; } // If a unit attention condition exists, only INQUIRY and REQUEST SENSE @@ -1205,7 +1207,7 @@ DPRINTF("SCSI command: %X; Dc=%d, D%c=%X; Hc=%d, H%c=%X\n", return UMS_RES_OK; } -static int _ums_parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) +static int _parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) { u32 len; int reply = UMS_RES_INVALID_ARG; @@ -1220,21 +1222,21 @@ static int _ums_parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) u32 mask = (1<<4); if (ums->cmnd[1] == 1 && ums->cmnd[2] == 0x80) // Inquiry S/N. mask = (1<<1) | (1<<2) | (1<<4); - reply = _ums_check_scsi_cmd(ums, 6, DATA_DIR_TO_HOST, mask, 0); + reply = _check_scsi_cmd(ums, 6, DATA_DIR_TO_HOST, mask, 0); if (reply == 0) reply = _scsi_inquiry(ums, bulk_ctxt); break; case SC_LOG_SENSE: ums->data_size_from_cmnd = get_array_be_to_le16(&ums->cmnd[7]); - reply = _ums_check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (1<<1) | (1<<2) | (3<<7), 0); + reply = _check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (1<<1) | (1<<2) | (3<<7), 0); if (reply == 0) reply = _scsi_log_sense(ums, bulk_ctxt); break; case SC_MODE_SELECT_6: ums->data_size_from_cmnd = ums->cmnd[4]; - reply = _ums_check_scsi_cmd(ums, 6, DATA_DIR_FROM_HOST, (1<<1) | (1<<4), 0); + reply = _check_scsi_cmd(ums, 6, DATA_DIR_FROM_HOST, (1<<1) | (1<<4), 0); if (reply == 0) { // We don't support MODE SELECT. @@ -1245,7 +1247,7 @@ static int _ums_parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) case SC_MODE_SELECT_10: ums->data_size_from_cmnd = get_array_be_to_le16(&ums->cmnd[7]); - reply = _ums_check_scsi_cmd(ums, 10, DATA_DIR_FROM_HOST, (1<<1) | (3<<7), 0); + reply = _check_scsi_cmd(ums, 10, DATA_DIR_FROM_HOST, (1<<1) | (3<<7), 0); if (reply == 0) { // We don't support MODE SELECT. @@ -1256,21 +1258,21 @@ static int _ums_parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) case SC_MODE_SENSE_6: ums->data_size_from_cmnd = ums->cmnd[4]; - reply = _ums_check_scsi_cmd(ums, 6, DATA_DIR_TO_HOST, (1<<1) | (1<<2) | (1<<4), 0); + reply = _check_scsi_cmd(ums, 6, DATA_DIR_TO_HOST, (1<<1) | (1<<2) | (1<<4), 0); if (reply == 0) reply = _scsi_mode_sense(ums, bulk_ctxt); break; case SC_MODE_SENSE_10: ums->data_size_from_cmnd = get_array_be_to_le16(&ums->cmnd[7]); - reply = _ums_check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (1<<1) | (1<<2) | (3<<7), 0); + reply = _check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (1<<1) | (1<<2) | (3<<7), 0); if (reply == 0) reply = _scsi_mode_sense(ums, bulk_ctxt); break; case SC_PREVENT_ALLOW_MEDIUM_REMOVAL: ums->data_size_from_cmnd = 0; - reply = _ums_check_scsi_cmd(ums, 6, DATA_DIR_NONE, (1<<4), 0); + reply = _check_scsi_cmd(ums, 6, DATA_DIR_NONE, (1<<4), 0); if (reply == 0) reply = _scsi_prevent_allow_removal(ums); break; @@ -1278,68 +1280,68 @@ static int _ums_parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) case SC_READ_6: len = ums->cmnd[4]; ums->data_size_from_cmnd = (len == 0 ? 256 : len) << UMS_DISK_LBA_SHIFT; - reply = _ums_check_scsi_cmd(ums, 6, DATA_DIR_TO_HOST, (7<<1) | (1<<4), 1); + reply = _check_scsi_cmd(ums, 6, DATA_DIR_TO_HOST, (7<<1) | (1<<4), 1); if (reply == 0) reply = _scsi_read(ums, bulk_ctxt); break; case SC_READ_10: ums->data_size_from_cmnd = get_array_be_to_le16(&ums->cmnd[7]) << UMS_DISK_LBA_SHIFT; - reply = _ums_check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (1<<1) | (0xf<<2) | (3<<7), 1); + reply = _check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (1<<1) | (0xf<<2) | (3<<7), 1); if (reply == 0) reply = _scsi_read(ums, bulk_ctxt); break; case SC_READ_12: ums->data_size_from_cmnd = get_array_be_to_le32(&ums->cmnd[6]) << UMS_DISK_LBA_SHIFT; - reply = _ums_check_scsi_cmd(ums, 12, DATA_DIR_TO_HOST, (1<<1) | (0xf<<2) | (0xf<<6), 1); + reply = _check_scsi_cmd(ums, 12, DATA_DIR_TO_HOST, (1<<1) | (0xf<<2) | (0xf<<6), 1); if (reply == 0) reply = _scsi_read(ums, bulk_ctxt); break; case SC_READ_CAPACITY: ums->data_size_from_cmnd = 8; - reply = _ums_check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (0xf<<2) | (1<<8), 1); + reply = _check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (0xf<<2) | (1<<8), 1); if (reply == 0) reply = _scsi_read_capacity(ums, bulk_ctxt); break; case SC_READ_FORMAT_CAPACITIES: ums->data_size_from_cmnd = get_array_be_to_le16(&ums->cmnd[7]); - reply = _ums_check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (3<<7), 1); + reply = _check_scsi_cmd(ums, 10, DATA_DIR_TO_HOST, (3<<7), 1); if (reply == 0) reply = _scsi_read_format_capacities(ums, bulk_ctxt); break; case SC_REQUEST_SENSE: ums->data_size_from_cmnd = ums->cmnd[4]; - reply = _ums_check_scsi_cmd(ums, 6, DATA_DIR_TO_HOST, (1<<4), 0); + reply = _check_scsi_cmd(ums, 6, DATA_DIR_TO_HOST, (1<<4), 0); if (reply == 0) reply = _scsi_request_sense(ums, bulk_ctxt); break; case SC_START_STOP_UNIT: ums->data_size_from_cmnd = 0; - reply = _ums_check_scsi_cmd(ums, 6, DATA_DIR_NONE, (1<<1) | (1<<4), 0); + reply = _check_scsi_cmd(ums, 6, DATA_DIR_NONE, (1<<1) | (1<<4), 0); if (reply == 0) reply = _scsi_start_stop(ums); break; case SC_SYNCHRONIZE_CACHE: ums->data_size_from_cmnd = 0; - reply = _ums_check_scsi_cmd(ums, 10, DATA_DIR_NONE, (0xf<<2) | (3<<7), 1); + reply = _check_scsi_cmd(ums, 10, DATA_DIR_NONE, (0xf<<2) | (3<<7), 1); if (reply == 0) reply = 0; // Don't bother break; case SC_TEST_UNIT_READY: ums->data_size_from_cmnd = 0; - reply = _ums_check_scsi_cmd(ums, 6, DATA_DIR_NONE, 0, 1); + reply = _check_scsi_cmd(ums, 6, DATA_DIR_NONE, 0, 1); break; // This command is used by Windows. We support a minimal version and BytChk must be 0. case SC_VERIFY: ums->data_size_from_cmnd = 0; - reply = _ums_check_scsi_cmd(ums, 10, DATA_DIR_NONE, (1<<1) | (0xf<<2) | (3<<7), 1); + reply = _check_scsi_cmd(ums, 10, DATA_DIR_NONE, (1<<1) | (0xf<<2) | (3<<7), 1); if (reply == 0) reply = _scsi_verify(ums, bulk_ctxt); break; @@ -1347,21 +1349,21 @@ static int _ums_parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) case SC_WRITE_6: len = ums->cmnd[4]; ums->data_size_from_cmnd = (len == 0 ? 256 : len) << UMS_DISK_LBA_SHIFT; - reply = _ums_check_scsi_cmd(ums, 6, DATA_DIR_FROM_HOST, (7<<1) | (1<<4), 1); + reply = _check_scsi_cmd(ums, 6, DATA_DIR_FROM_HOST, (7<<1) | (1<<4), 1); if (reply == 0) reply = _scsi_write(ums, bulk_ctxt); break; case SC_WRITE_10: ums->data_size_from_cmnd = get_array_be_to_le16(&ums->cmnd[7]) << UMS_DISK_LBA_SHIFT; - reply = _ums_check_scsi_cmd(ums, 10, DATA_DIR_FROM_HOST, (1<<1) | (0xf<<2) | (3<<7), 1); + reply = _check_scsi_cmd(ums, 10, DATA_DIR_FROM_HOST, (1<<1) | (0xf<<2) | (3<<7), 1); if (reply == 0) reply = _scsi_write(ums, bulk_ctxt); break; case SC_WRITE_12: ums->data_size_from_cmnd = get_array_be_to_le32(&ums->cmnd[6]) << UMS_DISK_LBA_SHIFT; - reply = _ums_check_scsi_cmd(ums, 12, DATA_DIR_FROM_HOST, (1<<1) | (0xf<<2) | (0xf<<6), 1); + reply = _check_scsi_cmd(ums, 12, DATA_DIR_FROM_HOST, (1<<1) | (0xf<<2) | (0xf<<6), 1); if (reply == 0) reply = _scsi_write(ums, bulk_ctxt); break; @@ -1375,7 +1377,7 @@ static int _ums_parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) case SC_SEND_DIAGNOSTIC: default: ums->data_size_from_cmnd = 0; - reply = _ums_check_scsi_cmd(ums, ums->cmnd_size, DATA_DIR_UNKNOWN, 0xFF, 0); + reply = _check_scsi_cmd(ums, ums->cmnd_size, DATA_DIR_UNKNOWN, 0xFF, 0); if (reply == 0) { ums->lun.sense_data = SS_INVALID_COMMAND; @@ -1387,7 +1389,7 @@ static int _ums_parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) if (reply == UMS_RES_INVALID_ARG) reply = 0; // Error reply length. - // Set up reply buffer for finish_reply(). Otherwise it's already set. + // Set up reply buffer for _finish_reply(). Otherwise it's already set. if (reply >= 0 && ums->data_dir == DATA_DIR_TO_HOST) { reply = MIN((u32)reply, ums->data_size_from_cmnd); @@ -1399,7 +1401,7 @@ static int _ums_parse_scsi_cmd(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) return UMS_RES_OK; } -static int pad_with_zeros(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) +static int _pad_with_zeros(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) { bulk_ctxt->bulk_in_buf_state = BUF_STATE_EMPTY; // For the first iteration. u32 current_len_to_keep = bulk_ctxt->bulk_in_length; @@ -1410,7 +1412,7 @@ static int pad_with_zeros(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) u32 nsend = MIN(ums->usb_amount_left, USB_EP_BUFFER_MAX_SIZE); memset(bulk_ctxt->bulk_in_buf + current_len_to_keep, 0, nsend - current_len_to_keep); bulk_ctxt->bulk_in_length = nsend; - _ums_transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED_DATA); + _transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED_DATA); ums->usb_amount_left -= nsend; current_len_to_keep = 0; } @@ -1418,7 +1420,7 @@ static int pad_with_zeros(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) return UMS_RES_OK; } -static int throw_away_data(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) +static int _throw_away_data(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) { if (bulk_ctxt->bulk_out_buf_state != BUF_STATE_EMPTY || ums->usb_amount_left > 0) { @@ -1428,7 +1430,7 @@ static int throw_away_data(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) u32 amount = MIN(ums->usb_amount_left, USB_EP_BUFFER_MAX_SIZE); bulk_ctxt->bulk_out_length = amount; - _ums_transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_out, USB_XFER_SYNCED_DATA); + _transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_out, USB_XFER_SYNCED_DATA); ums->usb_amount_left -= amount; return UMS_RES_OK; @@ -1449,7 +1451,7 @@ static int throw_away_data(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) return UMS_RES_OK; } -static int finish_reply(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) +static int _finish_reply(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) { int rc = UMS_RES_OK; @@ -1462,8 +1464,8 @@ static int finish_reply(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) case DATA_DIR_UNKNOWN: if (ums->can_stall) { - ums_set_stall(bulk_ctxt->bulk_out); - rc = ums_set_stall(bulk_ctxt->bulk_in); + _set_ep_stall(bulk_ctxt->bulk_out); + rc = _set_ep_stall(bulk_ctxt->bulk_in); ums->set_text(ums->label, "#FFDD00 Error:# Direction unknown. Stalled both EP!"); } // Else do nothing. break; @@ -1475,7 +1477,7 @@ static int finish_reply(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) // If there's no residue, simply send the last buffer. if (!ums->residue) { - _ums_transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED_DATA); + _transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED_DATA); /* For Bulk-only, if we're allowed to stall then send the * short packet and halt the bulk-in endpoint. If we can't @@ -1483,16 +1485,16 @@ static int finish_reply(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) } else if (ums->can_stall) { - _ums_transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED_DATA); - rc = ums_set_stall(bulk_ctxt->bulk_in); + _transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED_DATA); + rc = _set_ep_stall(bulk_ctxt->bulk_in); ums->set_text(ums->label, "#FFDD00 Error:# Residue. Stalled EP IN!"); } else - rc = pad_with_zeros(ums, bulk_ctxt); + rc = _pad_with_zeros(ums, bulk_ctxt); } // In case we used SDMMC transfer, reset the buffer address. - _ums_reset_buffer(bulk_ctxt, bulk_ctxt->bulk_in); + _reset_buffer(bulk_ctxt, bulk_ctxt->bulk_in); break; // We have processed all we want from the data the host has sent. @@ -1506,7 +1508,7 @@ static int finish_reply(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) rc = UMS_RES_PROT_FATAL; } else // We can't stall. Read in the excess data and throw it away. - rc = throw_away_data(ums, bulk_ctxt); + rc = _throw_away_data(ums, bulk_ctxt); } break; @@ -1541,7 +1543,7 @@ static int finish_reply(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) * Line always at SE0. */ -static int received_cbw(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) +static int _received_cbw(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) { // Was this a real packet? Should it be ignored? if (bulk_ctxt->bulk_out_status || bulk_ctxt->bulk_out_ignore || ums->lun.unmounted) @@ -1611,7 +1613,7 @@ static int received_cbw(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) * we can simply accept and discard any data received * until the next reset. */ - ums_wedge_bulk_in_endpoint(ums); + _wedge_bulk_in_endpoint(ums); bulk_ctxt->bulk_out_ignore = 1; return UMS_RES_INVALID_ARG; } @@ -1627,8 +1629,8 @@ static int received_cbw(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) * bulk pipes if we are allowed to. */ if (ums->can_stall) { - ums_set_stall(bulk_ctxt->bulk_out); - ums_set_stall(bulk_ctxt->bulk_in); + _set_ep_stall(bulk_ctxt->bulk_out); + _set_ep_stall(bulk_ctxt->bulk_in); ums->set_text(ums->label, "#FFDD00 Error:# CBW unknown - Stalled both EP!"); } @@ -1658,7 +1660,7 @@ static int received_cbw(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) return UMS_RES_OK; } -static int get_next_command(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) +static int _get_next_command(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) { int rc = UMS_RES_OK; @@ -1672,9 +1674,9 @@ static int get_next_command(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) // Queue a request to read a Bulk-only CBW. if (!ums->cbw_req_queued) - _ums_transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_out, USB_XFER_SYNCED_CMD); + _transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_out, USB_XFER_SYNCED_CMD); else - _ums_transfer_finish(ums, bulk_ctxt, bulk_ctxt->bulk_out, USB_XFER_SYNCED_CMD); + _transfer_finish(ums, bulk_ctxt, bulk_ctxt->bulk_out, USB_XFER_SYNCED_CMD); /* * On XUSB do not allow multiple requests for CBW to be done. @@ -1695,13 +1697,13 @@ static int get_next_command(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) // //wait irq. // } - rc = received_cbw(ums, bulk_ctxt); + rc = _received_cbw(ums, bulk_ctxt); bulk_ctxt->bulk_out_buf_state = BUF_STATE_EMPTY; return rc; } -static void send_status(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) +static void _send_status(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) { u8 status = USB_STATUS_PASS; u32 sd = ums->lun.sense_data; @@ -1724,26 +1726,26 @@ static void send_status(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) bulk_send_pkt_t *csw = (bulk_send_pkt_t *)bulk_ctxt->bulk_in_buf; csw->Signature = USB_BULK_CS_SIG; - csw->Tag = ums->tag; - csw->Residue = ums->residue; - csw->Status = status; + csw->Tag = ums->tag; + csw->Residue = ums->residue; + csw->Status = status; bulk_ctxt->bulk_in_length = USB_BULK_CS_WRAP_LEN; - _ums_transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED_CMD); + _transfer_start(ums, bulk_ctxt, bulk_ctxt->bulk_in, USB_XFER_SYNCED_CMD); } -static void handle_exception(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) +static void _handle_exception(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) { enum ums_state old_state; // Clear out the controller's fifos. - ums_flush_endpoint(bulk_ctxt->bulk_in); - ums_flush_endpoint(bulk_ctxt->bulk_out); + _flush_endpoint(bulk_ctxt->bulk_in); + _flush_endpoint(bulk_ctxt->bulk_out); /* Reset the I/O buffer states and pointers, the SCSI * state, and the exception. Then invoke the handler. */ - bulk_ctxt->bulk_in_buf_state = BUF_STATE_EMPTY; + bulk_ctxt->bulk_in_buf_state = BUF_STATE_EMPTY; bulk_ctxt->bulk_out_buf_state = BUF_STATE_EMPTY; old_state = ums->state; @@ -1751,10 +1753,10 @@ static void handle_exception(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) if (old_state != UMS_STATE_ABORT_BULK_OUT) { ums->lun.prevent_medium_removal = 0; - ums->lun.sense_data = SS_NO_SENSE; - ums->lun.unit_attention_data = SS_NO_SENSE; - ums->lun.sense_data_info = 0; - ums->lun.info_valid = 0; + ums->lun.sense_data = SS_NO_SENSE; + ums->lun.unit_attention_data = SS_NO_SENSE; + ums->lun.sense_data_info = 0; + ums->lun.info_valid = 0; } ums->state = UMS_STATE_NORMAL; @@ -1765,7 +1767,7 @@ static void handle_exception(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) case UMS_STATE_NORMAL: break; case UMS_STATE_ABORT_BULK_OUT: - send_status(ums, bulk_ctxt); + _send_status(ums, bulk_ctxt); break; case UMS_STATE_PROTOCOL_RESET: @@ -1775,7 +1777,7 @@ static void handle_exception(usbd_gadget_ums_t *ums, bulk_ctxt_t *bulk_ctxt) if (bulk_ctxt->bulk_out_ignore) { bulk_ctxt->bulk_out_ignore = 0; - ums_clear_stall(bulk_ctxt->bulk_in); + _clear_ep_stall(bulk_ctxt->bulk_in); } ums->lun.unit_attention_data = SS_RESET_OCCURRED; break; @@ -1811,8 +1813,6 @@ static inline void _system_maintainance(usbd_gadget_ums_t *ums) int usb_device_gadget_ums(usb_ctxt_t *usbs) { int res = 0; - sdmmc_t sdmmc; - sdmmc_storage_t storage; usbd_gadget_ums_t ums = {0}; // Get USB Controller ops. @@ -1835,17 +1835,18 @@ int usb_device_gadget_ums(usb_ctxt_t *usbs) ums.state = UMS_STATE_NORMAL; ums.can_stall = 0; - ums.bulk_ctxt.bulk_in = USB_EP_BULK_IN; + ums.bulk_ctxt.bulk_in = USB_EP_BULK_IN; ums.bulk_ctxt.bulk_in_buf = (u8 *)USB_EP_BULK_IN_BUF_ADDR; - ums.bulk_ctxt.bulk_out = USB_EP_BULK_OUT; + ums.bulk_ctxt.bulk_out = USB_EP_BULK_OUT; ums.bulk_ctxt.bulk_out_buf = (u8 *)USB_EP_BULK_OUT_BUF_ADDR; // Set LUN parameters. - ums.lun.ro = usbs->ro; - ums.lun.type = usbs->type; - ums.lun.partition = usbs->partition; - ums.lun.offset = usbs->offset; + ums.lun.ro = usbs->ro; + ums.lun.type = usbs->type; + ums.lun.partition = usbs->partition; + ums.lun.num_sectors = usbs->sectors; + ums.lun.offset = usbs->offset; ums.lun.removable = 1; // Always removable to force OSes to use prevent media removal. ums.lun.unit_attention_data = SS_RESET_OCCURRED; @@ -1860,36 +1861,52 @@ int usb_device_gadget_ums(usb_ctxt_t *usbs) if (usbs->type == MMC_SD) { sd_end(); - sd_mount(); + if (!sd_mount()) + { + ums.set_text(ums.label, "#FFDD00 Failed to init SD!#"); + res = 1; + goto init_fail; + } sd_unmount(); - ums.lun.sdmmc = &sd_sdmmc; + + ums.lun.sdmmc = &sd_sdmmc; ums.lun.storage = &sd_storage; } else { - ums.lun.sdmmc = &sdmmc; - ums.lun.storage = &storage; - sdmmc_storage_init_mmc(ums.lun.storage, ums.lun.sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400); - sdmmc_storage_set_mmc_partition(ums.lun.storage, ums.lun.partition - 1); + if (!emmc_initialize(false)) + { + ums.set_text(ums.label, "#FFDD00 Failed to init eMMC!#"); + res = 1; + goto init_fail; + } + emmc_set_partition(ums.lun.partition - 1); + + ums.lun.sdmmc = &emmc_sdmmc; + ums.lun.storage = &emmc_storage; } ums.set_text(ums.label, "#C7EA46 Status:# Waiting for connection"); // Initialize Control Endpoint. if (usb_ops.usb_device_enumerate(USB_GADGET_UMS)) - goto error; + goto usb_enum_error; ums.set_text(ums.label, "#C7EA46 Status:# Waiting for LUN"); if (usb_ops.usb_device_class_send_max_lun(0)) // One device for now. - goto error; + goto usb_enum_error; ums.set_text(ums.label, "#C7EA46 Status:# Started UMS"); - if (usbs->sectors) - ums.lun.num_sectors = usbs->sectors; - else - ums.lun.num_sectors = ums.lun.storage->sec_cnt; + // If partition sectors are not set get them from hardware. + if (!ums.lun.num_sectors) + { + if (usbs->type == MMC_EMMC && (ums.lun.partition - 1)) // eMMC BOOT0/1. + ums.lun.num_sectors = emmc_storage.ext_csd.boot_mult << 8; + else + ums.lun.num_sectors = ums.lun.storage->sec_cnt; // eMMC GPP or SD. + } do { @@ -1908,26 +1925,28 @@ int usb_device_gadget_ums(usb_ctxt_t *usbs) if (ums.state != UMS_STATE_NORMAL) { - handle_exception(&ums, &ums.bulk_ctxt); + _handle_exception(&ums, &ums.bulk_ctxt); continue; } - ums_handle_ep0_ctrl(&ums); + _handle_ep0_ctrl(&ums); - if (get_next_command(&ums, &ums.bulk_ctxt) || (ums.state > UMS_STATE_NORMAL)) + if (_get_next_command(&ums, &ums.bulk_ctxt) || (ums.state > UMS_STATE_NORMAL)) continue; - ums_handle_ep0_ctrl(&ums); + _handle_ep0_ctrl(&ums); - if (_ums_parse_scsi_cmd(&ums, &ums.bulk_ctxt) || (ums.state > UMS_STATE_NORMAL)) + _parse_scsi_cmd(&ums, &ums.bulk_ctxt); + + if (ums.state > UMS_STATE_NORMAL) continue; - ums_handle_ep0_ctrl(&ums); + _handle_ep0_ctrl(&ums); - if (finish_reply(&ums, &ums.bulk_ctxt) || (ums.state > UMS_STATE_NORMAL)) + if (_finish_reply(&ums, &ums.bulk_ctxt) || (ums.state > UMS_STATE_NORMAL)) continue; - send_status(&ums, &ums.bulk_ctxt); + _send_status(&ums, &ums.bulk_ctxt); } while (ums.state != UMS_STATE_TERMINATED); if (ums.lun.prevent_medium_removal) @@ -1936,14 +1955,15 @@ int usb_device_gadget_ums(usb_ctxt_t *usbs) ums.set_text(ums.label, "#C7EA46 Status:# Disk ejected"); goto exit; -error: +usb_enum_error: ums.set_text(ums.label, "#FFDD00 Error:# Timed out or canceled!"); res = 1; exit: if (ums.lun.type == MMC_EMMC) - sdmmc_storage_end(ums.lun.storage); + emmc_end(); +init_fail: usb_ops.usbd_end(true, false); return res; diff --git a/bdk/usb/usbd.c b/bdk/usb/usbd.c index 81d719a..2a7fe97 100644 --- a/bdk/usb/usbd.c +++ b/bdk/usb/usbd.c @@ -1,7 +1,7 @@ /* * Enhanced USB Device (EDCI) driver for Tegra X1 * - * Copyright (c) 2019-2021 CTCaer + * Copyright (c) 2019-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -30,16 +30,16 @@ #include #include #include +#include #include #include -#include #include typedef enum { - USB_HW_EP0 = 0, - USB_HW_EP1 = 1 + USB_HW_EP0 = 0, + USB_HW_EP1 = 1 } usb_hw_ep_t; typedef enum @@ -143,11 +143,11 @@ static int _usbd_reset_usb_otg_phy_device_mode() // Clear all device addresses, enabled setup requests and transmit events. usbd_otg->regs->periodiclistbase = 0; - usbd_otg->regs->endptsetupstat = usbd_otg->regs->endptsetupstat; - usbd_otg->regs->endptcomplete = usbd_otg->regs->endptcomplete; + usbd_otg->regs->endptsetupstat = usbd_otg->regs->endptsetupstat; + usbd_otg->regs->endptcomplete = usbd_otg->regs->endptcomplete; // Stop device controller. - usbd_otg->regs->usbcmd &= ~USB2D_USBCMD_RUN; + usbd_otg->regs->usbcmd &= ~USB2D_USBCMD_RUN; // Set controller mode to idle. usbd_otg->regs->usbmode &= ~USB2D_USBMODE_CM_MASK; @@ -192,16 +192,15 @@ static int _usbd_reset_usb_otg_phy_device_mode() usbd_otg->regs->usbintr = 0; // Set the ID pullup and disable all OTGSC interrupts. - usbd_otg->regs->otgsc = USB2D_OTGSC_USB_ID_PULLUP; + usbd_otg->regs->otgsc = USB2D_OTGSC_USB_ID_PULLUP; // Clear all relevant interrupt statuses. - usbd_otg->regs->usbsts = - USB2D_USBSTS_UI | USB2D_USBSTS_UEI | USB2D_USBSTS_PCI | - USB2D_USBSTS_FRI | USB2D_USBSTS_SEI | USB2D_USBSTS_AAI | - USB2D_USBSTS_URI | USB2D_USBSTS_SRI | USB2D_USBSTS_SLI; + usbd_otg->regs->usbsts = USB2D_USBSTS_UI | USB2D_USBSTS_UEI | USB2D_USBSTS_PCI | + USB2D_USBSTS_FRI | USB2D_USBSTS_SEI | USB2D_USBSTS_AAI | + USB2D_USBSTS_URI | USB2D_USBSTS_SRI | USB2D_USBSTS_SLI; // Disable and clear all OTGSC interrupts. - usbd_otg->regs->otgsc = USB2D_OTGSC_USB_IRQ_STS_MASK; + usbd_otg->regs->otgsc = USB2D_OTGSC_USB_IRQ_STS_MASK; // Clear EP0, EP1, EP2 setup requests. usbd_otg->regs->endptsetupstat = 7; //TODO: Shouldn't this be endptsetupstat = endptsetupstat? @@ -222,11 +221,10 @@ static void _usb_charger_detect() usbd_otg->charger_detect |= 1; // Configure detect pin. PINMUX_AUX(PINMUX_AUX_LCD_GPIO1) &= ~(PINMUX_PARKED | PINMUX_TRISTATE | PINMUX_PULL_MASK); - gpio_config(GPIO_PORT_V, GPIO_PIN_3, GPIO_MODE_GPIO); + gpio_direction_input(GPIO_PORT_V, GPIO_PIN_3); // Configure charger pin. - PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN1) &= - ~(PINMUX_INPUT_ENABLE | PINMUX_PARKED | PINMUX_TRISTATE | PINMUX_PULL_MASK); + PINMUX_AUX(PINMUX_AUX_USB_VBUS_EN1) &= ~(PINMUX_INPUT_ENABLE | PINMUX_PARKED | PINMUX_TRISTATE | PINMUX_PULL_MASK); gpio_config(GPIO_PORT_CC, GPIO_PIN_5, GPIO_MODE_GPIO); gpio_output_enable(GPIO_PORT_CC, GPIO_PIN_5, GPIO_OUTPUT_ENABLE); @@ -289,12 +287,12 @@ static void _usb_init_phy() // Configure misc UTMIP. USB(USB1_UTMIP_DEBOUNCE_CFG0) = (USB(USB1_UTMIP_DEBOUNCE_CFG0) & 0xFFFF0000) | 0xBB80; - USB(USB1_UTMIP_BIAS_CFG1) = (USB(USB1_UTMIP_BIAS_CFG1) & 0xFFFFC0FF) | 0x100; // when osc is 38.4KHz + USB(USB1_UTMIP_BIAS_CFG1) = (USB(USB1_UTMIP_BIAS_CFG1) & 0xFFFFC0FF) | 0x100; // when osc is 38.4KHz //USB(USB1_UTMIP_SPARE_CFG0) &= 0xFFFFFEE7; unpatched0 - USB(USB1_UTMIP_BIAS_CFG2) |= 2; //patched0 - UTMIP_HSSQUELCH_LEVEL_NEW: 2. + USB(USB1_UTMIP_BIAS_CFG2) |= 2; //patched0 - UTMIP_HSSQUELCH_LEVEL_NEW: 2. USB(USB1_UTMIP_SPARE_CFG0) &= 0xFFFFFE67; //patched0 - FUSE_HS_IREF_CAP_CFG - USB(USB1_UTMIP_TX_CFG0) |= 0x80000; + USB(USB1_UTMIP_TX_CFG0) |= 0x80000; //USB(USB1_UTMIP_HSRX_CFG0) = (USB(USB1_UTMIP_HSRX_CFG0) & 0xFFF003FF) | 0x88000 | 0x4000; unpatched1 USB(USB1_UTMIP_HSRX_CFG0) = (USB(USB1_UTMIP_HSRX_CFG0) & 0xF0F003FF) | 0x88000 | 0x4000; //patched1 - reset UTMIP_PCOUNT_UPDN_DIV: From 1 to 0. @@ -307,7 +305,7 @@ static void _usb_init_phy() CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) |= 0x40000000; // Enable USB2 tracking clock. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_Y_SET) = BIT(CLK_Y_USB2_TRK); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_Y_SET) = BIT(CLK_Y_USB2_TRK); CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK) & 0xFFFFFF00) | 6; // Set trank divisor to 4. USB(USB1_UTMIP_BIAS_CFG1) = (USB(USB1_UTMIP_BIAS_CFG1) & 0xFFC03F07) | 0x78000 | 0x50; // Set delays. @@ -338,7 +336,7 @@ static void _usb_init_phy() usleep(1); // Clear power downs on UTMIP ID and VBUS wake up, PD, PD2, PDZI, PDCHRP, PDDR. - PMC(APBDEV_PMC_USB_AO) &= 0xFFFFFFF3; // UTMIP ID and VBUS wake up. + PMC(APBDEV_PMC_USB_AO) &= 0xFFFFFFF3; // UTMIP ID and VBUS wake up. usleep(1); USB(USB1_UTMIP_XCVR_CFG0) &= 0xFFFFBFFF; // UTMIP_FORCE_PD_POWERDOWN. usleep(1); @@ -357,19 +355,25 @@ int usb_device_init() if (usb_init_done) return USB_RES_OK; + // Ease the stress to APB. + bpmp_clk_rate_relaxed(true); + // Initialize USB2 controller PHY. _usb_init_phy(); + // Restore OC. + bpmp_clk_rate_relaxed(false); + // AHB USB performance cfg. AHB_GIZMO(AHB_GIZMO_AHB_MEM) |= AHB_MEM_DONT_SPLIT_AHB_WR | AHB_MEM_ENB_FAST_REARBITRATE; - AHB_GIZMO(AHB_GIZMO_USB) |= AHB_GIZMO_IMMEDIATE; + AHB_GIZMO(AHB_GIZMO_USB) |= AHB_GIZMO_IMMEDIATE; AHB_GIZMO(AHB_ARBITRATION_PRIORITY_CTRL) = PRIORITY_CTRL_WEIGHT(7) | PRIORITY_SELECT_USB; - AHB_GIZMO(AHB_AHB_MEM_PREFETCH_CFG1) = - MEM_PREFETCH_ENABLE | MEM_PREFETCH_USB_MST_ID | MEM_PREFETCH_ADDR_BNDRY(12) | 0x1000; // Addr boundary 64KB, Inactivity 4096 cycles. + AHB_GIZMO(AHB_AHB_MEM_PREFETCH_CFG1) = MEM_PREFETCH_ENABLE | MEM_PREFETCH_USB_MST_ID | + MEM_PREFETCH_ADDR_BNDRY(12) | 0x1000; // Addr boundary 64KB, Inactivity 4096 cycles. // Set software and hardware context storage and clear it. usbdaemon = (usbd_t *)USBD_ADDR; // Depends on USB_TD_BUFFER_PAGE_SIZE aligned address. - usbd_otg = &usbd_usb_otg_controller_ctxt; + usbd_otg = &usbd_usb_otg_controller_ctxt; memset(usbd_otg, 0, sizeof(usbd_controller_t)); memset(usbdaemon, 0, sizeof(usbd_t)); @@ -443,6 +447,11 @@ static void _usb_device_power_down() usb_init_done = false; } +static void _usbd_disable_ep1() +{ + usbd_otg->regs->endptctrl[1] = 0; +} + static void _usbd_stall_reset_ep1(usb_dir_t direction, usb_ep_cfg_t stall) { stall &= 1; @@ -524,13 +533,11 @@ static void _usbd_initialize_ep_ctrl(u32 endpoint) { u32 endpoint_type = usbd_otg->regs->endptctrl[actual_ep] & ~USB2D_ENDPTCTRL_RX_EP_TYPE_MASK; if (actual_ep) - { endpoint_type |= usbd_otg->gadget ? USB2D_ENDPTCTRL_RX_EP_TYPE_INTR : USB2D_ENDPTCTRL_RX_EP_TYPE_BULK; - } else endpoint_type |= USB2D_ENDPTCTRL_RX_EP_TYPE_CTRL; - usbd_otg->regs->endptctrl[actual_ep] = endpoint_type; + usbd_otg->regs->endptctrl[actual_ep] = endpoint_type; usbd_otg->regs->endptctrl[actual_ep] &= ~USB2D_ENDPTCTRL_RX_EP_STALL; if (actual_ep == USB_HW_EP1) @@ -542,7 +549,7 @@ static void _usbd_initialize_ep_ctrl(u32 endpoint) static int _usbd_initialize_ep0() { - memset((void *)usbdaemon->qhs, 0, sizeof(dQH_t) * 4); // Clear all used EP queue heads. + memset((void *)usbdaemon->qhs, 0, sizeof(dQH_t) * 4); // Clear all used EP queue heads. memset((void *)usbdaemon->dtds, 0, sizeof(dTD_t) * 4); // Clear all used EP0 token heads. usbd_otg->regs->asynclistaddr = (u32)usbdaemon->qhs; @@ -583,8 +590,8 @@ int usbd_flush_endpoint(u32 endpoint) { usb_hw_ep_t actual_ep = (endpoint & 2) >> 1; - usb_dir_t direction = endpoint & 1; - u32 reg_mask = endpoint; + usb_dir_t direction = endpoint & 1; + u32 reg_mask = endpoint; // Flash all endpoints or 1. if (endpoint != USB_EP_ALL) @@ -628,19 +635,23 @@ int usbd_flush_endpoint(u32 endpoint) return USB_RES_OK; } +static void _usb_reset_disable_ep1() +{ + usbd_flush_endpoint(USB_EP_ALL); + _usbd_stall_reset_ep1(USB_DIR_OUT, USB_EP_CFG_RESET); // EP1 Bulk OUT. + _usbd_stall_reset_ep1(USB_DIR_IN, USB_EP_CFG_RESET); // EP1 Bulk IN. + _usbd_disable_ep1(); + + usbd_otg->config_num = 0; + usbd_otg->interface_num = 0; + usbd_otg->configuration_set = false; + usbd_otg->max_lun_set = false; +} + void usbd_end(bool reset_ep, bool only_controller) { if (reset_ep) - { - usbd_flush_endpoint(USB_EP_ALL); - _usbd_stall_reset_ep1(USB_DIR_OUT, USB_EP_CFG_RESET); // EP1 Bulk OUT. - _usbd_stall_reset_ep1(USB_DIR_IN, USB_EP_CFG_RESET); // EP1 Bulk IN. - - usbd_otg->config_num = 0; - usbd_otg->interface_num = 0; - usbd_otg->configuration_set = false; - usbd_otg->max_lun_set = false; - } + _usb_reset_disable_ep1(); // Stop device controller. usbd_otg->regs->usbcmd &= ~USB2D_USBCMD_RUN; @@ -659,9 +670,11 @@ static void _usbd_mark_ep_complete(u32 endpoint) usb_dir_t direction = endpoint & 1; usbd_flush_endpoint(endpoint); + memset((void *)&usbdaemon->dtds[endpoint * 4], 0, sizeof(dTD_t) * 4); - memset((void *)&usbdaemon->qhs[endpoint], 0, sizeof(dQH_t)); - usbdaemon->ep_configured[endpoint] = 0; + memset((void *)&usbdaemon->qhs[endpoint], 0, sizeof(dQH_t)); + + usbdaemon->ep_configured[endpoint] = 0; usbdaemon->ep_bytes_requested[endpoint] = 0; if (direction == USB_DIR_IN) @@ -762,7 +775,7 @@ static int _usbd_ep_operation(usb_ep_t endpoint, u8 *buf, u32 len, u32 sync_time // Set buffers addresses to all page pointers. u32 dt_buffer_offset = dtd_idx * USB_TD_BUFFER_MAX_SIZE; for (u32 i = 0; i < 4; i++) - usbdaemon->dtds[dtd_ep_idx + dtd_idx].pages[i] = + usbdaemon->dtds[dtd_ep_idx + dtd_idx].pages[i] = !buf ? 0 : (u32)&buf[dt_buffer_offset + (USB_TD_BUFFER_PAGE_SIZE * i)]; //usbdaemon->dtds[dtd_ep_idx + dtd_idx].pages[5] = @@ -785,13 +798,13 @@ static int _usbd_ep_operation(usb_ep_t endpoint, u8 *buf, u32 len, u32 sync_time AHB_GIZMO(AHB_AHB_MEM_PREFETCH_CFG1) |= MEM_PREFETCH_ENABLE; if (direction == USB_DIR_IN) - { prime_bit = USB2D_ENDPT_STATUS_TX_OFFSET << actual_ep; - bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false); - } else prime_bit = USB2D_ENDPT_STATUS_RX_OFFSET << actual_ep; + // Flush data before priming EP. + bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLEAN_WAY, false); + // Prime endpoint. usbd_otg->regs->endptprime |= prime_bit; // USB2_CONTROLLER_USB2D_ENDPTPRIME. @@ -825,8 +838,9 @@ out: else if (_usbd_get_ep_status(endpoint) != USB_EP_STATUS_IDLE) res = USB_ERROR_XFER_ERROR; + // Invalidate data after OP is done. if (direction == USB_DIR_OUT) - bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false); + bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, false); } return res; @@ -840,9 +854,8 @@ static int _usbd_ep_ack(usb_ep_t ep) static void _usbd_set_ep0_stall() { // EP Control endpoints must be always stalled together. - usbd_otg->regs->endptctrl[0] = - USB2D_ENDPTCTRL_TX_EP_ENABLE | USB2D_ENDPTCTRL_TX_EP_STALL | - USB2D_ENDPTCTRL_RX_EP_ENABLE | USB2D_ENDPTCTRL_RX_EP_STALL; + usbd_otg->regs->endptctrl[0] = USB2D_ENDPTCTRL_TX_EP_ENABLE | USB2D_ENDPTCTRL_TX_EP_STALL | + USB2D_ENDPTCTRL_RX_EP_ENABLE | USB2D_ENDPTCTRL_RX_EP_STALL; } int usbd_set_ep_stall(u32 endpoint, int ep_stall) @@ -1046,6 +1059,16 @@ static int _usbd_handle_set_request(bool *ep_stall) if (!res) { usbd_otg->config_num = usbd_otg->control_setup.wValue; + + // Remove configuration. + if (!usbd_otg->config_num) + { + //! TODO: Signal that to userspace. + _usb_reset_disable_ep1(); + return res; + } + + // Initialize configuration. _usbd_initialize_ep_ctrl(USB_EP_BULK_OUT); _usbd_initialize_ep_ctrl(USB_EP_BULK_IN); usbd_otg->configuration_set = true; @@ -1321,8 +1344,8 @@ static int _usbd_ep0_initialize() // Clear all device addresses, enabled setup requests, transmit events and flush all endpoints. usbd_otg->regs->periodiclistbase = 0; - usbd_otg->regs->endptsetupstat = usbd_otg->regs->endptsetupstat; - usbd_otg->regs->endptcomplete = usbd_otg->regs->endptcomplete; + usbd_otg->regs->endptsetupstat = usbd_otg->regs->endptsetupstat; + usbd_otg->regs->endptcomplete = usbd_otg->regs->endptcomplete; usbd_flush_endpoint(USB_EP_ALL); } @@ -1470,7 +1493,7 @@ int usb_device_ep1_out_reading_finish(u32 *pending_bytes, u32 sync_timeout) *pending_bytes = _usbd_get_ep1_out_bytes_read(); - bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false); + bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, false); if (ep_status == USB_EP_STATUS_IDLE) return USB_RES_OK; diff --git a/bdk/usb/xusbd.c b/bdk/usb/xusbd.c index 0f68ec7..87df551 100644 --- a/bdk/usb/xusbd.c +++ b/bdk/usb/xusbd.c @@ -1,7 +1,7 @@ /* * eXtensible USB Device driver (XDCI) for Tegra X1 * - * Copyright (c) 2020-2021 CTCaer + * Copyright (c) 2020-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -28,9 +28,9 @@ #include #include #include +#include #include #include -#include #include @@ -397,9 +397,9 @@ typedef struct _xusbd_event_queues_t { event_trb_t xusb_event_ring_seg0[XUSB_TRB_SLOTS]; event_trb_t xusb_event_ring_seg1[XUSB_TRB_SLOTS]; - data_trb_t xusb_cntrl_event_queue[XUSB_TRB_SLOTS]; - data_trb_t xusb_bulkin_event_queue[XUSB_TRB_SLOTS]; - data_trb_t xusb_bulkout_event_queue[XUSB_TRB_SLOTS]; + data_trb_t xusb_cntrl_event_queue[XUSB_TRB_SLOTS]; + data_trb_t xusb_bulkin_event_queue[XUSB_TRB_SLOTS]; + data_trb_t xusb_bulkout_event_queue[XUSB_TRB_SLOTS]; volatile xusb_ep_ctx_t xusb_ep_ctxt[4]; } xusbd_event_queues_t; @@ -676,8 +676,8 @@ static int _xusb_ep_init_context(u32 ep_idx) { case XUSB_EP_CTRL_IN: usbd_xotg->cntrl_producer_cycle = 1; - usbd_xotg->cntrl_epenqueue_ptr = xusb_evtq->xusb_cntrl_event_queue; - usbd_xotg->cntrl_epdequeue_ptr = xusb_evtq->xusb_cntrl_event_queue; + usbd_xotg->cntrl_epenqueue_ptr = xusb_evtq->xusb_cntrl_event_queue; + usbd_xotg->cntrl_epdequeue_ptr = xusb_evtq->xusb_cntrl_event_queue; _xusb_ep_set_type_and_metrics(ep_idx, ep_ctxt); @@ -685,16 +685,16 @@ static int _xusb_ep_init_context(u32 ep_idx) ep_ctxt->trd_dequeueptr_hi = 0; link_trb = (link_trb_t *)&xusb_evtq->xusb_cntrl_event_queue[XUSB_LINK_TRB_IDX]; - link_trb->toggle_cycle = 1; + link_trb->toggle_cycle = 1; link_trb->ring_seg_ptrlo = (u32)xusb_evtq->xusb_cntrl_event_queue >> 4; link_trb->ring_seg_ptrhi = 0; - link_trb->trb_type = XUSB_TRB_LINK; + link_trb->trb_type = XUSB_TRB_LINK; break; case USB_EP_BULK_OUT: usbd_xotg->bulkout_producer_cycle = 1; - usbd_xotg->bulkout_epenqueue_ptr = xusb_evtq->xusb_bulkout_event_queue; - usbd_xotg->bulkout_epdequeue_ptr = xusb_evtq->xusb_bulkout_event_queue; + usbd_xotg->bulkout_epenqueue_ptr = xusb_evtq->xusb_bulkout_event_queue; + usbd_xotg->bulkout_epdequeue_ptr = xusb_evtq->xusb_bulkout_event_queue; _xusb_ep_set_type_and_metrics(ep_idx, ep_ctxt); @@ -702,16 +702,16 @@ static int _xusb_ep_init_context(u32 ep_idx) ep_ctxt->trd_dequeueptr_hi = 0; link_trb = (link_trb_t *)&xusb_evtq->xusb_bulkout_event_queue[XUSB_LINK_TRB_IDX]; - link_trb->toggle_cycle = 1; + link_trb->toggle_cycle = 1; link_trb->ring_seg_ptrlo = (u32)xusb_evtq->xusb_bulkout_event_queue >> 4; link_trb->ring_seg_ptrhi = 0; - link_trb->trb_type = XUSB_TRB_LINK; + link_trb->trb_type = XUSB_TRB_LINK; break; case USB_EP_BULK_IN: usbd_xotg->bulkin_producer_cycle = 1; - usbd_xotg->bulkin_epenqueue_ptr = xusb_evtq->xusb_bulkin_event_queue; - usbd_xotg->bulkin_epdequeue_ptr = xusb_evtq->xusb_bulkin_event_queue; + usbd_xotg->bulkin_epenqueue_ptr = xusb_evtq->xusb_bulkin_event_queue; + usbd_xotg->bulkin_epdequeue_ptr = xusb_evtq->xusb_bulkin_event_queue; _xusb_ep_set_type_and_metrics(ep_idx, ep_ctxt); @@ -719,10 +719,10 @@ static int _xusb_ep_init_context(u32 ep_idx) ep_ctxt->trd_dequeueptr_hi = 0; link_trb = (link_trb_t *)&xusb_evtq->xusb_bulkin_event_queue[XUSB_LINK_TRB_IDX]; - link_trb->toggle_cycle = 1; + link_trb->toggle_cycle = 1; link_trb->ring_seg_ptrlo = (u32)xusb_evtq->xusb_bulkin_event_queue >> 4; link_trb->ring_seg_ptrhi = 0; - link_trb->trb_type = XUSB_TRB_LINK; + link_trb->trb_type = XUSB_TRB_LINK; break; } @@ -744,7 +744,7 @@ static int _xusbd_ep_initialize(u32 ep_idx) if (!res) { XUSB_DEV_XHCI(XUSB_DEV_XHCI_EP_PAUSE) &= ~BIT(ep_idx); - XUSB_DEV_XHCI(XUSB_DEV_XHCI_EP_HALT) &= ~BIT(ep_idx); + XUSB_DEV_XHCI(XUSB_DEV_XHCI_EP_HALT) &= ~BIT(ep_idx); } return res; default: @@ -752,6 +752,48 @@ static int _xusbd_ep_initialize(u32 ep_idx) } } +static void _xusbd_ep1_disable(u32 ep_idx) +{ + volatile xusb_ep_ctx_t *ep_ctxt = &xusb_evtq->xusb_ep_ctxt[ep_idx]; + u32 ep_mask = BIT(ep_idx); + + switch (ep_idx) + { + case USB_EP_BULK_OUT: + case USB_EP_BULK_IN: + // Skip if already disabled. + if (!ep_ctxt->ep_state) + return; + + XUSB_DEV_XHCI(XUSB_DEV_XHCI_EP_HALT) |= ep_mask; + + // Set EP state to disabled. + ep_ctxt->ep_state = EP_DISABLED; + + // Wait for EP status to change. + _xusb_xhci_mask_wait(XUSB_DEV_XHCI_EP_STCHG, ep_mask, ep_mask, 1000); + + // Clear status change. + XUSB_DEV_XHCI(XUSB_DEV_XHCI_EP_STCHG) = ep_mask; + break; + } +} + +static void _xusb_disable_ep1() +{ + _xusbd_ep1_disable(USB_EP_BULK_OUT); + _xusbd_ep1_disable(USB_EP_BULK_IN); + + // Device mode stop. + XUSB_DEV_XHCI(XUSB_DEV_XHCI_CTRL) &= ~XHCI_CTRL_RUN; + XUSB_DEV_XHCI(XUSB_DEV_XHCI_ST) |= XHCI_ST_RC; + + usbd_xotg->config_num = 0; + usbd_xotg->interface_num = 0; + usbd_xotg->max_lun_set = false; + usbd_xotg->device_state = XUSB_DEFAULT; +} + static void _xusb_init_phy() { // Configure and enable PLLU. @@ -785,7 +827,7 @@ static void _xusb_init_phy() (void)XUSB_PADCTL(XUSB_PADCTL_USB2_OTG_PAD0_CTL_1); // Commit write. // Enable USB2 tracking clock. - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_Y_SET) = BIT(CLK_Y_USB2_TRK); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_Y_SET) = BIT(CLK_Y_USB2_TRK); CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK) = (CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK) & 0xFFFFFF00) | 6; // Set trank divisor to 4. // Set tracking parameters and trigger it. @@ -841,11 +883,12 @@ static void _xusbd_init_device_clocks() int xusb_device_init() { - ///////////////////////////////////////////////// + // Ease the stress to APB. + bpmp_clk_rate_relaxed(true); + + // Disable USB2 device controller clocks. CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_USBD); CLOCK(CLK_RST_CONTROLLER_CLK_ENB_L_CLR) = BIT(CLK_L_USBD); - ///////////////////////////////////////////////// - // Enable XUSB clock and clear Reset to XUSB Pad Control. CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_SET) = BIT(CLK_W_XUSB); @@ -880,8 +923,11 @@ int xusb_device_init() // Initialize device clocks. _xusbd_init_device_clocks(); + // Restore OC. + bpmp_clk_rate_relaxed(false); + // Enable AHB redirect for access to IRAM for Event/EP ring buffers. - mc_enable_ahb_redirect(false); // Can be skipped if IRAM is not used. + mc_enable_ahb_redirect(); // Enable XUSB device IPFS. XUSB_DEV_DEV(XUSB_DEV_CONFIGURATION) |= DEV_CONFIGURATION_EN_FPCI; @@ -896,10 +942,10 @@ int xusb_device_init() // AHB USB performance cfg. AHB_GIZMO(AHB_GIZMO_AHB_MEM) |= AHB_MEM_DONT_SPLIT_AHB_WR | AHB_MEM_ENB_FAST_REARBITRATE; - AHB_GIZMO(AHB_GIZMO_USB3) |= AHB_GIZMO_IMMEDIATE; - AHB_GIZMO(AHB_ARBITRATION_PRIORITY_CTRL) = PRIORITY_CTRL_WEIGHT(7) | PRIORITY_SELECT_USB3; - AHB_GIZMO(AHB_AHB_MEM_PREFETCH_CFG1) = - MEM_PREFETCH_ENABLE | MEM_PREFETCH_USB3_MST_ID | MEM_PREFETCH_ADDR_BNDRY(12) | 0x1000; // Addr boundary 64KB, Inactivity 4096 cycles. + AHB_GIZMO(AHB_GIZMO_USB3) |= AHB_GIZMO_IMMEDIATE; + AHB_GIZMO(AHB_ARBITRATION_PRIORITY_CTRL) = PRIORITY_CTRL_WEIGHT(7) | PRIORITY_SELECT_USB3; + AHB_GIZMO(AHB_AHB_MEM_PREFETCH_CFG1) = MEM_PREFETCH_ENABLE | MEM_PREFETCH_USB3_MST_ID | + MEM_PREFETCH_ADDR_BNDRY(12) | 0x1000; // Addr boundary 64KB, Inactivity 4096 cycles. // Initialize context. usbd_xotg = &usbd_xotg_controller_ctxt; @@ -907,8 +953,8 @@ int xusb_device_init() // Initialize event and EP rings. _xusbd_ep_init_event_ring(); - memset(xusb_evtq->xusb_cntrl_event_queue, 0, sizeof(xusb_evtq->xusb_cntrl_event_queue)); - memset(xusb_evtq->xusb_bulkin_event_queue, 0, sizeof(xusb_evtq->xusb_bulkin_event_queue)); + memset(xusb_evtq->xusb_cntrl_event_queue, 0, sizeof(xusb_evtq->xusb_cntrl_event_queue)); + memset(xusb_evtq->xusb_bulkin_event_queue, 0, sizeof(xusb_evtq->xusb_bulkin_event_queue)); memset(xusb_evtq->xusb_bulkout_event_queue, 0, sizeof(xusb_evtq->xusb_bulkout_event_queue)); // Initialize Control EP. @@ -927,7 +973,45 @@ int xusb_device_init() return USB_RES_OK; } -static int _xusb_queue_trb(u32 ep_idx, void *trb, bool ring_doorbell) +//! TODO: Power down more stuff. +static void _xusb_device_power_down() +{ + // Disable clock for XUSB Super-Speed and set source to CLK_M. + CLOCK(CLK_RST_CONTROLLER_RST_DEV_W_SET) = BIT(CLK_W_XUSB_SS); + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_SS) &= 0x1FFFFF00; + usleep(2); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_CLR) = BIT(CLK_W_XUSB_SS); + + // Put XUSB device into reset. + CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_SET) = BIT(CLK_U_XUSB_DEV); + usleep(2); + + // Reset Full-Speed clock source to CLK_M and div1. + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_XUSB_FS) = 0; + usleep(2); + + // Disable XUSB device clock. + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_CLR) = BIT(CLK_U_XUSB_DEV); + + // Force UTMIP_PLL power down. + CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG1) &= (~BIT(15)); + CLOCK(CLK_RST_CONTROLLER_UTMIP_PLL_CFG2) |= BIT(4) | BIT(0); // UTMIP_FORCE_PD_SAMP_A/C_POWERDOWN. + + // Force enable UTMIPLL IDDQ. + CLOCK(CLK_RST_CONTROLLER_UTMIPLL_HW_PWRDN_CFG0) |= 3; + + // Disable PLLU. + clock_disable_pllu(); + + // Set XUSB_PADCTL clock reset. + CLOCK(CLK_RST_CONTROLLER_RST_DEV_W_SET) = BIT(CLK_W_XUSB_PADCTL); + + // Disable XUSB clock. + CLOCK(CLK_RST_CONTROLLER_RST_DEV_W_SET) = BIT(CLK_W_XUSB); + CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_CLR) = BIT(CLK_W_XUSB); +} + +static int _xusb_queue_trb(u32 ep_idx, const void *trb, bool ring_doorbell) { int res = USB_RES_OK; data_trb_t *next_trb; @@ -946,7 +1030,9 @@ static int _xusb_queue_trb(u32 ep_idx, void *trb, bool ring_doorbell) link_trb = (link_trb_t *)next_trb; link_trb->cycle = usbd_xotg->cntrl_producer_cycle & 1; link_trb->toggle_cycle = 1; + next_trb = (data_trb_t *)(link_trb->ring_seg_ptrlo << 4); + usbd_xotg->cntrl_producer_cycle ^= 1; } usbd_xotg->cntrl_epenqueue_ptr = next_trb; @@ -962,7 +1048,9 @@ static int _xusb_queue_trb(u32 ep_idx, void *trb, bool ring_doorbell) link_trb = (link_trb_t *)next_trb; link_trb->cycle = usbd_xotg->bulkout_producer_cycle & 1; link_trb->toggle_cycle = 1; + next_trb = (data_trb_t *)(link_trb->ring_seg_ptrlo << 4); + usbd_xotg->bulkout_producer_cycle ^= 1; } usbd_xotg->bulkout_epenqueue_ptr = next_trb; @@ -978,7 +1066,9 @@ static int _xusb_queue_trb(u32 ep_idx, void *trb, bool ring_doorbell) link_trb = (link_trb_t *)next_trb; link_trb->cycle = usbd_xotg->bulkin_producer_cycle & 1; link_trb->toggle_cycle = 1; + next_trb = (data_trb_t *)(link_trb->ring_seg_ptrlo << 4); + usbd_xotg->bulkin_producer_cycle ^= 1; } usbd_xotg->bulkin_epenqueue_ptr = next_trb; @@ -993,10 +1083,13 @@ static int _xusb_queue_trb(u32 ep_idx, void *trb, bool ring_doorbell) // Ring doorbell. if (ring_doorbell) { - bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false); + // Flush data before transfer. + bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLEAN_WAY, false); + u32 target_id = (ep_idx << 8) & 0xFFFF; if (ep_idx == XUSB_EP_CTRL_IN) target_id |= usbd_xotg->ctrl_seq_num << 16; + XUSB_DEV_XHCI(XUSB_DEV_XHCI_DB) = target_id; } @@ -1005,10 +1098,10 @@ static int _xusb_queue_trb(u32 ep_idx, void *trb, bool ring_doorbell) static void _xusb_create_status_trb(status_trb_t *trb, usb_dir_t direction) { - trb->cycle = usbd_xotg->cntrl_producer_cycle & 1; - trb->ioc = 1; // Enable interrupt on completion. + trb->cycle = usbd_xotg->cntrl_producer_cycle & 1; + trb->ioc = 1; // Enable interrupt on completion. trb->trb_type = XUSB_TRB_STATUS; - trb->dir = direction; + trb->dir = direction; } static void _xusb_create_normal_trb(normal_trb_t *trb, u8 *buf, u32 len, usb_dir_t direction) @@ -1022,16 +1115,16 @@ static void _xusb_create_normal_trb(normal_trb_t *trb, u8 *buf, u32 len, usb_dir // Single TRB transfer. trb->td_size = 0; - trb->chain = 0; + trb->chain = 0; if (direction == USB_DIR_IN) producer_cycle = usbd_xotg->bulkin_producer_cycle & 1; else producer_cycle = usbd_xotg->bulkout_producer_cycle & 1; - trb->cycle = producer_cycle; - trb->isp = 1; // Enable interrupt on short packet. - trb->ioc = 1; // Enable interrupt on completion. + trb->cycle = producer_cycle; + trb->isp = 1; // Enable interrupt on short packet. + trb->ioc = 1; // Enable interrupt on completion. trb->trb_type = XUSB_TRB_NORMAL; } @@ -1044,13 +1137,13 @@ static void _xusb_create_data_trb(data_trb_t *trb, u8 *buf, u32 len, usb_dir_t d // Single TRB transfer. trb->td_size = 0; - trb->chain = 0; + trb->chain = 0; - trb->cycle = usbd_xotg->cntrl_producer_cycle & 1; - trb->isp = 1; // Enable interrupt on short packet. - trb->ioc = 1; // Enable interrupt on completion. + trb->cycle = usbd_xotg->cntrl_producer_cycle & 1; + trb->isp = 1; // Enable interrupt on short packet. + trb->ioc = 1; // Enable interrupt on completion. trb->trb_type = XUSB_TRB_DATA; - trb->dir = direction; + trb->dir = direction; } static int _xusb_issue_status_trb(usb_dir_t direction) @@ -1061,6 +1154,7 @@ static int _xusb_issue_status_trb(usb_dir_t direction) if (usbd_xotg->cntrl_epenqueue_ptr == usbd_xotg->cntrl_epdequeue_ptr || direction == USB_DIR_OUT) { _xusb_create_status_trb(&trb, direction); + res = _xusb_queue_trb(XUSB_EP_CTRL_IN, &trb, EP_RING_DOORBELL); usbd_xotg->wait_for_event_trb = XUSB_TRB_STATUS; } @@ -1076,6 +1170,7 @@ static int _xusb_issue_normal_trb(u8 *buf, u32 len, usb_dir_t direction) u32 ep_idx = USB_EP_BULK_IN; if (direction == USB_DIR_OUT) ep_idx = USB_EP_BULK_OUT; + int res = _xusb_queue_trb(ep_idx, &trb, EP_RING_DOORBELL); if (!res) usbd_xotg->wait_for_event_trb = XUSB_TRB_NORMAL; @@ -1091,6 +1186,7 @@ static int _xusb_issue_data_trb(u8 *buf, u32 len, usb_dir_t direction) if (usbd_xotg->cntrl_epenqueue_ptr == usbd_xotg->cntrl_epdequeue_ptr) { _xusb_create_data_trb(&trb, buf, len, direction); + res = _xusb_queue_trb(XUSB_EP_CTRL_IN, &trb, EP_RING_DOORBELL); if (!res) usbd_xotg->wait_for_event_trb = XUSB_TRB_DATA; @@ -1130,7 +1226,7 @@ static int _xusb_wait_ep_stopped(u32 endpoint) return USB_RES_OK; } -static int _xusb_handle_transfer_event(transfer_event_trb_t *trb) +static int _xusb_handle_transfer_event(const transfer_event_trb_t *trb) { // Advance dequeue list. data_trb_t *next_trb; @@ -1360,12 +1456,12 @@ static int _xusb_handle_get_ep_status(u32 ep_idx) u32 ep_mask = BIT(ep_idx); static u8 xusb_ep_status_descriptor[2] = {0}; - xusb_ep_status_descriptor[0] = - (XUSB_DEV_XHCI(XUSB_DEV_XHCI_EP_HALT) & ep_mask) ? USB_STATUS_EP_HALTED : USB_STATUS_EP_OK; + xusb_ep_status_descriptor[0] = (XUSB_DEV_XHCI(XUSB_DEV_XHCI_EP_HALT) & ep_mask) ? USB_STATUS_EP_HALTED : USB_STATUS_EP_OK; + return _xusb_issue_data_trb(xusb_ep_status_descriptor, 2, USB_DIR_IN); } -static int _xusb_handle_get_class_request(usb_ctrl_setup_t *ctrl_setup) +static int _xusb_handle_get_class_request(const usb_ctrl_setup_t *ctrl_setup) { u8 _bRequest = ctrl_setup->bRequest; u16 _wIndex = ctrl_setup->wIndex; @@ -1383,6 +1479,7 @@ static int _xusb_handle_get_class_request(usb_ctrl_setup_t *ctrl_setup) case USB_REQUEST_BULK_RESET: usbd_xotg->bulk_reset_req = true; return _xusb_issue_status_trb(USB_DIR_IN); // DELAYED_STATUS; + case USB_REQUEST_BULK_GET_MAX_LUN: if (!usbd_xotg->max_lun_set) goto stall; @@ -1395,7 +1492,7 @@ stall: return USB_RES_OK; } -static int _xusb_handle_get_descriptor(usb_ctrl_setup_t *ctrl_setup) +static int _xusb_handle_get_descriptor(const usb_ctrl_setup_t *ctrl_setup) { u32 size; void *descriptor; @@ -1524,7 +1621,7 @@ static int _xusb_handle_get_descriptor(usb_ctrl_setup_t *ctrl_setup) return _xusb_issue_data_trb(descriptor, size, USB_DIR_IN); } -static void _xusb_handle_set_request_dev_address(usb_ctrl_setup_t *ctrl_setup) +static void _xusb_handle_set_request_dev_address(const usb_ctrl_setup_t *ctrl_setup) { u32 addr = ctrl_setup->wValue & 0xFF; @@ -1536,11 +1633,20 @@ static void _xusb_handle_set_request_dev_address(usb_ctrl_setup_t *ctrl_setup) usbd_xotg->device_state = XUSB_ADDRESSED_STS_WAIT; } -static void _xusb_handle_set_request_configuration(usb_ctrl_setup_t *ctrl_setup) +static void _xusb_handle_set_request_configuration(const usb_ctrl_setup_t *ctrl_setup) { - u32 config_num = ctrl_setup->wValue; - if (!config_num) //TODO! we can change device_state here. + usbd_xotg->config_num = ctrl_setup->wValue; + + // Remove configuration. + if (!usbd_xotg->config_num) + { + //! TODO: Signal that to userspace. + _xusb_disable_ep1(); + + _xusb_issue_status_trb(USB_DIR_IN); + return; + } // Initialize BULK EPs. _xusbd_ep_initialize(USB_EP_BULK_OUT); @@ -1551,8 +1657,6 @@ static void _xusb_handle_set_request_configuration(usb_ctrl_setup_t *ctrl_setup) XUSB_DEV_XHCI(XUSB_DEV_XHCI_ST) |= XHCI_ST_RC; _xusb_issue_status_trb(USB_DIR_IN); - - usbd_xotg->config_num = config_num; usbd_xotg->device_state = XUSB_CONFIGURED_STS_WAIT; } @@ -1862,7 +1966,7 @@ int xusb_device_enumerate(usb_gadget_type gadget) // Enable overrides for VBUS and ID. XUSB_PADCTL(XUSB_PADCTL_USB2_VBUS_ID) = (XUSB_PADCTL(XUSB_PADCTL_USB2_VBUS_ID) & ~(PADCTL_USB2_VBUS_ID_VBUS_OVR_MASK | PADCTL_USB2_VBUS_ID_SRC_MASK)) | - PADCTL_USB2_VBUS_ID_VBUS_OVR_EN | PADCTL_USB2_VBUS_ID_SRC_ID_OVR_EN; + PADCTL_USB2_VBUS_ID_VBUS_OVR_EN | PADCTL_USB2_VBUS_ID_SRC_ID_OVR_EN; // Clear halt for LTSSM. XUSB_DEV_XHCI(XUSB_DEV_XHCI_PORTHALT) &= ~XHCI_PORTHALT_HALT_LTSSM; @@ -1873,16 +1977,15 @@ int xusb_device_enumerate(usb_gadget_type gadget) // Override access to High/Full Speed. XUSB_DEV_XHCI(XUSB_DEV_XHCI_CFG_DEV_FE) = (XUSB_DEV_XHCI(XUSB_DEV_XHCI_CFG_DEV_FE) & ~XHCI_CFG_DEV_FE_PORTREGSEL_MASK) | XHCI_CFG_DEV_FE_PORTREGSEL_HSFS; - XUSB_DEV_XHCI(XUSB_DEV_XHCI_PORTSC) = - (XUSB_DEV_XHCI(XUSB_DEV_XHCI_PORTSC) & ~XHCI_PORTSC_PLS_MASK) | XHCI_PORTSC_LWS | XHCI_PORTSC_PLS_RXDETECT; + XUSB_DEV_XHCI(XUSB_DEV_XHCI_PORTSC) = (XUSB_DEV_XHCI(XUSB_DEV_XHCI_PORTSC) & ~XHCI_PORTSC_PLS_MASK) | XHCI_PORTSC_LWS | XHCI_PORTSC_PLS_RXDETECT; XUSB_DEV_XHCI(XUSB_DEV_XHCI_CFG_DEV_FE) &= ~XHCI_CFG_DEV_FE_PORTREGSEL_MASK; // Enable VBUS and set ID to Float. XUSB_PADCTL(XUSB_PADCTL_USB2_VBUS_ID) = (XUSB_PADCTL(XUSB_PADCTL_USB2_VBUS_ID) & ~PADCTL_USB2_VBUS_ID_OVR_MASK) | - PADCTL_USB2_VBUS_ID_OVR_FLOAT | PADCTL_USB2_VBUS_ID_VBUS_ON; + PADCTL_USB2_VBUS_ID_OVR_FLOAT | PADCTL_USB2_VBUS_ID_VBUS_ON; usbd_xotg->wait_for_event_trb = XUSB_TRB_SETUP; - usbd_xotg->device_state = XUSB_DEFAULT; + usbd_xotg->device_state = XUSB_DEFAULT; // Timeout if cable or communication isn't started in 1.5 minutes. u32 timer = get_tmr_ms() + 90000; @@ -1902,17 +2005,16 @@ int xusb_device_enumerate(usb_gadget_type gadget) return USB_RES_OK; } -//! TODO: Do a full deinit. void xusb_end(bool reset_ep, bool only_controller) { - CLOCK(CLK_RST_CONTROLLER_RST_DEV_W_SET) = BIT(CLK_W_XUSB_SS); - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_CLR) = BIT(CLK_W_XUSB_SS); - CLOCK(CLK_RST_CONTROLLER_RST_DEV_U_SET) = BIT(CLK_U_XUSB_DEV); - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_U_CLR) = BIT(CLK_U_XUSB_DEV); - CLOCK(CLK_RST_CONTROLLER_RST_DEV_W_SET) = BIT(CLK_W_XUSB_PADCTL); - CLOCK(CLK_RST_CONTROLLER_CLK_ENB_W_CLR) = BIT(CLK_W_XUSB); - CLOCK(CLK_RST_CONTROLLER_RST_DEV_W_SET) = BIT(CLK_W_XUSB); - mc_disable_ahb_redirect(); // Can be skipped if IRAM is not used. + // Disable endpoints and stop device mode operation. + _xusb_disable_ep1(); + + // Disable device mode. + XUSB_DEV_XHCI(XUSB_DEV_XHCI_CTRL) = 0; + + //! TODO: Add only controller support? + _xusb_device_power_down(); } int xusb_handle_ep0_ctrl_setup() @@ -1938,6 +2040,7 @@ int xusb_device_ep1_out_read(u8 *buf, u32 len, u32 *bytes_read, u32 sync_tries) int res = USB_RES_OK; usbd_xotg->tx_count[USB_DIR_OUT] = 0; usbd_xotg->tx_bytes[USB_DIR_OUT] = len; + _xusb_issue_normal_trb(buf, len, USB_DIR_OUT); usbd_xotg->tx_count[USB_DIR_OUT]++; @@ -1948,10 +2051,11 @@ int xusb_device_ep1_out_read(u8 *buf, u32 len, u32 *bytes_read, u32 sync_tries) if (bytes_read) *bytes_read = res ? 0 : usbd_xotg->tx_bytes[USB_DIR_OUT]; - - bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false); } + // Invalidate data after transfer. + bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, false); + return res; } @@ -1989,7 +2093,8 @@ int xusb_device_ep1_out_reading_finish(u32 *pending_bytes, u32 sync_tries) if (pending_bytes) *pending_bytes = res ? 0 : usbd_xotg->tx_bytes[USB_DIR_OUT]; - bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false); + // Invalidate data after transfer. + bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, false); return res; } @@ -1999,11 +2104,13 @@ int xusb_device_ep1_in_write(u8 *buf, u32 len, u32 *bytes_written, u32 sync_trie if (len > USB_EP_BUFFER_MAX_SIZE) len = USB_EP_BUFFER_MAX_SIZE; - bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLN_INV_WAY, false); + // Flush data before transfer. + bpmp_mmu_maintenance(BPMP_MMU_MAINT_CLEAN_WAY, false); int res = USB_RES_OK; usbd_xotg->tx_count[USB_DIR_IN] = 0; usbd_xotg->tx_bytes[USB_DIR_IN] = len; + _xusb_issue_normal_trb(buf, len, USB_DIR_IN); usbd_xotg->tx_count[USB_DIR_IN]++; @@ -2053,7 +2160,7 @@ bool xusb_device_class_send_max_lun(u8 max_lun) // Timeout if get MAX_LUN request doesn't happen in 10s. u32 timer = get_tmr_ms() + 10000; - usbd_xotg->max_lun = max_lun; + usbd_xotg->max_lun = max_lun; usbd_xotg->max_lun_set = true; // Wait for request and transfer start. diff --git a/bdk/utils/btn.c b/bdk/utils/btn.c index cc36573..55ca67b 100644 --- a/bdk/utils/btn.c +++ b/bdk/utils/btn.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer + * Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,8 +18,8 @@ #include "btn.h" #include #include +#include #include -#include #include u8 btn_read() @@ -29,6 +29,7 @@ u8 btn_read() res |= BTN_VOL_DOWN; if (!gpio_read(GPIO_PORT_X, GPIO_PIN_6)) res |= BTN_VOL_UP; + // HOAG can use the GPIO. Icosa/Iowa/AULA cannot. Traces are there but they miss a resistor. if (i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFSTAT) & MAX77620_ONOFFSTAT_EN0) res |= BTN_POWER; return res; @@ -44,6 +45,11 @@ u8 btn_read_vol() return res; } +u8 btn_read_home() +{ + return (!gpio_read(GPIO_PORT_Y, GPIO_PIN_1)) ? BTN_HOME : 0; +} + u8 btn_wait() { u8 res = 0, btn = btn_read(); diff --git a/bdk/utils/btn.h b/bdk/utils/btn.h index ac191fa..a1c91a3 100644 --- a/bdk/utils/btn.h +++ b/bdk/utils/btn.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 CTCaer + * Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -23,10 +23,12 @@ #define BTN_POWER BIT(0) #define BTN_VOL_DOWN BIT(1) #define BTN_VOL_UP BIT(2) +#define BTN_HOME BIT(3) #define BTN_SINGLE BIT(7) u8 btn_read(); u8 btn_read_vol(); +u8 btn_read_home(); u8 btn_wait(); u8 btn_wait_timeout(u32 time_ms, u8 mask); u8 btn_wait_timeout_single(u32 time_ms, u8 mask); diff --git a/bdk/utils/dirlist.c b/bdk/utils/dirlist.c index 3b09d1d..b1de140 100644 --- a/bdk/utils/dirlist.c +++ b/bdk/utils/dirlist.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 CTCaer + * Copyright (c) 2018-2025 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,21 +17,23 @@ #include #include +#include "dirlist.h" #include #include #include -#define MAX_ENTRIES 64 - -char *dirlist(const char *directory, const char *pattern, bool includeHiddenFiles, bool parse_dirs) +dirlist_t *dirlist(const char *directory, const char *pattern, bool includeHiddenFiles, bool parse_dirs) { int res = 0; - u32 i = 0, j = 0, k = 0; + u32 k = 0; DIR dir; FILINFO fno; - char *dir_entries = (char *)calloc(MAX_ENTRIES, 256); - char *temp = (char *)calloc(1, 256); + dirlist_t *dir_entries = (dirlist_t *)malloc(sizeof(dirlist_t)); + + // Setup pointer tree. + for (u32 i = 0; i < DIR_MAX_ENTRIES; i++) + dir_entries->name[i] = &dir_entries->data[i * 256]; if (!pattern && !f_opendir(&dir, directory)) { @@ -47,9 +49,8 @@ char *dirlist(const char *directory, const char *pattern, bool includeHiddenFile { if ((fno.fname[0] != '.') && (includeHiddenFiles || !(fno.fattrib & AM_HID))) { - strcpy(dir_entries + (k * 256), fno.fname); - k++; - if (k > (MAX_ENTRIES - 1)) + strcpy(&dir_entries->data[k * 256], fno.fname); + if (++k >= DIR_MAX_ENTRIES) break; } } @@ -62,9 +63,8 @@ char *dirlist(const char *directory, const char *pattern, bool includeHiddenFile { if (!(fno.fattrib & AM_DIR) && (fno.fname[0] != '.') && (includeHiddenFiles || !(fno.fattrib & AM_HID))) { - strcpy(dir_entries + (k * 256), fno.fname); - k++; - if (k > (MAX_ENTRIES - 1)) + strcpy(&dir_entries->data[k * 256], fno.fname); + if (++k >= DIR_MAX_ENTRIES) break; } res = f_findnext(&dir, &fno); @@ -74,27 +74,27 @@ char *dirlist(const char *directory, const char *pattern, bool includeHiddenFile if (!k) { - free(temp); free(dir_entries); return NULL; } - // Reorder ini files by ASCII ordering. - for (i = 0; i < k - 1 ; i++) + // Terminate name list. + dir_entries->name[k] = NULL; + + // Reorder ini files Alphabetically. + for (u32 i = 0; i < k - 1 ; i++) { - for (j = i + 1; j < k; j++) + for (u32 j = i + 1; j < k; j++) { - if (strcmp(&dir_entries[i * 256], &dir_entries[j * 256]) > 0) + if (strcasecmp(dir_entries->name[i], dir_entries->name[j]) > 0) { - strcpy(temp, &dir_entries[i * 256]); - strcpy(&dir_entries[i * 256], &dir_entries[j * 256]); - strcpy(&dir_entries[j * 256], temp); + char *tmp = dir_entries->name[i]; + dir_entries->name[i] = dir_entries->name[j]; + dir_entries->name[j] = tmp; } } } - free(temp); - return dir_entries; } diff --git a/bdk/utils/dirlist.h b/bdk/utils/dirlist.h index 32197f3..cb250c3 100644 --- a/bdk/utils/dirlist.h +++ b/bdk/utils/dirlist.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,4 +16,12 @@ #include -char *dirlist(const char *directory, const char *pattern, bool includeHiddenFiles, bool parse_dirs); +#define DIR_MAX_ENTRIES 64 + +typedef struct _dirlist_t +{ + char *name[DIR_MAX_ENTRIES]; + char data[DIR_MAX_ENTRIES * 256]; +} dirlist_t; + +dirlist_t *dirlist(const char *directory, const char *pattern, bool includeHiddenFiles, bool parse_dirs); diff --git a/bdk/utils/ini.c b/bdk/utils/ini.c index 5088f51..6832bdc 100644 --- a/bdk/utils/ini.c +++ b/bdk/utils/ini.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -21,25 +21,7 @@ #include #include #include - -static char *_strdup(char *str) -{ - if (!str) - return NULL; - - // Remove starting space. - if (str[0] == ' ' && strlen(str)) - str++; - - char *res = (char *)malloc(strlen(str) + 1); - strcpy(res, str); - - // Remove trailing space. - if (strlen(res) && res[strlen(res) - 1] == ' ') - res[strlen(res) - 1] = 0; - - return res; -} +#include u32 _find_section_name(char *lbuf, u32 lblen, char schar) { @@ -57,23 +39,30 @@ ini_sec_t *_ini_create_section(link_t *dst, ini_sec_t *csec, char *name, u8 type if (csec) list_append(dst, &csec->link); - csec = (ini_sec_t *)calloc(sizeof(ini_sec_t), 1); - csec->name = _strdup(name); + // Calculate total allocation size. + u32 len = name ? strlen(name) + 1 : 0; + char *buf = zalloc(sizeof(ini_sec_t) + len); + + csec = (ini_sec_t *)buf; + csec->name = strcpy_ns(buf + sizeof(ini_sec_t), name); csec->type = type; + // Initialize list. + list_init(&csec->kvs); + return csec; } -int ini_parse(link_t *dst, char *ini_path, bool is_dir) +int ini_parse(link_t *dst, const char *ini_path, bool is_dir) { FIL fp; u32 lblen; - u32 pathlen = strlen(ini_path); u32 k = 0; + u32 pathlen = strlen(ini_path); ini_sec_t *csec = NULL; - char *lbuf = NULL; - char *filelist = NULL; + char *lbuf = NULL; + dirlist_t *filelist = NULL; char *filename = (char *)malloc(256); strcpy(filename, ini_path); @@ -96,9 +85,9 @@ int ini_parse(link_t *dst, char *ini_path, bool is_dir) // Copy ini filename in path string. if (is_dir) { - if (filelist[k * 256]) + if (filelist->name[k]) { - strcpy(filename + pathlen, &filelist[k * 256]); + strcpy(filename + pathlen, filelist->name[k]); k++; } else @@ -132,7 +121,6 @@ int ini_parse(link_t *dst, char *ini_path, bool is_dir) _find_section_name(lbuf, lblen, ']'); csec = _ini_create_section(dst, csec, &lbuf[1], INI_CHOICE); - list_init(&csec->kvs); } else if (lblen > 1 && lbuf[0] == '{') // Create new caption. Support empty caption '{}'. { @@ -153,13 +141,22 @@ int ini_parse(link_t *dst, char *ini_path, bool is_dir) { u32 i = _find_section_name(lbuf, lblen, '='); - ini_kv_t *kv = (ini_kv_t *)calloc(sizeof(ini_kv_t), 1); - kv->key = _strdup(&lbuf[0]); - kv->val = _strdup(&lbuf[i + 1]); + // Calculate total allocation size. + u32 klen = strlen(&lbuf[0]) + 1; + u32 vlen = strlen(&lbuf[i + 1]) + 1; + char *buf = zalloc(sizeof(ini_kv_t) + klen + vlen); + + ini_kv_t *kv = (ini_kv_t *)buf; + buf += sizeof(ini_kv_t); + kv->key = strcpy_ns(buf, &lbuf[0]); + buf += klen; + kv->val = strcpy_ns(buf, &lbuf[i + 1]); list_append(&csec->kvs, &kv->link); } } while (!f_eof(&fp)); + free(lbuf); + f_close(&fp); if (csec) @@ -170,23 +167,61 @@ int ini_parse(link_t *dst, char *ini_path, bool is_dir) } } while (is_dir); - free(lbuf); free(filename); free(filelist); return 1; } -char *ini_check_payload_section(ini_sec_t *cfg) +char *ini_check_special_section(ini_sec_t *cfg) { if (cfg == NULL) return NULL; LIST_FOREACH_ENTRY(ini_kv_t, kv, &cfg->kvs, link) { - if (!strcmp("payload", kv->key)) + if (!strcmp("l4t", kv->key)) + return ((kv->val[0] == '1') ? (char *)-1 : NULL); + else if (!strcmp("payload", kv->key)) return kv->val; } return NULL; } + +void ini_free(link_t *src) +{ + ini_sec_t *prev_sec = NULL; + + // Parse and free all ini sections. + LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, src, link) + { + ini_kv_t *prev_kv = NULL; + + // Free all ini key allocations if they exist. + LIST_FOREACH_ENTRY(ini_kv_t, kv, &ini_sec->kvs, link) + { + // Free previous key. + if (prev_kv) + free(prev_kv); + + // Set next key to free. + prev_kv = kv; + } + + // Free last key. + if (prev_kv) + free(prev_kv); + + // Free previous section. + if (prev_sec) + free(prev_sec); + + // Set next section to free. + prev_sec = ini_sec; + } + + // Free last section. + if (prev_sec) + free(prev_sec); +} diff --git a/bdk/utils/ini.h b/bdk/utils/ini.h index 571d19d..35c13c8 100644 --- a/bdk/utils/ini.h +++ b/bdk/utils/ini.h @@ -43,8 +43,9 @@ typedef struct _ini_sec_t u32 color; } ini_sec_t; -int ini_parse(link_t *dst, char *ini_path, bool is_dir); -char *ini_check_payload_section(ini_sec_t *cfg); +int ini_parse(link_t *dst, const char *ini_path, bool is_dir); +char *ini_check_special_section(ini_sec_t *cfg); +void ini_free(link_t *src); #endif diff --git a/bdk/utils/list.h b/bdk/utils/list.h index ece5402..4d17261 100644 --- a/bdk/utils/list.h +++ b/bdk/utils/list.h @@ -28,16 +28,25 @@ /*! Iterate over all list links. */ #define LIST_FOREACH(iter, list) \ - for(link_t *iter = (list)->next; iter != (list); iter = iter->next) + for (link_t *iter = (list)->next; iter != (list); iter = iter->next) + +/*! Iterate over all list links backwards. */ +#define LIST_FOREACH_INVERSE(iter, list) \ + for (link_t *iter = (list)->prev; iter != (list); iter = iter->prev) /*! Safely iterate over all list links. */ #define LIST_FOREACH_SAFE(iter, list) \ - for(link_t *iter = (list)->next, *safe = iter->next; iter != (list); iter = safe, safe = iter->next) + for (link_t *iter = (list)->next, *safe = iter->next; iter != (list); iter = safe, safe = iter->next) /*! Iterate over all list members and make sure that the list has at least one entry. */ #define LIST_FOREACH_ENTRY(etype, iter, list, mn) \ if ((list)->next != (list)) \ - for(etype *iter = CONTAINER_OF((list)->next, etype, mn); &iter->mn != (list); iter = CONTAINER_OF(iter->mn.next, etype, mn)) + for (etype *iter = CONTAINER_OF((list)->next, etype, mn); &iter->mn != (list); iter = CONTAINER_OF(iter->mn.next, etype, mn)) + +/* Iterate over all list members backwards and make sure that the list has at least one entry. */ +#define LIST_FOREACH_ENTRY_INVERSE(type, iter, list, mn) \ + if ((list)->prev != (list)) \ + for (type *iter = CONTAINER_OF((list)->prev, type, mn); &iter->mn != (list); iter = CONTAINER_OF(iter->mn.prev, type, mn)) typedef struct _link_t { @@ -53,7 +62,7 @@ static inline void link_init(link_t *l) static inline int link_used(link_t *l) { - if(l->next == NULL) + if (l->next == NULL) return 1; return 0; } @@ -89,7 +98,7 @@ static inline void list_remove(link_t *l) static inline int list_empty(link_t *lh) { - if(lh->next == lh) + if (lh->next == lh) return 1; return 0; } diff --git a/bdk/utils/sprintf.c b/bdk/utils/sprintf.c index aa5b952..b86b96c 100644 --- a/bdk/utils/sprintf.c +++ b/bdk/utils/sprintf.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert -* Copyright (c) 2019-2020 CTCaer +* Copyright (c) 2019-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -28,22 +28,54 @@ static void _s_putc(char c) *sout_buf += 1; } -static void _s_puts(char *s) +static void _s_putspace(int fcnt) { + if (fcnt <= 0) + return; + + for (int i = 0; i < fcnt; i++) + _s_putc(' '); +} + +static void _s_puts(char *s, char fill, int fcnt) +{ + if (fcnt) + { + fcnt = fcnt - strlen(s); + + // Left padding. Check if padding is not space based (dot counts as such). + if (fill != '.') + _s_putspace(fcnt); + } + for (; *s; s++) _s_putc(*s); + + // Right padding. Check if padding is space based (dot counts as such). + if (fill == '.') + _s_putspace(fcnt); } static void _s_putn(u32 v, int base, char fill, int fcnt) { - char buf[65]; - static const char digits[] = "0123456789ABCDEFghijklmnopqrstuvwxyz"; - char *p; - int c = fcnt; + static const char digits[] = "0123456789ABCDEF"; - if (base > 36) + char *p; + char buf[65]; // Number char size + leftover for padding. + int c = fcnt; + bool negative = false; + + if (base != 10 && base != 16) return; + // Account for negative numbers. + if (base == 10 && v & 0x80000000) + { + negative = true; + v = (int)v * -1; + c--; + } + p = buf + 64; *p = 0; do @@ -53,18 +85,40 @@ static void _s_putn(u32 v, int base, char fill, int fcnt) v /= base; } while (v); + if (negative) + *--p = '-'; + if (fill != 0) { - while (c > 0) + while (c > 0 && p > buf) { *--p = fill; c--; } } - _s_puts(p); + _s_puts(p, 0, 0); } +/* + * Padding: + * Numbers: + * %3d: Fill: ' ', Count: 3. + * % 3d: Fill: ' ', Count: 3. + * %.3d: Fill: '.', Count: 3. + * %23d: Fill: '2', Count: 3. + * % 23d: Fill: ' ', Count: 23. + * %223d: Fill: '2', Count: 23. + * + * Strings, Fill: ' ': + * %3s: Count: 5, Left. + * %23s: Count: 5, Left. + * %223s: Count: 25, Left. + * %.3s: Count: 5, Right. + * %.23s: Count: 25, Right. + * %.223s: Count: 225, Right. + */ + void s_printf(char *out_buf, const char *fmt, ...) { va_list ap; @@ -73,58 +127,73 @@ void s_printf(char *out_buf, const char *fmt, ...) sout_buf = &out_buf; va_start(ap, fmt); - while(*fmt) + while (*fmt) { - if(*fmt == '%') + if (*fmt == '%') { fmt++; fill = 0; fcnt = 0; - if ((*fmt >= '0' && *fmt <= '9') || *fmt == ' ') + + // Check for padding. Number or space based (dot count as space for string). + if ((*fmt >= '0' && *fmt <= '9') || *fmt == ' ' || *fmt == '.') { - fcnt = *fmt; + fcnt = *fmt; // Padding size or padding type. fmt++; + if (*fmt >= '0' && *fmt <= '9') { + // Padding size exists. Previous char was type. fill = fcnt; fcnt = *fmt - '0'; fmt++; +parse_padding_dec: + // Parse padding size extra digits. + if (*fmt >= '0' && *fmt <= '9') + { + fcnt = fcnt * 10 + *fmt - '0'; + fmt++; + goto parse_padding_dec; + } } else { + // No padding type, use space. (Max padding size is 9). fill = ' '; fcnt -= '0'; } } - switch(*fmt) + + switch (*fmt) { case 'c': - _s_putc(va_arg(ap, u32)); - break; - case 's': - _s_puts(va_arg(ap, char *)); + char c = va_arg(ap, u32); + if (c != '\0') + _s_putc(c); break; + case 'd': _s_putn(va_arg(ap, u32), 10, fill, fcnt); break; + + case 's': + _s_puts(va_arg(ap, char *), fill, fcnt); + break; + case 'p': case 'P': case 'x': case 'X': _s_putn(va_arg(ap, u32), 16, fill, fcnt); break; - case 'k': - //gfx_con.fgcol = va_arg(ap, u32); - break; - case 'K': - //gfx_con.bgcol = va_arg(ap, u32); - //gfx_con.fillbg = 1; - break; + case '%': _s_putc('%'); break; + case '\0': goto out; + default: _s_putc('%'); _s_putc(*fmt); @@ -139,4 +208,92 @@ void s_printf(char *out_buf, const char *fmt, ...) out: **sout_buf = '\0'; va_end(ap); -} \ No newline at end of file +} + +void s_vprintf(char *out_buf, const char *fmt, va_list ap) +{ + int fill, fcnt; + + sout_buf = &out_buf; + + while (*fmt) + { + if (*fmt == '%') + { + fmt++; + fill = 0; + fcnt = 0; + + // Check for padding. Number or space based. + if ((*fmt >= '0' && *fmt <= '9') || *fmt == ' ') + { + fcnt = *fmt; // Padding size or padding type. + fmt++; + + if (*fmt >= '0' && *fmt <= '9') + { + // Padding size exists. Previous char was type. + fill = fcnt; + fcnt = *fmt - '0'; + fmt++; +parse_padding_dec: + // Parse padding size extra digits. + if (*fmt >= '0' && *fmt <= '9') + { + fcnt = fcnt * 10 + *fmt - '0'; + fmt++; + goto parse_padding_dec; + } + } + else + { + // No padding type, use space. (Max padding size is 9). + fill = ' '; + fcnt -= '0'; + } + } + + switch (*fmt) + { + case 'c': + char c = va_arg(ap, u32); + if (c != '\0') + _s_putc(c); + break; + + case 'd': + _s_putn(va_arg(ap, u32), 10, fill, fcnt); + break; + + case 's': + _s_puts(va_arg(ap, char *), fill, fcnt); + break; + + case 'p': + case 'P': + case 'x': + case 'X': + _s_putn(va_arg(ap, u32), 16, fill, fcnt); + break; + + case '%': + _s_putc('%'); + break; + + case '\0': + goto out; + + default: + _s_putc('%'); + _s_putc(*fmt); + break; + } + } + else + _s_putc(*fmt); + fmt++; + } + +out: + **sout_buf = '\0'; +} diff --git a/bdk/utils/sprintf.h b/bdk/utils/sprintf.h index 845f9b7..94ce468 100644 --- a/bdk/utils/sprintf.h +++ b/bdk/utils/sprintf.h @@ -17,8 +17,29 @@ #ifndef _SPRINTF_H_ #define _SPRINTF_H_ +#include + #include -void s_printf(char *out_buf, const char *fmt, ...); +/* + * Padding: + * Numbers: + * %3d: Fill: ' ', Count: 3. + * % 3d: Fill: ' ', Count: 3. + * %23d: Fill: '2', Count: 3. + * % 23d: Fill: ' ', Count: 23. + * %223d: Fill: '2', Count: 23. + * + * Strings, Fill: ' ': + * %3s: Count: 5, Left. + * %23s: Count: 5, Left. + * %223s: Count: 25, Left. + * %.3s: Count: 5, Right. + * %.23s: Count: 25, Right. + * %.223s: Count: 225, Right. + */ -#endif \ No newline at end of file +void s_printf(char *out_buf, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +void s_vprintf(char *out_buf, const char *fmt, va_list ap); + +#endif diff --git a/bdk/utils/types.h b/bdk/utils/types.h index e53c4f1..66c5d60 100644 --- a/bdk/utils/types.h +++ b/bdk/utils/types.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert -* Copyright (c) 2018-2021 CTCaer +* Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -20,26 +20,16 @@ #include -#define NULL ((void *)0) - -#define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) -#define ALIGN_DOWN(x, a) ((x) & ~((a) - 1)) -#define BIT(n) (1U << (n)) -#define MAX(a, b) ((a) > (b) ? (a) : (b)) -#define MIN(a, b) ((a) < (b) ? (a) : (b)) - -#define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x))) - -#define OFFSET_OF(t, m) ((u32)&((t *)NULL)->m) -#define CONTAINER_OF(mp, t, mn) ((t *)((u32)mp - OFFSET_OF(t, mn))) - +/* Types */ typedef signed char s8; typedef short s16; typedef short SHORT; typedef int s32; typedef int INT; +typedef int bool; typedef long LONG; typedef long long int s64; + typedef unsigned char u8; typedef unsigned char BYTE; typedef unsigned short u16; @@ -50,23 +40,72 @@ typedef unsigned int UINT; typedef unsigned long DWORD; typedef unsigned long long QWORD; typedef unsigned long long int u64; + typedef volatile unsigned char vu8; typedef volatile unsigned short vu16; typedef volatile unsigned int vu32; #ifdef __aarch64__ -typedef u64 uptr; +typedef unsigned long long uptr; #else /* __arm__ or __thumb__ */ -typedef u32 uptr; +typedef unsigned long uptr; #endif -typedef int bool; -#define true 1 +/* Important */ #define false 0 +#define true 1 +#define NULL ((void *)0) + +/* Misc */ #define DISABLE 0 #define ENABLE 1 +/* Sizes */ +#define SZ_1K 0x400 +#define SZ_2K 0x800 +#define SZ_4K 0x1000 +#define SZ_8K 0x2000 +#define SZ_16K 0x4000 +#define SZ_32K 0x8000 +#define SZ_64K 0x10000 +#define SZ_128K 0x20000 +#define SZ_256K 0x40000 +#define SZ_512K 0x80000 +#define SZ_1M 0x100000 +#define SZ_2M 0x200000 +#define SZ_4M 0x400000 +#define SZ_8M 0x800000 +#define SZ_16M 0x1000000 +#define SZ_32M 0x2000000 +#define SZ_64M 0x4000000 +#define SZ_128M 0x8000000 +#define SZ_256M 0x10000000 +#define SZ_512M 0x20000000 +#define SZ_1G 0x40000000 +#define SZ_2G 0x80000000 +#define SZ_PAGE SZ_4K + +/* Macros */ +#define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) +#define ALIGN_DOWN(x, a) ((x) & ~((a) - 1)) +#define BIT(n) (1U << (n)) +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) < (b) ? (a) : (b)) + +#define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x))) + +#define OFFSET_OF(t, m) ((uptr)&((t *)NULL)->m) +#define CONTAINER_OF(mp, t, mn) ((t *)((uptr)mp - OFFSET_OF(t, mn))) + +#define byte_swap_16(num) ((((num) >> 8) & 0xFF) | (((num) & 0xFF) << 8)) +#define byte_swap_32(num) ((((num) >> 24) & 0xFF) | (((num) & 0xFF00) << 8 ) | \ + (((num) >> 8 ) & 0xFF00) | (((num) & 0xFF) << 24)) + +#define likely(x) (__builtin_expect((x) != 0, 1)) +#define unlikely(x) (__builtin_expect((x) != 0, 0)) + +/* Bootloader/Nyx */ #define BOOT_CFG_AUTOBOOT_EN BIT(0) #define BOOT_CFG_FROM_LAUNCH BIT(1) #define BOOT_CFG_FROM_ID BIT(2) @@ -100,15 +139,15 @@ typedef struct __attribute__((__packed__)) _boot_cfg_t { struct { - char id[8]; // 7 char ASCII null teminated. - char emummc_path[0x78]; // emuMMC/XXX, ASCII null teminated. + char id[8]; // 7 char ASCII null terminated. + char emummc_path[0x78]; // emuMMC/XXX, ASCII null terminated. }; - u8 ums; // nyx_ums_type. + u8 ums; // nyx_ums_type. u8 xt_str[0x80]; }; } boot_cfg_t; -static_assert(sizeof(boot_cfg_t) == 0x84, "Boot CFG size is wrong!"); +static_assert(sizeof(boot_cfg_t) == 0x84, "Boot cfg storage size is wrong!"); typedef struct __attribute__((__packed__)) _ipl_ver_meta_t { diff --git a/bdk/utils/util.c b/bdk/utils/util.c index 146c404..69498ac 100644 --- a/bdk/utils/util.c +++ b/bdk/utils/util.c @@ -1,21 +1,22 @@ /* -* Copyright (c) 2018 naehrwert -* Copyright (c) 2018-2020 CTCaer -* -* This program is free software; you can redistribute it and/or modify it -* under the terms and conditions of the GNU General Public License, -* version 2, as published by the Free Software Foundation. -* -* This program is distributed in the hope it will be useful, but WITHOUT -* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -* more details. -* -* You should have received a copy of the GNU General Public License -* along with this program. If not, see . -*/ + * Copyright (c) 2018 naehrwert + * Copyright (c) 2018-2025 CTCaer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include -#include #include #include #include @@ -23,12 +24,10 @@ #include #include #include +#include #include -#include - -#define USE_RTC_TIMER - -extern volatile nyx_storage_t *nyx_str; +#include +#include u8 bit_count(u32 val) { @@ -51,55 +50,156 @@ u32 bit_count_mask(u8 bits) return val; } -u32 get_tmr_s() +char *strcpy_ns(char *dst, char *src) { - return RTC(APBDEV_RTC_SECONDS); + if (!src || !dst) + return NULL; + + // Remove starting space. + u32 len = strlen(src); + if (len && src[0] == ' ') + { + len--; + src++; + } + + strcpy(dst, src); + + // Remove trailing space. + if (len && dst[len - 1] == ' ') + dst[len - 1] = 0; + + return dst; } -u32 get_tmr_ms() +// Approximate square root finder for a 64-bit number. +u64 sqrt64(u64 num) { - // The registers must be read with the following order: - // RTC_MILLI_SECONDS (0x10) -> RTC_SHADOW_SECONDS (0xC) - return (RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000)); + u64 base = 0; + u64 limit = num; + u64 square_root = 0; + + while (base <= limit) + { + u64 tmp_sqrt = (base + limit) / 2; + + if (tmp_sqrt * tmp_sqrt == num) { + square_root = tmp_sqrt; + break; + } + + if (tmp_sqrt * tmp_sqrt < num) + { + square_root = base; + base = tmp_sqrt + 1; + } + else + limit = tmp_sqrt - 1; + } + + return square_root; } -u32 get_tmr_us() +#define TULONG_MAX ((unsigned long)((unsigned long)(~0L))) +#define TLONG_MAX ((long)(((unsigned long)(~0L)) >> 1)) +#define TLONG_MIN ((long)(~TLONG_MAX)) +#define ISSPACE(ch) ((ch >= '\t' && ch <= '\r') || (ch == ' ')) +#define ISDIGIT(ch) ( ch >= '0' && ch <= '9' ) +#define ISALPHA(ch) ((ch >= 'a' && ch <= 'z') || (ch >= 'A' && ch <= 'Z')) +#define ISUPPER(ch) ( ch >= 'A' && ch <= 'Z' ) + +/* + * Avoid using reentrant newlib version of strol. It's only used for errno. + * + * strol/atoi: + * Copyright (c) 1990 The Regents of the University of California. + */ +long strtol(const char *nptr, char **endptr, register int base) { - return TMR(TIMERUS_CNTR_1US); + register const char *s = nptr; + register unsigned long acc; + register int c; + register unsigned long cutoff; + register int neg = 0, any, cutlim; + + /* + * Skip white space and pick up leading +/- sign if any. + * If base is 0, allow 0x for hex and 0 for octal, else + * assume decimal; if base is already 16, allow 0x. + */ + do { + c = *s++; + } while (ISSPACE(c)); + if (c == '-') { + neg = 1; + c = *s++; + } else if (c == '+') + c = *s++; + if ((base == 0 || base == 16) && + c == '0' && (*s == 'x' || *s == 'X')) { + c = s[1]; + s += 2; + base = 16; + } + if (base == 0) + base = c == '0' ? 8 : 10; + + /* + * Compute the cutoff value between legal numbers and illegal + * numbers. That is the largest legal value, divided by the + * base. An input number that is greater than this value, if + * followed by a legal input character, is too big. One that + * is equal to this value may be valid or not; the limit + * between valid and invalid numbers is then based on the last + * digit. For instance, if the range for longs is + * [-2147483648..2147483647] and the input base is 10, + * cutoff will be set to 214748364 and cutlim to either + * 7 (neg==0) or 8 (neg==1), meaning that if we have accumulated + * a value > 214748364, or equal but the next digit is > 7 (or 8), + * the number is too big, and we will return a range error. + * + * Set any if any `digits' consumed; make it negative to indicate + * overflow. + */ + cutoff = neg ? -(unsigned long)TLONG_MIN : (base == 16 ? TULONG_MAX : TLONG_MAX); + cutlim = cutoff % (unsigned long)base; + cutoff /= (unsigned long)base; + for (acc = 0, any = 0;; c = *s++) { + if (ISDIGIT(c)) + c -= '0'; + else if (ISALPHA(c)) + c -= ISUPPER(c) ? 'A' - 10 : 'a' - 10; + else + break; + if (c >= base) + break; + if (any < 0 || acc > cutoff || (acc == cutoff && c > cutlim)) + any = -1; + else { + any = 1; + acc *= base; + acc += c; + } + } + if (any < 0) { + acc = neg ? TLONG_MIN : TLONG_MAX; + } else if (neg) + acc = -acc; + if (endptr != 0) + *endptr = (char *) (any ? s - 1 : nptr); + return (acc); } -void msleep(u32 ms) +int atoi(const char *nptr) { -#ifdef USE_RTC_TIMER - u32 start = RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000); - // Casting to u32 is important! - while (((u32)(RTC(APBDEV_RTC_MILLI_SECONDS) + (RTC(APBDEV_RTC_SHADOW_SECONDS) * 1000)) - start) <= ms) - ; -#else - bpmp_msleep(ms); -#endif + return (int)strtol(nptr, (char **)NULL, 10); } -void usleep(u32 us) +void reg_write_array(u32 *base, const reg_cfg_t *cfg, u32 num_cfg) { -#ifdef USE_RTC_TIMER - u32 start = TMR(TIMERUS_CNTR_1US); - - // Check if timer is at upper limits and use BPMP sleep so it doesn't wake up immediately. - if ((start + us) < start) - bpmp_usleep(us); - else - while ((u32)(TMR(TIMERUS_CNTR_1US) - start) <= us) // Casting to u32 is important! - ; -#else - bpmp_usleep(us); -#endif -} - -void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops) -{ - for(u32 i = 0; i < num_ops; i++) - base[ops[i].off] = ops[i].val; + // Expected register offset is a u32 array index. + for (u32 i = 0; i < num_cfg; i++) + base[cfg[i].idx] = cfg[i].val; } u32 crc32_calc(u32 crc, const u8 *buf, u32 len) @@ -110,7 +210,7 @@ u32 crc32_calc(u32 crc, const u8 *buf, u32 len) // Calculate CRC table. if (!table) { - table = calloc(256, sizeof(u32)); + table = zalloc(256 * sizeof(u32)); for (u32 i = 0; i < 256; i++) { u32 rem = i; @@ -139,18 +239,33 @@ u32 crc32_calc(u32 crc, const u8 *buf, u32 len) return ~crc; } +int qsort_compare_int(const void *a, const void *b) +{ + return (*(int *)a - *(int *)b); +} + +int qsort_compare_char(const void *a, const void *b) +{ + return strcmp(*(const char **)a, *(const char **)b); +} + +int qsort_compare_char_case(const void *a, const void *b) +{ + return strcasecmp(*(const char **)a, *(const char **)b); +} + void panic(u32 val) { // Set panic code. PMC(APBDEV_PMC_SCRATCH200) = val; - //PMC(APBDEV_PMC_CRYPTO_OP) = PMC_CRYPTO_OP_SE_DISABLE; - TMR(TIMER_WDT4_UNLOCK_PATTERN) = TIMER_MAGIC_PTRN; - TMR(TIMER_TMR9_TMR_PTV) = TIMER_EN | TIMER_PER_EN; - TMR(TIMER_WDT4_CONFIG) = TIMER_SRC(9) | TIMER_PER(1) | TIMER_PMCRESET_EN; - TMR(TIMER_WDT4_COMMAND) = TIMER_START_CNT; - while (true) - usleep(1); + // Disable SE. + //PMC(APBDEV_PMC_CRYPTO_OP) = PMC_CRYPTO_OP_SE_DISABLE; + + // Immediately cause a full system reset. + watchdog_start(0, TIMER_PMCRESET_EN); + + while (true); } void power_set_state(power_state_t state) @@ -161,10 +276,7 @@ void power_set_state(power_state_t state) sd_end(); // De-initialize and power down various hardware. - hw_reinit_workaround(false, 0); - - // Stop the alarm, in case we injected and powered off too fast. - max77620_rtc_stop_alarm(); + hw_deinit(false, 0); // Set power state. switch (state) @@ -179,7 +291,7 @@ void power_set_state(power_state_t state) break; case POWER_OFF: - // Initiate power down sequence and do not generate a reset (regulators retain state). + // Initiate power down sequence and do not generate a reset (regulators retain state after POR). i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, MAX77620_ONOFFCNFG1_PWR_OFF); break; @@ -194,7 +306,7 @@ void power_set_state(power_state_t state) reg |= MAX77620_ONOFFCNFG2_SFT_RST_WK; i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG2, reg); - // Initiate power down sequence and generate a reset (regulators' state resets). + // Initiate power down sequence and generate a reset (regulators' state resets after POR). i2c_send_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_ONOFFCNFG1, MAX77620_ONOFFCNFG1_SFT_RST); break; } diff --git a/bdk/utils/util.h b/bdk/utils/util.h index 5e7e913..2d8d9bd 100644 --- a/bdk/utils/util.h +++ b/bdk/utils/util.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2025 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -46,20 +46,16 @@ typedef enum ERR_SYSOLD_NYX = BIT(1), ERR_LIBSYS_MTC = BIT(2), ERR_SD_BOOT_EN = BIT(3), + ERR_PANIC_CODE = BIT(4), ERR_L4T_KERNEL = BIT(24), ERR_EXCEPTION = BIT(31), } hekate_errors_t; -#define byte_swap_32(num) ((((num) >> 24) & 0xff) | (((num) << 8) & 0xff0000) | \ - (((num) >> 8 )& 0xff00) | (((num) << 24) & 0xff000000)) - -#define byte_swap_16(num) ((((num) >> 8) & 0xff) | (((num) << 8) & 0xff00)) - -typedef struct _cfg_op_t +typedef struct _reg_cfg_t { - u32 off; + u32 idx; u32 val; -} cfg_op_t; +} reg_cfg_t; typedef struct _nyx_info_t { @@ -77,23 +73,25 @@ typedef struct _nyx_storage_t u32 cfg; u8 irama[0x8000]; u8 hekate[0x30000]; - u8 rsvd[0x800000 - sizeof(nyx_info_t)]; + u8 rsvd[SZ_8M - sizeof(nyx_info_t)]; nyx_info_t info; mtc_config_t mtc_cfg; - emc_table_t mtc_table[10]; + emc_table_t mtc_table[11]; // 10 + 1. } nyx_storage_t; u8 bit_count(u32 val); u32 bit_count_mask(u8 bits); +char *strcpy_ns(char *dst, char *src); +u64 sqrt64(u64 num); +long strtol(const char *nptr, char **endptr, register int base); +int atoi(const char *nptr); -void exec_cfg(u32 *base, const cfg_op_t *ops, u32 num_ops); +void reg_write_array(u32 *base, const reg_cfg_t *cfg, u32 num_cfg); u32 crc32_calc(u32 crc, const u8 *buf, u32 len); -u32 get_tmr_us(); -u32 get_tmr_ms(); -u32 get_tmr_s(); -void usleep(u32 us); -void msleep(u32 ms); +int qsort_compare_int(const void *a, const void *b); +int qsort_compare_char(const void *a, const void *b); +int qsort_compare_char_case(const void *a, const void *b); void panic(u32 val); void power_set_state(power_state_t state); diff --git a/bootloader/config.c b/bootloader/config.c index 271ff5e..37aed3b 100644 --- a/bootloader/config.c +++ b/bootloader/config.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,149 +17,30 @@ #include #include +#include + #include "config.h" -#include -#include #include "gfx/tui.h" #include -#include -#include -#include -#include -#include -#include -#include -#include extern hekate_config h_cfg; void set_default_configuration() { - h_cfg.autoboot = 0; + h_cfg.t210b01 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01; + + h_cfg.autoboot = 0; h_cfg.autoboot_list = 0; - h_cfg.bootwait = 3; - h_cfg.backlight = 100; - h_cfg.autohosoff = 0; - h_cfg.autonogc = 1; - h_cfg.updater2p = 0; - h_cfg.bootprotect = 0; + h_cfg.bootwait = 3; + h_cfg.noticker = 0; //! TODO: Add GUI option. + h_cfg.backlight = 100; + h_cfg.autohosoff = h_cfg.t210b01 ? 1 : 0; + h_cfg.autonogc = 1; + h_cfg.updater2p = 0; + h_cfg.bootprotect = 0; + h_cfg.errors = 0; h_cfg.eks = NULL; h_cfg.rcm_patched = fuse_check_patched_rcm(); h_cfg.emummc_force_disable = false; - h_cfg.t210b01 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01; -} - -int create_config_entry() -{ - if (!sd_mount()) - return 1; - - char lbuf[64]; - FIL fp; - bool mainIniFound = false; - - LIST_INIT(ini_sections); - - if (ini_parse(&ini_sections, "bootloader/hekate_ipl.ini", false)) - mainIniFound = true; - else - { - u8 res = f_open(&fp, "bootloader/hekate_ipl.ini", FA_READ); - if (res == FR_NO_FILE || res == FR_NO_PATH) - { - f_mkdir("bootloader"); - f_mkdir("bootloader/ini"); - f_mkdir("bootloader/payloads"); - f_mkdir("bootloader/sys"); - } - else - { - if (!res) - f_close(&fp); - return 1; - } - } - - if (f_open(&fp, "bootloader/hekate_ipl.ini", FA_WRITE | FA_CREATE_ALWAYS) != FR_OK) - return 1; - - // Add config entry. - f_puts("[config]\nautoboot=", &fp); - itoa(h_cfg.autoboot, lbuf, 10); - f_puts(lbuf, &fp); - - f_puts("\nautoboot_list=", &fp); - itoa(h_cfg.autoboot_list, lbuf, 10); - f_puts(lbuf, &fp); - - f_puts("\nbootwait=", &fp); - itoa(h_cfg.bootwait, lbuf, 10); - f_puts(lbuf, &fp); - - f_puts("\nbacklight=", &fp); - itoa(h_cfg.backlight, lbuf, 10); - f_puts(lbuf, &fp); - - f_puts("\nautohosoff=", &fp); - itoa(h_cfg.autohosoff, lbuf, 10); - f_puts(lbuf, &fp); - - f_puts("\nautonogc=", &fp); - itoa(h_cfg.autonogc, lbuf, 10); - f_puts(lbuf, &fp); - - f_puts("\nupdater2p=", &fp); - itoa(h_cfg.updater2p, lbuf, 10); - f_puts(lbuf, &fp); - - f_puts("\nbootprotect=", &fp); - itoa(h_cfg.bootprotect, lbuf, 10); - f_puts(lbuf, &fp); - f_puts("\n", &fp); - - if (mainIniFound) - { - // Re-construct existing entries. - LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sections, link) - { - if (!strcmp(ini_sec->name, "config")) - continue; - - switch (ini_sec->type) - { - case INI_CHOICE: // Re-construct Boot entry [ ]. - f_puts("[", &fp); - f_puts(ini_sec->name, &fp); - f_puts("]\n", &fp); - // Re-construct boot entry's config. - LIST_FOREACH_ENTRY(ini_kv_t, kv, &ini_sec->kvs, link) - { - f_puts(kv->key, &fp); - f_puts("=", &fp); - f_puts(kv->val, &fp); - f_puts("\n", &fp); - } - break; - case INI_CAPTION: // Re-construct caption entry { }. - f_puts("{", &fp); - f_puts(ini_sec->name, &fp); - f_puts("}\n", &fp); - break; - case INI_NEWLINE: // Re-construct cosmetic newline \n. - f_puts("\n", &fp); - break; - case INI_COMMENT: // Re-construct comment entry #. - f_puts("#", &fp); - f_puts(ini_sec->name, &fp); - f_puts("\n", &fp); - break; - } - } - } - - f_close(&fp); - sd_end(); - - return 0; } diff --git a/bootloader/config.h b/bootloader/config.h index 11f7f26..6710ce3 100644 --- a/bootloader/config.h +++ b/bootloader/config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,8 +17,9 @@ #ifndef _CONFIG_H_ #define _CONFIG_H_ +#include + #include "hos/hos.h" -#include typedef struct _hekate_config { @@ -26,6 +27,7 @@ typedef struct _hekate_config u32 autoboot; u32 autoboot_list; u32 bootwait; + u32 noticker; u32 backlight; u32 autohosoff; u32 autonogc; @@ -40,6 +42,5 @@ typedef struct _hekate_config } hekate_config; void set_default_configuration(); -int create_config_entry(); #endif /* _CONFIG_H_ */ diff --git a/bootloader/frontend/fe_emmc_tools.c b/bootloader/frontend/fe_emmc_tools.c deleted file mode 100644 index 15364c4..0000000 --- a/bootloader/frontend/fe_emmc_tools.c +++ /dev/null @@ -1,920 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018 Rajko Stojadinovic - * Copyright (c) 2018-2021 CTCaer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include - -#include "fe_emmc_tools.h" -#include -#include "../config.h" -#include -#include "../gfx/tui.h" -#include -#include -#include -#include -#include "../storage/nx_emmc.h" -#include -#include -#include -#include - -#define NUM_SECTORS_PER_ITER 8192 // 4MB Cache. -#define OUT_FILENAME_SZ 128 -#define SHA256_SZ 0x20 - -extern hekate_config h_cfg; - -extern void emmcsn_path_impl(char *path, char *sub_dir, char *filename, sdmmc_storage_t *storage); - -#pragma GCC push_options -#pragma GCC optimize ("Os") - -static int _dump_emmc_verify(sdmmc_storage_t *storage, u32 lba_curr, char *outFilename, emmc_part_t *part) -{ - FIL fp; - u8 sparseShouldVerify = 4; - u32 prevPct = 200; - u32 sdFileSector = 0; - int res = 0; - - u8 hashEm[SHA256_SZ]; - u8 hashSd[SHA256_SZ]; - - if (f_open(&fp, outFilename, FA_READ) == FR_OK) - { - u32 totalSectorsVer = (u32)((u64)f_size(&fp) >> (u64)9); - - u8 *bufEm = (u8 *)EMMC_BUF_ALIGNED; - u8 *bufSd = (u8 *)SDXC_BUF_ALIGNED; - - u32 pct = (u64)((u64)(lba_curr - part->lba_start) * 100u) / (u64)(part->lba_end - part->lba_start); - tui_pbar(0, gfx_con.y, pct, 0xFF96FF00, 0xFF155500); - - u32 num = 0; - while (totalSectorsVer > 0) - { - num = MIN(totalSectorsVer, NUM_SECTORS_PER_ITER); - - // Check every time or every 4. - // Every 4 protects from fake sd, sector corruption and frequent I/O corruption. - // Full provides all that, plus protection from extremely rare I/O corruption. - if (!(sparseShouldVerify % 4)) - { - if (!sdmmc_storage_read(storage, lba_curr, num, bufEm)) - { - gfx_con.fntsz = 16; - EPRINTFARGS("\nFailed to read %d blocks (@LBA %08X),\nfrom eMMC!\n\nVerification failed..\n", - num, lba_curr); - - f_close(&fp); - return 1; - } - f_lseek(&fp, (u64)sdFileSector << (u64)9); - if (f_read(&fp, bufSd, num << 9, NULL)) - { - gfx_con.fntsz = 16; - EPRINTFARGS("\nFailed to read %d blocks (@LBA %08X),\nfrom sd card!\n\nVerification failed..\n", num, lba_curr); - - f_close(&fp); - return 1; - } - - se_calc_sha256_oneshot(hashEm, bufEm, num << 9); - se_calc_sha256_oneshot(hashSd, bufSd, num << 9); - res = memcmp(hashEm, hashSd, SE_SHA_256_SIZE / 2); - - if (res) - { - gfx_con.fntsz = 16; - EPRINTFARGS("\nSD and eMMC data (@LBA %08X),\ndo not match!\n\nVerification failed..\n", lba_curr); - - f_close(&fp); - return 1; - } - } - - pct = (u64)((u64)(lba_curr - part->lba_start) * 100u) / (u64)(part->lba_end - part->lba_start); - if (pct != prevPct) - { - tui_pbar(0, gfx_con.y, pct, 0xFF96FF00, 0xFF155500); - prevPct = pct; - } - - lba_curr += num; - totalSectorsVer -= num; - sdFileSector += num; - sparseShouldVerify++; - - if (btn_read_vol() == (BTN_VOL_UP | BTN_VOL_DOWN)) - { - gfx_con.fntsz = 16; - WPRINTF("\n\nVerification was cancelled!"); - gfx_con.fntsz = 8; - msleep(1000); - - f_close(&fp); - - return 0; - } - } - f_close(&fp); - - tui_pbar(0, gfx_con.y, pct, 0xFFCCCCCC, 0xFF555555); - - return 0; - } - else - { - gfx_con.fntsz = 16; - EPRINTF("\nFile not found or could not be loaded.\n\nVerification failed..\n"); - return 1; - } -} - -static void _update_filename(char *outFilename, u32 sdPathLen, u32 numSplitParts, u32 currPartIdx) -{ - if (numSplitParts >= 10 && currPartIdx < 10) - { - outFilename[sdPathLen] = '0'; - itoa(currPartIdx, &outFilename[sdPathLen + 1], 10); - } - else - itoa(currPartIdx, &outFilename[sdPathLen], 10); -} - -static int _dump_emmc_part(char *sd_path, sdmmc_storage_t *storage, emmc_part_t *part) -{ - static const u32 FAT32_FILESIZE_LIMIT = 0xFFFFFFFF; - static const u32 SECTORS_TO_MIB_COEFF = 11; - - u32 multipartSplitSize = (1u << 31); - u32 totalSectors = part->lba_end - part->lba_start + 1; - u32 currPartIdx = 0; - u32 numSplitParts = 0; - u32 maxSplitParts = 0; - bool isSmallSdCard = false; - bool partialDumpInProgress = false; - int res = 0; - char *outFilename = sd_path; - u32 sdPathLen = strlen(sd_path); - - FIL partialIdxFp; - char partialIdxFilename[12]; - strcpy(partialIdxFilename, "partial.idx"); - - gfx_con.fntsz = 8; - gfx_printf("\nSD Card free space: %d MiB, Total backup size %d MiB\n\n", - sd_fs.free_clst * sd_fs.csize >> SECTORS_TO_MIB_COEFF, - totalSectors >> SECTORS_TO_MIB_COEFF); - - // 1GB parts for sd cards 8GB and less. - if ((sd_storage.csd.capacity >> (20 - sd_storage.csd.read_blkbits)) <= 8192) - multipartSplitSize = (1u << 30); - // Maximum parts fitting the free space available. - maxSplitParts = (sd_fs.free_clst * sd_fs.csize) / (multipartSplitSize / NX_EMMC_BLOCKSIZE); - - // Check if the USER partition or the RAW eMMC fits the sd card free space. - if (totalSectors > (sd_fs.free_clst * sd_fs.csize)) - { - isSmallSdCard = true; - - gfx_printf("%k\nSD card free space is smaller than backup size.%k\n", 0xFFFFBA00, 0xFFCCCCCC); - - if (!maxSplitParts) - { - gfx_con.fntsz = 16; - EPRINTF("Not enough free space for Partial Backup."); - - return 0; - } - } - // Check if we are continuing a previous raw eMMC or USER partition backup in progress. - if (f_open(&partialIdxFp, partialIdxFilename, FA_READ) == FR_OK && totalSectors > (FAT32_FILESIZE_LIMIT / NX_EMMC_BLOCKSIZE)) - { - gfx_printf("%kFound Partial Backup in progress. Continuing...%k\n\n", 0xFFAEFD14, 0xFFCCCCCC); - - partialDumpInProgress = true; - // Force partial dumping, even if the card is larger. - isSmallSdCard = true; - - f_read(&partialIdxFp, &currPartIdx, 4, NULL); - f_close(&partialIdxFp); - - if (!maxSplitParts) - { - gfx_con.fntsz = 16; - EPRINTF("Not enough free space for Partial Backup."); - - return 0; - } - - // Increase maxSplitParts to accommodate previously backed up parts. - maxSplitParts += currPartIdx; - } - else if (isSmallSdCard) - gfx_printf("%kPartial Backup enabled (with %d MiB parts)...%k\n\n", 0xFFFFBA00, multipartSplitSize >> 20, 0xFFCCCCCC); - - // Check if filesystem is FAT32 or the free space is smaller and backup in parts. - if (((sd_fs.fs_type != FS_EXFAT) && totalSectors > (FAT32_FILESIZE_LIMIT / NX_EMMC_BLOCKSIZE)) || isSmallSdCard) - { - u32 multipartSplitSectors = multipartSplitSize / NX_EMMC_BLOCKSIZE; - numSplitParts = (totalSectors + multipartSplitSectors - 1) / multipartSplitSectors; - - outFilename[sdPathLen++] = '.'; - - // Continue from where we left, if Partial Backup in progress. - _update_filename(outFilename, sdPathLen, numSplitParts, partialDumpInProgress ? currPartIdx : 0); - } - - FIL fp; - gfx_con_getpos(&gfx_con.savedx, &gfx_con.savedy); - if (!f_open(&fp, outFilename, FA_READ)) - { - f_close(&fp); - gfx_con.fntsz = 16; - - WPRINTF("An existing backup has been detected!"); - WPRINTF("Press POWER to Continue.\nPress VOL to go to the menu.\n"); - msleep(500); - - if (!(btn_wait() & BTN_POWER)) - return 0; - gfx_con.fntsz = 8; - gfx_clear_partial_grey(0x1B, gfx_con.savedy, 48); - } - gfx_con_setpos(gfx_con.savedx, gfx_con.savedy); - gfx_printf("Filename: %s\n\n", outFilename); - res = f_open(&fp, outFilename, FA_CREATE_ALWAYS | FA_WRITE); - if (res) - { - gfx_con.fntsz = 16; - EPRINTFARGS("Error (%d) creating file %s.\n", res, outFilename); - - return 0; - } - - u8 *buf = (u8 *)MIXD_BUF_ALIGNED; - - u32 lba_curr = part->lba_start; - u32 lbaStartPart = part->lba_start; - u32 bytesWritten = 0; - u32 prevPct = 200; - int retryCount = 0; - - // Continue from where we left, if Partial Backup in progress. - if (partialDumpInProgress) - { - lba_curr += currPartIdx * (multipartSplitSize / NX_EMMC_BLOCKSIZE); - totalSectors -= currPartIdx * (multipartSplitSize / NX_EMMC_BLOCKSIZE); - lbaStartPart = lba_curr; // Update the start LBA for verification. - } - u64 totalSize = (u64)((u64)totalSectors << 9); - if (!isSmallSdCard && (sd_fs.fs_type == FS_EXFAT || totalSize <= FAT32_FILESIZE_LIMIT)) - f_lseek(&fp, totalSize); - else - f_lseek(&fp, MIN(totalSize, multipartSplitSize)); - f_lseek(&fp, 0); - - u32 num = 0; - u32 pct = 0; - while (totalSectors > 0) - { - if (numSplitParts != 0 && bytesWritten >= multipartSplitSize) - { - f_close(&fp); - memset(&fp, 0, sizeof(fp)); - currPartIdx++; - - // Verify part. - if (_dump_emmc_verify(storage, lbaStartPart, outFilename, part)) - { - EPRINTF("\nPress any key and try again...\n"); - - return 0; - } - - _update_filename(outFilename, sdPathLen, numSplitParts, currPartIdx); - - // Always create partial.idx before next part, in case a fatal error occurs. - if (isSmallSdCard) - { - // Create partial backup index file. - if (f_open(&partialIdxFp, partialIdxFilename, FA_CREATE_ALWAYS | FA_WRITE) == FR_OK) - { - f_write(&partialIdxFp, &currPartIdx, 4, NULL); - f_close(&partialIdxFp); - } - else - { - gfx_con.fntsz = 16; - EPRINTF("\nError creating partial.idx file.\n"); - - return 0; - } - - // More parts to backup that do not currently fit the sd card free space or fatal error. - if (currPartIdx >= maxSplitParts) - { - gfx_puts("\n\n1. Press any key to unmount SD Card.\n\ - 2. Remove SD Card and move files to free space.\n\ - Don\'t move the partial.idx file!\n\ - 3. Re-insert SD Card.\n\ - 4. Select the SAME option again to continue.\n"); - gfx_con.fntsz = 16; - - return 1; - } - } - - // Create next part. - gfx_con_setpos(gfx_con.savedx, gfx_con.savedy); - gfx_printf("Filename: %s\n\n", outFilename); - lbaStartPart = lba_curr; - res = f_open(&fp, outFilename, FA_CREATE_ALWAYS | FA_WRITE); - if (res) - { - gfx_con.fntsz = 16; - EPRINTFARGS("Error (%d) creating file %s.\n", res, outFilename); - - return 0; - } - - bytesWritten = 0; - - totalSize = (u64)((u64)totalSectors << 9); - f_lseek(&fp, MIN(totalSize, multipartSplitSize)); - f_lseek(&fp, 0); - } - - retryCount = 0; - num = MIN(totalSectors, NUM_SECTORS_PER_ITER); - while (!sdmmc_storage_read(storage, lba_curr, num, buf)) - { - EPRINTFARGS("Error reading %d blocks @ LBA %08X,\nfrom eMMC (try %d), retrying...", - num, lba_curr, ++retryCount); - - msleep(150); - if (retryCount >= 3) - { - gfx_con.fntsz = 16; - EPRINTFARGS("\nFailed to read %d blocks @ LBA %08X\nfrom eMMC. Aborting..\n", - num, lba_curr); - EPRINTF("\nPress any key and try again...\n"); - - f_close(&fp); - f_unlink(outFilename); - - return 0; - } - } - res = f_write(&fp, buf, NX_EMMC_BLOCKSIZE * num, NULL); - if (res) - { - gfx_con.fntsz = 16; - EPRINTFARGS("\nFatal error (%d) when writing to SD Card", res); - EPRINTF("\nPress any key and try again...\n"); - - f_close(&fp); - f_unlink(outFilename); - - return 0; - } - pct = (u64)((u64)(lba_curr - part->lba_start) * 100u) / (u64)(part->lba_end - part->lba_start); - if (pct != prevPct) - { - tui_pbar(0, gfx_con.y, pct, 0xFFCCCCCC, 0xFF555555); - prevPct = pct; - } - - lba_curr += num; - totalSectors -= num; - bytesWritten += num * NX_EMMC_BLOCKSIZE; - - // Force a flush after a lot of data if not splitting. - if (numSplitParts == 0 && bytesWritten >= multipartSplitSize) - { - f_sync(&fp); - bytesWritten = 0; - } - - // Check for cancellation combo. - if (btn_read_vol() == (BTN_VOL_UP | BTN_VOL_DOWN)) - { - gfx_con.fntsz = 16; - WPRINTF("\n\nThe backup was cancelled!"); - EPRINTF("\nPress any key...\n"); - msleep(1500); - - f_close(&fp); - f_unlink(outFilename); - - return 0; - } - } - tui_pbar(0, gfx_con.y, 100, 0xFFCCCCCC, 0xFF555555); - - // Backup operation ended successfully. - f_close(&fp); - - // Verify last part or single file backup. - if (_dump_emmc_verify(storage, lbaStartPart, outFilename, part)) - { - EPRINTF("\nPress any key and try again...\n"); - - return 0; - } - else - tui_pbar(0, gfx_con.y, 100, 0xFF96FF00, 0xFF155500); - - gfx_con.fntsz = 16; - // Remove partial backup index file if no fatal errors occurred. - if (isSmallSdCard) - { - f_unlink(partialIdxFilename); - gfx_printf("%k\n\nYou can now join the files\nand get the complete eMMC RAW GPP backup.", 0xFFCCCCCC); - } - gfx_puts("\n\n"); - - return 1; -} - -typedef enum -{ - PART_BOOT = BIT(0), - PART_SYSTEM = BIT(1), - PART_USER = BIT(2), - PART_RAW = BIT(3), - PART_GP_ALL = BIT(7) -} emmcPartType_t; - -static void _dump_emmc_selected(emmcPartType_t dumpType) -{ - int res = 0; - u32 timer = 0; - gfx_clear_partial_grey(0x1B, 0, 1256); - tui_sbar(true); - gfx_con_setpos(0, 0); - - if (!sd_mount()) - goto out; - - gfx_puts("Checking for available free space...\n\n"); - // Get SD Card free space for Partial Backup. - f_getfree("", &sd_fs.free_clst, NULL); - - sdmmc_storage_t storage; - sdmmc_t sdmmc; - if (!sdmmc_storage_init_mmc(&storage, &sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400)) - { - EPRINTF("Failed to init eMMC."); - goto out; - } - - int i = 0; - char sdPath[OUT_FILENAME_SZ]; - // Create Restore folders, if they do not exist. - emmcsn_path_impl(sdPath, "/restore", "", &storage); - emmcsn_path_impl(sdPath, "/restore/partitions", "", &storage); - - timer = get_tmr_s(); - if (dumpType & PART_BOOT) - { - const u32 BOOT_PART_SIZE = storage.ext_csd.boot_mult << 17; - - emmc_part_t bootPart; - memset(&bootPart, 0, sizeof(bootPart)); - bootPart.lba_start = 0; - bootPart.lba_end = (BOOT_PART_SIZE / NX_EMMC_BLOCKSIZE) - 1; - for (i = 0; i < 2; i++) - { - strcpy(bootPart.name, "BOOT"); - bootPart.name[4] = (u8)('0' + i); - bootPart.name[5] = 0; - - gfx_printf("%k%02d: %s (%07X-%07X)%k\n", 0xFF00DDFF, i, - bootPart.name, bootPart.lba_start, bootPart.lba_end, 0xFFCCCCCC); - - sdmmc_storage_set_mmc_partition(&storage, i + 1); - - emmcsn_path_impl(sdPath, "", bootPart.name, &storage); - res = _dump_emmc_part(sdPath, &storage, &bootPart); - } - } - - if ((dumpType & PART_SYSTEM) || (dumpType & PART_USER) || (dumpType & PART_RAW)) - { - sdmmc_storage_set_mmc_partition(&storage, EMMC_GPP); - - if ((dumpType & PART_SYSTEM) || (dumpType & PART_USER)) - { - LIST_INIT(gpt); - nx_emmc_gpt_parse(&gpt, &storage); - LIST_FOREACH_ENTRY(emmc_part_t, part, &gpt, link) - { - if ((dumpType & PART_USER) == 0 && !strcmp(part->name, "USER")) - continue; - if ((dumpType & PART_SYSTEM) == 0 && strcmp(part->name, "USER")) - continue; - - gfx_printf("%k%02d: %s (%07X-%07X)%k\n", 0xFF00DDFF, i++, - part->name, part->lba_start, part->lba_end, 0xFFCCCCCC); - - emmcsn_path_impl(sdPath, "/partitions", part->name, &storage); - res = _dump_emmc_part(sdPath, &storage, part); - // If a part failed, don't continue. - if (!res) - break; - } - nx_emmc_gpt_free(&gpt); - } - - if (dumpType & PART_RAW) - { - // Get GP partition size dynamically. - const u32 RAW_AREA_NUM_SECTORS = storage.sec_cnt; - - emmc_part_t rawPart; - memset(&rawPart, 0, sizeof(rawPart)); - rawPart.lba_start = 0; - rawPart.lba_end = RAW_AREA_NUM_SECTORS - 1; - strcpy(rawPart.name, "rawnand.bin"); - { - gfx_printf("%k%02d: %s (%07X-%07X)%k\n", 0xFF00DDFF, i++, - rawPart.name, rawPart.lba_start, rawPart.lba_end, 0xFFCCCCCC); - - emmcsn_path_impl(sdPath, "", rawPart.name, &storage); - res = _dump_emmc_part(sdPath, &storage, &rawPart); - } - } - } - - gfx_putc('\n'); - timer = get_tmr_s() - timer; - gfx_printf("Time taken: %dm %ds.\n", timer / 60, timer % 60); - sdmmc_storage_end(&storage); - if (res) - gfx_printf("\n%kFinished and verified!%k\nPress any key...\n", 0xFF96FF00, 0xFFCCCCCC); - -out: - sd_end(); - btn_wait(); -} - -void dump_emmc_system() { _dump_emmc_selected(PART_SYSTEM); } -void dump_emmc_user() { _dump_emmc_selected(PART_USER); } -void dump_emmc_boot() { _dump_emmc_selected(PART_BOOT); } -void dump_emmc_rawnand() { _dump_emmc_selected(PART_RAW); } - -static int _restore_emmc_part(char *sd_path, sdmmc_storage_t *storage, emmc_part_t *part, bool allow_multi_part) -{ - static const u32 SECTORS_TO_MIB_COEFF = 11; - - u32 totalSectors = part->lba_end - part->lba_start + 1; - u32 currPartIdx = 0; - u32 numSplitParts = 0; - u32 lbaStartPart = part->lba_start; - int res = 0; - char *outFilename = sd_path; - u32 sdPathLen = strlen(sd_path); - u64 fileSize = 0; - u64 totalCheckFileSize = 0; - gfx_con.fntsz = 8; - - FIL fp; - FILINFO fno; - - gfx_con_getpos(&gfx_con.savedx, &gfx_con.savedy); - - bool use_multipart = false; - - if (allow_multi_part) - { - // Check to see if there is a combined file and if so then use that. - if (f_stat(outFilename, &fno)) - { - // If not, check if there are partial files and the total size matches. - gfx_printf("No single file, checking for part files...\n"); - - outFilename[sdPathLen++] = '.'; - - // Stat total size of the part files. - while ((u32)((u64)totalCheckFileSize >> (u64)9) != totalSectors) - { - _update_filename(outFilename, sdPathLen, 99, numSplitParts); - - gfx_con_setpos(gfx_con.savedx, gfx_con.savedy); - gfx_printf("\nFilename: %s\n", outFilename); - - if (f_stat(outFilename, &fno)) - { - WPRINTFARGS("Error (%d) file not found '%s'. Aborting...\n", res, outFilename); - return 0; - } - else - totalCheckFileSize += (u64)fno.fsize; - - numSplitParts++; - } - - gfx_printf("\n%X sectors total.\n", (u32)((u64)totalCheckFileSize >> (u64)9)); - - if ((u32)((u64)totalCheckFileSize >> (u64)9) != totalSectors) - { - gfx_con.fntsz = 16; - EPRINTF("Size of SD Card split backups does not match,\neMMC's selected part size.\n"); - - return 0; - } - else - { - use_multipart = true; - _update_filename(outFilename, sdPathLen, numSplitParts, 0); - } - } - } - - res = f_open(&fp, outFilename, FA_READ); - gfx_con_setpos(gfx_con.savedx, gfx_con.savedy); - gfx_printf("\nFilename: %s\n", outFilename); - if (res) - { - if (res != FR_NO_FILE) - EPRINTFARGS("Error (%d) while opening backup. Continuing...\n", res); - else - WPRINTFARGS("Error (%d) file not found. Continuing...\n", res); - gfx_con.fntsz = 16; - - return 0; - } - else if (!use_multipart && (((u32)((u64)f_size(&fp) >> (u64)9)) != totalSectors)) // Check total restore size vs emmc size. - { - gfx_con.fntsz = 16; - EPRINTF("Size of the SD Card backup does not match,\neMMC's selected part size.\n"); - f_close(&fp); - - return 0; - } - else - { - fileSize = (u64)f_size(&fp); - gfx_printf("\nTotal restore size: %d MiB.\n\n", - (u32)((use_multipart ? (u64)totalCheckFileSize : fileSize) >> (u64)9) >> SECTORS_TO_MIB_COEFF); - } - - u8 *buf = (u8 *)MIXD_BUF_ALIGNED; - - u32 lba_curr = part->lba_start; - u32 bytesWritten = 0; - u32 prevPct = 200; - int retryCount = 0; - - u32 num = 0; - u32 pct = 0; - - gfx_con_getpos(&gfx_con.savedx, &gfx_con.savedy); - - while (totalSectors > 0) - { - // If we have more than one part, check the size for the split parts and make sure that the bytes written is not more than that. - if (numSplitParts != 0 && bytesWritten >= fileSize) - { - // If we have more bytes written then close the file pointer and increase the part index we are using - f_close(&fp); - memset(&fp, 0, sizeof(fp)); - currPartIdx++; - - // Verify part. - if (_dump_emmc_verify(storage, lbaStartPart, outFilename, part)) - { - EPRINTF("\nPress any key and try again...\n"); - - return 0; - } - - _update_filename(outFilename, sdPathLen, numSplitParts, currPartIdx); - - // Read from next part. - gfx_con_setpos(gfx_con.savedx, gfx_con.savedy); - gfx_printf("Filename: %s\n\n", outFilename); - - lbaStartPart = lba_curr; - - // Try to open the next file part - res = f_open(&fp, outFilename, FA_READ); - if (res) - { - gfx_con.fntsz = 16; - EPRINTFARGS("Error (%d) opening file %s.\n", res, outFilename); - - return 0; - } - fileSize = (u64)f_size(&fp); - bytesWritten = 0; - } - - retryCount = 0; - num = MIN(totalSectors, NUM_SECTORS_PER_ITER); - - res = f_read(&fp, buf, NX_EMMC_BLOCKSIZE * num, NULL); - if (res) - { - gfx_con.fntsz = 16; - EPRINTFARGS("\nFatal error (%d) when reading from SD Card", res); - EPRINTF("\nThis device may be in an inoperative state!\n\nPress any key and try again now...\n"); - - f_close(&fp); - return 0; - } - while (!sdmmc_storage_write(storage, lba_curr, num, buf)) - { - EPRINTFARGS("Error writing %d blocks @ LBA %08X\nto eMMC (try %d), retrying...", - num, lba_curr, ++retryCount); - - msleep(150); - if (retryCount >= 3) - { - gfx_con.fntsz = 16; - EPRINTFARGS("\nFailed to write %d blocks @ LBA %08X\nfrom eMMC. Aborting..\n", - num, lba_curr); - EPRINTF("\nThis device may be in an inoperative state!\n\nPress any key and try again...\n"); - - f_close(&fp); - return 0; - } - } - pct = (u64)((u64)(lba_curr - part->lba_start) * 100u) / (u64)(part->lba_end - part->lba_start); - if (pct != prevPct) - { - tui_pbar(0, gfx_con.y, pct, 0xFFCCCCCC, 0xFF555555); - prevPct = pct; - } - - lba_curr += num; - totalSectors -= num; - bytesWritten += num * NX_EMMC_BLOCKSIZE; - } - tui_pbar(0, gfx_con.y, 100, 0xFFCCCCCC, 0xFF555555); - - // Restore operation ended successfully. - f_close(&fp); - - // Verify restored data. - if (_dump_emmc_verify(storage, lbaStartPart, outFilename, part)) - { - EPRINTF("\nPress any key and try again...\n"); - - return 0; - } - else - tui_pbar(0, gfx_con.y, 100, 0xFF96FF00, 0xFF155500); - - gfx_con.fntsz = 16; - gfx_puts("\n\n"); - - return 1; -} - -static void _restore_emmc_selected(emmcPartType_t restoreType) -{ - int res = 0; - u32 timer = 0; - gfx_clear_partial_grey(0x1B, 0, 1256); - tui_sbar(true); - gfx_con_setpos(0, 0); - - gfx_printf("%kThis may render the device inoperative!\n\n", 0xFFFFDD00); - gfx_printf("Are you really sure?\n\n%k", 0xFFCCCCCC); - if ((restoreType & PART_BOOT) || (restoreType & PART_GP_ALL)) - { - gfx_puts("The mode you selected will only restore\nthe "); - if (restoreType & PART_BOOT) - gfx_puts("boot "); - gfx_puts("partitions that it can find.\n"); - gfx_puts("If it is not found, it will be skipped\nand continue with the next.\n\n"); - } - gfx_con_getpos(&gfx_con.savedx, &gfx_con.savedy); - - u8 failsafe_wait = 10; - while (failsafe_wait > 0) - { - gfx_con_setpos(gfx_con.savedx, gfx_con.savedy); - gfx_printf("%kWait... (%ds) %k", 0xFF888888, failsafe_wait, 0xFFCCCCCC); - msleep(1000); - failsafe_wait--; - } - gfx_con_setpos(gfx_con.savedx, gfx_con.savedy); - - gfx_puts("Press POWER to Continue.\nPress VOL to go to the menu.\n\n\n"); - - u32 btn = btn_wait(); - if (!(btn & BTN_POWER)) - goto out; - - if (!sd_mount()) - goto out; - - sdmmc_storage_t storage; - sdmmc_t sdmmc; - if (!sdmmc_storage_init_mmc(&storage, &sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400)) - { - EPRINTF("Failed to init eMMC."); - goto out; - } - - int i = 0; - char sdPath[OUT_FILENAME_SZ]; - - timer = get_tmr_s(); - if (restoreType & PART_BOOT) - { - const u32 BOOT_PART_SIZE = storage.ext_csd.boot_mult << 17; - - emmc_part_t bootPart; - memset(&bootPart, 0, sizeof(bootPart)); - bootPart.lba_start = 0; - bootPart.lba_end = (BOOT_PART_SIZE / NX_EMMC_BLOCKSIZE) - 1; - for (i = 0; i < 2; i++) - { - strcpy(bootPart.name, "BOOT"); - bootPart.name[4] = (u8)('0' + i); - bootPart.name[5] = 0; - - gfx_printf("%k%02d: %s (%07X-%07X)%k\n", 0xFF00DDFF, i, - bootPart.name, bootPart.lba_start, bootPart.lba_end, 0xFFCCCCCC); - - sdmmc_storage_set_mmc_partition(&storage, i + 1); - - emmcsn_path_impl(sdPath, "/restore", bootPart.name, &storage); - res = _restore_emmc_part(sdPath, &storage, &bootPart, false); - } - } - - if (restoreType & PART_GP_ALL) - { - sdmmc_storage_set_mmc_partition(&storage, EMMC_GPP); - - LIST_INIT(gpt); - nx_emmc_gpt_parse(&gpt, &storage); - LIST_FOREACH_ENTRY(emmc_part_t, part, &gpt, link) - { - gfx_printf("%k%02d: %s (%07X-%07X)%k\n", 0xFF00DDFF, i++, - part->name, part->lba_start, part->lba_end, 0xFFCCCCCC); - - emmcsn_path_impl(sdPath, "/restore/partitions/", part->name, &storage); - res = _restore_emmc_part(sdPath, &storage, part, false); - } - nx_emmc_gpt_free(&gpt); - } - - if (restoreType & PART_RAW) - { - // Get GP partition size dynamically. - const u32 RAW_AREA_NUM_SECTORS = storage.sec_cnt; - - emmc_part_t rawPart; - memset(&rawPart, 0, sizeof(rawPart)); - rawPart.lba_start = 0; - rawPart.lba_end = RAW_AREA_NUM_SECTORS - 1; - strcpy(rawPart.name, "rawnand.bin"); - { - gfx_printf("%k%02d: %s (%07X-%07X)%k\n", 0xFF00DDFF, i++, - rawPart.name, rawPart.lba_start, rawPart.lba_end, 0xFFCCCCCC); - - emmcsn_path_impl(sdPath, "/restore", rawPart.name, &storage); - res = _restore_emmc_part(sdPath, &storage, &rawPart, true); - } - } - - gfx_putc('\n'); - timer = get_tmr_s() - timer; - gfx_printf("Time taken: %dm %ds.\n", timer / 60, timer % 60); - sdmmc_storage_end(&storage); - if (res) - gfx_printf("\n%kFinished and verified!%k\nPress any key...\n", 0xFF96FF00, 0xFFCCCCCC); - -out: - sd_end(); - btn_wait(); -} - -void restore_emmc_boot() { _restore_emmc_selected(PART_BOOT); } -void restore_emmc_rawnand() { _restore_emmc_selected(PART_RAW); } -void restore_emmc_gpp_parts() { _restore_emmc_selected(PART_GP_ALL); } - -#pragma GCC pop_options diff --git a/bootloader/frontend/fe_info.c b/bootloader/frontend/fe_info.c index 938e071..67bcfba 100644 --- a/bootloader/frontend/fe_info.c +++ b/bootloader/frontend/fe_info.c @@ -1,7 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer - * Copyright (c) 2018 balika011 + * Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,31 +17,15 @@ #include +#include + #include "fe_info.h" #include "../config.h" -#include #include "../hos/hos.h" #include "../hos/pkg1.h" #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../storage/nx_emmc.h" -#include -#include -#include -#include extern hekate_config h_cfg; -extern void emmcsn_path_impl(char *path, char *sub_dir, char *filename, sdmmc_storage_t *storage); #pragma GCC push_options #pragma GCC optimize ("Os") @@ -51,7 +34,6 @@ void print_fuseinfo() { u32 fuse_size = h_cfg.t210b01 ? 0x368 : 0x300; u32 fuse_address = h_cfg.t210b01 ? 0x7000F898 : 0x7000F900; - u32 fuse_array_size = (h_cfg.t210b01 ? 256 : 192) * sizeof(u32); gfx_clear_partial_grey(0x1B, 0, 1256); gfx_con_setpos(0, 0); @@ -72,62 +54,10 @@ void print_fuseinfo() byte_swap_32(FUSE(FUSE_PRIVATE_KEY0)), byte_swap_32(FUSE(FUSE_PRIVATE_KEY1)), byte_swap_32(FUSE(FUSE_PRIVATE_KEY2)), byte_swap_32(FUSE(FUSE_PRIVATE_KEY3))); - gfx_printf("%kFuse cache:\n\n%k", 0xFF00DDFF, 0xFFCCCCCC); + gfx_printf("%kFuse cache:\n\n%k", TXT_CLR_CYAN_L, TXT_CLR_DEFAULT); gfx_hexdump(fuse_address, (u8 *)fuse_address, fuse_size); - gfx_puts("\nPress POWER to dump them to SD Card.\nPress VOL to go to the menu.\n"); - - u32 btn = btn_wait(); - if (btn & BTN_POWER) - { - if (sd_mount()) - { - char path[64]; - emmcsn_path_impl(path, "/dumps", "fuse_cached.bin", NULL); - if (!sd_save_to_file((u8 *)fuse_address, fuse_size, path)) - gfx_puts("\nfuse_cached.bin saved!\n"); - - u32 words[256]; - fuse_read_array(words); - emmcsn_path_impl(path, "/dumps", "fuse_array_raw.bin", NULL); - if (!sd_save_to_file((u8 *)words, fuse_array_size, path)) - gfx_puts("\nfuse_array_raw.bin saved!\n"); - - sd_end(); - } - - btn_wait(); - } -} - -void print_kfuseinfo() -{ - gfx_clear_partial_grey(0x1B, 0, 1256); - gfx_con_setpos(0, 0); - - gfx_printf("%kKFuse contents:\n\n%k", 0xFF00DDFF, 0xFFCCCCCC); - u32 buf[KFUSE_NUM_WORDS]; - if (!kfuse_read(buf)) - EPRINTF("CRC fail."); - else - gfx_hexdump(0, (u8 *)buf, KFUSE_NUM_WORDS * 4); - - gfx_puts("\nPress POWER to dump them to SD Card.\nPress VOL to go to the menu.\n"); - - u32 btn = btn_wait(); - if (btn & BTN_POWER) - { - if (sd_mount()) - { - char path[64]; - emmcsn_path_impl(path, "/dumps", "kfuses.bin", NULL); - if (!sd_save_to_file((u8 *)buf, KFUSE_NUM_WORDS * 4, path)) - gfx_puts("\nDone!\n"); - sd_end(); - } - - btn_wait(); - } + btn_wait(); } void print_mmc_info() @@ -137,7 +67,7 @@ void print_mmc_info() static const u32 SECTORS_TO_MIB_COEFF = 11; - if (!sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400)) + if (!emmc_initialize(false)) { EPRINTF("Failed to init eMMC."); goto out; @@ -147,7 +77,7 @@ void print_mmc_info() u16 card_type; u32 speed = 0; - gfx_printf("%kCID:%k\n", 0xFF00DDFF, 0xFFCCCCCC); + gfx_printf("%kCID:%k\n", TXT_CLR_CYAN_L, TXT_CLR_DEFAULT); switch (emmc_storage.csd.mmca_vsn) { case 2: /* MMC v2.0 - v2.2 */ @@ -174,7 +104,7 @@ void print_mmc_info() else { gfx_printf("%kExtended CSD V1.%d:%k\n", - 0xFF00DDFF, emmc_storage.ext_csd.ext_struct, 0xFFCCCCCC); + TXT_CLR_CYAN_L, emmc_storage.ext_csd.ext_struct, TXT_CLR_DEFAULT); card_type = emmc_storage.ext_csd.card_type; char card_type_support[96]; card_type_support[0] = 0; @@ -214,7 +144,7 @@ void print_mmc_info() " Current Rate: %d MB/s\n" " Type Support: ", emmc_storage.csd.mmca_vsn, emmc_storage.ext_csd.rev, emmc_storage.ext_csd.dev_version, emmc_storage.csd.cmdclass, - emmc_storage.csd.capacity == (4096 * 512) ? "High" : "Low", speed & 0xFFFF, (speed >> 16) & 0xFFFF, + emmc_storage.csd.capacity == (4096 * EMMC_BLOCKSIZE) ? "High" : "Low", speed & 0xFFFF, (speed >> 16) & 0xFFFF, emmc_storage.csd.busspeed); gfx_con.fntsz = 8; gfx_printf("%s", card_type_support); @@ -223,38 +153,38 @@ void print_mmc_info() u32 boot_size = emmc_storage.ext_csd.boot_mult << 17; u32 rpmb_size = emmc_storage.ext_csd.rpmb_mult << 17; - gfx_printf("%keMMC Partitions:%k\n", 0xFF00DDFF, 0xFFCCCCCC); - gfx_printf(" 1: %kBOOT0 %k\n Size: %5d KiB (LBA Sectors: 0x%07X)\n", 0xFF96FF00, 0xFFCCCCCC, - boot_size / 1024, boot_size / 512); + gfx_printf("%keMMC Partitions:%k\n", TXT_CLR_CYAN_L, TXT_CLR_DEFAULT); + gfx_printf(" 1: %kBOOT0 %k\n Size: %5d KiB (LBA Sectors: 0x%07X)\n", TXT_CLR_GREENISH, TXT_CLR_DEFAULT, + boot_size / 1024, boot_size / EMMC_BLOCKSIZE); gfx_put_small_sep(); - gfx_printf(" 2: %kBOOT1 %k\n Size: %5d KiB (LBA Sectors: 0x%07X)\n", 0xFF96FF00, 0xFFCCCCCC, - boot_size / 1024, boot_size / 512); + gfx_printf(" 2: %kBOOT1 %k\n Size: %5d KiB (LBA Sectors: 0x%07X)\n", TXT_CLR_GREENISH, TXT_CLR_DEFAULT, + boot_size / 1024, boot_size / EMMC_BLOCKSIZE); gfx_put_small_sep(); - gfx_printf(" 3: %kRPMB %k\n Size: %5d KiB (LBA Sectors: 0x%07X)\n", 0xFF96FF00, 0xFFCCCCCC, - rpmb_size / 1024, rpmb_size / 512); + gfx_printf(" 3: %kRPMB %k\n Size: %5d KiB (LBA Sectors: 0x%07X)\n", TXT_CLR_GREENISH, TXT_CLR_DEFAULT, + rpmb_size / 1024, rpmb_size / EMMC_BLOCKSIZE); gfx_put_small_sep(); - gfx_printf(" 0: %kGPP (USER) %k\n Size: %5d MiB (LBA Sectors: 0x%07X)\n\n", 0xFF96FF00, 0xFFCCCCCC, + gfx_printf(" 0: %kGPP (USER) %k\n Size: %5d MiB (LBA Sectors: 0x%07X)\n\n", TXT_CLR_GREENISH, TXT_CLR_DEFAULT, emmc_storage.sec_cnt >> SECTORS_TO_MIB_COEFF, emmc_storage.sec_cnt); gfx_put_small_sep(); - gfx_printf("%kGPP (eMMC USER) partition table:%k\n", 0xFF00DDFF, 0xFFCCCCCC); + gfx_printf("%kGPP (eMMC USER) partition table:%k\n", TXT_CLR_CYAN_L, TXT_CLR_DEFAULT); - sdmmc_storage_set_mmc_partition(&emmc_storage, EMMC_GPP); + emmc_set_partition(EMMC_GPP); LIST_INIT(gpt); - nx_emmc_gpt_parse(&gpt, &emmc_storage); + emmc_gpt_parse(&gpt); int gpp_idx = 0; LIST_FOREACH_ENTRY(emmc_part_t, part, &gpt, link) { gfx_printf(" %02d: %k%s%k\n Size: % 5d MiB (LBA Sectors 0x%07X)\n LBA Range: %08X-%08X\n", - gpp_idx++, 0xFFAEFD14, part->name, 0xFFCCCCCC, (part->lba_end - part->lba_start + 1) >> SECTORS_TO_MIB_COEFF, + gpp_idx++, TXT_CLR_GREENISH, part->name, TXT_CLR_DEFAULT, (part->lba_end - part->lba_start + 1) >> SECTORS_TO_MIB_COEFF, part->lba_end - part->lba_start + 1, part->lba_start, part->lba_end); gfx_put_small_sep(); } - nx_emmc_gpt_free(&gpt); + emmc_gpt_free(&gpt); } } out: - sdmmc_storage_end(&emmc_storage); + emmc_end(); btn_wait(); } @@ -268,7 +198,7 @@ void print_sdcard_info() if (sd_initialize(false)) { - gfx_printf("%kCard IDentification:%k\n", 0xFF00DDFF, 0xFFCCCCCC); + gfx_printf("%kCard IDentification:%k\n", TXT_CLR_CYAN_L, TXT_CLR_DEFAULT); gfx_printf( " Vendor ID: %02x\n" " OEM ID: %c%c\n" @@ -284,7 +214,7 @@ void print_sdcard_info() sd_storage.cid.month, sd_storage.cid.year); u16 *sd_errors = sd_get_error_count(); - gfx_printf("%kCard-Specific Data V%d.0:%k\n", 0xFF00DDFF, sd_storage.csd.structure + 1, 0xFFCCCCCC); + gfx_printf("%kCard-Specific Data V%d.0:%k\n", TXT_CLR_CYAN_L, sd_storage.csd.structure + 1, TXT_CLR_DEFAULT); gfx_printf( " Cmd Classes: %02X\n" " Capacity: %d MiB\n" @@ -308,7 +238,7 @@ void print_sdcard_info() gfx_puts("Acquiring FAT volume info...\n\n"); f_getfree("", &sd_fs.free_clst, NULL); gfx_printf("%kFound %s volume:%k\n Free: %d MiB\n Cluster: %d KiB\n", - 0xFF00DDFF, sd_fs.fs_type == FS_EXFAT ? "exFAT" : "FAT32", 0xFFCCCCCC, + TXT_CLR_CYAN_L, sd_fs.fs_type == FS_EXFAT ? "exFAT" : "FAT32", TXT_CLR_DEFAULT, sd_fs.free_clst * sd_fs.csize >> SECTORS_TO_MIB_COEFF, (sd_fs.csize > 1) ? (sd_fs.csize >> 1) : 512); f_mount(NULL, "", 1); } @@ -318,7 +248,7 @@ void print_sdcard_info() "Make sure that a FAT partition exists..", res); } - sdmmc_storage_end(&sd_storage); + sd_end(); } else { @@ -327,6 +257,7 @@ void print_sdcard_info() EPRINTF("Make sure that it is inserted."); else EPRINTF("SD Card Reader is not properly seated!"); + sd_end(); } btn_wait(); @@ -336,7 +267,7 @@ void print_fuel_gauge_info() { int value = 0; - gfx_printf("%kFuel Gauge Info:\n%k", 0xFF00DDFF, 0xFFCCCCCC); + gfx_printf("%kFuel Gauge Info:\n%k", TXT_CLR_CYAN_L, TXT_CLR_DEFAULT); max17050_get_property(MAX17050_RepSOC, &value); gfx_printf("Capacity now: %3d%\n", value >> 8); @@ -351,16 +282,10 @@ void print_fuel_gauge_info() gfx_printf("Capacity (design): %4d mAh\n", value); max17050_get_property(MAX17050_Current, &value); - if (value >= 0) - gfx_printf("Current now: %d mA\n", value / 1000); - else - gfx_printf("Current now: -%d mA\n", ~value / 1000); + gfx_printf("Current now: %d mA\n", value / 1000); max17050_get_property(MAX17050_AvgCurrent, &value); - if (value >= 0) - gfx_printf("Current average: %d mA\n", value / 1000); - else - gfx_printf("Current average: -%d mA\n", ~value / 1000); + gfx_printf("Current average: %d mA\n", value / 1000); max17050_get_property(MAX17050_VCELL, &value); gfx_printf("Voltage now: %4d mV\n", value); @@ -378,35 +303,30 @@ void print_fuel_gauge_info() gfx_printf("Empty voltage (design): %4d mV\n", value); max17050_get_property(MAX17050_TEMP, &value); - if (value >= 0) - gfx_printf("Battery temperature: %d.%d oC\n", value / 10, value % 10); - else - gfx_printf("Battery temperature: -%d.%d oC\n", ~value / 10, (~value) % 10); + gfx_printf("Battery temperature: %d.%d oC\n", value / 10, + (value >= 0 ? value : (~value)) % 10); } void print_battery_charger_info() { int value = 0; - gfx_printf("%k\n\nBattery Charger Info:\n%k", 0xFF00DDFF, 0xFFCCCCCC); - - bq24193_get_property(BQ24193_InputVoltageLimit, &value); - gfx_printf("Input voltage limit: %4d mV\n", value); + gfx_printf("%k\n\nBattery Charger Info:\n%k", TXT_CLR_CYAN_L, TXT_CLR_DEFAULT); bq24193_get_property(BQ24193_InputCurrentLimit, &value); - gfx_printf("Input current limit: %4d mA\n", value); + gfx_printf("Input current limit: %4d mA\n", value); bq24193_get_property(BQ24193_SystemMinimumVoltage, &value); - gfx_printf("Min voltage limit: %4d mV\n", value); + gfx_printf("System voltage limit: %4d mV\n", value); bq24193_get_property(BQ24193_FastChargeCurrentLimit, &value); - gfx_printf("Fast charge current limit: %4d mA\n", value); + gfx_printf("Charge current limit: %4d mA\n", value); bq24193_get_property(BQ24193_ChargeVoltageLimit, &value); - gfx_printf("Charge voltage limit: %4d mV\n", value); + gfx_printf("Charge voltage limit: %4d mV\n", value); bq24193_get_property(BQ24193_ChargeStatus, &value); - gfx_printf("Charge status: "); + gfx_printf("Charge status: "); switch (value) { case 0: @@ -426,7 +346,7 @@ void print_battery_charger_info() break; } bq24193_get_property(BQ24193_TempStatus, &value); - gfx_printf("Temperature status: "); + gfx_printf("Temperature status: "); switch (value) { case 0: @@ -461,7 +381,7 @@ void print_battery_info() u8 *buf = (u8 *)malloc(0x100 * 2); - gfx_printf("%k\n\nBattery Fuel Gauge Registers:\n%k", 0xFF00DDFF, 0xFFCCCCCC); + gfx_printf("%k\n\nBattery Fuel Gauge Registers:\n%k", TXT_CLR_CYAN_L, TXT_CLR_DEFAULT); for (int i = 0; i < 0x200; i += 2) { @@ -471,94 +391,7 @@ void print_battery_info() gfx_hexdump(0, (u8 *)buf, 0x200); - gfx_puts("\nPress POWER to dump them to SD Card.\nPress VOL to go to the menu.\n"); - - u32 btn = btn_wait(); - - if (btn & BTN_POWER) - { - if (sd_mount()) - { - char path[64]; - emmcsn_path_impl(path, "/dumps", "fuel_gauge.bin", NULL); - if (sd_save_to_file((u8 *)buf, 0x200, path)) - EPRINTF("\nError creating fuel.bin file."); - else - gfx_puts("\nDone!\n"); - sd_end(); - } - - btn_wait(); - } - free(buf); -} - -void _ipatch_process(u32 offset, u32 value) -{ - gfx_printf("%8x %8x", BOOTROM_BASE + offset, value); - u8 lo = value & 0xff; - switch (value >> 8) - { - case 0x20: - gfx_printf(" MOVS R0, #0x%02X", lo); - break; - case 0xDF: - gfx_printf(" SVC #0x%02X", lo); - break; - } - gfx_puts("\n"); -} - -void bootrom_ipatches_info() -{ - gfx_clear_partial_grey(0x1B, 0, 1256); - gfx_con_setpos(0, 0); - - static const u32 BOOTROM_SIZE = 0x18000; - - u32 res = fuse_read_ipatch(_ipatch_process); - if (res != 0) - EPRINTFARGS("Failed to read ipatches. Error: %d", res); - - gfx_puts("\nPress POWER to dump them to SD Card.\nPress VOL to go to the menu.\n"); - - u32 btn = btn_wait(); - if (btn & BTN_POWER) - { - if (sd_mount()) - { - char path[64]; - u32 iram_evp_thunks[0x200]; - u32 iram_evp_thunks_len = sizeof(iram_evp_thunks); - res = fuse_read_evp_thunk(iram_evp_thunks, &iram_evp_thunks_len); - if (res == 0) - { - emmcsn_path_impl(path, "/dumps", "evp_thunks.bin", NULL); - if (!sd_save_to_file((u8 *)iram_evp_thunks, iram_evp_thunks_len, path)) - gfx_puts("\nevp_thunks.bin saved!\n"); - } - else - EPRINTFARGS("Failed to read evp_thunks. Error: %d", res); - - emmcsn_path_impl(path, "/dumps", "bootrom_patched.bin", NULL); - if (!sd_save_to_file((u8 *)BOOTROM_BASE, BOOTROM_SIZE, path)) - gfx_puts("\nbootrom_patched.bin saved!\n"); - - u32 ipatch_backup[14]; - memcpy(ipatch_backup, (void *)IPATCH_BASE, sizeof(ipatch_backup)); - memset((void*)IPATCH_BASE, 0, sizeof(ipatch_backup)); - - emmcsn_path_impl(path, "/dumps", "bootrom_unpatched.bin", NULL); - if (!sd_save_to_file((u8 *)BOOTROM_BASE, BOOTROM_SIZE, path)) - gfx_puts("\nbootrom_unpatched.bin saved!\n"); - - memcpy((void*)IPATCH_BASE, ipatch_backup, sizeof(ipatch_backup)); - - sd_end(); - } - - btn_wait(); - } + btn_wait(); } #pragma GCC pop_options diff --git a/bootloader/frontend/fe_info.h b/bootloader/frontend/fe_info.h index 5818bee..db649aa 100644 --- a/bootloader/frontend/fe_info.h +++ b/bootloader/frontend/fe_info.h @@ -1,7 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer - * Copyright (c) 2018 balika011 + * Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -20,12 +19,10 @@ #define _FE_INFO_H_ void print_fuseinfo(); -void print_kfuseinfo(); void print_mmc_info(); void print_sdcard_info(); void print_fuel_gauge_info(); void print_battery_charger_info(); void print_battery_info(); -void bootrom_ipatches_info(); #endif diff --git a/bootloader/frontend/fe_tools.c b/bootloader/frontend/fe_tools.c index 3ec6dd0..eb47fb0 100644 --- a/bootloader/frontend/fe_tools.c +++ b/bootloader/frontend/fe_tools.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2024 CTCaer * Copyright (c) 2018 Reisyukaku * * This program is free software; you can redistribute it and/or modify it @@ -19,254 +19,27 @@ #include #include +#include + #include "fe_tools.h" #include "../config.h" -#include #include "../gfx/tui.h" -#include "../hos/hos.h" -#include "../hos/pkg1.h" -#include "../hos/pkg2.h" #include -#include -#include -#include -#include -#include "../storage/nx_emmc.h" -#include -#include -#include -#include -#include extern boot_cfg_t b_cfg; extern hekate_config h_cfg; -extern void emmcsn_path_impl(char *path, char *sub_dir, char *filename, sdmmc_storage_t *storage); - #pragma GCC push_options #pragma GCC optimize ("Os") -void dump_packages12() -{ - if (!sd_mount()) - return; - - char path[64]; - - u8 *pkg1 = (u8 *)calloc(1, 0x40000); - u8 *warmboot = (u8 *)calloc(1, 0x40000); - u8 *secmon = (u8 *)calloc(1, 0x40000); - u8 *loader = (u8 *)calloc(1, 0x40000); - u8 *pkg2 = NULL; - u8 kb = 0; - - tsec_ctxt_t tsec_ctxt; - - gfx_clear_partial_grey(0x1B, 0, 1256); - gfx_con_setpos(0, 0); - - if (!sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400)) - { - EPRINTF("Failed to init eMMC."); - goto out_free; - } - sdmmc_storage_set_mmc_partition(&emmc_storage, EMMC_BOOT0); - - // Read package1. - sdmmc_storage_read(&emmc_storage, 0x100000 / NX_EMMC_BLOCKSIZE, 0x40000 / NX_EMMC_BLOCKSIZE, pkg1); - const pkg1_id_t *pkg1_id = pkg1_identify(pkg1); - if (!pkg1_id) - { - EPRINTF("Unknown pkg1 version for reading\nTSEC firmware."); - // Dump package1. - emmcsn_path_impl(path, "/pkg1", "pkg1_enc.bin", &emmc_storage); - if (sd_save_to_file(pkg1, 0x40000, path)) - goto out_free; - gfx_puts("\nEnc pkg1 dumped to pkg1_enc.bin\n"); - - goto out_free; - } - - kb = pkg1_id->kb; - - tsec_ctxt.fw = (void *)pkg1 + pkg1_id->tsec_off; - tsec_ctxt.pkg1 = (void *)pkg1; - tsec_ctxt.pkg11_off = pkg1_id->pkg11_off; - tsec_ctxt.secmon_base = pkg1_id->secmon_base; - - // Read keyblob. - u8 *keyblob = (u8 *)calloc(NX_EMMC_BLOCKSIZE, 1); - sdmmc_storage_read(&emmc_storage, 0x180000 / NX_EMMC_BLOCKSIZE + kb, 1, keyblob); - - // Decrypt. - hos_keygen(keyblob, kb, &tsec_ctxt, false, false); - free(keyblob); - - if (kb <= KB_FIRMWARE_VERSION_600) - pkg1_decrypt(pkg1_id, pkg1); - - if (kb <= KB_FIRMWARE_VERSION_620) - { - const u8 *sec_map = pkg1_unpack(warmboot, NULL, secmon, loader, pkg1_id, pkg1); - - pk11_hdr_t *hdr_pk11 = (pk11_hdr_t *)(pkg1 + pkg1_id->pkg11_off + 0x20); - - // Use correct sizes. - u32 sec_size[3] = { hdr_pk11->wb_size, hdr_pk11->ldr_size, hdr_pk11->sm_size }; - for (u32 i = 0; i < 3; i++) - { - if (sec_map[i] == PK11_SECTION_WB) - hdr_pk11->wb_size = sec_size[i]; - else if (sec_map[i] == PK11_SECTION_LD) - hdr_pk11->ldr_size = sec_size[i]; - else if (sec_map[i] == PK11_SECTION_SM) - hdr_pk11->sm_size = sec_size[i]; - } - - // Display info. - gfx_printf("%kNX Bootloader size: %k0x%05X\n\n", 0xFFC7EA46, 0xFFCCCCCC, hdr_pk11->ldr_size); - - gfx_printf("%kSecure monitor addr: %k0x%05X\n", 0xFFC7EA46, 0xFFCCCCCC, pkg1_id->secmon_base); - gfx_printf("%kSecure monitor size: %k0x%05X\n\n", 0xFFC7EA46, 0xFFCCCCCC, hdr_pk11->sm_size); - - gfx_printf("%kWarmboot addr: %k0x%05X\n", 0xFFC7EA46, 0xFFCCCCCC, pkg1_id->warmboot_base); - gfx_printf("%kWarmboot size: %k0x%05X\n\n", 0xFFC7EA46, 0xFFCCCCCC, hdr_pk11->wb_size); - - // Dump package1.1. - emmcsn_path_impl(path, "/pkg1", "pkg1_decr.bin", &emmc_storage); - if (sd_save_to_file(pkg1, 0x40000, path)) - goto out_free; - gfx_puts("\npkg1 dumped to pkg1_decr.bin\n"); - - // Dump nxbootloader. - emmcsn_path_impl(path, "/pkg1", "nxloader.bin", &emmc_storage); - if (sd_save_to_file(loader, hdr_pk11->ldr_size, path)) - goto out_free; - gfx_puts("NX Bootloader dumped to nxloader.bin\n"); - - // Dump secmon. - emmcsn_path_impl(path, "/pkg1", "secmon.bin", &emmc_storage); - if (sd_save_to_file(secmon, hdr_pk11->sm_size, path)) - goto out_free; - gfx_puts("Secure Monitor dumped to secmon.bin\n"); - - // Dump warmboot. - emmcsn_path_impl(path, "/pkg1", "warmboot.bin", &emmc_storage); - if (sd_save_to_file(warmboot, hdr_pk11->wb_size, path)) - goto out_free; - gfx_puts("Warmboot dumped to warmboot.bin\n\n\n"); - } - - // Dump package2.1. - sdmmc_storage_set_mmc_partition(&emmc_storage, EMMC_GPP); - // Parse eMMC GPT. - LIST_INIT(gpt); - nx_emmc_gpt_parse(&gpt, &emmc_storage); - // Find package2 partition. - emmc_part_t *pkg2_part = nx_emmc_part_find(&gpt, "BCPKG2-1-Normal-Main"); - if (!pkg2_part) - goto out; - - // Read in package2 header and get package2 real size. - u8 *tmp = (u8 *)malloc(NX_EMMC_BLOCKSIZE); - nx_emmc_part_read(&emmc_storage, pkg2_part, 0x4000 / NX_EMMC_BLOCKSIZE, 1, tmp); - u32 *hdr_pkg2_raw = (u32 *)(tmp + 0x100); - u32 pkg2_size = hdr_pkg2_raw[0] ^ hdr_pkg2_raw[2] ^ hdr_pkg2_raw[3]; - free(tmp); - // Read in package2. - u32 pkg2_size_aligned = ALIGN(pkg2_size, NX_EMMC_BLOCKSIZE); - pkg2 = malloc(pkg2_size_aligned); - nx_emmc_part_read(&emmc_storage, pkg2_part, 0x4000 / NX_EMMC_BLOCKSIZE, - pkg2_size_aligned / NX_EMMC_BLOCKSIZE, pkg2); - -#if 0 - emmcsn_path_impl(path, "/pkg2", "pkg2_encr.bin", &emmc_storage); - if (sd_save_to_file(pkg2, pkg2_size_aligned, path)) - goto out; - gfx_puts("\npkg2 dumped to pkg2_encr.bin\n"); -#endif - - // Decrypt package2 and parse KIP1 blobs in INI1 section. - pkg2_hdr_t *pkg2_hdr = pkg2_decrypt(pkg2, kb, false); - if (!pkg2_hdr) - { - gfx_printf("Pkg2 decryption failed!\n"); - goto out; - } - - // Display info. - gfx_printf("%kKernel size: %k0x%05X\n\n", 0xFFC7EA46, 0xFFCCCCCC, pkg2_hdr->sec_size[PKG2_SEC_KERNEL]); - gfx_printf("%kINI1 size: %k0x%05X\n\n", 0xFFC7EA46, 0xFFCCCCCC, pkg2_hdr->sec_size[PKG2_SEC_INI1]); - - // Dump pkg2.1. - emmcsn_path_impl(path, "/pkg2", "pkg2_decr.bin", &emmc_storage); - if (sd_save_to_file(pkg2, pkg2_hdr->sec_size[PKG2_SEC_KERNEL] + pkg2_hdr->sec_size[PKG2_SEC_INI1], path)) - goto out; - gfx_puts("\npkg2 dumped to pkg2_decr.bin\n"); - - // Dump kernel. - emmcsn_path_impl(path, "/pkg2", "kernel.bin", &emmc_storage); - if (sd_save_to_file(pkg2_hdr->data, pkg2_hdr->sec_size[PKG2_SEC_KERNEL], path)) - goto out; - gfx_puts("Kernel dumped to kernel.bin\n"); - - // Dump INI1. - emmcsn_path_impl(path, "/pkg2", "ini1.bin", &emmc_storage); - u32 ini1_off = pkg2_hdr->sec_size[PKG2_SEC_KERNEL]; - u32 ini1_size = pkg2_hdr->sec_size[PKG2_SEC_INI1]; - if (!ini1_size) - { - pkg2_get_newkern_info(pkg2_hdr->data); - ini1_off = pkg2_newkern_ini1_start; - ini1_size = pkg2_newkern_ini1_end - pkg2_newkern_ini1_start; - } - if (ini1_off) - { - if (sd_save_to_file(pkg2_hdr->data + ini1_off, ini1_size, path)) - goto out; - gfx_puts("INI1 dumped to ini1.bin\n"); - } - else - { - gfx_puts("Failed to dump INI1!\n"); - goto out; - } - - gfx_puts("\nDone. Press any key...\n"); - -out: - nx_emmc_gpt_free(&gpt); -out_free: - free(pkg1); - free(secmon); - free(warmboot); - free(loader); - free(pkg2); - sdmmc_storage_end(&emmc_storage); - sd_end(); - - if (kb >= KB_FIRMWARE_VERSION_620) - se_aes_key_clear(8); - - btn_wait(); -} - -void _toggle_autorcm(bool enable) +static void _toggle_autorcm(bool enable) { gfx_clear_partial_grey(0x1B, 0, 1256); gfx_con_setpos(0, 0); - if (!sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400)) - { - EPRINTF("Failed to init eMMC."); - goto out; - } - - u8 *tempbuf = (u8 *)malloc(0x200); - sdmmc_storage_set_mmc_partition(&emmc_storage, EMMC_BOOT0); - int i, sect = 0; u8 corr_mod0, mod1; + u8 *tempbuf = (u8 *)malloc(0x200); // Get the correct RSA modulus byte masks. nx_emmc_get_autorcm_masks(&corr_mod0, &mod1); @@ -274,7 +47,7 @@ void _toggle_autorcm(bool enable) // Iterate BCTs. for (i = 0; i < 4; i++) { - sect = (0x200 + (0x4000 * i)) / NX_EMMC_BLOCKSIZE; + sect = (0x200 + (0x4000 * i)) / EMMC_BLOCKSIZE; sdmmc_storage_read(&emmc_storage, sect, 1, tempbuf); // Check if 2nd byte of modulus is correct. @@ -289,20 +62,41 @@ void _toggle_autorcm(bool enable) } free(tempbuf); - sdmmc_storage_end(&emmc_storage); if (enable) - gfx_printf("%kAutoRCM mode enabled!%k", 0xFFFFBA00, 0xFFCCCCCC); + gfx_printf("%kAutoRCM mode enabled!%k", TXT_CLR_ORANGE, TXT_CLR_DEFAULT); else - gfx_printf("%kAutoRCM mode disabled!%k", 0xFF96FF00, 0xFFCCCCCC); + gfx_printf("%kAutoRCM mode disabled!%k", TXT_CLR_GREENISH, TXT_CLR_DEFAULT); gfx_printf("\n\nPress any key...\n"); -out: btn_wait(); } -void _enable_autorcm() { _toggle_autorcm(true); } -void _disable_autorcm() { _toggle_autorcm(false); } +static void _enable_autorcm() { _toggle_autorcm(true); } +static void _disable_autorcm() { _toggle_autorcm(false); } + +bool tools_autorcm_enabled() +{ + u8 mod0, mod1; + u8 *tempbuf = (u8 *)malloc(0x200); + + // Get the correct RSA modulus byte masks. + nx_emmc_get_autorcm_masks(&mod0, &mod1); + + // Get 1st RSA modulus. + emmc_set_partition(EMMC_BOOT0); + sdmmc_storage_read(&emmc_storage, 0x200 / EMMC_BLOCKSIZE, 1, tempbuf); + + // Check if 2nd byte of modulus is correct. + bool enabled = false; + if (tempbuf[0x11] == mod1) + if (tempbuf[0x10] != mod0) + enabled = true; + + free(tempbuf); + + return enabled; +} void menu_autorcm() { @@ -311,18 +105,13 @@ void menu_autorcm() if (h_cfg.rcm_patched) { - gfx_printf("%kThis device is RCM patched and\nAutoRCM function is disabled.\n\n" - "In case %kAutoRCM%k is enabled\nthis will %kBRICK%k the device PERMANENTLY!!%k", - 0xFFFFDD00, 0xFFFF0000, 0xFFFFDD00, 0xFFFF0000, 0xFFFFDD00, 0xFFCCCCCC); + WPRINTF("This device is RCM patched and the\nfunction is disabled to avoid BRICKS!\n"); btn_wait(); return; } - // Do a simple check on the main BCT. - bool disabled = true; - - if (!sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400)) + if (!emmc_initialize(false)) { EPRINTF("Failed to init eMMC."); btn_wait(); @@ -330,21 +119,8 @@ void menu_autorcm() return; } - u8 mod0, mod1; - // Get the correct RSA modulus byte masks. - nx_emmc_get_autorcm_masks(&mod0, &mod1); - - u8 *tempbuf = (u8 *)malloc(0x200); - sdmmc_storage_set_mmc_partition(&emmc_storage, EMMC_BOOT0); - sdmmc_storage_read(&emmc_storage, 0x200 / NX_EMMC_BLOCKSIZE, 1, tempbuf); - - // Check if 2nd byte of modulus is correct. - if (tempbuf[0x11] == mod1) - if (tempbuf[0x10] != mod0) - disabled = false; - - free(tempbuf); - sdmmc_storage_end(&emmc_storage); + // Do a simple check on the main BCT. + bool enabled = tools_autorcm_enabled(); // Create AutoRCM menu. ment_t *ments = (ment_t *)malloc(sizeof(ment_t) * 6); @@ -356,17 +132,17 @@ void menu_autorcm() ments[2].type = MENT_CAPTION; ments[3].type = MENT_CHGLINE; - if (disabled) + if (!enabled) { ments[2].caption = "Status: Disabled!"; - ments[2].color = 0xFF96FF00; + ments[2].color = TXT_CLR_GREENISH; ments[4].caption = "Enable AutoRCM"; ments[4].handler = _enable_autorcm; } else { ments[2].caption = "Status: Enabled!"; - ments[2].color = 0xFFFFBA00; + ments[2].color = TXT_CLR_ORANGE; ments[4].caption = "Disable AutoRCM"; ments[4].handler = _disable_autorcm; } @@ -377,6 +153,10 @@ void menu_autorcm() menu_t menu = {ments, "This corrupts BOOT0!", 0, 0}; tui_do_menu(&menu); + + emmc_end(); + + free(ments); } #pragma GCC pop_options diff --git a/bootloader/frontend/fe_tools.h b/bootloader/frontend/fe_tools.h index 637bcab..e9f2bfb 100644 --- a/bootloader/frontend/fe_tools.h +++ b/bootloader/frontend/fe_tools.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,7 +18,7 @@ #ifndef _FE_TOOLS_H_ #define _FE_TOOLS_H_ -void dump_packages12(); void menu_autorcm(); +bool tools_autorcm_enabled(); #endif diff --git a/bootloader/gfx/gfx.c b/bootloader/gfx/gfx.c index dcc272b..37d7c37 100644 --- a/bootloader/gfx/gfx.c +++ b/bootloader/gfx/gfx.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -155,9 +155,9 @@ void gfx_con_init() gfx_con.y = 0; gfx_con.savedx = 0; gfx_con.savedy = 0; - gfx_con.fgcol = 0xFFCCCCCC; + gfx_con.fgcol = TXT_CLR_DEFAULT; gfx_con.fillbg = 1; - gfx_con.bgcol = 0xFF1B1B1B; + gfx_con.bgcol = TXT_CLR_BG; gfx_con.mute = 0; gfx_con_init_done = true; @@ -265,7 +265,7 @@ void gfx_putc(char c) } } -void gfx_puts(char *s) +void gfx_puts(const char *s) { if (!s || !gfx_con_init_done || gfx_con.mute) return; @@ -276,14 +276,24 @@ void gfx_puts(char *s) static void _gfx_putn(u32 v, int base, char fill, int fcnt) { - char buf[65]; - static const char digits[] = "0123456789ABCDEFghijklmnopqrstuvwxyz"; - char *p; - int c = fcnt; + static const char digits[] = "0123456789ABCDEF"; - if (base > 36) + char *p; + char buf[65]; + int c = fcnt; + bool negative = false; + + if (base != 10 && base != 16) return; + // Account for negative numbers. + if (base == 10 && v & 0x80000000) + { + negative = true; + v = (int)v * -1; + c--; + } + p = buf + 64; *p = 0; do @@ -293,9 +303,12 @@ static void _gfx_putn(u32 v, int base, char fill, int fcnt) v /= base; } while (v); + if (negative) + *--p = '-'; + if (fill != 0) { - while (c > 0) + while (c > 0 && p > buf) { *--p = fill; c--; @@ -330,9 +343,9 @@ void gfx_printf(const char *fmt, ...) int fill, fcnt; va_start(ap, fmt); - while(*fmt) + while (*fmt) { - if(*fmt == '%') + if (*fmt == '%') { fmt++; fill = 0; @@ -397,6 +410,17 @@ void gfx_printf(const char *fmt, ...) va_end(ap); } +static void _gfx_cputs(u32 color, const char *s) +{ + gfx_con.fgcol = color; + gfx_puts(s); + gfx_putc('\n'); + gfx_con.fgcol = TXT_CLR_DEFAULT; +} + +void gfx_wputs(const char *s) { _gfx_cputs(TXT_CLR_WARNING, s); } +void gfx_eputs(const char *s) { _gfx_cputs(TXT_CLR_ERROR, s); } + void gfx_hexdump(u32 base, const void *buf, u32 len) { if (!gfx_con_init_done || gfx_con.mute) @@ -406,17 +430,17 @@ void gfx_hexdump(u32 base, const void *buf, u32 len) u8 prevFontSize = gfx_con.fntsz; gfx_con.fntsz = 8; - for(u32 i = 0; i < len; i++) + for (u32 i = 0; i < len; i++) { - if(i % 0x10 == 0) + if (i % 0x10 == 0) { - if(i != 0) + if (i != 0) { gfx_puts("| "); - for(u32 j = 0; j < 0x10; j++) + for (u32 j = 0; j < 0x10; j++) { u8 c = buff[i - 0x10 + j]; - if(c >= 32 && c <= 126) + if (c >= 32 && c <= 126) gfx_putc(c); else gfx_putc('.'); @@ -437,10 +461,10 @@ void gfx_hexdump(u32 base, const void *buf, u32 len) gfx_puts(" "); } gfx_puts("| "); - for(u32 j = 0; j < (ln ? k : k + 1); j++) + for (u32 j = 0; j < (ln ? k : k + 1); j++) { u8 c = buff[i - k + j]; - if(c >= 32 && c <= 126) + if (c >= 32 && c <= 126) gfx_putc(c); else gfx_putc('.'); diff --git a/bootloader/gfx/gfx.h b/bootloader/gfx/gfx.h index fe1b979..b2fa915 100644 --- a/bootloader/gfx/gfx.h +++ b/bootloader/gfx/gfx.h @@ -19,12 +19,27 @@ #ifndef _GFX_H_ #define _GFX_H_ -#include +#include -#define EPRINTF(text) gfx_printf("%k"text"%k\n", 0xFFFF0000, 0xFFCCCCCC) -#define EPRINTFARGS(text, args...) gfx_printf("%k"text"%k\n", 0xFFFF0000, args, 0xFFCCCCCC) -#define WPRINTF(text) gfx_printf("%k"text"%k\n", 0xFFFFDD00, 0xFFCCCCCC) -#define WPRINTFARGS(text, args...) gfx_printf("%k"text"%k\n", 0xFFFFDD00, args, 0xFFCCCCCC) +#define TXT_CLR_BG 0xFF1B1B1B // Dark Grey. +#define TXT_CLR_DEFAULT 0xFFCCCCCC // Light Grey. +#define TXT_CLR_WARNING 0xFFFFDD00 // Yellow. +#define TXT_CLR_ERROR 0xFFFF0000 // Red. +#define TXT_CLR_CYAN_L 0xFF00CCFF // Light Cyan. +#define TXT_CLR_TURQUOISE 0xFF00FFCC // Turquoise. +#define TXT_CLR_ORANGE 0xFFFFBA00 // Orange. +#define TXT_CLR_GREENISH 0xFF96FF00 // Toxic Green. +#define TXT_CLR_GREEN_D 0xFF008800 // Dark Green. +#define TXT_CLR_RED_D 0xFF880000 // Dark Red. +#define TXT_CLR_GREY_D 0xFF303030 // Darkest Grey. +#define TXT_CLR_GREY_DM 0xFF444444 // Darker Grey. +#define TXT_CLR_GREY_M 0xFF555555 // Dark Grey. +#define TXT_CLR_GREY 0xFF888888 // Grey. + +#define EPRINTF(text) gfx_eputs(text) +#define EPRINTFARGS(text, args...) gfx_printf("%k"text"%k\n", TXT_CLR_ERROR, args, TXT_CLR_DEFAULT) +#define WPRINTF(text) gfx_wputs(text) +#define WPRINTFARGS(text, args...) gfx_printf("%k"text"%k\n", TXT_CLR_WARNING, args, TXT_CLR_DEFAULT) typedef struct _gfx_ctxt_t { @@ -61,8 +76,10 @@ void gfx_con_setcol(u32 fgcol, int fillbg, u32 bgcol); void gfx_con_getpos(u32 *x, u32 *y); void gfx_con_setpos(u32 x, u32 y); void gfx_putc(char c); -void gfx_puts(char *s); -void gfx_printf(const char *fmt, ...); +void gfx_puts(const char *s); +void gfx_wputs(const char *s); +void gfx_eputs(const char *s); +void gfx_printf(const char *fmt, ...) /* __attribute__((format(printf, 1, 2))) */; void gfx_hexdump(u32 base, const void *buf, u32 len); void gfx_set_pixel(u32 x, u32 y, u32 color); diff --git a/bootloader/gfx/logos.c b/bootloader/gfx/logos.c new file mode 100644 index 0000000..8b14e15 --- /dev/null +++ b/bootloader/gfx/logos.c @@ -0,0 +1,431 @@ +/* + * Copyright (c) 2018-2022 CTCaer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +#include +#include +#include "logos.h" + +// 68 x 192 @8bpp Grayscale RAW. +#define BOOTLOGO_WIDTH 68 +#define BOOTLOGO_HEIGHT 192 +#define BOOTLOGO_X ((720 - BOOTLOGO_WIDTH) / 2) +#define BOOTLOGO_Y ((1280 - BOOTLOGO_HEIGHT) / 2) +#define BOOTLOGO_SIZE 13056 +#define BOOTLOGO_BLZ_SIZE 3988 + +u8 bootlogo_blz[] = { + 0x0F, 0xF0, 0x80, 0x1B, 0x1B, 0x40, 0xF0, 0x1E, 0x1F, 0x48, 0x5A, 0x0F, 0xF0, 0x0F, 0xF0, 0xE4, + 0x17, 0xF0, 0x91, 0x13, 0x26, 0x28, 0x23, 0x1E, 0x0A, 0xA0, 0x0F, 0xF0, 0xC3, 0x22, 0xF0, 0xC3, + 0xA4, 0x1E, 0x29, 0x33, 0xDB, 0x2C, 0xEA, 0x53, 0x83, 0x0F, 0xF0, 0x38, 0xF0, 0xBC, 0x39, 0x21, + 0x22, 0xB0, 0x87, 0x20, 0x2F, 0x27, 0x3E, 0xDB, 0x35, 0x01, 0xA6, 0x69, 0xF2, 0x3C, 0xFD, 0x25, + 0x2D, 0x38, 0x77, 0x28, 0x15, 0x8A, 0x33, 0x45, 0xDB, 0x09, 0xEF, 0xBB, 0x44, 0xD0, 0xC0, 0x18, + 0xEF, 0x2E, 0x3B, 0xF5, 0x32, 0x25, 0x41, 0xC0, 0x83, 0x52, 0xE1, 0x07, 0xCD, 0x08, 0xF4, 0xF5, + 0x3B, 0x61, 0xB2, 0x95, 0xF1, 0x01, 0x10, 0xE7, 0xA3, 0x02, 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0x21, + 0x34, 0x47, 0xDB, 0x08, 0x3A, 0x28, 0x43, 0xB0, 0x9B, 0xBB, 0xB3, 0xAC, 0xAC, 0x04, 0xB3, 0xBB, + 0xA4, 0x3F, 0x20, 0x1C, 0x1E, 0x1F, 0x04, 0x40, 0x88, 0x03, 0x30, 0x00, 0x00, 0x20, 0x20, 0x20, + 0x1F, 0x1F, 0xD9, 0x80, 0x83, 0x20, 0x32, 0x44, 0xDB, 0x38, 0x26, 0x12, 0xC0, 0x4A, 0x40, 0x62, + 0x6D, 0x6D, 0x62, 0x4A, 0x02, 0x20, 0x0F, 0xF0, 0x15, 0xF0, 0xE0, 0x20, 0x2E, 0x3B, 0xDB, 0x32, + 0x24, 0x05, 0x50, 0x0F, 0xF0, 0xC0, 0x0F, 0xF0, 0x15, 0xF0, 0x1E, 0x26, 0x2E, 0x31, 0x29, 0x20, + 0x03, 0x06, 0x60, 0x0F, 0xF0, 0x26, 0xF0, 0x42, 0xF0, 0x20, 0x23, 0x24, 0x20, 0x0F, 0x1D, 0x06, + 0x60, 0x0F, 0xF0, 0x0F, 0xF0, 0x13, 0xF0, 0x1C, 0x1D, 0x1D, 0x1E, 0x1C, 0x00, 0x00, 0x09, 0x90, + 0x03, 0x30, 0x00, 0x00, 0x1B, 0x1B, 0x1B, 0x1E, 0x94, 0x0F, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, + 0x6C, 0x23, 0x00, 0x00 +}; + +u8 battery_icons_blz[] = { + 0x17, 0xC0, 0x5D, 0x51, 0x79, 0x12, 0x79, 0x48, 0x69, 0x00, 0x0D, 0x46, 0xE3, 0x0F, 0xF0, 0x20, + 0xF0, 0x35, 0x2E, 0x38, 0x3F, 0x40, 0xEF, 0xCF, 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0x3C, 0xF0, 0x0F, 0xF0, 0x27, 0xF0, 0x3C, 0xF0, 0xFF, 0x3C, 0xF0, 0x30, 0xF0, 0x3C, 0xF0, + 0x3C, 0xF0, 0x0F, 0xF0, 0x27, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0xFF, 0x30, 0xF0, 0x3C, 0xF0, 0x3C, + 0xF0, 0x0F, 0xF0, 0x27, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x30, 0xF0, 0xFF, 0x3C, 0xF0, 0x3C, 0xF0, + 0x0F, 0xF0, 0x27, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x30, 0xF0, 0x3C, 0xF0, 0xFF, 0x3C, 0xF0, 0x0F, + 0xF0, 0x27, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x30, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0xFF, 0x0F, 0xF0, + 0x27, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x30, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x0F, 0xF0, 0xFF, 0x27, + 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x30, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x0F, 0xF0, 0x27, 0xF0, 0xFF, + 0x3C, 0xF0, 0x3C, 0xF0, 0x30, 0xF0, 0x3C, 0xF0, 0x84, 0x90, 0x3F, 0x00, 0x00, 0x00, 0x0F, 0xF0, + 0xFF, 0x09, 0x90, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x02, 0x07, 0x01, 0xB1, 0x40, + 0x81, 0x20, 0x33, 0x0C, 0x08, 0x00, 0x00, 0x0F, 0xF0, 0xC6, 0x09, 0x90, 0x03, 0x30, 0x00, 0x00, + 0x0D, 0x03, 0x02, 0x2D, 0x0A, 0x07, 0x07, 0x75, 0x30, 0x39, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0x0F, + 0xF0, 0x1B, 0xF0, 0x03, 0x00, 0xFE, 0x39, 0x00, 0xB1, 0x29, 0x1B, 0xF3, 0x39, 0x26, 0x00, 0x00, + 0x81, 0x0F, 0xF0, 0x09, 0x90, 0x03, 0x30, 0x00, 0x00, 0xFE, 0x3B, 0x27, 0xF5, 0x0F, 0x39, 0x26, + 0xB3, 0x2A, 0x1C, 0x17, 0x05, 0x03, 0x00, 0xFF, 0xE4, 0x02, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, + 0x6A, 0x09, 0x00, 0x00 +}; + +u8 *render_static_bootlogo() +{ + // Clear background. + gfx_clear_grey(0x1B); + + // Set default logo. + u8 *logo_buf = (void *)malloc(SZ_16K); + blz_uncompress_srcdest(bootlogo_blz, sizeof(bootlogo_blz), logo_buf, BOOTLOGO_SIZE); + gfx_set_rect_grey(logo_buf, BOOTLOGO_WIDTH, BOOTLOGO_HEIGHT, BOOTLOGO_X, BOOTLOGO_Y); + + return logo_buf; +} + +bool render_ticker_logo(u32 boot_wait, u32 backlight) +{ + u32 btn = 0; + + u32 ticker_step_us = boot_wait * 1000000; + ticker_step_us /= BOOTLOGO_HEIGHT; + + // Set default logo. + u8 *logo_buf = render_static_bootlogo(); + + // Clear line. + u8 *grey = malloc(6 * BOOTLOGO_HEIGHT); + memset(grey, 0x1B, 6 * BOOTLOGO_HEIGHT); + gfx_set_rect_grey(grey, 6, BOOTLOGO_HEIGHT, 362, BOOTLOGO_Y); + free(grey); + + // Enable backlight to show first frame. + display_backlight_brightness(backlight, 1000); + + // Animated line as ticker. + for (u32 i = 1; i <= BOOTLOGO_HEIGHT; i++) + { + // If only VOL- was pressed, exit. + btn = btn_read_vol(); + if (btn == BTN_VOL_DOWN) + break; + + // Wait before setting next tick. + usleep(ticker_step_us); + + // Set next ticker progress. + gfx_set_rect_grey(logo_buf + BOOTLOGO_WIDTH * (BOOTLOGO_HEIGHT - i) + 36, 6, 1, 362, BOOTLOGO_Y + BOOTLOGO_HEIGHT - i); + } + free(logo_buf); + + return (btn == BTN_VOL_DOWN); +} + +bool render_ticker(u32 boot_wait, u32 backlight, bool no_ticker) +{ + u32 btn = 0; + + u32 ticker_step_us = boot_wait * 1000000; + ticker_step_us /= 1280; + + // Save bottom lines. + u32 *logo_line = (u32 *)malloc(1280 * sizeof(u32) * 2); + for (u32 i = 1280; !no_ticker && i >= 1; i--) + { + logo_line[i - 1] = gfx_ctxt.fb[i * gfx_ctxt.width - 2]; + logo_line[i - 1 + 1280] = gfx_ctxt.fb[i * gfx_ctxt.width - 1]; + } + + // Enable backlight to show first frame. + display_backlight_brightness(backlight, 1000); + + // Animated line as ticker. + for (u32 i = 1280; i >= 1; i--) + { + // If only VOL- was pressed, exit. + btn = btn_read_vol(); + if (btn == BTN_VOL_DOWN) + break; + + // Wait before setting next tick. + usleep(ticker_step_us); + + // Set bottom lines ticker progress. + if (!no_ticker) + { + gfx_ctxt.fb[i * gfx_ctxt.width - 2] = TXT_CLR_DEFAULT; + gfx_ctxt.fb[i * gfx_ctxt.width - 1] = TXT_CLR_DEFAULT; + } + } + + // Restore bottom lines. + for (u32 i = 1280; !no_ticker && i >= 1; i--) + { + gfx_ctxt.fb[i * gfx_ctxt.width - 2] = logo_line[i - 1]; + gfx_ctxt.fb[i * gfx_ctxt.width - 1] = logo_line[i - 1 + 1280]; + } + free(logo_line); + + return (btn == BTN_VOL_DOWN); +} diff --git a/bootloader/gfx/logos.h b/bootloader/gfx/logos.h index 7420cc6..7876379 100644 --- a/bootloader/gfx/logos.h +++ b/bootloader/gfx/logos.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018 CTCaer + * Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -14,322 +14,19 @@ * along with this program. If not, see . */ -#ifndef _HEKATE_LOGOS_H_ -#define _HEKATE_LOGOS_H_ - -// 68 x 192 @8bpp Grayscale RAW. -#define X_BOOTLOGO 68 -#define Y_BOOTLOGO 192 -#define SZ_BOOTLOGO 13056 -#define SZ_BOOTLOGO_BLZ 3988 -static u8 BOOTLOGO_BLZ[SZ_BOOTLOGO_BLZ] = { - 0x0F, 0xF0, 0x80, 0x1B, 0x1B, 0x40, 0xF0, 0x1E, 0x1F, 0x48, 0x5A, 0x0F, 0xF0, 0x0F, 0xF0, 0xE4, - 0x17, 0xF0, 0x91, 0x13, 0x26, 0x28, 0x23, 0x1E, 0x0A, 0xA0, 0x0F, 0xF0, 0xC3, 0x22, 0xF0, 0xC3, - 0xA4, 0x1E, 0x29, 0x33, 0xDB, 0x2C, 0xEA, 0x53, 0x83, 0x0F, 0xF0, 0x38, 0xF0, 0xBC, 0x39, 0x21, - 0x22, 0xB0, 0x87, 0x20, 0x2F, 0x27, 0x3E, 0xDB, 0x35, 0x01, 0xA6, 0x69, 0xF2, 0x3C, 0xFD, 0x25, - 0x2D, 0x38, 0x77, 0x28, 0x15, 0x8A, 0x33, 0x45, 0xDB, 0x09, 0xEF, 0xBB, 0x44, 0xD0, 0xC0, 0x18, - 0xEF, 0x2E, 0x3B, 0xF5, 0x32, 0x25, 0x41, 0xC0, 0x83, 0x52, 0xE1, 0x07, 0xCD, 0x08, 0xF4, 0xF5, - 0x3B, 0x61, 0xB2, 0x95, 0xF1, 0x01, 0x10, 0xE7, 0xA3, 0x02, 0x95, 0x91, 0x3C, 0xFD, 0x41, 0x90, - 0x41, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x3D, 0x7F, 0x3D, 0x9B, 0xFA, 0x41, 0xF0, 0x41, 0xF0, 0x0F, - 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0x81, 0x59, 0x15, 0x0E, 0x3C, 0xC0, 0x2A, 0x00, 0xF5, 0xC7, 0xE1, 0x34, 0x38, 0x23, 0x31, 0x0B, - 0x07, 0xC9, 0x2F, 0x1F, 0x33, 0x00, 0x80, 0x2D, 0x00, 0x1E, 0x90, 0x4D, 0x12, 0x0C, 0x2D, 0xC0, - 0x41, 0x0F, 0x23, 0x0A, 0x03, 0x30, 0x00, 0x00, 0xD9, 0x33, 0x22, 0xE7, 0x36, 0x06, 0x24, 0x06, - 0x00, 0xCB, 0x2F, 0x1F, 0x39, 0x30, 0x15, 0x05, 0x22, 0x03, 0x06, 0x60, 0x0F, 0xF0, 0x21, 0xF0, - 0x0F, 0x03, 0x02, 0x03, 0x00, 0x8E, 0xF9, 0x3A, 0x3C, 0xA0, 0x0F, 0xF0, 0x27, 0xF0, 0x3C, 0xF0, - 0x3C, 0xF0, 0x30, 0xF0, 0xFC, 0x3C, 0xF0, 0x3C, 0xF0, 0x0F, 0xF0, 0x27, 0xF0, 0x3C, 0xF0, 0x3C, - 0xF0, 0x30, 0xF0, 0x3C, 0xF0, 0xFF, 0x3C, 0xF0, 0x0F, 0xF0, 0x27, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, - 0x30, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0xFF, 0x0F, 0xF0, 0x27, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x30, - 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x0F, 0xF0, 0xFF, 0x27, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x30, 0xF0, - 0x3C, 0xF0, 0x3C, 0xF0, 0x0F, 0xF0, 0x27, 0xF0, 0xFF, 0x3C, 0xF0, 0x3C, 0xF0, 0x30, 0xF0, 0x3C, - 0xF0, 0x3C, 0xF0, 0x0F, 0xF0, 0x27, 0xF0, 0x3C, 0xF0, 0xFF, 0x3C, 0xF0, 0x30, 0xF0, 0x3C, 0xF0, - 0x3C, 0xF0, 0x0F, 0xF0, 0x27, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0xFF, 0x30, 0xF0, 0x3C, 0xF0, 0x3C, - 0xF0, 0x0F, 0xF0, 0x27, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x30, 0xF0, 0xFF, 0x3C, 0xF0, 0x3C, 0xF0, - 0x0F, 0xF0, 0x27, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x30, 0xF0, 0x3C, 0xF0, 0xFF, 0x3C, 0xF0, 0x0F, - 0xF0, 0x27, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x30, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0xFF, 0x0F, 0xF0, - 0x27, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x30, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x0F, 0xF0, 0xFF, 0x27, - 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x30, 0xF0, 0x3C, 0xF0, 0x3C, 0xF0, 0x0F, 0xF0, 0x27, 0xF0, 0xFF, - 0x3C, 0xF0, 0x3C, 0xF0, 0x30, 0xF0, 0x3C, 0xF0, 0x84, 0x90, 0x3F, 0x00, 0x00, 0x00, 0x0F, 0xF0, - 0xFF, 0x09, 0x90, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x09, 0x02, 0x07, 0x01, 0xB1, 0x40, - 0x81, 0x20, 0x33, 0x0C, 0x08, 0x00, 0x00, 0x0F, 0xF0, 0xC6, 0x09, 0x90, 0x03, 0x30, 0x00, 0x00, - 0x0D, 0x03, 0x02, 0x2D, 0x0A, 0x07, 0x07, 0x75, 0x30, 0x39, 0x00, 0x00, 0x00, 0x0F, 0xF0, 0x0F, - 0xF0, 0x1B, 0xF0, 0x03, 0x00, 0xFE, 0x39, 0x00, 0xB1, 0x29, 0x1B, 0xF3, 0x39, 0x26, 0x00, 0x00, - 0x81, 0x0F, 0xF0, 0x09, 0x90, 0x03, 0x30, 0x00, 0x00, 0xFE, 0x3B, 0x27, 0xF5, 0x0F, 0x39, 0x26, - 0xB3, 0x2A, 0x1C, 0x17, 0x05, 0x03, 0x00, 0xFF, 0xE4, 0x02, 0x00, 0x00, 0x0D, 0x00, 0x00, 0x00, - 0x6A, 0x09, 0x00, 0x00 -}; +#define BATTERY_EMPTY_WIDTH 21 +#define BATTERY_EMPTY_BATT_HEIGHT 38 +#define BATTERY_EMPTY_CHRG_HEIGHT 12 +#define BATTERY_EMPTY_SIZE 3150 +#define BATTERY_EMPTY_BLZ_SIZE 740 +extern u8 battery_icons_blz[]; + +u8 *render_static_bootlogo(); +bool render_ticker_logo(u32 boot_wait, u32 backlight); +bool render_ticker(u32 boot_wait, u32 backlight, bool no_ticker); #endif diff --git a/bootloader/gfx/tui.c b/bootloader/gfx/tui.c index 12e3356..5c1ef28 100644 --- a/bootloader/gfx/tui.c +++ b/bootloader/gfx/tui.c @@ -15,12 +15,10 @@ * along with this program. If not, see . */ -#include +#include + #include "tui.h" #include "../config.h" -#include -#include -#include extern hekate_config h_cfg; @@ -42,23 +40,20 @@ void tui_sbar(bool force_update) int battVoltCurr = 0; gfx_con_getpos(&cx, &cy); - gfx_con_setpos(0, 1260); + gfx_con_setpos(0, 1260); max17050_get_property(MAX17050_RepSOC, (int *)&battPercent); max17050_get_property(MAX17050_VCELL, &battVoltCurr); gfx_clear_partial_grey(0x30, 1256, 24); - gfx_printf("%K%k Battery: %d.%d%% (%d mV) - Charge:", 0xFF303030, 0xFF888888, + gfx_printf("%K%k Battery: %d.%d%% (%d mV) - Charge:", TXT_CLR_GREY_D, TXT_CLR_GREY, (battPercent >> 8) & 0xFF, (battPercent & 0xFF) / 26, battVoltCurr); max17050_get_property(MAX17050_Current, &battVoltCurr); - if (battVoltCurr >= 0) - gfx_printf(" %k+%d mA%k%K\n", - 0xFF008800, battVoltCurr / 1000, 0xFFCCCCCC, 0xFF1B1B1B); - else - gfx_printf(" %k-%d mA%k%K\n", - 0xFF880000, (~battVoltCurr) / 1000, 0xFFCCCCCC, 0xFF1B1B1B); + gfx_printf(" %k%d mA%k%K\n", battVoltCurr >= 0 ? TXT_CLR_GREEN_D : TXT_CLR_RED_D, + battVoltCurr / 1000, TXT_CLR_DEFAULT, TXT_CLR_BG); + gfx_con.fntsz = prevFontSize; gfx_con_setpos(cx, cy); } @@ -73,7 +68,7 @@ void tui_pbar(int x, int y, u32 val, u32 fgcol, u32 bgcol) gfx_con_setpos(x, y); - gfx_printf("%k[%3d%%]%k", fgcol, val, 0xFFCCCCCC); + gfx_printf("%k[%3d%%]%k", fgcol, val, TXT_CLR_DEFAULT); x += 7 * gfx_con.fntsz; @@ -98,7 +93,7 @@ void *tui_do_menu(menu_t *menu) while (true) { - gfx_con_setcol(0xFFCCCCCC, 1, 0xFF1B1B1B); + gfx_con_setcol(TXT_CLR_DEFAULT, 1, TXT_CLR_BG); gfx_con_setpos(menu->x, menu->y); gfx_printf("[%s]\n\n", menu->caption); @@ -131,25 +126,25 @@ void *tui_do_menu(menu_t *menu) for (cnt = 0; menu->ents[cnt].type != MENT_END; cnt++) { if (cnt == idx) - gfx_con_setcol(0xFF1B1B1B, 1, 0xFFCCCCCC); + gfx_con_setcol(TXT_CLR_BG, 1, TXT_CLR_DEFAULT); else - gfx_con_setcol(0xFFCCCCCC, 1, 0xFF1B1B1B); + gfx_con_setcol(TXT_CLR_DEFAULT, 1, TXT_CLR_BG); if (menu->ents[cnt].type == MENT_CAPTION) gfx_printf("%k %s", menu->ents[cnt].color, menu->ents[cnt].caption); else if (menu->ents[cnt].type != MENT_CHGLINE) gfx_printf(" %s", menu->ents[cnt].caption); - if(menu->ents[cnt].type == MENT_MENU) - gfx_printf("%k...", 0xFF0099EE); + if (menu->ents[cnt].type == MENT_MENU) + gfx_printf("%k...", TXT_CLR_CYAN_L); gfx_printf(" \n"); } - gfx_con_setcol(0xFFCCCCCC, 1, 0xFF1B1B1B); + gfx_con_setcol(TXT_CLR_DEFAULT, 1, TXT_CLR_BG); gfx_putc('\n'); // Print errors, help and battery status. gfx_con_setpos(0, 1127); - gfx_printf("%k Warning: %k Nyx is missing!", 0xFF800000, 0xFF555555); + gfx_printf("%k Warning: %kNyx is missing!", TXT_CLR_RED_D, TXT_CLR_GREY_M); gfx_con_setpos(0, 1191); - gfx_printf("%k VOL: Move up/down\n PWR: Select option%k", 0xFF555555, 0xFFCCCCCC); + gfx_printf("%k VOL: Move up/down\n PWR: Select option%k", TXT_CLR_GREY_M, TXT_CLR_DEFAULT); display_backlight_brightness(h_cfg.backlight, 1000); diff --git a/bootloader/gfx/tui.h b/bootloader/gfx/tui.h index 14537f6..0fd3194 100644 --- a/bootloader/gfx/tui.h +++ b/bootloader/gfx/tui.h @@ -18,8 +18,7 @@ #ifndef _TUI_H_ #define _TUI_H_ -#include -#include +#include #define MENT_END 0 #define MENT_HANDLER 1 diff --git a/bootloader/hos/fss.c b/bootloader/hos/fss.c deleted file mode 100644 index 2056130..0000000 --- a/bootloader/hos/fss.c +++ /dev/null @@ -1,243 +0,0 @@ -/* - * Atmosphère Fusée Secondary Storage (Package3) parser. - * - * Copyright (c) 2019-2021 CTCaer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -#include "fss.h" -#include "hos.h" -#include "../config.h" -#include -#include -#include "../storage/emummc.h" -#include - -#include -#define DPRINTF(...) - -extern hekate_config h_cfg; - -extern bool is_ipl_updated(void *buf, char *path, bool force); - -// FSS0 Magic and Meta header offset. -#define FSS0_MAGIC 0x30535346 -#define FSS0_META_OFFSET 0x4 -#define FSS0_VERSION_0_17_0 0x110000 - -// FSS0 Content Types. -#define CNT_TYPE_FSP 0 -#define CNT_TYPE_EXO 1 // Exosphere (Secure Monitor). -#define CNT_TYPE_WBT 2 // Warmboot (SC7Exit fw). -#define CNT_TYPE_RBT 3 // Rebootstub (Warmboot based reboot fw). -#define CNT_TYPE_SP1 4 // Sept Primary (TSEC and Sept Secondary loader). -#define CNT_TYPE_SP2 5 // Sept Secondary (Acts as pkg11 and derives keys). -#define CNT_TYPE_KIP 6 // KIP1 (Used for replacement or addition). -#define CNT_TYPE_BMP 7 -#define CNT_TYPE_EMC 8 -#define CNT_TYPE_KLD 9 // Kernel Loader. -#define CNT_TYPE_KRN 10 // Kernel. -#define CNT_TYPE_EXF 11 // Exosphere Mariko fatal payload. -#define CNT_TYPE_TKG 12 // Tsec Keygen. - -// FSS0 Content Flags. -#define CNT_FLAG0_EXPERIMENTAL BIT(0) - -// FSS0 Meta Header. -typedef struct _fss_meta_t -{ - u32 magic; - u32 size; - u32 crt0_off; - u32 cnt_off; - u32 cnt_count; - u32 hos_ver; - u32 version; - u32 git_rev; -} fss_meta_t; - -// FSS0 Content Header. -typedef struct _fss_content_t -{ - u32 offset; - u32 size; - u8 type; - u8 flags0; - u8 flags1; - u8 flags2; - u32 rsvd1; - char name[0x10]; -} fss_content_t; - -static void _set_fss_path_and_update_r2p(launch_ctxt_t *ctxt, const char *path) -{ - char *r2p_path = malloc(256); - u32 path_len = strlen(path); - - strcpy(r2p_path, path); - - while(path_len) - { - if ((r2p_path[path_len - 1] == '/') || (r2p_path[path_len - 1] == '\\')) - { - r2p_path[path_len] = 0; - strcat(r2p_path, "reboot_payload.bin"); - u8 *r2p_payload = sd_file_read(r2p_path, NULL); - - is_ipl_updated(r2p_payload, r2p_path, h_cfg.updater2p ? true : false); - - free(r2p_payload); - - // Save FSS0 parent path. - r2p_path[path_len] = 0; - ctxt->fss0_main_path = r2p_path; - return; - } - path_len--; - } - - free(r2p_path); -} - -int parse_fss(launch_ctxt_t *ctxt, const char *path) -{ - FIL fp; - - bool stock = false; - bool experimental = false; - - // Skip if stock and Exosphere and warmboot are not needed. - bool pkg1_old = ctxt->pkg1_id->kb <= KB_FIRMWARE_VERSION_620; // Should check if t210b01? - bool emummc_disabled = !emu_cfg.enabled || h_cfg.emummc_force_disable; - - LIST_FOREACH_ENTRY(ini_kv_t, kv, &ctxt->cfg->kvs, link) - { - if (!strcmp("stock", kv->key)) - if (kv->val[0] == '1') - stock = true; - - if (!strcmp("fss0experimental", kv->key)) - if (kv->val[0] == '1') - experimental = true; - } - -#ifdef HOS_MARIKO_STOCK_SECMON - if (stock && emummc_disabled && (pkg1_old || h_cfg.t210b01)) - return 1; -#else - if (stock && emummc_disabled && pkg1_old) - return 1; -#endif - - // Try to open FSS0. - if (f_open(&fp, path, FA_READ) != FR_OK) - return 0; - - void *fss = malloc(f_size(&fp)); - - // Read first 1024 bytes of the FSS0 file. - f_read(&fp, fss, 1024, NULL); - - // Get FSS0 Meta header offset. - u32 fss_meta_addr = *(u32 *)(fss + FSS0_META_OFFSET); - fss_meta_t *fss_meta = (fss_meta_t *)(fss + fss_meta_addr); - - // Check if valid FSS0 and parse it. - if (fss_meta->magic == FSS0_MAGIC) - { - gfx_printf("Found FSS/PK3, Atmosphere %d.%d.%d-%08x\n" - "Max HOS: %d.%d.%d\n" - "Unpacking.. ", - fss_meta->version >> 24, (fss_meta->version >> 16) & 0xFF, (fss_meta->version >> 8) & 0xFF, fss_meta->git_rev, - fss_meta->hos_ver >> 24, (fss_meta->hos_ver >> 16) & 0xFF, (fss_meta->hos_ver >> 8) & 0xFF); - - ctxt->atmosphere = true; - ctxt->fss0_hosver = fss_meta->hos_ver; - - // Parse FSS0 contents. - fss_content_t *curr_fss_cnt = (fss_content_t *)(fss + fss_meta->cnt_off); - void *content; - for (u32 i = 0; i < fss_meta->cnt_count; i++) - { - content = (void *)(fss + curr_fss_cnt[i].offset); - - // Check if offset is inside limits. - if ((curr_fss_cnt[i].offset + curr_fss_cnt[i].size) > fss_meta->size) - continue; - - // If content is experimental and experimental config is not enabled, skip it. - if ((curr_fss_cnt[i].flags0 & CNT_FLAG0_EXPERIMENTAL) && !experimental) - continue; - - // Prepare content. - switch (curr_fss_cnt[i].type) - { - case CNT_TYPE_KIP: - if (stock) - continue; - merge_kip_t *mkip1 = (merge_kip_t *)malloc(sizeof(merge_kip_t)); - mkip1->kip1 = content; - list_append(&ctxt->kip1_list, &mkip1->link); - DPRINTF("Loaded %s.kip1 from FSS0 (size %08X)\n", curr_fss_cnt[i].name, curr_fss_cnt[i].size); - break; - - case CNT_TYPE_KRN: - if (stock) - continue; - ctxt->kernel_size = curr_fss_cnt[i].size; - ctxt->kernel = content; - break; - - case CNT_TYPE_EXO: - ctxt->secmon_size = curr_fss_cnt[i].size; - ctxt->secmon = content; - break; - - case CNT_TYPE_EXF: - ctxt->exofatal_size = curr_fss_cnt[i].size; - ctxt->exofatal = content; - break; - - case CNT_TYPE_WBT: - if (h_cfg.t210b01) - continue; - ctxt->warmboot_size = curr_fss_cnt[i].size; - ctxt->warmboot = content; - break; - - default: - continue; - } - - // Load content to launch context. - f_lseek(&fp, curr_fss_cnt[i].offset); - f_read(&fp, content, curr_fss_cnt[i].size, NULL); - } - - gfx_printf("Done!\n"); - f_close(&fp); - - // Set FSS0 path and update r2p if needed. - _set_fss_path_and_update_r2p(ctxt, path); - - return 1; - } - - f_close(&fp); - free(fss); - - return 0; -} diff --git a/bootloader/hos/hos.c b/bootloader/hos/hos.c index 423c928..4504a4a 100644 --- a/bootloader/hos/hos.c +++ b/bootloader/hos/hos.c @@ -2,7 +2,7 @@ * Copyright (c) 2018 naehrwert * Copyright (c) 2018 st4rk * Copyright (c) 2018 Ced2911 - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2025 CTCaer * Copyright (c) 2018 balika011 * * This program is free software; you can redistribute it and/or modify it @@ -20,32 +20,14 @@ #include +#include + #include "hos.h" #include "hos_config.h" #include "secmon_exo.h" +#include "../frontend/fe_tools.h" #include "../config.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include #include "../storage/emummc.h" -#include -#include "../storage/nx_emmc.h" -#include -#include -#include -#include extern hekate_config h_cfg; @@ -54,7 +36,7 @@ extern hekate_config h_cfg; #define EHPRINTFARGS(text, args...) \ ({ gfx_con.mute = false; \ - gfx_printf("%k"text"%k\n", 0xFFFF0000, args, 0xFFCCCCCC); }) + gfx_printf("%k"text"%k\n", TXT_CLR_ERROR, args, TXT_CLR_DEFAULT); }) #define PKG2_LOAD_ADDR 0xA9800000 @@ -65,6 +47,18 @@ extern hekate_config h_cfg; #define SECMON_MAILBOX_ADDR 0x40002E00 #define SECMON7_MAILBOX_ADDR 0x40000000 #define SECMON_STATE_OFFSET 0xF8 + +typedef enum +{ + SECMON_STATE_NOT_READY = 0, + + PKG1_STATE_NOT_READY = 0, + PKG1_STATE_BCT_COPIED = 1, + PKG1_STATE_DRAM_READY = 2, + PKG1_STATE_PKG2_READY_OLD = 3, + PKG1_STATE_PKG2_READY = 4 +} pkg1_states_t; + typedef struct _secmon_mailbox_t { // < 4.0.0 Signals - 0: Not ready, 1: BCT ready, 2: DRAM and pkg2 ready, 3: Continue boot. @@ -96,7 +90,7 @@ typedef struct _kb_t u8 padding[0x150]; } kb_t; -static const u8 keyblob_keyseeds[][SE_KEY_128_SIZE] = { +static const u8 keyblob_keyseeds[HOS_KB_VERSION_600 - HOS_KB_VERSION_100 + 1][SE_KEY_128_SIZE] = { { 0xDF, 0x20, 0x6F, 0x59, 0x44, 0x54, 0xEF, 0xDC, 0x70, 0x74, 0x48, 0x3B, 0x0D, 0xED, 0x9F, 0xD3 }, // 1.0.0. { 0x0C, 0x25, 0x61, 0x5D, 0x68, 0x4C, 0xEB, 0x42, 0x1C, 0x23, 0x79, 0xEA, 0x82, 0x25, 0x12, 0xAC }, // 3.0.0. { 0x33, 0x76, 0x85, 0xEE, 0x88, 0x4A, 0xAE, 0x0A, 0xC2, 0x8A, 0xFD, 0x7D, 0x63, 0xC0, 0x43, 0x3B }, // 3.0.1. @@ -118,16 +112,23 @@ static const u8 master_kekseed_620[SE_KEY_128_SIZE] = { 0x37, 0x4B, 0x77, 0x29, 0x59, 0xB4, 0x04, 0x30, 0x81, 0xF6, 0xE5, 0x8C, 0x6D, 0x36, 0x17, 0x9A }; //!TODO: Update on tsec/mkey changes. -static const u8 master_kekseed_t210_tsec_v4[][SE_KEY_128_SIZE] = { +static const u8 master_kekseed_t210_tsec_v4[HOS_KB_VERSION_MAX - HOS_KB_VERSION_810 + 1][SE_KEY_128_SIZE] = { { 0xDE, 0xDC, 0xE3, 0x39, 0x30, 0x88, 0x16, 0xF8, 0xAE, 0x97, 0xAD, 0xEC, 0x64, 0x2D, 0x41, 0x41 }, // 8.1.0. { 0x1A, 0xEC, 0x11, 0x82, 0x2B, 0x32, 0x38, 0x7A, 0x2B, 0xED, 0xBA, 0x01, 0x47, 0x7E, 0x3B, 0x67 }, // 9.0.0. { 0x30, 0x3F, 0x02, 0x7E, 0xD8, 0x38, 0xEC, 0xD7, 0x93, 0x25, 0x34, 0xB5, 0x30, 0xEB, 0xCA, 0x7A }, // 9.1.0. { 0x84, 0x67, 0xB6, 0x7F, 0x13, 0x11, 0xAE, 0xE6, 0x58, 0x9B, 0x19, 0xAF, 0x13, 0x6C, 0x80, 0x7A }, // 12.1.0. { 0x68, 0x3B, 0xCA, 0x54, 0xB8, 0x6F, 0x92, 0x48, 0xC3, 0x05, 0x76, 0x87, 0x88, 0x70, 0x79, 0x23 }, // 13.0.0. + { 0xF0, 0x13, 0x37, 0x9A, 0xD5, 0x63, 0x51, 0xC3, 0xB4, 0x96, 0x35, 0xBC, 0x9C, 0xE8, 0x76, 0x81 }, // 14.0.0. + { 0x6E, 0x77, 0x86, 0xAC, 0x83, 0x0A, 0x8D, 0x3E, 0x7D, 0xB7, 0x66, 0xA0, 0x22, 0xB7, 0x6E, 0x67 }, // 15.0.0. + { 0x99, 0x22, 0x09, 0x57, 0xA7, 0xF9, 0x5E, 0x94, 0xFE, 0x78, 0x7F, 0x41, 0xD6, 0xE7, 0x56, 0xE6 }, // 16.0.0. + { 0x71, 0xB9, 0xA6, 0xC0, 0xFF, 0x97, 0x6B, 0x0C, 0xB4, 0x40, 0xB9, 0xD5, 0x81, 0x5D, 0x81, 0x90 }, // 17.0.0. + { 0x00, 0x04, 0x5D, 0xF0, 0x4D, 0xCD, 0x14, 0xA3, 0x1C, 0xBF, 0xDE, 0x48, 0x55, 0xBA, 0x35, 0xC1 }, // 18.0.0. + { 0xD7, 0x63, 0x74, 0x46, 0x4E, 0xBA, 0x78, 0x0A, 0x7C, 0x9D, 0xB3, 0xE8, 0x7A, 0x3D, 0x71, 0xE3 }, // 19.0.0. + { 0xA1, 0x7D, 0x34, 0xDB, 0x2D, 0x9D, 0xDA, 0xE5, 0xF8, 0x15, 0x63, 0x4C, 0x8F, 0xE7, 0x6C, 0xD8 }, // 20.0.0. }; //!TODO: Update on mkey changes. -static const u8 master_kekseed_t210b01[][SE_KEY_128_SIZE] = { +static const u8 master_kekseed_t210b01[HOS_KB_VERSION_MAX - HOS_KB_VERSION_600 + 1][SE_KEY_128_SIZE] = { { 0x77, 0x60, 0x5A, 0xD2, 0xEE, 0x6E, 0xF8, 0x3C, 0x3F, 0x72, 0xE2, 0x59, 0x9D, 0xAC, 0x5E, 0x56 }, // 6.0.0. { 0x1E, 0x80, 0xB8, 0x17, 0x3E, 0xC0, 0x60, 0xAA, 0x11, 0xBE, 0x1A, 0x4A, 0xA6, 0x6F, 0xE4, 0xAE }, // 6.2.0. { 0x94, 0x08, 0x67, 0xBD, 0x0A, 0x00, 0x38, 0x84, 0x11, 0xD3, 0x1A, 0xDB, 0xDD, 0x8D, 0xF1, 0x8A }, // 7.0.0. @@ -136,6 +137,13 @@ static const u8 master_kekseed_t210b01[][SE_KEY_128_SIZE] = { { 0x0E, 0x44, 0x0C, 0xED, 0xB4, 0x36, 0xC0, 0x3F, 0xAA, 0x1D, 0xAE, 0xBF, 0x62, 0xB1, 0x09, 0x82 }, // 9.1.0. { 0xE5, 0x41, 0xAC, 0xEC, 0xD1, 0xA7, 0xD1, 0xAB, 0xED, 0x03, 0x77, 0xF1, 0x27, 0xCA, 0xF8, 0xF1 }, // 12.1.0. { 0x52, 0x71, 0x9B, 0xDF, 0xA7, 0x8B, 0x61, 0xD8, 0xD5, 0x85, 0x11, 0xE4, 0x8E, 0x4F, 0x74, 0xC6 }, // 13.0.0. + { 0xD2, 0x68, 0xC6, 0x53, 0x9D, 0x94, 0xF9, 0xA8, 0xA5, 0xA8, 0xA7, 0xC8, 0x8F, 0x53, 0x4B, 0x7A }, // 14.0.0. + { 0xEC, 0x61, 0xBC, 0x82, 0x1E, 0x0F, 0x5A, 0xC3, 0x2B, 0x64, 0x3F, 0x9D, 0xD6, 0x19, 0x22, 0x2D }, // 15.0.0. + { 0xA5, 0xEC, 0x16, 0x39, 0x1A, 0x30, 0x16, 0x08, 0x2E, 0xCF, 0x09, 0x6F, 0x5E, 0x7C, 0xEE, 0xA9 }, // 16.0.0. + { 0x8D, 0xEE, 0x9E, 0x11, 0x36, 0x3A, 0x9B, 0x0A, 0x6A, 0xC7, 0xBB, 0xE9, 0xD1, 0x03, 0xF7, 0x80 }, // 17.0.0. + { 0x4F, 0x41, 0x3C, 0x3B, 0xFB, 0x6A, 0x01, 0x2A, 0x68, 0x9F, 0x83, 0xE9, 0x53, 0xBD, 0x16, 0xD2 }, // 18.0.0. + { 0x31, 0xBE, 0x25, 0xFB, 0xDB, 0xB4, 0xEE, 0x49, 0x5C, 0x77, 0x05, 0xC2, 0x36, 0x9F, 0x34, 0x80 }, // 19.0.0. + { 0x1A, 0x31, 0x62, 0x87, 0xA8, 0x09, 0xCA, 0xF8, 0x69, 0x15, 0x45, 0xC2, 0x6B, 0xAA, 0x5A, 0x8A }, // 20.0.0. }; static const u8 console_keyseed[SE_KEY_128_SIZE] = @@ -150,7 +158,7 @@ const u8 package2_keyseed[SE_KEY_128_SIZE] = static void _hos_crit_error(const char *text) { gfx_con.mute = false; - gfx_printf("%k%s%k\n", 0xFFFF0000, text, 0xFFCCCCCC); + gfx_printf("%k%s%k\n", TXT_CLR_ERROR, text, TXT_CLR_DEFAULT); } static void _se_lock(bool lock_se) @@ -179,33 +187,16 @@ static void _se_lock(bool lock_se) gfx_printf("SE(0x4) = %08X\n", SE(0x4)); gfx_printf("SE(SE_CRYPTO_SECURITY_PERKEY_REG) = %08X\n", SE(SE_CRYPTO_SECURITY_PERKEY_REG)); gfx_printf("SE(SE_RSA_SECURITY_PERKEY_REG) = %08X\n", SE(SE_RSA_SECURITY_PERKEY_REG)); - for(u32 i = 0; i < 16; i++) + for (u32 i = 0; i < 16; i++) gfx_printf("%02X ", SE(SE_CRYPTO_KEYTABLE_ACCESS_REG + i * 4) & 0xFF); gfx_putc('\n'); - for(u32 i = 0; i < 2; i++) + for (u32 i = 0; i < 2; i++) gfx_printf("%02X ", SE(SE_RSA_KEYTABLE_ACCESS_REG + i * 4) & 0xFF); gfx_putc('\n'); gfx_hexdump(SE_BASE, (void *)SE_BASE, 0x400);*/ } -void _sysctr0_reset() -{ - SYSCTR0(SYSCTR0_CNTCR) = 0; - SYSCTR0(SYSCTR0_COUNTERID0) = 0; - SYSCTR0(SYSCTR0_COUNTERID1) = 0; - SYSCTR0(SYSCTR0_COUNTERID2) = 0; - SYSCTR0(SYSCTR0_COUNTERID3) = 0; - SYSCTR0(SYSCTR0_COUNTERID4) = 0; - SYSCTR0(SYSCTR0_COUNTERID5) = 0; - SYSCTR0(SYSCTR0_COUNTERID6) = 0; - SYSCTR0(SYSCTR0_COUNTERID7) = 0; - SYSCTR0(SYSCTR0_COUNTERID8) = 0; - SYSCTR0(SYSCTR0_COUNTERID9) = 0; - SYSCTR0(SYSCTR0_COUNTERID10) = 0; - SYSCTR0(SYSCTR0_COUNTERID11) = 0; -} - -bool hos_eks_rw_try(u8 *buf, bool write) +static bool _hos_eks_rw_try(u8 *buf, bool write) { for (u32 i = 0; i < 3; i++) { @@ -234,8 +225,8 @@ static void _hos_eks_get() if (!h_cfg.eks) { // Read EKS blob. - u8 *mbr = calloc(512 , 1); - if (!hos_eks_rw_try(mbr, false)) + u8 *mbr = zalloc(SD_BLOCKSIZE); + if (!_hos_eks_rw_try(mbr, false)) goto out; // Decrypt EKS blob. @@ -264,7 +255,7 @@ static void _hos_eks_save() bool new_eks = false; if (!h_cfg.eks) { - h_cfg.eks = calloc(512 , 1); + h_cfg.eks = zalloc(SD_BLOCKSIZE); new_eks = true; } @@ -272,8 +263,8 @@ static void _hos_eks_save() if (h_cfg.eks->enabled != HOS_EKS_TSEC_VER) { // Read EKS blob. - u8 *mbr = calloc(512 , 1); - if (!hos_eks_rw_try(mbr, false)) + u8 *mbr = zalloc(SD_BLOCKSIZE); + if (!_hos_eks_rw_try(mbr, false)) { if (new_eks) { @@ -285,8 +276,8 @@ static void _hos_eks_save() } // Get keys. - u8 *keys = (u8 *)calloc(0x2000, 1); - se_get_aes_keys(keys + 0x1000, keys, SE_KEY_128_SIZE); + u8 *keys = (u8 *)zalloc(SZ_8K); + se_get_aes_keys(keys + SZ_4K, keys, SE_KEY_128_SIZE); // Set magic and personalized info. h_cfg.eks->magic = HOS_EKS_MAGIC; @@ -299,13 +290,13 @@ static void _hos_eks_save() memcpy(h_cfg.eks->troot_dev, keys + 11 * SE_KEY_128_SIZE, SE_KEY_128_SIZE); // Encrypt EKS blob. - u8 *eks = calloc(512 , 1); + u8 *eks = zalloc(SD_BLOCKSIZE); memcpy(eks, h_cfg.eks, sizeof(hos_eks_mbr_t)); se_aes_crypt_ecb(14, ENCRYPT, eks, sizeof(hos_eks_mbr_t), eks, sizeof(hos_eks_mbr_t)); // Write EKS blob to SD. memcpy(mbr + 0x80, eks, sizeof(hos_eks_mbr_t)); - hos_eks_rw_try(mbr, true); + _hos_eks_rw_try(mbr, true); free(eks); free(keys); @@ -314,33 +305,33 @@ out: } } -void hos_eks_clear(u32 kb) +static void _hos_eks_clear(u32 kb) { // Check if Erista based unit. if (h_cfg.t210b01) return; - if (h_cfg.eks && kb >= KB_FIRMWARE_VERSION_700) + if (h_cfg.eks && kb >= HOS_KB_VERSION_700) { // Check if current Master key is enabled. if (h_cfg.eks->enabled) { // Read EKS blob. - u8 *mbr = calloc(512 , 1); - if (!hos_eks_rw_try(mbr, false)) + u8 *mbr = zalloc(SD_BLOCKSIZE); + if (!_hos_eks_rw_try(mbr, false)) goto out; // Disable current Master key version. h_cfg.eks->enabled = 0; // Encrypt EKS blob. - u8 *eks = calloc(512 , 1); + u8 *eks = zalloc(SD_BLOCKSIZE); memcpy(eks, h_cfg.eks, sizeof(hos_eks_mbr_t)); se_aes_crypt_ecb(14, ENCRYPT, eks, sizeof(hos_eks_mbr_t), eks, sizeof(hos_eks_mbr_t)); // Write EKS blob to SD. memcpy(mbr + 0x80, eks, sizeof(hos_eks_mbr_t)); - hos_eks_rw_try(mbr, true); + _hos_eks_rw_try(mbr, true); free(eks); out: @@ -349,43 +340,41 @@ out: } } -int hos_keygen_t210b01(u32 kb) +static int _hos_keygen(void *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt, bool stock, bool is_exo) { - // Use SBK as Device key 4x unsealer and KEK for mkey in T210B01 units. - se_aes_unwrap_key(10, 14, console_keyseed_4xx); - - // Derive master key. - se_aes_unwrap_key(7, 12, &master_kekseed_t210b01[kb - KB_FIRMWARE_VERSION_600]); - se_aes_unwrap_key(7, 7, master_keyseed_retail); - - // Derive latest pkg2 key. - se_aes_unwrap_key(8, 7, package2_keyseed); - - return 1; -} - -int hos_keygen(void *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt, bool stock, bool is_exo) -{ - static bool sbk_wiped = false; + static bool sbk_is_set = true; u32 retries = 0; bool use_tsec = false; tsec_keys_t tsec_keys; kb_t *kb_data = (kb_t *)keyblob; - if (kb > KB_FIRMWARE_VERSION_MAX) + if (kb > HOS_KB_VERSION_MAX) return 0; + // Do Mariko keygen. if (h_cfg.t210b01) - return hos_keygen_t210b01(kb); + { + // Use SBK as Device key 4x unsealer and KEK for mkey in T210B01 units. + se_aes_unwrap_key(10, 14, console_keyseed_4xx); + + // Derive master key. + se_aes_unwrap_key(7, 12, master_kekseed_t210b01[kb - HOS_KB_VERSION_600]); + se_aes_unwrap_key(7, 7, master_keyseed_retail); + + // Derive latest pkg2 key. + se_aes_unwrap_key(8, 7, package2_keyseed); + + return 1; + } // Do Erista keygen. - // SBK is wiped. Try to restore it from fuses. - if (sbk_wiped) + // Check if SBK is wiped and try to restore it from fuses. + if (!sbk_is_set) { if (fuse_set_sbk()) - sbk_wiped = false; + sbk_is_set = true; else return 1; // Continue with current SE keys. } @@ -394,21 +383,21 @@ int hos_keygen(void *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt, bool stock, bool i _hos_eks_get(); // Use tsec keygen for old firmware or if EKS keys does not exist for newer. - if (kb <= KB_FIRMWARE_VERSION_620 || !h_cfg.eks || (h_cfg.eks && h_cfg.eks->enabled != HOS_EKS_TSEC_VER)) + if (kb <= HOS_KB_VERSION_620 || !h_cfg.eks || (h_cfg.eks->enabled != HOS_EKS_TSEC_VER)) use_tsec = true; - if (kb <= KB_FIRMWARE_VERSION_600) + if (kb <= HOS_KB_VERSION_600) { tsec_ctxt->size = 0xF00; tsec_ctxt->type = TSEC_FW_TYPE_OLD; } - else if (kb == KB_FIRMWARE_VERSION_620) + else if (kb == HOS_KB_VERSION_620) { tsec_ctxt->size = 0x2900; tsec_ctxt->type = TSEC_FW_TYPE_EMU; // Prepare smmu tsec page for 6.2.0. - u8 *tsec_paged = (u8 *)page_alloc(3); + u8 *tsec_paged = (u8 *)smmu_page_zalloc(3); memcpy(tsec_paged, (void *)tsec_ctxt->fw, tsec_ctxt->size); tsec_ctxt->fw = tsec_paged; } @@ -423,7 +412,7 @@ int hos_keygen(void *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt, bool stock, bool i tsec_ctxt->fw = sd_file_read("bootloader/sys/thk.bin", NULL); if (!tsec_ctxt->fw) { - _hos_crit_error("\nFailed to load thk.bin"); + _hos_crit_error("Failed to load thk.bin"); return 0; } @@ -447,12 +436,12 @@ int hos_keygen(void *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt, bool stock, bool i // We rely on racing conditions, make sure we cover even the unluckiest cases. if (retries > 15) { - _hos_crit_error("\nFailed to get TSEC keys. Please try again."); + _hos_crit_error("Failed to get TSEC keys."); return 0; } } - if (kb >= KB_FIRMWARE_VERSION_700) + if (kb >= HOS_KB_VERSION_700) { // For 7.0.0 and up, save EKS slot if it doesn't exist. if (use_tsec) @@ -463,8 +452,8 @@ int hos_keygen(void *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt, bool stock, bool i // Use 8.1.0 for 7.0.0 otherwise the proper one. u32 mkey_idx = 0; - if (kb >= KB_FIRMWARE_VERSION_810) - mkey_idx = kb - KB_FIRMWARE_VERSION_810; + if (kb >= HOS_KB_VERSION_810) + mkey_idx = kb - HOS_KB_VERSION_810; if (!is_exo) { @@ -493,7 +482,7 @@ int hos_keygen(void *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt, bool stock, bool i se_aes_unwrap_key(8, 13, package2_keyseed); } } - else if (kb == KB_FIRMWARE_VERSION_620) + else if (kb == HOS_KB_VERSION_620) { // Set TSEC key. se_aes_key_set(12, tsec_keys.tsec, SE_KEY_128_SIZE); @@ -570,26 +559,26 @@ int hos_keygen(void *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt, bool stock, bool i { switch (kb) { - case KB_FIRMWARE_VERSION_100: - case KB_FIRMWARE_VERSION_300: - case KB_FIRMWARE_VERSION_301: + case HOS_KB_VERSION_100: + case HOS_KB_VERSION_300: + case HOS_KB_VERSION_301: se_aes_unwrap_key(13, 15, console_keyseed); se_aes_unwrap_key(12, 12, master_keyseed_retail); break; - case KB_FIRMWARE_VERSION_400: + case HOS_KB_VERSION_400: se_aes_unwrap_key(13, 15, console_keyseed_4xx); se_aes_unwrap_key(15, 15, console_keyseed); se_aes_unwrap_key(14, 12, master_keyseed_4xx); se_aes_unwrap_key(12, 12, master_keyseed_retail); - sbk_wiped = true; + sbk_is_set = false; break; - case KB_FIRMWARE_VERSION_500: - case KB_FIRMWARE_VERSION_600: + case HOS_KB_VERSION_500: + case HOS_KB_VERSION_600: se_aes_unwrap_key(10, 15, console_keyseed_4xx); se_aes_unwrap_key(15, 15, console_keyseed); se_aes_unwrap_key(14, 12, master_keyseed_4xx); se_aes_unwrap_key(12, 12, master_keyseed_retail); - sbk_wiped = true; + sbk_is_set = false; break; } } @@ -611,35 +600,35 @@ int hos_keygen(void *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt, bool stock, bool i static int _read_emmc_pkg1(launch_ctxt_t *ctxt) { - const u32 BOOTLOADER_SIZE = 0x40000; - const u32 BOOTLOADER_MAIN_OFFSET = 0x100000; - const u32 BOOTLOADER_BACKUP_OFFSET = 0x140000; - const u32 HOS_KEYBLOBS_OFFSET = 0x180000; - - const u32 ERISTA_PKG1_ON_MARIKO_MAGIC = 0x20014770; // For 8.0.0 Erista and up. - - u32 pk1_offset = h_cfg.t210b01 ? sizeof(bl_hdr_t210b01_t) : 0; // Skip T210B01 OEM header. - u32 bootloader_offset = BOOTLOADER_MAIN_OFFSET; - ctxt->pkg1 = (void *)malloc(BOOTLOADER_SIZE); + const u32 pk1_offset = h_cfg.t210b01 ? sizeof(bl_hdr_t210b01_t) : 0; // Skip T210B01 OEM header. + u32 bootloader_offset = PKG1_BOOTLOADER_MAIN_OFFSET; + ctxt->pkg1 = (void *)malloc(PKG1_BOOTLOADER_SIZE); try_load: // Read package1. emummc_storage_set_mmc_partition(EMMC_BOOT0); - emummc_storage_read(bootloader_offset / NX_EMMC_BLOCKSIZE, BOOTLOADER_SIZE / NX_EMMC_BLOCKSIZE, ctxt->pkg1); + emummc_storage_read(bootloader_offset / EMMC_BLOCKSIZE, PKG1_BOOTLOADER_SIZE / EMMC_BLOCKSIZE, ctxt->pkg1); ctxt->pkg1_id = pkg1_identify(ctxt->pkg1 + pk1_offset); if (!ctxt->pkg1_id) { // Check if wrong pkg1 was flashed. bool wrong_pkg1; - u32 pkg1_build_check = *(u32 *)(ctxt->pkg1 + pk1_offset + 0x10); - if (!h_cfg.t210b01) // For Erista check if start is 0 and build offset is not 0. - wrong_pkg1 = *(u32 *)ctxt->pkg1 == 0 && pkg1_build_check != 0; - else // For Mariko works for 8.0.0 Erista pkg1 and up. - wrong_pkg1 = pkg1_build_check == ERISTA_PKG1_ON_MARIKO_MAGIC; + + const u32 pkg1_erista_check = ((bl_hdr_t210b01_t *)ctxt->pkg1)->entrypoint; + const u32 pkg1_mariko_check = *(u32 *)(ctxt->pkg1 + sizeof(pk1_hdr_t) * 2); + + if (!h_cfg.t210b01) // For Erista check if start is 0 and entrypoint matches Mariko. + wrong_pkg1 = *(u32 *)ctxt->pkg1 == 0 && pkg1_erista_check == PKG1_MARIKO_ON_ERISTA_MAGIC; + else // For Mariko check if start is not 0 and build id. It works for 8.0.0 Erista pkg1 and up. + wrong_pkg1 = *(u32 *)ctxt->pkg1 != 0 && pkg1_mariko_check == PKG1_ERISTA_ON_MARIKO_MAGIC; if (wrong_pkg1) - _hos_crit_error("Wrong pkg1 flashed!"); + { + _hos_crit_error("Wrong pkg1 flashed:"); + EPRINTFARGS("%s pkg1 on %s!", + !h_cfg.t210b01 ? "Mariko" : "Erista", !h_cfg.t210b01 ? "Erista" : "Mariko"); + } else { _hos_crit_error("Unknown pkg1 version."); @@ -648,10 +637,10 @@ try_load: } // Try backup bootloader. - if (bootloader_offset != BOOTLOADER_BACKUP_OFFSET) + if (bootloader_offset != PKG1_BOOTLOADER_BACKUP_OFFSET) { EPRINTF("\nTrying backup bootloader..."); - bootloader_offset = BOOTLOADER_BACKUP_OFFSET; + bootloader_offset = PKG1_BOOTLOADER_BACKUP_OFFSET; goto try_load; } @@ -660,10 +649,10 @@ try_load: gfx_printf("Identified pkg1 and mkey %d\n\n", ctxt->pkg1_id->kb); // Read the correct keyblob for older HOS versions. - if (ctxt->pkg1_id->kb <= KB_FIRMWARE_VERSION_600) + if (ctxt->pkg1_id->kb <= HOS_KB_VERSION_600) { - ctxt->keyblob = (u8 *)calloc(NX_EMMC_BLOCKSIZE, 1); - emummc_storage_read(HOS_KEYBLOBS_OFFSET / NX_EMMC_BLOCKSIZE + ctxt->pkg1_id->kb, 1, ctxt->keyblob); + ctxt->keyblob = (u8 *)zalloc(EMMC_BLOCKSIZE); + emummc_storage_read(PKG1_HOS_KEYBLOBS_OFFSET / EMMC_BLOCKSIZE + ctxt->pkg1_id->kb, 1, ctxt->keyblob); } return 1; @@ -677,46 +666,45 @@ static u8 *_read_emmc_pkg2(launch_ctxt_t *ctxt) // Parse eMMC GPT. LIST_INIT(gpt); - nx_emmc_gpt_parse(&gpt, &emmc_storage); + emmc_gpt_parse(&gpt); DPRINTF("Parsed GPT\n"); // Find package2 partition. - emmc_part_t *pkg2_part = nx_emmc_part_find(&gpt, "BCPKG2-1-Normal-Main"); + emmc_part_t *pkg2_part = emmc_part_find(&gpt, "BCPKG2-1-Normal-Main"); if (!pkg2_part) goto out; // Read in package2 header and get package2 real size. - const u32 BCT_SIZE = 0x4000; + static const u32 BCT_SIZE = SZ_16K; bctBuf = (u8 *)malloc(BCT_SIZE); - nx_emmc_part_read(&emmc_storage, pkg2_part, BCT_SIZE / NX_EMMC_BLOCKSIZE, 1, bctBuf); + emmc_part_read(pkg2_part, BCT_SIZE / EMMC_BLOCKSIZE, 1, bctBuf); u32 *hdr = (u32 *)(bctBuf + 0x100); u32 pkg2_size = hdr[0] ^ hdr[2] ^ hdr[3]; DPRINTF("pkg2 size on emmc is %08X\n", pkg2_size); // Read in Boot Config. - memset(bctBuf, 0, BCT_SIZE); - nx_emmc_part_read(&emmc_storage, pkg2_part, 0, BCT_SIZE / NX_EMMC_BLOCKSIZE, bctBuf); + emmc_part_read(pkg2_part, 0, BCT_SIZE / EMMC_BLOCKSIZE, bctBuf); // Read in package2. - u32 pkg2_size_aligned = ALIGN(pkg2_size, NX_EMMC_BLOCKSIZE); + u32 pkg2_size_aligned = ALIGN(pkg2_size, EMMC_BLOCKSIZE); DPRINTF("pkg2 size aligned is %08X\n", pkg2_size_aligned); ctxt->pkg2 = malloc(pkg2_size_aligned); ctxt->pkg2_size = pkg2_size; - nx_emmc_part_read(&emmc_storage, pkg2_part, BCT_SIZE / NX_EMMC_BLOCKSIZE, - pkg2_size_aligned / NX_EMMC_BLOCKSIZE, ctxt->pkg2); + emmc_part_read(pkg2_part, BCT_SIZE / EMMC_BLOCKSIZE, + pkg2_size_aligned / EMMC_BLOCKSIZE, ctxt->pkg2); out: - nx_emmc_gpt_free(&gpt); + emmc_gpt_free(&gpt); return bctBuf; } static void _free_launch_components(launch_ctxt_t *ctxt) { + // Free the malloc'ed guaranteed addresses. + free(ctxt->pkg3); free(ctxt->keyblob); free(ctxt->pkg1); free(ctxt->pkg2); free(ctxt->warmboot); - free(ctxt->secmon); - free(ctxt->kernel); free(ctxt->kip1_patches); } @@ -728,7 +716,7 @@ static bool _get_fs_exfat_compatible(link_t *info, u32 *hos_revision) LIST_FOREACH_ENTRY(pkg2_kip1_info_t, ki, info, link) { - if (strncmp((const char*)ki->kip1->name, "FS", sizeof(ki->kip1->name))) + if (strcmp((char *)ki->kip1->name, "FS")) continue; if (!se_calc_sha256_oneshot(sha_buf, ki->kip1, ki->size)) @@ -736,7 +724,7 @@ static bool _get_fs_exfat_compatible(link_t *info, u32 *hos_revision) pkg2_get_ids(&kip_ids, &fs_ids_cnt); - for (u32 fs_idx = 0; fs_idx < fs_ids_cnt; fs_idx++) + for (int fs_idx = fs_ids_cnt - 1; fs_idx >= 0; fs_idx--) { if (!memcmp(sha_buf, kip_ids[fs_idx].hash, 8)) { @@ -758,11 +746,11 @@ static bool _get_fs_exfat_compatible(link_t *info, u32 *hos_revision) break; } - // Hash didn't match or FAT32 + exFAT. + // FAT32 + exFAT or unknown FS version. return true; } -int hos_launch(ini_sec_t *cfg) +void hos_launch(ini_sec_t *cfg) { u8 kb; u32 secmon_base; @@ -770,9 +758,9 @@ int hos_launch(ini_sec_t *cfg) bool is_exo = false; launch_ctxt_t ctxt = {0}; tsec_ctxt_t tsec_ctxt = {0}; - volatile secmon_mailbox_t *secmon_mailbox; minerva_change_freq(FREQ_1600); + sdram_src_pllc(true); list_init(&ctxt.kip1_list); ctxt.cfg = cfg; @@ -787,31 +775,44 @@ int hos_launch(ini_sec_t *cfg) int res = emummc_storage_init_mmc(); if (res) { - if (res == 2) - _hos_crit_error("Failed to init eMMC."); - else - _hos_crit_error("Failed to init emuMMC."); + _hos_crit_error(res == 2 ? "Failed to init eMMC." : "Failed to init emuMMC."); goto error; } // Check if SD Card is GPT. if (sd_is_gpt()) - _hos_crit_error("SD has GPT only!"); - - // Read package1 and the correct keyblob. - if (!_read_emmc_pkg1(&ctxt)) + { + _hos_crit_error("SD has GPT only! Run Fix Hybrid MBR!"); goto error; - - kb = ctxt.pkg1_id->kb; + } // Try to parse config if present. - if (ctxt.cfg && !parse_boot_config(&ctxt)) + if (!parse_boot_config(&ctxt)) { _hos_crit_error("Wrong ini cfg or missing/corrupt files!"); goto error; } + // Read package1 and the correct keyblob. + if (!_read_emmc_pkg1(&ctxt)) + { + // Check if stock is enabled and device can boot in OFW. + if (ctxt.stock && (h_cfg.t210b01 || !tools_autorcm_enabled())) + { + sdram_src_pllc(false); + emmc_end(); + + WPRINTF("\nRebooting to OFW in 5s..."); + msleep(5000); + + power_set_state(REBOOT_BYPASS_FUSES); + } + goto error; + } + + kb = ctxt.pkg1_id->kb; + bool emummc_enabled = emu_cfg.enabled && !h_cfg.emummc_force_disable; // Enable emummc patching. @@ -823,7 +824,7 @@ int hos_launch(ini_sec_t *cfg) goto error; } - ctxt.atmosphere = true; // Set atmosphere patching in case of no fss0. + ctxt.patch_krn_proc_id = true; // Set kernel process id patching in case of no pkg3. config_kip1patch(&ctxt, "emummc"); } else if (!emu_cfg.enabled && ctxt.emummc_forced) @@ -838,7 +839,7 @@ int hos_launch(ini_sec_t *cfg) if (!ctxt.stock) { u32 fuses = fuse_read_odm(7); - if ((h_cfg.autonogc && + if ((h_cfg.autonogc && // Prevent GC fuse burning (sysMMC and emuMMC). ( (!(fuses & ~0xF) && (ctxt.pkg1_id->fuses >= 5)) || // LAFW v2, 4.0.0+ (!(fuses & ~0x3FF) && (ctxt.pkg1_id->fuses >= 11)) || // LAFW v3, 9.0.0+ @@ -847,12 +848,12 @@ int hos_launch(ini_sec_t *cfg) (!(fuses & ~0x3FFF) && (ctxt.pkg1_id->fuses >= 15)) // LAFW v5, 12.0.2+ ) ) - || ((emummc_enabled) && + || ((emummc_enabled) && // Force NOGC if already burnt (only emuMMC). ( - ((fuses & 0x400) && (ctxt.pkg1_id->fuses <= 10)) || // HOS 9.0.0+ fuses burnt. - ((fuses & 0x2000) && (ctxt.pkg1_id->fuses <= 13)) || // HOS 11.0.0+ fuses burnt. - // Detection broken! Use kip1patch=nogc // HOS 12.0.0+ - ((fuses & 0x4000) && (ctxt.pkg1_id->fuses <= 14)) // HOS 12.0.2+ fuses burnt. + ((fuses & BIT(10)) && (ctxt.pkg1_id->fuses <= 10)) || // HOS 9.0.0+ fuses burnt. + ((fuses & BIT(13)) && (ctxt.pkg1_id->fuses <= 13)) || // HOS 11.0.0+ fuses burnt. + // Detection broken! Use kip1patch=nogc // HOS 12.0.0+ + ((fuses & BIT(14)) && (ctxt.pkg1_id->fuses <= 14)) // HOS 12.0.2+ fuses burnt. ) )) config_kip1patch(&ctxt, "nogc"); @@ -863,17 +864,19 @@ int hos_launch(ini_sec_t *cfg) // Check if secmon is exosphere. if (ctxt.secmon) is_exo = !memcmp((void *)((u8 *)ctxt.secmon + ctxt.secmon_size - 4), "LENY", 4); + + // Get secmon and warmboot bases. const pkg1_id_t *pk1_latest = pkg1_get_latest(); - secmon_base = is_exo ? pk1_latest->secmon_base : ctxt.pkg1_id->secmon_base; + secmon_base = is_exo ? pk1_latest->secmon_base : ctxt.pkg1_id->secmon_base; warmboot_base = is_exo ? pk1_latest->warmboot_base : ctxt.pkg1_id->warmboot_base; - // Generate keys. - tsec_ctxt.fw = (u8 *)ctxt.pkg1 + ctxt.pkg1_id->tsec_off; - tsec_ctxt.pkg1 = ctxt.pkg1; + // Set package1 and tsec fw offsets. + tsec_ctxt.fw = (u8 *)ctxt.pkg1 + ctxt.pkg1_id->tsec_off; + tsec_ctxt.pkg1 = ctxt.pkg1; tsec_ctxt.pkg11_off = ctxt.pkg1_id->pkg11_off; - tsec_ctxt.secmon_base = secmon_base; - if (!hos_keygen(ctxt.keyblob, kb, &tsec_ctxt, ctxt.stock, is_exo)) + // Generate keys. + if (!_hos_keygen(ctxt.keyblob, kb, &tsec_ctxt, ctxt.stock, is_exo)) goto error; gfx_puts("Generated keys\n"); @@ -881,19 +884,28 @@ int hos_launch(ini_sec_t *cfg) if (!ctxt.warmboot || !ctxt.secmon) { // Decrypt PK1 or PK11. - if (kb <= KB_FIRMWARE_VERSION_600 || h_cfg.t210b01) + if (kb <= HOS_KB_VERSION_600 || h_cfg.t210b01) { if (!pkg1_decrypt(ctxt.pkg1_id, ctxt.pkg1)) { _hos_crit_error("Pkg1 decryption failed!"); + + // Check if T210B01 BEK is missing or wrong. if (h_cfg.t210b01) - EPRINTF("Is BEK missing?"); + { + u32 bek_vector[4] = {0}; + se_aes_crypt_ecb(13, ENCRYPT, bek_vector, SE_KEY_128_SIZE, bek_vector, SE_KEY_128_SIZE); + if (bek_vector[0] == 0x59C14895) // Encrypted zeroes first 32bits. + EPRINTF("Pkg1 corrupt?"); + else + EPRINTF("BEK is missing!"); + } goto error; } } // Unpack PK11. - if (h_cfg.t210b01 || (kb <= KB_FIRMWARE_VERSION_620 && !emummc_enabled)) + if (h_cfg.t210b01 || (kb <= HOS_KB_VERSION_620 && !emummc_enabled)) { // Skip T210B01 OEM header. u32 pk1_offset = 0; @@ -908,16 +920,16 @@ int hos_launch(ini_sec_t *cfg) } else { - _hos_crit_error("No mandatory secmon or warmboot provided!"); + _hos_crit_error("No mandatory pkg1 files provided!"); goto error; } } // Configure and manage Warmboot binary. - if (!pkg1_warmboot_config(&ctxt, warmboot_base)) + if (!pkg1_warmboot_config(&ctxt, warmboot_base, ctxt.pkg1_id->fuses, kb)) { // Can only happen on T210B01. - _hos_crit_error("Failed to match warmboot with fuses!\nIf you continue, sleep wont work!"); + _hos_crit_error("\nFailed to match warmboot with fuses!\nIf you continue, sleep wont work!"); gfx_puts("\nPress POWER to continue.\nPress VOL to go to the menu.\n"); display_backlight_brightness(h_cfg.backlight, 1000); @@ -932,7 +944,7 @@ int hos_launch(ini_sec_t *cfg) else if (!h_cfg.t210b01) { // Patch warmboot on T210 to allow downgrading. - if (kb >= KB_FIRMWARE_VERSION_700) + if (kb >= HOS_KB_VERSION_700) { _hos_crit_error("No warmboot provided!"); goto error; @@ -966,7 +978,7 @@ int hos_launch(ini_sec_t *cfg) _hos_crit_error("Pkg2 decryption failed!\npkg1/pkg2 mismatch or old hekate!"); // Clear EKS slot, in case something went wrong with tsec keygen. - hos_eks_clear(kb); + _hos_eks_clear(kb); goto error; } @@ -985,7 +997,7 @@ int hos_launch(ini_sec_t *cfg) ctxt.kernel = pkg2_hdr->data; ctxt.kernel_size = pkg2_hdr->sec_size[PKG2_SEC_KERNEL]; - if (!ctxt.stock && (ctxt.svcperm || ctxt.debugmode || ctxt.atmosphere)) + if (!ctxt.stock && (ctxt.svcperm || ctxt.debugmode || ctxt.patch_krn_proc_id)) { // Hash only Kernel when it embeds INI1. u8 kernel_hash[0x20]; @@ -1004,18 +1016,18 @@ int hos_launch(ini_sec_t *cfg) } // In case a kernel patch option is set; allows to disable SVC verification or/and enable debug mode. - kernel_patch_t *kernel_patchset = ctxt.pkg2_kernel_id->kernel_patchset; + const kernel_patch_t *kernel_patchset = ctxt.pkg2_kernel_id->kernel_patchset; if (kernel_patchset != NULL) { - gfx_printf("%kPatching kernel%k\n", 0xFFFFBA00, 0xFFCCCCCC); + gfx_printf("%kPatching kernel%k\n", TXT_CLR_ORANGE, TXT_CLR_DEFAULT); u32 *temp; for (u32 i = 0; kernel_patchset[i].id != 0xFFFFFFFF; i++) { if ((ctxt.svcperm && kernel_patchset[i].id == SVC_VERIFY_DS) - || (ctxt.debugmode && kernel_patchset[i].id == DEBUG_MODE_EN && !(ctxt.atmosphere && ctxt.secmon)) - || (ctxt.atmosphere && kernel_patchset[i].id == ATM_GEN_PATCH)) + || (ctxt.debugmode && kernel_patchset[i].id == DEBUG_MODE_EN && !(ctxt.patch_krn_proc_id && ctxt.secmon)) + || (ctxt.patch_krn_proc_id && kernel_patchset[i].id == ATM_GEN_PATCH)) *(vu32 *)(ctxt.kernel + kernel_patchset[i].off) = kernel_patchset[i].val; - else if (ctxt.atmosphere && kernel_patchset[i].id == ATM_ARR_PATCH) + else if (ctxt.patch_krn_proc_id && kernel_patchset[i].id == ATM_ARR_PATCH) { temp = (u32 *)kernel_patchset[i].ptr; for (u32 j = 0; j < kernel_patchset[i].val; j++) @@ -1033,7 +1045,7 @@ int hos_launch(ini_sec_t *cfg) pkg2_merge_kip(&kip1_info, (pkg2_kip1_t *)mki->kip1); // Check if FS is compatible with exFAT and if 5.1.0. - if (!ctxt.stock && (sd_fs.fs_type == FS_EXFAT || kb == KB_FIRMWARE_VERSION_500)) + if (!ctxt.stock && (sd_fs.fs_type == FS_EXFAT || kb == HOS_KB_VERSION_500 || ctxt.pkg1_id->fuses == 13)) { bool exfat_compat = _get_fs_exfat_compatible(&kip1_info, &ctxt.exo_ctx.hos_revision); @@ -1041,20 +1053,17 @@ int hos_launch(ini_sec_t *cfg) { _hos_crit_error("SD Card is exFAT but installed HOS driver\nonly supports FAT32!"); - _free_launch_components(&ctxt); goto error; } } // Patch kip1s in memory if needed. - if (ctxt.kip1_patches) - gfx_printf("%kPatching kips%k\n", 0xFFFFBA00, 0xFFCCCCCC); - const char* unappliedPatch = pkg2_patch_kips(&kip1_info, ctxt.kip1_patches); - if (unappliedPatch != NULL) + const char *failed_patch = pkg2_patch_kips(&kip1_info, ctxt.kip1_patches); + if (failed_patch != NULL) { - EHPRINTFARGS("Failed to apply '%s'!", unappliedPatch); + EHPRINTFARGS("Failed to apply '%s'!", failed_patch); - bool emmc_patch_failed = !strcmp(unappliedPatch, "emummc"); + bool emmc_patch_failed = !strcmp(failed_patch, "emummc"); if (!emmc_patch_failed) { gfx_puts("\nPress POWER to continue.\nPress VOL to go to the menu.\n"); @@ -1062,20 +1071,24 @@ int hos_launch(ini_sec_t *cfg) } if (emmc_patch_failed || !(btn_wait() & BTN_POWER)) - { - _free_launch_components(&ctxt); goto error; // MUST stop here, because if user requests 'nogc' but it's not applied, their GC controller gets updated! - } } // Rebuild and encrypt package2. - pkg2_build_encrypt((void *)PKG2_LOAD_ADDR, &ctxt, &kip1_info); + pkg2_build_encrypt((void *)PKG2_LOAD_ADDR, &ctxt, &kip1_info, is_exo); - gfx_printf("Rebuilt & loaded pkg2\n\n%kBooting...%k\n", 0xFF96FF00, 0xFFCCCCCC); + // Configure Exosphere if secmon is replaced. + if (is_exo) + config_exosphere(&ctxt, warmboot_base); - // Set initial mailbox values. - int bootStateDramPkg2 = 0; - int bootStatePkg2Continue = 0; + // Unmount SD card and eMMC. + sd_end(); + emmc_end(); + + // Close AHB aperture. Important when stock old secmon is used. + mc_disable_ahb_redirect(); + + gfx_printf("Rebuilt & loaded pkg2\n\n%kBooting...%k\n", TXT_CLR_GREENISH, TXT_CLR_DEFAULT); // Clear pkg1/pkg2 keys. se_aes_key_clear(8); @@ -1084,122 +1097,106 @@ int hos_launch(ini_sec_t *cfg) // Clear derived master key in case of Erista and 7.0.0+ se_aes_key_clear(9); + // Set secmon mailbox pkg2 ready state. + u32 pkg1_state_pkg2_ready = PKG1_STATE_PKG2_READY; + // Finalize per firmware key access. Skip access control if Exosphere 2. switch (kb | (is_exo << 7)) { - case KB_FIRMWARE_VERSION_100: - case KB_FIRMWARE_VERSION_300: - case KB_FIRMWARE_VERSION_301: + case HOS_KB_VERSION_100: + case HOS_KB_VERSION_300: + case HOS_KB_VERSION_301: se_key_acc_ctrl(12, SE_KEY_TBL_DIS_KEY_ACCESS_FLAG | SE_KEY_LOCK_FLAG); se_key_acc_ctrl(13, SE_KEY_TBL_DIS_KEY_ACCESS_FLAG | SE_KEY_LOCK_FLAG); - bootStateDramPkg2 = 2; - bootStatePkg2Continue = 3; + pkg1_state_pkg2_ready = PKG1_STATE_PKG2_READY_OLD; break; - case KB_FIRMWARE_VERSION_400: - case KB_FIRMWARE_VERSION_500: - case KB_FIRMWARE_VERSION_600: + case HOS_KB_VERSION_400: + case HOS_KB_VERSION_500: + case HOS_KB_VERSION_600: se_key_acc_ctrl(12, SE_KEY_TBL_DIS_KEY_ACCESS_FLAG | SE_KEY_LOCK_FLAG); se_key_acc_ctrl(15, SE_KEY_TBL_DIS_KEY_ACCESS_FLAG | SE_KEY_LOCK_FLAG); - default: - bootStateDramPkg2 = 2; - bootStatePkg2Continue = 4; break; } // Clear BCT area for retail units and copy it over if dev unit. - if (kb <= KB_FIRMWARE_VERSION_500 && !is_exo) + if (kb <= HOS_KB_VERSION_500 && !is_exo) { - memset((void *)SECMON_BCT_CFG_ADDR, 0, 0x3000); + memset((void *)SECMON_BCT_CFG_ADDR, 0, SZ_4K + SZ_8K); if (fuse_read_hw_state() == FUSE_NX_HW_STATE_DEV) - memcpy((void *)SECMON_BCT_CFG_ADDR, bootConfigBuf, 0x1000); + memcpy((void *)SECMON_BCT_CFG_ADDR, bootConfigBuf, SZ_4K); } else { - memset((void *)SECMON6_BCT_CFG_ADDR, 0, 0x800); + memset((void *)SECMON6_BCT_CFG_ADDR, 0, SZ_2K); if (fuse_read_hw_state() == FUSE_NX_HW_STATE_DEV) - memcpy((void *)SECMON6_BCT_CFG_ADDR, bootConfigBuf, 0x800); + memcpy((void *)SECMON6_BCT_CFG_ADDR, bootConfigBuf, SZ_2K); } - free(bootConfigBuf); - - // Config Exosphère if booting full Atmosphère. - if (is_exo) - config_exosphere(&ctxt, warmboot_base); - - // Unmount SD card and eMMC. - sd_end(); - sdmmc_storage_end(&emmc_storage); // Finalize MC carveout. - if (kb <= KB_FIRMWARE_VERSION_301 && !is_exo) + if (kb <= HOS_KB_VERSION_301 && !is_exo) mc_config_carveout(); // Lock SE before starting 'SecureMonitor' if < 6.2.0, otherwise lock bootrom and ipatches. - _se_lock(kb <= KB_FIRMWARE_VERSION_600 && !is_exo); + _se_lock(kb <= HOS_KB_VERSION_600 && !is_exo); - // Reset sysctr0 counters. - if (kb >= KB_FIRMWARE_VERSION_620) - _sysctr0_reset(); + // Reset sysctr0 counters. Mandatory for 6.2.0 and up. + for (u32 i = 0; i < SYSCTR0_COUNTERS; i++) + SYSCTR0(SYSCTR0_COUNTERS_BASE + i * sizeof(u32)) = 0; // NX Bootloader locks LP0 Carveout secure scratch registers. //pmc_scratch_lock(PMC_SEC_LOCK_LP0_PARAMS); // Set secmon mailbox address and clear it. - if (kb >= KB_FIRMWARE_VERSION_700 || is_exo) + volatile secmon_mailbox_t *secmon_mailbox; + if (kb >= HOS_KB_VERSION_700 || is_exo) { memset((void *)SECMON7_MAILBOX_ADDR, 0, 0x200); secmon_mailbox = (secmon_mailbox_t *)(SECMON7_MAILBOX_ADDR + SECMON_STATE_OFFSET); } else { - if (kb <= KB_FIRMWARE_VERSION_301) + if (kb <= HOS_KB_VERSION_301) memset((void *)SECMON_MAILBOX_ADDR, 0, 0x200); secmon_mailbox = (secmon_mailbox_t *)(SECMON_MAILBOX_ADDR + SECMON_STATE_OFFSET); } - // Start from DRAM ready signal and reset outgoing value. - secmon_mailbox->in = bootStateDramPkg2; - secmon_mailbox->out = 0; + // Start directly from PKG2 ready signal and reset outgoing value. + secmon_mailbox->in = pkg1_state_pkg2_ready; + secmon_mailbox->out = SECMON_STATE_NOT_READY; // Disable display. This must be executed before secmon to provide support for all fw versions. display_end(); + clock_disable_host1x(); - // Clear EMC_SCRATCH0. - EMC(EMC_SCRATCH0) = 0; + // Override uCID if set. + EMC(EMC_SCRATCH0) = ctxt.ucid; // Hold USBD, USB2, AHBDMA and APBDMA in reset for SoC state validation on sleep. CLOCK(CLK_RST_CONTROLLER_RST_DEV_L_SET) = BIT(CLK_L_USBD); CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = BIT(CLK_H_AHBDMA) | BIT(CLK_H_APBDMA) | BIT(CLK_H_USB2); + // Reset arbiter. + hw_config_arbiter(true); + + // Scale down RAM OC if enabled. + sdram_src_pllc(false); + minerva_prep_boot_freq(); + // Flush cache and disable MMU. bpmp_mmu_disable(); bpmp_clk_rate_set(BPMP_CLK_NORMAL); - // Scale down RAM OC if enabled. - if (ctxt.stock) - minerva_prep_boot_freq(); - - // emuMMC: Some cards (Sandisk U1), do not like a fast power cycle. Wait min 100ms. - sdmmc_storage_init_wait_sd(); - // Launch secmon. - if (smmu_is_used()) - smmu_exit(); - else - ccplex_boot_cpu0(secmon_base); + ccplex_boot_cpu0(secmon_base, true); - // Wait for secmon to get ready. - while (!secmon_mailbox->out) - ; - - // Signal pkg2 ready and continue boot. - secmon_mailbox->in = bootStatePkg2Continue; - - // Halt ourselves in waitevent state and resume if there's JTAG activity. + // Halt ourselves in wait-event state. while (true) bpmp_halt(); error: - sdmmc_storage_end(&emmc_storage); + _free_launch_components(&ctxt); + sdram_src_pllc(false); + emmc_end(); - return 0; + EPRINTF("\nFailed to launch HOS!"); } diff --git a/bootloader/hos/hos.h b/bootloader/hos/hos.h index a74e3b4..a04f650 100644 --- a/bootloader/hos/hos.h +++ b/bootloader/hos/hos.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2025 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,35 +18,43 @@ #ifndef _HOS_H_ #define _HOS_H_ +#include + #include "pkg1.h" #include "pkg2.h" -#include -#include -#include -#include #include -#define KB_FIRMWARE_VERSION_100 0 -#define KB_FIRMWARE_VERSION_300 1 -#define KB_FIRMWARE_VERSION_301 2 -#define KB_FIRMWARE_VERSION_400 3 -#define KB_FIRMWARE_VERSION_500 4 -#define KB_FIRMWARE_VERSION_600 5 -#define KB_FIRMWARE_VERSION_620 6 -#define KB_FIRMWARE_VERSION_700 7 -#define KB_FIRMWARE_VERSION_810 8 -#define KB_FIRMWARE_VERSION_900 9 -#define KB_FIRMWARE_VERSION_910 10 -#define KB_FIRMWARE_VERSION_1210 11 -#define KB_FIRMWARE_VERSION_1300 12 -#define KB_FIRMWARE_VERSION_MAX KB_FIRMWARE_VERSION_1300 //!TODO: Update on mkey changes. +//!TODO: Update on mkey changes. +enum { + HOS_KB_VERSION_100 = 0, + HOS_KB_VERSION_300 = 1, + HOS_KB_VERSION_301 = 2, + HOS_KB_VERSION_400 = 3, + HOS_KB_VERSION_500 = 4, + HOS_KB_VERSION_600 = 5, + HOS_KB_VERSION_620 = 6, + HOS_KB_VERSION_700 = 7, + HOS_KB_VERSION_810 = 8, + HOS_KB_VERSION_900 = 9, + HOS_KB_VERSION_910 = 10, + HOS_KB_VERSION_1210 = 11, + HOS_KB_VERSION_1300 = 12, + HOS_KB_VERSION_1400 = 13, + HOS_KB_VERSION_1500 = 14, + HOS_KB_VERSION_1600 = 15, + HOS_KB_VERSION_1700 = 16, + HOS_KB_VERSION_1800 = 17, + HOS_KB_VERSION_1900 = 18, + HOS_KB_VERSION_2000 = 19, + HOS_KB_VERSION_MAX = HOS_KB_VERSION_2000 +}; #define HOS_TSEC_VERSION 4 //! TODO: Update on TSEC Root Key changes. #define HOS_PKG11_MAGIC 0x31314B50 #define HOS_EKS_MAGIC 0x31534B45 // EKS1. -#define HOS_EKS_TSEC_VER (KB_FIRMWARE_VERSION_700 + HOS_TSEC_VERSION) +#define HOS_EKS_TSEC_VER (HOS_KB_VERSION_700 + HOS_TSEC_VERSION) // Use official Mariko secmon when in stock. Needs access to TZRAM. //#define HOS_MARIKO_STOCK_SECMON @@ -93,20 +101,22 @@ typedef struct _launch_ctxt_t u32 pkg2_size; bool new_pkg2; - void *kernel; - u32 kernel_size; + void *kernel; + u32 kernel_size; link_t kip1_list; - char* kip1_patches; + char *kip1_patches; bool svcperm; bool debugmode; bool stock; bool emummc_forced; - char *fss0_main_path; - u32 fss0_hosver; - bool atmosphere; + void *pkg3; + u32 pkg3_hosver; + bool patch_krn_proc_id; + + int ucid; exo_ctxt_t exo_ctx; @@ -119,8 +129,6 @@ typedef struct _merge_kip_t link_t link; } merge_kip_t; -void hos_eks_clear(u32 kb); -int hos_launch(ini_sec_t *cfg); -int hos_keygen(void *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt, bool stock, bool is_exo); +void hos_launch(ini_sec_t *cfg); #endif diff --git a/bootloader/hos/hos_config.c b/bootloader/hos/hos_config.c index 406e50d..6bfb4a7 100644 --- a/bootloader/hos/hos_config.c +++ b/bootloader/hos/hos_config.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2025 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,15 +17,12 @@ #include +#include + #include "hos.h" #include "hos_config.h" -#include "fss.h" +#include "pkg3.h" #include -#include -#include -#include - -#include //#define DPRINTF(...) gfx_printf(__VA_ARGS__) #define DPRINTF(...) @@ -61,14 +58,14 @@ static int _config_kip1(launch_ctxt_t *ctxt, const char *value) { u32 size; - if (!memcmp(value + strlen(value) - 1, "*", 1)) + if (value[strlen(value) - 1] == '*') { char *dir = (char *)malloc(256); strcpy(dir, value); u32 dirlen = 0; dir[strlen(dir) - 2] = 0; - char *filelist = dirlist(dir, "*.kip*", false, false); + dirlist_t *filelist = dirlist(dir, "*.kip*", false, false); strcat(dir, "/"); dirlen = strlen(dir); @@ -78,10 +75,10 @@ static int _config_kip1(launch_ctxt_t *ctxt, const char *value) { while (true) { - if (!filelist[i * 256]) + if (!filelist->name[i]) break; - strcpy(dir + dirlen, &filelist[i * 256]); + strcpy(dir + dirlen, filelist->name[i]); merge_kip_t *mkip1 = (merge_kip_t *)malloc(sizeof(merge_kip_t)); mkip1->kip1 = sd_file_read(dir, &size); @@ -122,30 +119,28 @@ static int _config_kip1(launch_ctxt_t *ctxt, const char *value) int config_kip1patch(launch_ctxt_t *ctxt, const char *value) { - if (value == NULL) - return 0; - - int valueLen = strlen(value); - if (!valueLen) + int len = strlen(value); + if (!len) return 0; if (ctxt->kip1_patches == NULL) { - ctxt->kip1_patches = malloc(valueLen + 1); - memcpy(ctxt->kip1_patches, value, valueLen); - ctxt->kip1_patches[valueLen] = 0; + ctxt->kip1_patches = malloc(len + 1); + memcpy(ctxt->kip1_patches, value, len); + ctxt->kip1_patches[len] = 0; } else { - char *oldAlloc = ctxt->kip1_patches; - int oldSize = strlen(oldAlloc); - ctxt->kip1_patches = malloc(oldSize + 1 + valueLen + 1); - memcpy(ctxt->kip1_patches, oldAlloc, oldSize); - free(oldAlloc); - oldAlloc = NULL; - ctxt->kip1_patches[oldSize++] = ','; - memcpy(&ctxt->kip1_patches[oldSize], value, valueLen); - ctxt->kip1_patches[oldSize + valueLen] = 0; + char *old_addr = ctxt->kip1_patches; + int old_len = strlen(old_addr); + + ctxt->kip1_patches = malloc(old_len + 1 + len + 1); + memcpy(ctxt->kip1_patches, old_addr, old_len); + free(old_addr); + + ctxt->kip1_patches[old_len++] = ','; + memcpy(&ctxt->kip1_patches[old_len], value, len); + ctxt->kip1_patches[old_len + len] = 0; } return 1; } @@ -190,12 +185,12 @@ static int _config_emummc_forced(launch_ctxt_t *ctxt, const char *value) return 1; } -static int _config_atmosphere(launch_ctxt_t *ctxt, const char *value) +static int _config_kernel_proc_id(launch_ctxt_t *ctxt, const char *value) { if (*value == '1') { - DPRINTF("Enabled atmosphere patching\n"); - ctxt->atmosphere = true; + DPRINTF("Enabled kernel process id send/recv patching\n"); + ctxt->patch_krn_proc_id = true; } return 1; } @@ -223,7 +218,7 @@ static int _config_exo_user_pmu_access(launch_ctxt_t *ctxt, const char *value) static int _config_exo_usb3_force(launch_ctxt_t *ctxt, const char *value) { // Override key found. - ctxt->exo_ctx.usb3_force = calloc(sizeof(bool), 1); + ctxt->exo_ctx.usb3_force = zalloc(sizeof(bool)); if (*value == '1') { @@ -236,7 +231,7 @@ static int _config_exo_usb3_force(launch_ctxt_t *ctxt, const char *value) static int _config_exo_cal0_blanking(launch_ctxt_t *ctxt, const char *value) { // Override key found. - ctxt->exo_ctx.cal0_blank = calloc(sizeof(bool), 1); + ctxt->exo_ctx.cal0_blank = zalloc(sizeof(bool)); if (*value == '1') { @@ -249,7 +244,7 @@ static int _config_exo_cal0_blanking(launch_ctxt_t *ctxt, const char *value) static int _config_exo_cal0_writes_enable(launch_ctxt_t *ctxt, const char *value) { // Override key found. - ctxt->exo_ctx.cal0_allow_writes_sys = calloc(sizeof(bool), 1); + ctxt->exo_ctx.cal0_allow_writes_sys = zalloc(sizeof(bool)); if (*value == '1') { @@ -260,9 +255,9 @@ static int _config_exo_cal0_writes_enable(launch_ctxt_t *ctxt, const char *value return 1; } -static int _config_fss(launch_ctxt_t *ctxt, const char *value) +static int _config_pkg3(launch_ctxt_t *ctxt, const char *value) { - return parse_fss(ctxt, value); + return parse_pkg3(ctxt, value); } static int _config_exo_fatal_payload(launch_ctxt_t *ctxt, const char *value) @@ -274,6 +269,14 @@ static int _config_exo_fatal_payload(launch_ctxt_t *ctxt, const char *value) return 1; } +static int _config_ucid(launch_ctxt_t *ctxt, const char *value) +{ + // Override uCID if set. + ctxt->ucid = atoi(value); + + return 1; +} + typedef struct _cfg_handler_t { const char *key; @@ -281,32 +284,42 @@ typedef struct _cfg_handler_t } cfg_handler_t; static const cfg_handler_t _config_handlers[] = { - { "warmboot", _config_warmboot }, - { "secmon", _config_secmon }, - { "kernel", _config_kernel }, - { "kip1", _config_kip1 }, - { "kip1patch", config_kip1patch }, - { "fullsvcperm", _config_svcperm }, - { "debugmode", _config_debugmode }, - { "stock", _config_stock }, - { "atmosphere", _config_atmosphere }, - { "fss0", _config_fss }, - { "exofatal", _config_exo_fatal_payload}, - { "emummcforce", _config_emummc_forced }, + { "stock", _config_stock }, + { "warmboot", _config_warmboot }, + { "secmon", _config_secmon }, + { "kernel", _config_kernel }, + { "kip1", _config_kip1 }, + { "kip1patch", config_kip1patch }, + { "fullsvcperm", _config_svcperm }, + { "debugmode", _config_debugmode }, + { "kernelprocid", _config_kernel_proc_id }, + + // To override elements from PKG3, it should be set before others. + { "pkg3", _config_pkg3 }, + { "fss0", _config_pkg3 }, + + { "exofatal", _config_exo_fatal_payload}, + { "emummcforce", _config_emummc_forced }, { "nouserexceptions", _config_dis_exo_user_exceptions }, - { "userpmu", _config_exo_user_pmu_access }, - { "usb3force", _config_exo_usb3_force }, - { "cal0blank", _config_exo_cal0_blanking }, - { "cal0writesys", _config_exo_cal0_writes_enable }, + { "userpmu", _config_exo_user_pmu_access }, + { "usb3force", _config_exo_usb3_force }, + { "cal0blank", _config_exo_cal0_blanking }, + { "cal0writesys", _config_exo_cal0_writes_enable }, + { "ucid", _config_ucid }, { NULL, NULL }, }; int parse_boot_config(launch_ctxt_t *ctxt) { + if (!ctxt->cfg) + return 1; + + // Check each config key. LIST_FOREACH_ENTRY(ini_kv_t, kv, &ctxt->cfg->kvs, link) { - for(u32 i = 0; _config_handlers[i].key; i++) + for (u32 i = 0; _config_handlers[i].key; i++) { + // If key matches, call its handler. if (!strcmp(_config_handlers[i].key, kv->key)) { if (!_config_handlers[i].handler(ctxt, kv->val)) @@ -316,6 +329,8 @@ int parse_boot_config(launch_ctxt_t *ctxt) return 0; } + + break; } } } diff --git a/bootloader/hos/pkg1.c b/bootloader/hos/pkg1.c index f4ae12c..9d6b783 100644 --- a/bootloader/hos/pkg1.c +++ b/bootloader/hos/pkg1.c @@ -1,7 +1,7 @@ /* * Copyright (c) 2018 naehrwert * Copyright (c) 2018 st4rk - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2025 CTCaer * Copyright (c) 2018 balika011 * * This program is free software; you can redistribute it and/or modify it @@ -20,19 +20,12 @@ #include #include +#include + #include "hos.h" #include "pkg1.h" #include "../config.h" -#include #include -#include -#include -#include -#include -#include -#include -#include -#include extern hekate_config h_cfg; @@ -40,7 +33,7 @@ extern hekate_config h_cfg; #define SM_100_ADR 0x4002B020 // Original: 0x40014020. PATCHSET_DEF(_secmon_1_patchset, // Patch the relocator to be able to run from SM_100_ADR. - { 0x1E0, _ADRP(0, 0x7C013000 - _PAGEOFF(SM_100_ADR)) }, + { 0x1E0, _ADRP(0, TZRAM_BASE + 0x3000 - _PAGEOFF(SM_100_ADR)) }, // Patch package2 signature/hash checks. { 0x9F0 + 0xADC, _NOP() } ); @@ -150,28 +143,36 @@ static const u8 sec_map_100[3] = { PK11_SECTION_SM, PK11_SECTION_LD, PK11_SECTIO static const u8 sec_map_2xx[3] = { PK11_SECTION_WB, PK11_SECTION_LD, PK11_SECTION_SM }; static const u8 sec_map_4xx[3] = { PK11_SECTION_LD, PK11_SECTION_SM, PK11_SECTION_WB }; - // ID (Timestamp), KB, Fuses, TSEC, PK11, SECMON, Warmboot. + // Timestamp KB FU TSEC PK11 SECMON Warmboot static const pkg1_id_t _pkg1_ids[] = { - { "20161121183008", 0, 1, 0x1900, 0x3FE0, SM_100_ADR, 0x8000D000, _secmon_1_patchset }, // 1.0.0 (Patched relocator). - { "20170210155124", 0, 2, 0x1900, 0x3FE0, 0x4002D000, 0x8000D000, _secmon_2_patchset }, // 2.0.0 - 2.3.0. - { "20170519101410", 1, 3, 0x1A00, 0x3FE0, 0x4002D000, 0x8000D000, _secmon_3_patchset }, // 3.0.0. - { "20170710161758", 2, 4, 0x1A00, 0x3FE0, 0x4002D000, 0x8000D000, _secmon_3_patchset }, // 3.0.1 - 3.0.2. - { "20170921172629", 3, 5, 0x1800, 0x3FE0, 0x4002B000, 0x4003B000, _secmon_4_patchset }, // 4.0.0 - 4.1.0. - { "20180220163747", 4, 6, 0x1900, 0x3FE0, 0x4002B000, 0x4003B000, _secmon_5_patchset }, // 5.0.0 - 5.1.0. - { "20180802162753", 5, 7, 0x1900, 0x3FE0, 0x4002B000, 0x4003D800, _secmon_6_patchset }, // 6.0.0 - 6.1.0. - { "20181107105733", 6, 8, 0x0E00, 0x6FE0, 0x4002B000, 0x4003D800, _secmon_62_patchset}, // 6.2.0. - { "20181218175730", 7, 9, 0x0F00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 7.0.0. - { "20190208150037", 7, 9, 0x0F00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 7.0.1. - { "20190314172056", 7, 9, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 8.0.0 - 8.0.1. - { "20190531152432", 8, 10, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 8.1.0 - 8.1.1. - { "20190809135709", 9, 11, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 9.0.0 - 9.0.1. - { "20191021113848", 10, 12, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 9.1.0 - 9.2.0. - { "20200303104606", 10, 13, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 10.0.0 - 10.2.0. - { "20201030110855", 10, 14, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 11.0.0 - 11.0.1. - { "20210129111626", 10, 14, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 12.0.0 - 12.0.1. - { "20210422145837", 10, 15, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 12.0.2 - 12.0.3. - { "20210607122020", 11, 15, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 12.1.0. - { "20210805123738", 12, 15, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 13.0.0+ + { "20161121", 0, 1, 0x1900, 0x3FE0, SM_100_ADR, 0x8000D000, _secmon_1_patchset }, // 1.0.0 (Patched relocator). + { "20170210", 0, 2, 0x1900, 0x3FE0, 0x4002D000, 0x8000D000, _secmon_2_patchset }, // 2.0.0 - 2.3.0. + { "20170519", 1, 3, 0x1A00, 0x3FE0, 0x4002D000, 0x8000D000, _secmon_3_patchset }, // 3.0.0. + { "20170710", 2, 4, 0x1A00, 0x3FE0, 0x4002D000, 0x8000D000, _secmon_3_patchset }, // 3.0.1 - 3.0.2. + { "20170921", 3, 5, 0x1800, 0x3FE0, 0x4002B000, 0x4003B000, _secmon_4_patchset }, // 4.0.0 - 4.1.0. + { "20180220", 4, 6, 0x1900, 0x3FE0, 0x4002B000, 0x4003B000, _secmon_5_patchset }, // 5.0.0 - 5.1.0. + { "20180802", 5, 7, 0x1900, 0x3FE0, 0x4002B000, 0x4003D800, _secmon_6_patchset }, // 6.0.0 - 6.1.0. + { "20181107", 6, 8, 0x0E00, 0x6FE0, 0x4002B000, 0x4003D800, _secmon_62_patchset}, // 6.2.0. + { "20181218", 7, 9, 0x0F00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 7.0.0. + { "20190208", 7, 9, 0x0F00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 7.0.1. + { "20190314", 7, 9, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 8.0.0 - 8.0.1. + { "20190531", 8, 10, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 8.1.0 - 8.1.1. + { "20190809", 9, 11, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 9.0.0 - 9.0.1. + { "20191021", 10, 12, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 9.1.0 - 9.2.0. + { "20200303", 10, 13, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 10.0.0 - 10.2.0. + { "20201030", 10, 14, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 11.0.0 - 11.0.1. + { "20210129", 10, 14, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 12.0.0 - 12.0.1. + { "20210422", 10, 15, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 12.0.2 - 12.0.3. + { "20210607", 11, 15, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 12.1.0. + { "20210805", 12, 15, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 13.0.0 - 13.2.0. + { "20220105", 12, 16, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 13.2.1. + { "20220209", 13, 16, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 14.0.0 - 14.1.2. + { "20220801", 14, 17, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 15.0.0 - 15.0.1. + { "20230111", 15, 18, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 16.0.0 - 16.1.0. + { "20230906", 16, 19, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 17.0.0 - 17.0.1. + { "20240207", 17, 19, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 18.0.0 - 18.1.0. + { "20240808", 18, 20, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 19.0.0 - 19.0.1. + { "20250206", 19, 21, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000, NULL }, // 20.0.0+ }; const pkg1_id_t *pkg1_get_latest() @@ -182,13 +183,16 @@ const pkg1_id_t *pkg1_get_latest() const pkg1_id_t *pkg1_identify(u8 *pkg1) { char build_date[15]; - memcpy(build_date, (char *)(pkg1 + 0x10), 14); + pk1_hdr_t *hdr = (pk1_hdr_t *)pkg1; + + memcpy(build_date, hdr->timestamp, 14); build_date[14] = 0; gfx_printf("Found pkg1 ('%s').\n\n", build_date); - for (u32 i = 0; i < ARRAY_SIZE(_pkg1_ids); i++) - if (!memcmp(pkg1 + 0x10, _pkg1_ids[i].id, 8)) + for (int i = ARRAY_SIZE(_pkg1_ids) - 1; i >= 0; i--) + if (!memcmp(hdr->timestamp, _pkg1_ids[i].id, 8)) return &_pkg1_ids[i]; + return NULL; } @@ -226,7 +230,6 @@ const u8 *pkg1_unpack(void *wm_dst, u32 *wb_sz, void *sm_dst, void *ldr_dst, con const pk11_hdr_t *hdr = (pk11_hdr_t *)(pkg1 + id->pkg11_off + 0x20); u32 sec_size[3] = { hdr->wb_size, hdr->ldr_size, hdr->sm_size }; - //u32 sec_off[3] = { hdr->wb_off, hdr->ldr_off, hdr->sm_off }; // Get correct header mapping. if (id->fuses == 1) // 1.0.0. @@ -240,17 +243,25 @@ const u8 *pkg1_unpack(void *wm_dst, u32 *wb_sz, void *sm_dst, void *ldr_dst, con u8 *pdata = (u8 *)hdr + sizeof(pk11_hdr_t); for (u32 i = 0; i < 3; i++) { - if (sec_map[i] == PK11_SECTION_WB && wm_dst) + u32 ssize = sec_size[sec_map[i]]; + switch (sec_map[i]) { - memcpy(wm_dst, pdata, sec_size[sec_map[i]]); + case PK11_SECTION_WB: + if (wm_dst) + memcpy(wm_dst, pdata, ssize); if (wb_sz) - *wb_sz = sec_size[sec_map[i]]; + *wb_sz = ssize; + break; + case PK11_SECTION_LD: + if (ldr_dst) + memcpy(ldr_dst, pdata, ssize); + break; + case PK11_SECTION_SM: + if (sm_dst) + memcpy(sm_dst, pdata, ssize); + break; } - else if (sec_map[i] == PK11_SECTION_LD && ldr_dst) - memcpy(ldr_dst, pdata, sec_size[sec_map[i]]); - else if (sec_map[i] == PK11_SECTION_SM && sm_dst) - memcpy(sm_dst, pdata, sec_size[sec_map[i]]); - pdata += sec_size[sec_map[i]]; + pdata += ssize; } return sec_map; @@ -258,7 +269,7 @@ const u8 *pkg1_unpack(void *wm_dst, u32 *wb_sz, void *sm_dst, void *ldr_dst, con void pkg1_secmon_patch(void *hos_ctxt, u32 secmon_base, bool t210b01) { - patch_t *secmon_patchset; + const patch_t *secmon_patchset; launch_ctxt_t *ctxt = (launch_ctxt_t *)hos_ctxt; // Patch Secmon to allow for an unsigned package2 and patched kernel. @@ -271,9 +282,9 @@ void pkg1_secmon_patch(void *hos_ctxt, u32 secmon_base, bool t210b01) else if (t210b01) { // For T210B01 we patch 6.X.X as is. Otherwise we decompress the program payload. - if (ctxt->pkg1_id->kb == KB_FIRMWARE_VERSION_600) + if (ctxt->pkg1_id->kb == HOS_KB_VERSION_600) secmon_patchset = _secmon_6_mariko_patchset; - else if (ctxt->pkg1_id->kb == KB_FIRMWARE_VERSION_620) + else if (ctxt->pkg1_id->kb == HOS_KB_VERSION_620) secmon_patchset = _secmon_620_mariko_patchset; else { @@ -282,9 +293,9 @@ void pkg1_secmon_patch(void *hos_ctxt, u32 secmon_base, bool t210b01) memset((void *)TZRAM_PROG_ADDR, 0, 0x38800); // Get size of compressed program payload and set patch offset. - u32 idx = ctxt->pkg1_id->kb - KB_FIRMWARE_VERSION_700; + u32 idx = ctxt->pkg1_id->kb - HOS_KB_VERSION_700; u32 patch_offset = TZRAM_PROG_PK2_SIG_PATCH; - if (ctxt->pkg1_id->kb > KB_FIRMWARE_VERSION_910 || !memcmp(ctxt->pkg1_id->id, "20200303104606", 8)) //TODO: Add 11.0.0 support. + if (ctxt->pkg1_id->kb > HOS_KB_VERSION_910 || !memcmp(ctxt->pkg1_id->id, "20200303", 8)) //TODO: Add 11.0.0 support. { idx++; patch_offset = TZRAM_PROG_PK2_SIG_PATCH_1000; @@ -303,7 +314,7 @@ void pkg1_secmon_patch(void *hos_ctxt, u32 secmon_base, bool t210b01) return; // Patch Secmon. - gfx_printf("%kPatching Secure Monitor%k\n", 0xFFFFBA00, 0xFFCCCCCC); + gfx_printf("%kPatching Secure Monitor%k\n", TXT_CLR_ORANGE, TXT_CLR_DEFAULT); for (u32 i = 0; secmon_patchset[i].off != 0xFFFFFFFF; i++) *(vu32 *)(secmon_base + secmon_patchset[i].off) = secmon_patchset[i].val; } @@ -311,7 +322,7 @@ void pkg1_secmon_patch(void *hos_ctxt, u32 secmon_base, bool t210b01) void pkg1_warmboot_patch(void *hos_ctxt) { launch_ctxt_t *ctxt = (launch_ctxt_t *)hos_ctxt; - patch_t *warmboot_patchset; + const patch_t *warmboot_patchset; // Patch warmboot on T210 to allow downgrading. switch (ctxt->pkg1_id->kb) @@ -326,7 +337,7 @@ void pkg1_warmboot_patch(void *hos_ctxt) warmboot_patchset = _warmboot_4_patchset; break; } - gfx_printf("%kPatching Warmboot%k\n", 0xFFFFBA00, 0xFFCCCCCC); + gfx_printf("%kPatching Warmboot%k\n", TXT_CLR_ORANGE, TXT_CLR_DEFAULT); for (u32 i = 0; warmboot_patchset[i].off != 0xFFFFFFFF; i++) *(vu32 *)(ctxt->pkg1_id->warmboot_base + warmboot_patchset[i].off) = warmboot_patchset[i].val; } @@ -343,32 +354,30 @@ static void _warmboot_filename(char *out, u32 fuses) strcat(out, ".bin"); } -int pkg1_warmboot_config(void *hos_ctxt, u32 warmboot_base) +int pkg1_warmboot_config(void *hos_ctxt, u32 warmboot_base, u32 fuses_fw, u8 kb) { launch_ctxt_t *ctxt = (launch_ctxt_t *)hos_ctxt; - u32 kb = ctxt->pkg1_id->kb; int res = 1; - // Set warmboot address in PMC if required. - if (kb <= KB_FIRMWARE_VERSION_301) - PMC(APBDEV_PMC_SCRATCH1) = warmboot_base; - if (h_cfg.t210b01) { u32 pa_id; u32 fuses_max = 32; // Current ODM7 max. - u32 fuses_fw = ctxt->pkg1_id->fuses; u8 burnt_fuses = bit_count(fuse_read_odm(7)); // Save current warmboot in storage cache (MWS) and check if another one is needed. if (!ctxt->warmboot) { char path[128]; - f_mkdir("warmboot_mariko"); strcpy(path, "warmboot_mariko/wb_"); _warmboot_filename(path, fuses_fw); - if (f_stat(path, NULL)) + + // Check if warmboot fw exists and save it. + if (ctxt->warmboot_size && f_stat(path, NULL)) + { + f_mkdir("warmboot_mariko"); sd_save_to_file((void *)warmboot_base, ctxt->warmboot_size, path); + } // Load warmboot fw from storage (MWS) if not matched. if (burnt_fuses > fuses_fw) @@ -388,7 +397,7 @@ int pkg1_warmboot_config(void *hos_ctxt, u32 warmboot_base) tmp_fuses++; } - // Check if proper warmboot firmware was found. + // Check if proper warmboot firmware was not found. if (!ctxt->warmboot) res = 0; } @@ -399,15 +408,11 @@ int pkg1_warmboot_config(void *hos_ctxt, u32 warmboot_base) // Configure Warmboot parameters. Anything lower is not supported. switch (burnt_fuses) { - case 7: - pa_id = 0x87; + case 7 ... 8: + pa_id = 0x21 * (burnt_fuses - 3) + 3; break; - case 8: // 0x21 raise. - pa_id = 0xA8; - break; - default: // From 7.0.0 and up PA id raises by 0x21 with a static base. - pa_id = 0x108; - pa_id += 0x21 * (burnt_fuses - 8); + default: // From 7.0.0 and up PA id is 0x21 multiplied with fuses. + pa_id = 0x21 * burnt_fuses; break; } @@ -417,12 +422,48 @@ int pkg1_warmboot_config(void *hos_ctxt, u32 warmboot_base) } else { + // Set warmboot address in PMC if required. + if (kb <= HOS_KB_VERSION_301) + PMC(APBDEV_PMC_SCRATCH1) = warmboot_base; + // Set Warmboot Physical Address ID for 3.0.0 - 3.0.2. - if (kb == KB_FIRMWARE_VERSION_300) + if (kb == HOS_KB_VERSION_300) PMC(APBDEV_PMC_SECURE_SCRATCH32) = 0xE3; // Warmboot 3.0.0 PA address id. - else if (kb == KB_FIRMWARE_VERSION_301) + else if (kb == HOS_KB_VERSION_301) PMC(APBDEV_PMC_SECURE_SCRATCH32) = 0x104; // Warmboot 3.0.1/.2 PA address id. } return res; } + +void pkg1_warmboot_rsa_mod(u32 warmboot_base) +{ + // Set warmboot binary rsa modulus. + u8 *rsa_mod = (u8 *)malloc(EMMC_BLOCKSIZE); + + emmc_set_partition(EMMC_BOOT0); + + u32 sector; + u8 mod0, mod1; + + // Get the correct RSA modulus byte masks. + nx_emmc_get_autorcm_masks(&mod0, &mod1); + + // Iterate BCTs. + for (u32 i = 0; i < 4; i++) + { + sector = 1 + (32 * i); // 0x4000 bct + 0x200 offset. + sdmmc_storage_read(&emmc_storage, sector, 1, rsa_mod); + + // Check if 2nd byte of modulus is correct. + if (rsa_mod[0x11] != mod1) + continue; + + // Patch AutoRCM out. + rsa_mod[0x10] = mod0; + + break; + } + + memcpy((void *)(warmboot_base + 0x10), rsa_mod + 0x10, 0x100); +} diff --git a/bootloader/hos/pkg1.h b/bootloader/hos/pkg1.h index 15565c0..c0dab9a 100644 --- a/bootloader/hos/pkg1.h +++ b/bootloader/hos/pkg1.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2018 naehrwert + * Copyright (c) 2022-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,7 +18,7 @@ #ifndef _PKG1_H_ #define _PKG1_H_ -#include +#include #define PKG1_MAGIC 0x31314B50 @@ -25,6 +26,14 @@ #define PK11_SECTION_LD 1 #define PK11_SECTION_SM 2 +#define PKG1_BOOTLOADER_SIZE SZ_256K +#define PKG1_BOOTLOADER_MAIN_OFFSET 0x100000 +#define PKG1_BOOTLOADER_BACKUP_OFFSET 0x140000 +#define PKG1_HOS_KEYBLOBS_OFFSET 0x180000 + +#define PKG1_ERISTA_ON_MARIKO_MAGIC 0xE59FD00C // For 4.0.0 Erista and up. +#define PKG1_MARIKO_ON_ERISTA_MAGIC 0x40010040 // Mariko pkg1 entrypoint. + typedef struct _patch_t { u32 off; @@ -32,24 +41,35 @@ typedef struct _patch_t } patch_t; #define PATCHSET_DEF(name, ...) \ - patch_t name[] = { \ + const patch_t name[] = { \ __VA_ARGS__, \ { 0xFFFFFFFF, 0xFFFFFFFF } \ } typedef struct _bl_hdr_t210b01_t { - u8 aes_mac[0x10]; - u8 rsa_sig[0x100]; - u8 salt[0x20]; - u8 sha256[0x20]; - u32 version; - u32 size; - u32 load_addr; - u32 entrypoint; - u8 rsvd[0x10]; +/* 0x000 */ u8 aes_mac[0x10]; +/* 0x010 */ u8 rsa_sig[0x100]; +/* 0x110 */ u8 salt[0x20]; +/* 0x130 */ u8 sha256[0x20]; +/* 0x150 */ u32 version; +/* 0x154 */ u32 size; +/* 0x158 */ u32 load_addr; +/* 0x15C */ u32 entrypoint; +/* 0x160 */ u8 rsvd[0x10]; } bl_hdr_t210b01_t; +typedef struct _pk1_hdr_t +{ +/* 0x00 */ u32 si_sha256; // Secure Init. +/* 0x04 */ u32 sm_sha256; // Secure Monitor. +/* 0x08 */ u32 sl_sha256; // Secure Loader. +/* 0x0C */ u32 unk; // what's this? It's not warmboot. +/* 0x10 */ char timestamp[14]; +/* 0x1E */ u8 keygen; +/* 0x1F */ u8 version; +} pk1_hdr_t; + typedef struct _pkg1_id_t { const char *id; @@ -59,7 +79,7 @@ typedef struct _pkg1_id_t u16 pkg11_off; u32 secmon_base; u32 warmboot_base; - patch_t *secmon_patchset; + const patch_t *secmon_patchset; } pkg1_id_t; typedef struct _pk11_hdr_t @@ -80,6 +100,7 @@ int pkg1_decrypt(const pkg1_id_t *id, u8 *pkg1); const u8 *pkg1_unpack(void *wm_dst, u32 *wb_sz, void *sm_dst, void *ldr_dst, const pkg1_id_t *id, u8 *pkg1); void pkg1_secmon_patch(void *hos_ctxt, u32 secmon_base, bool t210b01); void pkg1_warmboot_patch(void *hos_ctxt); -int pkg1_warmboot_config(void *hos_ctxt, u32 warmboot_base); +int pkg1_warmboot_config(void *hos_ctxt, u32 warmboot_base, u32 fuses_fw, u8 kb); +void pkg1_warmboot_rsa_mod(u32 warmboot_base); #endif diff --git a/bootloader/hos/pkg2.c b/bootloader/hos/pkg2.c index cb3d74b..4ad838c 100644 --- a/bootloader/hos/pkg2.c +++ b/bootloader/hos/pkg2.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2025 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,6 +17,8 @@ #include +#include + #include "hos.h" #include "pkg2.h" #include "pkg2_ini_kippatch.h" @@ -24,29 +26,18 @@ #include "../config.h" #include #include -#include -#include -#include #include "../storage/emummc.h" -#include -#include -#include +//#define DPRINTF(...) gfx_printf(__VA_ARGS__) +#define DPRINTF(...) extern hekate_config h_cfg; extern const u8 package2_keyseed[]; -u32 pkg2_newkern_ini1_val; +u32 pkg2_newkern_ini1_info; u32 pkg2_newkern_ini1_start; u32 pkg2_newkern_ini1_end; - -#ifdef KIP1_PATCH_DEBUG - #include - #define DPRINTF(...) gfx_printf(__VA_ARGS__) - #define DEBUG_PRINTING -#else - #define DPRINTF(...) -#endif +u32 pkg2_newkern_ini1_rela; enum kip_offset_section { @@ -63,11 +54,11 @@ enum kip_offset_section #define KIP_PATCH_OFFSET_MASK (~KIP_PATCH_SECTION_MASK) #define GET_KIP_PATCH_SECTION(x) (((x) >> KIP_PATCH_SECTION_SHIFT) & 7) #define GET_KIP_PATCH_OFFSET(x) ((x) & KIP_PATCH_OFFSET_MASK) -#define KPS(x) ((u32)(x) << KIP_PATCH_SECTION_SHIFT) +#define KPS(x) ((u32)(x) << KIP_PATCH_SECTION_SHIFT) #include "pkg2_patches.inl" -static kip1_id_t *_kip_id_sets = _kip_ids; +static kip1_id_t *_kip_id_sets = (kip1_id_t *)_kip_ids; static u32 _kip_id_sets_cnt = ARRAY_SIZE(_kip_ids); void pkg2_get_ids(kip1_id_t **ids, u32 *entries) @@ -78,118 +69,109 @@ void pkg2_get_ids(kip1_id_t **ids, u32 *entries) static void parse_external_kip_patches() { - static bool ext_patches_done = false; + static bool ext_patches_parsed = false; - if (ext_patches_done) + if (ext_patches_parsed) return; - u32 curr_kip_idx = 0; - char path[64]; - strcpy(path, "bootloader/patches.ini"); - LIST_INIT(ini_kip_sections); - if (ini_patch_parse(&ini_kip_sections, path)) + if (ini_patch_parse(&ini_kip_sections, "bootloader/patches.ini")) { // Copy ids into a new patchset. - _kip_id_sets = calloc(sizeof(kip1_id_t), 256); // Max 256 kip ids. + _kip_id_sets = zalloc(sizeof(kip1_id_t) * 256); // Max 256 kip ids. memcpy(_kip_id_sets, _kip_ids, sizeof(_kip_ids)); // Parse patchsets and glue them together. LIST_FOREACH_ENTRY(ini_kip_sec_t, ini_psec, &ini_kip_sections, link) { - kip1_id_t* curr_kip = NULL; + kip1_id_t *kip = NULL; bool found = false; - for (curr_kip_idx = 0; curr_kip_idx < _kip_id_sets_cnt + 1; curr_kip_idx++) + for (u32 kip_idx = 0; kip_idx < _kip_id_sets_cnt + 1; kip_idx++) { - curr_kip = &_kip_id_sets[curr_kip_idx]; + kip = &_kip_id_sets[kip_idx]; - if (!curr_kip->name) + // Check if reached the end of predefined list. + if (!kip->name) break; - if (!strcmp(curr_kip->name, ini_psec->name) && !memcmp(curr_kip->hash, ini_psec->hash, 8)) + // Check if name and hash match. + if (!strcmp(kip->name, ini_psec->name) && !memcmp(kip->hash, ini_psec->hash, 8)) { found = true; break; } } - if (!curr_kip) + if (!kip) continue; // If not found, create a new empty entry. if (!found) { - curr_kip->name = ini_psec->name; - memcpy(curr_kip->hash, ini_psec->hash, 8); - curr_kip->patchset = calloc(sizeof(kip1_patchset_t), 1); + kip->name = ini_psec->name; + memcpy(kip->hash, ini_psec->hash, 8); + kip->patchset = zalloc(sizeof(kip1_patchset_t)); _kip_id_sets_cnt++; } - kip1_patchset_t *patchsets = (kip1_patchset_t *)calloc(sizeof(kip1_patchset_t), 16); // Max 16 patchsets per kip. + kip1_patchset_t *patchsets = (kip1_patchset_t *)zalloc(sizeof(kip1_patchset_t) * 16); // Max 16 patchsets per kip. - u32 curr_patchset_idx; - for(curr_patchset_idx = 0; curr_kip->patchset[curr_patchset_idx].name != NULL; curr_patchset_idx++) + u32 patchset_idx; + for (patchset_idx = 0; kip->patchset[patchset_idx].name != NULL; patchset_idx++) { - patchsets[curr_patchset_idx].name = curr_kip->patchset[curr_patchset_idx].name; - patchsets[curr_patchset_idx].patches = curr_kip->patchset[curr_patchset_idx].patches; + patchsets[patchset_idx].name = kip->patchset[patchset_idx].name; + patchsets[patchset_idx].patches = kip->patchset[patchset_idx].patches; } - curr_kip->patchset = patchsets; + kip->patchset = patchsets; bool first_ext_patch = true; - u32 curr_patch_idx = 0; + u32 patch_idx = 0; // Parse patches and glue them together to a patchset. - kip1_patch_t *patches = calloc(sizeof(kip1_patch_t), 32); // Max 32 patches per set. + kip1_patch_t *patches = zalloc(sizeof(kip1_patch_t) * 32); // Max 32 patches per set. LIST_FOREACH_ENTRY(ini_patchset_t, pt, &ini_psec->pts, link) { if (first_ext_patch) { first_ext_patch = false; - patchsets[curr_patchset_idx].name = malloc(strlen(pt->name) + 1); - strcpy(patchsets[curr_patchset_idx].name, pt->name); - patchsets[curr_patchset_idx].patches = patches; + patchsets[patchset_idx].name = pt->name; + patchsets[patchset_idx].patches = patches; } - else + else if (strcmp(pt->name, patchsets[patchset_idx].name)) { - // Check if new patchset name is found and create a new set. - if (strcmp(pt->name, patchsets[curr_patchset_idx].name)) - { - curr_patchset_idx++; - curr_patch_idx = 0; - patches = calloc(sizeof(kip1_patch_t), 16); // Max 16 patches per set. + // New patchset name found, create a new set. + patchset_idx++; + patch_idx = 0; + patches = zalloc(sizeof(kip1_patch_t) * 32); // Max 32 patches per set. - patchsets[curr_patchset_idx].name = malloc(strlen(pt->name) + 1); - strcpy(patchsets[curr_patchset_idx].name, pt->name); - patchsets[curr_patchset_idx].patches = patches; - } + patchsets[patchset_idx].name = pt->name; + patchsets[patchset_idx].patches = patches; } if (pt->length) { - patches[curr_patch_idx].offset = pt->offset; - patches[curr_patch_idx].length = pt->length; + patches[patch_idx].offset = pt->offset; + patches[patch_idx].length = pt->length; - patches[curr_patch_idx].srcData = malloc(pt->length); - patches[curr_patch_idx].dstData = malloc(pt->length); - memcpy(patches[curr_patch_idx].srcData, pt->srcData, pt->length); - memcpy(patches[curr_patch_idx].dstData, pt->dstData, pt->length); + patches[patch_idx].src_data = (char *)pt->src_data; + patches[patch_idx].dst_data = (char *)pt->dst_data; } else - patches[curr_patch_idx].srcData = malloc(1); // Empty patches check. Keep everything else as 0. + patches[patch_idx].src_data = malloc(1); // Empty patches check. Keep everything else as 0. - curr_patch_idx++; + patch_idx++; } - curr_patchset_idx++; - patchsets[curr_patchset_idx].name = NULL; - patchsets[curr_patchset_idx].patches = NULL; + patchset_idx++; + patchsets[patchset_idx].name = NULL; + patchsets[patchset_idx].patches = NULL; } } - ext_patches_done = true; + ext_patches_parsed = true; } -const pkg2_kernel_id_t *pkg2_identify(u8 *hash) +const pkg2_kernel_id_t *pkg2_identify(const u8 *hash) { for (u32 i = 0; i < ARRAY_SIZE(_pkg2_kernel_ids); i++) { @@ -207,18 +189,29 @@ static u32 _pkg2_calc_kip1_size(pkg2_kip1_t *kip1) return size; } -void pkg2_get_newkern_info(u8 *kern_data) +static void _pkg2_get_newkern_info(u8 *kern_data) { - u32 pkg2_newkern_ini1_off = 0; + u32 crt_start = 0; + pkg2_newkern_ini1_info = 0; pkg2_newkern_ini1_start = 0; + pkg2_newkern_ini1_rela = 0; + + u32 first_op = *(u32 *)kern_data; + if ((first_op & 0xFE000000) == 0x14000000) + crt_start = (first_op & 0x1FFFFFF) << 2; // Find static OP offset that is close to INI1 offset. u32 counter_ops = 0x100; while (counter_ops) { - if (*(u32 *)(kern_data + 0x100 - counter_ops) == PKG2_NEWKERN_GET_INI1_HEURISTIC) + if (*(u32 *)(kern_data + crt_start + 0x100 - counter_ops) == PKG2_NEWKERN_GET_INI1_HEURISTIC) { - pkg2_newkern_ini1_off = 0x100 - counter_ops + 12; // OP found. Add 12 for the INI1 offset. + // OP found. Add 12 for the INI1 info offset. + pkg2_newkern_ini1_info = crt_start + 0x100 - counter_ops + 12; + + // On v2 kernel with dynamic crt there's a NOP after heuristic. Offset one op. + if (crt_start) + pkg2_newkern_ini1_info += 4; break; } @@ -229,11 +222,19 @@ void pkg2_get_newkern_info(u8 *kern_data) if (!counter_ops) return; - u32 info_op = *(u32 *)(kern_data + pkg2_newkern_ini1_off); - pkg2_newkern_ini1_val = ((info_op & 0xFFFF) >> 3) + pkg2_newkern_ini1_off; // Parse ADR and PC. + u32 info_op = *(u32 *)(kern_data + pkg2_newkern_ini1_info); + pkg2_newkern_ini1_info += ((info_op & 0xFFFF) >> 3); // Parse ADR and PC. - pkg2_newkern_ini1_start = *(u32 *)(kern_data + pkg2_newkern_ini1_val); - pkg2_newkern_ini1_end = *(u32 *)(kern_data + pkg2_newkern_ini1_val + 0x8); + pkg2_newkern_ini1_start = *(u32 *)(kern_data + pkg2_newkern_ini1_info); + pkg2_newkern_ini1_end = *(u32 *)(kern_data + pkg2_newkern_ini1_info + 0x8); + + // On v2 kernel with dynamic crt, values are relative to value address. + if (crt_start) + { + pkg2_newkern_ini1_rela = pkg2_newkern_ini1_info; + pkg2_newkern_ini1_start += pkg2_newkern_ini1_info; + pkg2_newkern_ini1_end += pkg2_newkern_ini1_info + 0x8; + } } bool pkg2_parse_kips(link_t *info, pkg2_hdr_t *pkg2, bool *new_pkg2) @@ -242,7 +243,7 @@ bool pkg2_parse_kips(link_t *info, pkg2_hdr_t *pkg2, bool *new_pkg2) // Check for new pkg2 type. if (!pkg2->sec_size[PKG2_SEC_INI1]) { - pkg2_get_newkern_info(pkg2->data); + _pkg2_get_newkern_info(pkg2->data); if (!pkg2_newkern_ini1_start) return false; @@ -273,7 +274,7 @@ DPRINTF(" kip1 %d:%s @ %08X (%08X)\n", i, kip1->name, (u32)kip1, ki->size); int pkg2_has_kip(link_t *info, u64 tid) { LIST_FOREACH_ENTRY(pkg2_kip1_info_t, ki, info, link) - if(ki->kip1->tid == tid) + if (ki->kip1->tid == tid) return 1; return 0; } @@ -309,7 +310,7 @@ void pkg2_merge_kip(link_t *info, pkg2_kip1_t *kip1) pkg2_add_kip(info, kip1); } -int pkg2_decompress_kip(pkg2_kip1_info_t* ki, u32 sectsToDecomp) +static int _decompress_kip(pkg2_kip1_info_t *ki, u32 sectsToDecomp) { u32 compClearMask = ~sectsToDecomp; if ((ki->kip1->flags & compClearMask) == ki->kip1->flags) @@ -318,70 +319,70 @@ int pkg2_decompress_kip(pkg2_kip1_info_t* ki, u32 sectsToDecomp) pkg2_kip1_t hdr; memcpy(&hdr, ki->kip1, sizeof(hdr)); - unsigned int newKipSize = sizeof(hdr); - for (u32 sectIdx = 0; sectIdx < KIP1_NUM_SECTIONS; sectIdx++) + u32 new_kip_size = sizeof(hdr); + for (u32 sect_idx = 0; sect_idx < KIP1_NUM_SECTIONS; sect_idx++) { - u32 sectCompBit = 1u << sectIdx; + u32 comp_bit_mask = BIT(sect_idx); // For compressed, cant get actual decompressed size without doing it, so use safe "output size". - if (sectIdx < 3 && (sectsToDecomp & sectCompBit) && (hdr.flags & sectCompBit)) - newKipSize += hdr.sections[sectIdx].size_decomp; + if (sect_idx < 3 && (sectsToDecomp & comp_bit_mask) && (hdr.flags & comp_bit_mask)) + new_kip_size += hdr.sections[sect_idx].size_decomp; else - newKipSize += hdr.sections[sectIdx].size_comp; + new_kip_size += hdr.sections[sect_idx].size_comp; } - pkg2_kip1_t* newKip = malloc(newKipSize); - unsigned char* dstDataPtr = newKip->data; - const unsigned char* srcDataPtr = ki->kip1->data; - for (u32 sectIdx = 0; sectIdx < KIP1_NUM_SECTIONS; sectIdx++) + pkg2_kip1_t *new_kip = malloc(new_kip_size); + u8 *dst_data = new_kip->data; + const u8 *src_data = ki->kip1->data; + for (u32 sect_idx = 0; sect_idx < KIP1_NUM_SECTIONS; sect_idx++) { - u32 sectCompBit = 1u << sectIdx; + u32 comp_bit_mask = BIT(sect_idx); // Easy copy path for uncompressed or ones we dont want to uncompress. - if (sectIdx >= 3 || !(sectsToDecomp & sectCompBit) || !(hdr.flags & sectCompBit)) + if (sect_idx >= 3 || !(sectsToDecomp & comp_bit_mask) || !(hdr.flags & comp_bit_mask)) { - unsigned int dataSize = hdr.sections[sectIdx].size_comp; + u32 dataSize = hdr.sections[sect_idx].size_comp; if (dataSize == 0) continue; - memcpy(dstDataPtr, srcDataPtr, dataSize); - srcDataPtr += dataSize; - dstDataPtr += dataSize; + memcpy(dst_data, src_data, dataSize); + src_data += dataSize; + dst_data += dataSize; continue; } - unsigned int compSize = hdr.sections[sectIdx].size_comp; - unsigned int outputSize = hdr.sections[sectIdx].size_decomp; - gfx_printf("Decomping %s KIP1 sect %d of size %d...\n", (const char*)hdr.name, sectIdx, compSize); - if (blz_uncompress_srcdest(srcDataPtr, compSize, dstDataPtr, outputSize) == 0) + u32 comp_size = hdr.sections[sect_idx].size_comp; + u32 output_size = hdr.sections[sect_idx].size_decomp; + gfx_printf("Decomping '%s', sect %d, size %d..\n", (char *)hdr.name, sect_idx, comp_size); + if (blz_uncompress_srcdest(src_data, comp_size, dst_data, output_size) == 0) { gfx_con.mute = false; - gfx_printf("%kERROR decomping sect %d of %s KIP!%k\n", 0xFFFF0000, sectIdx, (char*)hdr.name, 0xFFCCCCCC); - free(newKip); + gfx_printf("%kERROR decomping sect %d of '%s'!%k\n", TXT_CLR_ERROR, sect_idx, (char *)hdr.name, TXT_CLR_DEFAULT); + free(new_kip); return 1; } else { - DPRINTF("Done! Decompressed size is %d!\n", outputSize); + DPRINTF("Done! Decompressed size is %d!\n", output_size); } - hdr.sections[sectIdx].size_comp = outputSize; - srcDataPtr += compSize; - dstDataPtr += outputSize; + hdr.sections[sect_idx].size_comp = output_size; + src_data += comp_size; + dst_data += output_size; } hdr.flags &= compClearMask; - memcpy(newKip, &hdr, sizeof(hdr)); - newKipSize = dstDataPtr-(unsigned char*)(newKip); + memcpy(new_kip, &hdr, sizeof(hdr)); + new_kip_size = dst_data - (u8 *)(new_kip); free(ki->kip1); - ki->kip1 = newKip; - ki->size = newKipSize; + ki->kip1 = new_kip; + ki->size = new_kip_size; return 0; } -static int _kipm_inject(const char *kipm_path, char *target_name, pkg2_kip1_info_t* ki) +static int _kipm_inject(const char *kipm_path, char *target_name, pkg2_kip1_info_t *ki) { - if (!strcmp((const char *)ki->kip1->name, target_name)) + if (!strcmp((char *)ki->kip1->name, target_name)) { u32 size = 0; u8 *kipm_data = (u8 *)sd_file_read(kipm_path, &size); @@ -405,9 +406,9 @@ static int _kipm_inject(const char *kipm_path, char *target_name, pkg2_kip1_info u32 new_offset = 0; - for (u32 currSectIdx = 0; currSectIdx < KIP1_NUM_SECTIONS - 2; currSectIdx++) + for (u32 section_idx = 0; section_idx < KIP1_NUM_SECTIONS - 2; section_idx++) { - if(!currSectIdx) // .text. + if (!section_idx) // .text. { memcpy(ki->kip1->data + inject_size, fs_kip->data, fs_kip->sections[0].size_comp); ki->kip1->sections[0].size_decomp += inject_size; @@ -415,11 +416,11 @@ static int _kipm_inject(const char *kipm_path, char *target_name, pkg2_kip1_info } else // Others. { - if (currSectIdx < 3) - memcpy(ki->kip1->data + new_offset + inject_size, fs_kip->data + new_offset, fs_kip->sections[currSectIdx].size_comp); - ki->kip1->sections[currSectIdx].offset += inject_size; + if (section_idx < 3) + memcpy(ki->kip1->data + new_offset + inject_size, fs_kip->data + new_offset, fs_kip->sections[section_idx].size_comp); + ki->kip1->sections[section_idx].offset += inject_size; } - new_offset += fs_kip->sections[currSectIdx].size_comp; + new_offset += fs_kip->sections[section_idx].size_comp; } // Patch PMC capabilities for 1.0.0. @@ -442,32 +443,28 @@ static int _kipm_inject(const char *kipm_path, char *target_name, pkg2_kip1_info return 1; } -static bool ext_patches_parsed = false; - -const char* pkg2_patch_kips(link_t *info, char* patchNames) +const char *pkg2_patch_kips(link_t *info, char *patch_names) { - if (patchNames == NULL || patchNames[0] == 0) + bool emummc_patch_selected = false; + + if (patch_names == NULL || patch_names[0] == 0) return NULL; - if (!ext_patches_parsed) - { - parse_external_kip_patches(); - ext_patches_parsed = true; - } + gfx_printf("%kPatching kips%k\n", TXT_CLR_ORANGE, TXT_CLR_DEFAULT); static const u32 MAX_NUM_PATCHES_REQUESTED = sizeof(u32) * 8; - char* patches[MAX_NUM_PATCHES_REQUESTED]; + char *patches[MAX_NUM_PATCHES_REQUESTED]; - u32 numPatches = 1; - patches[0] = patchNames; + u32 patches_num = 1; + patches[0] = patch_names; { - for (char* p = patchNames; *p != 0; p++) + for (char *p = patch_names; *p != 0; p++) { if (*p == ',') { *p = 0; - patches[numPatches++] = p + 1; - if (numPatches >= MAX_NUM_PATCHES_REQUESTED) + patches[patches_num++] = p + 1; + if (patches_num >= MAX_NUM_PATCHES_REQUESTED) return "too_many_patches"; } else if (*p >= 'A' && *p <= 'Z') // Convert to lowercase. @@ -475,201 +472,224 @@ const char* pkg2_patch_kips(link_t *info, char* patchNames) } } - u32 patchesApplied = 0; // Bitset over patches. - for (u32 i = 0; i < numPatches; i++) + u32 patches_applied = 0; // Bitset over patches. + for (u32 i = 0; i < patches_num; i++) { // Eliminate leading spaces. - for (const char* p = patches[i]; *p != 0; p++) + for (const char *p = patches[i]; *p != 0; p++) { if (*p == ' ' || *p == '\t' || *p == '\r' || *p == '\n') patches[i]++; else break; } - int valueLen = strlen(patches[i]); - if (valueLen == 0) + + int patch_len = strlen(patches[i]); + if (patch_len == 0) continue; // Eliminate trailing spaces. - for (int chIdx = valueLen - 1; chIdx >= 0; chIdx--) + for (int chIdx = patch_len - 1; chIdx >= 0; chIdx--) { - const char* p = patches[i] + chIdx; + const char *p = patches[i] + chIdx; if (*p == ' ' || *p == '\t' || *p == '\r' || *p == '\n') - valueLen = chIdx; + patch_len = chIdx; else break; } - patches[i][valueLen] = 0; + patches[i][patch_len] = 0; DPRINTF("Requested patch: '%s'\n", patches[i]); } - u32 shaBuf[32 / sizeof(u32)]; + // Parse external patches if needed. + for (u32 i = 0; i < patches_num; i++) + { + if (!strcmp(patches[i], "emummc")) + { + // emuMMC patch is managed on its own. + emummc_patch_selected = true; + patches_applied |= BIT(i); + continue; + } + + if (strcmp(patches[i], "nogc")) + parse_external_kip_patches(); + } + + u32 kip_hash[SE_SHA_256_SIZE / sizeof(u32)]; LIST_FOREACH_ENTRY(pkg2_kip1_info_t, ki, info, link) { - shaBuf[0] = 0; // sha256 for this kip not yet calculated. - for (u32 currKipIdx = 0; currKipIdx < _kip_id_sets_cnt; currKipIdx++) + // Reset hash so it can be calculated for the new kip. + kip_hash[0] = 0; + + bool emummc_patch_apply = emummc_patch_selected && !strcmp((char *)ki->kip1->name, "FS"); + + // Check all SHA256 ID sets. (IDs are grouped per KIP. IDs are still unique.) + for (u32 kip_id_idx = 0; kip_id_idx < _kip_id_sets_cnt; kip_id_idx++) { - if (strncmp((const char*)ki->kip1->name, _kip_id_sets[currKipIdx].name, sizeof(ki->kip1->name)) != 0) + // Check if KIP name macthes ID's KIP name. + if (strcmp((char *)ki->kip1->name, _kip_id_sets[kip_id_idx].name) != 0) continue; - u32 bitsAffected = 0; - kip1_patchset_t* currPatchset = _kip_id_sets[currKipIdx].patchset; - while (currPatchset != NULL && currPatchset->name != NULL) + // Check if there are patches to apply. + bool patches_found = false; + const kip1_patchset_t *patchset = _kip_id_sets[kip_id_idx].patchset; + while (patchset != NULL && patchset->name != NULL && !patches_found) { - for (u32 i = 0; i < numPatches; i++) + for (u32 i = 0; i < patches_num; i++) { // Continue if patch name does not match. - if (strcmp(currPatchset->name, patches[i]) != 0) + if (strcmp(patchset->name, patches[i]) != 0) continue; - bitsAffected = i + 1; + patches_found = true; break; } - currPatchset++; + patchset++; } - // Dont bother even hashing this KIP if we dont have any patches enabled for it. - if (bitsAffected == 0) + // Don't bother hashing this KIP if no patches are enabled for it. + if (!patches_found && !emummc_patch_apply) continue; - if (shaBuf[0] == 0) - { - if (!se_calc_sha256_oneshot(shaBuf, ki->kip1, ki->size)) - memset(shaBuf, 0, sizeof(shaBuf)); - } + // Check if current KIP not hashed and hash it. + if (kip_hash[0] == 0) + if (!se_calc_sha256_oneshot(kip_hash, ki->kip1, ki->size)) + memset(kip_hash, 0, sizeof(kip_hash)); - if (memcmp(shaBuf, _kip_id_sets[currKipIdx].hash, sizeof(_kip_id_sets[0].hash)) != 0) + // Check if kip is the expected version. + if (memcmp(kip_hash, _kip_id_sets[kip_id_idx].hash, sizeof(_kip_id_sets[0].hash)) != 0) continue; - // Find out which sections are affected by the enabled patches, to know which to decompress. - bitsAffected = 0; - currPatchset = _kip_id_sets[currKipIdx].patchset; - while (currPatchset != NULL && currPatchset->name != NULL) + // Find out which sections are affected by the enabled patches, in order to decompress them. + u32 sections_affected = 0; + patchset = _kip_id_sets[kip_id_idx].patchset; + while (patchset != NULL && patchset->name != NULL) { - if (currPatchset->patches != NULL) + if (patchset->patches != NULL) { - for (u32 currEnabIdx = 0; currEnabIdx < numPatches; currEnabIdx++) + for (u32 patch_idx = 0; patch_idx < patches_num; patch_idx++) { - if (strcmp(currPatchset->name, patches[currEnabIdx])) + if (strcmp(patchset->name, patches[patch_idx])) continue; - if (!strcmp(currPatchset->name, "emummc")) - bitsAffected |= 1u << GET_KIP_PATCH_SECTION(currPatchset->patches->offset); - - for (const kip1_patch_t* currPatch=currPatchset->patches; currPatch != NULL && (currPatch->length != 0); currPatch++) - bitsAffected |= 1u << GET_KIP_PATCH_SECTION(currPatch->offset); + for (const kip1_patch_t *patch = patchset->patches; patch != NULL && (patch->length != 0); patch++) + sections_affected |= BIT(GET_KIP_PATCH_SECTION(patch->offset)); } } - currPatchset++; + patchset++; } + // If emuMMC is enabled, set its affected section. + if (emummc_patch_apply) + sections_affected |= BIT(KIP_TEXT); + // Got patches to apply to this kip, have to decompress it. -#ifdef DEBUG_PRINTING - u32 preDecompTime = get_tmr_us(); -#endif - if (pkg2_decompress_kip(ki, bitsAffected)) - return (const char*)ki->kip1->name; // Failed to decompress. + if (_decompress_kip(ki, sections_affected)) + return (char *)ki->kip1->name; // Failed to decompress. -#ifdef DEBUG_PRINTING - u32 postDecompTime = get_tmr_us(); - if (!se_calc_sha256_oneshot(shaBuf, ki->kip1, ki->size)) - memset(shaBuf, 0, sizeof(shaBuf)); - - DPRINTF("%dms %s KIP1 size %d hash %08X\n", (postDecompTime-preDecompTime) / 1000, ki->kip1->name, (int)ki->size, __builtin_bswap32(shaBuf[0])); -#endif - - currPatchset = _kip_id_sets[currKipIdx].patchset; - bool emummc_patch_selected = false; - while (currPatchset != NULL && currPatchset->name != NULL) + // Apply all patches for matched ID. + patchset = _kip_id_sets[kip_id_idx].patchset; + while (patchset != NULL && patchset->name != NULL) { - for (u32 currEnabIdx = 0; currEnabIdx < numPatches; currEnabIdx++) + for (u32 patch_idx = 0; patch_idx < patches_num; patch_idx++) { - if (strcmp(currPatchset->name, patches[currEnabIdx])) + // Check if patchset name matches requested patch. + if (strcmp(patchset->name, patches[patch_idx])) continue; - u32 appliedMask = 1u << currEnabIdx; + u32 applied_mask = BIT(patch_idx); - if (!strcmp(currPatchset->name, "emummc")) + // Check if patchset is empty. + if (patchset->patches == NULL) { - emummc_patch_selected = true; - patchesApplied |= appliedMask; - - continue; // Patching is done later. - } - - if (currPatchset->patches == NULL) - { - DPRINTF("Patch '%s' not necessary for %s KIP1\n", currPatchset->name, (const char*)ki->kip1->name); - patchesApplied |= appliedMask; + DPRINTF("Patch '%s' not necessary for %s\n", patchset->name, (char *)ki->kip1->name); + patches_applied |= applied_mask; continue; // Continue in case it's double defined. } - unsigned char* kipSectData = ki->kip1->data; - for (u32 currSectIdx = 0; currSectIdx < KIP1_NUM_SECTIONS; currSectIdx++) + // Apply patches per section. + u8 *kip_sect_data = ki->kip1->data; + for (u32 section_idx = 0; section_idx < KIP1_NUM_SECTIONS; section_idx++) { - if (bitsAffected & (1u << currSectIdx)) + if (sections_affected & BIT(section_idx)) { - gfx_printf("Applying patch '%s' on %s KIP1 sect %d\n", currPatchset->name, (const char*)ki->kip1->name, currSectIdx); - for (const kip1_patch_t* currPatch = currPatchset->patches; currPatch != NULL && currPatch->srcData != 0; currPatch++) + gfx_printf("Applying '%s' on %s, sect %d\n", patchset->name, (char *)ki->kip1->name, section_idx); + for (const kip1_patch_t *patch = patchset->patches; patch != NULL && patch->src_data != NULL; patch++) { - if (GET_KIP_PATCH_SECTION(currPatch->offset) != currSectIdx) + // Check if patch is in current section. + if (GET_KIP_PATCH_SECTION(patch->offset) != section_idx) continue; - if (!currPatch->length) + // Check if patch is empty. + if (!patch->length) { gfx_con.mute = false; - gfx_printf("%kPatch is empty!%k\n", 0xFFFF0000, 0xFFCCCCCC); - return currPatchset->name; // MUST stop here as it's not probably intended. + gfx_printf("%kPatch empty!%k\n", TXT_CLR_ERROR, TXT_CLR_DEFAULT); + return patchset->name; // MUST stop here as it's not probably intended. } - u32 currOffset = GET_KIP_PATCH_OFFSET(currPatch->offset); // If source does not match and is not already patched, throw an error. - if ((memcmp(&kipSectData[currOffset], currPatch->srcData, currPatch->length) != 0) && - (memcmp(&kipSectData[currOffset], currPatch->dstData, currPatch->length) != 0)) + u32 patch_offset = GET_KIP_PATCH_OFFSET(patch->offset); + if (patch->src_data != KIP1_PATCH_SRC_NO_CHECK && + (memcmp(&kip_sect_data[patch_offset], patch->src_data, patch->length) != 0) && + (memcmp(&kip_sect_data[patch_offset], patch->dst_data, patch->length) != 0)) { gfx_con.mute = false; - gfx_printf("%kPatch data mismatch at 0x%x!%k\n", 0xFFFF0000, currOffset, 0xFFCCCCCC); - return currPatchset->name; // MUST stop here as kip is likely corrupt. + gfx_printf("%kPatch mismatch at 0x%x!%k\n", TXT_CLR_ERROR, patch_offset, TXT_CLR_DEFAULT); + return patchset->name; // MUST stop here as kip is likely corrupt. } else { - DPRINTF("Patching %d bytes at offset 0x%x\n", currPatch->length, currOffset); - memcpy(&kipSectData[currOffset], currPatch->dstData, currPatch->length); + DPRINTF("Patching %d bytes at offset 0x%x\n", patch->length, patch_offset); + memcpy(&kip_sect_data[patch_offset], patch->dst_data, patch->length); } } } - kipSectData += ki->kip1->sections[currSectIdx].size_comp; + kip_sect_data += ki->kip1->sections[section_idx].size_comp; } - patchesApplied |= appliedMask; - continue; // Continue in case it's double defined. + patches_applied |= applied_mask; } - currPatchset++; + + patchset++; } - if (emummc_patch_selected && !strncmp(_kip_id_sets[currKipIdx].name, "FS", sizeof(ki->kip1->name))) + + // emuMMC must be applied after all other patches, since it affects TEXT offset. + if (emummc_patch_apply) { - emummc_patch_selected = false; - emu_cfg.fs_ver = currKipIdx; - if (currKipIdx) + // Encode ID. + emu_cfg.fs_ver = kip_id_idx; + if (kip_id_idx) emu_cfg.fs_ver--; - if (currKipIdx > 17) + if (kip_id_idx > 17) emu_cfg.fs_ver -= 2; + // Inject emuMMC code. gfx_printf("Injecting emuMMC. FS ID: %d\n", emu_cfg.fs_ver); - if (_kipm_inject("/bootloader/sys/emummc.kipm", "FS", ki)) + if (_kipm_inject("bootloader/sys/emummc.kipm", "FS", ki)) return "emummc"; + + // Skip checking again. + emummc_patch_selected = false; + emummc_patch_apply = false; } } } - for (u32 i = 0; i < numPatches; i++) + // Check if all patches were applied. + for (u32 i = 0; i < patches_num; i++) { - if ((patchesApplied & (1u << i)) == 0) + if ((patches_applied & BIT(i)) == 0) return patches[i]; } + // Check if emuMMC was applied. + if (emummc_patch_selected) + return "emummc"; + return NULL; } @@ -694,7 +714,7 @@ pkg2_hdr_t *pkg2_decrypt(void *data, u8 kb, bool is_exo) pkg2_keyslot = 8; // Decrypt 7.0.0 pkg2 via 8.1.0 mkey on Erista. - if (!h_cfg.t210b01 && kb == KB_FIRMWARE_VERSION_700) + if (!h_cfg.t210b01 && kb == HOS_KB_VERSION_700) { u8 tmp_mkey[SE_KEY_128_SIZE]; @@ -710,11 +730,11 @@ pkg2_hdr_t *pkg2_decrypt(void *data, u8 kb, bool is_exo) // Decrypt header. se_aes_crypt_ctr(pkg2_keyslot, hdr, sizeof(pkg2_hdr_t), hdr, sizeof(pkg2_hdr_t), hdr); - //gfx_hexdump((u32)hdr, hdr, 0x100); if (hdr->magic != PKG2_MAGIC) return NULL; + // Decrypt sections. for (u32 i = 0; i < 4; i++) { DPRINTF("sec %d has size %08X\n", i, hdr->sec_size[i]); @@ -722,7 +742,6 @@ DPRINTF("sec %d has size %08X\n", i, hdr->sec_size[i]); continue; se_aes_crypt_ctr(pkg2_keyslot, pdata, hdr->sec_size[i], pdata, hdr->sec_size[i], &hdr->sec_ctr[i * SE_AES_IV_SIZE]); - //gfx_hexdump((u32)pdata, pdata, 0x100); pdata += hdr->sec_size[i]; } @@ -730,29 +749,38 @@ DPRINTF("sec %d has size %08X\n", i, hdr->sec_size[i]); return hdr; } -static u32 _pkg2_ini1_build(u8 *pdst, pkg2_hdr_t *hdr, link_t *kips_info, bool new_pkg2) +static u32 _pkg2_ini1_build(u8 *pdst, u8 *psec, pkg2_hdr_t *hdr, link_t *kips_info, bool new_pkg2) { + // Calculate INI1 size. u32 ini1_size = sizeof(pkg2_ini1_t); - pkg2_ini1_t *ini1 = (pkg2_ini1_t *)pdst; - - // Set initial header and magic. - memset(ini1, 0, sizeof(pkg2_ini1_t)); - ini1->magic = INI1_MAGIC; - pdst += sizeof(pkg2_ini1_t); - - // Merge kips into INI1. LIST_FOREACH_ENTRY(pkg2_kip1_info_t, ki, kips_info, link) { -DPRINTF("adding kip1 '%s' @ %08X (%08X)\n", ki->kip1->name, (u32)ki->kip1, ki->size); - memcpy(pdst, ki->kip1, ki->size); - pdst += ki->size; ini1_size += ki->size; - ini1->num_procs++; } // Align size and set it. ini1_size = ALIGN(ini1_size, 4); - ini1->size = ini1_size; + + // For new kernel if INI1 fits in the old one, use it. + bool use_old_ini_region = psec && ini1_size <= (pkg2_newkern_ini1_end - pkg2_newkern_ini1_start); + if (use_old_ini_region) + pdst = psec + pkg2_newkern_ini1_start; + + // Set initial header and magic. + pkg2_ini1_t *ini1 = (pkg2_ini1_t *)pdst; + memset(ini1, 0, sizeof(pkg2_ini1_t)); + ini1->magic = INI1_MAGIC; + ini1->size = ini1_size; + pdst += sizeof(pkg2_ini1_t); + + // Merge KIPs into INI1. + LIST_FOREACH_ENTRY(pkg2_kip1_info_t, ki, kips_info, link) + { +DPRINTF("adding kip1 '%s' @ %08X (%08X)\n", (char *)ki->kip1->name, (u32)ki->kip1, ki->size); + memcpy(pdst, ki->kip1, ki->size); + pdst += ki->size; + ini1->num_procs++; + } // Encrypt INI1 in its own section if old pkg2. Otherwise it gets embedded into Kernel. if (!new_pkg2) @@ -767,18 +795,19 @@ DPRINTF("adding kip1 '%s' @ %08X (%08X)\n", ki->kip1->name, (u32)ki->kip1, ki->s hdr->sec_off[PKG2_SEC_INI1] = 0; } - return ini1_size; + return !use_old_ini_region ? ini1_size : 0; } -void pkg2_build_encrypt(void *dst, void *hos_ctxt, link_t *kips_info) +void pkg2_build_encrypt(void *dst, void *hos_ctxt, link_t *kips_info, bool is_exo) { - u8 *pdst = (u8 *)dst; - launch_ctxt_t * ctxt = (launch_ctxt_t *)hos_ctxt; + launch_ctxt_t *ctxt = (launch_ctxt_t *)hos_ctxt; + u32 meso_magic = *(u32 *)(ctxt->kernel + 4); u32 kernel_size = ctxt->kernel_size; - bool is_meso = *(u32 *)(ctxt->kernel + 4) == ATM_MESOSPHERE; u8 kb = ctxt->pkg1_id->kb; + u8 *pdst = (u8 *)dst; // Force new Package2 if Mesosphere. + bool is_meso = (meso_magic & 0xF0FFFFFF) == ATM_MESOSPHERE; if (is_meso) ctxt->new_pkg2 = true; @@ -786,7 +815,7 @@ void pkg2_build_encrypt(void *dst, void *hos_ctxt, link_t *kips_info) u8 key_ver = kb ? kb + 1 : 0; if (pkg2_keyslot == 9) { - key_ver = KB_FIRMWARE_VERSION_810 + 1; + key_ver = HOS_KB_VERSION_810 + 1; pkg2_keyslot = 8; } @@ -817,12 +846,23 @@ DPRINTF("%s @ %08X (%08X)\n", is_meso ? "Mesosphere": "kernel",(u32)ctxt->kernel hdr->sec_off[PKG2_SEC_KERNEL] = 0x10000000; else { - // Set new INI1 offset to kernel. - *(u32 *)(pdst + (is_meso ? 8 : pkg2_newkern_ini1_val)) = kernel_size; - // Build INI1 for new Package2. - kernel_size += _pkg2_ini1_build(pdst + kernel_size, hdr, kips_info, ctxt->new_pkg2); + u32 ini1_size = _pkg2_ini1_build(pdst + kernel_size, is_meso ? NULL : pdst, hdr, kips_info, true); hdr->sec_off[PKG2_SEC_KERNEL] = 0x60000; + + // Set new INI1 offset to kernel. + u32 meso_meta_offset = *(u32 *)(pdst + 8); + if (is_meso && (meso_magic & 0x0F000000)) // MSS1. + *(u32 *)(pdst + meso_meta_offset) = kernel_size - meso_meta_offset; + else if (ini1_size) + { + if (is_meso) // MSS0. + *(u32 *)(pdst + 8) = kernel_size; + else + *(u32 *)(pdst + pkg2_newkern_ini1_info) = kernel_size - pkg2_newkern_ini1_rela; + } + + kernel_size += ini1_size; } hdr->sec_size[PKG2_SEC_KERNEL] = kernel_size; se_aes_crypt_ctr(pkg2_keyslot, pdst, kernel_size, pdst, kernel_size, &hdr->sec_ctr[PKG2_SEC_KERNEL * SE_AES_IV_SIZE]); @@ -832,16 +872,19 @@ DPRINTF("kernel encrypted\n"); // Build INI1 for old Package2. u32 ini1_size = 0; if (!ctxt->new_pkg2) - ini1_size = _pkg2_ini1_build(pdst, hdr, kips_info, false); + ini1_size = _pkg2_ini1_build(pdst, NULL, hdr, kips_info, false); DPRINTF("INI1 encrypted\n"); - // Calculate SHA256 over encrypted Kernel and INI1. - u8 *pk2_hash_data = (u8 *)dst + 0x100 + sizeof(pkg2_hdr_t); - se_calc_sha256_oneshot(&hdr->sec_sha256[0x20 * PKG2_SEC_KERNEL], - (void *)pk2_hash_data, hdr->sec_size[PKG2_SEC_KERNEL]); - pk2_hash_data += hdr->sec_size[PKG2_SEC_KERNEL]; - se_calc_sha256_oneshot(&hdr->sec_sha256[0x20 * PKG2_SEC_INI1], - (void *)pk2_hash_data, hdr->sec_size[PKG2_SEC_INI1]); + if (!is_exo) // Not needed on Exosphere 1.0.0 and up. + { + // Calculate SHA256 over encrypted sections. Only 3 have valid hashes. + u8 *pk2_hash_data = (u8 *)dst + 0x100 + sizeof(pkg2_hdr_t); + for (u32 i = PKG2_SEC_KERNEL; i <= PKG2_SEC_UNUSED; i++) + { + se_calc_sha256_oneshot(&hdr->sec_sha256[SE_SHA_256_SIZE * i], (void *)pk2_hash_data, hdr->sec_size[i]); + pk2_hash_data += hdr->sec_size[i]; + } + } // Encrypt header. *(u32 *)hdr->ctr = 0x100 + sizeof(pkg2_hdr_t) + kernel_size + ini1_size; diff --git a/bootloader/hos/pkg2.h b/bootloader/hos/pkg2.h index 8a63a86..551e46e 100644 --- a/bootloader/hos/pkg2.h +++ b/bootloader/hos/pkg2.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 CTCaer + * Copyright (c) 2018-2025 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,34 +18,37 @@ #ifndef _PKG2_H_ #define _PKG2_H_ -#include -#include +#include -#define PKG2_MAGIC 0x31324B50 -#define PKG2_SEC_BASE 0x80000000 +#define PKG2_MAGIC 0x31324B50 +#define PKG2_SEC_BASE 0x80000000 #define PKG2_SEC_KERNEL 0 -#define PKG2_SEC_INI1 1 +#define PKG2_SEC_INI1 1 +#define PKG2_SEC_UNUSED 2 #define INI1_MAGIC 0x31494E49 -#define PKG2_NEWKERN_GET_INI1_HEURISTIC 0xD2800015 // Offset of OP + 12 is the INI1 offset. + +//! TODO: Update on kernel change if needed. +// Offset of OP + 12 is the INI1 offset. On v2 with dynamic crt0 it's + 16. +#define PKG2_NEWKERN_GET_INI1_HEURISTIC 0xD2800015 // MOV X21, #0. #define PKG2_NEWKERN_START 0x800 #define ATM_MESOSPHERE 0x3053534D -extern u32 pkg2_newkern_ini1_val; +extern u32 pkg2_newkern_ini1_info; extern u32 pkg2_newkern_ini1_start; extern u32 pkg2_newkern_ini1_end; typedef struct _kernel_patch_t { - u32 id; - u32 off; - u32 val; - u32 *ptr; + u32 id; + u32 off; + u32 val; + const u32 *ptr; } kernel_patch_t; #define KERNEL_PATCHSET_DEF(name, ...) \ - kernel_patch_t name[] = { \ + static const kernel_patch_t name[] = { \ __VA_ARGS__, \ {0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, (u32 *)0xFFFFFFFF} \ } @@ -65,18 +68,18 @@ enum typedef struct _pkg2_hdr_t { - u8 ctr[0x10]; - u8 sec_ctr[0x40]; - u32 magic; - u32 base; - u32 pad0; - u8 pkg2_ver; - u8 bl_ver; - u16 pad1; - u32 sec_size[4]; - u32 sec_off[4]; - u8 sec_sha256[0x80]; - u8 data[]; +/* 0x000 */ u8 ctr[0x10]; +/* 0x010 */ u8 sec_ctr[0x40]; +/* 0x050 */ u32 magic; +/* 0x054 */ u32 base; +/* 0x058 */ u32 pad0; +/* 0x05C */ u8 pkg2_ver; +/* 0x05D */ u8 bl_ver; +/* 0x05E */ u16 pad1; +/* 0x060 */ u32 sec_size[4]; +/* 0x070 */ u32 sec_off[4]; +/* 0x080 */ u8 sec_sha256[0x80]; +/* 0x100 */ u8 data[]; } pkg2_hdr_t; typedef struct _pkg2_ini1_t @@ -99,17 +102,17 @@ typedef struct _pkg2_kip1_sec_t typedef struct _pkg2_kip1_t { - u32 magic; - u8 name[12]; - u64 tid; - u32 proc_cat; - u8 main_thrd_prio; - u8 def_cpu_core; - u8 res; - u8 flags; - pkg2_kip1_sec_t sections[KIP1_NUM_SECTIONS]; - u32 caps[0x20]; - u8 data[]; +/* 0x000 */ u32 magic; +/* 0x004 */ u8 name[12]; +/* 0x010 */ u64 tid; +/* 0x018 */ u32 proc_cat; +/* 0x01C */ u8 main_thrd_prio; +/* 0x01D */ u8 def_cpu_core; +/* 0x01E */ u8 res; +/* 0x01F */ u8 flags; +/* 0x020 */ pkg2_kip1_sec_t sections[KIP1_NUM_SECTIONS]; +/* 0x080 */ u32 caps[0x20]; +/* 0x100 */ u8 data[]; } pkg2_kip1_t; typedef struct _pkg2_kip1_info_t @@ -122,41 +125,42 @@ typedef struct _pkg2_kip1_info_t typedef struct _pkg2_kernel_id_t { u8 hash[8]; - kernel_patch_t *kernel_patchset; + const kernel_patch_t *kernel_patchset; } pkg2_kernel_id_t; +#define KIP1_PATCH_SRC_NO_CHECK (char *)(-1) + typedef struct _kip1_patch_t { - u32 offset; // section+offset of patch to apply. - u32 length; // In bytes, 0 means last patch. - char* srcData; // That must match. - char* dstData; // That it gets replaced by. + u32 offset; // section+offset of patch to apply. + u32 length; // In bytes, 0 means last patch. + char *src_data; // That must match. + char *dst_data; // That it gets replaced by. } kip1_patch_t; typedef struct _kip1_patchset_t { - char* name; // NULL means end. - kip1_patch_t* patches; // NULL means not necessary. + char *name; // NULL means end. + const kip1_patch_t *patches; // NULL means not necessary. } kip1_patchset_t; typedef struct _kip1_id_t { - const char* name; + const char *name; u8 hash[8]; - kip1_patchset_t* patchset; + const kip1_patchset_t *patchset; } kip1_id_t; -void pkg2_get_newkern_info(u8 *kern_data); bool pkg2_parse_kips(link_t *info, pkg2_hdr_t *pkg2, bool *new_pkg2); int pkg2_has_kip(link_t *info, u64 tid); void pkg2_replace_kip(link_t *info, u64 tid, pkg2_kip1_t *kip1); void pkg2_add_kip(link_t *info, pkg2_kip1_t *kip1); void pkg2_merge_kip(link_t *info, pkg2_kip1_t *kip1); void pkg2_get_ids(kip1_id_t **ids, u32 *entries); -const char* pkg2_patch_kips(link_t *info, char* patchNames); +const char *pkg2_patch_kips(link_t *info, char *patch_names); -const pkg2_kernel_id_t *pkg2_identify(u8 *hash); +const pkg2_kernel_id_t *pkg2_identify(const u8 *hash); pkg2_hdr_t *pkg2_decrypt(void *data, u8 kb, bool is_exo); -void pkg2_build_encrypt(void *dst, void *hos_ctxt, link_t *kips_info); +void pkg2_build_encrypt(void *dst, void *hos_ctxt, link_t *kips_info, bool is_exo); #endif diff --git a/bootloader/hos/pkg2_ini_kippatch.c b/bootloader/hos/pkg2_ini_kippatch.c index 4caf31d..9567eef 100644 --- a/bootloader/hos/pkg2_ini_kippatch.c +++ b/bootloader/hos/pkg2_ini_kippatch.c @@ -1,18 +1,35 @@ +/* + * Copyright (c) 2019-2024 CTCaer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + #include #include +#include + #include "pkg2_ini_kippatch.h" #include -#include #define KPS(x) ((u32)(x) << 29) -static u8 *_htoa(u8 *result, const char *ptr, u8 byte_len) +static u8 *_htoa(u8 *result, const char *ptr, u8 byte_len, u8 *buf) { char ch = *ptr; u32 ascii_len = byte_len * 2; if (!result) - result = malloc(byte_len); + result = buf; u8 *dst = result; while (ch == ' ' || ch == '\t') @@ -45,24 +62,11 @@ static u8 *_htoa(u8 *result, const char *ptr, u8 byte_len) return result; } -static char *_strdup(char *str) -{ - if (!str) - return NULL; - if (str[0] == ' ' && (strlen(str) > 1)) - str++; - char *res = (char *)malloc(strlen(str) + 1); - strcpy(res, str); - if (res[strlen(res) - 1] == ' ' && (strlen(res) > 1)) - res[strlen(res) - 1] = 0; - - return res; -} - static u32 _find_patch_section_name(char *lbuf, u32 lblen, char schar) { u32 i; - for (i = 0; i < lblen && lbuf[i] != schar && lbuf[i] != '\n' && lbuf[i] != '\r'; i++) + // Depends on 'FF_USE_STRFUNC 2' that removes \r. + for (i = 0; i < lblen && lbuf[i] != schar && lbuf[i] != '\n'; i++) ; lbuf[i] = 0; @@ -74,27 +78,36 @@ static ini_kip_sec_t *_ini_create_kip_section(link_t *dst, ini_kip_sec_t *ksec, if (ksec) list_append(dst, &ksec->link); - ksec = (ini_kip_sec_t *)calloc(sizeof(ini_kip_sec_t), 1); - u32 i = _find_patch_section_name(name, strlen(name), ':') + 1; - ksec->name = _strdup(name); + // Calculate total allocation size. + u32 len = strlen(name); + char *buf = zalloc(sizeof(ini_kip_sec_t) + len + 1); + + ksec = (ini_kip_sec_t *)buf; + u32 i = _find_patch_section_name(name, len, ':') + 1; + ksec->name = strcpy_ns(buf + sizeof(ini_kip_sec_t), name); // Get hash section. - _htoa(ksec->hash, &name[i], 8); + _htoa(ksec->hash, &name[i], 8, NULL); + + // Initialize list. + list_init(&ksec->pts); return ksec; } -int ini_patch_parse(link_t *dst, char *ini_path) +int ini_patch_parse(link_t *dst, const char *ini_path) { FIL fp; u32 lblen; - char lbuf[512]; + char *lbuf; ini_kip_sec_t *ksec = NULL; // Open ini. if (f_open(&fp, ini_path, FA_READ) != FR_OK) return 0; + lbuf = malloc(512); + do { // Fetch one line. @@ -110,37 +123,46 @@ int ini_patch_parse(link_t *dst, char *ini_path) { _find_patch_section_name(lbuf, lblen, ']'); + // Set patchset kip name and hash. ksec = _ini_create_kip_section(dst, ksec, &lbuf[1]); - list_init(&ksec->pts); } - else if (ksec && lbuf[0] == '.') //Extract key/value. + else if (ksec && lbuf[0] == '.') // Extract key/value. { - u32 tmp = 0; - u32 i = _find_patch_section_name(lbuf, lblen, '='); + u32 str_start = 0; + u32 pos = _find_patch_section_name(lbuf, lblen, '='); - ini_patchset_t *pt = (ini_patchset_t *)calloc(sizeof(ini_patchset_t), 1); + // Calculate total allocation size. + char *buf = zalloc(sizeof(ini_patchset_t) + strlen(&lbuf[1]) + 1); + ini_patchset_t *pt = (ini_patchset_t *)buf; - pt->name = _strdup(&lbuf[1]); + // Set patch name. + pt->name = strcpy_ns(buf + sizeof(ini_patchset_t), &lbuf[1]); - u8 kip_sidx = lbuf[i + 1] - '0'; + u8 kip_sidx = lbuf[pos + 1] - '0'; + pos += 3; if (kip_sidx < 6) { + // Set patch offset. pt->offset = KPS(kip_sidx); - tmp = _find_patch_section_name(&lbuf[i + 3], lblen, ':'); - pt->offset |= strtol(&lbuf[i + 3], NULL, 16); + str_start = _find_patch_section_name(&lbuf[pos], lblen - pos, ':'); + pt->offset |= strtol(&lbuf[pos], NULL, 16); + pos += str_start + 1; - i += tmp + 4; + // Set patch size. + str_start = _find_patch_section_name(&lbuf[pos], lblen - pos, ':'); + pt->length = strtol(&lbuf[pos], NULL, 16); + pos += str_start + 1; - tmp = _find_patch_section_name(&lbuf[i], lblen, ':'); - pt->length = strtol(&lbuf[i], NULL, 16); + u8 *data = malloc(pt->length * 2); - i += tmp + 1; + // Set patch source data. + str_start = _find_patch_section_name(&lbuf[pos], lblen - pos, ','); + pt->src_data = _htoa(NULL, &lbuf[pos], pt->length, data); + pos += str_start + 1; - tmp = _find_patch_section_name(&lbuf[i], lblen, ','); - pt->srcData = _htoa(NULL, &lbuf[i], pt->length); - i += tmp + 1; - pt->dstData = _htoa(NULL, &lbuf[i], pt->length); + // Set patch destination data. + pt->dst_data = _htoa(NULL, &lbuf[pos], pt->length, data + pt->length); } list_append(&ksec->pts, &pt->link); @@ -152,5 +174,7 @@ int ini_patch_parse(link_t *dst, char *ini_path) if (ksec) list_append(dst, &ksec->link); + free(lbuf); + return 1; } diff --git a/bootloader/hos/pkg2_ini_kippatch.h b/bootloader/hos/pkg2_ini_kippatch.h index 039adaf..07881c1 100644 --- a/bootloader/hos/pkg2_ini_kippatch.h +++ b/bootloader/hos/pkg2_ini_kippatch.h @@ -17,16 +17,15 @@ #ifndef _INIPATCH_H_ #define _INIPATCH_H_ -#include -#include +#include typedef struct _ini_patchset_t { char *name; - u32 offset; // section + offset of patch to apply. - u32 length; // In bytes, 0 means last patch. - u8 *srcData; // That must match. - u8 *dstData; // Gets replaced with. + u32 offset; // section + offset of patch to apply. + u32 length; // In bytes, 0 means last patch. + u8 *src_data; // That must match. + u8 *dst_data; // Gets replaced with. link_t link; } ini_patchset_t; @@ -38,6 +37,6 @@ typedef struct _ini_kip_sec_t link_t link; } ini_kip_sec_t; -int ini_patch_parse(link_t *dst, char *ini_path); +int ini_patch_parse(link_t *dst, const char *ini_path); #endif diff --git a/bootloader/hos/pkg2_patches.inl b/bootloader/hos/pkg2_patches.inl index e4066d5..075df1b 100644 --- a/bootloader/hos/pkg2_patches.inl +++ b/bootloader/hos/pkg2_patches.inl @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2024 CTCaer * Copyright (c) 2018 Atmosphère-NX * * This program is free software; you can redistribute it and/or modify it @@ -63,37 +63,37 @@ #define ID_RCV_OFF_1101 0x22B28 #define ID_RCV_OFF_1200 0x23424 -static u32 PRC_ID_SND_100[] = +static const u32 PRC_ID_SND_100[] = { 0xA9BF2FEA, 0x2A0E03EB, 0xD37EF56B, 0xF86B6B8B, 0x92FFFFE9, 0x8A090168, 0xD2FFFFE9, 0x8A09016B, 0xD2FFFFC9, 0xEB09017F, 0x54000040, 0xF9412948, 0xA8C12FEA }; #define CODE_OFF_2ND_100 (CODE_OFF_1ST_100 + sizeof(PRC_ID_SND_100) + sizeof(u32)) -static u32 PRC_ID_RCV_100[] = +static const u32 PRC_ID_RCV_100[] = { 0xA9BF2FEA, 0x2A1C03EA, 0xD37EF54A, 0xF86A69AA, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000040, 0xF9412968, 0xA8C12FEA }; -static u32 PRC_ID_SND_200[] = +static const u32 PRC_ID_SND_200[] = { 0xA9BF2FEA, 0x2A1803EB, 0xD37EF56B, 0xF86B6B8B, 0x92FFFFE9, 0x8A090168, 0xD2FFFFE9, 0x8A09016B, 0xD2FFFFC9, 0xEB09017F, 0x54000040, 0xF9413148, 0xA8C12FEA }; #define CODE_OFF_2ND_200 (CODE_OFF_1ST_200 + sizeof(PRC_ID_SND_200) + sizeof(u32)) -static u32 PRC_ID_RCV_200[] = +static const u32 PRC_ID_RCV_200[] = { 0xA9BF2FEA, 0x2A0F03EA, 0xD37EF54A, 0xF9405FEB, 0xF86A696A, 0xF9407BEB, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000040, 0xF9413168, 0xA8C12FEA }; -static u32 PRC_ID_SND_300[] = +static const u32 PRC_ID_SND_300[] = { 0xA9BF2FEA, 0x2A1803EB, 0xD37EF56B, 0xF86B6B8B, 0x92FFFFE9, 0x8A090168, 0xD2FFFFE9, 0x8A09016B, 0xD2FFFFC9, 0xEB09017F, 0x54000040, 0xF9415548, 0xA8C12FEA }; #define CODE_OFF_2ND_300 (CODE_OFF_1ST_300 + sizeof(PRC_ID_SND_300) + sizeof(u32)) -static u32 PRC_ID_RCV_300[] = +static const u32 PRC_ID_RCV_300[] = { 0xA9BF2FEA, 0x2A0F03EA, 0xD37EF54A, 0xF9405FEB, 0xF86A696A, 0xF9407BEB, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000040, 0xF9415568, 0xA8C12FEA @@ -101,52 +101,52 @@ static u32 PRC_ID_RCV_300[] = #define CODE_OFF_2ND_302 (CODE_OFF_1ST_302 + sizeof(PRC_ID_SND_300) + sizeof(u32)) -static u32 PRC_ID_SND_400[] = +static const u32 PRC_ID_SND_400[] = { 0x2A1703EA, 0xD37EF54A, 0xF86A6B8A, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000060, 0xF94053EA, 0xF9415948, 0xF94053EA }; #define CODE_OFF_2ND_400 (CODE_OFF_1ST_400 + sizeof(PRC_ID_SND_400) + sizeof(u32)) -static u32 PRC_ID_RCV_400[] = +static const u32 PRC_ID_RCV_400[] = { 0xF9403BED, 0x2A0E03EA, 0xD37EF54A, 0xF86A69AA, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000040, 0xF9415B28, 0xD503201F }; -static u32 PRC_ID_SND_500[] = +static const u32 PRC_ID_SND_500[] = { 0x2A1703EA, 0xD37EF54A, 0xF86A6B6A, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000060, 0xF94043EA, 0xF9415948, 0xF94043EA }; #define CODE_OFF_2ND_500 (CODE_OFF_1ST_500 + sizeof(PRC_ID_SND_500) + sizeof(u32)) -static u32 PRC_ID_RCV_500[] = +static const u32 PRC_ID_RCV_500[] = { 0xF9403BED, 0x2A1503EA, 0xD37EF54A, 0xF86A69AA, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000040, 0xF9415B08, 0xF9406FEA }; -static u32 PRC_ID_SND_600[] = +static const u32 PRC_ID_SND_600[] = { 0xA9BF2FEA, 0xF94037EB, 0x2A1503EA, 0xD37EF54A, 0xF86A696A, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000100, 0xA9BF27E8, 0xF9400308, 0xF9401D08, 0xAA1803E0, 0xD63F0100, 0xA8C127E8, 0xAA0003E8, 0xA8C12FEA, 0xAA0803E0 }; #define CODE_OFF_2ND_600 (CODE_OFF_1ST_600 + sizeof(PRC_ID_SND_600) + sizeof(u32)) -static u32 PRC_ID_RCV_600[] = +static const u32 PRC_ID_RCV_600[] = { 0xA9BF2FEA, 0xF94043EB, 0x2A1503EA, 0xD37EF54A, 0xF86A696A, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000100, 0xA9BF27E8, 0xF9400308, 0xF9401D08, 0xAA1803E0, 0xD63F0100, 0xA8C127E8, 0xAA0003E8, 0xA8C12FEA, 0xAA0803E0 }; -static u32 PRC_ID_SND_700[] = +static const u32 PRC_ID_SND_700[] = { 0xA9BF2FEA, 0xF9403BEB, 0x2A1903EA, 0xD37EF54A, 0xF86A696A, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000100, 0xA9BF27E8, 0xF94002A8, 0xF9401D08, 0xAA1503E0, 0xD63F0100, 0xA8C127E8, 0xAA0003E8, 0xA8C12FEA, 0xAA0803E0 }; #define CODE_OFF_2ND_700 (CODE_OFF_1ST_700 + sizeof(PRC_ID_SND_700) + sizeof(u32)) -static u32 PRC_ID_RCV_700[] = +static const u32 PRC_ID_RCV_700[] = { 0xA9BF2FEA, 0xF9404FEB, 0x2A1603EA, 0xD37EF54A, 0xF86A696A, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000100, 0xA9BF27E8, 0xF9400368, 0xF9401D08, 0xAA1B03E0, @@ -155,56 +155,56 @@ static u32 PRC_ID_RCV_700[] = #define CODE_OFF_2ND_800 (CODE_OFF_1ST_800 + sizeof(PRC_ID_SND_700) + sizeof(u32)) -static u32 PRC_ID_SND_900[] = +static const u32 PRC_ID_SND_900[] = { 0xA9BF2FEA, 0xF94037EB, 0x2A1603EA, 0xD37EF54A, 0xF86A696A, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000100, 0xA9BF27E8, 0xF94002E8, 0xF9401D08, 0xAA1703E0, 0xD63F0100, 0xA8C127E8, 0xAA0003E8, 0xA8C12FEA, 0xAA0803E0 }; #define CODE_OFF_2ND_900 (CODE_OFF_1ST_900 + sizeof(PRC_ID_SND_900) + sizeof(u32)) -static u32 PRC_ID_RCV_900[] = +static const u32 PRC_ID_RCV_900[] = { 0xA9BF2FEA, 0xF9404BEB, 0x2A1703EA, 0xD37EF54A, 0xF86A696A, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000100, 0xA9BF27E8, 0xF9400368, 0xF9401D08, 0xAA1B03E0, 0xD63F0100, 0xA8C127E8, 0xAA0003E8, 0xA8C12FEA, 0xAA0803E0 }; -static u32 PRC_ID_SND_1000[] = +static const u32 PRC_ID_SND_1000[] = { 0xA9BF2FEA, 0xF94063EB, 0x2A1603EA, 0xD37EF54A, 0xF86A696A, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000100, 0xA9BF27E8, 0xF94002E8, 0xF9401D08, 0xAA1703E0, 0xD63F0100, 0xA8C127E8, 0xAA0003E8, 0xA8C12FEA, 0xAA0803E0 }; #define CODE_OFF_2ND_1000 (CODE_OFF_1ST_1000 + sizeof(PRC_ID_SND_1000) + sizeof(u32)) -static u32 PRC_ID_RCV_1000[] = +static const u32 PRC_ID_RCV_1000[] = { 0xA9BF2FEA, 0xF94067EB, 0x2A1A03EA, 0xD37EF54A, 0xF86A696A, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000100, 0xA9BF27E8, 0xF9400388, 0xF9401D08, 0xAA1C03E0, 0xD63F0100, 0xA8C127E8, 0xAA0003E8, 0xA8C12FEA, 0xAA0803E0 }; -static u32 PRC_ID_SND_1100[] = +static const u32 PRC_ID_SND_1100[] = { 0xA9BF2FEA, 0xF94043EB, 0x5280006A, 0xD37EF54A, 0xF86A696A, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000100, 0xA9BF27E8, 0xF94002A8, 0xF9401D08, 0xAA1503E0, 0xD63F0100, 0xA8C127E8, 0xAA0003E8, 0xA8C12FEA, 0xAA0803E0 }; #define CODE_OFF_2ND_1100 (CODE_OFF_1ST_1100 + sizeof(PRC_ID_SND_1100) + sizeof(u32)) -static u32 PRC_ID_RCV_1100[] = +static const u32 PRC_ID_RCV_1100[] = { 0xA9BF2FEA, 0xF94073EB, 0x5280006A, 0xD37EF54A, 0xF86A696A, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000100, 0xA9BF27E8, 0xF9400308, 0xF9401D08, 0xAA1803E0, 0xD63F0100, 0xA8C127E8, 0xAA0003E8, 0xA8C12FEA, 0xAA0803E0 }; -static u32 PRC_ID_SND_1200[] = +static const u32 PRC_ID_SND_1200[] = { 0xA9BF2FEA, 0xF9404FEB, 0x5280006A, 0xD37EF54A, 0xF86A696A, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000100, 0xA9BF27E8, 0xF94002C8, 0xF9401D08, 0xAA1603E0, 0xD63F0100, 0xA8C127E8, 0xAA0003E8, 0xA8C12FEA, 0xAA0803E0 }; #define CODE_OFF_2ND_1200 (CODE_OFF_1ST_1200 + sizeof(PRC_ID_SND_1200) + sizeof(u32)) -static u32 PRC_ID_RCV_1200[] = +static const u32 PRC_ID_RCV_1200[] = { 0xA9BF2FEA, 0xF94073EB, 0x5280006A, 0xD37EF54A, 0xF86A696A, 0x92FFFFE9, 0x8A090148, 0xD2FFFFE9, 0x8A09014A, 0xD2FFFFC9, 0xEB09015F, 0x54000100, 0xA9BF27E8, 0xF9400388, 0xF9401D08, 0xAA1C03E0, @@ -448,316 +448,467 @@ static const pkg2_kernel_id_t _pkg2_kernel_ids[] = }; // All kip patch offsets are without the 0x100-sized header. -static kip1_patch_t _fs_emummc[] = -{ - { KPS(KIP_TEXT) | 1, 0, "", "" }, - { 0, 0, NULL, NULL } -}; - -static kip1_patchset_t _fs_patches_100[] = -{ +static const kip1_patchset_t _fs_patches_100[] = { { "nogc", NULL }, - { "emummc", _fs_emummc }, { NULL, NULL } }; -static kip1_patch_t _fs_nogc_40x[] = -{ - { KPS(KIP_TEXT) | 0xA3458, 4, "\x14\x40\x80\x72", "\x14\x80\x80\x72" }, - { KPS(KIP_TEXT) | 0xAAB44, 8, "\xF4\x4F\xBE\xA9\xFD\x7B\x01\xA9", "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, +static const kip1_patch_t _fs_nogc_40x[] = { + { KPS(KIP_TEXT) | 0xA3458, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x72" }, + { KPS(KIP_TEXT) | 0xAAB44, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, { 0, 0, NULL, NULL } }; -static kip1_patchset_t _fs_patches_40x[] = -{ +static const kip1_patchset_t _fs_patches_40x[] = { { "nogc", _fs_nogc_40x }, - { "emummc", _fs_emummc }, { NULL, NULL } }; -static kip1_patch_t _fs_nogc_410[] = -{ - { KPS(KIP_TEXT) | 0xA34BC, 4, "\x14\x40\x80\x72", "\x14\x80\x80\x72" }, - { KPS(KIP_TEXT) | 0xAABA8, 8, "\xF4\x4F\xBE\xA9\xFD\x7B\x01\xA9", "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, +static const kip1_patch_t _fs_nogc_410[] = { + { KPS(KIP_TEXT) | 0xA34BC, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x72" }, + { KPS(KIP_TEXT) | 0xAABA8, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, { 0, 0, NULL, NULL } }; -static kip1_patchset_t _fs_patches_410[] = -{ +static const kip1_patchset_t _fs_patches_410[] = { { "nogc", _fs_nogc_410 }, - { "emummc", _fs_emummc }, { NULL, NULL } }; -static kip1_patch_t _fs_nogc_50x[] = -{ - { KPS(KIP_TEXT) | 0xCF3C4, 4, "\x14\x40\x80\x52", "\x14\x80\x80\x52" }, - { KPS(KIP_TEXT) | 0xD73A0, 8, "\xF4\x4F\xBE\xA9\xFD\x7B\x01\xA9", "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, +static const kip1_patch_t _fs_nogc_50x[] = { + { KPS(KIP_TEXT) | 0xCF3C4, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { KPS(KIP_TEXT) | 0xD73A0, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, { 0, 0, NULL, NULL } }; -static kip1_patchset_t _fs_patches_50x[] = -{ +static const kip1_patchset_t _fs_patches_50x[] = { { "nogc", _fs_nogc_50x }, - { "emummc", _fs_emummc }, { NULL, NULL } }; -static kip1_patch_t _fs_nogc_510[] = -{ - { KPS(KIP_TEXT) | 0xCF794, 4, "\x14\x40\x80\x52", "\x14\x80\x80\x52" }, - { KPS(KIP_TEXT) | 0xD7770, 8, "\xF4\x4F\xBE\xA9\xFD\x7B\x01\xA9", "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, +static const kip1_patch_t _fs_nogc_510[] = { + { KPS(KIP_TEXT) | 0xCF794, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { KPS(KIP_TEXT) | 0xD7770, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, { 0, 0, NULL, NULL } }; -static kip1_patchset_t _fs_patches_510[] = -{ +static const kip1_patchset_t _fs_patches_510[] = { { "nogc", _fs_nogc_510 }, - { "emummc", _fs_emummc }, { NULL, NULL } }; -static kip1_patch_t _fs_nogc_600[] = -{ - { KPS(KIP_TEXT) | 0x12CC20, 8, "\xF4\x4F\xBE\xA9\xFD\x7B\x01\xA9", "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, - { KPS(KIP_TEXT) | 0x1538F4, 4, "\x14\x40\x80\x52", "\x14\x80\x80\x52" }, +static const kip1_patch_t _fs_nogc_600[] = { + { KPS(KIP_TEXT) | 0x12CC20, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x1538F4, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, { 0, 0, NULL, NULL } }; -static kip1_patch_t _fs_nogc_600_exfat[] = -{ - { KPS(KIP_TEXT) | 0x138320, 8, "\xF4\x4F\xBE\xA9\xFD\x7B\x01\xA9", "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, - { KPS(KIP_TEXT) | 0x15EFF4, 4, "\x14\x40\x80\x52", "\x14\x80\x80\x52" }, +static const kip1_patch_t _fs_nogc_600_exfat[] = { + { KPS(KIP_TEXT) | 0x138320, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x15EFF4, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, { 0, 0, NULL, NULL } }; -static kip1_patchset_t _fs_patches_600[] = -{ +static const kip1_patchset_t _fs_patches_600[] = { { "nogc", _fs_nogc_600 }, - { "emummc", _fs_emummc }, { NULL, NULL } }; -static kip1_patchset_t _fs_patches_600_exfat[] = -{ +static const kip1_patchset_t _fs_patches_600_exfat[] = { { "nogc", _fs_nogc_600_exfat }, - { "emummc", _fs_emummc }, { NULL, NULL } }; -static kip1_patch_t _fs_nogc_700[] = -{ - { KPS(KIP_TEXT) | 0x134160, 8, "\xF4\x4F\xBE\xA9\xFD\x7B\x01\xA9", "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, - { KPS(KIP_TEXT) | 0x15BF04, 4, "\x14\x40\x80\x52", "\x14\x80\x80\x52" }, +static const kip1_patch_t _fs_nogc_700[] = { + { KPS(KIP_TEXT) | 0x134160, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x15BF04, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, { 0, 0, NULL, NULL } }; -static kip1_patch_t _fs_nogc_700_exfat[] = -{ - { KPS(KIP_TEXT) | 0x13F710, 8, "\xF4\x4F\xBE\xA9\xFD\x7B\x01\xA9", "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, - { KPS(KIP_TEXT) | 0x1674B4, 4, "\x14\x40\x80\x52", "\x14\x80\x80\x52" }, +static const kip1_patch_t _fs_nogc_700_exfat[] = { + { KPS(KIP_TEXT) | 0x13F710, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x1674B4, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, { 0, 0, NULL, NULL } }; -static kip1_patchset_t _fs_patches_700[] = -{ +static const kip1_patchset_t _fs_patches_700[] = { { "nogc", _fs_nogc_700 }, - { "emummc", _fs_emummc }, { NULL, NULL } }; -static kip1_patchset_t _fs_patches_700_exfat[] = -{ +static const kip1_patchset_t _fs_patches_700_exfat[] = { { "nogc", _fs_nogc_700_exfat }, - { "emummc", _fs_emummc }, { NULL, NULL } }; -static kip1_patch_t _fs_nogc_800[] = -{ - { KPS(KIP_TEXT) | 0x136800, 8, "\xF4\x4F\xBE\xA9\xFD\x7B\x01\xA9", "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, - { KPS(KIP_TEXT) | 0x15EB94, 4, "\x14\x40\x80\x52", "\x14\x80\x80\x52" }, +static const kip1_patch_t _fs_nogc_800[] = { + { KPS(KIP_TEXT) | 0x136800, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x15EB94, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, { 0, 0, NULL, NULL } }; -static kip1_patch_t _fs_nogc_800_exfat[] = -{ - { KPS(KIP_TEXT) | 0x141DB0, 8, "\xF4\x4F\xBE\xA9\xFD\x7B\x01\xA9", "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, - { KPS(KIP_TEXT) | 0x16A144, 4, "\x14\x40\x80\x52", "\x14\x80\x80\x52" }, +static const kip1_patch_t _fs_nogc_800_exfat[] = { + { KPS(KIP_TEXT) | 0x141DB0, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x16A144, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, { 0, 0, NULL, NULL } }; -static kip1_patchset_t _fs_patches_800[] = -{ +static const kip1_patchset_t _fs_patches_800[] = { { "nogc", _fs_nogc_800 }, - { "emummc", _fs_emummc }, { NULL, NULL } }; -static kip1_patchset_t _fs_patches_800_exfat[] = -{ +static const kip1_patchset_t _fs_patches_800_exfat[] = { { "nogc", _fs_nogc_800_exfat }, - { "emummc", _fs_emummc }, { NULL, NULL } }; -static kip1_patch_t _fs_nogc_900[] = -{ - { KPS(KIP_TEXT) | 0x129420, 8, "\xF4\x4F\xBE\xA9\xFD\x7B\x01\xA9", "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, - { KPS(KIP_TEXT) | 0x143268, 4, "\x14\x40\x80\x52", "\x14\x80\x80\x52" }, +static const kip1_patch_t _fs_nogc_900[] = { + { KPS(KIP_TEXT) | 0x129420, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x143268, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, { 0, 0, NULL, NULL } }; -static kip1_patchset_t _fs_patches_900[] = -{ +static const kip1_patchset_t _fs_patches_900[] = { { "nogc", _fs_nogc_900 }, - { "emummc", _fs_emummc }, { NULL, NULL } }; -static kip1_patch_t _fs_nogc_910[] = -{ - { KPS(KIP_TEXT) | 0x129430, 8, "\xF4\x4F\xBE\xA9\xFD\x7B\x01\xA9", "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, - { KPS(KIP_TEXT) | 0x143278, 4, "\x14\x40\x80\x52", "\x14\x80\x80\x52" }, +static const kip1_patch_t _fs_nogc_910[] = { + { KPS(KIP_TEXT) | 0x129430, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x143278, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, { 0, 0, NULL, NULL } }; -static kip1_patchset_t _fs_patches_910[] = -{ +static const kip1_patchset_t _fs_patches_910[] = { { "nogc", _fs_nogc_910 }, - { "emummc", _fs_emummc }, { NULL, NULL } }; -static kip1_patch_t _fs_nogc_1000[] = -{ - { KPS(KIP_TEXT) | 0x13BE90, 8, "\xF4\x4F\xBE\xA9\xFD\x7B\x01\xA9", "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, - { KPS(KIP_TEXT) | 0x14DE08, 4, "\x14\x40\x80\x52", "\x14\x80\x80\x52" }, +static const kip1_patch_t _fs_nogc_1000[] = { + { KPS(KIP_TEXT) | 0x13BE90, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x14DE08, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, { 0, 0, NULL, NULL } }; -static kip1_patchset_t _fs_patches_1000[] = -{ +static const kip1_patchset_t _fs_patches_1000[] = { { "nogc", _fs_nogc_1000 }, - { "emummc", _fs_emummc }, { NULL, NULL } }; -static kip1_patch_t _fs_nogc_1020[] = -{ - { KPS(KIP_TEXT) | 0x13C2F0, 8, "\xF4\x4F\xBE\xA9\xFD\x7B\x01\xA9", "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, - { KPS(KIP_TEXT) | 0x14E268, 4, "\x14\x40\x80\x52", "\x14\x80\x80\x52" }, +static const kip1_patch_t _fs_nogc_1020[] = { + { KPS(KIP_TEXT) | 0x13C2F0, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x14E268, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, { 0, 0, NULL, NULL } }; -static kip1_patchset_t _fs_patches_1020[] = -{ +static const kip1_patchset_t _fs_patches_1020[] = { { "nogc", _fs_nogc_1020 }, - { "emummc", _fs_emummc }, { NULL, NULL } }; -static kip1_patch_t _fs_nogc_1100[] = -{ - { KPS(KIP_TEXT) | 0x1398B4, 8, "\xF4\x4F\xBE\xA9\xFD\x7B\x01\xA9", "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, - { KPS(KIP_TEXT) | 0x156EB8, 4, "\x14\x40\x80\x52", "\x14\x80\x80\x52" }, +static const kip1_patch_t _fs_nogc_1100[] = { + { KPS(KIP_TEXT) | 0x1398B4, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x156EB8, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, { 0, 0, NULL, NULL } }; -static kip1_patchset_t _fs_patches_1100[] = -{ +static const kip1_patchset_t _fs_patches_1100[] = { { "nogc", _fs_nogc_1100 }, - { "emummc", _fs_emummc }, { NULL, NULL } }; -static kip1_patch_t _fs_nogc_1200[] = -{ - { KPS(KIP_TEXT) | 0x13EA24, 8, "\xFD\x7B\xBE\xA9\xF4\x4F\x01\xA9", "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, - { KPS(KIP_TEXT) | 0x155368, 4, "\x14\x40\x80\x52", "\x14\x80\x80\x52" }, +static const kip1_patch_t _fs_nogc_1200[] = { + { KPS(KIP_TEXT) | 0x13EA24, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x155368, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, { 0, 0, NULL, NULL } }; -static kip1_patchset_t _fs_patches_1200[] = -{ +static const kip1_patchset_t _fs_patches_1200[] = { { "nogc", _fs_nogc_1200 }, - { "emummc", _fs_emummc }, { NULL, NULL } }; -static kip1_patch_t _fs_nogc_1203[] = -{ - { KPS(KIP_TEXT) | 0x13EB34, 8, "\xFD\x7B\xBE\xA9\xF4\x4F\x01\xA9", "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, - { KPS(KIP_TEXT) | 0x155478, 4, "\x14\x40\x80\x52", "\x14\x80\x80\x52" }, +static const kip1_patch_t _fs_nogc_1203[] = { + { KPS(KIP_TEXT) | 0x13EB34, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x155478, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, { 0, 0, NULL, NULL } }; -static kip1_patchset_t _fs_patches_1203[] = -{ +static const kip1_patchset_t _fs_patches_1203[] = { { "nogc", _fs_nogc_1203 }, - { "emummc", _fs_emummc }, { NULL, NULL } }; -static kip1_patch_t _fs_nogc_1300[] = -{ - { KPS(KIP_TEXT) | 0x1425D0, 8, "\xFD\x7B\xBE\xA9\xF4\x4F\x01\xA9", "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, - { KPS(KIP_TEXT) | 0x159018, 4, "\x14\x40\x80\x52", "\x14\x80\x80\x52" }, +static const kip1_patch_t _fs_nogc_1300[] = { + { KPS(KIP_TEXT) | 0x1425D0, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x159018, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, { 0, 0, NULL, NULL } }; -static kip1_patchset_t _fs_patches_1300[] = -{ +static const kip1_patchset_t _fs_patches_1300[] = { { "nogc", _fs_nogc_1300 }, - { "emummc", _fs_emummc }, + { NULL, NULL } +}; + +static const kip1_patch_t _fs_nogc_1310[] = { + { KPS(KIP_TEXT) | 0x142570, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x158FB8, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { 0, 0, NULL, NULL } +}; + +static const kip1_patchset_t _fs_patches_1310[] = { + { "nogc", _fs_nogc_1310 }, + { NULL, NULL } +}; + +static const kip1_patch_t _fs_nogc_1400[] = { + { KPS(KIP_TEXT) | 0x164230, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x18A2E8, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { 0, 0, NULL, NULL } +}; + +static const kip1_patchset_t _fs_patches_1400[] = { + { "nogc", _fs_nogc_1400 }, + { NULL, NULL } +}; + +static const kip1_patch_t _fs_nogc_1400_exfat[] = { + { KPS(KIP_TEXT) | 0x16F5B0, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x195668, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { 0, 0, NULL, NULL } +}; + +static const kip1_patchset_t _fs_patches_1400_exfat[] = { + { "nogc", _fs_nogc_1400_exfat }, + { NULL, NULL } +}; + +static const kip1_patch_t _fs_nogc_1500[] = { + { KPS(KIP_TEXT) | 0x15ECE4, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x184158, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { 0, 0, NULL, NULL } +}; + +static const kip1_patchset_t _fs_patches_1500[] = { + { "nogc", _fs_nogc_1500 }, + { NULL, NULL } +}; + +static const kip1_patch_t _fs_nogc_1500_exfat[] = { + { KPS(KIP_TEXT) | 0x169C74, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x18F0E8, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { 0, 0, NULL, NULL } +}; + +static const kip1_patchset_t _fs_patches_1500_exfat[] = { + { "nogc", _fs_nogc_1500_exfat }, + { NULL, NULL } +}; + +static const kip1_patch_t _fs_nogc_1600[] = { + { KPS(KIP_TEXT) | 0x160B70, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x1865D8, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { 0, 0, NULL, NULL } +}; + +static const kip1_patchset_t _fs_patches_1600[] = { + { "nogc", _fs_nogc_1600 }, + { NULL, NULL } +}; + +static const kip1_patch_t _fs_nogc_1600_exfat[] = { + { KPS(KIP_TEXT) | 0x16B850, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x1912B8, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { 0, 0, NULL, NULL } +}; + +static const kip1_patchset_t _fs_patches_1600_exfat[] = { + { "nogc", _fs_nogc_1600_exfat }, + { NULL, NULL } +}; + +static const kip1_patch_t _fs_nogc_1603[] = { + { KPS(KIP_TEXT) | 0x160BC0, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x186628, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { 0, 0, NULL, NULL } +}; + +static const kip1_patchset_t _fs_patches_1603[] = { + { "nogc", _fs_nogc_1603 }, + { NULL, NULL } +}; + +static const kip1_patch_t _fs_nogc_1603_exfat[] = { + { KPS(KIP_TEXT) | 0x16B8A0, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x191308, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { 0, 0, NULL, NULL } +}; + +static const kip1_patchset_t _fs_patches_1603_exfat[] = { + { "nogc", _fs_nogc_1603_exfat }, + { NULL, NULL } +}; + +static const kip1_patch_t _fs_nogc_1700[] = { + { KPS(KIP_TEXT) | 0x165100, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x18B048, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { 0, 0, NULL, NULL } +}; + +static const kip1_patchset_t _fs_patches_1700[] = { + { "nogc", _fs_nogc_1700 }, + { NULL, NULL } +}; + +static const kip1_patch_t _fs_nogc_1700_exfat[] = { + { KPS(KIP_TEXT) | 0x16FF60, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x195EA8, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { 0, 0, NULL, NULL } +}; + +static const kip1_patchset_t _fs_patches_1700_exfat[] = { + { "nogc", _fs_nogc_1700_exfat }, + { NULL, NULL } +}; + +static const kip1_patch_t _fs_nogc_1800[] = { + { KPS(KIP_TEXT) | 0x164A50, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x18AE48, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { 0, 0, NULL, NULL } +}; + +static const kip1_patchset_t _fs_patches_1800[] = { + { "nogc", _fs_nogc_1800 }, + { NULL, NULL } +}; + +static const kip1_patch_t _fs_nogc_1800_exfat[] = { + { KPS(KIP_TEXT) | 0x16FAE0, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x195ED8, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { 0, 0, NULL, NULL } +}; + +static const kip1_patchset_t _fs_patches_1800_exfat[] = { + { "nogc", _fs_nogc_1800_exfat }, + { NULL, NULL } +}; + +static const kip1_patch_t _fs_nogc_1900[] = { + { KPS(KIP_TEXT) | 0x16F070, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x195B74, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { KPS(KIP_TEXT) | 0x195D74, 4, KIP1_PATCH_SRC_NO_CHECK, "\x16\x80\x80\x52" }, + { 0, 0, NULL, NULL } +}; + +static const kip1_patchset_t _fs_patches_1900[] = { + { "nogc", _fs_nogc_1900 }, + { NULL, NULL } +}; + +static const kip1_patch_t _fs_nogc_1900_exfat[] = { + { KPS(KIP_TEXT) | 0x17A8A0, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x1A13A4, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { KPS(KIP_TEXT) | 0x1A15A4, 4, KIP1_PATCH_SRC_NO_CHECK, "\x16\x80\x80\x52" }, + { 0, 0, NULL, NULL } +}; + +static const kip1_patchset_t _fs_patches_1900_exfat[] = { + { "nogc", _fs_nogc_1900_exfat }, + { NULL, NULL } +}; + +static const kip1_patch_t _fs_nogc_2000[] = { + { KPS(KIP_TEXT) | 0x17C150, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x1A7D24, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { KPS(KIP_TEXT) | 0x1A7F24, 4, KIP1_PATCH_SRC_NO_CHECK, "\x16\x80\x80\x52" }, + { 0, 0, NULL, NULL } +}; + +static const kip1_patchset_t _fs_patches_2000[] = { + { "nogc", _fs_nogc_2000 }, + { NULL, NULL } +}; + +static const kip1_patch_t _fs_nogc_2000_exfat[] = { + { KPS(KIP_TEXT) | 0x187A70, 8, KIP1_PATCH_SRC_NO_CHECK, "\xE0\x03\x1F\x2A\xC0\x03\x5F\xD6" }, + { KPS(KIP_TEXT) | 0x1B3644, 4, KIP1_PATCH_SRC_NO_CHECK, "\x14\x80\x80\x52" }, + { KPS(KIP_TEXT) | 0x1B3844, 4, KIP1_PATCH_SRC_NO_CHECK, "\x16\x80\x80\x52" }, + { 0, 0, NULL, NULL } +}; + +static const kip1_patchset_t _fs_patches_2000_exfat[] = { + { "nogc", _fs_nogc_2000_exfat }, { NULL, NULL } }; // SHA256 hashes. -static kip1_id_t _kip_ids[] = +static const kip1_id_t _kip_ids[] = { - { "FS", "\xde\x9f\xdd\xa4\x08\x5d\xd5\xfe", _fs_patches_100 }, // FS 1.0.0 - { "FS", "\xfc\x3e\x80\x99\x1d\xca\x17\x96", _fs_patches_100 }, // FS 1.0.0 exFAT - { "FS", "\xcd\x7b\xbe\x18\xd6\x13\x0b\x28", _fs_patches_100 }, // FS 2.0.0 - { "FS", "\xe7\x66\x92\xdf\xaa\x04\x20\xe9", _fs_patches_100 }, // FS 2.0.0 exFAT - { "FS", "\x0d\x70\x05\x62\x7b\x07\x76\x7c", _fs_patches_100 }, // FS 2.1.0 - { "FS", "\xdb\xd8\x5f\xca\xcc\x19\x3d\xa8", _fs_patches_100 }, // FS 2.1.0 exFAT - { "FS", "\xa8\x6d\xa5\xe8\x7e\xf1\x09\x7b", _fs_patches_100 }, // FS 3.0.0 - { "FS", "\x98\x1c\x57\xe7\xf0\x2f\x70\xf7", _fs_patches_100 }, // FS 3.0.0 exFAT - { "FS", "\x57\x39\x7c\x06\x3f\x10\xb6\x31", _fs_patches_100 }, // FS 3.0.1 - { "FS", "\x07\x30\x99\xd7\xc6\xad\x7d\x89", _fs_patches_100 }, // FS 3.0.1 exFAT - { "FS", "\x06\xe9\x07\x19\x59\x5a\x01\x0c", _fs_patches_40x }, // FS 4.0.1 - { "FS", "\x54\x9b\x0f\x8d\x6f\x72\xc4\xe9", _fs_patches_40x }, // FS 4.0.1 exFAT - { "FS", "\x80\x96\xaf\x7c\x6a\x35\xaa\x82", _fs_patches_410 }, // FS 4.1.0 - { "FS", "\x02\xd5\xab\xaa\xfd\x20\xc8\xb0", _fs_patches_410 }, // FS 4.1.0 exFAT - { "FS", "\xa6\xf2\x7a\xd9\xac\x7c\x73\xad", _fs_patches_50x }, // FS 5.0.0 - { "FS", "\xce\x3e\xcb\xa2\xf2\xf0\x62\xf5", _fs_patches_50x }, // FS 5.0.0 exFAT - { "FS", "\x76\xf8\x74\x02\xc9\x38\x7c\x0f", _fs_patches_510 }, // FS 5.1.0 - { "FS", "\x10\xb2\xd8\x16\x05\x48\x85\x99", _fs_patches_510 }, // FS 5.1.0 exFAT - { "FS", "\x1b\x82\xcb\x22\x18\x67\xcb\x52", _fs_patches_600 }, // FS 6.0.0-4.0 - { "FS", "\x96\x6a\xdd\x3d\x20\xb6\x27\x13", _fs_patches_600_exfat }, // FS 6.0.0-4.0 exFAT - { "FS", "\x3a\x57\x4d\x43\x61\x86\x19\x1d", _fs_patches_600 }, // FS 6.0.0-5.0 - { "FS", "\x33\x05\x53\xf6\xb5\xfb\x55\xc4", _fs_patches_600_exfat }, // FS 6.0.0-5.0 exFAT - { "FS", "\x2A\xDB\xE9\x7E\x9B\x5F\x41\x77", _fs_patches_700 }, // FS 7.0.0 - { "FS", "\x2C\xCE\x65\x9C\xEC\x53\x6A\x8E", _fs_patches_700_exfat }, // FS 7.0.0 exFAT - { "FS", "\xB2\xF5\x17\x6B\x35\x48\x36\x4D", _fs_patches_800 }, // FS 8.0.0 - { "FS", "\xDB\xD9\x41\xC0\xC5\x3C\x52\xCC", _fs_patches_800_exfat }, // FS 8.0.0 exFAT - { "FS", "\x6B\x09\xB6\x7B\x29\xC0\x20\x24", _fs_patches_800 }, // FS 8.1.0 - { "FS", "\xB4\xCA\xE1\xF2\x49\x65\xD9\x2E", _fs_patches_800_exfat }, // FS 8.1.0 exFAT - { "FS", "\x46\x87\x40\x76\x1E\x19\x3E\xB7", _fs_patches_900 }, // FS 9.0.0 - { "FS", "\x7C\x95\x13\x76\xE5\xC1\x2D\xF8", _fs_patches_900 }, // FS 9.0.0 exFAT - { "FS", "\xB5\xE7\xA6\x4C\x6F\x5C\x4F\xE3", _fs_patches_910 }, // FS 9.1.0 - { "FS", "\xF1\x96\xD1\x44\xD0\x44\x45\xB6", _fs_patches_910 }, // FS 9.1.0 exFAT - { "FS", "\x3E\xEB\xD9\xB7\xBC\xD1\xB5\xE0", _fs_patches_1000 }, // FS 10.0.0 - { "FS", "\x81\x7E\xA2\xB0\xB7\x02\xC1\xF3", _fs_patches_1000 }, // FS 10.0.0 exFAT - { "FS", "\xA9\x52\xB6\x57\xAD\xF9\xC2\xBA", _fs_patches_1020 }, // FS 10.2.0 - { "FS", "\x16\x0D\x3E\x10\x4E\xAD\x61\x76", _fs_patches_1020 }, // FS 10.2.0 exFAT - { "FS", "\xE3\x99\x15\x6E\x84\x4E\xB0\xAA", _fs_patches_1100 }, // FS 11.0.0 - { "FS", "\x0B\xA1\x5B\xB3\x04\xB5\x05\x63", _fs_patches_1100 }, // FS 11.0.0 exFAT - { "FS", "\xDC\x2A\x08\x49\x96\xBB\x3C\x01", _fs_patches_1200 }, // FS 12.0.0 - { "FS", "\xD5\xA5\xBF\x36\x64\x0C\x49\xEA", _fs_patches_1200 }, // FS 12.0.0 exFAT - { "FS", "\xC8\x67\x62\xBE\x19\xA5\x1F\xA0", _fs_patches_1203 }, // FS 12.0.3 - { "FS", "\xE1\xE8\xD3\xD6\xA2\xFE\x0B\x10", _fs_patches_1203 }, // FS 12.0.3 exFAT - { "FS", "\x7D\x20\x05\x47\x17\x8A\x83\x6A", _fs_patches_1300 }, // FS 13.0.0 - { "FS", "\x51\xEB\xFA\x9C\xCF\x66\xC0\x9E", _fs_patches_1300 }, // FS 13.0.0 exFAT + { "FS", "\xde\x9f\xdd\xa4\x08\x5d\xd5\xfe", _fs_patches_100 }, // FS 1.0.0 + { "FS", "\xfc\x3e\x80\x99\x1d\xca\x17\x96", _fs_patches_100 }, // FS 1.0.0 exFAT + { "FS", "\xcd\x7b\xbe\x18\xd6\x13\x0b\x28", _fs_patches_100 }, // FS 2.0.0 + { "FS", "\xe7\x66\x92\xdf\xaa\x04\x20\xe9", _fs_patches_100 }, // FS 2.0.0 exFAT + { "FS", "\x0d\x70\x05\x62\x7b\x07\x76\x7c", _fs_patches_100 }, // FS 2.1.0 + { "FS", "\xdb\xd8\x5f\xca\xcc\x19\x3d\xa8", _fs_patches_100 }, // FS 2.1.0 exFAT + { "FS", "\xa8\x6d\xa5\xe8\x7e\xf1\x09\x7b", _fs_patches_100 }, // FS 3.0.0 + { "FS", "\x98\x1c\x57\xe7\xf0\x2f\x70\xf7", _fs_patches_100 }, // FS 3.0.0 exFAT + { "FS", "\x57\x39\x7c\x06\x3f\x10\xb6\x31", _fs_patches_100 }, // FS 3.0.1 + { "FS", "\x07\x30\x99\xd7\xc6\xad\x7d\x89", _fs_patches_100 }, // FS 3.0.1 exFAT + { "FS", "\x06\xe9\x07\x19\x59\x5a\x01\x0c", _fs_patches_40x }, // FS 4.0.1 + { "FS", "\x54\x9b\x0f\x8d\x6f\x72\xc4\xe9", _fs_patches_40x }, // FS 4.0.1 exFAT + { "FS", "\x80\x96\xaf\x7c\x6a\x35\xaa\x82", _fs_patches_410 }, // FS 4.1.0 + { "FS", "\x02\xd5\xab\xaa\xfd\x20\xc8\xb0", _fs_patches_410 }, // FS 4.1.0 exFAT + { "FS", "\xa6\xf2\x7a\xd9\xac\x7c\x73\xad", _fs_patches_50x }, // FS 5.0.0 + { "FS", "\xce\x3e\xcb\xa2\xf2\xf0\x62\xf5", _fs_patches_50x }, // FS 5.0.0 exFAT + { "FS", "\x76\xf8\x74\x02\xc9\x38\x7c\x0f", _fs_patches_510 }, // FS 5.1.0 + { "FS", "\x10\xb2\xd8\x16\x05\x48\x85\x99", _fs_patches_510 }, // FS 5.1.0 exFAT + { "FS", "\x1b\x82\xcb\x22\x18\x67\xcb\x52", _fs_patches_600 }, // FS 6.0.0-4.0 + { "FS", "\x96\x6a\xdd\x3d\x20\xb6\x27\x13", _fs_patches_600_exfat }, // FS 6.0.0-4.0 exFAT + { "FS", "\x3a\x57\x4d\x43\x61\x86\x19\x1d", _fs_patches_600 }, // FS 6.0.0-5.0 + { "FS", "\x33\x05\x53\xf6\xb5\xfb\x55\xc4", _fs_patches_600_exfat }, // FS 6.0.0-5.0 exFAT + { "FS", "\x2A\xDB\xE9\x7E\x9B\x5F\x41\x77", _fs_patches_700 }, // FS 7.0.0 + { "FS", "\x2C\xCE\x65\x9C\xEC\x53\x6A\x8E", _fs_patches_700_exfat }, // FS 7.0.0 exFAT + { "FS", "\xB2\xF5\x17\x6B\x35\x48\x36\x4D", _fs_patches_800 }, // FS 8.0.0 + { "FS", "\xDB\xD9\x41\xC0\xC5\x3C\x52\xCC", _fs_patches_800_exfat }, // FS 8.0.0 exFAT + { "FS", "\x6B\x09\xB6\x7B\x29\xC0\x20\x24", _fs_patches_800 }, // FS 8.1.0 + { "FS", "\xB4\xCA\xE1\xF2\x49\x65\xD9\x2E", _fs_patches_800_exfat }, // FS 8.1.0 exFAT + { "FS", "\x46\x87\x40\x76\x1E\x19\x3E\xB7", _fs_patches_900 }, // FS 9.0.0 + { "FS", "\x7C\x95\x13\x76\xE5\xC1\x2D\xF8", _fs_patches_900 }, // FS 9.0.0 exFAT + { "FS", "\xB5\xE7\xA6\x4C\x6F\x5C\x4F\xE3", _fs_patches_910 }, // FS 9.1.0 + { "FS", "\xF1\x96\xD1\x44\xD0\x44\x45\xB6", _fs_patches_910 }, // FS 9.1.0 exFAT + { "FS", "\x3E\xEB\xD9\xB7\xBC\xD1\xB5\xE0", _fs_patches_1000 }, // FS 10.0.0 + { "FS", "\x81\x7E\xA2\xB0\xB7\x02\xC1\xF3", _fs_patches_1000 }, // FS 10.0.0 exFAT + { "FS", "\xA9\x52\xB6\x57\xAD\xF9\xC2\xBA", _fs_patches_1020 }, // FS 10.2.0 + { "FS", "\x16\x0D\x3E\x10\x4E\xAD\x61\x76", _fs_patches_1020 }, // FS 10.2.0 exFAT + { "FS", "\xE3\x99\x15\x6E\x84\x4E\xB0\xAA", _fs_patches_1100 }, // FS 11.0.0 + { "FS", "\x0B\xA1\x5B\xB3\x04\xB5\x05\x63", _fs_patches_1100 }, // FS 11.0.0 exFAT + { "FS", "\xDC\x2A\x08\x49\x96\xBB\x3C\x01", _fs_patches_1200 }, // FS 12.0.0 + { "FS", "\xD5\xA5\xBF\x36\x64\x0C\x49\xEA", _fs_patches_1200 }, // FS 12.0.0 exFAT + { "FS", "\xC8\x67\x62\xBE\x19\xA5\x1F\xA0", _fs_patches_1203 }, // FS 12.0.3 + { "FS", "\xE1\xE8\xD3\xD6\xA2\xFE\x0B\x10", _fs_patches_1203 }, // FS 12.0.3 exFAT + { "FS", "\x7D\x20\x05\x47\x17\x8A\x83\x6A", _fs_patches_1300 }, // FS 13.0.0 + { "FS", "\x51\xEB\xFA\x9C\xCF\x66\xC0\x9E", _fs_patches_1300 }, // FS 13.0.0 exFAT + { "FS", "\x91\xBA\x65\xA2\x1C\x1D\x50\xAE", _fs_patches_1310 }, // FS 13.1.0 + { "FS", "\x76\x38\x27\xEE\x9C\x20\x7E\x5B", _fs_patches_1310 }, // FS 13.1.0 exFAT + { "FS", "\x88\x7A\xC1\x50\x80\x6C\x75\xCC", _fs_patches_1400 }, // FS 14.0.0 + { "FS", "\xD4\x88\xD1\xF2\x92\x17\x35\x5C", _fs_patches_1400_exfat }, // FS 14.0.0 exFAT + { "FS", "\xD0\xD4\x49\x18\x14\xB5\x62\xAF", _fs_patches_1500 }, // FS 15.0.0 + { "FS", "\x34\xC0\xD9\xED\x6A\xD1\x87\x3D", _fs_patches_1500_exfat }, // FS 15.0.0 exFAT + { "FS", "\x56\xE8\x56\x56\x6C\x38\xD8\xBE", _fs_patches_1600 }, // FS 16.0.0 + { "FS", "\xCF\xAB\x45\x0C\x2C\x53\x9D\xA9", _fs_patches_1600_exfat }, // FS 16.0.0 exFAT + { "FS", "\x39\xEE\x1F\x1E\x0E\xA7\x32\x5D", _fs_patches_1603 }, // FS 16.0.3 + { "FS", "\x62\xC6\x5E\xFD\x9A\xBF\x7C\x43", _fs_patches_1603_exfat }, // FS 16.0.3 exFAT + { "FS", "\x27\x07\x3B\xF0\xA1\xB8\xCE\x61", _fs_patches_1700 }, // FS 17.0.0 + { "FS", "\xEE\x0F\x4B\xAC\x6D\x1F\xFC\x4B", _fs_patches_1700_exfat }, // FS 17.0.0 exFAT + { "FS", "\x79\x5F\x5A\x5E\xB0\xC6\x77\x9E", _fs_patches_1800 }, // FS 18.0.0 + { "FS", "\x1E\x2C\x64\xB1\xCC\xE2\x78\x24", _fs_patches_1800_exfat }, // FS 18.0.0 exFAT + { "FS", "\xA3\x39\xF0\x1C\x95\xBF\xA7\x68", _fs_patches_1800 }, // FS 18.1.0 + { "FS", "\x20\x4C\xBA\x86\xDE\x08\x44\x6A", _fs_patches_1800_exfat }, // FS 18.1.0 exFAT + { "FS", "\xD9\x4C\x68\x15\xF8\xF5\x0A\x20", _fs_patches_1900 }, // FS 19.0.0 + { "FS", "\xED\xA8\x78\x68\xA4\x49\x07\x50", _fs_patches_1900_exfat }, // FS 19.0.0 exFAT + { "FS", "\x63\x54\x96\x9E\x60\xA7\x97\x7B", _fs_patches_2000 }, // FS 20.0.0 + { "FS", "\x47\x41\x07\x10\x65\x4F\xA4\x3F", _fs_patches_2000_exfat }, // FS 20.0.0 exFAT + { "FS", "\xED\x34\xB4\x50\x58\x4A\x5B\x43", _fs_patches_2000 }, // FS 20.1.0 + { "FS", "\xA5\x1A\xA4\x92\x6C\x41\x87\x59", _fs_patches_2000_exfat }, // FS 20.1.0 exFAT }; diff --git a/bootloader/hos/pkg3.c b/bootloader/hos/pkg3.c new file mode 100644 index 0000000..6752063 --- /dev/null +++ b/bootloader/hos/pkg3.c @@ -0,0 +1,282 @@ +/* + * Atmosphère Package 3 parser. + * + * Copyright (c) 2019-2025 CTCaer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +#include + +#include "pkg3.h" +#include "hos.h" +#include "../config.h" +#include +#include "../storage/emummc.h" + +//#define DPRINTF(...) gfx_printf(__VA_ARGS__) +#define DPRINTF(...) + +extern hekate_config h_cfg; + +extern bool is_ipl_updated(void *buf, const char *path, bool force); + +#define PKG3_KIP_SKIP_MAX 16 + +// PKG3 Magic and Meta header offset. +#define PKG3_MAGIC 0x30535346 // FSS0. +#define PKG3_META_OFFSET 0x4 +#define PKG3_VERSION_0_17_0 0x110000 + +// PKG3 Content Types. +#define CNT_TYPE_FSP 0 +#define CNT_TYPE_EXO 1 // Exosphere (Secure Monitor). +#define CNT_TYPE_WBT 2 // Warmboot (SC7Exit fw). +#define CNT_TYPE_RBT 3 // Rebootstub (Warmboot based reboot fw). +#define CNT_TYPE_SP1 4 // Sept Primary (TSEC and Sept Secondary loader). +#define CNT_TYPE_SP2 5 // Sept Secondary (Acts as pkg11 and derives keys). +#define CNT_TYPE_KIP 6 // KIP1 (Used for replacement or addition). +#define CNT_TYPE_BMP 7 +#define CNT_TYPE_EMC 8 +#define CNT_TYPE_KLD 9 // Kernel Loader. +#define CNT_TYPE_KRN 10 // Kernel. +#define CNT_TYPE_EXF 11 // Exosphere Mariko fatal payload. +#define CNT_TYPE_TKG 12 // Tsec Keygen. + +// PKG3 Content Flags. +#define CNT_FLAG0_EXPERIMENTAL BIT(0) + +// PKG3 Meta Header. +typedef struct _pkg3_meta_t +{ + u32 magic; + u32 size; + u32 crt0_off; + u32 cnt_off; + u32 cnt_count; + u32 hos_ver; + u32 version; + u32 git_rev; +} pkg3_meta_t; + +// PKG3 Content Header. +typedef struct _pkg3_content_t +{ + u32 offset; + u32 size; + u8 type; + u8 flags0; + u8 flags1; + u8 flags2; + u32 rsvd1; + char name[0x10]; +} pkg3_content_t; + +static void _pkg3_update_r2p() +{ + u8 *r2p_payload = sd_file_read("atmosphere/reboot_payload.bin", NULL); + + is_ipl_updated(r2p_payload, "atmosphere/reboot_payload.bin", h_cfg.updater2p ? true : false); + + free(r2p_payload); +} + +static int _pkg3_kip1_skip(char ***pkg3_kip1_skip, u32 *pkg3_kip1_skip_num, char *value) +{ + int len = strlen(value); + if (!len || (*pkg3_kip1_skip_num) >= PKG3_KIP_SKIP_MAX) + return 0; + + // Allocate pointer list memory. + if (!(*pkg3_kip1_skip)) + (*pkg3_kip1_skip) = calloc(PKG3_KIP_SKIP_MAX, sizeof(char *)); + + // Set first kip name. + (*pkg3_kip1_skip)[(*pkg3_kip1_skip_num)++] = value; + + // Check if more names are set separated by comma. + for (char *c = value; *c != 0; c++) + { + if (*c == ',') + { + *c = 0; // Null termination. + + // Set next kip name to the list. + (*pkg3_kip1_skip)[(*pkg3_kip1_skip_num)++] = c + 1; + + if ((*pkg3_kip1_skip_num) >= PKG3_KIP_SKIP_MAX) + return 0; + } + } + + return 1; +} + +int parse_pkg3(launch_ctxt_t *ctxt, const char *path) +{ + FIL fp; + + char **pkg3_kip1_skip = NULL; + u32 pkg3_kip1_skip_num = 0; + + bool stock = false; + bool experimental = false; + + // Skip if stock and Exosphere and warmboot are not needed. + bool pkg1_old = ctxt->pkg1_id->kb <= HOS_KB_VERSION_620; // Should check if t210b01? + bool emummc_disabled = !emu_cfg.enabled || h_cfg.emummc_force_disable; + + LIST_FOREACH_ENTRY(ini_kv_t, kv, &ctxt->cfg->kvs, link) + { + if (!strcmp("stock", kv->key)) + if (kv->val[0] == '1') + stock = true; + + if (!strcmp("pkg3ex", kv->key)) + if (kv->val[0] == '1') + experimental = true; + + if (!strcmp("pkg3kip1skip", kv->key)) + _pkg3_kip1_skip(&pkg3_kip1_skip, &pkg3_kip1_skip_num, kv->val); + } + +#ifdef HOS_MARIKO_STOCK_SECMON + if (stock && emummc_disabled && (pkg1_old || h_cfg.t210b01)) + return 1; +#else + if (stock && emummc_disabled && pkg1_old) + return 1; +#endif + + // Try to open PKG3. + if (f_open(&fp, path, FA_READ) != FR_OK) + return 0; + + void *pkg3 = malloc(f_size(&fp)); + + // Read first 1024 bytes of the PKG3 file. + f_read(&fp, pkg3, 1024, NULL); + + // Get PKG3 Meta header offset. + u32 pkg3_meta_addr = *(u32 *)(pkg3 + PKG3_META_OFFSET); + pkg3_meta_t *pkg3_meta = (pkg3_meta_t *)(pkg3 + pkg3_meta_addr); + + // Check if valid PKG3 and parse it. + if (pkg3_meta->magic == PKG3_MAGIC) + { + gfx_printf("Atmosphere %d.%d.%d-%08x via PKG3\n" + "Max HOS: %d.%d.%d\n" + "Unpacking.. ", + pkg3_meta->version >> 24, (pkg3_meta->version >> 16) & 0xFF, (pkg3_meta->version >> 8) & 0xFF, pkg3_meta->git_rev, + pkg3_meta->hos_ver >> 24, (pkg3_meta->hos_ver >> 16) & 0xFF, (pkg3_meta->hos_ver >> 8) & 0xFF); + + ctxt->patch_krn_proc_id = true; + ctxt->pkg3_hosver = pkg3_meta->hos_ver; + + // Parse PKG3 contents. + pkg3_content_t *curr_pkg3_cnt = (pkg3_content_t *)(pkg3 + pkg3_meta->cnt_off); + void *content; + for (u32 i = 0; i < pkg3_meta->cnt_count; i++) + { + content = (void *)(pkg3 + curr_pkg3_cnt[i].offset); + + // Check if offset is inside limits. + if ((curr_pkg3_cnt[i].offset + curr_pkg3_cnt[i].size) > pkg3_meta->size) + continue; + + // If content is experimental and experimental config is not enabled, skip it. + if ((curr_pkg3_cnt[i].flags0 & CNT_FLAG0_EXPERIMENTAL) && !experimental) + continue; + + // Prepare content. + switch (curr_pkg3_cnt[i].type) + { + case CNT_TYPE_KIP: + if (stock) + continue; + + bool should_skip = false; + for (u32 k = 0; k < pkg3_kip1_skip_num; k++) + { + if (!strcmp(curr_pkg3_cnt[i].name, pkg3_kip1_skip[k])) + { + gfx_printf("Skipped %s.kip1 from PKG3\n", curr_pkg3_cnt[i].name); + should_skip = true; + break; + } + } + if (should_skip) + continue; + + merge_kip_t *mkip1 = (merge_kip_t *)malloc(sizeof(merge_kip_t)); + mkip1->kip1 = content; + list_append(&ctxt->kip1_list, &mkip1->link); + DPRINTF("Loaded %s.kip1 from PKG3 (size %08X)\n", curr_pkg3_cnt[i].name, curr_pkg3_cnt[i].size); + break; + + case CNT_TYPE_KRN: + if (stock) + continue; + ctxt->kernel_size = curr_pkg3_cnt[i].size; + ctxt->kernel = content; + break; + + case CNT_TYPE_EXO: + ctxt->secmon_size = curr_pkg3_cnt[i].size; + ctxt->secmon = content; + break; + + case CNT_TYPE_EXF: + ctxt->exofatal_size = curr_pkg3_cnt[i].size; + ctxt->exofatal = content; + break; + + case CNT_TYPE_WBT: + if (h_cfg.t210b01) + continue; + ctxt->warmboot_size = curr_pkg3_cnt[i].size; + ctxt->warmboot = content; + break; + + default: + continue; + } + + // Load content to launch context. + f_lseek(&fp, curr_pkg3_cnt[i].offset); + f_read(&fp, content, curr_pkg3_cnt[i].size, NULL); + } + + gfx_printf("Done!\n"); + f_close(&fp); + + ctxt->pkg3 = pkg3; + + // Update r2p if needed. + _pkg3_update_r2p(); + + free(pkg3_kip1_skip); + + return 1; + } + + // Failed. Close and free all. + f_close(&fp); + + free(pkg3_kip1_skip); + free(pkg3); + + return 0; +} diff --git a/bootloader/hos/fss.h b/bootloader/hos/pkg3.h similarity index 88% rename from bootloader/hos/fss.h rename to bootloader/hos/pkg3.h index e7e23bb..8d230ab 100644 --- a/bootloader/hos/fss.h +++ b/bootloader/hos/pkg3.h @@ -14,11 +14,11 @@ * along with this program. If not, see . */ -#ifndef _FSS_H_ -#define _FSS_H_ +#ifndef _PKG3_H_ +#define _PKG3_H_ #include "hos.h" -int parse_fss(launch_ctxt_t *ctxt, const char *path); +int parse_pkg3(launch_ctxt_t *ctxt, const char *path); #endif diff --git a/bootloader/hos/secmon_exo.c b/bootloader/hos/secmon_exo.c index 3ecade6..5b2d9f1 100644 --- a/bootloader/hos/secmon_exo.c +++ b/bootloader/hos/secmon_exo.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2024 CTCaer * Copyright (c) 2019 Atmosphère-NX * * This program is free software; you can redistribute it and/or modify it @@ -18,20 +18,12 @@ #include #include +#include + #include "hos.h" #include "../config.h" -#include -#include #include -#include -#include #include "../storage/emummc.h" -#include "../storage/nx_emmc.h" -#include -#include -#include -#include -#include extern hekate_config h_cfg; @@ -131,7 +123,7 @@ typedef struct _atm_fatal_error_ctx #define ATM_FATAL_MAGIC 0x30454641 // AFE0 #define ATM_EXO_FATAL_ADDR 0x80020000 -#define ATM_EXO_FATAL_SIZE 0x20000 +#define ATM_EXO_FATAL_SIZE SZ_128K #define ATM_WB_HEADER_OFF 0x244 #define ATM_WB_MAGIC 0x30544257 // WBT0 @@ -147,7 +139,7 @@ typedef struct _atm_fatal_error_ctx #define EXO_FLAG_CAL0_WRITES_SYS BIT(6) #define EXO_FLAG_ENABLE_USB3 BIT(7) -#define EXO_FW_VER(mj, mn, rv) (((mj) << 24) | ((mn) << 16) | ((rv) << 8)) +#define EXO_FW_VER(mj, mn) (((mj) << 24) | ((mn) << 16)) void config_exosphere(launch_ctxt_t *ctxt, u32 warmboot_base) { @@ -164,56 +156,61 @@ void config_exosphere(launch_ctxt_t *ctxt, u32 warmboot_base) //! TODO: Replace current HOS version decoding (as it's bound to break in the future). - // Old exosphere target versioning. Use fuses for a simpler decoding. - if (ctxt->pkg1_id->fuses <= 3 || ctxt->pkg1_id->fuses >= 10) // 1.0.0 - 3.0.0, 8.1.0+. + // Old exosphere target versioning. + if (ctxt->pkg1_id->kb >= HOS_KB_VERSION_1210) // 12.1.0+ + exo_fw_no = ctxt->pkg1_id->kb + 4; + else if (ctxt->pkg1_id->fuses <= 3 || ctxt->pkg1_id->fuses >= 10) // 1.0.0 - 3.0.0, 8.1.0 - 12.0.3. exo_fw_no = ctxt->pkg1_id->fuses; else - exo_fw_no = ctxt->pkg1_id->fuses - 1; // 3.0.1 - 7.0.1, 8.0.x. + exo_fw_no = ctxt->pkg1_id->fuses - 1; // 3.0.1 - 7.0.1, 8.0.x. // Handle versions that change API and do not burn new fuse. - if (!memcmp(ctxt->pkg1_id->id, "20190314172056", 8) || // 8.0.x, same fuses with 7.0.1. - !memcmp(ctxt->pkg1_id->id, "20210129111626", 8) || // 12.0.0, same fuses with 11.0.0. - !memcmp(ctxt->pkg1_id->id, "20210805123730", 8) // 13.0.0, same fuses with 12.1.0. + if (!memcmp(ctxt->pkg1_id->id, "20190314", 8) || // 8.0.x, same fuses with 7.0.1. + !memcmp(ctxt->pkg1_id->id, "20210129", 8) // 12.0.0, same fuses with 11.0.0. ) exo_fw_no++; + // Set 12.1.0 specific revision. + if (ctxt->pkg1_id->kb == HOS_KB_VERSION_1210) + ctxt->exo_ctx.hos_revision = 1; + // Feed old exosphere target versioning to new. switch (exo_fw_no) { case 1 ... 4: case 6: - exo_fw_no = EXO_FW_VER(exo_fw_no, 0, 0); + exo_fw_no = EXO_FW_VER(exo_fw_no, 0); break; case 5: - exo_fw_no = EXO_FW_VER(5, ctxt->exo_ctx.hos_revision, 0); + exo_fw_no = EXO_FW_VER(5, ctxt->exo_ctx.hos_revision); break; case 7: - exo_fw_no = EXO_FW_VER(6, 2, 0); + exo_fw_no = EXO_FW_VER(6, 2); break; case 8 ... 9: - exo_fw_no = EXO_FW_VER(exo_fw_no - 1, 0, 0); + exo_fw_no = EXO_FW_VER(exo_fw_no - 1, 0); break; case 10: - exo_fw_no = EXO_FW_VER(8, 1, 0); + exo_fw_no = EXO_FW_VER(8, 1); break; case 11: - exo_fw_no = EXO_FW_VER(9, 0, 0); + exo_fw_no = EXO_FW_VER(9, 0); break; case 12: - exo_fw_no = EXO_FW_VER(9, 1, 0); + exo_fw_no = EXO_FW_VER(9, 1); break; - case 13 ... 16: //!TODO: Update on API changes. 16: 13.0.0. - exo_fw_no = EXO_FW_VER(exo_fw_no - 3, ctxt->exo_ctx.hos_revision, 0); + case 13 ... 23: //!TODO: Update on API changes. 23: 20.0.0. + exo_fw_no = EXO_FW_VER(exo_fw_no - 3, ctxt->exo_ctx.hos_revision); break; } // Parse exosphere.ini. if (!ctxt->stock) { - LIST_INIT(ini_sections); - if (ini_parse(&ini_sections, "exosphere.ini", false)) + LIST_INIT(ini_exo_sections); + if (ini_parse(&ini_exo_sections, "exosphere.ini", false)) { - LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sections, link) + LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_exo_sections, link) { // Only parse exosphere section. if (!(ini_sec->type == INI_CHOICE) || strcmp(ini_sec->name, "exosphere")) @@ -247,15 +244,12 @@ void config_exosphere(launch_ctxt_t *ctxt, u32 warmboot_base) } // Parse usb mtim settings. Avoid parsing if it's overridden. - if (ctxt->fss0_main_path && !ctxt->exo_ctx.usb3_force) + if (!ctxt->exo_ctx.usb3_force) { - char settings_path[256]; - strcpy(settings_path, ctxt->fss0_main_path); - strcat(settings_path, "config/system_settings.ini"); - LIST_INIT(sys_settings); - if (ini_parse(&ini_sections, settings_path, false)) + LIST_INIT(ini_sys_sections); + if (ini_parse(&ini_sys_sections, "atmosphere/config/system_settings.ini", false)) { - LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sections, link) + LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sys_sections, link) { // Only parse usb section. if (!(ini_sec->type == INI_CHOICE) || strcmp(ini_sec->name, "usb")) @@ -275,8 +269,8 @@ void config_exosphere(launch_ctxt_t *ctxt, u32 warmboot_base) } } - // To avoid problems, make private debug mode always on if not semi-stock. - if (!ctxt->stock || (emu_cfg.enabled && !h_cfg.emummc_force_disable)) + // Private debug mode always on for CFW mode. + if (!ctxt->stock) exo_flags |= EXO_FLAG_DBG_PRIV; // Enable user debug. @@ -319,33 +313,7 @@ void config_exosphere(launch_ctxt_t *ctxt, u32 warmboot_base) wb_cfg->fwno = exo_fw_no; // Set warmboot binary rsa modulus. - u8 *rsa_mod = (u8 *)malloc(512); - - sdmmc_storage_set_mmc_partition(&emmc_storage, EMMC_BOOT0); - - u32 sector; - u8 mod0, mod1; - - // Get the correct RSA modulus byte masks. - nx_emmc_get_autorcm_masks(&mod0, &mod1); - - // Iterate BCTs. - for (u32 i = 0; i < 4; i++) - { - sector = 1 + (32 * i); // 0x4000 bct + 0x200 offset. - sdmmc_storage_read(&emmc_storage, sector, 1, rsa_mod); - - // Check if 2nd byte of modulus is correct. - if (rsa_mod[0x11] != mod1) - continue; - - // Patch AutoRCM out. - rsa_mod[0x10] = mod0; - - break; - } - - memcpy((void *)(warmboot_base + 0x10), rsa_mod + 0x10, 0x100); + pkg1_warmboot_rsa_mod(warmboot_base); } if (emu_cfg.enabled && !h_cfg.emummc_force_disable) @@ -360,12 +328,10 @@ void config_exosphere(launch_ctxt_t *ctxt, u32 warmboot_base) else strcpy((char *)exo_cfg->emummc_cfg.file_cfg.path, emu_cfg.path); - if (emu_cfg.nintendo_path && !ctxt->stock) + if (!ctxt->stock && emu_cfg.nintendo_path && emu_cfg.nintendo_path[0]) strcpy((char *)exo_cfg->emummc_cfg.nintendo_path, emu_cfg.nintendo_path); - else if (ctxt->stock) - strcpy((char *)exo_cfg->emummc_cfg.nintendo_path, "Nintendo"); else - exo_cfg->emummc_cfg.nintendo_path[0] = 0; + strcpy((char *)exo_cfg->emummc_cfg.nintendo_path, "Nintendo"); } // Copy over exosphere fatal for Mariko. @@ -438,12 +404,12 @@ void secmon_exo_check_panic() // Check if mixed atmosphere sysmodules. if ((u32)rpt->title_id == HOS_PID_BOOT2) - WPRINTF("Is fss0 path correct?\n"); + WPRINTF("Mismatched Atmosphere files?\n"); // Save context to the SD card. char filepath[0x40]; f_mkdir("atmosphere/fatal_errors"); - strcpy(filepath, "/atmosphere/fatal_errors/report_"); + strcpy(filepath, "atmosphere/fatal_errors/report_"); itoa((u32)((u64)rpt->report_identifier >> 32), filepath + strlen(filepath), 16); itoa((u32)(rpt->report_identifier), filepath + strlen(filepath), 16); strcat(filepath, ".bin"); diff --git a/bootloader/hos/secmon_exo.h b/bootloader/hos/secmon_exo.h index 78f4192..a5b494b 100644 --- a/bootloader/hos/secmon_exo.h +++ b/bootloader/hos/secmon_exo.h @@ -17,7 +17,7 @@ #ifndef _SECMON_EXO_H_ #define _SECMON_EXO_H_ -#include +#include void config_exosphere(launch_ctxt_t *ctxt, u32 warmboot_base); void secmon_exo_check_panic(); diff --git a/bootloader/l4t/l4t.c b/bootloader/l4t/l4t.c new file mode 100644 index 0000000..5c84825 --- /dev/null +++ b/bootloader/l4t/l4t.c @@ -0,0 +1,1188 @@ +/* + * L4T Loader for Tegra X1 + * + * Copyright (c) 2020-2025 CTCaer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#include + +#include +#include + +#include "../hos/hos.h" +#include "../hos/pkg1.h" +#include "l4t.h" +#include "l4t_config.inl" + +/* + * API Revision info + * + * 0: Base. + * 1: SDMMC1 LA programming for SDMMC1 UHS DDR200. + * 2: Arachne Register Cell v1. + * 3: Arachne Register Cell v2. PTSA Rework support. + * 4: Arachne Register Cell v3. DRAM OPT and DDR200 changes. + * 5: Arachne Register Cell v4. DRAM FREQ and DDR200 changes. + * 6: Arachne Register Cell v5. Signal quality and performance changes. TZ param changes. + * 7: Arachne Register Cell v6. Decouple of rd/wr latencies. + */ + +#define L4T_LOADER_API_REV 7 +#define L4T_FIRMWARE_REV 0x37524556 // REV7. + +#ifdef DEBUG_UART_PORT + #include + #define UPRINTF(...) uart_printf(__VA_ARGS__) +#else + #define UPRINTF(...) +#endif + +#if CARVEOUT_NVDEC_TSEC_ENABLE && CARVEOUT_SECFW_ENABLE +#error "NVDEC and SECFW carveouts can't be used together!" +#endif + +#if CARVEOUT_NVDEC_TSEC_ENABLE + #define TZDRAM_SIZE_CFG SZ_8M +#else + #define TZDRAM_SIZE_CFG SZ_1M +#endif + +// TZDRAM addresses and sizes. +#define TZDRAM_SIZE TZDRAM_SIZE_CFG // Secure Element. +#define TZDRAM_BASE (0xFFFFFFFF - TZDRAM_SIZE + 1) // 0xFFF00000 or 0xFF800000. +#define TZDRAM_COLD_ENTRY (TZDRAM_BASE) +#define TZDRAM_WARM_ENTRY (TZDRAM_BASE + 0x200) +#define TZ_PARAM_SIZE SZ_4K +#define TZ_PARAM_BASE (0xFFFFFFFF - TZ_PARAM_SIZE + 1) // 0xFFFFF000. + +// Carveout sizes. +#define CARVEOUT_NVDEC_SIZE SZ_1M +#define CARVEOUT_TSEC_SIZE SZ_1M +#define CARVEOUT_SECFW_SIZE SZ_1M +#define CARVEOUT_GPUFW_SIZE SZ_256K +#if CARVEOUT_NVDEC_TSEC_ENABLE + #define CARVEOUT_GPUWPR_SIZE CARVEOUT_GPUWPR_SIZE_CFG +#else + #define CARVEOUT_GPUWPR_SIZE (SZ_512K + SZ_256K) +#endif + +#define SC7ENTRY_HDR_SIZE 0x400 + +// Always start 1MB below TZDRAM for Secure Firmware or NVDEC. +#define GEN_CARVEOUT_TOP (TZDRAM_BASE - SZ_1M) + +// NVDEC and SECFW bases. +#define NVDFW_BASE GEN_CARVEOUT_TOP // 0xFF700000. +#define SECFW_BASE GEN_CARVEOUT_TOP // 0xFFE00000. + +// Secure Elements addresses for T210. +#define SC7ENTRY_HDR_BASE (SECFW_BASE + 0) +#define SC7ENTRY_BASE (SECFW_BASE + SC7ENTRY_HDR_SIZE) // After header. +#define SC7EXIT_BASE (SECFW_BASE + SZ_64K) // 64KB after SECFW_BASE. +#define R2P_PAYLOAD_BASE (SECFW_BASE + SZ_256K) // 256KB after SECFW_BASE. +#define MTCTABLE_BASE (SECFW_BASE + SZ_512K) // 512KB after SECFW_BASE. +#define BPMPFW_BASE (SECFW_BASE + SZ_512K + SZ_256K) // 768KB after SECFW_BASE. +#define BPMPFW_ENTRYPOINT (BPMPFW_BASE + 0x100) // Used internally also. + +// Secure Elements addresses for T210B01. +#define BPMPFW_B01_BASE (SECFW_BASE) // !! DTS carveout-start must match !! +#define BPMPFW_B01_ENTRYPOINT (BPMPFW_B01_BASE + 0x40) // Used internally also. +#define BPMPFW_B01_HEAP_BASE (BPMPFW_B01_BASE + SZ_256K - SZ_1K) // 255KB after BPMPFW_B01_BASE. +#define BPMPFW_B01_EDTB_BASE (BPMPFW_B01_BASE + SZ_1M - 0) // Top BPMPFW carveout minus EMC DTB size. +#define BPMPFW_B01_ADTB_BASE (BPMPFW_B01_BASE + 0x26008) // Attached BPMP-FW DTB address. +#define SC7EXIT_B01_BASE (BPMPFW_B01_HEAP_BASE - SZ_4K) // 4KB before BPMP heap. + +// BPMP-FW defines. Offsets are 0xD8 below real main binary. +#define BPMPFW_B01_DTB_ADDR (BPMPFW_B01_BASE + 0x14) // u32. DTB address if not attached. +#define BPMPFW_B01_CC_INIT_OP (BPMPFW_B01_BASE + 0x17324) // u8. Initial table training OP. 0: OP_SWITCH, 1: OP_TRAIN, 2: OP_TRAIN_SWITCH. Default: OP_TRAIN. +#define BPMPFW_B01_LOGLEVEL (BPMPFW_B01_BASE + 0x2547C) // u32. Log level. Default 3. +#define BPMPFW_B01_LOGLEVEL (BPMPFW_B01_BASE + 0x2547C) // u32. Log level. Default 3. +#define BPMPFW_B01_CC_PT_TIME (BPMPFW_B01_BASE + 0x25644) // u32. Periodic training period (in ms). Default 100 ms. +#define BPMPFW_B01_CC_DEBUG (BPMPFW_B01_BASE + 0x257F8) // u32. EMC Clock Change debug mask. Default: 0x50000101. + +// BPMP-FW attached DTB defines. Can be generalized. +#define BPMPFW_B01_DTB_EMC_ENTRIES 4 +#define BPMPFW_B01_DTB_SERIAL_PORT_VAL (BPMPFW_B01_ADTB_BASE + 0x5B) // u8. DTB UART port offset. 0: Disabled. +#define BPMPFW_B01_DTB_SET_SERIAL_PORT(port) (*(u8 *)BPMPFW_B01_DTB_SERIAL_PORT_VAL = port) +#define BPMPFW_B01_DTB_EMC_TBL_OFF (BPMPFW_B01_ADTB_BASE + 0xA0) +#define BPMPFW_B01_DTB_EMC_TBL_SZ 0x1120 +#define BPMPFW_B01_DTB_EMC_NAME_VAL 0xA +#define BPMPFW_B01_DTB_EMC_ENABLE_OFF 0x20 +#define BPMPFW_B01_DTB_EMC_VALUES_OFF 0x4C +#define BPMPFW_B01_DTB_EMC_FREQ_VAL 0x8C +#define BPMPFW_B01_DTB_EMC_OPT_VAL 0xEDC +#define BPMPFW_B01_DTB_EMC_TBL_START(idx) (BPMPFW_B01_DTB_EMC_TBL_OFF + BPMPFW_B01_DTB_EMC_TBL_SZ * (idx)) +#define BPMPFW_B01_DTB_EMC_TBL_SET_VAL(idx, off, val) (*(u32 *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + (off)) = (val)) +#define BPMPFW_B01_DTB_EMC_TBL_SET_FREQ(idx, freq) (*(u32 *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + BPMPFW_B01_DTB_EMC_FREQ_VAL) = (freq)) +#define BPMPFW_B01_DTB_EMC_TBL_SET_OPTC(idx, opt) (*(u32 *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + BPMPFW_B01_DTB_EMC_OPT_VAL) = (opt)) +#define BPMPFW_B01_DTB_EMC_TBL_SET_NAME(idx, name) (strcpy((char *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + BPMPFW_B01_DTB_EMC_NAME_VAL), (name))) +#define BPMPFW_B01_DTB_EMC_TBL_ENABLE(idx) (*(char *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + BPMPFW_B01_DTB_EMC_ENABLE_OFF) = 'n') +#define BPMPFW_B01_DTB_EMC_TBL_OFFSET(idx) ((void *)(BPMPFW_B01_DTB_EMC_TBL_START(idx) + BPMPFW_B01_DTB_EMC_VALUES_OFF)) + +// MTC table defines for T210B01. +#define BPMPFW_B01_MTC_TABLE_BASE 0xA0000000 +#define BPMPFW_B01_MTC_FREQ_TABLE_SIZE 4300 +#define BPMPFW_B01_MTC_TABLE_SIZE (BPMPFW_B01_MTC_FREQ_TABLE_SIZE * 3) +#define BPMPFW_B01_MTC_TABLE(idx) (BPMPFW_B01_MTC_TABLE_BASE + BPMPFW_B01_MTC_TABLE_SIZE * (idx)) +#define BPMPFW_B01_MTC_TABLE_OFFSET(idx, fidx) ((void *)(BPMPFW_B01_MTC_TABLE(idx) + BPMPFW_B01_MTC_FREQ_TABLE_SIZE * (fidx))) + +// BL31 Enable IRAM based config. +#define BL31_IRAM_PARAMS 0x4D415249 // "IRAM". +#define BL31_EXTRA_FEATURES_ENABLE 0x52545845 // "EXTR". + +// BL31 Flags. +#define FLAGS_PMC_NON_SECURE BIT(0) +#define FLAGS_SC7_NO_BASE_RESTRICTION BIT(1) + +// BL31 config. +#define PARAM_EP 1 +#define PARAM_BL31 3 +#define PARAM_EP_SECURE 0 +#define PARAM_EP_NON_SECURE 1 +#define VERSION_1 1 +#define SPSR_EL2T BIT(3) + +// BL33 config. +#define BL33_LOAD_BASE 0xAA000000 // DTB is loaded at 0xA8000000, so 32MB above. +#define BL33_ENV_BASE (BL33_LOAD_BASE - SZ_256K) // Before BL33_LOAD_BASE. +#define BL33_ENV_MAGIC_OFFSET (BL33_ENV_BASE - 4) +#define BL33_ENV_MAGIC 0x33334C42 +#define BL33_DTB_OFFSET (BL33_LOAD_BASE + 0x10) // After code end. +#define BL33_DTB_BASE (BL33_LOAD_BASE + *(u32 *)BL33_DTB_OFFSET) +#define BL33_DTB_UART_STATUS 0x1C94 +#define BL33_DTB_UART_STS_OF 0x12C +#define BL33_DTB_STDOUT_PATH 0x3F34 +#define BL33_DTB_STDERR_PATH 0x3F54 +#define BL33_DTB_SET_UART_STATUS(port) (strcpy((char *)(BL33_DTB_BASE + BL33_DTB_UART_STATUS + (port - 1) * BL33_DTB_UART_STS_OF), "okay")) +#define BL33_DTB_SET_STDOUT_PATH(path) (strcpy((char *)(BL33_DTB_BASE + BL33_DTB_STDOUT_PATH), (path))) +#define BL33_DTB_SET_STDERR_PATH(path) (strcpy((char *)(BL33_DTB_BASE + BL33_DTB_STDERR_PATH), (path))) + +// Misc. +#define DTB_MAGIC 0xEDFE0DD0 // D00DFEED. +#define FALCON_DMA_PAGE_SIZE 0x100 +#define ACR_GSC3_ENABLE_MAGIC 0xC0EDBBCC +#define SOC_ID_T210 0x210 +#define SOC_ID_T210B01 0x214 +#define SKU_NX 0x83 +#define HDCP22 2 + +typedef struct _tsec_init_t { + u32 sku; + u32 hdcp; + u32 soc; +} tsec_init_t; + +typedef struct _param_header { + u8 type; // type of the structure. + u8 version; // version of this structure. + u16 size; // size of this structure in bytes. + u32 attr; // attributes: unused bits SBZ. +} param_header_t; + +typedef struct _aapcs64_params { + u64 x0; + u64 x1; + u64 x2; + u64 x3; + u64 x4; + u64 x5; + u64 x6; + u64 x7; +} aapcs64_params_t; + +typedef struct _entry_point_info { + param_header_t hdr; + u64 pc; + u32 spsr; + u32 align0; // Alignment to u64 for the above member. + aapcs64_params_t args; +} entry_point_info_t; + +typedef struct _image_info { + param_header_t hdr; + u64 image_base; // physical address of base of image. + u32 image_size; // bytes read from image file. + u32 image_max_size; +} image_info_t; + +typedef struct _bl_v1_params { + param_header_t hdr; + u64 bl31_image_info; + u64 bl32_ep_info; + u64 bl32_image_info; + u64 bl33_ep_info; + u64 bl33_image_info; +} bl31_v1_params_t; + +typedef struct _plat_params_from_bl2 { + // TZDRAM. + u64 tzdram_size; + u64 tzdram_base; + + s32 uart_id; // UART port ID. + s32 l2_ecc_parity_prot_dis; // L2 ECC parity protection disable flag. + u64 boot_profiler_shmem_base; // SHMEM base address for storing the boot logs. + + // SC7-Entry firmware. + u64 sc7entry_fw_size; + u64 sc7entry_fw_base; + + s32 enable_ccplex_lock_step; // Enable dual execution. + + // Enable below features. + s32 enable_extra_features; + + // MTC table. + u64 emc_table_size; + u64 emc_table_base; + + // Initial R2P payload. + u64 r2p_payload_size; + u64 r2p_payload_base; + + u64 flags; // Platform flags. +} bl31_plat_params_from_bl2_t; + +typedef struct _l4t_fw_t +{ + u32 addr; + char *name; +} l4t_fw_t; + +typedef struct _l4t_ctxt_t +{ + char *path; + + char *ram_oc_txt; + int ram_oc_freq; + int ram_oc_vdd2; + int ram_oc_vddq; + int ram_oc_opt; + + u32 serial_port; + u32 sld_type; + + u32 sc7entry_size; + + emc_table_t *mtc_table; + + bl31_v1_params_t bl31_v1_params; + bl31_plat_params_from_bl2_t bl31_plat_params; + entry_point_info_t bl33_ep_info; +} l4t_ctxt_t; + +#define DRAM_VDD2_OC_MIN_VOLTAGE 1050 +#define DRAM_VDD2_OC_MAX_VOLTAGE 1175 +#define DRAM_VDD2Q_OC_MAX_VOLTAGE 1237 +#define DRAM_VDDQ_OC_MIN_VOLTAGE 550 +#define DRAM_VDDQ_OC_MAX_VOLTAGE 650 +#define DRAM_T210B01_TBL_MAX_FREQ 1600000 + +#define NA 0 // Default to 0 for incorrect dram ids. + +//!TODO: Update on dram config changes. +static const u8 mtc_table_idx_t210b01[] = { +/* 00 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 */ + NA, NA, NA, 7, NA, 7, 7, NA, 0, 1, 2, 3, 0, 1, 2, 3, NA, 4, 5, 4, 8, 8, 8, 5, 4, 6, 6, 6, 5, 9, 9, 9, 10, 10, 10 +}; + +#undef NA + +static const l4t_fw_t l4t_fw[] = { + { TZDRAM_BASE, "bl31.bin" }, + { BL33_LOAD_BASE, "bl33.bin" }, + { SC7ENTRY_BASE, "sc7entry.bin" }, + { SC7EXIT_BASE, "sc7exit.bin" }, + { SC7EXIT_B01_BASE, "sc7exit_b01.bin" }, //!TODO: Update on fuse burns. + { BPMPFW_BASE, "bpmpfw.bin" }, + { BPMPFW_B01_BASE, "bpmpfw_b01.bin" }, + { BPMPFW_B01_MTC_TABLE_BASE, "mtc_tbl_b01.bin" }, +}; + +enum { + BL31_FW = 0, + BL33_FW = 1, + SC7ENTRY_FW = 2, + SC7EXIT_FW = 3, + SC7EXIT_B01_FW = 4, + BPMPFW_FW = 5, + BPMPFW_B01_FW = 6, + BPMPFW_B01_MTC_TBL = 7 +}; + +static void _l4t_crit_error(const char *text, bool needs_update) +{ + gfx_con.mute = false; + gfx_printf("%kL4T Error: %s!%sFailed to launch L4T!\n%k", + TXT_CLR_ERROR, text, needs_update ? "\nUpdate bootloader folder!\n\n" : "\n\n", TXT_CLR_DEFAULT); +} + +char *sd_path; +u32 sd_path_len; +static int _l4t_sd_load(u32 idx) +{ + FIL fp; + void *load_address = (void *)l4t_fw[idx].addr; + + if (idx == SC7EXIT_B01_FW) + load_address -= sizeof(u32); + + strcpy(sd_path + sd_path_len, l4t_fw[idx].name); + + if (f_open(&fp, sd_path, FA_READ) != FR_OK) + return 0; + + u32 size = f_size(&fp); + if (f_read(&fp, load_address, size, NULL) != FR_OK) + size = 0; + + f_close(&fp); + + u32 rev = *(u32 *)(load_address + size - sizeof(u32)); + if (idx >= SC7ENTRY_FW && rev != L4T_FIRMWARE_REV) + return 0; + + return size; +} + +static void _l4t_sdram_lp0_save_params(bool t210b01) +{ + struct tegra_pmc_regs *pmc = (struct tegra_pmc_regs *)PMC_BASE; + +#define _REG_S(base, off) *(u32 *)((base) + (off)) +#define MC_S(off) _REG_S(MC_BASE, off) + +#define pack(src, src_bits, dst, dst_bits) { \ + u32 mask = 0xffffffff >> (31 - ((1 ? src_bits) - (0 ? src_bits))); \ + dst &= ~(mask << (0 ? dst_bits)); \ + dst |= ((src >> (0 ? src_bits)) & mask) << (0 ? dst_bits); } + +#define s(param, src_bits, pmcreg, dst_bits) \ + pack(MC_S(param), src_bits, pmc->pmcreg, dst_bits) + +// 32 bits version of s macro. +#define s32(param, pmcreg) pmc->pmcreg = MC_S(param) + + // Only save changed carveout registers into PMC for SC7 Exit. + + // VPR. + s(MC_VIDEO_PROTECT_BOM, 31:20, secure_scratch52, 26:15); + s(MC_VIDEO_PROTECT_SIZE_MB, 11:0, secure_scratch53, 11:0); + if (!t210b01) { + s(MC_VIDEO_PROTECT_REG_CTRL, 1:0, secure_scratch13, 31:30); + } else { + s(MC_VIDEO_PROTECT_REG_CTRL, 1:0, secure_scratch14, 31:30); + } + + // TZDRAM. + s(MC_SEC_CARVEOUT_BOM, 31:20, secure_scratch53, 23:12); + s(MC_SEC_CARVEOUT_SIZE_MB, 11:0, secure_scratch54, 11:0); + if (!t210b01) { + s(MC_SEC_CARVEOUT_REG_CTRL, 0:0, secure_scratch18, 30:30); + } else { + s(MC_SEC_CARVEOUT_REG_CTRL, 0:0, secure_scratch19, 29:29); + } + + // NVDEC or SECFW. + s(MC_SECURITY_CARVEOUT1_BOM, 31:17, secure_scratch50, 29:15); + s(MC_SECURITY_CARVEOUT1_SIZE_128KB, 11:0, secure_scratch57, 11:0); + s32(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0, secure_scratch59); + s32(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1, secure_scratch60); + s32(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2, secure_scratch61); + s32(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3, secure_scratch62); + if (!t210b01) + { + s(MC_SECURITY_CARVEOUT1_CFG0, 2:0, secure_scratch56, 27:25); + s(MC_SECURITY_CARVEOUT1_CFG0, 6:3, secure_scratch41, 28:25); + s(MC_SECURITY_CARVEOUT1_CFG0, 13:7, secure_scratch42, 31:25); + s(MC_SECURITY_CARVEOUT1_CFG0, 17:14, secure_scratch43, 28:25); + s(MC_SECURITY_CARVEOUT1_CFG0, 21:18, secure_scratch44, 28:25); + s(MC_SECURITY_CARVEOUT1_CFG0, 25:22, secure_scratch56, 31:28); + s(MC_SECURITY_CARVEOUT1_CFG0, 26:26, secure_scratch57, 24:24); + } + else + { + s(MC_SECURITY_CARVEOUT1_CFG0, 1:0, secure_scratch56, 31:30); + s(MC_SECURITY_CARVEOUT1_CFG0, 2:2, secure_scratch57, 24:24); + s(MC_SECURITY_CARVEOUT1_CFG0, 6:3, secure_scratch42, 28:25); + s(MC_SECURITY_CARVEOUT1_CFG0, 10:7, secure_scratch43, 28:25); + s(MC_SECURITY_CARVEOUT1_CFG0, 13:11, secure_scratch42, 31:29); + s(MC_SECURITY_CARVEOUT1_CFG0, 17:14, secure_scratch44, 28:25); + s(MC_SECURITY_CARVEOUT1_CFG0, 21:18, secure_scratch47, 25:22); + s(MC_SECURITY_CARVEOUT1_CFG0, 26:22, secure_scratch57, 29:25); + } + + // GPU FW. + s(MC_SECURITY_CARVEOUT2_BOM, 31:17, secure_scratch51, 29:15); + s(MC_SECURITY_CARVEOUT2_SIZE_128KB, 11:0, secure_scratch56, 23:12); + if (!t210b01) + { + s(MC_SECURITY_CARVEOUT2_CFG0, 2:0, secure_scratch55, 27:25); + s(MC_SECURITY_CARVEOUT2_CFG0, 6:3, secure_scratch19, 31:28); + s(MC_SECURITY_CARVEOUT2_CFG0, 10:7, secure_scratch20, 31:28); + s(MC_SECURITY_CARVEOUT2_CFG0, 13:11, secure_scratch41, 31:29); + s(MC_SECURITY_CARVEOUT2_CFG0, 17:14, secure_scratch39, 30:27); + s(MC_SECURITY_CARVEOUT2_CFG0, 21:18, secure_scratch40, 30:27); + s(MC_SECURITY_CARVEOUT2_CFG0, 25:22, secure_scratch55, 31:28); + s(MC_SECURITY_CARVEOUT2_CFG0, 26:26, secure_scratch56, 24:24); + } + else + { + s(MC_SECURITY_CARVEOUT2_CFG0, 1:0, secure_scratch55, 31:30); + s(MC_SECURITY_CARVEOUT2_CFG0, 2:2, secure_scratch56, 24:24); + s(MC_SECURITY_CARVEOUT2_CFG0, 6:3, secure_scratch20, 31:28); + s(MC_SECURITY_CARVEOUT2_CFG0, 10:7, secure_scratch39, 30:27); + s(MC_SECURITY_CARVEOUT2_CFG0, 13:11, secure_scratch41, 31:29); + s(MC_SECURITY_CARVEOUT2_CFG0, 17:14, secure_scratch40, 30:27); + s(MC_SECURITY_CARVEOUT2_CFG0, 21:18, secure_scratch41, 28:25); + s(MC_SECURITY_CARVEOUT2_CFG0, 26:22, secure_scratch56, 29:25); + } + + // GPU WPR. + s(MC_SECURITY_CARVEOUT3_BOM, 31:17, secure_scratch50, 14:0); + s(MC_SECURITY_CARVEOUT3_SIZE_128KB, 11:0, secure_scratch56, 11:0); + s32(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2, secure_scratch71); + s32(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4, secure_scratch73); + if (!t210b01) + { + s(MC_SECURITY_CARVEOUT3_CFG0, 2:0, secure_scratch57, 27:25); + s(MC_SECURITY_CARVEOUT3_CFG0, 10:3, secure_scratch47, 29:22); + s(MC_SECURITY_CARVEOUT3_CFG0, 13:11, secure_scratch43, 31:29); + s(MC_SECURITY_CARVEOUT3_CFG0, 21:14, secure_scratch48, 29:22); + s(MC_SECURITY_CARVEOUT3_CFG0, 25:22, secure_scratch57, 31:28); + s(MC_SECURITY_CARVEOUT3_CFG0, 26:26, secure_scratch58, 0:0); + } + else + { + s(MC_SECURITY_CARVEOUT3_CFG0, 1:0, secure_scratch57, 31:30); + s(MC_SECURITY_CARVEOUT3_CFG0, 2:2, secure_scratch58, 0:0); + s(MC_SECURITY_CARVEOUT3_CFG0, 6:3, secure_scratch47, 29:26); + s(MC_SECURITY_CARVEOUT3_CFG0, 10:7, secure_scratch48, 25:22); + s(MC_SECURITY_CARVEOUT3_CFG0, 13:11, secure_scratch43, 31:29); + s(MC_SECURITY_CARVEOUT3_CFG0, 17:14, secure_scratch48, 29:26); + s(MC_SECURITY_CARVEOUT3_CFG0, 21:18, secure_scratch52, 30:27); + s(MC_SECURITY_CARVEOUT3_CFG0, 26:22, secure_scratch58, 5:1); + } + + // TSECA. + s(MC_SECURITY_CARVEOUT4_BOM, 31:17, secure_scratch51, 14:0); + s(MC_SECURITY_CARVEOUT4_SIZE_128KB, 11:0, secure_scratch55, 23:12); + s(MC_SECURITY_CARVEOUT4_CFG0, 26:0, secure_scratch39, 26:0); + + // TSECB. + s(MC_SECURITY_CARVEOUT5_BOM, 31:17, secure_scratch52, 14:0); + s(MC_SECURITY_CARVEOUT5_SIZE_128KB, 11:0, secure_scratch57, 23:12); + s(MC_SECURITY_CARVEOUT5_CFG0, 26:0, secure_scratch40, 26:0); +} + +static void _l4t_mc_config_carveout(bool t210b01) +{ + // Disabled VPR carveout. DT decides if enabled or not. + MC(MC_VIDEO_PROTECT_BOM) = 0xFFF00000; + MC(MC_VIDEO_PROTECT_SIZE_MB) = 0; + MC(MC_VIDEO_PROTECT_REG_CTRL) = VPR_CTRL_TZ_SECURE | VPR_CTRL_LOCKED; + + // Temporarily disable TZDRAM carveout. For launching coldboot TZ. + MC(MC_SEC_CARVEOUT_BOM) = 0xFFF00000; + MC(MC_SEC_CARVEOUT_SIZE_MB) = 0; + MC(MC_SEC_CARVEOUT_REG_CTRL) = 0; + + // Print real one, not temp disabled. + UPRINTF("TZD: TZDRAM Carveout: %08X - %08X\n", TZDRAM_BASE, TZDRAM_BASE - 1 + TZDRAM_SIZE); + + // Configure generalized security carveouts. + u32 carveout_base = GEN_CARVEOUT_TOP; + +#if CARVEOUT_NVDEC_TSEC_ENABLE + + // Set NVDEC keyslot sticky bits. + clock_enable_nvdec(); + clock_enable_nvjpg(); + NVDEC(NVDEC_SA_KEYSLOT_GLOBAL_RW) = 0xFFFF; // Read disable. + NVDEC(NVDEC_SA_KEYSLOT_TZ) = 0xFFFFFFFF; // TZ enable. + NVDEC(NVDEC_SA_KEYSLOT_FALCON) = 0; // Falcon disable. + NVDEC(NVDEC_SA_KEYSLOT_OTF) = 0; // OTF disable. + NVDEC(NVDEC_VPR_ALL_OTF_GOTO_VPR) = 1; // Enable. + clock_disable_nvjpg(); + clock_disable_nvdec(); + + // Set NVDEC carveout. Only for NVDEC bl/prod. + carveout_base -= ALIGN(CARVEOUT_NVDEC_SIZE, SZ_1M); + MC(MC_SECURITY_CARVEOUT1_BOM) = carveout_base; + MC(MC_SECURITY_CARVEOUT1_BOM_HI) = 0; + MC(MC_SECURITY_CARVEOUT1_SIZE_128KB) = CARVEOUT_NVDEC_SIZE / SZ_128K; + MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0) = 0; + MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1) = 0; + MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2) = SEC_CARVEOUT_CA2_R_TSEC | SEC_CARVEOUT_CA2_W_TSEC; + MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3) = SEC_CARVEOUT_CA3_R_NVDEC | SEC_CARVEOUT_CA3_W_NVDEC; + MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4) = 0; + MC(MC_SECURITY_CARVEOUT1_CFG0) = SEC_CARVEOUT_CFG_LOCKED | + SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY | + SEC_CARVEOUT_CFG_RD_SEC | + SEC_CARVEOUT_CFG_RD_FALCON_LS | + SEC_CARVEOUT_CFG_RD_FALCON_HS | + SEC_CARVEOUT_CFG_WR_FALCON_HS | + SEC_CARVEOUT_CFG_APERTURE_ID(1) | + SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH; + UPRINTF("GSC1: NVDEC Carveout: %08X - %08X\n", + MC(MC_SECURITY_CARVEOUT1_BOM), MC(MC_SECURITY_CARVEOUT1_BOM) + MC(MC_SECURITY_CARVEOUT1_SIZE_128KB) * SZ_128K); + +#elif CARVEOUT_SECFW_ENABLE + + // Flush data to ram. + bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, false); + + // Set SC7-Entry/SC7-Exit/R2P/MTC Table or SC7-Exit/BPMP-FW carveout. Only BPMP, CCPLEX and AHB have R/W access. + MC(MC_SECURITY_CARVEOUT1_BOM) = carveout_base; + MC(MC_SECURITY_CARVEOUT1_BOM_HI) = 0; + MC(MC_SECURITY_CARVEOUT1_SIZE_128KB) = CARVEOUT_SECFW_SIZE / SZ_128K; + MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS0) = SEC_CARVEOUT_CA0_R_BPMP_C | + SEC_CARVEOUT_CA0_R_PPCSAHBSLV; + MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS1) = SEC_CARVEOUT_CA1_W_BPMP_C | + SEC_CARVEOUT_CA1_R_CCPLEX_C | + SEC_CARVEOUT_CA1_R_CCPLEXLP_C | + SEC_CARVEOUT_CA1_W_CCPLEX_C | + SEC_CARVEOUT_CA1_W_CCPLEXLP_C | + SEC_CARVEOUT_CA1_W_PPCSAHBSLV; + MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS2) = 0; + MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS3) = 0; + MC(MC_SECURITY_CARVEOUT1_CLIENT_ACCESS4) = 0; + MC(MC_SECURITY_CARVEOUT1_CFG0) = SEC_CARVEOUT_CFG_RD_NS | + SEC_CARVEOUT_CFG_RD_SEC | + SEC_CARVEOUT_CFG_WR_NS | + SEC_CARVEOUT_CFG_WR_SEC | + SEC_CARVEOUT_CFG_LOCKED; + UPRINTF("GSC1: SECFW Carveout: %08X - %08X\n", + MC(MC_SECURITY_CARVEOUT1_BOM), MC(MC_SECURITY_CARVEOUT1_BOM) + MC(MC_SECURITY_CARVEOUT1_SIZE_128KB) * SZ_128K); + +#endif + + // Set GPU FW WPR carveout. Same value is used for GPU WPR carveout calculation if not full TOS. + carveout_base -= ALIGN(CARVEOUT_GPUFW_SIZE, SZ_1M); + + // Sanitize it and enable GSC3 for ACR. + memset((void *)carveout_base, 0, CARVEOUT_GPUFW_SIZE); + *(u32 *)(carveout_base + CARVEOUT_GPUFW_SIZE - sizeof(u32)) = ACR_GSC3_ENABLE_MAGIC; + + tsec_init_t *tsec_init = (tsec_init_t *)(carveout_base + CARVEOUT_GPUFW_SIZE - FALCON_DMA_PAGE_SIZE); + + // Set TSEC init info. + tsec_init->sku = SKU_NX; + tsec_init->hdcp = HDCP22; + tsec_init->soc = t210b01 ? SOC_ID_T210B01 : SOC_ID_T210; + + // Flush data to ram. + bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, false); + + // Set carveout config. + MC(MC_SECURITY_CARVEOUT2_BOM) = carveout_base; + MC(MC_SECURITY_CARVEOUT2_BOM_HI) = 0; + MC(MC_SECURITY_CARVEOUT2_SIZE_128KB) = CARVEOUT_GPUFW_SIZE / SZ_128K; + MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS0) = 0; + MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS1) = 0; + MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS2) = SEC_CARVEOUT_CA2_R_GPU | SEC_CARVEOUT_CA2_W_GPU | SEC_CARVEOUT_CA2_R_TSEC; + MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS3) = 0; + MC(MC_SECURITY_CARVEOUT2_CLIENT_ACCESS4) = SEC_CARVEOUT_CA4_R_GPU2 | SEC_CARVEOUT_CA4_W_GPU2; + MC(MC_SECURITY_CARVEOUT2_CFG0) = SEC_CARVEOUT_CFG_LOCKED | + SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY | + SEC_CARVEOUT_CFG_RD_NS | + SEC_CARVEOUT_CFG_RD_SEC | + SEC_CARVEOUT_CFG_RD_FALCON_LS | + SEC_CARVEOUT_CFG_RD_FALCON_HS | + SEC_CARVEOUT_CFG_WR_FALCON_LS | + SEC_CARVEOUT_CFG_WR_FALCON_HS | + SEC_CARVEOUT_CFG_APERTURE_ID(2) | + SEC_CARVEOUT_CFG_SEND_CFG_TO_GPU | + SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH; // SEC_CARVEOUT_CFG_IS_WPR is set from GPU. + UPRINTF("GSC2: GPUFW Carveout: %08X - %08X\n", + MC(MC_SECURITY_CARVEOUT2_BOM), MC(MC_SECURITY_CARVEOUT2_BOM) + MC(MC_SECURITY_CARVEOUT2_SIZE_128KB) * SZ_128K); + + // Set GPU WPR carveout. +#if CARVEOUT_NVDEC_TSEC_ENABLE + carveout_base -= ALIGN(CARVEOUT_GPUWPR_SIZE, SZ_1M); + MC(MC_SECURITY_CARVEOUT3_BOM) = carveout_base; +#else + MC(MC_SECURITY_CARVEOUT3_BOM) = carveout_base + CARVEOUT_GPUFW_SIZE; +#endif + MC(MC_SECURITY_CARVEOUT3_BOM_HI) = 0x0; + MC(MC_SECURITY_CARVEOUT3_SIZE_128KB) = CARVEOUT_GPUWPR_SIZE / SZ_128K; + MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS0) = 0; + MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS1) = 0; + MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS2) = 0; // HOS: SEC_CARVEOUT_CA2_R_GPU | SEC_CARVEOUT_CA2_W_GPU + MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS3) = 0; + MC(MC_SECURITY_CARVEOUT3_CLIENT_ACCESS4) = 0; // HOS: SEC_CARVEOUT_CA4_R_GPU2 | SEC_CARVEOUT_CA4_W_GPU2 + MC(MC_SECURITY_CARVEOUT3_CFG0) = SEC_CARVEOUT_CFG_LOCKED | + SEC_CARVEOUT_CFG_UNTRANSLATED_ONLY | + SEC_CARVEOUT_CFG_RD_NS | + SEC_CARVEOUT_CFG_RD_SEC | + SEC_CARVEOUT_CFG_RD_FALCON_LS | + SEC_CARVEOUT_CFG_RD_FALCON_HS | + SEC_CARVEOUT_CFG_WR_FALCON_LS | + SEC_CARVEOUT_CFG_WR_FALCON_HS | + SEC_CARVEOUT_CFG_APERTURE_ID(3) | + SEC_CARVEOUT_CFG_SEND_CFG_TO_GPU | + SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH; // SEC_CARVEOUT_CFG_IS_WPR is set from GPU. + UPRINTF("GSC3: GPUW2 Carveout: %08X - %08X\n", + MC(MC_SECURITY_CARVEOUT3_BOM), MC(MC_SECURITY_CARVEOUT3_BOM) + MC(MC_SECURITY_CARVEOUT3_SIZE_128KB) * SZ_128K); + + /* + * Set TSECA/B carveout. Only for NVDEC bl/prod and TSEC. + * + * Otherwise disabled. + * + * With HOS SC7-Exit fw, it gets set to disallow RAM access for BPMP. But TZ can change it. + * We lock the carveout and save it in restore scratch registers so SC7-Exit can't touch it. + */ + carveout_base -= CARVEOUT_NVDEC_TSEC_ENABLE ? ALIGN(CARVEOUT_TSEC_SIZE, SZ_1M) : 0; + MC(MC_SECURITY_CARVEOUT4_BOM) = CARVEOUT_NVDEC_TSEC_ENABLE ? carveout_base : 0; + MC(MC_SECURITY_CARVEOUT4_SIZE_128KB) = CARVEOUT_NVDEC_TSEC_ENABLE ? CARVEOUT_TSEC_SIZE / SZ_128K : 0; + MC(MC_SECURITY_CARVEOUT4_CFG0) = SEC_CARVEOUT_CFG_LOCKED | + SEC_CARVEOUT_CFG_RD_FALCON_HS | + SEC_CARVEOUT_CFG_WR_FALCON_HS | + SEC_CARVEOUT_CFG_APERTURE_ID(4) | + SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH; + + UPRINTF("GSC4: TSEC1 Carveout: %08X - %08X\n", + MC(MC_SECURITY_CARVEOUT4_BOM), MC(MC_SECURITY_CARVEOUT4_BOM) + MC(MC_SECURITY_CARVEOUT4_SIZE_128KB) * SZ_128K); + + // Set TSECA carveout. Only for NVDEC bl/prod and TSEC. Otherwise disabled. + carveout_base -= CARVEOUT_NVDEC_TSEC_ENABLE ? ALIGN(CARVEOUT_TSEC_SIZE, SZ_1M) : 0; + MC(MC_SECURITY_CARVEOUT5_BOM) = CARVEOUT_NVDEC_TSEC_ENABLE ? carveout_base : 0; + MC(MC_SECURITY_CARVEOUT5_SIZE_128KB) = CARVEOUT_NVDEC_TSEC_ENABLE ? CARVEOUT_TSEC_SIZE / SZ_128K : 0; + MC(MC_SECURITY_CARVEOUT5_CFG0) = SEC_CARVEOUT_CFG_LOCKED | + SEC_CARVEOUT_CFG_RD_FALCON_HS | + SEC_CARVEOUT_CFG_WR_FALCON_HS | + SEC_CARVEOUT_CFG_APERTURE_ID(5) | + SEC_CARVEOUT_CFG_FORCE_APERTURE_ID_MATCH; + UPRINTF("GSC5: TSEC2 Carveout: %08X - %08X\n", + MC(MC_SECURITY_CARVEOUT5_BOM), MC(MC_SECURITY_CARVEOUT5_BOM) + MC(MC_SECURITY_CARVEOUT5_SIZE_128KB) * SZ_128K); + + UPRINTF("DRAM Bank 0 TOP: %08X\n", carveout_base); + + // Save carveouts to lp0 pmc registers. + _l4t_sdram_lp0_save_params(t210b01); +} + +static void _l4t_late_hw_config(bool t210b01) +{ + // Reset System Counters. + for (u32 i = 0; i < SYSCTR0_COUNTERS; i += sizeof(u32)) + SYSCTR0(SYSCTR0_COUNTERS_BASE + i) = 0; + + /* + * PMIC config scratch register + * + * bit00: active cluster slow + * bit01: Set: max77621/max77812. Unset: OVR/OVR2. + * bit02-07: unused + * bit08-15: pmic cpu i2c address + * bit16:23: pmic cpu i2c en reg + * bit24:31: pmic cpu i2c en val + */ + PMC(APBDEV_PMC_SCRATCH201) = BIT(1); + + // Clear PLLM override for SC7. + PMC(APBDEV_PMC_PLLP_WB0_OVERRIDE) &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE_ENABLE; + + // Set spare reg to 0xE0000 and clear everything else. + if (t210b01 && (SYSREG(AHB_AHB_SPARE_REG) & 0xE0000000) != 0xE0000000) + SYSREG(AHB_AHB_SPARE_REG) = 0xE0000 << 12; + + // HDA loopback disable on prod. + PMC(APBDEV_PMC_STICKY_BITS) = PMC_STICKY_BITS_HDA_LPBK_DIS; + + // Clear any MC error. + MC(MC_INTSTATUS) = MC(MC_INTSTATUS); + + +#if LOCK_PMC_REGISTERS + // Lock LP0 parameters and misc secure registers. Always happens on warmboot. + #if CARVEOUT_NVDEC_TSEC_ENABLE + pmc_scratch_lock(PMC_SEC_LOCK_CARVEOUTS_L4T | PMC_SEC_LOCK_SE_SRK); + #else + pmc_scratch_lock(PMC_SEC_LOCK_LP0_PARAMS | PMC_SEC_LOCK_MISC | PMC_SEC_LOCK_SE_SRK); + #endif + + // Lock SE2 SRK and misc secure regs. Also lock writes on normal LP0 scratch regs. + if (t210b01) + pmc_scratch_lock(PMC_SEC_LOCK_MISC_B01 | PMC_SEC_LOCK_SE2_SRK_B01 | PMC_SEC_LOCK_LP0_PARAMS_B01); +#endif +} + +static void _l4t_bpmpfw_b01_config(l4t_ctxt_t *ctxt) +{ + char *ram_oc_txt = ctxt->ram_oc_txt; + u32 ram_oc_freq = ctxt->ram_oc_freq; + u32 ram_oc_opt = ctxt->ram_oc_opt; + u32 ram_id = fuse_read_dramid(true); + + // Set default parameters. + *(u32 *)BPMPFW_B01_DTB_ADDR = 0; + *(u8 *)BPMPFW_B01_CC_INIT_OP = OP_TRAIN; + *(u32 *)BPMPFW_B01_CC_PT_TIME = 100; + +#if DEBUG_LOG_BPMPFW + // Set default debug parameters. + *(u32 *)BPMPFW_B01_LOGLEVEL = 3; + *(u32 *)BPMPFW_B01_CC_DEBUG = 0x50000101; + + // Set serial debug port. + if (*(u32 *)BPMPFW_B01_ADTB_BASE == DTB_MAGIC) + BPMPFW_B01_DTB_SET_SERIAL_PORT(ctxt->serial_port); +#endif + + // Set and copy MTC tables. + u32 mtc_idx = mtc_table_idx_t210b01[ram_id]; + for (u32 i = 0; i < 3; i++) + { + minerva_sdmmc_la_program(BPMPFW_B01_MTC_TABLE_OFFSET(mtc_idx, i), true); + memcpy(BPMPFW_B01_DTB_EMC_TBL_OFFSET(i), BPMPFW_B01_MTC_TABLE_OFFSET(mtc_idx, i), BPMPFW_B01_MTC_FREQ_TABLE_SIZE); + } + + // Always use Arachne Register Cell (ARC) for setting rated frequencies if no ram_oc is defined. + if (!ram_oc_freq) + { + if (ram_id >= LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AM_MGCJ && + ram_id <= LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTE) + { + ram_oc_txt = "1866000"; + ram_oc_freq = 1866000; + } + else + { + ram_oc_txt = "2133000"; + ram_oc_freq = 2133000; + } + } + + // Set DRAM voltage. + if (ctxt->ram_oc_vdd2) + max7762x_regulator_set_voltage(REGULATOR_SD1, ctxt->ram_oc_vdd2 * 1000); + if (ctxt->ram_oc_vddq) + max7762x_regulator_set_voltage(REGULATOR_RAM0, ctxt->ram_oc_vddq * 1000); + + // A frequency of lower or equal with stock max will skip ARC. + if (ram_oc_freq > DRAM_T210B01_TBL_MAX_FREQ) + { + // Final table. + const u32 tbl_idx = BPMPFW_B01_DTB_EMC_ENTRIES - 1; + + // Copy table and prep it for Arachne. + memcpy(BPMPFW_B01_DTB_EMC_TBL_OFFSET(tbl_idx), BPMPFW_B01_MTC_TABLE_OFFSET(mtc_idx, 2), BPMPFW_B01_MTC_FREQ_TABLE_SIZE); + + BPMPFW_B01_DTB_EMC_TBL_SET_NAME(tbl_idx, ram_oc_txt); + BPMPFW_B01_DTB_EMC_TBL_SET_FREQ(tbl_idx, ram_oc_freq); + BPMPFW_B01_DTB_EMC_TBL_SET_OPTC(tbl_idx, ram_oc_opt); + + // Enable table. + BPMPFW_B01_DTB_EMC_TBL_ENABLE(tbl_idx); + + UPRINTF("RAM Frequency set to: %d KHz. Voltage: %d mV\n", ram_oc_freq, ctxt->ram_oc_vdd2); + } + + // Save BPMP-FW entrypoint for TZ. + PMC(APBDEV_PMC_SCRATCH39) = BPMPFW_B01_ENTRYPOINT; + PMC(APBDEV_PMC_SCRATCH_WRITE_DISABLE1) |= BIT(15); +} + +static int _l4t_sc7_exit_config(bool t210b01) +{ + if (!t210b01) + { + // Apply Nintendo Switch (2017) RSA modulus to SC7-Exit firmware. + emmc_initialize(false); + pkg1_warmboot_rsa_mod(SC7EXIT_BASE); + emmc_end(); + + // Set SC7-Exit firmware address for bootrom to find. + PMC(APBDEV_PMC_SCRATCH1) = SC7EXIT_BASE; + } + else + { + launch_ctxt_t hos_ctxt = {0}; + u32 fw_fuses = *(u32 *)(SC7EXIT_B01_BASE - sizeof(u32)); // Fuses count in front of actual firmware. + + // Get latest SC7-Exit if needed and setup PA id. + if (!pkg1_warmboot_config(&hos_ctxt, 0, fw_fuses, 0)) + { + gfx_con.mute = false; + gfx_wputs("\nFailed to match warmboot with fuses!\nIf you continue, sleep wont work!"); + + gfx_puts("\nPress POWER to continue.\nPress VOL to go to the menu.\n"); + + if (!(btn_wait() & BTN_POWER)) + return 0; + } + + // Copy loaded warmboot fw to address if from storage. + if (hos_ctxt.warmboot) + memcpy((void *)SC7EXIT_B01_BASE, hos_ctxt.warmboot, hos_ctxt.warmboot_size); + + // Set SC7-Exit firmware address for bootrom to find. + PMC(APBDEV_PMC_SECURE_SCRATCH119) = SC7EXIT_B01_BASE; + PMC(APBDEV_PMC_SEC_DISABLE8) |= BIT(30); + } + + return 1; +} + +static void _l4t_bl33_cfg_set_key(char *env, const char *key, const char *val) +{ + strcat(env, key); + strcat(env, "="); + strcat(env, val); + strcat(env, "\n"); +} + +static void _l4t_set_config(l4t_ctxt_t *ctxt, const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b01) +{ + char *bl33_env = (char *)BL33_ENV_BASE; + bl33_env[0] = '\0'; + char val[4] = {0}; + + // Set default SLD type. + ctxt->sld_type = BL_MAGIC_L4TLDR_SLD; + + // Parse ini section and prepare BL33 env. + LIST_FOREACH_ENTRY(ini_kv_t, kv, &ini_sec->kvs, link) + { + if (!strcmp("boot_prefixes", kv->key)) + ctxt->path = kv->val; + else if (!strcmp("ram_oc", kv->key)) + { + ctxt->ram_oc_txt = kv->val; + ctxt->ram_oc_freq = atoi(kv->val); + } + else if (!strcmp("ram_oc_vdd2", kv->key)) + { + ctxt->ram_oc_vdd2 = atoi(kv->val); + + if (t210b01 && ctxt->ram_oc_vdd2 > DRAM_VDD2_OC_MAX_VOLTAGE) + ctxt->ram_oc_vdd2 = DRAM_VDD2_OC_MAX_VOLTAGE; + else if (!t210b01 && ctxt->ram_oc_vdd2 > DRAM_VDD2Q_OC_MAX_VOLTAGE) + ctxt->ram_oc_vdd2 = DRAM_VDD2Q_OC_MAX_VOLTAGE; + else if (ctxt->ram_oc_vdd2 < DRAM_VDD2_OC_MIN_VOLTAGE) + ctxt->ram_oc_vdd2 = DRAM_VDD2_OC_MIN_VOLTAGE; + } + else if (!strcmp("ram_oc_vddq", kv->key)) + { + ctxt->ram_oc_vddq = atoi(kv->val); + if (ctxt->ram_oc_vddq > DRAM_VDDQ_OC_MAX_VOLTAGE) + ctxt->ram_oc_vddq = DRAM_VDDQ_OC_MAX_VOLTAGE; + else if (ctxt->ram_oc_vddq < DRAM_VDDQ_OC_MIN_VOLTAGE) + ctxt->ram_oc_vddq = 0; + } + else if (!strcmp("ram_oc_opt", kv->key)) + ctxt->ram_oc_opt = atoi(kv->val); + else if (!strcmp("uart_port", kv->key)) + ctxt->serial_port = atoi(kv->val); + else if (!strcmp("sld_type", kv->key)) + ctxt->sld_type = strtol(kv->val, NULL, 16); + + // Set key/val to BL33 env. + _l4t_bl33_cfg_set_key(bl33_env, kv->key, kv->val); + } + +#ifdef DEBUG_UART_PORT + // Override port if bootloader UART debug is enabled. + ctxt->serial_port = DEBUG_UART_PORT + 1; +#endif + + // Set r2p parameters. + if (entry_idx >= 10) + { + val[0] = '1'; + val[1] = '0' + (entry_idx % 10); + } + else + val[0] = '0' + entry_idx; + _l4t_bl33_cfg_set_key(bl33_env, "autoboot", val); + + // NULL terminate at single char for the next env sets. + val[1] = 0; + + val[0] = '0' + is_list; + _l4t_bl33_cfg_set_key(bl33_env, "autoboot_list", val); + + val[0] = '0' + L4T_LOADER_API_REV; + _l4t_bl33_cfg_set_key(bl33_env, "loader_rev", val); + + // Enable BL33 memory env import. + *(u32 *)(BL33_ENV_MAGIC_OFFSET) = BL33_ENV_MAGIC; + + // Set boot path. + sd_path = (char *)malloc(512); + sd_path_len = strlen(ctxt->path); + strcpy(sd_path, ctxt->path); +} + +void launch_l4t(const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b01) +{ + l4t_ctxt_t *ctxt = (l4t_ctxt_t *)TZ_PARAM_BASE; + memset(ctxt, 0, TZ_PARAM_SIZE); + + gfx_con_setpos(0, 0); + + // Parse config. + _l4t_set_config(ctxt, ini_sec, entry_idx, is_list, t210b01); + + if (!ctxt->path) + { + _l4t_crit_error("Path missing", false); + return; + } + + // Get MTC table. + ctxt->mtc_table = minerva_get_mtc_table(); + if (!t210b01 && !ctxt->mtc_table) + { + _l4t_crit_error("Minerva missing", true); + return; + } + + // Load BL31 (ATF/TrustZone fw). + if (!_l4t_sd_load(BL31_FW)) + { + _l4t_crit_error("BL31 missing", false); + return; + } + + // Load BL33 (U-BOOT/CBOOT). + if (!_l4t_sd_load(BL33_FW)) + { + _l4t_crit_error("BL33 missing", false); + return; + } + + // Set firmware path. + strcpy(sd_path, "bootloader/sys/l4t/"); + sd_path_len = strlen(sd_path); + + if (!t210b01) + { + // Load SC7-Entry firmware. + ctxt->sc7entry_size = _l4t_sd_load(SC7ENTRY_FW); + if (!ctxt->sc7entry_size) + { + _l4t_crit_error("loading SC7-Entry", true); + return; + } + + // Load BPMP-FW. Does power management. + if (!_l4t_sd_load(BPMPFW_FW)) + { + _l4t_crit_error("loading BPMP-FW", true); + return; + } + } + else + { + // Load BPMP-FW. Manages SC7-Entry also. + if (!_l4t_sd_load(BPMPFW_B01_FW)) + { + _l4t_crit_error("loading BPMP-FW", true); + return; + } + + // Load BPMP-FW MTC table. + if (!_l4t_sd_load(BPMPFW_B01_MTC_TBL)) + { + _l4t_crit_error("loading BPMP-FW MTC", true); + return; + } + } + + // Load SC7-Exit firmware. + if (!_l4t_sd_load(!t210b01 ? SC7EXIT_FW : SC7EXIT_B01_FW)) + { + _l4t_crit_error("loading SC7-Exit", true); + return; + } + + // Set SC7-Exit firmware address to PMC for bootrom and do further setup. + if (!_l4t_sc7_exit_config(t210b01)) + return; + + // Done loading bootloaders/firmware. + sd_end(); + + // We don't need AHB aperture open. + mc_disable_ahb_redirect(); + + // Enable debug port. + if (ctxt->serial_port) + { + pinmux_config_uart(ctxt->serial_port - 1); + clock_enable_uart(ctxt->serial_port - 1); + } + + // Restore UARTB/C TX pins to SPIO. + gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO); + gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO); + + // Configure BL33 parameters. + if (*(u32 *)BL33_DTB_BASE == DTB_MAGIC) + { + // Defaults are for UARTA. + char *bl33_serial_port = NULL; + switch (ctxt->serial_port) + { + case 0: // Disable. + break; + case 1: // UARTA. + bl33_serial_port = "70006000"; + break; + case 2: // UARTB. + bl33_serial_port = "70006040"; + break; + case 3: // UARTC. + bl33_serial_port = "70006200"; + break; + } + + if (bl33_serial_port) + { + BL33_DTB_SET_STDOUT_PATH(bl33_serial_port); + BL33_DTB_SET_STDERR_PATH(bl33_serial_port); + BL33_DTB_SET_UART_STATUS(ctxt->serial_port); + } + } + + // Set BL31 params. + ctxt->bl31_v1_params.hdr.type = PARAM_BL31; + ctxt->bl31_v1_params.hdr.version = VERSION_1; + ctxt->bl31_v1_params.hdr.size = sizeof(bl31_v1_params_t); + ctxt->bl31_v1_params.hdr.attr = PARAM_EP_SECURE; + ctxt->bl31_v1_params.bl33_ep_info = (u64)(u32)&ctxt->bl33_ep_info; + + // Set BL33 params. + ctxt->bl33_ep_info.hdr.type = PARAM_EP; + ctxt->bl33_ep_info.hdr.version = VERSION_1; + ctxt->bl33_ep_info.hdr.size = sizeof(entry_point_info_t); + ctxt->bl33_ep_info.hdr.attr = PARAM_EP_NON_SECURE; + ctxt->bl33_ep_info.pc = BL33_LOAD_BASE; + ctxt->bl33_ep_info.spsr = SPSR_EL2T; + + // Set Platform parameters. + ctxt->bl31_plat_params.tzdram_base = TZDRAM_BASE; + ctxt->bl31_plat_params.tzdram_size = TZDRAM_SIZE; +#if DEBUG_LOG_ATF + ctxt->bl31_plat_params.uart_id = ctxt->serial_port; +#endif + + if (!t210b01) + { + // Set SC7-Entry fw parameters. For now BPMP-FW is not used on T210. + ctxt->bl31_plat_params.sc7entry_fw_base = SC7ENTRY_HDR_BASE; + ctxt->bl31_plat_params.sc7entry_fw_size = ALIGN(ctxt->sc7entry_size + SC7ENTRY_HDR_SIZE, SZ_PAGE); + } + + // Enable below features. + ctxt->bl31_plat_params.enable_extra_features = BL31_EXTRA_FEATURES_ENABLE; + + if (!t210b01) + { + // Set R2P payload. + reloc_meta_t *reloc = (reloc_meta_t *)(IPL_LOAD_ADDR + 0x7C); + memcpy((u8 *)R2P_PAYLOAD_BASE, (u8 *)reloc->start, reloc->end - reloc->start); + memset((u8 *)R2P_PAYLOAD_BASE + 0x94, 0, sizeof(boot_cfg_t)); // Clear Boot Config Storage. + + // Set R2P payload fw parameters. + ctxt->bl31_plat_params.r2p_payload_base = R2P_PAYLOAD_BASE; + ctxt->bl31_plat_params.r2p_payload_size = ALIGN(reloc->end - reloc->start, SZ_PAGE); + } + + // Set PMC access security. NS is mandatory for T210B01. + ctxt->bl31_plat_params.flags = FLAGS_PMC_NON_SECURE; // Unsecure it unconditionally to reduce SMC calls to a minimum. + // Lift SC7 placement restrictions. Disables TZDRAM increased carveout too. + ctxt->bl31_plat_params.flags |= FLAGS_SC7_NO_BASE_RESTRICTION; + + // Prepare EMC table. + if (ctxt->mtc_table) + { + // Set DRAM voltage. + if (ctxt->ram_oc_vdd2) + max7762x_regulator_set_voltage(REGULATOR_SD1, ctxt->ram_oc_vdd2 * 1000); + + // Train the rest of the table, apply FSP WAR, set RAM to 800 MHz. + minerva_prep_boot_l4t(ctxt->ram_oc_freq, ctxt->ram_oc_opt); + + // Set emc table parameters and copy it. + int table_entries = minerva_get_mtc_table_entries(); + ctxt->bl31_plat_params.emc_table_base = MTCTABLE_BASE; + ctxt->bl31_plat_params.emc_table_size = sizeof(emc_table_t) * table_entries; + memcpy((u32 *)MTCTABLE_BASE, ctxt->mtc_table, sizeof(emc_table_t) * table_entries); + } + + // Set and enable IRAM based BL31 config. + PMC(APBDEV_PMC_SECURE_SCRATCH112) = PMC(APBDEV_PMC_SECURE_SCRATCH108); + PMC(APBDEV_PMC_SECURE_SCRATCH114) = PMC(APBDEV_PMC_SECURE_SCRATCH109); + PMC(APBDEV_PMC_SECURE_SCRATCH108) = (u32)&ctxt->bl31_v1_params; + PMC(APBDEV_PMC_SECURE_SCRATCH109) = (u32)&ctxt->bl31_plat_params; + PMC(APBDEV_PMC_SECURE_SCRATCH110) = BL31_IRAM_PARAMS; + + // Set panel model. + PMC(APBDEV_PMC_SECURE_SCRATCH113) = display_get_decoded_panel_id(); + + // Set charging limit parameters. + if (fuse_read_hw_type() == FUSE_NX_HW_TYPE_HOAG) + { + int in_volt_lim = 0; + bq24193_get_property(BQ24193_ChargeVoltageLimit, &in_volt_lim); + + PMC(APBDEV_PMC_SECURE_SCRATCH113) |= in_volt_lim << 16; + } + + // Disable writes to above registers. + PMC(APBDEV_PMC_SEC_DISABLE8) |= BIT(18) | BIT(16) | BIT(12) | BIT(10) | BIT(8); + + // Set BPMP-FW parameters. + if (t210b01) + _l4t_bpmpfw_b01_config(ctxt); + + // Set carveouts and save them to PMC for SC7 Exit. + _l4t_mc_config_carveout(t210b01); + + // Deinit any unneeded HW. + hw_deinit(false, ctxt->sld_type); + + // Do late hardware config. + _l4t_late_hw_config(t210b01); + + if (t210b01) + { + // Launch BL31. + ccplex_boot_cpu0(TZDRAM_COLD_ENTRY, true); + + // Enable Wrap burst for BPMP, GPU and PCIE. + MSELECT(MSELECT_CONFIG) = (MSELECT(MSELECT_CONFIG) & (~(MSELECT_CFG_ERR_RESP_EN_GPU | MSELECT_CFG_ERR_RESP_EN_PCIE))) | + (MSELECT_CFG_WRAP_TO_INCR_GPU | MSELECT_CFG_WRAP_TO_INCR_PCIE | MSELECT_CFG_WRAP_TO_INCR_BPMP); + + // For T210B01, prep reset vector for SC7 save state and start BPMP-FW. + EXCP_VEC(EVP_COP_RESET_VECTOR) = BPMPFW_B01_ENTRYPOINT; + void (*bpmp_fw_ptr)() = (void *)BPMPFW_B01_ENTRYPOINT; + (*bpmp_fw_ptr)(); + } + else + { + // If T210, BPMP-FW runs BL31. + void (*bpmp_fw_ptr)() = (void *)BPMPFW_ENTRYPOINT; + (*bpmp_fw_ptr)(); + } + + // Halt BPMP. + while (true) + bpmp_halt(); +} diff --git a/bootloader/frontend/fe_emmc_tools.h b/bootloader/l4t/l4t.h similarity index 66% rename from bootloader/frontend/fe_emmc_tools.h rename to bootloader/l4t/l4t.h index 059a03a..9e02ea6 100644 --- a/bootloader/frontend/fe_emmc_tools.h +++ b/bootloader/l4t/l4t.h @@ -1,6 +1,7 @@ /* - * Copyright (c) 2018 Rajko Stojadinovic - * Copyright (c) 2018 CTCaer + * L4T Loader for Tegra X1 + * + * Copyright (c) 2020-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -15,16 +16,9 @@ * along with this program. If not, see . */ -#ifndef _FE_EMMC_TOOLS_H_ -#define _FE_EMMC_TOOLS_H_ +#ifndef _L4T_H_ +#define _L4T_H_ -void dump_emmc_system(); -void dump_emmc_user(); -void dump_emmc_boot(); -void dump_emmc_rawnand(); - -void restore_emmc_boot(); -void restore_emmc_rawnand(); -void restore_emmc_gpp_parts(); +void launch_l4t(const ini_sec_t *ini_sec, int entry_idx, int is_list, bool t210b01); #endif diff --git a/bootloader/l4t/l4t_config.inl b/bootloader/l4t/l4t_config.inl new file mode 100644 index 0000000..0810f13 --- /dev/null +++ b/bootloader/l4t/l4t_config.inl @@ -0,0 +1,36 @@ +/* + * L4T Loader for Tegra X1 + * + * Copyright (c) 2020-2022 CTCaer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +// Set to 1 to enable early boot debugging. +#define DEBUG_LOG_ATF 0 +#define DEBUG_LOG_BPMPFW 0 // Do not enable if UART setup is hindered during early boot. + +// Set to 1 to lock PMC registers that contain LP0 parameters. +#define LOCK_PMC_REGISTERS 0 + +// Configurable carveout enable config. Only one can be enabled at a time. +#define CARVEOUT_NVDEC_TSEC_ENABLE 0 // Enable for NVDEC bl/prod and full TOS/DRM. +#define CARVEOUT_SECFW_ENABLE 1 // SECFW is always allocated even if carveout is disabled. + +/* + * WPR Carveout size config. + * + * L4T: 2MB or 13MB. On non SecureOS env, only 0x100 bytes are used, probably also on full TOS. + * On 4GB+ systems, it's normally placed at BANK1_TOP - SIZE; + */ +#define CARVEOUT_GPUWPR_SIZE_CFG (SZ_8M + SZ_4M + SZ_1M) // Mandatory when CARVEOUT_NVDEC_TSEC_ENABLE is 1. diff --git a/bootloader/libs/fatfs/diskio.c b/bootloader/libs/fatfs/diskio.c index 0f87131..d207d96 100644 --- a/bootloader/libs/fatfs/diskio.c +++ b/bootloader/libs/fatfs/diskio.c @@ -9,10 +9,9 @@ #include +#include + #include /* FatFs lower layer API */ -#include -#include -#include /*-----------------------------------------------------------------------*/ /* Get Drive Status */ diff --git a/bootloader/libs/fatfs/ffconf.h b/bootloader/libs/fatfs/ffconf.h index 32cad8a..c6b94bc 100644 --- a/bootloader/libs/fatfs/ffconf.h +++ b/bootloader/libs/fatfs/ffconf.h @@ -256,7 +256,7 @@ #define FF_FS_NORTC 1 #define FF_NORTC_MON 1 #define FF_NORTC_MDAY 1 -#define FF_NORTC_YEAR 2021 +#define FF_NORTC_YEAR 2025 /* The option FF_FS_NORTC switches timestamp function. If the system does not have / any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable / the timestamp function. Every object modified by FatFs will have a fixed timestamp diff --git a/bootloader/libs/fatfs/ffsystem.c b/bootloader/libs/fatfs/ffsystem.c deleted file mode 100644 index 6f5f435..0000000 --- a/bootloader/libs/fatfs/ffsystem.c +++ /dev/null @@ -1,39 +0,0 @@ -/*------------------------------------------------------------------------*/ -/* Sample Code of OS Dependent Functions for FatFs */ -/* (C) ChaN, 2018 */ -/* (C) CTCaer, 2018 */ -/*------------------------------------------------------------------------*/ - - -#include -#include - - - -#if FF_USE_LFN == 3 /* Dynamic memory allocation */ - -/*------------------------------------------------------------------------*/ -/* Allocate a memory block */ -/*------------------------------------------------------------------------*/ - -void* ff_memalloc ( /* Returns pointer to the allocated memory block (null if not enough core) */ - UINT msize /* Number of bytes to allocate */ -) -{ - return malloc(msize); /* Allocate a new memory block with POSIX API */ -} - - -/*------------------------------------------------------------------------*/ -/* Free a memory block */ -/*------------------------------------------------------------------------*/ - -void ff_memfree ( - void* mblock /* Pointer to the memory block to free (nothing to do if null) */ -) -{ - free(mblock); /* Free the memory block with POSIX API */ -} - -#endif - diff --git a/bootloader/main.c b/bootloader/main.c index a929b52..4ec3eab 100644 --- a/bootloader/main.c +++ b/bootloader/main.c @@ -1,7 +1,7 @@ /* * Copyright (c) 2018 naehrwert * - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,43 +19,19 @@ #include #include -#include +#include #include "config.h" -#include -#include #include "gfx/logos.h" #include "gfx/tui.h" #include "hos/hos.h" #include "hos/secmon_exo.h" +#include "l4t/l4t.h" #include #include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include #include "storage/emummc.h" -#include "storage/nx_emmc.h" -#include -#include -#include -#include -#include -#include -#include "frontend/fe_emmc_tools.h" #include "frontend/fe_tools.h" #include "frontend/fe_info.h" @@ -63,78 +39,50 @@ hekate_config h_cfg; boot_cfg_t __attribute__((section ("._boot_cfg"))) b_cfg; const volatile ipl_ver_meta_t __attribute__((section ("._ipl_version"))) ipl_ver = { .magic = BL_MAGIC, - .version = (BL_VER_MJ + '0') | ((BL_VER_MN + '0') << 8) | ((BL_VER_HF + '0') << 16), + .version = (BL_VER_MJ + '0') | ((BL_VER_MN + '0') << 8) | ((BL_VER_HF + '0') << 16) | ((BL_VER_RL) << 24), .rsvd0 = 0, .rsvd1 = 0 }; volatile nyx_storage_t *nyx_str = (nyx_storage_t *)NYX_STORAGE_ADDR; -void emmcsn_path_impl(char *path, char *sub_dir, char *filename, sdmmc_storage_t *storage) +static void _check_power_off_from_hos() { - char emmcSN[9]; - bool init_done = false; + // Power off on alarm wakeup from HOS shutdown. For modchips/dongles. + u8 hos_wakeup = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_IRQTOP); - memcpy(path, "backup", 7); - f_mkdir(path); + // Clear RTC interrupts. + (void)i2c_recv_byte(I2C_5, MAX77620_RTC_I2C_ADDR, MAX77620_RTC_RTCINT_REG); - if (!storage) + // Stop the alarm, in case we injected and powered off too fast. + max77620_rtc_stop_alarm(); + + // Handle RTC wake up. + if (hos_wakeup & MAX77620_IRQ_TOP_RTC_MASK) { - if (!sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400)) - memcpy(emmcSN, "00000000", 9); - else - { - init_done = true; - itoa(emmc_storage.cid.serial, emmcSN, 16); - } - } - else - itoa(storage->cid.serial, emmcSN, 16); - - u32 sub_dir_len = strlen(sub_dir); // Can be a null-terminator. - u32 filename_len = strlen(filename); // Can be a null-terminator. - - memcpy(path + strlen(path), "/", 2); - memcpy(path + strlen(path), emmcSN, 9); - f_mkdir(path); - memcpy(path + strlen(path), sub_dir, sub_dir_len + 1); - if (sub_dir_len) - f_mkdir(path); - memcpy(path + strlen(path), "/", 2); - memcpy(path + strlen(path), filename, filename_len + 1); - - if (init_done) - sdmmc_storage_end(&emmc_storage); -} - -void render_default_bootlogo() -{ - gfx_clear_grey(0x1B); - u8 *BOOTLOGO = (void *)malloc(0x4000); - blz_uncompress_srcdest(BOOTLOGO_BLZ, SZ_BOOTLOGO_BLZ, BOOTLOGO, SZ_BOOTLOGO); - gfx_set_rect_grey(BOOTLOGO, X_BOOTLOGO, Y_BOOTLOGO, 326, 544); - free(BOOTLOGO); -} - -void check_power_off_from_hos() -{ - // Power off on AutoRCM wakeup from HOS shutdown. For modchips/dongles. - u8 hosWakeup = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_IRQTOP); - if (hosWakeup & MAX77620_IRQ_TOP_RTC_MASK) - { - sd_end(); - - // Stop the alarm, in case we injected too fast. - max77620_rtc_stop_alarm(); - if (h_cfg.autohosoff == 1) { - render_default_bootlogo(); + render_static_bootlogo(); - display_backlight_brightness(10, 5000); - display_backlight_brightness(100, 25000); - msleep(600); - display_backlight_brightness(0, 20000); + if (display_get_decoded_panel_id() != PANEL_SAM_AMS699VC01) + { + // Slow fading for LCD panels. + display_backlight_brightness(10, 5000); + display_backlight_brightness(100, 25000); + msleep(600); + display_backlight_brightness(0, 20000); + } + else + { + // Blink 3 times for OLED panel. + for (u32 i = 0; i < 3; i++) + { + msleep(150); + display_backlight_brightness(100, 0); + msleep(150); + display_backlight_brightness(0, 0); + } + } } power_set_state(POWER_OFF_RESET); } @@ -149,16 +97,16 @@ void check_power_off_from_hos() #define RCM_PAYLOAD_ADDR (EXT_PAYLOAD_ADDR + ALIGN(PATCHED_RELOC_SZ, 0x10)) #define COREBOOT_END_ADDR 0xD0000000 #define COREBOOT_VER_OFF 0x41 -#define CBFS_DRAM_EN_ADDR 0x4003e000 +#define CBFS_DRAM_EN_ADDR 0x4003E000 #define CBFS_DRAM_MAGIC 0x4452414D // "DRAM" static void *coreboot_addr; -void reloc_patcher(u32 payload_dst, u32 payload_src, u32 payload_size) +static void _reloc_patcher(u32 payload_dst, u32 payload_src, u32 payload_size) { memcpy((u8 *)payload_src, (u8 *)IPL_LOAD_ADDR, PATCHED_RELOC_SZ); - volatile reloc_meta_t *relocator = (reloc_meta_t *)(payload_src + RELOC_META_OFF); + reloc_meta_t *relocator = (reloc_meta_t *)(payload_src + RELOC_META_OFF); relocator->start = payload_dst - ALIGN(PATCHED_RELOC_SZ, 0x10); relocator->stack = PATCHED_RELOC_STACK; @@ -167,16 +115,16 @@ void reloc_patcher(u32 payload_dst, u32 payload_src, u32 payload_size) if (payload_size == 0x7000) { - memcpy((u8 *)(payload_src + ALIGN(PATCHED_RELOC_SZ, 0x10)), coreboot_addr, 0x7000); //Bootblock + memcpy((u8 *)(payload_src + ALIGN(PATCHED_RELOC_SZ, 0x10)), coreboot_addr, 0x7000); // Bootblock. *(vu32 *)CBFS_DRAM_EN_ADDR = CBFS_DRAM_MAGIC; } } -bool is_ipl_updated(void *buf, char *path, bool force) +bool is_ipl_updated(void *buf, const char *path, bool force) { ipl_ver_meta_t *update_ft = (ipl_ver_meta_t *)(buf + PATCHED_RELOC_SZ + sizeof(boot_cfg_t)); - bool magic_valid = update_ft->magic == ipl_ver.magic; + bool magic_valid = update_ft->magic == ipl_ver.magic; bool force_update = force && !magic_valid; bool is_valid_old = magic_valid && (byte_swap_32(update_ft->version) < byte_swap_32(ipl_ver.version)); @@ -189,9 +137,8 @@ bool is_ipl_updated(void *buf, char *path, bool force) if (force_update || is_valid_old) { FIL fp; - volatile reloc_meta_t *reloc = (reloc_meta_t *)(IPL_LOAD_ADDR + RELOC_META_OFF); - boot_cfg_t *tmp_cfg = malloc(sizeof(boot_cfg_t)); - memset(tmp_cfg, 0, sizeof(boot_cfg_t)); + reloc_meta_t *reloc = (reloc_meta_t *)(IPL_LOAD_ADDR + RELOC_META_OFF); + boot_cfg_t *tmp_cfg = zalloc(sizeof(boot_cfg_t)); f_open(&fp, path, FA_WRITE | FA_CREATE_ALWAYS); f_write(&fp, (u8 *)reloc->start, reloc->end - reloc->start, NULL); @@ -210,422 +157,251 @@ bool is_ipl_updated(void *buf, char *path, bool force) return true; } -int launch_payload(char *path, bool update, bool clear_screen) +static void _launch_payload(char *path, bool update, bool clear_screen) { if (clear_screen) gfx_clear_grey(0x1B); gfx_con_setpos(0, 0); - if (sd_mount()) + FIL fp; + if (f_open(&fp, path, FA_READ)) { - FIL fp; - if (f_open(&fp, path, FA_READ)) - { - gfx_con.mute = false; - EPRINTFARGS("Payload file is missing!\n(%s)", path); + gfx_con.mute = false; + EPRINTFARGS("Payload file is missing!\n(%s)", path); - goto out; - } + goto out; + } - // Read and copy the payload to our chosen address - void *buf; - u32 size = f_size(&fp); + // Read and copy the payload to our chosen address + void *buf; + u32 size = f_size(&fp); - if (size < 0x30000) - buf = (void *)RCM_PAYLOAD_ADDR; - else - { - coreboot_addr = (void *)(COREBOOT_END_ADDR - size); - buf = coreboot_addr; - if (h_cfg.t210b01) - { - f_close(&fp); - - gfx_con.mute = false; - EPRINTF("Coreboot not allowed on Mariko!"); - - goto out; - } - } - - if (f_read(&fp, buf, size, NULL)) + if (size < 0x30000) + buf = (void *)RCM_PAYLOAD_ADDR; + else + { + coreboot_addr = (void *)(COREBOOT_END_ADDR - size); + buf = coreboot_addr; + if (h_cfg.t210b01) { f_close(&fp); + gfx_con.mute = false; + EPRINTF("Coreboot not allowed on Mariko!"); + goto out; } + } + if (f_read(&fp, buf, size, NULL)) + { f_close(&fp); - if (update && is_ipl_updated(buf, path, false)) - goto out; + goto out; + } - sd_end(); + f_close(&fp); - if (size < 0x30000) - { - if (update) - memcpy((u8 *)(RCM_PAYLOAD_ADDR + PATCHED_RELOC_SZ), &b_cfg, sizeof(boot_cfg_t)); // Transfer boot cfg. - else - reloc_patcher(PATCHED_RELOC_ENTRY, EXT_PAYLOAD_ADDR, ALIGN(size, 0x10)); + if (update && is_ipl_updated(buf, path, false)) + goto out; - hw_reinit_workaround(false, byte_swap_32(*(u32 *)(buf + size - sizeof(u32)))); - } + sd_end(); + + if (size < 0x30000) + { + if (update) + memcpy((u8 *)(RCM_PAYLOAD_ADDR + PATCHED_RELOC_SZ), &b_cfg, sizeof(boot_cfg_t)); // Transfer boot cfg. else - { - reloc_patcher(PATCHED_RELOC_ENTRY, EXT_PAYLOAD_ADDR, 0x7000); + _reloc_patcher(PATCHED_RELOC_ENTRY, EXT_PAYLOAD_ADDR, ALIGN(size, 0x10)); - // Get coreboot seamless display magic. - u32 magic = 0; - char *magic_ptr = buf + COREBOOT_VER_OFF; - memcpy(&magic, magic_ptr + strlen(magic_ptr) - 4, 4); - hw_reinit_workaround(true, magic); - } + hw_deinit(false, byte_swap_32(*(u32 *)(buf + size - sizeof(u32)))); + } + else + { + _reloc_patcher(PATCHED_RELOC_ENTRY, EXT_PAYLOAD_ADDR, 0x7000); + // Get coreboot seamless display magic. + u32 magic = 0; + char *magic_ptr = buf + COREBOOT_VER_OFF; + memcpy(&magic, magic_ptr + strlen(magic_ptr) - 4, 4); + hw_deinit(true, magic); + } + + void (*update_ptr)() = (void *)RCM_PAYLOAD_ADDR; + void (*ext_payload_ptr)() = (void *)EXT_PAYLOAD_ADDR; + + // Launch our payload. + if (!update) + { // Some cards (Sandisk U1), do not like a fast power cycle. Wait min 100ms. sdmmc_storage_init_wait_sd(); - void (*ext_payload_ptr)() = (void *)EXT_PAYLOAD_ADDR; - void (*update_ptr)() = (void *)RCM_PAYLOAD_ADDR; - - // Launch our payload. - if (!update) - (*ext_payload_ptr)(); - else - { - // Set updated flag to skip check on launch. - EMC(EMC_SCRATCH0) |= EMC_HEKA_UPD; - (*update_ptr)(); - } + (*ext_payload_ptr)(); + } + else + { + // Set updated flag to skip check on launch. + EMC(EMC_SCRATCH0) |= EMC_HEKA_UPD; + (*update_ptr)(); } out: if (!update) - sd_end(); - - return 1; -} - -void auto_launch_update() -{ - // Check if already chainloaded update and clear flag. Otherwise check for updates. - if (EMC(EMC_SCRATCH0) & EMC_HEKA_UPD) - EMC(EMC_SCRATCH0) &= ~EMC_HEKA_UPD; - else if (sd_mount()) { - // Check if update.bin exists and is newer and launch it. Otherwise create it. - if (!f_stat("bootloader/update.bin", NULL)) - launch_payload("bootloader/update.bin", true, false); - else - { - u8 *buf = calloc(0x200, 1); - is_ipl_updated(buf, "bootloader/update.bin", true); - free(buf); - } + gfx_con.mute = false; + EPRINTF("Failed to launch payload!"); } } -void launch_tools() +static void _launch_payloads() { u8 max_entries = 61; - char *filelist = NULL; + ment_t *ments = NULL; char *file_sec = NULL; char *dir = NULL; - - ment_t *ments = (ment_t *)malloc(sizeof(ment_t) * (max_entries + 3)); + dirlist_t *filelist = NULL; gfx_clear_grey(0x1B); gfx_con_setpos(0, 0); - if (sd_mount()) + if (!sd_mount()) + goto failed_sd_mount; + + ments = (ment_t *)malloc(sizeof(ment_t) * (max_entries + 3)); + + dir = (char *)malloc(256); + memcpy(dir, "bootloader/payloads", 20); + + filelist = dirlist(dir, NULL, false, false); + + u32 i = 0; + + if (filelist) { - dir = (char *)malloc(256); + // Build configuration menu. + ments[0].type = MENT_BACK; + ments[0].caption = "Back"; - memcpy(dir, "bootloader/payloads", 20); + ments[1].type = MENT_CHGLINE; - filelist = dirlist(dir, NULL, false, false); - - u32 i = 0; - - if (filelist) + while (true) { - // Build configuration menu. - ments[0].type = MENT_BACK; - ments[0].caption = "Back"; - ments[1].type = MENT_CHGLINE; + if (i > max_entries || !filelist->name[i]) + break; + ments[i + 2].type = INI_CHOICE; + ments[i + 2].caption = filelist->name[i]; + ments[i + 2].data = filelist->name[i]; - while (true) - { - if (i > max_entries || !filelist[i * 256]) - break; - ments[i + 2].type = INI_CHOICE; - ments[i + 2].caption = &filelist[i * 256]; - ments[i + 2].data = &filelist[i * 256]; - - i++; - } + i++; } + } - if (i > 0) + if (i > 0) + { + memset(&ments[i + 2], 0, sizeof(ment_t)); + menu_t menu = { ments, "Choose a payload", 0, 0 }; + + file_sec = (char *)tui_do_menu(&menu); + + if (!file_sec) { - memset(&ments[i + 2], 0, sizeof(ment_t)); - menu_t menu = { ments, "Choose a file to launch", 0, 0 }; + free(ments); + free(dir); + free(filelist); + sd_end(); - file_sec = (char *)tui_do_menu(&menu); - - if (!file_sec) - { - free(ments); - free(dir); - free(filelist); - sd_end(); - - return; - } + return; } - else - EPRINTF("No payloads or modules found."); - - free(ments); - free(filelist); } else - { - free(ments); - goto out; - } + EPRINTF("No payloads found."); if (file_sec) { memcpy(dir + strlen(dir), "/", 2); memcpy(dir + strlen(dir), file_sec, strlen(file_sec) + 1); - launch_payload(dir, false, true); - EPRINTF("Failed to launch payload."); + _launch_payload(dir, false, true); } -out: - sd_end(); +failed_sd_mount: free(dir); + free(ments); + free(filelist); + sd_end(); btn_wait(); } -void ini_list_launcher() +static void _launch_ini_list() { u8 max_entries = 61; - char *payload_path = NULL; - char *emummc_path = NULL; - + char *special_path = NULL; + char *emummc_path = NULL; + ment_t *ments = NULL; ini_sec_t *cfg_sec = NULL; + LIST_INIT(ini_list_sections); gfx_clear_grey(0x1B); gfx_con_setpos(0, 0); - if (sd_mount()) + if (!sd_mount()) + goto parse_failed; + + // Check that ini files exist and parse them. + if (!ini_parse(&ini_list_sections, "bootloader/ini", true)) { - if (ini_parse(&ini_list_sections, "bootloader/ini", true)) - { - // Build configuration menu. - ment_t *ments = (ment_t *)malloc(sizeof(ment_t) * (max_entries + 3)); - ments[0].type = MENT_BACK; - ments[0].caption = "Back"; - ments[1].type = MENT_CHGLINE; - - u32 i = 2; - LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_list_sections, link) - { - if (!strcmp(ini_sec->name, "config") || - ini_sec->type == INI_COMMENT || ini_sec->type == INI_NEWLINE) - continue; - ments[i].type = ini_sec->type; - ments[i].caption = ini_sec->name; - ments[i].data = ini_sec; - if (ini_sec->type == MENT_CAPTION) - ments[i].color = ini_sec->color; - i++; - - if ((i - 1) > max_entries) - break; - } - if (i > 2) - { - memset(&ments[i], 0, sizeof(ment_t)); - menu_t menu = { - ments, "Launch ini configurations", 0, 0 - }; - - cfg_sec = (ini_sec_t *)tui_do_menu(&menu); - - if (cfg_sec) - { - u32 non_cfg = 1; - for (u32 j = 2; j < i; j++) - { - if (ments[j].type != INI_CHOICE) - non_cfg++; - - if (ments[j].data == cfg_sec) - { - b_cfg.boot_cfg = BOOT_CFG_FROM_LAUNCH; - b_cfg.autoboot = j - non_cfg; - b_cfg.autoboot_list = 1; - - break; - } - } - } - - payload_path = ini_check_payload_section(cfg_sec); - - if (cfg_sec) - { - LIST_FOREACH_ENTRY(ini_kv_t, kv, &cfg_sec->kvs, link) - { - if (!strcmp("emummc_force_disable", kv->key)) - h_cfg.emummc_force_disable = atoi(kv->val); - else if (!strcmp("emupath", kv->key)) - emummc_path = kv->val; - } - } - - if (emummc_path && !emummc_set_path(emummc_path)) - { - EPRINTF("emupath is wrong!"); - goto wrong_emupath; - } - - if (!cfg_sec) - { - free(ments); - - return; - } - } - else - EPRINTF("No extra configs found."); - free(ments); - } - else - EPRINTF("Could not find any ini\nin bootloader/ini!"); + EPRINTF("No .ini files in bootloader/ini!"); + goto parse_failed; } - if (!cfg_sec) - goto out; + // Build configuration menu. + ments = (ment_t *)malloc(sizeof(ment_t) * (max_entries + 3)); + ments[0].type = MENT_BACK; + ments[0].caption = "Back"; - if (payload_path) + ments[1].type = MENT_CHGLINE; + + u32 sec_idx = 2; + LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_list_sections, link) { - launch_payload(payload_path, false, true); - EPRINTF("Failed to launch payload."); - free(payload_path); - } - else if (!hos_launch(cfg_sec)) - { -wrong_emupath: - EPRINTF("Failed to launch HOS."); - if (emummc_path) - { - sd_mount(); - emummc_load_cfg(); - } + if (ini_sec->type == INI_COMMENT || + ini_sec->type == INI_NEWLINE || + !strcmp(ini_sec->name, "config")) + continue; + + ments[sec_idx].type = ini_sec->type; + ments[sec_idx].caption = ini_sec->name; + ments[sec_idx].data = ini_sec; + + if (ini_sec->type == MENT_CAPTION) + ments[sec_idx].color = ini_sec->color; + sec_idx++; + + if ((sec_idx - 1) > max_entries) + break; } -out: - - btn_wait(); -} - -void launch_firmware() -{ - u8 max_entries = 61; - char *payload_path = NULL; - char *emummc_path = NULL; - - ini_sec_t *cfg_sec = NULL; - LIST_INIT(ini_sections); - - gfx_clear_grey(0x1B); - gfx_con_setpos(0, 0); - - if (sd_mount()) + if (sec_idx > 2) { - if (ini_parse(&ini_sections, "bootloader/hekate_ipl.ini", false)) + memset(&ments[sec_idx], 0, sizeof(ment_t)); + menu_t menu = { + ments, "Launch ini entries", 0, 0 + }; + + cfg_sec = (ini_sec_t *)tui_do_menu(&menu); + + special_path = ini_check_special_section(cfg_sec); + + if (cfg_sec && !special_path) { - // Build configuration menu. - ment_t *ments = (ment_t *)malloc(sizeof(ment_t) * (max_entries + 6)); - ments[0].type = MENT_BACK; - ments[0].caption = "Back"; - ments[1].type = MENT_CHGLINE; - - ments[2].type = MENT_HANDLER; - ments[2].caption = "Payloads..."; - ments[2].handler = launch_tools; - ments[3].type = MENT_HANDLER; - ments[3].caption = "More configs..."; - ments[3].handler = ini_list_launcher; - - ments[4].type = MENT_CHGLINE; - - u32 i = 5; - LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sections, link) + LIST_FOREACH_ENTRY(ini_kv_t, kv, &cfg_sec->kvs, link) { - if (!strcmp(ini_sec->name, "config") || - ini_sec->type == INI_COMMENT || ini_sec->type == INI_NEWLINE) - continue; - ments[i].type = ini_sec->type; - ments[i].caption = ini_sec->name; - ments[i].data = ini_sec; - if (ini_sec->type == MENT_CAPTION) - ments[i].color = ini_sec->color; - i++; - - if ((i - 4) > max_entries) - break; - } - if (i < 6) - { - ments[i].type = MENT_CAPTION; - ments[i].caption = "No main configs found..."; - ments[i].color = 0xFFFFDD00; - i++; - } - memset(&ments[i], 0, sizeof(ment_t)); - menu_t menu = { - ments, "Launch configurations", 0, 0 - }; - - cfg_sec = (ini_sec_t *)tui_do_menu(&menu); - - if (cfg_sec) - { - u8 non_cfg = 4; - for (u32 j = 5; j < i; j++) - { - if (ments[j].type != INI_CHOICE) - non_cfg++; - if (ments[j].data == cfg_sec) - { - b_cfg.boot_cfg = BOOT_CFG_FROM_LAUNCH; - b_cfg.autoboot = j - non_cfg; - b_cfg.autoboot_list = 0; - - break; - } - } - } - - payload_path = ini_check_payload_section(cfg_sec); - - if (cfg_sec) - { - LIST_FOREACH_ENTRY(ini_kv_t, kv, &cfg_sec->kvs, link) - { - if (!strcmp("emummc_force_disable", kv->key)) - h_cfg.emummc_force_disable = atoi(kv->val); - if (!strcmp("emupath", kv->key)) - emummc_path = kv->val; - } + if (!strcmp("emummc_force_disable", kv->key)) + h_cfg.emummc_force_disable = atoi(kv->val); + else if (!strcmp("emupath", kv->key)) + emummc_path = kv->val; } if (emummc_path && !emummc_set_path(emummc_path)) @@ -633,46 +409,203 @@ void launch_firmware() EPRINTF("emupath is wrong!"); goto wrong_emupath; } - - if (!cfg_sec) - { - free(ments); - sd_end(); - return; - } - - free(ments); } + + if (!cfg_sec) + { + free(ments); + + return; + } + } + else + EPRINTF("No extra configs found."); + +parse_failed: + if (!cfg_sec) + goto out; + + if (special_path) + { + // Try to launch Payload or L4T. + if (special_path != (char *)-1) + _launch_payload(special_path, false, true); else - EPRINTF("Could not open 'bootloader/hekate_ipl.ini'.\nMake sure it exists!"); + { + u32 entry_idx = 0; + for (u32 i = 0; i < sec_idx; i++) + { + if (ments[i].data == cfg_sec) + { + entry_idx = i; + break; + } + } + launch_l4t(cfg_sec, entry_idx, 1, h_cfg.t210b01); + } + } + else + { + hos_launch(cfg_sec); + +wrong_emupath: + if (emummc_path) + { + sd_mount(); + emummc_load_cfg(); // Reload emuMMC config in case of emupath. + } } +out: + free(ments); + + btn_wait(); +} + +static void _launch_config() +{ + u8 max_entries = 61; + char *special_path = NULL; + char *emummc_path = NULL; + + ment_t *ments = NULL; + ini_sec_t *cfg_sec = NULL; + + LIST_INIT(ini_sections); + + gfx_clear_grey(0x1B); + gfx_con_setpos(0, 0); + + if (!sd_mount()) + goto parse_failed; + + // Load emuMMC configuration. + emummc_load_cfg(); + + // Parse main configuration. + ini_parse(&ini_sections, "bootloader/hekate_ipl.ini", false); + + // Build configuration menu. + ments = (ment_t *)malloc(sizeof(ment_t) * (max_entries + 6)); + ments[0].type = MENT_BACK; + ments[0].caption = "Back"; + + ments[1].type = MENT_CHGLINE; + + ments[2].type = MENT_HANDLER; + ments[2].caption = "Payloads..."; + ments[2].handler = _launch_payloads; + + ments[3].type = MENT_HANDLER; + ments[3].caption = "More configs..."; + ments[3].handler = _launch_ini_list; + + ments[4].type = MENT_CHGLINE; + + u32 sec_idx = 5; + LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sections, link) + { + if (ini_sec->type == INI_COMMENT || + ini_sec->type == INI_NEWLINE || + !strcmp(ini_sec->name, "config")) + continue; + + ments[sec_idx].type = ini_sec->type; + ments[sec_idx].caption = ini_sec->name; + ments[sec_idx].data = ini_sec; + + if (ini_sec->type == MENT_CAPTION) + ments[sec_idx].color = ini_sec->color; + sec_idx++; + + if ((sec_idx - 4) > max_entries) + break; + } + + if (sec_idx < 6) + { + ments[sec_idx].type = MENT_CAPTION; + ments[sec_idx].caption = "No main configs found..."; + ments[sec_idx].color = TXT_CLR_WARNING; + sec_idx++; + } + + memset(&ments[sec_idx], 0, sizeof(ment_t)); + menu_t menu = { + ments, "Launch configurations", 0, 0 + }; + + cfg_sec = (ini_sec_t *)tui_do_menu(&menu); + + special_path = ini_check_special_section(cfg_sec); + + if (cfg_sec && !special_path) + { + LIST_FOREACH_ENTRY(ini_kv_t, kv, &cfg_sec->kvs, link) + { + if (!strcmp("emummc_force_disable", kv->key)) + h_cfg.emummc_force_disable = atoi(kv->val); + if (!strcmp("emupath", kv->key)) + emummc_path = kv->val; + } + + if (emummc_path && !emummc_set_path(emummc_path)) + { + EPRINTF("emupath is wrong!"); + goto wrong_emupath; + } + } + + if (!cfg_sec) + { + free(ments); + sd_end(); + return; + } + +parse_failed: if (!cfg_sec) { gfx_printf("\nPress any key...\n"); goto out; } - if (payload_path) + if (special_path) { - launch_payload(payload_path, false, true); - EPRINTF("Failed to launch payload."); - free(payload_path); + // Try to launch Payload or L4T. + if (special_path != (char *)-1) + _launch_payload(special_path, false, true); + else + { + u32 entry_idx = 0; + for (u32 i = 0; i < sec_idx; i++) + { + if (ments[i].data == cfg_sec) + { + entry_idx = i; + break; + } + } + launch_l4t(cfg_sec, entry_idx, 0, h_cfg.t210b01); + } } - else if (!hos_launch(cfg_sec)) + else { + hos_launch(cfg_sec); + wrong_emupath: - EPRINTF("Failed to launch HOS."); if (emummc_path) { sd_mount(); - emummc_load_cfg(); + emummc_load_cfg(); // Reload emuMMC config in case of emupath. } } out: sd_end(); + free(ments); + h_cfg.emummc_force_disable = false; btn_wait(); @@ -680,29 +613,27 @@ out: #define NYX_VER_OFF 0x9C -void nyx_load_run() +static void _nyx_load_run() { - sd_mount(); - u8 *nyx = sd_file_read("bootloader/sys/nyx.bin", NULL); if (!nyx) return; sd_end(); - render_default_bootlogo(); + render_static_bootlogo(); display_backlight_brightness(h_cfg.backlight, 1000); // Check if Nyx version is old. u32 expected_nyx_ver = ((NYX_VER_MJ + '0') << 24) | ((NYX_VER_MN + '0') << 16) | ((NYX_VER_HF + '0') << 8); - u32 nyx_ver = byte_swap_32(*(u32 *)(nyx + NYX_VER_OFF)); + u32 nyx_ver = byte_swap_32(*(u32 *)(nyx + NYX_VER_OFF)) & 0xFFFFFF00; if (nyx_ver < expected_nyx_ver) { h_cfg.errors |= ERR_SYSOLD_NYX; gfx_con_setpos(0, 0); WPRINTF("Old Nyx GUI found! There will be dragons!\n"); - WPRINTF("\nUpdate the bootloader folder!\n\n"); + WPRINTF("\nUpdate bootloader folder!\n\n"); WPRINTF("Press any key..."); msleep(1000); @@ -714,43 +645,43 @@ void nyx_load_run() // Set Nyx mode. nyx_str->cfg = 0; - if (b_cfg.extra_cfg) + if (b_cfg.extra_cfg & EXTRA_CFG_NYX_UMS) { - if (b_cfg.extra_cfg & EXTRA_CFG_NYX_UMS) - { - b_cfg.extra_cfg &= ~(EXTRA_CFG_NYX_UMS); - nyx_str->cfg |= NYX_CFG_UMS; - nyx_str->cfg |= b_cfg.ums << 24; - } + b_cfg.extra_cfg &= ~(EXTRA_CFG_NYX_UMS); + + nyx_str->cfg |= NYX_CFG_UMS; + nyx_str->cfg |= b_cfg.ums << 24; } // Set hekate version used to boot Nyx. nyx_str->version = ipl_ver.version - 0x303030; // Convert ASCII to numbers. // Set SD card initialization info. - nyx_str->info.magic = NYX_NEW_INFO; + nyx_str->info.magic = NYX_NEW_INFO; nyx_str->info.sd_init = sd_get_mode(); + + // Set SD card error info. u16 *sd_errors = sd_get_error_count(); for (u32 i = 0; i < 3; i++) nyx_str->info.sd_errors[i] = sd_errors[i]; - //memcpy((u8 *)nyx_str->irama, (void *)IRAM_BASE, 0x8000); - volatile reloc_meta_t *reloc = (reloc_meta_t *)(IPL_LOAD_ADDR + RELOC_META_OFF); + reloc_meta_t *reloc = (reloc_meta_t *)(IPL_LOAD_ADDR + RELOC_META_OFF); memcpy((u8 *)nyx_str->hekate, (u8 *)reloc->start, reloc->end - reloc->start); - void (*nyx_ptr)() = (void *)nyx; + // Do one last training. + minerva_periodic_training(); bpmp_mmu_disable(); bpmp_clk_rate_set(BPMP_CLK_NORMAL); - minerva_periodic_training(); - // Some cards (Sandisk U1), do not like a fast power cycle. Wait min 100ms. + // Some cards (Sandisk U1), do not like a fast power cycle. sdmmc_storage_init_wait_sd(); + void (*nyx_ptr)() = (void *)nyx; (*nyx_ptr)(); } -static ini_sec_t *get_ini_sec_from_id(ini_sec_t *ini_sec, char **bootlogoCustomEntry, char **emummc_path) +static ini_sec_t *_get_ini_sec_from_id(ini_sec_t *ini_sec, char **bootlogoCustomEntry, char **emummc_path) { ini_sec_t *cfg_sec = NULL; @@ -763,17 +694,17 @@ static ini_sec_t *get_ini_sec_from_id(ini_sec_t *ini_sec, char **bootlogoCustomE else break; } - if (!strcmp("logopath", kv->key)) - *bootlogoCustomEntry = kv->val; - if (!strcmp("emummc_force_disable", kv->key)) - h_cfg.emummc_force_disable = atoi(kv->val); if (!strcmp("emupath", kv->key)) *emummc_path = kv->val; + else if (!strcmp("logopath", kv->key)) + *bootlogoCustomEntry = kv->val; + else if (!strcmp("emummc_force_disable", kv->key)) + h_cfg.emummc_force_disable = atoi(kv->val); } if (!cfg_sec) { - *bootlogoCustomEntry = NULL; - *emummc_path = NULL; + *emummc_path = NULL; + *bootlogoCustomEntry = NULL; h_cfg.emummc_force_disable = false; } @@ -786,13 +717,32 @@ static void _bootloader_corruption_protect() if (!f_stat("bootloader", &fno)) { if (!h_cfg.bootprotect && (fno.fattrib & AM_ARC)) - f_chmod("bootloader", 0, AM_ARC); + f_chmod("bootloader", 0, AM_ARC); else if (h_cfg.bootprotect && !(fno.fattrib & AM_ARC)) f_chmod("bootloader", AM_ARC, AM_ARC); } } -static void _auto_launch_firmware() +static void _check_for_updated_bootloader() +{ + // Check if already chainloaded update and clear flag. Otherwise check for updates. + if (EMC(EMC_SCRATCH0) & EMC_HEKA_UPD) + EMC(EMC_SCRATCH0) &= ~EMC_HEKA_UPD; + else + { + // Check if update.bin exists and is newer and launch it. Otherwise create it. + if (!f_stat("bootloader/update.bin", NULL)) + _launch_payload("bootloader/update.bin", true, false); + else + { + u8 *buf = zalloc(0x200); + is_ipl_updated(buf, "bootloader/update.bin", true); + free(buf); + } + } +} + +static void _auto_launch() { struct _bmp_data { @@ -804,11 +754,14 @@ static void _auto_launch_firmware() u32 pos_y; }; - char *emummc_path = NULL; + u32 boot_wait = h_cfg.bootwait; + u32 boot_entry_id = 0; + ini_sec_t *cfg_sec = NULL; + char *emummc_path = NULL; char *bootlogoCustomEntry = NULL; - ini_sec_t *cfg_sec = NULL; + bool config_entry_found = false; - auto_launch_update(); + _check_for_updated_bootloader(); bool boot_from_id = (b_cfg.boot_cfg & BOOT_CFG_FROM_ID) && (b_cfg.boot_cfg & BOOT_CFG_AUTOBOOT_EN); if (boot_from_id) @@ -820,162 +773,154 @@ static void _auto_launch_firmware() LIST_INIT(ini_sections); LIST_INIT(ini_list_sections); - if (sd_mount()) + // Load emuMMC configuration. + emummc_load_cfg(); + + // Parse hekate main configuration. + if (!ini_parse(&ini_sections, "bootloader/hekate_ipl.ini", false)) + goto out; // Can't load hekate_ipl.ini. + + // Load configuration. + LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sections, link) { - if (f_stat("bootloader/hekate_ipl.ini", NULL)) - create_config_entry(); - - if (ini_parse(&ini_sections, "bootloader/hekate_ipl.ini", false)) + // Skip other ini entries for autoboot. + if (ini_sec->type == INI_CHOICE) { - u32 configEntry = 0; - u32 boot_entry_id = 0; - - // Load configuration. - LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sections, link) + if (!config_entry_found && !strcmp(ini_sec->name, "config")) { - // Skip other ini entries for autoboot. - if (ini_sec->type == INI_CHOICE) + config_entry_found = true; + LIST_FOREACH_ENTRY(ini_kv_t, kv, &ini_sec->kvs, link) { - if (!strcmp(ini_sec->name, "config")) - { - configEntry = 1; - LIST_FOREACH_ENTRY(ini_kv_t, kv, &ini_sec->kvs, link) - { - if (!strcmp("autoboot", kv->key)) - h_cfg.autoboot = atoi(kv->val); - else if (!strcmp("autoboot_list", kv->key)) - h_cfg.autoboot_list = atoi(kv->val); - else if (!strcmp("bootwait", kv->key)) - { - h_cfg.bootwait = atoi(kv->val); - - /* - * Clamp value to default if it exceeds 20s to protect against corruption. - * Allow up to 20s though for use in cases where user needs lots of time. - * For example dock-only use and r2p with enough time to reach dock and cancel it. - */ - if (h_cfg.bootwait > 20) - h_cfg.bootwait = 3; - } - else if (!strcmp("backlight", kv->key)) - h_cfg.backlight = atoi(kv->val); - else if (!strcmp("autohosoff", kv->key)) - h_cfg.autohosoff = atoi(kv->val); - else if (!strcmp("autonogc", kv->key)) - h_cfg.autonogc = atoi(kv->val); - else if (!strcmp("updater2p", kv->key)) - h_cfg.updater2p = atoi(kv->val); - else if (!strcmp("bootprotect", kv->key)) - h_cfg.bootprotect = atoi(kv->val); - } - boot_entry_id++; - - // Override autoboot. - if (b_cfg.boot_cfg & BOOT_CFG_AUTOBOOT_EN) - { - h_cfg.autoboot = b_cfg.autoboot; - h_cfg.autoboot_list = b_cfg.autoboot_list; - } - - // Apply bootloader protection against corruption. - _bootloader_corruption_protect(); - - continue; - } - - if (boot_from_id) - cfg_sec = get_ini_sec_from_id(ini_sec, &bootlogoCustomEntry, &emummc_path); - else if (h_cfg.autoboot == boot_entry_id && configEntry) - { - cfg_sec = ini_sec; - LIST_FOREACH_ENTRY(ini_kv_t, kv, &cfg_sec->kvs, link) - { - if (!strcmp("logopath", kv->key)) - bootlogoCustomEntry = kv->val; - else if (!strcmp("emummc_force_disable", kv->key)) - h_cfg.emummc_force_disable = atoi(kv->val); - else if (!strcmp("emupath", kv->key)) - emummc_path = kv->val; - } - } - if (cfg_sec) - break; - boot_entry_id++; + if (!strcmp("autoboot", kv->key)) + h_cfg.autoboot = atoi(kv->val); + else if (!strcmp("autoboot_list", kv->key)) + h_cfg.autoboot_list = atoi(kv->val); + else if (!strcmp("bootwait", kv->key)) + boot_wait = atoi(kv->val); + else if (!strcmp("backlight", kv->key)) + h_cfg.backlight = atoi(kv->val); + else if (!strcmp("noticker", kv->key)) + h_cfg.noticker = atoi(kv->val); + else if (!strcmp("autohosoff", kv->key)) + h_cfg.autohosoff = atoi(kv->val); + else if (!strcmp("autonogc", kv->key)) + h_cfg.autonogc = atoi(kv->val); + else if (!strcmp("updater2p", kv->key)) + h_cfg.updater2p = atoi(kv->val); + else if (!strcmp("bootprotect", kv->key)) + h_cfg.bootprotect = atoi(kv->val); } - } + boot_entry_id++; - if (h_cfg.autohosoff && !(b_cfg.boot_cfg & BOOT_CFG_AUTOBOOT_EN)) - check_power_off_from_hos(); - - if (h_cfg.autoboot_list || (boot_from_id && !cfg_sec)) - { - if (boot_from_id && cfg_sec) - goto skip_list; - - cfg_sec = NULL; - boot_entry_id = 1; - bootlogoCustomEntry = NULL; - - if (ini_parse(&ini_list_sections, "bootloader/ini", true)) + // Override autoboot. + if (b_cfg.boot_cfg & BOOT_CFG_AUTOBOOT_EN) { - LIST_FOREACH_ENTRY(ini_sec_t, ini_sec_list, &ini_list_sections, link) - { - if (ini_sec_list->type == INI_CHOICE) - { - if (!strcmp(ini_sec_list->name, "config")) - continue; - - if (boot_from_id) - cfg_sec = get_ini_sec_from_id(ini_sec_list, &bootlogoCustomEntry, &emummc_path); - else if (h_cfg.autoboot == boot_entry_id) - { - h_cfg.emummc_force_disable = false; - cfg_sec = ini_sec_list; - LIST_FOREACH_ENTRY(ini_kv_t, kv, &cfg_sec->kvs, link) - { - if (!strcmp("logopath", kv->key)) - bootlogoCustomEntry = kv->val; - else if (!strcmp("emummc_force_disable", kv->key)) - h_cfg.emummc_force_disable = atoi(kv->val); - else if (!strcmp("emupath", kv->key)) - emummc_path = kv->val; - } - } - if (cfg_sec) - break; - boot_entry_id++; - } - } - + h_cfg.autoboot = b_cfg.autoboot; + h_cfg.autoboot_list = b_cfg.autoboot_list; } - } -skip_list: - // Add missing configuration entry. - if (!configEntry) - create_config_entry(); + // Apply bootloader protection against corruption. + _bootloader_corruption_protect(); - if (!cfg_sec) - goto out; // No configurations or auto boot is disabled. + // If ini list, exit here. + if (!boot_from_id && h_cfg.autoboot_list) + break; + + continue; + } + + if (boot_from_id) + cfg_sec = _get_ini_sec_from_id(ini_sec, &bootlogoCustomEntry, &emummc_path); + else if (h_cfg.autoboot == boot_entry_id && config_entry_found) + { + cfg_sec = ini_sec; + LIST_FOREACH_ENTRY(ini_kv_t, kv, &cfg_sec->kvs, link) + { + if (!strcmp("logopath", kv->key)) + bootlogoCustomEntry = kv->val; + else if (!strcmp("emupath", kv->key)) + emummc_path = kv->val; + else if (!strcmp("emummc_force_disable", kv->key)) + h_cfg.emummc_force_disable = atoi(kv->val); + else if (!strcmp("bootwait", kv->key)) + boot_wait = atoi(kv->val); + } + } + if (cfg_sec) + break; + boot_entry_id++; } - else - goto out; // Can't load hekate_ipl.ini. } - else - goto out; - u8 *bitmap = NULL; - struct _bmp_data bmpData; - bool bootlogoFound = false; - if (!(b_cfg.boot_cfg & BOOT_CFG_FROM_LAUNCH) && h_cfg.bootwait) + if (h_cfg.autohosoff && !(b_cfg.boot_cfg & BOOT_CFG_AUTOBOOT_EN)) + _check_power_off_from_hos(); + + if (h_cfg.autoboot_list || (boot_from_id && !cfg_sec)) + { + if (boot_from_id && cfg_sec) + goto skip_list; + + cfg_sec = NULL; + boot_entry_id = 1; + bootlogoCustomEntry = NULL; + + if (!ini_parse(&ini_list_sections, "bootloader/ini", true)) + goto skip_list; + + LIST_FOREACH_ENTRY(ini_sec_t, ini_sec_list, &ini_list_sections, link) + { + if (ini_sec_list->type != INI_CHOICE) + continue; + + if (!strcmp(ini_sec_list->name, "config")) + continue; + + if (boot_from_id) + cfg_sec = _get_ini_sec_from_id(ini_sec_list, &bootlogoCustomEntry, &emummc_path); + else if (h_cfg.autoboot == boot_entry_id) + { + h_cfg.emummc_force_disable = false; + cfg_sec = ini_sec_list; + LIST_FOREACH_ENTRY(ini_kv_t, kv, &cfg_sec->kvs, link) + { + if (!strcmp("logopath", kv->key)) + bootlogoCustomEntry = kv->val; + else if (!strcmp("emupath", kv->key)) + emummc_path = kv->val; + else if (!strcmp("emummc_force_disable", kv->key)) + h_cfg.emummc_force_disable = atoi(kv->val); + else if (!strcmp("bootwait", kv->key)) + boot_wait = atoi(kv->val); + } + } + if (cfg_sec) + break; + boot_entry_id++; + } + } + +skip_list: + if (!cfg_sec) + goto out; // No configurations or auto boot is disabled. + + // Check if entry is payload or l4t special case. + char *special_path = ini_check_special_section(cfg_sec); + + if ((!(b_cfg.boot_cfg & BOOT_CFG_FROM_LAUNCH) && boot_wait) || // Conditional for HOS/Payload. + (special_path && special_path == (char *)-1)) // Always show for L4T. { u32 fsize; - u8 *BOOTLOGO = NULL; + u8 *logo_buf = NULL; + u8 *bitmap = NULL; + struct _bmp_data bmpData; + bool bootlogoFound = false; - if (bootlogoCustomEntry) // Check if user set custom logo path at the boot entry. + // Check if user set custom logo path at the boot entry. + if (bootlogoCustomEntry) bitmap = (u8 *)sd_file_read(bootlogoCustomEntry, &fsize); - if (!bitmap) // Custom entry bootlogo not found, trying default custom one. + // Custom entry bootlogo not found, trying default custom one. + if (!bitmap) bitmap = (u8 *)sd_file_read("bootloader/bootlogo.bmp", &fsize); if (bitmap) @@ -996,18 +941,18 @@ skip_list: bmpData.size_x <= 720 && bmpData.size_y <= 1280) { - if (bmpData.size <= fsize && ((bmpData.size - bmpData.offset) < 0x400000)) + if (bmpData.size <= fsize && ((bmpData.size - bmpData.offset) < SZ_4M)) { // Avoid unaligned access from BM 2-byte MAGIC and remove header. - BOOTLOGO = (u8 *)malloc(0x400000); - memcpy(BOOTLOGO, bitmap + bmpData.offset, bmpData.size - bmpData.offset); + logo_buf = (u8 *)malloc(SZ_4M); + memcpy(logo_buf, bitmap + bmpData.offset, bmpData.size - bmpData.offset); free(bitmap); // Center logo if res < 720x1280. bmpData.pos_x = (720 - bmpData.size_x) >> 1; bmpData.pos_y = (1280 - bmpData.size_y) >> 1; // Get background color from 1st pixel. if (bmpData.size_x < 720 || bmpData.size_y < 1280) - gfx_clear_color(*(u32 *)BOOTLOGO); + gfx_clear_color(*(u32 *)logo_buf); bootlogoFound = true; } @@ -1016,38 +961,42 @@ skip_list: free(bitmap); } + // Clamp value to default if it exceeds 20s to protect against corruption. + if (boot_wait > 20) + boot_wait = 3; + // Render boot logo. if (bootlogoFound) { - gfx_render_bmp_argb((u32 *)BOOTLOGO, bmpData.size_x, bmpData.size_y, + gfx_render_bmp_argb((u32 *)logo_buf, bmpData.size_x, bmpData.size_y, bmpData.pos_x, bmpData.pos_y); - free(BOOTLOGO); + free(logo_buf); + + // Do animated waiting before booting. If VOL- is pressed go into bootloader menu. + if (render_ticker(boot_wait, h_cfg.backlight, h_cfg.noticker)) + goto out; } else - render_default_bootlogo(); + { + // Do animated waiting before booting. If VOL- is pressed go into bootloader menu. + if (render_ticker_logo(boot_wait, h_cfg.backlight)) + goto out; + } } if (b_cfg.boot_cfg & BOOT_CFG_FROM_LAUNCH) display_backlight_brightness(h_cfg.backlight, 0); - else if (h_cfg.bootwait) - display_backlight_brightness(h_cfg.backlight, 1000); + else if (btn_read_vol() == BTN_VOL_DOWN) // 0s bootwait VOL- check. + goto out; - // Wait before booting. If VOL- is pressed go into bootloader menu. - if (!(b_cfg.boot_cfg & BOOT_CFG_FROM_LAUNCH)) + if (special_path) { - u32 btn = btn_wait_timeout_single(h_cfg.bootwait * 1000, BTN_VOL_DOWN | BTN_SINGLE); - - if (btn & BTN_VOL_DOWN) - goto out; - } - - char *payload_path = ini_check_payload_section(cfg_sec); - - if (payload_path) - { - launch_payload(payload_path, false, false); - free(payload_path); - goto payload_error; + // Try to launch Payload or L4T. + if (special_path != (char *)-1) + _launch_payload(special_path, false, false); + else + launch_l4t(cfg_sec, h_cfg.autoboot, h_cfg.autoboot_list, h_cfg.t210b01); + goto error; } else { @@ -1063,15 +1012,13 @@ skip_list: hos_launch(cfg_sec); wrong_emupath: - EPRINTF("\nFailed to launch HOS!"); - if (emummc_path || b_cfg.boot_cfg & BOOT_CFG_TO_EMUMMC) { sd_mount(); - emummc_load_cfg(); + emummc_load_cfg(); // Reload emuMMC config in case of emupath. } -payload_error: +error: gfx_con.mute = false; gfx_printf("\nPress any key...\n"); display_backlight_brightness(h_cfg.backlight, 1000); @@ -1090,76 +1037,59 @@ out: // L4T: Clear custom boot mode flags from PMC_SCRATCH0. PMC(APBDEV_PMC_SCRATCH0) &= ~PMC_SCRATCH0_MODE_CUSTOM_ALL; - nyx_load_run(); -} - -static void _patched_rcm_protection() -{ - if (!h_cfg.rcm_patched || hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01) - return; - - // Check if AutoRCM is enabled and protect from a permanent brick. - if (!sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400)) - return; - - u8 *buf = (u8 *)malloc(0x200); - sdmmc_storage_set_mmc_partition(&emmc_storage, EMMC_BOOT0); - - u32 sector; - u8 corr_mod0, mod1; - - // Get the correct RSA modulus byte masks. - nx_emmc_get_autorcm_masks(&corr_mod0, &mod1); - - // Iterate BCTs. - for (u32 i = 0; i < 4; i++) - { - sector = 1 + (32 * i); // 0x4000 bct + 0x200 offset. - sdmmc_storage_read(&emmc_storage, sector, 1, buf); - - // Check if 2nd byte of modulus is correct. - if (buf[0x11] != mod1) - continue; - - // If AutoRCM is enabled, disable it. - if (buf[0x10] != corr_mod0) - { - buf[0x10] = corr_mod0; - - sdmmc_storage_write(&emmc_storage, sector, 1, buf); - } - } - - free(buf); - sdmmc_storage_end(&emmc_storage); + _nyx_load_run(); } #define EXCP_EN_ADDR 0x4003FFFC -#define EXCP_MAGIC 0x30505645 // EVP0 +#define EXCP_MAGIC 0x30505645 // "EVP0". #define EXCP_TYPE_ADDR 0x4003FFF8 -#define EXCP_TYPE_RESET 0x545352 // RST -#define EXCP_TYPE_UNDEF 0x464455 // UDF -#define EXCP_TYPE_PABRT 0x54424150 // PABT -#define EXCP_TYPE_DABRT 0x54424144 // DABT +#define EXCP_TYPE_RESET 0x545352 // "RST". +#define EXCP_TYPE_UNDEF 0x464455 // "UDF". +#define EXCP_TYPE_PABRT 0x54424150 // "PABT". +#define EXCP_TYPE_DABRT 0x54424144 // "DABT". +#define EXCP_TYPE_WDT 0x544457 // "WDT". #define EXCP_LR_ADDR 0x4003FFF4 +#define PSTORE_LOG_OFFSET 0x180000 +#define PSTORE_RAM_SIG 0x43474244 // "DBGC". + +typedef struct _pstore_buf { + u32 sig; + u32 start; + u32 size; +} pstore_buf_t; + static void _show_errors() { - u32 *excp_enabled = (u32 *)EXCP_EN_ADDR; - u32 *excp_type = (u32 *)EXCP_TYPE_ADDR; u32 *excp_lr = (u32 *)EXCP_LR_ADDR; + u32 *excp_type = (u32 *)EXCP_TYPE_ADDR; + u32 *excp_enabled = (u32 *)EXCP_EN_ADDR; + u32 panic_status = hw_rst_status & 0xFFFFF; + + // Check for exception error. if (*excp_enabled == EXCP_MAGIC) h_cfg.errors |= ERR_EXCEPTION; - //! FIXME: Find a better way to identify if that scratch has proper data. - if (0 && PMC(APBDEV_PMC_SCRATCH37) & PMC_SCRATCH37_KERNEL_PANIC_FLAG) + // Check for L4T kernel panic. + if (PMC(APBDEV_PMC_SCRATCH37) == PMC_SCRATCH37_KERNEL_PANIC_MAGIC) { // Set error and clear flag. h_cfg.errors |= ERR_L4T_KERNEL; - PMC(APBDEV_PMC_SCRATCH37) &= ~PMC_SCRATCH37_KERNEL_PANIC_FLAG; + PMC(APBDEV_PMC_SCRATCH37) = 0; } + // Check for watchdog panic. + if (hw_rst_reason == PMC_RST_STATUS_WATCHDOG && panic_status && + panic_status <= 0xFF && panic_status != 0x20 && panic_status != 0x21) + { + h_cfg.errors |= ERR_PANIC_CODE; + } + + // Check if we had a panic while in CFW. + secmon_exo_check_panic(); + + // Handle errors. if (h_cfg.errors) { gfx_clear_grey(0x1B); @@ -1167,21 +1097,29 @@ static void _show_errors() display_backlight_brightness(150, 1000); if (h_cfg.errors & ERR_SD_BOOT_EN) - WPRINTF("Failed to mount SD!\n"); + { + WPRINTF("Failed to init or mount SD!\n"); + + // Clear the module bits as to not cram the error screen. + h_cfg.errors &= ~(ERR_LIBSYS_LP0 | ERR_LIBSYS_MTC); + } if (h_cfg.errors & ERR_LIBSYS_LP0) - WPRINTF("Missing LP0 (sleep mode) lib!\n"); + WPRINTF("Missing LP0 (sleep) lib!\n"); if (h_cfg.errors & ERR_LIBSYS_MTC) - WPRINTF("Missing or old Minerva lib!\n"); + WPRINTF("Missing Minerva lib!\n"); if (h_cfg.errors & (ERR_LIBSYS_LP0 | ERR_LIBSYS_MTC)) WPRINTF("\nUpdate bootloader folder!\n\n"); if (h_cfg.errors & ERR_EXCEPTION) { - WPRINTFARGS("An exception occurred (LR %08X):\n", *excp_lr); + WPRINTFARGS("hekate exception occurred (LR %08X):\n", *excp_lr); switch (*excp_type) { + case EXCP_TYPE_WDT: + WPRINTF("Hang detected in LP0/Minerva!"); + break; case EXCP_TYPE_RESET: WPRINTF("RESET"); break; @@ -1195,23 +1133,50 @@ static void _show_errors() WPRINTF("DABRT"); break; } - WPRINTF("\n"); + gfx_puts("\n"); // Clear the exception. *excp_enabled = 0; + *excp_type = 0; } - if (0 && h_cfg.errors & ERR_L4T_KERNEL) + if (h_cfg.errors & ERR_L4T_KERNEL) { - WPRINTF("Panic occurred while running L4T.\n"); - if (!sd_save_to_file((void *)PSTORE_ADDR, PSTORE_SZ, "L4T_panic.bin")) - WPRINTF("PSTORE saved to L4T_panic.bin\n"); + WPRINTF("L4T Kernel panic occurred!\n"); + if (!(h_cfg.errors & ERR_SD_BOOT_EN)) + { + if (!sd_save_to_file((void *)PSTORE_ADDR, PSTORE_SZ, "L4T_panic.bin")) + WPRINTF("PSTORE saved to L4T_panic.bin"); + pstore_buf_t *buf = (pstore_buf_t *)(PSTORE_ADDR + PSTORE_LOG_OFFSET); + if (buf->sig == PSTORE_RAM_SIG && buf->size && buf->size < 0x80000) + { + u32 log_offset = PSTORE_ADDR + PSTORE_LOG_OFFSET + sizeof(pstore_buf_t); + if (!sd_save_to_file((void *)log_offset, buf->size, "L4T_panic.txt")) + WPRINTF("Log saved to L4T_panic.txt"); + } + } + gfx_puts("\n"); + } + + if (h_cfg.errors & ERR_PANIC_CODE) + { + u32 r = (hw_rst_status >> 20) & 0xF; + u32 g = (hw_rst_status >> 24) & 0xF; + u32 b = (hw_rst_status >> 28) & 0xF; + r = (r << 16) | (r << 20); + g = (g << 8) | (g << 12); + b = (b << 0) | (b << 4); + u32 color = r | g | b; + + WPRINTF("HOS panic occurred!\n"); + gfx_printf("Color: %k####%k, Code: %02X\n\n", color, TXT_CLR_DEFAULT, panic_status); } WPRINTF("Press any key..."); - msleep(1000); + msleep(1000); // Guard against injection VOL+. btn_wait(); + msleep(500); // Guard against force menu VOL-. } } @@ -1224,27 +1189,31 @@ static void _check_low_battery() int batt_volt = 0; int charge_status = 0; + // Enable charger in case it's disabled. + bq24193_enable_charger(); + bq24193_get_property(BQ24193_ChargeStatus, &charge_status); - max17050_get_property(MAX17050_AvgVCELL, &batt_volt); + max17050_get_property(MAX17050_AvgVCELL, &batt_volt); - enough_battery = charge_status ? 3250 : 3000; + enough_battery = charge_status ? 3300 : 3100; + // If battery voltage is enough, exit. if (batt_volt > enough_battery || !batt_volt) goto out; // Prepare battery icon resources. - u8 *battery_res = malloc(ALIGN(SZ_BATTERY_EMPTY, 0x1000)); - blz_uncompress_srcdest(BATTERY_EMPTY_BLZ, SZ_BATTERY_EMPTY_BLZ, battery_res, SZ_BATTERY_EMPTY); + u8 *battery_res = malloc(ALIGN(BATTERY_EMPTY_SIZE, SZ_4K)); + blz_uncompress_srcdest(battery_icons_blz, BATTERY_EMPTY_BLZ_SIZE, battery_res, BATTERY_EMPTY_SIZE); - u8 *battery_icon = malloc(0x95A); // 21x38x3 - u8 *charging_icon = malloc(0x2F4); // 21x12x3 - u8 *no_charging_icon = calloc(0x2F4, 1); + u8 *battery_icon = malloc(0x95A); // 21x38x3 + u8 *charging_icon = malloc(0x2F4); // 21x12x3 + u8 *no_charging_icon = zalloc(0x2F4); memcpy(charging_icon, battery_res, 0x2F4); memcpy(battery_icon, battery_res + 0x2F4, 0x95A); - u32 battery_icon_y_pos = 1280 - 16 - Y_BATTERY_EMPTY_BATT; - u32 charging_icon_y_pos = 1280 - 16 - Y_BATTERY_EMPTY_BATT - 12 - Y_BATTERY_EMPTY_CHRG; + u32 battery_icon_y_pos = 1280 - 16 - BATTERY_EMPTY_BATT_HEIGHT; + u32 charging_icon_y_pos = 1280 - 16 - BATTERY_EMPTY_BATT_HEIGHT - 12 - BATTERY_EMPTY_CHRG_HEIGHT; free(battery_res); charge_status = !charge_status; @@ -1259,8 +1228,9 @@ static void _check_low_battery() int current_charge_status = 0; bq24193_get_property(BQ24193_ChargeStatus, ¤t_charge_status); max17050_get_property(MAX17050_AvgVCELL, &batt_volt); - enough_battery = current_charge_status ? 3250 : 3000; + enough_battery = current_charge_status ? 3300 : 3100; + // If battery voltage is enough, exit. if (batt_volt > enough_battery) break; @@ -1268,38 +1238,42 @@ static void _check_low_battery() if (screen_on && (charge_status != current_charge_status)) { if (current_charge_status) - gfx_set_rect_rgb(charging_icon, X_BATTERY_EMPTY, Y_BATTERY_EMPTY_CHRG, 16, charging_icon_y_pos); + gfx_set_rect_rgb(charging_icon, BATTERY_EMPTY_WIDTH, BATTERY_EMPTY_CHRG_HEIGHT, 16, charging_icon_y_pos); else - gfx_set_rect_rgb(no_charging_icon, X_BATTERY_EMPTY, Y_BATTERY_EMPTY_CHRG, 16, charging_icon_y_pos); + gfx_set_rect_rgb(no_charging_icon, BATTERY_EMPTY_WIDTH, BATTERY_EMPTY_CHRG_HEIGHT, 16, charging_icon_y_pos); } // Check if it's time to turn off display. if (screen_on && timer < get_tmr_ms()) { + // If battery is not charging, power off. if (!current_charge_status) { max77620_low_battery_monitor_config(true); + + // Handle full hw deinit and power off. power_set_state(POWER_OFF_RESET); } + // If charging, just disable display. display_end(); screen_on = false; } - // Check if charging status changed or Power button was pressed. + // Check if charging status changed or Power button was pressed and enable display. if ((charge_status != current_charge_status) || (btn_wait_timeout_single(0, BTN_POWER) & BTN_POWER)) { if (!screen_on) { display_init(); - u32 *fb = display_init_framebuffer_pitch(); + u32 *fb = display_init_window_a_pitch(); gfx_init_ctxt(fb, 720, 1280, 720); - gfx_set_rect_rgb(battery_icon, X_BATTERY_EMPTY, Y_BATTERY_EMPTY_BATT, 16, battery_icon_y_pos); + gfx_set_rect_rgb(battery_icon, BATTERY_EMPTY_WIDTH, BATTERY_EMPTY_BATT_HEIGHT, 16, battery_icon_y_pos); if (current_charge_status) - gfx_set_rect_rgb(charging_icon, X_BATTERY_EMPTY, Y_BATTERY_EMPTY_CHRG, 16, charging_icon_y_pos); + gfx_set_rect_rgb(charging_icon, BATTERY_EMPTY_WIDTH, BATTERY_EMPTY_CHRG_HEIGHT, 16, charging_icon_y_pos); else - gfx_set_rect_rgb(no_charging_icon, X_BATTERY_EMPTY, Y_BATTERY_EMPTY_CHRG, 16, charging_icon_y_pos); + gfx_set_rect_rgb(no_charging_icon, BATTERY_EMPTY_WIDTH, BATTERY_EMPTY_CHRG_HEIGHT, 16, charging_icon_y_pos); display_backlight_pwm_init(); display_backlight_brightness(100, 1000); @@ -1317,7 +1291,8 @@ static void _check_low_battery() charge_status = current_charge_status; } - display_end(); + if (screen_on) + display_end(); free(battery_icon); free(charging_icon); @@ -1328,9 +1303,47 @@ out: max77620_low_battery_monitor_config(true); } -void ipl_reload() +static void _r2c_get_config_t210b01() { - hw_reinit_workaround(false, 0); + rtc_reboot_reason_t rr; + if (!max77620_rtc_get_reboot_reason(&rr)) + return; + + // Check if reason is actually set. + if (rr.dec.reason != REBOOT_REASON_NOP) + { + // Clear boot storage. + memset(&b_cfg, 0, sizeof(boot_cfg_t)); + + // Enable boot storage. + b_cfg.boot_cfg |= BOOT_CFG_AUTOBOOT_EN; + } + + switch (rr.dec.reason) + { + case REBOOT_REASON_NOP: + break; + case REBOOT_REASON_REC: + PMC(APBDEV_PMC_SCRATCH0) |= PMC_SCRATCH0_MODE_RECOVERY; + case REBOOT_REASON_SELF: + b_cfg.autoboot = rr.dec.autoboot_idx; + b_cfg.autoboot_list = rr.dec.autoboot_list; + break; + case REBOOT_REASON_MENU: + break; + case REBOOT_REASON_UMS: + b_cfg.extra_cfg |= EXTRA_CFG_NYX_UMS; + b_cfg.ums = rr.dec.ums_idx; + break; + case REBOOT_REASON_PANIC: + PMC(APBDEV_PMC_SCRATCH37) = PMC_SCRATCH37_KERNEL_PANIC_MAGIC; + break; + } +} + +static void _ipl_reload() +{ + hw_deinit(false, 0); // Reload hekate. void (*ipl_ptr)() = (void *)IPL_LOAD_ADDR; @@ -1341,7 +1354,7 @@ static void _about() { static const char credits[] = "\nhekate (c) 2018, naehrwert, st4rk\n\n" - " (c) 2018-2021, CTCaer\n\n" + " (c) 2018-2025, CTCaer\n\n" " ___________________________________________\n\n" "Thanks to: %kderrek, nedwill, plutoo,\n" " shuffle2, smea, thexyz, yellows8%k\n" @@ -1350,12 +1363,13 @@ static void _about() " Shiny Quagsire, WinterMute\n" " ___________________________________________\n\n" "Open source and free packages used:\n\n" - " - FatFs R0.13b\n" - " (c) 2018, ChaN\n\n" + " - FatFs R0.13c\n" + " (c) 2006-2018, ChaN\n" + " (c) 2018-2022, CTCaer\n\n" " - bcl-1.2.0\n" " (c) 2003-2006, Marcus Geelnard\n\n" - " - Atmosphere (Exo st/types, prc id patches)\n" - " (c) 2018-2019, Atmosphere-NX\n\n" + " - blz\n" + " (c) 2018, SciresM\n\n" " - elfload\n" " (c) 2014, Owen Shepherd\n" " (c) 2018, M4xw\n" @@ -1383,9 +1397,9 @@ static void _about() gfx_clear_grey(0x1B); gfx_con_setpos(0, 0); - gfx_printf(credits, 0xFF00CCFF, 0xFFCCCCCC); + gfx_printf(credits, TXT_CLR_CYAN_L, TXT_CLR_DEFAULT); gfx_con.fntsz = 8; - gfx_printf(octopus, 0xFF00CCFF, 0xFF00FFCC, 0xFF00CCFF, 0xFFCCCCCC); + gfx_printf(octopus, TXT_CLR_CYAN_L, TXT_CLR_TURQUOISE, TXT_CLR_CYAN_L, TXT_CLR_DEFAULT); btn_wait(); } @@ -1393,62 +1407,24 @@ static void _about() ment_t ment_cinfo[] = { MDEF_BACK(), MDEF_CHGLINE(), - MDEF_CAPTION("---- SoC Info ----", 0xFF0AB9E6), - MDEF_HANDLER("Ipatches & bootrom", bootrom_ipatches_info), + MDEF_CAPTION("---- SoC Info ----", TXT_CLR_CYAN_L), MDEF_HANDLER("Fuses", print_fuseinfo), - //MDEF_HANDLER("Print kfuse info", print_kfuseinfo), MDEF_CHGLINE(), - MDEF_CAPTION("-- Storage Info --", 0xFF0AB9E6), - MDEF_HANDLER("eMMC", print_mmc_info), + MDEF_CAPTION("-- Storage Info --", TXT_CLR_CYAN_L), + MDEF_HANDLER("eMMC", print_mmc_info), MDEF_HANDLER("SD Card", print_sdcard_info), MDEF_CHGLINE(), - MDEF_CAPTION("------ Misc ------", 0xFF0AB9E6), + MDEF_CAPTION("------ Misc ------", TXT_CLR_CYAN_L), MDEF_HANDLER("Battery", print_battery_info), MDEF_END() }; menu_t menu_cinfo = { ment_cinfo, "Console Info", 0, 0 }; -ment_t ment_restore[] = { - MDEF_BACK(), - MDEF_CHGLINE(), - MDEF_CAPTION("------ Full --------", 0xFF0AB9E6), - MDEF_HANDLER("Restore eMMC BOOT0/1", restore_emmc_boot), - MDEF_HANDLER("Restore eMMC RAW GPP", restore_emmc_rawnand), - MDEF_CHGLINE(), - MDEF_CAPTION("-- GPP Partitions --", 0xFF0AB9E6), - MDEF_HANDLER("Restore GPP partitions", restore_emmc_gpp_parts), - MDEF_END() -}; - -menu_t menu_restore = { ment_restore, "Restore Options", 0, 0 }; - -ment_t ment_backup[] = { - MDEF_BACK(), - MDEF_CHGLINE(), - MDEF_CAPTION("------ Full --------", 0xFF0AB9E6), - MDEF_HANDLER("Backup eMMC BOOT0/1", dump_emmc_boot), - MDEF_HANDLER("Backup eMMC RAW GPP", dump_emmc_rawnand), - MDEF_CHGLINE(), - MDEF_CAPTION("-- GPP Partitions --", 0xFF0AB9E6), - MDEF_HANDLER("Backup eMMC SYS", dump_emmc_system), - MDEF_HANDLER("Backup eMMC USER", dump_emmc_user), - MDEF_END() -}; - -menu_t menu_backup = { ment_backup, "Backup Options", 0, 0 }; - ment_t ment_tools[] = { MDEF_BACK(), MDEF_CHGLINE(), - //MDEF_CAPTION("-- Backup & Restore --", 0xFF0AB9E6), - //MDEF_MENU("Backup", &menu_backup), - //MDEF_MENU("Restore", &menu_restore), - //MDEF_CHGLINE(), - //MDEF_CAPTION("-------- Misc --------", 0xFF0AB9E6), - //MDEF_HANDLER("Dump package1/2", dump_packages12), - //MDEF_CHGLINE(), - MDEF_CAPTION("-------- Other -------", 0xFFFFDD00), + MDEF_CAPTION("-------- Other -------", TXT_CLR_WARNING), MDEF_HANDLER("AutoRCM", menu_autorcm), MDEF_END() }; @@ -1460,21 +1436,21 @@ power_state_t STATE_REBOOT_RCM = REBOOT_RCM; power_state_t STATE_REBOOT_BYPASS_FUSES = REBOOT_BYPASS_FUSES; ment_t ment_top[] = { - MDEF_HANDLER("Launch", launch_firmware), - MDEF_CAPTION("---------------", 0xFF444444), + MDEF_HANDLER("Launch", _launch_config), + MDEF_CAPTION("---------------", TXT_CLR_GREY_DM), MDEF_MENU("Tools", &menu_tools), MDEF_MENU("Console info", &menu_cinfo), - MDEF_CAPTION("---------------", 0xFF444444), - MDEF_HANDLER("Reload", ipl_reload), + MDEF_CAPTION("---------------", TXT_CLR_GREY_DM), + MDEF_HANDLER("Reload", _ipl_reload), MDEF_HANDLER_EX("Reboot (OFW)", &STATE_REBOOT_BYPASS_FUSES, power_set_state_ex), MDEF_HANDLER_EX("Reboot (RCM)", &STATE_REBOOT_RCM, power_set_state_ex), MDEF_HANDLER_EX("Power off", &STATE_POWER_OFF, power_set_state_ex), - MDEF_CAPTION("---------------", 0xFF444444), + MDEF_CAPTION("---------------", TXT_CLR_GREY_DM), MDEF_HANDLER("About", _about), MDEF_END() }; -menu_t menu_top = { ment_top, "hekate v5.6.2", 0, 0 }; +menu_t menu_top = { ment_top, "hekate v6.3.1", 0, 0 }; extern void pivot_stack(u32 stack_top); @@ -1483,15 +1459,15 @@ void ipl_main() // Do initial HW configuration. This is compatible with consecutive reruns without a reset. hw_init(); - // Pivot the stack so we have enough space. - pivot_stack(IPL_STACK_TOP); + // Pivot the stack under IPL. (Only max 4KB is needed). + pivot_stack(IPL_LOAD_ADDR); - // Tegra/Horizon configuration goes to 0x80000000+, package2 goes to 0xA9800000, we place our heap in between. - heap_init(IPL_HEAP_START); + // Place heap at a place outside of L4T/HOS configuration and binaries. + heap_init((void *)IPL_HEAP_START); #ifdef DEBUG_UART_PORT uart_send(DEBUG_UART_PORT, (u8 *)"hekate: Hello!\r\n", 16); - uart_wait_idle(DEBUG_UART_PORT, UART_TX_IDLE); + uart_wait_xfer(DEBUG_UART_PORT, UART_TX_IDLE); #endif // Check if battery is enough. @@ -1500,9 +1476,25 @@ void ipl_main() // Set bootloader's default configuration. set_default_configuration(); + // Prep RTC regs for read. Needed for T210B01 R2C. + max77620_rtc_prep_read(); + + // Initialize display. + display_init(); + + // Overclock BPMP. + bpmp_clk_rate_set(h_cfg.t210b01 ? BPMP_CLK_DEFAULT_BOOST : BPMP_CLK_LOWER_BOOST); + // Mount SD Card. h_cfg.errors |= !sd_mount() ? ERR_SD_BOOT_EN : 0; + // Check if watchdog was fired previously. + if (watchdog_fired()) + goto skip_lp0_minerva_config; + + // Enable watchdog protection to avoid SD corruption based hanging in LP0/Minerva config. + watchdog_start(5000000 / 2, TIMER_FIQENABL_EN); // 5 seconds. + // Save sdram lp0 config. void *sdram_params = h_cfg.t210b01 ? sdram_get_params_t210b01() : sdram_get_params_patched(); if (!ianos_loader("bootloader/sys/libsys_lp0.bso", DRAM_LIB, sdram_params)) @@ -1512,37 +1504,34 @@ void ipl_main() if (minerva_init()) //!TODO: Add Tegra210B01 support to minerva. h_cfg.errors |= ERR_LIBSYS_MTC; - display_init(); + // Disable watchdog protection. + watchdog_end(); - u32 *fb = display_init_framebuffer_pitch(); +skip_lp0_minerva_config: + // Initialize display window, backlight and gfx console. + u32 *fb = display_init_window_a_pitch(); gfx_init_ctxt(fb, 720, 1280, 720); - gfx_con_init(); + // Initialize backlight PWM. display_backlight_pwm_init(); //display_backlight_brightness(h_cfg.backlight, 1000); - // Overclock BPMP. - bpmp_clk_rate_set(h_cfg.t210b01 ? BPMP_CLK_DEFAULT_BOOST : BPMP_CLK_LOWER_BOOST); + // Get R2C config from RTC. + if (h_cfg.t210b01) + _r2c_get_config_t210b01(); - // Check if we had a panic while in CFW. - secmon_exo_check_panic(); - - // Check if RCM is patched and protect from a possible brick. - _patched_rcm_protection(); - - // Load emuMMC configuration from SD. - emummc_load_cfg(); - - // Show exception, library errors and L4T kernel panics. + // Show exceptions, HOS errors, library errors and L4T kernel panics. _show_errors(); // Load saved configuration and auto boot if enabled. - _auto_launch_firmware(); + if (!(h_cfg.errors & ERR_SD_BOOT_EN)) + _auto_launch(); // Failed to launch Nyx, unmount SD Card. sd_end(); + // Set ram to a freq that doesn't need periodic training. minerva_change_freq(FREQ_800); while (true) diff --git a/bootloader/start.S b/bootloader/start.S index 269f2c7..d1def0a 100644 --- a/bootloader/start.S +++ b/bootloader/start.S @@ -60,7 +60,8 @@ _reloc_ipl: BX R3 _real_start: - /* Initially, we place our stack in IRAM but will move it to SDRAM later. */ + /* Initially, we place our stack under relocator but will move it to under the payload. */ + /* This depends on application scope. */ LDR SP, =0x4003FF00 LDR R0, =__bss_start EOR R1, R1, R1 diff --git a/bootloader/storage/emummc.c b/bootloader/storage/emummc.c index 62e3578..64fe907 100644 --- a/bootloader/storage/emummc.c +++ b/bootloader/storage/emummc.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021 CTCaer + * Copyright (c) 2019-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,17 +17,11 @@ #include #include +#include + #include "emummc.h" -#include #include "../config.h" -#include -#include #include -#include -#include "../storage/nx_emmc.h" -#include -#include -#include extern hekate_config h_cfg; emummc_cfg_t emu_cfg = { 0 }; @@ -42,9 +36,9 @@ void emummc_load_cfg() emu_cfg.active_part = 0; emu_cfg.fs_ver = 0; if (!emu_cfg.nintendo_path) - emu_cfg.nintendo_path = (char *)malloc(0x80); + emu_cfg.nintendo_path = (char *)malloc(0x200); if (!emu_cfg.emummc_file_based_path) - emu_cfg.emummc_file_based_path = (char *)malloc(0x80); + emu_cfg.emummc_file_based_path = (char *)malloc(0x200); emu_cfg.nintendo_path[0] = 0; emu_cfg.emummc_file_based_path[0] = 0; @@ -61,14 +55,14 @@ void emummc_load_cfg() LIST_FOREACH_ENTRY(ini_kv_t, kv, &ini_sec->kvs, link) { - if (!strcmp("enabled", kv->key)) + if (!strcmp("enabled", kv->key)) emu_cfg.enabled = atoi(kv->val); - else if (!strcmp("sector", kv->key)) - emu_cfg.sector = strtol(kv->val, NULL, 16); - else if (!strcmp("id", kv->key)) - emu_cfg.id = strtol(kv->val, NULL, 16); - else if (!strcmp("path", kv->key)) - emu_cfg.path = kv->val; + else if (!strcmp("sector", kv->key)) + emu_cfg.sector = strtol(kv->val, NULL, 16); + else if (!strcmp("id", kv->key)) + emu_cfg.id = strtol(kv->val, NULL, 16); + else if (!strcmp("path", kv->key)) + emu_cfg.path = kv->val; else if (!strcmp("nintendo_path", kv->key)) strcpy(emu_cfg.nintendo_path, kv->val); } @@ -144,7 +138,7 @@ int emummc_storage_init_mmc() emu_cfg.active_part = 0; // Always init eMMC even when in emuMMC. eMMC is needed from the emuMMC driver anyway. - if (!sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400)) + if (!emmc_initialize(false)) return 2; if (!emu_cfg.enabled || h_cfg.emummc_force_disable) @@ -183,7 +177,7 @@ out: int emummc_storage_end() { if (!emu_cfg.enabled || h_cfg.emummc_force_disable) - sdmmc_storage_end(&emmc_storage); + emmc_end(); else sd_end(); @@ -279,7 +273,7 @@ int emummc_storage_write(u32 sector, u32 num_sectors, void *buf) int emummc_storage_set_mmc_partition(u32 partition) { emu_cfg.active_part = partition; - sdmmc_storage_set_mmc_partition(&emmc_storage, partition); + emmc_set_partition(partition); if (!emu_cfg.enabled || h_cfg.emummc_force_disable || emu_cfg.sector) return 1; diff --git a/bootloader/storage/emummc.h b/bootloader/storage/emummc.h index 7e162fd..617b36b 100644 --- a/bootloader/storage/emummc.h +++ b/bootloader/storage/emummc.h @@ -17,8 +17,7 @@ #ifndef EMUMMC_H #define EMUMMC_H -#include -#include +#include typedef enum { diff --git a/bootloader/storage/nx_emmc.c b/bootloader/storage/nx_emmc.c deleted file mode 100644 index 223c449..0000000 --- a/bootloader/storage/nx_emmc.c +++ /dev/null @@ -1,110 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2019-2021 CTCaer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -#include "nx_emmc.h" -#include "emummc.h" -#include -#include -#include -#include - -sdmmc_t emmc_sdmmc; -sdmmc_storage_t emmc_storage; -FATFS emmc_fs; - -void nx_emmc_gpt_parse(link_t *gpt, sdmmc_storage_t *storage) -{ - gpt_t *gpt_buf = (gpt_t *)calloc(NX_GPT_NUM_BLOCKS, NX_EMMC_BLOCKSIZE); - - emummc_storage_read(NX_GPT_FIRST_LBA, NX_GPT_NUM_BLOCKS, gpt_buf); - - // Check if no GPT or more than max allowed entries. - if (memcmp(&gpt_buf->header.signature, "EFI PART", 8) || gpt_buf->header.num_part_ents > 128) - goto out; - - for (u32 i = 0; i < gpt_buf->header.num_part_ents; i++) - { - emmc_part_t *part = (emmc_part_t *)calloc(sizeof(emmc_part_t), 1); - - if (gpt_buf->entries[i].lba_start < gpt_buf->header.first_use_lba) - continue; - - part->index = i; - part->lba_start = gpt_buf->entries[i].lba_start; - part->lba_end = gpt_buf->entries[i].lba_end; - part->attrs = gpt_buf->entries[i].attrs; - - // ASCII conversion. Copy only the LSByte of the UTF-16LE name. - for (u32 j = 0; j < 36; j++) - part->name[j] = gpt_buf->entries[i].name[j]; - part->name[35] = 0; - - list_append(gpt, &part->link); - } - -out: - free(gpt_buf); -} - -void nx_emmc_gpt_free(link_t *gpt) -{ - LIST_FOREACH_SAFE(iter, gpt) - free(CONTAINER_OF(iter, emmc_part_t, link)); -} - -emmc_part_t *nx_emmc_part_find(link_t *gpt, const char *name) -{ - LIST_FOREACH_ENTRY(emmc_part_t, part, gpt, link) - if (!strcmp(part->name, name)) - return part; - - return NULL; -} - -int nx_emmc_part_read(sdmmc_storage_t *storage, emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf) -{ - // The last LBA is inclusive. - if (part->lba_start + sector_off > part->lba_end) - return 0; - - return emummc_storage_read(part->lba_start + sector_off, num_sectors, buf); -} - -int nx_emmc_part_write(sdmmc_storage_t *storage, emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf) -{ - // The last LBA is inclusive. - if (part->lba_start + sector_off > part->lba_end) - return 0; - - return emummc_storage_write(part->lba_start + sector_off, num_sectors, buf); -} - -void nx_emmc_get_autorcm_masks(u8 *mod0, u8 *mod1) -{ - if (fuse_read_hw_state() == FUSE_NX_HW_STATE_PROD) - { - *mod0 = 0xF7; - *mod1 = 0x86; - } - else - { - *mod0 = 0x37; - *mod1 = 0x84; - } -} diff --git a/bootloader/storage/nx_emmc.h b/bootloader/storage/nx_emmc.h deleted file mode 100644 index f89f526..0000000 --- a/bootloader/storage/nx_emmc.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2019-2020 CTCaer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#ifndef _NX_EMMC_H_ -#define _NX_EMMC_H_ - -#include -#include -#include -#include - -#define NX_GPT_FIRST_LBA 1 -#define NX_GPT_NUM_BLOCKS 33 -#define NX_EMMC_BLOCKSIZE 512 - -typedef struct _emmc_part_t -{ - u32 index; - u32 lba_start; - u32 lba_end; - u64 attrs; - char name[37]; - link_t link; -} emmc_part_t; - -extern sdmmc_t emmc_sdmmc; -extern sdmmc_storage_t emmc_storage; -extern FATFS emmc_fs; - -void nx_emmc_gpt_parse(link_t *gpt, sdmmc_storage_t *storage); -void nx_emmc_gpt_free(link_t *gpt); -emmc_part_t *nx_emmc_part_find(link_t *gpt, const char *name); -int nx_emmc_part_read(sdmmc_storage_t *storage, emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf); -int nx_emmc_part_write(sdmmc_storage_t *storage, emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf); - -void nx_emmc_get_autorcm_masks(u8 *mod0, u8 *mod1); - -#endif diff --git a/bootloader/storage/nx_sd.c b/bootloader/storage/nx_sd.c deleted file mode 100644 index f2cec2f..0000000 --- a/bootloader/storage/nx_sd.c +++ /dev/null @@ -1,233 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include -#include -#include -#include -#include -#include - -static bool sd_mounted = false; -static u16 sd_errors[3] = { 0 }; // Init and Read/Write errors. -static u32 sd_mode = SD_UHS_SDR82; - -sdmmc_t sd_sdmmc; -sdmmc_storage_t sd_storage; -FATFS sd_fs; - -void sd_error_count_increment(u8 type) -{ - switch (type) - { - case SD_ERROR_INIT_FAIL: - sd_errors[0]++; - break; - case SD_ERROR_RW_FAIL: - sd_errors[1]++; - break; - case SD_ERROR_RW_RETRY: - sd_errors[2]++; - break; - } -} - -u16 *sd_get_error_count() -{ - return sd_errors; -} - -bool sd_get_card_removed() -{ - if (!sdmmc_get_sd_inserted()) - return true; - - return false; -} - -bool sd_get_card_mounted() -{ - return sd_mounted; -} - -u32 sd_get_mode() -{ - return sd_mode; -} - -int sd_init_retry(bool power_cycle) -{ - u32 bus_width = SDMMC_BUS_WIDTH_4; - u32 type = SDHCI_TIMING_UHS_SDR82; - - // Power cycle SD card. - if (power_cycle) - { - sd_mode--; - sdmmc_storage_end(&sd_storage); - } - - // Get init parameters. - switch (sd_mode) - { - case SD_INIT_FAIL: // Reset to max. - return 0; - case SD_1BIT_HS25: - bus_width = SDMMC_BUS_WIDTH_1; - type = SDHCI_TIMING_SD_HS25; - break; - case SD_4BIT_HS25: - type = SDHCI_TIMING_SD_HS25; - break; - case SD_UHS_SDR82: - type = SDHCI_TIMING_UHS_SDR82; - break; - default: - sd_mode = SD_UHS_SDR82; - } - - return sdmmc_storage_init_sd(&sd_storage, &sd_sdmmc, bus_width, type); -} - -bool sd_initialize(bool power_cycle) -{ - if (power_cycle) - sdmmc_storage_end(&sd_storage); - - int res = !sd_init_retry(false); - - while (true) - { - if (!res) - return true; - else if (!sdmmc_get_sd_inserted()) // SD Card is not inserted. - { - sd_mode = SD_UHS_SDR82; - break; - } - else - { - sd_errors[SD_ERROR_INIT_FAIL]++; - - if (sd_mode == SD_INIT_FAIL) - break; - else - res = !sd_init_retry(true); - } - } - - sdmmc_storage_end(&sd_storage); - - return false; -} - -bool sd_mount() -{ - if (sd_mounted) - return true; - - int res = !sd_initialize(false); - - if (res) - { - gfx_con.mute = false; - EPRINTF("Failed to init SD card."); - if (!sdmmc_get_sd_inserted()) - EPRINTF("Make sure that it is inserted."); - else - EPRINTF("SD Card Reader is not properly seated!"); - } - else - { - res = f_mount(&sd_fs, "", 1); - if (res == FR_OK) - { - sd_mounted = true; - return true; - } - else - { - gfx_con.mute = false; - EPRINTFARGS("Failed to mount SD card (FatFS Error %d).\nMake sure that a FAT partition exists..", res); - } - } - - return false; -} - -static void _sd_deinit() -{ - if (sd_mode == SD_INIT_FAIL) - sd_mode = SD_UHS_SDR82; - - if (sd_mounted) - { - f_mount(NULL, "", 1); - sdmmc_storage_end(&sd_storage); - sd_mounted = false; - } -} - -void sd_unmount() { _sd_deinit(); } -void sd_end() { _sd_deinit(); } - -bool sd_is_gpt() -{ - return sd_fs.part_type; -} - -void *sd_file_read(const char *path, u32 *fsize) -{ - FIL fp; - if (f_open(&fp, path, FA_READ) != FR_OK) - return NULL; - - u32 size = f_size(&fp); - if (fsize) - *fsize = size; - - void *buf = malloc(size); - - if (f_read(&fp, buf, size, NULL) != FR_OK) - { - free(buf); - f_close(&fp); - - return NULL; - } - - f_close(&fp); - - return buf; -} - -int sd_save_to_file(void *buf, u32 size, const char *filename) -{ - FIL fp; - u32 res = 0; - res = f_open(&fp, filename, FA_CREATE_ALWAYS | FA_WRITE); - if (res) - { - EPRINTFARGS("Error (%d) creating file\n%s.\n", res, filename); - return res; - } - - f_write(&fp, buf, size, NULL); - f_close(&fp); - - return 0; -} diff --git a/loader/Makefile b/loader/Makefile index d59ed08..c2a12c0 100644 --- a/loader/Makefile +++ b/loader/Makefile @@ -27,10 +27,10 @@ OBJS = $(addprefix $(BUILDDIR)/$(TARGET)/, \ ################################################################################ CUSTOMDEFINES := -DBL_MAGIC=$(IPL_MAGIC) -CUSTOMDEFINES += -DBL_VER_MJ=$(BLVERSION_MAJOR) -DBL_VER_MN=$(BLVERSION_MINOR) -DBL_VER_HF=$(BLVERSION_HOTFX) -DBL_RESERVED=$(BLVERSION_RSVD) +CUSTOMDEFINES += -DBL_VER_MJ=$(BLVERSION_MAJOR) -DBL_VER_MN=$(BLVERSION_MINOR) -DBL_VER_HF=$(BLVERSION_HOTFX) -DBL_VER_RL=$(BLVERSION_REL) #TODO: Considering reinstating some of these when pointer warnings have been fixed. -WARNINGS := -Wall -Wno-array-bounds -Wno-stringop-overflow +WARNINGS := -Wall -Wsign-compare -Wno-array-bounds -Wno-stringop-overflow ARCH := -march=armv4t -mtune=arm7tdmi -mthumb-interwork CFLAGS = $(ARCH) -O2 -g -nostdlib -ffunction-sections -fdata-sections -fomit-frame-pointer -std=gnu11 $(WARNINGS) $(CUSTOMDEFINES) @@ -46,7 +46,7 @@ clean: @rm -rf $(OBJS) $(TARGET).bin: $(BUILDDIR)/$(TARGET)/$(TARGET).elf - $(OBJCOPY) -S -O binary $< $(OUTPUTDIR)/$(PAYLOAD_NAME).bin + @$(OBJCOPY) -S -O binary $< $(OUTPUTDIR)/$(PAYLOAD_NAME).bin $(BUILDDIR)/$(TARGET)/$(TARGET).elf: $(OBJS) @$(CC) $(LDFLAGS) -T link.ld $^ -o $@ diff --git a/loader/link.ld b/loader/link.ld index b217fd3..81e1085 100644 --- a/loader/link.ld +++ b/loader/link.ld @@ -15,6 +15,14 @@ SECTIONS { *(.rodata*); *(._payload_00); *(._payload_01); + + /* + * To mitigate bad injectors/chainloaders, + * miss-align binary size to account for version info. + * !If version text is not appended, then use ". = ALIGN(4)"! + */ + data_end_ua = .; + . = ((data_end_ua + 0x6 + 4 - 1) & ~(4 - 1)) - 6; } __ldr_end = .; . = ALIGN(0x10); diff --git a/loader/loader.c b/loader/loader.c index fc1a1f7..03bc63e 100644 --- a/loader/loader.c +++ b/loader/loader.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 CTCaer + * Copyright (c) 2019-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -32,12 +32,12 @@ boot_cfg_t __attribute__((section ("._boot_cfg"))) b_cfg; const volatile ipl_ver_meta_t __attribute__((section ("._ipl_version"))) ipl_ver = { .magic = BL_MAGIC, - .version = (BL_VER_MJ + '0') | ((BL_VER_MN + '0') << 8) | ((BL_VER_HF + '0') << 16), + .version = (BL_VER_MJ + '0') | ((BL_VER_MN + '0') << 8) | ((BL_VER_HF + '0') << 16) | ((BL_VER_RL) << 24), .rsvd0 = 0, .rsvd1 = 0 }; -const volatile char __attribute__((section ("._octopus"))) octopus[] = +const char __attribute__((section ("._octopus"))) octopus[] = "\n" " ___\n" " .-' `'.\n" @@ -60,39 +60,46 @@ const volatile char __attribute__((section ("._octopus"))) octopus[] = void loader_main() { // Preliminary BPMP clocks init. - CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x10; // Set HCLK div to 2 and PCLK div to 1. - CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0; // Set SCLK div to 1. - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; // Set clk source to Run and PLLP_OUT2 (204MHz). + CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 0x10; // Set HCLK div to 2 and PCLK div to 1. + CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_SYS) = 0; // Set SCLK div to 1. + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20004444; // Set clk source to Run and PLLP_OUT2 (204MHz). CLOCK(CLK_RST_CONTROLLER_SUPER_SCLK_DIVIDER) = 0x80000000; // Enable SUPER_SDIV to 1. - CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3. - CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // Set SCLK to PLLP_OUT (408MHz). + CLOCK(CLK_RST_CONTROLLER_CLK_SYSTEM_RATE) = 2; // Set HCLK div to 1 and PCLK div to 3. + CLOCK(CLK_RST_CONTROLLER_SCLK_BURST_POLICY) = 0x20003333; // Set SCLK to PLLP_OUT (408MHz). - // Get Loader and Payload size. - u32 payload_size = sizeof(payload_00) + sizeof(payload_01); // Actual payload size. - payload_size += (u32)payload_01 - (u32)payload_00 - sizeof(payload_00); // Add array alignment. + // Set arbiter. + ARB_PRI(ARB_PRIO_CPU_PRIORITY) = 0x12412D1; + ARB_PRI(ARB_PRIO_COP_PRIORITY) = 0x0000000; + ARB_PRI(ARB_PRIO_VCP_PRIORITY) = 0x220244A; + ARB_PRI(ARB_PRIO_DMA_PRIORITY) = 0x320369B; + + // Get Payload size. + u32 payload_size = sizeof(payload_00) + sizeof(payload_01); // Actual payload size. + payload_size += (u32)payload_01 - (u32)payload_00 - sizeof(payload_00); // Add compiler alignment. + payload_size = ALIGN(payload_size, 4); // Align size to 4 bytes. u32 *payload_addr = (u32 *)payload_00; // Relocate payload to a safer place. - u32 bytes = ALIGN(payload_size, 4) >> 2; - u32 *addr = payload_addr + bytes - 1; - u32 *dst = (u32 *)(IPL_RELOC_TOP - 4); - while (bytes) + u32 words = payload_size >> 2; + u32 *src = payload_addr + words - 1; + u32 *dst = (u32 *)(IPL_RELOC_TOP - 4); + while (words) { - *dst = *addr; + *dst = *src; + src--; dst--; - addr--; - bytes--; + words--; } // Set source address of the first part. - u8 *src_addr = (void *)(IPL_RELOC_TOP - ALIGN(payload_size, 4)); + u8 *src_addr = (void *)(IPL_RELOC_TOP - payload_size); // Uncompress first part. - u32 dst_pos = LZ_Uncompress((const u8 *)src_addr, (u8*)IPL_LOAD_ADDR, sizeof(payload_00)); + u32 dst_pos = LZ_Uncompress((const u8 *)src_addr, (u8 *)IPL_LOAD_ADDR, sizeof(payload_00)); - // Set source address of the second part. Includes array alignment. + // Set source address of the second part. Includes compiler alignment. src_addr += (u32)payload_01 - (u32)payload_00; // Uncompress second part. - LZ_Uncompress((const u8 *)src_addr, (u8*)IPL_LOAD_ADDR + dst_pos, sizeof(payload_01)); + LZ_Uncompress((const u8 *)src_addr, (u8 *)IPL_LOAD_ADDR + dst_pos, sizeof(payload_01)); // Copy over boot configuration storage. memcpy((u8 *)(IPL_LOAD_ADDR + IPL_PATCHED_RELOC_SZ), &b_cfg, sizeof(boot_cfg_t)); diff --git a/modules/hekate_libsys_lp0/Makefile b/modules/hekate_libsys_lp0/Makefile index 8013839..90efa07 100644 --- a/modules/hekate_libsys_lp0/Makefile +++ b/modules/hekate_libsys_lp0/Makefile @@ -15,7 +15,7 @@ OBJS = $(addprefix $(BUILD)/,\ ) ARCH := -march=armv4t -mtune=arm7tdmi -mthumb-interwork -CFLAGS = $(ARCH) -O2 -nostdlib -fpie -ffunction-sections -fdata-sections -fomit-frame-pointer -std=gnu11 -Wall $(CUSTOMDEFINES) +CFLAGS = $(ARCH) -O2 -nostdlib -fpie -ffunction-sections -fdata-sections -fomit-frame-pointer -std=gnu11 -Wall -Wsign-compare $(CUSTOMDEFINES) LDFLAGS = $(ARCH) -fpie -pie -nostartfiles -lgcc .PHONY: clean all @@ -28,7 +28,7 @@ $(BUILD)/%.o: ./%.c $(TARGET).bso: $(OBJS) @$(CC) $(LDFLAGS) -e _modInit $^ -o $(OUTPUT)/$(TARGET).bso @$(STRIP) -g $(OUTPUT)/$(TARGET).bso - @echo "-------------\nBuilt module: "$(TARGET)".bso\n-------------" + @echo -e "-------------\nBuilt module: "$(TARGET)".bso\n-------------" clean: @rm -rf $(OUTPUT)/$(TARGET).bso diff --git a/modules/hekate_libsys_lp0/sdram_lp0_param_t210b01.h b/modules/hekate_libsys_lp0/sdram_lp0_param_t210b01.h index 8510688..924c766 100644 --- a/modules/hekate_libsys_lp0/sdram_lp0_param_t210b01.h +++ b/modules/hekate_libsys_lp0/sdram_lp0_param_t210b01.h @@ -981,6 +981,7 @@ struct sdram_params_t210b01 /* Specifies the value for MC_MTS_CARVEOUT_REG_CTRL */ u32 mc_mts_carveout_reg_ctrl; + /* Specifies the clients that are allowed to access untranslated memory */ u32 mc_untranslated_region_check; /* Just a place holder for special usage when there is no BCT for certain registers */ diff --git a/modules/hekate_libsys_lp0/sys_sdramlp0.c b/modules/hekate_libsys_lp0/sys_sdramlp0.c index e806fcb..c55819a 100644 --- a/modules/hekate_libsys_lp0/sys_sdramlp0.c +++ b/modules/hekate_libsys_lp0/sys_sdramlp0.c @@ -1115,7 +1115,7 @@ static void _sdram_lp0_save_params_t210(const void *params) c32(0, scratch3); s(PllMInputDivider, 7:0, scratch3, 7:0); - c(0x3e, scratch3, 15:8); + c(0x3E, scratch3, 15:8); c(0, scratch3, 20:16); s(PllMKVCO, 0:0, scratch3, 21:21); s(PllMKCP, 1:0, scratch3, 23:22); @@ -1125,6 +1125,7 @@ static void _sdram_lp0_save_params_t210(const void *params) c32(0, scratch4); s(PllMStableTime, 9:0, scratch4, 9:0); + s(PllMStableTime, 9:0, scratch4, 19:10); } #pragma GCC diagnostic ignored "-Wparentheses" diff --git a/modules/hekate_libsys_minerva/Makefile b/modules/hekate_libsys_minerva/Makefile index ba7238f..5e3f086 100644 --- a/modules/hekate_libsys_minerva/Makefile +++ b/modules/hekate_libsys_minerva/Makefile @@ -15,7 +15,7 @@ OBJS = $(addprefix $(BUILD)/,\ ) ARCH := -march=armv4t -mtune=arm7tdmi -mthumb-interwork -CFLAGS = $(ARCH) -O2 -nostdlib -fpie -ffunction-sections -fdata-sections -fomit-frame-pointer -std=gnu11 -Wall $(CUSTOMDEFINES) +CFLAGS = $(ARCH) -O2 -nostdlib -fpie -ffunction-sections -fdata-sections -fomit-frame-pointer -std=gnu11 -Wall -Wsign-compare $(CUSTOMDEFINES) LDFLAGS = $(ARCH) -fpie -pie -nostartfiles -lgcc .PHONY: clean all @@ -28,7 +28,7 @@ $(BUILD)/%.o: ./%.c $(TARGET).bso: $(OBJS) @$(CC) $(LDFLAGS) -e _minerva_init $^ -o $(OUTPUT)/$(TARGET).bso @$(STRIP) -g $(OUTPUT)/$(TARGET).bso - @echo "-------------\nBuilt module: "$(TARGET)".bso\n-------------" + @echo -e "-------------\nBuilt module: "$(TARGET)".bso\n-------------" clean: @rm -rf $(OUTPUT)/$(TARGET).bso diff --git a/modules/hekate_libsys_minerva/mtc.h b/modules/hekate_libsys_minerva/mtc.h index 07a9dc1..860c7d7 100644 --- a/modules/hekate_libsys_minerva/mtc.h +++ b/modules/hekate_libsys_minerva/mtc.h @@ -2,7 +2,7 @@ * Minerva Training Cell * DRAM Training for Tegra X1 SoC. Supports DDR2/3 and LPDDR3/4. * - * Copyright (c) 2018 CTCaer + * Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -44,17 +44,38 @@ #define EMC_CH1(off) _REG(EMC1_BASE, off) /* End of addresses and access macros */ -#define EMC_TABLE_SIZE_R7 49280 #define EMC_TABLE_ENTRY_SIZE_R7 4928 #define EMC_TABLE_ENTRY_SIZE_R3 4300 +#define EMC_TABLE_SIZE_R7 (EMC_TABLE_ENTRY_SIZE_R7 * 7) #define EMC_STATUS_UPDATE_TIMEOUT 1000 #define EMC_PERIODIC_TRAIN_MS 100 #define EMC_TEMP_COMP_MS 1000 +/* Training types */ +#define NEEDS_TRAINING_CA BIT(0) +#define NEEDS_TRAINING_CA_VREF BIT(1) +#define NEEDS_TRAINING_QUSE BIT(2) +#define NEEDS_TRAINING_QUSE_VREF BIT(3) +#define NEEDS_TRAINING_WR BIT(4) +#define NEEDS_TRAINING_WR_VREF BIT(5) +#define NEEDS_TRAINING_RD BIT(6) +#define NEEDS_TRAINING_RD_VREF BIT(7) +#define NEEDS_TRAINING_SWAP_RANK BIT(8) +#define NEEDS_TRAINING_IN_SELF_REFRESH BIT(9) + +#define NEEDS_TRISTATE_TRAINING (NEEDS_TRAINING_CA | NEEDS_TRAINING_CA_VREF | \ + NEEDS_TRAINING_QUSE | NEEDS_TRAINING_WR | \ + NEEDS_TRAINING_WR_VREF | NEEDS_TRAINING_RD | \ + NEEDS_TRAINING_RD_VREF) +#define NEEDS_TRAINING_CA_COMBO (NEEDS_TRAINING_CA | NEEDS_TRAINING_CA_VREF) +#define NEEDS_TRAINING_QUSE_COMBO (NEEDS_TRAINING_QUSE | NEEDS_TRAINING_QUSE_VREF) +#define NEEDS_TRAINING_WR_COMBO (NEEDS_TRAINING_WR | NEEDS_TRAINING_WR_VREF) +#define NEEDS_TRAINING_RD_COMBO (NEEDS_TRAINING_RD | NEEDS_TRAINING_RD_VREF) + typedef struct { - s32 rate_to; - s32 rate_from; + u32 rate_to; + u32 rate_from; emc_table_t *mtc_table; u32 table_entries; emc_table_t *current_emc_table; @@ -64,7 +85,7 @@ typedef struct bool emc_2X_clk_src_is_pllmb; bool fsp_for_src_freq; bool train_ram_patterns; - bool init_done; + u32 init_done; } mtc_config_t; enum train_mode_t diff --git a/modules/hekate_libsys_minerva/mtc_switch_tables.h b/modules/hekate_libsys_minerva/mtc_switch_tables.h index 13d9e71..3b9548f 100644 --- a/modules/hekate_libsys_minerva/mtc_switch_tables.h +++ b/modules/hekate_libsys_minerva/mtc_switch_tables.h @@ -27,934 +27,11 @@ #define DRAM_6GB_SAMSUNG_K4FHE3D4HM_MFCH 4 #define DRAM_4GB_COPPER_HYNIX 5 #define DRAM_4GB_COPPER_MICRON 6 +#define DRAM_8GB_SAMSUNG_K4FBE3D4HM_MGXX 7 // nx_abca2_0_3 and nx_abca2_1. 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0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x77, 0x00, 0x05, 0x08, 0x11, 0x00, 0x08, 0x00, 0x04, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x06, 0x80, 0x18, 0x40, 0x01, 0x00, 0x00, 0x00, 0xEA, 0x1A, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x31, 0x30, 0x5F, 0x32, 0x30, 0x34, 0x30, 0x30, 0x30, 0x5F, 0x4E, 0x6F, 0x43, 0x66, 0x67, 0x56, 0x65, 0x72, 0x73, 0x69, 0x6F, 0x6E, 0x5F, 0x56, 0x39, 0x2E, 0x38, 0x2E, 0x37, 0x5F, 0x56, 0x31, 0x2E, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -3114,932 +2191,8 @@ static const unsigned char nx_abca2_0_3_10NoCfgVersion_V9_8_7_V1_6[49280] = }; // nx_abca2_2. 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0x73, 0x69, 0x6F, 0x6E, 0x5F, 0x56, 0x39, 0x2E, 0x38, 0x2E, 0x37, 0x5F, 0x56, 0x31, 0x2E, 0x36, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, diff --git a/modules/hekate_libsys_minerva/mtc_table.h b/modules/hekate_libsys_minerva/mtc_table.h index 9bf8164..f6aa716 100644 --- a/modules/hekate_libsys_minerva/mtc_table.h +++ b/modules/hekate_libsys_minerva/mtc_table.h @@ -33,227 +33,227 @@ typedef struct typedef struct { - u32 emc_rc_idx; - u32 emc_rfc_idx; - u32 emc_rfcpb_idx; - u32 emc_refctrl2_idx; - u32 emc_rfc_slr_idx; - u32 emc_ras_idx; - u32 emc_rp_idx; - u32 emc_r2w_idx; - u32 emc_w2r_idx; - u32 emc_r2p_idx; - u32 emc_w2p_idx; - u32 emc_r2r_idx; - u32 emc_tppd_idx; - u32 emc_ccdmw_idx; - u32 emc_rd_rcd_idx; - u32 emc_wr_rcd_idx; - u32 emc_rrd_idx; - u32 emc_rext_idx; - u32 emc_wext_idx; - u32 emc_wdv_chk_idx; - u32 emc_wdv_idx; - u32 emc_wsv_idx; - u32 emc_wev_idx; - u32 emc_wdv_mask_idx; - u32 emc_ws_duration_idx; - u32 emc_we_duration_idx; - u32 emc_quse_idx; - u32 emc_quse_width_idx; - u32 emc_ibdly_idx; - u32 emc_obdly_idx; - u32 emc_einput_idx; - u32 emc_mrw6_idx; - u32 emc_einput_duration_idx; - u32 emc_puterm_extra_idx; - u32 emc_puterm_width_idx; - u32 emc_qrst_idx; - u32 emc_qsafe_idx; - u32 emc_rdv_idx; - u32 emc_rdv_mask_idx; - u32 emc_rdv_early_idx; - u32 emc_rdv_early_mask_idx; - u32 emc_refresh_idx; - u32 emc_burst_refresh_num_idx; - u32 emc_pre_refresh_req_cnt_idx; - u32 emc_pdex2wr_idx; - u32 emc_pdex2rd_idx; - u32 emc_pchg2pden_idx; - u32 emc_act2pden_idx; - u32 emc_ar2pden_idx; - u32 emc_rw2pden_idx; - u32 emc_cke2pden_idx; - u32 emc_pdex2cke_idx; - u32 emc_pdex2mrr_idx; - u32 emc_txsr_idx; - u32 emc_txsrdll_idx; - u32 emc_tcke_idx; - u32 emc_tckesr_idx; - u32 emc_tpd_idx; - u32 emc_tfaw_idx; - u32 emc_trpab_idx; - u32 emc_tclkstable_idx; - u32 emc_tclkstop_idx; - u32 emc_mrw7_idx; - u32 emc_trefbw_idx; - u32 emc_odt_write_idx; - u32 emc_fbio_cfg5_idx; - u32 emc_fbio_cfg7_idx; - u32 emc_cfg_dig_dll_idx; - u32 emc_cfg_dig_dll_period_idx; - u32 emc_pmacro_ib_rxrt_idx; - u32 emc_cfg_pipe_1_idx; - u32 emc_cfg_pipe_2_idx; - u32 emc_pmacro_quse_ddll_rank0_4_idx; - u32 emc_pmacro_quse_ddll_rank0_5_idx; - u32 emc_pmacro_quse_ddll_rank1_4_idx; - u32 emc_pmacro_quse_ddll_rank1_5_idx; - u32 emc_mrw8_idx; - u32 emc_pmacro_ob_ddll_long_dq_rank1_4_idx; - u32 emc_pmacro_ob_ddll_long_dq_rank1_5_idx; - u32 emc_pmacro_ob_ddll_long_dqs_rank0_0_idx; - u32 emc_pmacro_ob_ddll_long_dqs_rank0_1_idx; - u32 emc_pmacro_ob_ddll_long_dqs_rank0_2_idx; - u32 emc_pmacro_ob_ddll_long_dqs_rank0_3_idx; - u32 emc_pmacro_ob_ddll_long_dqs_rank0_4_idx; - u32 emc_pmacro_ob_ddll_long_dqs_rank0_5_idx; - u32 emc_pmacro_ob_ddll_long_dqs_rank1_0_idx; - u32 emc_pmacro_ob_ddll_long_dqs_rank1_1_idx; - u32 emc_pmacro_ob_ddll_long_dqs_rank1_2_idx; - u32 emc_pmacro_ob_ddll_long_dqs_rank1_3_idx; - u32 emc_pmacro_ob_ddll_long_dqs_rank1_4_idx; - u32 emc_pmacro_ob_ddll_long_dqs_rank1_5_idx; - u32 emc_pmacro_ddll_long_cmd_0_idx; - u32 emc_pmacro_ddll_long_cmd_1_idx; - u32 emc_pmacro_ddll_long_cmd_2_idx; - u32 emc_pmacro_ddll_long_cmd_3_idx; - u32 emc_pmacro_ddll_long_cmd_4_idx; - u32 emc_pmacro_ddll_short_cmd_0_idx; - u32 emc_pmacro_ddll_short_cmd_1_idx; - u32 emc_pmacro_ddll_short_cmd_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte1_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte2_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte3_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte4_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte5_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte6_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte7_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte1_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte2_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte3_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte4_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte5_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte6_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte7_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3_idx; - u32 emc_txdsrvttgen_idx; - u32 emc_fdpd_ctrl_dq_idx; - u32 emc_fdpd_ctrl_cmd_idx; - u32 emc_fbio_spare_idx; - u32 emc_zcal_interval_idx; - u32 emc_zcal_wait_cnt_idx; - u32 emc_mrs_wait_cnt_idx; - u32 emc_mrs_wait_cnt2_idx; - u32 emc_auto_cal_channel_idx; - u32 emc_dll_cfg_0_idx; - u32 emc_dll_cfg_1_idx; - u32 emc_pmacro_autocal_cfg_common_idx; - u32 emc_pmacro_zctrl_idx; - u32 emc_cfg_idx; - u32 emc_cfg_pipe_idx; - u32 emc_dyn_self_ref_control_idx; - u32 emc_qpop_idx; - u32 emc_dqs_brlshft_0_idx; - u32 emc_dqs_brlshft_1_idx; - u32 emc_cmd_brlshft_2_idx; - u32 emc_cmd_brlshft_3_idx; - u32 emc_pmacro_pad_cfg_ctrl_idx; - u32 emc_pmacro_data_pad_rx_ctrl_idx; - u32 emc_pmacro_cmd_pad_rx_ctrl_idx; - u32 emc_pmacro_data_rx_term_mode_idx; - u32 emc_pmacro_cmd_rx_term_mode_idx; - u32 emc_pmacro_cmd_pad_tx_ctrl_idx; - u32 emc_pmacro_data_pad_tx_ctrl_idx; - u32 emc_pmacro_common_pad_tx_ctrl_idx; - u32 emc_pmacro_vttgen_ctrl_0_idx; - u32 emc_pmacro_vttgen_ctrl_1_idx; - u32 emc_pmacro_vttgen_ctrl_2_idx; - u32 emc_pmacro_brick_ctrl_rfu1_idx; - u32 emc_pmacro_cmd_brick_ctrl_fdpd_idx; - u32 emc_pmacro_brick_ctrl_rfu2_idx; - u32 emc_pmacro_data_brick_ctrl_fdpd_idx; - u32 emc_pmacro_bg_bias_ctrl_0_idx; - u32 emc_cfg_3_idx; - u32 emc_pmacro_tx_pwrd_0_idx; - u32 emc_pmacro_tx_pwrd_1_idx; - u32 emc_pmacro_tx_pwrd_2_idx; - u32 emc_pmacro_tx_pwrd_3_idx; - u32 emc_pmacro_tx_pwrd_4_idx; - u32 emc_pmacro_tx_pwrd_5_idx; - u32 emc_config_sample_delay_idx; - u32 emc_pmacro_tx_sel_clk_src_0_idx; - u32 emc_pmacro_tx_sel_clk_src_1_idx; - u32 emc_pmacro_tx_sel_clk_src_2_idx; - u32 emc_pmacro_tx_sel_clk_src_3_idx; - u32 emc_pmacro_tx_sel_clk_src_4_idx; - u32 emc_pmacro_tx_sel_clk_src_5_idx; - u32 emc_pmacro_ddll_bypass_idx; - u32 emc_pmacro_ddll_pwrd_0_idx; - u32 emc_pmacro_ddll_pwrd_1_idx; - u32 emc_pmacro_ddll_pwrd_2_idx; - u32 emc_pmacro_cmd_ctrl_0_idx; - u32 emc_pmacro_cmd_ctrl_1_idx; - u32 emc_pmacro_cmd_ctrl_2_idx; - u32 emc_tr_timing_0_idx; - u32 emc_tr_dvfs_idx; - u32 emc_tr_ctrl_1_idx; - u32 emc_tr_rdv_idx; - u32 emc_tr_qpop_idx; - u32 emc_tr_rdv_mask_idx; - u32 emc_mrw14_idx; - u32 emc_tr_qsafe_idx; - u32 emc_tr_qrst_idx; - u32 emc_training_ctrl_idx; - u32 emc_training_settle_idx; - u32 emc_training_vref_settle_idx; - u32 emc_training_ca_fine_ctrl_idx; - u32 emc_training_ca_ctrl_misc_idx; - u32 emc_training_ca_ctrl_misc1_idx; - u32 emc_training_ca_vref_ctrl_idx; - u32 emc_training_quse_cors_ctrl_idx; - u32 emc_training_quse_fine_ctrl_idx; - u32 emc_training_quse_ctrl_misc_idx; - u32 emc_training_quse_vref_ctrl_idx; - u32 emc_training_read_fine_ctrl_idx; - u32 emc_training_read_ctrl_misc_idx; - u32 emc_training_read_vref_ctrl_idx; - u32 emc_training_write_fine_ctrl_idx; - u32 emc_training_write_ctrl_misc_idx; - u32 emc_training_write_vref_ctrl_idx; - u32 emc_training_mpc_idx; - u32 emc_mrw15_idx; + u32 emc_rc; + u32 emc_rfc; + u32 emc_rfcpb; + u32 emc_refctrl2; + u32 emc_rfc_slr; + u32 emc_ras; + u32 emc_rp; + u32 emc_r2w; + u32 emc_w2r; + u32 emc_r2p; + u32 emc_w2p; + u32 emc_r2r; + u32 emc_tppd; + u32 emc_ccdmw; + u32 emc_rd_rcd; + u32 emc_wr_rcd; + u32 emc_rrd; + u32 emc_rext; + u32 emc_wext; + u32 emc_wdv_chk; + u32 emc_wdv; + u32 emc_wsv; + u32 emc_wev; + u32 emc_wdv_mask; + u32 emc_ws_duration; + u32 emc_we_duration; + u32 emc_quse; + u32 emc_quse_width; + u32 emc_ibdly; + u32 emc_obdly; + u32 emc_einput; + u32 emc_mrw6; + u32 emc_einput_duration; + u32 emc_puterm_extra; + u32 emc_puterm_width; + u32 emc_qrst; + u32 emc_qsafe; + u32 emc_rdv; + u32 emc_rdv_mask; + u32 emc_rdv_early; + u32 emc_rdv_early_mask; + u32 emc_refresh; + u32 emc_burst_refresh_num; + u32 emc_pre_refresh_req_cnt; + u32 emc_pdex2wr; + u32 emc_pdex2rd; + u32 emc_pchg2pden; + u32 emc_act2pden; + u32 emc_ar2pden; + u32 emc_rw2pden; + u32 emc_cke2pden; + u32 emc_pdex2cke; + u32 emc_pdex2mrr; + u32 emc_txsr; + u32 emc_txsrdll; + u32 emc_tcke; + u32 emc_tckesr; + u32 emc_tpd; + u32 emc_tfaw; + u32 emc_trpab; + u32 emc_tclkstable; + u32 emc_tclkstop; + u32 emc_mrw7; + u32 emc_trefbw; + u32 emc_odt_write; + u32 emc_fbio_cfg5; + u32 emc_fbio_cfg7; + u32 emc_cfg_dig_dll; + u32 emc_cfg_dig_dll_period; + u32 emc_pmacro_ib_rxrt; + u32 emc_cfg_pipe_1; + u32 emc_cfg_pipe_2; + u32 emc_pmacro_quse_ddll_rank0_4; + u32 emc_pmacro_quse_ddll_rank0_5; + u32 emc_pmacro_quse_ddll_rank1_4; + u32 emc_pmacro_quse_ddll_rank1_5; + u32 emc_mrw8; + u32 emc_pmacro_ob_ddll_long_dq_rank1_4; + u32 emc_pmacro_ob_ddll_long_dq_rank1_5; + u32 emc_pmacro_ob_ddll_long_dqs_rank0_0; + u32 emc_pmacro_ob_ddll_long_dqs_rank0_1; + u32 emc_pmacro_ob_ddll_long_dqs_rank0_2; + u32 emc_pmacro_ob_ddll_long_dqs_rank0_3; + u32 emc_pmacro_ob_ddll_long_dqs_rank0_4; + u32 emc_pmacro_ob_ddll_long_dqs_rank0_5; + u32 emc_pmacro_ob_ddll_long_dqs_rank1_0; + u32 emc_pmacro_ob_ddll_long_dqs_rank1_1; + u32 emc_pmacro_ob_ddll_long_dqs_rank1_2; + u32 emc_pmacro_ob_ddll_long_dqs_rank1_3; + u32 emc_pmacro_ob_ddll_long_dqs_rank1_4; + u32 emc_pmacro_ob_ddll_long_dqs_rank1_5; + u32 emc_pmacro_ddll_long_cmd_0; + u32 emc_pmacro_ddll_long_cmd_1; + u32 emc_pmacro_ddll_long_cmd_2; + u32 emc_pmacro_ddll_long_cmd_3; + u32 emc_pmacro_ddll_long_cmd_4; + u32 emc_pmacro_ddll_short_cmd_0; + u32 emc_pmacro_ddll_short_cmd_1; + u32 emc_pmacro_ddll_short_cmd_2; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_3; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte1_3; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte2_3; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte3_3; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte4_3; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte5_3; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte6_3; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte7_3; + u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd0_3; + u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd1_3; + u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd2_3; + u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_3; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_3; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte1_3; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte2_3; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte3_3; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte4_3; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte5_3; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte6_3; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte7_3; + u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd0_0; + u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd0_1; + u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd0_2; + u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd0_3; + u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd1_0; + u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd1_1; + u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd1_2; + u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd1_3; + u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd2_0; + u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd2_1; + u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd2_2; + u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd2_3; + u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_0; + u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_1; + u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_2; + u32 emc_pmacro_ob_ddll_short_dq_rank1_cmd3_3; + u32 emc_txdsrvttgen; + u32 emc_fdpd_ctrl_dq; + u32 emc_fdpd_ctrl_cmd; + u32 emc_fbio_spare; + u32 emc_zcal_interval; + u32 emc_zcal_wait_cnt; + u32 emc_mrs_wait_cnt; + u32 emc_mrs_wait_cnt2; + u32 emc_auto_cal_channel; + u32 emc_dll_cfg_0; + u32 emc_dll_cfg_1; + u32 emc_pmacro_autocal_cfg_common; + u32 emc_pmacro_zctrl; + u32 emc_cfg; + u32 emc_cfg_pipe; + u32 emc_dyn_self_ref_control; + u32 emc_qpop; + u32 emc_dqs_brlshft_0; + u32 emc_dqs_brlshft_1; + u32 emc_cmd_brlshft_2; + u32 emc_cmd_brlshft_3; + u32 emc_pmacro_pad_cfg_ctrl; + u32 emc_pmacro_data_pad_rx_ctrl; + u32 emc_pmacro_cmd_pad_rx_ctrl; + u32 emc_pmacro_data_rx_term_mode; + u32 emc_pmacro_cmd_rx_term_mode; + u32 emc_pmacro_cmd_pad_tx_ctrl; + u32 emc_pmacro_data_pad_tx_ctrl; + u32 emc_pmacro_common_pad_tx_ctrl; + u32 emc_pmacro_vttgen_ctrl_0; + u32 emc_pmacro_vttgen_ctrl_1; + u32 emc_pmacro_vttgen_ctrl_2; + u32 emc_pmacro_brick_ctrl_rfu1; + u32 emc_pmacro_cmd_brick_ctrl_fdpd; + u32 emc_pmacro_brick_ctrl_rfu2; + u32 emc_pmacro_data_brick_ctrl_fdpd; + u32 emc_pmacro_bg_bias_ctrl_0; + u32 emc_cfg_3; + u32 emc_pmacro_tx_pwrd_0; + u32 emc_pmacro_tx_pwrd_1; + u32 emc_pmacro_tx_pwrd_2; + u32 emc_pmacro_tx_pwrd_3; + u32 emc_pmacro_tx_pwrd_4; + u32 emc_pmacro_tx_pwrd_5; + u32 emc_config_sample_delay; + u32 emc_pmacro_tx_sel_clk_src_0; + u32 emc_pmacro_tx_sel_clk_src_1; + u32 emc_pmacro_tx_sel_clk_src_2; + u32 emc_pmacro_tx_sel_clk_src_3; + u32 emc_pmacro_tx_sel_clk_src_4; + u32 emc_pmacro_tx_sel_clk_src_5; + u32 emc_pmacro_ddll_bypass; + u32 emc_pmacro_ddll_pwrd_0; + u32 emc_pmacro_ddll_pwrd_1; + u32 emc_pmacro_ddll_pwrd_2; + u32 emc_pmacro_cmd_ctrl_0; + u32 emc_pmacro_cmd_ctrl_1; + u32 emc_pmacro_cmd_ctrl_2; + u32 emc_tr_timing_0; + u32 emc_tr_dvfs; + u32 emc_tr_ctrl_1; + u32 emc_tr_rdv; + u32 emc_tr_qpop; + u32 emc_tr_rdv_mask; + u32 emc_mrw14; + u32 emc_tr_qsafe; + u32 emc_tr_qrst; + u32 emc_training_ctrl; + u32 emc_training_settle; + u32 emc_training_vref_settle; + u32 emc_training_ca_fine_ctrl; + u32 emc_training_ca_ctrl_misc; + u32 emc_training_ca_ctrl_misc1; + u32 emc_training_ca_vref_ctrl; + u32 emc_training_quse_cors_ctrl; + u32 emc_training_quse_fine_ctrl; + u32 emc_training_quse_ctrl_misc; + u32 emc_training_quse_vref_ctrl; + u32 emc_training_read_fine_ctrl; + u32 emc_training_read_ctrl_misc; + u32 emc_training_read_vref_ctrl; + u32 emc_training_write_fine_ctrl; + u32 emc_training_write_ctrl_misc; + u32 emc_training_write_vref_ctrl; + u32 emc_training_mpc; + u32 emc_mrw15; } burst_regs_t; typedef struct @@ -267,186 +267,186 @@ typedef struct typedef struct { - u32 ptfv_dqsosc_movavg_c0d0u0_idx; - u32 ptfv_dqsosc_movavg_c0d0u1_idx; - u32 ptfv_dqsosc_movavg_c0d1u0_idx; - u32 ptfv_dqsosc_movavg_c0d1u1_idx; - u32 ptfv_dqsosc_movavg_c1d0u0_idx; - u32 ptfv_dqsosc_movavg_c1d0u1_idx; - u32 ptfv_dqsosc_movavg_c1d1u0_idx; - u32 ptfv_dqsosc_movavg_c1d1u1_idx; - u32 ptfv_write_samples_idx; - u32 ptfv_dvfs_samples_idx; - u32 ptfv_movavg_weight_idx; - u32 ptfv_config_ctrl_idx; + u32 ptfv_dqsosc_movavg_c0d0u0; + u32 ptfv_dqsosc_movavg_c0d0u1; + u32 ptfv_dqsosc_movavg_c0d1u0; + u32 ptfv_dqsosc_movavg_c0d1u1; + u32 ptfv_dqsosc_movavg_c1d0u0; + u32 ptfv_dqsosc_movavg_c1d0u1; + u32 ptfv_dqsosc_movavg_c1d1u0; + u32 ptfv_dqsosc_movavg_c1d1u1; + u32 ptfv_write_samples; + u32 ptfv_dvfs_samples; + u32 ptfv_movavg_weight; + u32 ptfv_config_ctrl; } ptfv_list_table_t; typedef struct { - u32 emc0_mrw10_idx; - u32 emc1_mrw10_idx; - u32 emc0_mrw11_idx; - u32 emc1_mrw11_idx; - u32 emc0_mrw12_idx; - u32 emc1_mrw12_idx; - u32 emc0_mrw13_idx; - u32 emc1_mrw13_idx; + u32 emc0_mrw10; + u32 emc1_mrw10; + u32 emc0_mrw11; + u32 emc1_mrw11; + u32 emc0_mrw12; + u32 emc1_mrw12; + u32 emc0_mrw13; + u32 emc1_mrw13; } burst_reg_per_ch_t; typedef struct { - u32 emc_pmacro_ib_ddll_long_dqs_rank0_0_idx; - u32 emc_pmacro_ib_ddll_long_dqs_rank0_1_idx; - u32 emc_pmacro_ib_ddll_long_dqs_rank0_2_idx; - u32 emc_pmacro_ib_ddll_long_dqs_rank0_3_idx; - u32 emc_pmacro_ib_ddll_long_dqs_rank1_0_idx; - u32 emc_pmacro_ib_ddll_long_dqs_rank1_1_idx; - u32 emc_pmacro_ib_ddll_long_dqs_rank1_2_idx; - u32 emc_pmacro_ib_ddll_long_dqs_rank1_3_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte0_0_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte0_1_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte0_2_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte1_0_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte1_1_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte1_2_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte2_0_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte2_1_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte2_2_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte3_0_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte3_1_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte3_2_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte4_0_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte4_1_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte4_2_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte5_0_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte5_1_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte5_2_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte6_0_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte6_1_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte6_2_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte7_0_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte7_1_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank0_byte7_2_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte0_0_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte0_1_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte0_2_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte1_0_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte1_1_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte1_2_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte2_0_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte2_1_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte2_2_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte3_0_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte3_1_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte3_2_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte4_0_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte4_1_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte4_2_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte5_0_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte5_1_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte5_2_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte6_0_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte6_1_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte6_2_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte7_0_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte7_1_idx; - u32 emc_pmacro_ib_ddll_short_dq_rank1_byte7_2_idx; - u32 emc_pmacro_ib_vref_dqs_0_idx; - u32 emc_pmacro_ib_vref_dqs_1_idx; - u32 emc_pmacro_ib_vref_dq_0_idx; - u32 emc_pmacro_ib_vref_dq_1_idx; - u32 emc_pmacro_ob_ddll_long_dq_rank0_0_idx; - u32 emc_pmacro_ob_ddll_long_dq_rank0_1_idx; - u32 emc_pmacro_ob_ddll_long_dq_rank0_2_idx; - u32 emc_pmacro_ob_ddll_long_dq_rank0_3_idx; - u32 emc_pmacro_ob_ddll_long_dq_rank0_4_idx; - u32 emc_pmacro_ob_ddll_long_dq_rank0_5_idx; - u32 emc_pmacro_ob_ddll_long_dq_rank1_0_idx; - u32 emc_pmacro_ob_ddll_long_dq_rank1_1_idx; - u32 emc_pmacro_ob_ddll_long_dq_rank1_2_idx; - u32 emc_pmacro_ob_ddll_long_dq_rank1_3_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte1_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte1_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte1_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte2_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte2_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte2_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte3_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte3_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte3_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte4_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte4_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte4_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte5_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte5_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte5_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte6_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte6_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte6_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte7_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte7_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_byte7_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd0_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd0_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd0_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd1_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd1_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd1_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd2_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd2_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd2_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte1_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte1_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte1_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte2_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte2_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte2_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte3_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte3_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte3_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte4_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte4_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte4_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte5_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte5_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte5_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte6_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte6_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte6_2_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte7_0_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte7_1_idx; - u32 emc_pmacro_ob_ddll_short_dq_rank1_byte7_2_idx; - u32 emc_pmacro_quse_ddll_rank0_0_idx; - u32 emc_pmacro_quse_ddll_rank0_1_idx; - u32 emc_pmacro_quse_ddll_rank0_2_idx; - u32 emc_pmacro_quse_ddll_rank0_3_idx; - u32 emc_pmacro_quse_ddll_rank1_0_idx; - u32 emc_pmacro_quse_ddll_rank1_1_idx; - u32 emc_pmacro_quse_ddll_rank1_2_idx; - u32 emc_pmacro_quse_ddll_rank1_3_idx; + u32 emc_pmacro_ib_ddll_long_dqs_rank0_0; + u32 emc_pmacro_ib_ddll_long_dqs_rank0_1; + u32 emc_pmacro_ib_ddll_long_dqs_rank0_2; + u32 emc_pmacro_ib_ddll_long_dqs_rank0_3; + u32 emc_pmacro_ib_ddll_long_dqs_rank1_0; + u32 emc_pmacro_ib_ddll_long_dqs_rank1_1; + u32 emc_pmacro_ib_ddll_long_dqs_rank1_2; + u32 emc_pmacro_ib_ddll_long_dqs_rank1_3; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte0_0; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte0_1; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte0_2; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte1_0; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte1_1; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte1_2; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte2_0; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte2_1; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte2_2; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte3_0; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte3_1; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte3_2; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte4_0; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte4_1; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte4_2; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte5_0; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte5_1; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte5_2; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte6_0; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte6_1; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte6_2; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte7_0; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte7_1; + u32 emc_pmacro_ib_ddll_short_dq_rank0_byte7_2; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte0_0; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte0_1; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte0_2; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte1_0; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte1_1; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte1_2; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte2_0; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte2_1; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte2_2; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte3_0; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte3_1; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte3_2; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte4_0; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte4_1; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte4_2; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte5_0; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte5_1; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte5_2; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte6_0; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte6_1; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte6_2; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte7_0; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte7_1; + u32 emc_pmacro_ib_ddll_short_dq_rank1_byte7_2; + u32 emc_pmacro_ib_vref_dqs_0; + u32 emc_pmacro_ib_vref_dqs_1; + u32 emc_pmacro_ib_vref_dq_0; + u32 emc_pmacro_ib_vref_dq_1; + u32 emc_pmacro_ob_ddll_long_dq_rank0_0; + u32 emc_pmacro_ob_ddll_long_dq_rank0_1; + u32 emc_pmacro_ob_ddll_long_dq_rank0_2; + u32 emc_pmacro_ob_ddll_long_dq_rank0_3; + u32 emc_pmacro_ob_ddll_long_dq_rank0_4; + u32 emc_pmacro_ob_ddll_long_dq_rank0_5; + u32 emc_pmacro_ob_ddll_long_dq_rank1_0; + u32 emc_pmacro_ob_ddll_long_dq_rank1_1; + u32 emc_pmacro_ob_ddll_long_dq_rank1_2; + u32 emc_pmacro_ob_ddll_long_dq_rank1_3; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_0; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_1; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte0_2; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte1_0; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte1_1; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte1_2; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte2_0; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte2_1; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte2_2; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte3_0; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte3_1; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte3_2; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte4_0; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte4_1; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte4_2; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte5_0; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte5_1; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte5_2; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte6_0; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte6_1; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte6_2; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte7_0; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte7_1; + u32 emc_pmacro_ob_ddll_short_dq_rank0_byte7_2; + u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd0_0; + u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd0_1; + u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd0_2; + u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd1_0; + u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd1_1; + u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd1_2; + u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd2_0; + u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd2_1; + u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd2_2; + u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_0; + u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_1; + u32 emc_pmacro_ob_ddll_short_dq_rank0_cmd3_2; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_0; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_1; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte0_2; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte1_0; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte1_1; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte1_2; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte2_0; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte2_1; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte2_2; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte3_0; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte3_1; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte3_2; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte4_0; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte4_1; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte4_2; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte5_0; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte5_1; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte5_2; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte6_0; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte6_1; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte6_2; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte7_0; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte7_1; + u32 emc_pmacro_ob_ddll_short_dq_rank1_byte7_2; + u32 emc_pmacro_quse_ddll_rank0_0; + u32 emc_pmacro_quse_ddll_rank0_1; + u32 emc_pmacro_quse_ddll_rank0_2; + u32 emc_pmacro_quse_ddll_rank0_3; + u32 emc_pmacro_quse_ddll_rank1_0; + u32 emc_pmacro_quse_ddll_rank1_1; + u32 emc_pmacro_quse_ddll_rank1_2; + u32 emc_pmacro_quse_ddll_rank1_3; } trim_regs_t; typedef struct { - u32 emc_cmd_brlshft_0_idx; - u32 emc_cmd_brlshft_1_idx; - u32 emc0_data_brlshft_0_idx; - u32 emc1_data_brlshft_0_idx; - u32 emc0_data_brlshft_1_idx; - u32 emc1_data_brlshft_1_idx; - u32 emc_quse_brlshft_0_idx; - u32 emc_quse_brlshft_1_idx; - u32 emc_quse_brlshft_2_idx; - u32 emc_quse_brlshft_3_idx; + u32 emc_cmd_brlshft_0; + u32 emc_cmd_brlshft_1; + u32 emc0_data_brlshft_0; + u32 emc1_data_brlshft_0; + u32 emc0_data_brlshft_1; + u32 emc1_data_brlshft_1; + u32 emc_quse_brlshft_0; + u32 emc_quse_brlshft_1; + u32 emc_quse_brlshft_2; + u32 emc_quse_brlshft_3; } trim_perch_regs_t; typedef struct @@ -460,10 +460,10 @@ typedef struct typedef struct { - u32 emc0_training_opt_dqs_ib_vref_rank0_idx; - u32 emc1_training_opt_dqs_ib_vref_rank0_idx; - u32 emc0_training_opt_dqs_ib_vref_rank1_idx; - u32 emc1_training_opt_dqs_ib_vref_rank1_idx; + u32 emc0_training_opt_dqs_ib_vref_rank0; + u32 emc1_training_opt_dqs_ib_vref_rank0; + u32 emc0_training_opt_dqs_ib_vref_rank1; + u32 emc1_training_opt_dqs_ib_vref_rank1; } vref_perch_regs_t; typedef struct diff --git a/modules/hekate_libsys_minerva/sys_sdrammtc.c b/modules/hekate_libsys_minerva/sys_sdrammtc.c index a2a0c9b..f447501 100644 --- a/modules/hekate_libsys_minerva/sys_sdrammtc.c +++ b/modules/hekate_libsys_minerva/sys_sdrammtc.c @@ -2,7 +2,7 @@ * Minerva Training Cell * DRAM Training for Tegra X1 SoC. Supports LPDDR4. * - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -34,8 +34,6 @@ #define PERF_HACK -bool emc_2X_clk_src_is_pllmb; -bool fsp_for_src_freq; bool train_ram_patterns; /* @@ -82,14 +80,23 @@ static pllm_clk_config_t pllm_clk_config_table[] = {38400, 1459200, 76, 2, 0}, {38400, 1600000, 125, 3, 0}, {38400, 1728000, 90, 2, 0}, // Custom. Normalized 1733 MHz. - {38400, 1795200, 187, 4, 0}, // Custom. + {38400, 1795200, 187, 4, 0}, // Custom. Normalized 1800 MHz. {38400, 1862400, 97, 2, 0}, // JEDEC Standard. (T210 official max). - {38400, 1894400, 148, 3, 0}, // Custom. - {38400, 1932800, 151, 3, 0}, // Custom. + {38400, 1894400, 148, 3, 0}, // Custom. Normalized 1900 MHz. + {38400, 1932800, 151, 3, 0}, // Custom. Normalized 1933 MHz. + {38400, 1958400, 102, 2, 0}, // Custom. Normalized 1966 MHz. {38400, 1996800, 104, 2, 0}, // Custom. Normalized 2000 MHz. - {38400, 2064000, 215, 4, 0}, // Custom. - {38400, 2099200, 164, 3, 0}, // Custom. + {38400, 2035200, 106, 2, 0}, // Custom. Normalized 2033 MHz. + {38400, 2064000, 215, 4, 0}, // Custom. Normalized 2066 MHz. + {38400, 2099200, 164, 3, 0}, // Custom. Normalized 2100 MHz. {38400, 2131200, 111, 2, 0}, // JEDEC Standard. (T210B01 official max). + {38400, 2163200, 169, 3, 0}, // Custom. Normalized 2166 MHz. + {38400, 2188800, 114, 2, 0}, // Custom. Normalized 2200 MHz. + {38400, 2227200, 116, 2, 0}, // Custom. Normalized 2233 MHz. + {38400, 2265600, 118, 2, 0}, // Custom. Normalized 2266 MHz. + {38400, 2291200, 179, 3, 0}, // Custom. Normalized 2300 MHz. + {38400, 2329600, 182, 3, 0}, // Custom. Normalized 2333 MHz. + {38400, 2361600, 123, 2, 0}, // Custom. Normalized 2366 MHz. {0, 0, 0, 0, 0} }; @@ -1161,7 +1168,7 @@ static u32 _get_dram_temperature() if (channel1_enabled) { _request_mmr_data(0x40040000, EMC_CHANNEL1); - mr4_1 = EMC(EMC_MRR); + mr4_1 = EMC(EMC_MRR) & 0xFFFF; if (mr4_1 < 0xF001) mr4_1 &= 0x7; @@ -1182,25 +1189,24 @@ out: return mr4_0; } -static u32 _pllm_clk_base_cfg(u32 rate_KHz, u32 clk_src_emc, bool emc_2X_clk_src_is_PLLMB) +static u32 _pllm_clk_base_cfg(u32 rate_KHz, u32 clk_src_emc, bool new_src_is_PLLMB) { u32 dividers = 0; u32 i = 0; u32 pll_ref = 38400; // Only 38.4MHz crystal is supported for T210. - pllm_clk_config_t *pllm_clk_config; + pllm_clk_config_t *pllm_clk_config = NULL; for (i = 0; pllm_clk_config_table[i].pll_osc_in; i++) { - if (pllm_clk_config_table[i].pll_osc_in == pll_ref && pllm_clk_config_table[i].pll_out == rate_KHz) - break; + if (pllm_clk_config_table[i].pll_osc_in == pll_ref && (pllm_clk_config_table[i].pll_out - 19200) <= rate_KHz) + pllm_clk_config = &pllm_clk_config_table[i]; } - pllm_clk_config = &pllm_clk_config_table[i]; - if (pllm_clk_config->pll_osc_in) + if (pllm_clk_config && pllm_clk_config->pll_osc_in) { dividers = pllm_clk_config->pll_input_div | (pllm_clk_config->pll_feedback_div << 8) | ((pllm_clk_config->pll_post_div & 0x1F) << 20); - if (emc_2X_clk_src_is_PLLMB) + if (new_src_is_PLLMB) { CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) = dividers; CLOCK(CLK_RST_CONTROLLER_PLLMB_BASE) |= PLLM_ENABLE; @@ -1272,8 +1278,8 @@ static u32 _digital_dll_prelock(emc_table_t *mtc_table_entry, u32 needs_tristate while (EMC_CH1(EMC_CFG_DIG_DLL) & 1) ; - EMC(EMC_DLL_CFG_0) = mtc_table_entry->burst_regs.emc_dll_cfg_0_idx; - EMC(EMC_DLL_CFG_1) = mtc_table_entry->burst_regs.emc_dll_cfg_1_idx; + EMC(EMC_DLL_CFG_0) = mtc_table_entry->burst_regs.emc_dll_cfg_0; + EMC(EMC_DLL_CFG_1) = mtc_table_entry->burst_regs.emc_dll_cfg_1; _change_dll_src(mtc_table_entry, selected_clk_src_emc); @@ -1346,19 +1352,19 @@ static u32 _dvfs_power_ramp_down(bool flip_backward, emc_table_t *src_emc_table_ if (flip_backward) { - pmacro_cmd_pad = dst_emc_table_entry->burst_regs.emc_pmacro_cmd_pad_tx_ctrl_idx; - pmacro_dq_pad = dst_emc_table_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl_idx; - pmacro_rfu1 = dst_emc_table_entry->burst_regs.emc_pmacro_brick_ctrl_rfu1_idx; - pmacro_cfg5 = dst_emc_table_entry->burst_regs.emc_fbio_cfg5_idx; - pmacro_common_tx = dst_emc_table_entry->burst_regs.emc_pmacro_common_pad_tx_ctrl_idx; + pmacro_cmd_pad = dst_emc_table_entry->burst_regs.emc_pmacro_cmd_pad_tx_ctrl; + pmacro_dq_pad = dst_emc_table_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl; + pmacro_rfu1 = dst_emc_table_entry->burst_regs.emc_pmacro_brick_ctrl_rfu1; + pmacro_cfg5 = dst_emc_table_entry->burst_regs.emc_fbio_cfg5; + pmacro_common_tx = dst_emc_table_entry->burst_regs.emc_pmacro_common_pad_tx_ctrl; } else { - pmacro_cmd_pad = src_emc_table_entry->burst_regs.emc_pmacro_cmd_pad_tx_ctrl_idx; - pmacro_dq_pad = (dst_emc_table_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl_idx & 0x101) | src_emc_table_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl_idx; - pmacro_rfu1 = src_emc_table_entry->burst_regs.emc_pmacro_brick_ctrl_rfu1_idx; - pmacro_cfg5 = src_emc_table_entry->burst_regs.emc_fbio_cfg5_idx; - pmacro_common_tx = src_emc_table_entry->burst_regs.emc_pmacro_common_pad_tx_ctrl_idx; + pmacro_cmd_pad = src_emc_table_entry->burst_regs.emc_pmacro_cmd_pad_tx_ctrl; + pmacro_dq_pad = (dst_emc_table_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl & 0x101) | src_emc_table_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl; + pmacro_rfu1 = src_emc_table_entry->burst_regs.emc_pmacro_brick_ctrl_rfu1; + pmacro_cfg5 = src_emc_table_entry->burst_regs.emc_fbio_cfg5; + pmacro_common_tx = src_emc_table_entry->burst_regs.emc_pmacro_common_pad_tx_ctrl; } u32 pmacro_cmd_pad_drvforceon = pmacro_cmd_pad | 0x4000000; @@ -1411,7 +1417,7 @@ static u32 _dvfs_power_ramp_down(bool flip_backward, emc_table_t *src_emc_table_ return ramp_down_wait; } -static u32 _dvfs_power_ramp_up(bool flip_backward, emc_table_t *src_emc_table_entry, emc_table_t *dst_emc_table_entry, u8 needs_training, u32 dst_clock_period) +static u32 _dvfs_power_ramp_up(bool flip_backward, emc_table_t *src_emc_table_entry, emc_table_t *dst_emc_table_entry, u32 needs_training, u32 dst_clock_period) { u32 pmacro_cmd_pad; u32 pmacro_dq_pad; @@ -1425,43 +1431,43 @@ static u32 _dvfs_power_ramp_up(bool flip_backward, emc_table_t *src_emc_table_en if (flip_backward) { - pmacro_cmd_pad = src_emc_table_entry->burst_regs.emc_pmacro_cmd_pad_tx_ctrl_idx; - pmacro_dq_pad = src_emc_table_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl_idx; - pmacro_rfu1 = src_emc_table_entry->burst_regs.emc_pmacro_brick_ctrl_rfu1_idx; - pmacro_cfg5 = src_emc_table_entry->burst_regs.emc_fbio_cfg5_idx; - pmacro_common_tx = src_emc_table_entry->burst_regs.emc_pmacro_common_pad_tx_ctrl_idx; + pmacro_cmd_pad = src_emc_table_entry->burst_regs.emc_pmacro_cmd_pad_tx_ctrl; + pmacro_dq_pad = src_emc_table_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl; + pmacro_rfu1 = src_emc_table_entry->burst_regs.emc_pmacro_brick_ctrl_rfu1; + pmacro_cfg5 = src_emc_table_entry->burst_regs.emc_fbio_cfg5; + pmacro_common_tx = src_emc_table_entry->burst_regs.emc_pmacro_common_pad_tx_ctrl; } - else if (needs_training & 3) + else if (needs_training & NEEDS_TRAINING_CA_COMBO) { - pmacro_cmd_pad = dst_emc_table_entry->shadow_regs_ca_train.emc_pmacro_cmd_pad_tx_ctrl_idx; - pmacro_dq_pad = dst_emc_table_entry->shadow_regs_ca_train.emc_pmacro_data_pad_tx_ctrl_idx; - pmacro_rfu1 = dst_emc_table_entry->shadow_regs_ca_train.emc_pmacro_brick_ctrl_rfu1_idx; - pmacro_cfg5 = dst_emc_table_entry->shadow_regs_ca_train.emc_fbio_cfg5_idx; - pmacro_common_tx = dst_emc_table_entry->shadow_regs_ca_train.emc_pmacro_common_pad_tx_ctrl_idx; + pmacro_cmd_pad = dst_emc_table_entry->shadow_regs_ca_train.emc_pmacro_cmd_pad_tx_ctrl; + pmacro_dq_pad = dst_emc_table_entry->shadow_regs_ca_train.emc_pmacro_data_pad_tx_ctrl; + pmacro_rfu1 = dst_emc_table_entry->shadow_regs_ca_train.emc_pmacro_brick_ctrl_rfu1; + pmacro_cfg5 = dst_emc_table_entry->shadow_regs_ca_train.emc_fbio_cfg5; + pmacro_common_tx = dst_emc_table_entry->shadow_regs_ca_train.emc_pmacro_common_pad_tx_ctrl; } - else if (needs_training & 0xC) + else if (needs_training & NEEDS_TRAINING_QUSE_COMBO) { - pmacro_cmd_pad = dst_emc_table_entry->shadow_regs_quse_train.emc_pmacro_cmd_pad_tx_ctrl_idx; - pmacro_dq_pad = dst_emc_table_entry->shadow_regs_quse_train.emc_pmacro_data_pad_tx_ctrl_idx; - pmacro_rfu1 = dst_emc_table_entry->shadow_regs_quse_train.emc_pmacro_brick_ctrl_rfu1_idx; - pmacro_cfg5 = dst_emc_table_entry->shadow_regs_quse_train.emc_fbio_cfg5_idx; - pmacro_common_tx = dst_emc_table_entry->shadow_regs_quse_train.emc_pmacro_common_pad_tx_ctrl_idx; + pmacro_cmd_pad = dst_emc_table_entry->shadow_regs_quse_train.emc_pmacro_cmd_pad_tx_ctrl; + pmacro_dq_pad = dst_emc_table_entry->shadow_regs_quse_train.emc_pmacro_data_pad_tx_ctrl; + pmacro_rfu1 = dst_emc_table_entry->shadow_regs_quse_train.emc_pmacro_brick_ctrl_rfu1; + pmacro_cfg5 = dst_emc_table_entry->shadow_regs_quse_train.emc_fbio_cfg5; + pmacro_common_tx = dst_emc_table_entry->shadow_regs_quse_train.emc_pmacro_common_pad_tx_ctrl; } - else if (needs_training & 0xF0) + else if (needs_training & (NEEDS_TRAINING_WR_COMBO | NEEDS_TRAINING_RD_COMBO)) { - pmacro_cmd_pad = dst_emc_table_entry->shadow_regs_rdwr_train.emc_pmacro_cmd_pad_tx_ctrl_idx; - pmacro_dq_pad = dst_emc_table_entry->shadow_regs_rdwr_train.emc_pmacro_data_pad_tx_ctrl_idx; - pmacro_rfu1 = dst_emc_table_entry->shadow_regs_rdwr_train.emc_pmacro_brick_ctrl_rfu1_idx; - pmacro_cfg5 = dst_emc_table_entry->shadow_regs_rdwr_train.emc_fbio_cfg5_idx; - pmacro_common_tx = dst_emc_table_entry->shadow_regs_rdwr_train.emc_pmacro_common_pad_tx_ctrl_idx; + pmacro_cmd_pad = dst_emc_table_entry->shadow_regs_rdwr_train.emc_pmacro_cmd_pad_tx_ctrl; + pmacro_dq_pad = dst_emc_table_entry->shadow_regs_rdwr_train.emc_pmacro_data_pad_tx_ctrl; + pmacro_rfu1 = dst_emc_table_entry->shadow_regs_rdwr_train.emc_pmacro_brick_ctrl_rfu1; + pmacro_cfg5 = dst_emc_table_entry->shadow_regs_rdwr_train.emc_fbio_cfg5; + pmacro_common_tx = dst_emc_table_entry->shadow_regs_rdwr_train.emc_pmacro_common_pad_tx_ctrl; } else { - pmacro_cmd_pad = dst_emc_table_entry->burst_regs.emc_pmacro_cmd_pad_tx_ctrl_idx; - pmacro_dq_pad = dst_emc_table_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl_idx; - pmacro_rfu1 = dst_emc_table_entry->burst_regs.emc_pmacro_brick_ctrl_rfu1_idx; - pmacro_cfg5 = dst_emc_table_entry->burst_regs.emc_fbio_cfg5_idx; - pmacro_common_tx = dst_emc_table_entry->burst_regs.emc_pmacro_common_pad_tx_ctrl_idx; + pmacro_cmd_pad = dst_emc_table_entry->burst_regs.emc_pmacro_cmd_pad_tx_ctrl; + pmacro_dq_pad = dst_emc_table_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl; + pmacro_rfu1 = dst_emc_table_entry->burst_regs.emc_pmacro_brick_ctrl_rfu1; + pmacro_cfg5 = dst_emc_table_entry->burst_regs.emc_fbio_cfg5; + pmacro_common_tx = dst_emc_table_entry->burst_regs.emc_pmacro_common_pad_tx_ctrl; } pmacro_cmd_pad_data = (pmacro_cmd_pad & 0xFAFEFDFD) | 0x4000000; @@ -1543,21 +1549,25 @@ static u32 _minerva_update_clock_tree_delay(emc_table_t *src_emc_entry, emc_tabl if (upd_type_bits & 0x5400) { _request_mmr_data(0x80130000, channel1_enabled); // Dev0 MRR 19. - temp_ch0_0 = (EMC(EMC_MRR) & 0xFF) << 8; - temp_ch0_1 = EMC(EMC_MRR) & 0xFF00; + u32 mrr = EMC(EMC_MRR); + temp_ch0_0 = (mrr & 0xFF) << 8; + temp_ch0_1 = mrr & 0xFF00; if (channel1_enabled) { - temp_ch1_0 = (EMC_CH1(EMC_MRR) & 0xFF) << 8; - temp_ch1_1 = EMC_CH1(EMC_MRR) & 0xFF00; + mrr = EMC_CH1(EMC_MRR); + temp_ch1_0 = (mrr & 0xFF) << 8; + temp_ch1_1 = mrr & 0xFF00; } _request_mmr_data(0x80120000, channel1_enabled); // Dev0 MRR 18. - temp_ch0_0 |= EMC(EMC_MRR) & 0xFF; - temp_ch0_1 |= (EMC(EMC_MRR) & 0xFF00) >> 8; + mrr = EMC(EMC_MRR); + temp_ch0_0 |= mrr & 0xFF; + temp_ch0_1 |= (mrr & 0xFF00) >> 8; if (channel1_enabled) { - temp_ch1_0 |= EMC_CH1(EMC_MRR) & 0xFF; - temp_ch1_1 |= (EMC_CH1(EMC_MRR) & 0xFF00) >> 8; + mrr = EMC_CH1(EMC_MRR); + temp_ch1_0 |= mrr & 0xFF; + temp_ch1_1 |= (mrr & 0xFF00) >> 8; } } @@ -1566,22 +1576,22 @@ static u32 _minerva_update_clock_tree_delay(emc_table_t *src_emc_entry, emc_tabl { case DVFS_PT1: case TRAINING_PT1: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0_idx += 100 * cval; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0 += 100 * cval; if (update_type > PERIODIC_TRAINING_UPDATE || !(upd_type_bits & 0x6800)) goto calc_td0_0; break; case DVFS_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0_idx = - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0_idx / dst_emc_entry->ptfv_list.ptfv_dvfs_samples_idx; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0 = + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0 / dst_emc_entry->ptfv_list.ptfv_dvfs_samples; break; case TRAINING_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0_idx = - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0_idx / dst_emc_entry->ptfv_list.ptfv_write_samples_idx; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0 = + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0 / dst_emc_entry->ptfv_list.ptfv_write_samples; break; case PERIODIC_TRAINING_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0_idx = - (100 * cval + dst_emc_entry->ptfv_list.ptfv_movavg_weight_idx * dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0_idx) - / (dst_emc_entry->ptfv_list.ptfv_movavg_weight_idx + 1); + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0 = + (100 * cval + dst_emc_entry->ptfv_list.ptfv_movavg_weight * dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0) + / (dst_emc_entry->ptfv_list.ptfv_movavg_weight + 1); break; default: if (update_type > PERIODIC_TRAINING_UPDATE || !(upd_type_bits & 0x6800)) @@ -1589,12 +1599,12 @@ static u32 _minerva_update_clock_tree_delay(emc_table_t *src_emc_entry, emc_tabl break; } - tdelta = dst_emc_entry->current_dram_clktree_c0d0u0 - (dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0_idx / 100); + tdelta = dst_emc_entry->current_dram_clktree_c0d0u0 - (dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0 / 100); if (tdelta < 0) tdelta *= -1; adelta = tdelta; if (update_type == TRAINING_UPDATE || ((dst_rate_mhz * tdelta * 128) / 1000000) > dst_emc_entry->tree_margin) - dst_emc_entry->current_dram_clktree_c0d0u0 = dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0_idx / 100; + dst_emc_entry->current_dram_clktree_c0d0u0 = dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0 / 100; calc_td0_0: cval = tval / (src_rate_mhz * temp_ch0_1); @@ -1602,22 +1612,22 @@ calc_td0_0: { case DVFS_PT1: case TRAINING_PT1: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1_idx += 100 * cval; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1 += 100 * cval; if (update_type > PERIODIC_TRAINING_UPDATE || !(upd_type_bits & 0x6800)) goto calc_td1_0; break; case DVFS_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1_idx = - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1_idx / dst_emc_entry->ptfv_list.ptfv_dvfs_samples_idx; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1 = + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1 / dst_emc_entry->ptfv_list.ptfv_dvfs_samples; break; case TRAINING_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1_idx = - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1_idx / dst_emc_entry->ptfv_list.ptfv_write_samples_idx; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1 = + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1 / dst_emc_entry->ptfv_list.ptfv_write_samples; break; case PERIODIC_TRAINING_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1_idx = - (100 * cval + dst_emc_entry->ptfv_list.ptfv_movavg_weight_idx * dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1_idx) - / (dst_emc_entry->ptfv_list.ptfv_movavg_weight_idx + 1); + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1 = + (100 * cval + dst_emc_entry->ptfv_list.ptfv_movavg_weight * dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1) + / (dst_emc_entry->ptfv_list.ptfv_movavg_weight + 1); break; default: if (update_type > PERIODIC_TRAINING_UPDATE || !(upd_type_bits & 0x6800)) @@ -1625,13 +1635,13 @@ calc_td0_0: break; } - tdelta = dst_emc_entry->current_dram_clktree_c0d0u1 - (dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1_idx / 100); + tdelta = dst_emc_entry->current_dram_clktree_c0d0u1 - (dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1 / 100); if (tdelta < 0) tdelta *= -1; if ((u32)tdelta > adelta) adelta = tdelta; if (update_type == TRAINING_UPDATE || ((dst_rate_mhz * tdelta * 128) / 1000000) > dst_emc_entry->tree_margin) - dst_emc_entry->current_dram_clktree_c0d0u1 = dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1_idx / 100; + dst_emc_entry->current_dram_clktree_c0d0u1 = dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1 / 100; calc_td1_0: if (channel1_enabled) @@ -1641,22 +1651,22 @@ calc_td1_0: { case DVFS_PT1: case TRAINING_PT1: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0_idx += 100 * cval; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0 += 100 * cval; if (update_type > PERIODIC_TRAINING_UPDATE || !(upd_type_bits & 0x6800)) goto calc_td1_1; break; case DVFS_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0_idx = - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0_idx / dst_emc_entry->ptfv_list.ptfv_dvfs_samples_idx; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0 = + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0 / dst_emc_entry->ptfv_list.ptfv_dvfs_samples; break; case TRAINING_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0_idx = - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0_idx / dst_emc_entry->ptfv_list.ptfv_write_samples_idx; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0 = + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0 / dst_emc_entry->ptfv_list.ptfv_write_samples; break; case PERIODIC_TRAINING_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0_idx = - (100 * cval + dst_emc_entry->ptfv_list.ptfv_movavg_weight_idx * dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0_idx) - / (dst_emc_entry->ptfv_list.ptfv_movavg_weight_idx + 1); + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0 = + (100 * cval + dst_emc_entry->ptfv_list.ptfv_movavg_weight * dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0) + / (dst_emc_entry->ptfv_list.ptfv_movavg_weight + 1); break; default: if (update_type > PERIODIC_TRAINING_UPDATE || !(upd_type_bits & 0x6800)) @@ -1664,13 +1674,13 @@ calc_td1_0: break; } - tdelta = dst_emc_entry->current_dram_clktree_c1d0u0 - (dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0_idx / 100); + tdelta = dst_emc_entry->current_dram_clktree_c1d0u0 - (dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0 / 100); if (tdelta < 0) tdelta *= -1; if ((u32)tdelta > adelta) adelta = tdelta; if (update_type == TRAINING_UPDATE || ((dst_rate_mhz * tdelta * 128) / 1000000) > dst_emc_entry->tree_margin) - dst_emc_entry->current_dram_clktree_c1d0u0 = dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0_idx / 100; + dst_emc_entry->current_dram_clktree_c1d0u0 = dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0 / 100; calc_td1_1: cval = tval / (src_rate_mhz * temp_ch1_1); @@ -1678,22 +1688,22 @@ calc_td1_1: { case DVFS_PT1: case TRAINING_PT1: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1_idx += 100 * cval; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1 += 100 * cval; if (update_type > PERIODIC_TRAINING_UPDATE || !(upd_type_bits & 0x6800)) goto calc_dev2; break; case DVFS_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1_idx = - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1_idx / dst_emc_entry->ptfv_list.ptfv_dvfs_samples_idx; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1 = + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1 / dst_emc_entry->ptfv_list.ptfv_dvfs_samples; break; case TRAINING_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1_idx = - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1_idx / dst_emc_entry->ptfv_list.ptfv_write_samples_idx; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1 = + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1 / dst_emc_entry->ptfv_list.ptfv_write_samples; break; case PERIODIC_TRAINING_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1_idx = - (100 * cval + dst_emc_entry->ptfv_list.ptfv_movavg_weight_idx * dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1_idx) - / (dst_emc_entry->ptfv_list.ptfv_movavg_weight_idx + 1); + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1 = + (100 * cval + dst_emc_entry->ptfv_list.ptfv_movavg_weight * dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1) + / (dst_emc_entry->ptfv_list.ptfv_movavg_weight + 1); break; default: if (update_type > PERIODIC_TRAINING_UPDATE || !(upd_type_bits & 0x6800)) @@ -1701,13 +1711,13 @@ calc_td1_1: break; } - tdelta = dst_emc_entry->current_dram_clktree_c1d0u1 - (dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1_idx / 100); + tdelta = dst_emc_entry->current_dram_clktree_c1d0u1 - (dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1 / 100); if (tdelta < 0) tdelta *= -1; if ((u32)tdelta > adelta) adelta = tdelta; if (update_type == TRAINING_UPDATE || ((dst_rate_mhz * tdelta * 128) / 1000000) > dst_emc_entry->tree_margin) - dst_emc_entry->current_dram_clktree_c1d0u1 = dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1_idx / 100; + dst_emc_entry->current_dram_clktree_c1d0u1 = dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1 / 100; } calc_dev2: @@ -1717,21 +1727,25 @@ calc_dev2: if (update_type <= PERIODIC_TRAINING_UPDATE && upd_type_bits & 0x5400) { _request_mmr_data(0x40130000, channel1_enabled); // Dev1 MRR 19. - temp_ch0_0 = (EMC(EMC_MRR) & 0xFF) << 8; - temp_ch0_1 = EMC(EMC_MRR) & 0xFF00; + u32 mrr = EMC(EMC_MRR); + temp_ch0_0 = (mrr& 0xFF) << 8; + temp_ch0_1 = mrr & 0xFF00; if (channel1_enabled) { - temp_ch1_0 = (EMC_CH1(EMC_MRR) & 0xFF) << 8; - temp_ch1_1 = EMC_CH1(EMC_MRR) & 0xFF00; + mrr = EMC_CH1(EMC_MRR); + temp_ch1_0 = (mrr & 0xFF) << 8; + temp_ch1_1 = mrr & 0xFF00; } _request_mmr_data(0x40120000, channel1_enabled); // Dev1 MRR 18 - temp_ch0_0 |= EMC(EMC_MRR) & 0xFF; - temp_ch0_1 |= ((EMC(EMC_MRR) & 0xFF00) >> 8); + mrr = EMC(EMC_MRR); + temp_ch0_0 |= mrr & 0xFF; + temp_ch0_1 |= ((mrr & 0xFF00) >> 8); if (channel1_enabled) { - temp_ch1_0 |= EMC_CH1(EMC_MRR) & 0xFF; - temp_ch1_1 |= (EMC_CH1(EMC_MRR) & 0xFF00) >> 8; + mrr = EMC_CH1(EMC_MRR); + temp_ch1_0 |= mrr & 0xFF; + temp_ch1_1 |= (mrr & 0xFF00) >> 8; } } @@ -1740,22 +1754,22 @@ calc_dev2: { case DVFS_PT1: case TRAINING_PT1: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0_idx += 100 * cval; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0 += 100 * cval; if (update_type > PERIODIC_TRAINING_UPDATE || !(upd_type_bits & 0x6800)) goto calc_tmp_td0_1; break; case DVFS_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0_idx = - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0_idx / dst_emc_entry->ptfv_list.ptfv_dvfs_samples_idx; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0 = + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0 / dst_emc_entry->ptfv_list.ptfv_dvfs_samples; break; case TRAINING_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0_idx = - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0_idx / dst_emc_entry->ptfv_list.ptfv_write_samples_idx; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0 = + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0 / dst_emc_entry->ptfv_list.ptfv_write_samples; break; case PERIODIC_TRAINING_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0_idx = - (100 * cval + dst_emc_entry->ptfv_list.ptfv_movavg_weight_idx * dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0_idx) - / (dst_emc_entry->ptfv_list.ptfv_movavg_weight_idx + 1); + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0 = + (100 * cval + dst_emc_entry->ptfv_list.ptfv_movavg_weight * dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0) + / (dst_emc_entry->ptfv_list.ptfv_movavg_weight + 1); break; default: if (update_type > PERIODIC_TRAINING_UPDATE || !(upd_type_bits & 0x6800)) @@ -1763,13 +1777,13 @@ calc_dev2: break; } - tdelta = dst_emc_entry->current_dram_clktree_c0d1u0 - (dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0_idx / 100); + tdelta = dst_emc_entry->current_dram_clktree_c0d1u0 - (dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0 / 100); if (tdelta < 0) tdelta *= -1; if ((u32)tdelta > adelta) adelta = tdelta; if (update_type == TRAINING_UPDATE || ((dst_rate_mhz * tdelta * 128) / 1000000) > dst_emc_entry->tree_margin) - dst_emc_entry->current_dram_clktree_c0d1u0 = dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0_idx / 100; + dst_emc_entry->current_dram_clktree_c0d1u0 = dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0 / 100; calc_tmp_td0_1: cval = tval / (src_rate_mhz * temp_ch0_1); @@ -1777,22 +1791,22 @@ calc_tmp_td0_1: { case DVFS_PT1: case TRAINING_PT1: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1_idx += 100 * cval; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1 += 100 * cval; if (update_type > PERIODIC_TRAINING_UPDATE || !(upd_type_bits & 0x6800)) goto calc_tmp_td1_0; break; case DVFS_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1_idx = - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1_idx / dst_emc_entry->ptfv_list.ptfv_dvfs_samples_idx; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1 = + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1 / dst_emc_entry->ptfv_list.ptfv_dvfs_samples; break; case TRAINING_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1_idx = - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1_idx / dst_emc_entry->ptfv_list.ptfv_write_samples_idx; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1 = + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1 / dst_emc_entry->ptfv_list.ptfv_write_samples; break; case PERIODIC_TRAINING_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1_idx = - (100 * cval + dst_emc_entry->ptfv_list.ptfv_movavg_weight_idx * dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1_idx) - / (dst_emc_entry->ptfv_list.ptfv_movavg_weight_idx + 1); + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1 = + (100 * cval + dst_emc_entry->ptfv_list.ptfv_movavg_weight * dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1) + / (dst_emc_entry->ptfv_list.ptfv_movavg_weight + 1); break; default: if (update_type > PERIODIC_TRAINING_UPDATE || !(upd_type_bits & 0x6800)) @@ -1800,13 +1814,13 @@ calc_tmp_td0_1: break; } - tdelta = dst_emc_entry->current_dram_clktree_c0d1u1 - (dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1_idx / 100); + tdelta = dst_emc_entry->current_dram_clktree_c0d1u1 - (dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1 / 100); if (tdelta < 0) tdelta *= -1; if ((u32)tdelta > adelta) adelta = tdelta; if (update_type == TRAINING_UPDATE || ((dst_rate_mhz * tdelta * 128) / 1000000) > dst_emc_entry->tree_margin) - dst_emc_entry->current_dram_clktree_c0d1u1 = dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1_idx / 100; + dst_emc_entry->current_dram_clktree_c0d1u1 = dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1 / 100; calc_tmp_td1_0: if (channel1_enabled) @@ -1816,22 +1830,22 @@ calc_tmp_td1_0: { case DVFS_PT1: case TRAINING_PT1: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0_idx += 100 * cval; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0 += 100 * cval; if (update_type > PERIODIC_TRAINING_UPDATE || !(upd_type_bits & 0x6800)) goto calc_tmp_td1_1; break; case DVFS_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0_idx = - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0_idx / dst_emc_entry->ptfv_list.ptfv_dvfs_samples_idx; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0 = + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0 / dst_emc_entry->ptfv_list.ptfv_dvfs_samples; break; case TRAINING_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0_idx = - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0_idx / dst_emc_entry->ptfv_list.ptfv_write_samples_idx; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0 = + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0 / dst_emc_entry->ptfv_list.ptfv_write_samples; break; case PERIODIC_TRAINING_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0_idx = - (100 * cval + dst_emc_entry->ptfv_list.ptfv_movavg_weight_idx * dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0_idx) - / (dst_emc_entry->ptfv_list.ptfv_movavg_weight_idx + 1); + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0 = + (100 * cval + dst_emc_entry->ptfv_list.ptfv_movavg_weight * dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0) + / (dst_emc_entry->ptfv_list.ptfv_movavg_weight + 1); break; default: if (update_type > PERIODIC_TRAINING_UPDATE || !(upd_type_bits & 0x6800)) @@ -1839,13 +1853,13 @@ calc_tmp_td1_0: break; } - tdelta = dst_emc_entry->current_dram_clktree_c1d1u0 - (dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0_idx / 100); + tdelta = dst_emc_entry->current_dram_clktree_c1d1u0 - (dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0 / 100); if (tdelta < 0) tdelta *= -1; if ((u32)tdelta > adelta) adelta = tdelta; if (update_type == TRAINING_UPDATE || ((dst_rate_mhz * tdelta * 128) / 1000000) > dst_emc_entry->tree_margin) - dst_emc_entry->current_dram_clktree_c1d1u0 = dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0_idx / 100; + dst_emc_entry->current_dram_clktree_c1d1u0 = dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0 / 100; calc_tmp_td1_1: cval = tval / (src_rate_mhz * temp_ch1_1); @@ -1853,22 +1867,22 @@ calc_tmp_td1_1: { case DVFS_PT1: case TRAINING_PT1: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1_idx += 100 * cval; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1 += 100 * cval; if (update_type > PERIODIC_TRAINING_UPDATE || !(upd_type_bits & 0x6800)) goto out; break; case DVFS_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1_idx = - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1_idx / dst_emc_entry->ptfv_list.ptfv_dvfs_samples_idx; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1 = + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1 / dst_emc_entry->ptfv_list.ptfv_dvfs_samples; break; case TRAINING_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1_idx = - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1_idx / dst_emc_entry->ptfv_list.ptfv_write_samples_idx; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1 = + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1 / dst_emc_entry->ptfv_list.ptfv_write_samples; break; case PERIODIC_TRAINING_UPDATE: - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1_idx = - (100 * cval + dst_emc_entry->ptfv_list.ptfv_movavg_weight_idx * dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1_idx) - / (dst_emc_entry->ptfv_list.ptfv_movavg_weight_idx + 1); + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1 = + (100 * cval + dst_emc_entry->ptfv_list.ptfv_movavg_weight * dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1) + / (dst_emc_entry->ptfv_list.ptfv_movavg_weight + 1); break; default: if (update_type > PERIODIC_TRAINING_UPDATE || !(upd_type_bits & 0x6800)) @@ -1876,13 +1890,13 @@ calc_tmp_td1_1: break; } - tdelta = dst_emc_entry->current_dram_clktree_c1d1u1 - (dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1_idx / 100); + tdelta = dst_emc_entry->current_dram_clktree_c1d1u1 - (dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1 / 100); if (tdelta < 0) tdelta *= -1; if ((u32)tdelta > adelta) adelta = tdelta; if (update_type == TRAINING_UPDATE || ((dst_rate_mhz * tdelta * 128) / 1000000) > dst_emc_entry->tree_margin) - dst_emc_entry->current_dram_clktree_c1d1u1 = dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1_idx / 100; + dst_emc_entry->current_dram_clktree_c1d1u1 = dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1 / 100; } out: @@ -1910,30 +1924,30 @@ static u32 _minerva_periodic_compensation_handler(emc_table_t *src_emc_entry, em if (seq_type == DVFS_SEQUENCE) { - if (src_emc_entry->periodic_training && dst_emc_entry->ptfv_list.ptfv_config_ctrl_idx & 1) + if (src_emc_entry->periodic_training && dst_emc_entry->ptfv_list.ptfv_config_ctrl & 1) { - u32 samples = dst_emc_entry->ptfv_list.ptfv_dvfs_samples_idx; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0_idx = src_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0_idx * samples; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1_idx = src_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1_idx * samples; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0_idx = src_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0_idx * samples; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1_idx = src_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1_idx * samples; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0_idx = src_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0_idx * samples; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1_idx = src_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1_idx * samples; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0_idx = src_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0_idx * samples; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1_idx = src_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1_idx * samples; + u32 samples = dst_emc_entry->ptfv_list.ptfv_dvfs_samples; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0 = src_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0 * samples; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1 = src_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1 * samples; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0 = src_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0 * samples; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1 = src_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1 * samples; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0 = src_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0 * samples; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1 = src_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1 * samples; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0 = src_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0 * samples; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1 = src_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1 * samples; } else { - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0_idx = 0; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1_idx = 0; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0_idx = 0; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1_idx = 0; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0_idx = 0; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1_idx = 0; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0_idx = 0; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1_idx = 0; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0 = 0; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1 = 0; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0 = 0; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1 = 0; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0 = 0; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1 = 0; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0 = 0; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1 = 0; - for (u32 i = 0; i < dst_emc_entry->ptfv_list.ptfv_dvfs_samples_idx; i++) + for (u32 i = 0; i < dst_emc_entry->ptfv_list.ptfv_dvfs_samples; i++) { _start_periodic_compensation(); _usleep(delay); @@ -1945,16 +1959,16 @@ static u32 _minerva_periodic_compensation_handler(emc_table_t *src_emc_entry, em } else if (seq_type == WRITE_TRAINING_SEQUENCE) { - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0_idx = 0; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1_idx = 0; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0_idx = 0; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1_idx = 0; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0_idx = 0; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1_idx = 0; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0_idx = 0; - dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1_idx = 0; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u0 = 0; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d0u1 = 0; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u0 = 0; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d0u1 = 0; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u0 = 0; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c0d1u1 = 0; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u0 = 0; + dst_emc_entry->ptfv_list.ptfv_dqsosc_movavg_c1d1u1 = 0; - for (u32 i = 0; i < dst_emc_entry->ptfv_list.ptfv_write_samples_idx; i++) + for (u32 i = 0; i < dst_emc_entry->ptfv_list.ptfv_write_samples; i++) { _start_periodic_compensation(); _usleep(delay); @@ -1974,10 +1988,10 @@ static u32 _minerva_periodic_compensation_handler(emc_table_t *src_emc_entry, em } #define STORE_TRIM_VAL(chan, rank, reg, byte) \ - ((mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank##rank##_##reg##_idx >> \ + ((mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank##rank##_##reg >> \ EMC_PMACRO_OB_DDLL_LONG_DQ_BYTE##byte##_SHIFT) & 0x7FF) \ + \ - (((mtc_table_entry->trim_perch_regs.emc##chan##_data_brlshft_##rank##_idx >> \ + (((mtc_table_entry->trim_perch_regs.emc##chan##_data_brlshft_##rank >> \ EMC_DATA_BRLSHFT_##rank##_RANK##rank##_BYTE##byte##_DATA_BRLSHFT_SHIFT) & 0x7) << 6) static u32 _minerva_apply_periodic_compensation_trimmer(emc_table_t *mtc_table_entry, u32 trim_emc_reg_addr) @@ -2190,44 +2204,44 @@ static bool _check_freq_changed(u32 dst_entry_rate_KHz, u32 dst_entry_clk_src_em static void _save_train_results(emc_table_t *mtc_table_entry, u32 needs_training, u32 dram_dev_num, bool channel1_enabled) { - bool needs_ca_training = needs_training & 1; - bool needs_ca_vref_training = (needs_training >> 1) & 1; - bool needs_quse_training = (needs_training >> 2) & 1; - bool needs_quse_vref_training = (needs_training >> 3) & 1; - bool needs_wr_training = (needs_training >> 4) & 1; - bool needs_wr_vref_training = (needs_training >> 5) & 1; - bool needs_rd_training = (needs_training >> 6) & 1; - bool needs_rd_vref_training = (needs_training >> 7) & 1; - bool needs_training_in_self_refresh = (needs_training >> 9) & 1; + bool needs_ca_training = !!(needs_training & NEEDS_TRAINING_CA); + bool needs_ca_vref_training = !!(needs_training & NEEDS_TRAINING_CA_VREF); + bool needs_quse_training = !!(needs_training & NEEDS_TRAINING_QUSE); + bool needs_quse_vref_training = !!(needs_training & NEEDS_TRAINING_QUSE_VREF); + bool needs_wr_training = !!(needs_training & NEEDS_TRAINING_WR); + bool needs_wr_vref_training = !!(needs_training & NEEDS_TRAINING_WR_VREF); + bool needs_rd_training = !!(needs_training & NEEDS_TRAINING_RD); + bool needs_rd_vref_training = !!(needs_training & NEEDS_TRAINING_RD_VREF); + bool needs_training_in_self_refresh = !!(needs_training & NEEDS_TRAINING_IN_SELF_REFRESH); if (needs_ca_training) { - mtc_table_entry->trim_perch_regs.emc_cmd_brlshft_0_idx = EMC_CH0(EMC_CMD_BRLSHFT_0); - mtc_table_entry->trim_perch_regs.emc_cmd_brlshft_1_idx = channel1_enabled ? EMC_CH1(EMC_CMD_BRLSHFT_1) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_4_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_5_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5) : 0; + mtc_table_entry->trim_perch_regs.emc_cmd_brlshft_0 = EMC_CH0(EMC_CMD_BRLSHFT_0); + mtc_table_entry->trim_perch_regs.emc_cmd_brlshft_1 = channel1_enabled ? EMC_CH1(EMC_CMD_BRLSHFT_1) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_4 = EMC_CH0(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_4); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_5 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_5) : 0; if (needs_training_in_self_refresh) { - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd0_0_idx = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd0_1_idx = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd0_2_idx = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd1_0_idx = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd1_1_idx = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd1_2_idx = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd2_0_idx = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd2_1_idx = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd2_2_idx = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd3_0_idx = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd3_1_idx = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd3_2_idx = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd0_0 = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_0); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd0_1 = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_1); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd0_2 = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD0_2); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd1_0 = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_0); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd1_1 = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_1); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd1_2 = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD1_2); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd2_0 = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_0); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd2_1 = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_1); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd2_2 = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD2_2); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd3_0 = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_0); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd3_1 = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_1); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_cmd3_2 = EMC(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_CMD3_2); } } if (needs_ca_vref_training) { - mtc_table_entry->burst_reg_per_ch.emc0_mrw10_idx = (EMC_CH0(EMC_TRAINING_OPT_CA_VREF) & 0xFFFF) | 0x880C0000; - mtc_table_entry->burst_reg_per_ch.emc1_mrw10_idx = (channel1_enabled ? EMC_CH1(EMC_TRAINING_OPT_CA_VREF) & 0xFFFF : 0) | 0x880C0000; + mtc_table_entry->burst_reg_per_ch.emc0_mrw10 = (EMC_CH0(EMC_TRAINING_OPT_CA_VREF) & 0xFFFF) | 0x880C0000; + mtc_table_entry->burst_reg_per_ch.emc1_mrw10 = (channel1_enabled ? EMC_CH1(EMC_TRAINING_OPT_CA_VREF) & 0xFFFF : 0) | 0x880C0000; u32 mrw11_dev_selectn; if (dram_dev_num == TWO_RANK) @@ -2235,12 +2249,12 @@ static void _save_train_results(emc_table_t *mtc_table_entry, u32 needs_training else mrw11_dev_selectn = 0xC80C0000; - mtc_table_entry->burst_reg_per_ch.emc0_mrw11_idx = + mtc_table_entry->burst_reg_per_ch.emc0_mrw11 = ((EMC_CH0(EMC_TRAINING_OPT_CA_VREF) >> 16) & 0xFF) | (EMC_CH0(EMC_TRAINING_OPT_CA_VREF) >> 24 << 8) | (mrw11_dev_selectn & 0xFFFFFF00); - mtc_table_entry->burst_reg_per_ch.emc1_mrw11_idx = + mtc_table_entry->burst_reg_per_ch.emc1_mrw11 = (((channel1_enabled ? EMC_CH1(EMC_TRAINING_OPT_CA_VREF) : 0) >> 16) & 0xFF) | ((channel1_enabled ? EMC_CH1(EMC_TRAINING_OPT_CA_VREF) : 0) >> 24 << 8) | (mrw11_dev_selectn & 0xFFFFFF00); @@ -2248,23 +2262,23 @@ static void _save_train_results(emc_table_t *mtc_table_entry, u32 needs_training if (needs_quse_training || needs_rd_training) { - mtc_table_entry->trim_perch_regs.emc_quse_brlshft_0_idx = EMC_CH0(EMC_QUSE_BRLSHFT_0); - mtc_table_entry->trim_perch_regs.emc_quse_brlshft_1_idx = channel1_enabled ? EMC_CH1(EMC_QUSE_BRLSHFT_1) : 0; + mtc_table_entry->trim_perch_regs.emc_quse_brlshft_0 = EMC_CH0(EMC_QUSE_BRLSHFT_0); + mtc_table_entry->trim_perch_regs.emc_quse_brlshft_1 = channel1_enabled ? EMC_CH1(EMC_QUSE_BRLSHFT_1) : 0; - mtc_table_entry->trim_regs.emc_pmacro_quse_ddll_rank0_0_idx = EMC_CH0(EMC_PMACRO_QUSE_DDLL_RANK0_0); - mtc_table_entry->trim_regs.emc_pmacro_quse_ddll_rank0_1_idx = EMC_CH0(EMC_PMACRO_QUSE_DDLL_RANK0_1); - mtc_table_entry->trim_regs.emc_pmacro_quse_ddll_rank0_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_QUSE_DDLL_RANK0_2) : 0; - mtc_table_entry->trim_regs.emc_pmacro_quse_ddll_rank0_3_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_QUSE_DDLL_RANK0_3) : 0; + mtc_table_entry->trim_regs.emc_pmacro_quse_ddll_rank0_0 = EMC_CH0(EMC_PMACRO_QUSE_DDLL_RANK0_0); + mtc_table_entry->trim_regs.emc_pmacro_quse_ddll_rank0_1 = EMC_CH0(EMC_PMACRO_QUSE_DDLL_RANK0_1); + mtc_table_entry->trim_regs.emc_pmacro_quse_ddll_rank0_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_QUSE_DDLL_RANK0_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_quse_ddll_rank0_3 = channel1_enabled ? EMC_CH1(EMC_PMACRO_QUSE_DDLL_RANK0_3) : 0; if (dram_dev_num == TWO_RANK) { - mtc_table_entry->trim_perch_regs.emc_quse_brlshft_2_idx = EMC_CH0(EMC_QUSE_BRLSHFT_2); - mtc_table_entry->trim_perch_regs.emc_quse_brlshft_3_idx = channel1_enabled ? EMC_CH1(EMC_QUSE_BRLSHFT_3) : 0; + mtc_table_entry->trim_perch_regs.emc_quse_brlshft_2 = EMC_CH0(EMC_QUSE_BRLSHFT_2); + mtc_table_entry->trim_perch_regs.emc_quse_brlshft_3 = channel1_enabled ? EMC_CH1(EMC_QUSE_BRLSHFT_3) : 0; - mtc_table_entry->trim_regs.emc_pmacro_quse_ddll_rank1_0_idx = EMC_CH0(EMC_PMACRO_QUSE_DDLL_RANK1_0); - mtc_table_entry->trim_regs.emc_pmacro_quse_ddll_rank1_1_idx = EMC_CH0(EMC_PMACRO_QUSE_DDLL_RANK1_1); - mtc_table_entry->trim_regs.emc_pmacro_quse_ddll_rank1_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_QUSE_DDLL_RANK1_2) : 0; - mtc_table_entry->trim_regs.emc_pmacro_quse_ddll_rank1_3_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_QUSE_DDLL_RANK1_3) : 0; + mtc_table_entry->trim_regs.emc_pmacro_quse_ddll_rank1_0 = EMC_CH0(EMC_PMACRO_QUSE_DDLL_RANK1_0); + mtc_table_entry->trim_regs.emc_pmacro_quse_ddll_rank1_1 = EMC_CH0(EMC_PMACRO_QUSE_DDLL_RANK1_1); + mtc_table_entry->trim_regs.emc_pmacro_quse_ddll_rank1_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_QUSE_DDLL_RANK1_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_quse_ddll_rank1_3 = channel1_enabled ? EMC_CH1(EMC_PMACRO_QUSE_DDLL_RANK1_3) : 0; } } @@ -2291,84 +2305,84 @@ static void _save_train_results(emc_table_t *mtc_table_entry, u32 needs_training ib_vref_dqs_1 |= (emc1_opt_dqs_array[i] + ((emc1_training_opt_dqs_ib_vref_rank1_val >> (8 * i)) & 0xFF)) >> 1 << (8 * i); } - mtc_table_entry->trim_regs.emc_pmacro_ib_vref_dqs_0_idx = ib_vref_dqs_0; - mtc_table_entry->trim_regs.emc_pmacro_ib_vref_dqs_1_idx = ib_vref_dqs_1; + mtc_table_entry->trim_regs.emc_pmacro_ib_vref_dqs_0 = ib_vref_dqs_0; + mtc_table_entry->trim_regs.emc_pmacro_ib_vref_dqs_1 = ib_vref_dqs_1; } else { - mtc_table_entry->trim_regs.emc_pmacro_ib_vref_dqs_0_idx = EMC(EMC_PMACRO_IB_VREF_DQS_0); - mtc_table_entry->trim_regs.emc_pmacro_ib_vref_dqs_1_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_VREF_DQS_1) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_vref_dqs_0 = EMC(EMC_PMACRO_IB_VREF_DQS_0); + mtc_table_entry->trim_regs.emc_pmacro_ib_vref_dqs_1 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_VREF_DQS_1) : 0; } } if (needs_rd_training) { - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_long_dqs_rank0_0_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_long_dqs_rank0_1_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_long_dqs_rank0_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_long_dqs_rank0_3_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_long_dqs_rank0_0 = EMC_CH0(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_0); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_long_dqs_rank0_1 = EMC_CH0(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_1); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_long_dqs_rank0_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_long_dqs_rank0_3 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK0_3) : 0; if (dram_dev_num == TWO_RANK) { - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_long_dqs_rank1_0_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_long_dqs_rank1_1_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_long_dqs_rank1_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_long_dqs_rank1_3_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_long_dqs_rank1_0 = EMC_CH0(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_0); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_long_dqs_rank1_1 = EMC_CH0(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_1); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_long_dqs_rank1_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_long_dqs_rank1_3 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_LONG_DQS_RANK1_3) : 0; } if (needs_training_in_self_refresh) { - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte0_0_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte0_1_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte0_2_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte1_0_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte1_1_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte1_2_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte2_0_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte2_1_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte2_2_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte3_0_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte3_1_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte3_2_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte4_0_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte4_1_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte4_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte5_0_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte5_1_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte5_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte6_0_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte6_1_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte6_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte7_0_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte7_1_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte7_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte0_0 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_0); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte0_1 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_1); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte0_2 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE0_2); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte1_0 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_0); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte1_1 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_1); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte1_2 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE1_2); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte2_0 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_0); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte2_1 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_1); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte2_2 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE2_2); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte3_0 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_0); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte3_1 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_1); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte3_2 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE3_2); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte4_0 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_0) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte4_1 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_1) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte4_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE4_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte5_0 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_0) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte5_1 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_1) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte5_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE5_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte6_0 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_0) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte6_1 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_1) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte6_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE6_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte7_0 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_0) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte7_1 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_1) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank0_byte7_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK0_BYTE7_2) : 0; if (dram_dev_num == TWO_RANK) { - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte0_0_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte0_1_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte0_2_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte1_0_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte1_1_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte1_2_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte2_0_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte2_1_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte2_2_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte3_0_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte3_1_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte3_2_idx = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2); - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte4_0_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte4_1_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte4_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte5_0_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte5_1_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte5_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte6_0_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte6_1_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte6_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte7_0_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte7_1_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte7_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte0_0 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_0); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte0_1 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_1); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte0_2 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE0_2); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte1_0 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_0); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte1_1 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_1); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte1_2 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE1_2); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte2_0 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_0); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte2_1 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_1); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte2_2 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE2_2); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte3_0 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_0); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte3_1 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_1); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte3_2 = EMC_CH0(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE3_2); + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte4_0 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_0) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte4_1 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_1) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte4_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE4_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte5_0 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_0) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte5_1 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_1) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte5_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE5_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte6_0 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_0) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte6_1 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_1) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte6_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE6_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte7_0 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_0) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte7_1 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_1) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ib_ddll_short_dq_rank1_byte7_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_IB_DDLL_SHORT_DQ_RANK1_BYTE7_2) : 0; } } @@ -2390,7 +2404,7 @@ static void _save_train_results(emc_table_t *mtc_table_entry, u32 needs_training if (mtc_table_entry->save_restore_mod_regs[3] & 0x80000000) ib_vref_dq_byte3_icr = ((EMC(EMC_PMACRO_IB_VREF_DQ_0) >> 24) & 0x7F) - (mtc_table_entry->save_restore_mod_regs[3] & 0x7F); - mtc_table_entry->trim_regs.emc_pmacro_ib_vref_dq_0_idx = + mtc_table_entry->trim_regs.emc_pmacro_ib_vref_dq_0 = ((ib_vref_dq_byte0_icr & 0x7F) | (ib_vref_dq_byte1_icr & 0x7F) << 8) | ((ib_vref_dq_byte2_icr & 0x7F) << 16) @@ -2412,7 +2426,7 @@ static void _save_train_results(emc_table_t *mtc_table_entry, u32 needs_training if (mtc_table_entry->save_restore_mod_regs[7] & 0x80000000) ib_vref_dq_byte7_icr = ((EMC(EMC_PMACRO_IB_VREF_DQ_1) >> 24) & 0x7F) - (mtc_table_entry->save_restore_mod_regs[7] & 0x7F); - mtc_table_entry->trim_regs.emc_pmacro_ib_vref_dq_1_idx = + mtc_table_entry->trim_regs.emc_pmacro_ib_vref_dq_1 = ((ib_vref_dq_byte4_icr & 0x7F) | (ib_vref_dq_byte5_icr & 0x7F) << 8) | ((ib_vref_dq_byte6_icr & 0x7F) << 16) @@ -2422,81 +2436,81 @@ static void _save_train_results(emc_table_t *mtc_table_entry, u32 needs_training if (needs_wr_training) { - mtc_table_entry->trim_perch_regs.emc0_data_brlshft_0_idx = EMC_CH0(EMC_DATA_BRLSHFT_0); - mtc_table_entry->trim_perch_regs.emc1_data_brlshft_0_idx = channel1_enabled ? EMC_CH1(EMC_DATA_BRLSHFT_0) : 0; + mtc_table_entry->trim_perch_regs.emc0_data_brlshft_0 = EMC_CH0(EMC_DATA_BRLSHFT_0); + mtc_table_entry->trim_perch_regs.emc1_data_brlshft_0 = channel1_enabled ? EMC_CH1(EMC_DATA_BRLSHFT_0) : 0; if (dram_dev_num == TWO_RANK) { - mtc_table_entry->trim_perch_regs.emc0_data_brlshft_1_idx = EMC_CH0(EMC_DATA_BRLSHFT_1); - mtc_table_entry->trim_perch_regs.emc1_data_brlshft_1_idx = channel1_enabled ? EMC_CH1(EMC_DATA_BRLSHFT_1) : 0; + mtc_table_entry->trim_perch_regs.emc0_data_brlshft_1 = EMC_CH0(EMC_DATA_BRLSHFT_1); + mtc_table_entry->trim_perch_regs.emc1_data_brlshft_1 = channel1_enabled ? EMC_CH1(EMC_DATA_BRLSHFT_1) : 0; } - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_0_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_1_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_3_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_0 = EMC_CH0(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_0); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_1 = EMC_CH0(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_1); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank0_3 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK0_3) : 0; if (dram_dev_num == TWO_RANK) { - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_0_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_1_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_3_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_0 = EMC_CH0(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_0); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_1 = EMC_CH0(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_1); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_long_dq_rank1_3 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_LONG_DQ_RANK1_3) : 0; } if (needs_training_in_self_refresh) { - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte0_0_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte0_1_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte0_2_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte1_0_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte1_1_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte1_2_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte2_0_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte2_1_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte2_2_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte3_0_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte3_1_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte3_2_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte4_0_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte4_1_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte4_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte5_0_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte5_1_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte5_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte6_0_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte6_1_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte6_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte7_0_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte7_1_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte7_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte0_0 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_0); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte0_1 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_1); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte0_2 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE0_2); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte1_0 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_0); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte1_1 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_1); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte1_2 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE1_2); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte2_0 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_0); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte2_1 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_1); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte2_2 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE2_2); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte3_0 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_0); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte3_1 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_1); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte3_2 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE3_2); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte4_0 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_0) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte4_1 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_1) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte4_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE4_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte5_0 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_0) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte5_1 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_1) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte5_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE5_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte6_0 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_0) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte6_1 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_1) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte6_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE6_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte7_0 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_0) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte7_1 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_1) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank0_byte7_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK0_BYTE7_2) : 0; if (dram_dev_num == TWO_RANK) { - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte0_0_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte0_1_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte0_2_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte1_0_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte1_1_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte1_2_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte2_0_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte2_1_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte2_2_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte3_0_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte3_1_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte3_2_idx = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2); - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte4_0_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte4_1_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte4_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte5_0_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte5_1_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte5_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte6_0_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte6_1_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte6_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte7_0_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte7_1_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1) : 0; - mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte7_2_idx = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte0_0 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_0); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte0_1 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_1); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte0_2 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE0_2); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte1_0 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_0); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte1_1 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_1); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte1_2 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE1_2); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte2_0 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_0); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte2_1 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_1); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte2_2 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE2_2); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte3_0 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_0); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte3_1 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_1); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte3_2 = EMC_CH0(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE3_2); + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte4_0 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_0) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte4_1 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_1) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte4_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE4_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte5_0 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_0) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte5_1 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_1) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte5_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE5_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte6_0 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_0) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte6_1 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_1) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte6_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE6_2) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte7_0 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_0) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte7_1 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_1) : 0; + mtc_table_entry->trim_regs.emc_pmacro_ob_ddll_short_dq_rank1_byte7_2 = channel1_enabled ? EMC_CH1(EMC_PMACRO_OB_DDLL_SHORT_DQ_RANK1_BYTE7_2) : 0; } } @@ -2541,10 +2555,10 @@ static void _save_train_results(emc_table_t *mtc_table_entry, u32 needs_training if (dram_dev_num == TWO_RANK) mr13_dev_ext_cnt_sp_addr = 0x480E0000; - mtc_table_entry->burst_reg_per_ch.emc1_mrw12_idx = (u8)emc0_ib_vref_dq_byte10_modded_plus | 0x880E0000 | (emc0_ib_vref_dq_byte11_modded_plus << 8); - mtc_table_entry->burst_reg_per_ch.emc0_mrw12_idx = emc0_ib_vref_dq_byte8_modded_plus | 0x880E0000 | (emc0_mrw12_op_sp1 << 8); - mtc_table_entry->burst_reg_per_ch.emc0_mrw13_idx = emc0_ib_vref_dq_byte9_modded_a_plus << 8 | emc0_mrw13_op_sp0 | mr13_dev_ext_cnt_sp_addr; - mtc_table_entry->burst_reg_per_ch.emc1_mrw13_idx = (emc1_mrw13_op_sp1 << 8) | emc1_mrw13_op_sp0 | mr13_dev_ext_cnt_sp_addr; + mtc_table_entry->burst_reg_per_ch.emc1_mrw12 = (u8)emc0_ib_vref_dq_byte10_modded_plus | 0x880E0000 | (emc0_ib_vref_dq_byte11_modded_plus << 8); + mtc_table_entry->burst_reg_per_ch.emc0_mrw12 = emc0_ib_vref_dq_byte8_modded_plus | 0x880E0000 | (emc0_mrw12_op_sp1 << 8); + mtc_table_entry->burst_reg_per_ch.emc0_mrw13 = emc0_ib_vref_dq_byte9_modded_a_plus << 8 | emc0_mrw13_op_sp0 | mr13_dev_ext_cnt_sp_addr; + mtc_table_entry->burst_reg_per_ch.emc1_mrw13 = (emc1_mrw13_op_sp1 << 8) | emc1_mrw13_op_sp0 | mr13_dev_ext_cnt_sp_addr; } } } @@ -2561,47 +2575,51 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e u32 ramp_up_wait; u32 ramp_down_wait; u32 bg_regulator_mode_change; - u32 mr13_flip_fspop = 0; - u32 mr13_flip_fspwr = 0; + u32 mr13_flip_fspop; + u32 mr13_flip_fspwr; u32 mr13_catr_enable; - /* needs_training LOBYTE table var */ + /* needs_training flags */ /* - | bit | Description | - |-----|----------------------------| - | 0 | Needs CA training | - | 1 | Needs CA_VREF training | - | 2 | Needs QUSE training | - | 3 | Needs QUSE_VREF training | - | 4 | Needs WR training | - | 5 | Needs WR_VREF training | - | 6 | Needs RD training | - | 7 | Needs RD_VREF training | + | bit | Description | + |-----|----------------------------------| + | 0 | Needs CA training | + | 1 | Needs CA_VREF training | + | 2 | Needs QUSE training | + | 3 | Needs QUSE_VREF training | + | 4 | Needs WR training | + | 5 | Needs WR_VREF training | + | 6 | Needs RD training | + | 7 | Needs RD_VREF training | + | 8 | Needs SWAP_RANK training | + | 9 | Needs IN_SELF_REFRESH training | */ bool compensate_trimmer_applicable = false; - bool needs_ca_or_cavref_training = (needs_training & 3) != 0; - bool needs_tristate_training = (needs_training & 0xF7) != 0; - bool needs_ca_training = needs_training & 1; - bool needs_ca_vref_training = (needs_training >> 1) & 1; - bool needs_quse_training = (needs_training >> 2) & 1; - bool needs_quse_vref_training = (needs_training >> 3) & 1; - bool needs_wr_training = (needs_training >> 4) & 1; - bool needs_wr_vref_training = (needs_training >> 5) & 1; - bool needs_rd_training = (needs_training >> 6) & 1; - bool needs_rd_vref_training = (needs_training >> 7) & 1; - bool needs_swap_rank_training = (needs_training >> 8) & 1; + bool needs_ca_combo_training = !!(needs_training & NEEDS_TRAINING_CA_COMBO); + bool needs_tristate_training = !!(needs_training & NEEDS_TRISTATE_TRAINING); - bool zcal_resistor_shared = (src_emc_entry->burst_regs.emc_zcal_wait_cnt_idx >> 31) & 1; - bool enable_bg_regulator = (dst_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0_idx & 1) ^ 1; - bool channel1_enabled = (src_emc_entry->burst_regs.emc_fbio_cfg7_idx >> 2) & 1; + bool needs_ca_training = !!(needs_training & NEEDS_TRAINING_CA); + bool needs_ca_vref_training = !!(needs_training & NEEDS_TRAINING_CA_VREF); + bool needs_quse_training = !!(needs_training & NEEDS_TRAINING_QUSE); + bool needs_quse_vref_training = !!(needs_training & NEEDS_TRAINING_QUSE_VREF); + bool needs_wr_training = !!(needs_training & NEEDS_TRAINING_WR); + bool needs_wr_vref_training = !!(needs_training & NEEDS_TRAINING_WR_VREF); + bool needs_rd_training = !!(needs_training & NEEDS_TRAINING_RD); + bool needs_rd_vref_training = !!(needs_training & NEEDS_TRAINING_RD_VREF); + bool needs_swap_rank_training = !!(needs_training & NEEDS_TRAINING_SWAP_RANK); + + bool zcal_resistor_shared = (src_emc_entry->burst_regs.emc_zcal_wait_cnt >> 31) & 1; + bool enable_bg_regulator = (dst_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0 & 1) ^ 1; + bool channel1_enabled = (src_emc_entry->burst_regs.emc_fbio_cfg7 >> 2) & 1; u32 dram_type = EMC(EMC_FBIO_CFG5) & 3; u32 dram_dev_num = (MC(MC_EMEM_ADR_CFG) & 1) + 1; u32 src_clock_period = 1000000000 / src_emc_entry->rate_khz; // In picoseconds. u32 dst_clock_period = 1000000000 / dst_emc_entry->rate_khz; // In picoseconds. - fsp_for_src_freq = !fsp_for_src_freq; + // Get current FSP op/write value. + bool enable_fsp_opwr = !(EMC(EMC_MRW3) & 0xC0); if (dram_type != DRAM_TYPE_LPDDR4) { @@ -2622,7 +2640,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e EPRINTF("Step 1"); emc_dbg_o = EMC(EMC_DBG); emc_pin_o = EMC(EMC_PIN); - emc_cfg = dst_emc_entry->burst_regs.emc_cfg_idx & 0xFFFFFFF; + emc_cfg = dst_emc_entry->burst_regs.emc_cfg & 0xFFFFFFF; emc_sel_dpd_ctrl = dst_emc_entry->emc_sel_dpd_ctrl & 0xFFFFFEC3; emc_cfg_pipe_clk_o = EMC(EMC_CFG_PIPE_CLK); _digital_dll_disable(); @@ -2681,27 +2699,27 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e EMC(EMC_CFG_PIPE_CLK) = emc_cfg_pipe_clk_o | 1; // CLK_ALWAYS_ON. EMC(EMC_FDPD_CTRL_CMD_NO_RAMP) = dst_emc_entry->emc_fdpd_ctrl_cmd_no_ramp & 0xFFFFFFFE; - bg_regulator_mode_change = src_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0_idx ^ dst_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0_idx; + bg_regulator_mode_change = src_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0 ^ dst_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0; bg_regulator_mode_change = (bg_regulator_mode_change | (bg_regulator_mode_change >> 2)) & 1; if (bg_regulator_mode_change) { EMC(EMC_DBG) = emc_dbg_o | 2; if (enable_bg_regulator) - EMC(EMC_PMACRO_BG_BIAS_CTRL_0) = src_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0_idx & 0xFFFFFFFE; + EMC(EMC_PMACRO_BG_BIAS_CTRL_0) = src_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0 & 0xFFFFFFFE; else - EMC(EMC_PMACRO_BG_BIAS_CTRL_0) = src_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0_idx & 0xFFFFFFFB; + EMC(EMC_PMACRO_BG_BIAS_CTRL_0) = src_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0 & 0xFFFFFFFB; } // Check if we need to turn on VREF generator. - if ((!(src_emc_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl_idx & 0x100) - && (dst_emc_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl_idx & 0x100)) - || (!(src_emc_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl_idx & 1) - && (dst_emc_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl_idx & 1))) + if ((!(src_emc_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl & 0x100) + && (dst_emc_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl & 0x100)) + || (!(src_emc_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl & 1) + && (dst_emc_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl & 1))) { EMC(EMC_PMACRO_DATA_PAD_TX_CTRL) = - (((dst_emc_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl_idx & 1) | (src_emc_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl_idx & 0xFFFFFFFE)) & 0xFFFFFEFF) - | (((dst_emc_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl_idx >> 8) & 0x1) << 8); + (((dst_emc_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl & 1) | (src_emc_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl & 0xFFFFFFFE)) & 0xFFFFFEFF) + | (((dst_emc_entry->burst_regs.emc_pmacro_data_pad_tx_ctrl >> 8) & 0x1) << 8); } _usleep(1); @@ -2710,7 +2728,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e // Step 2 - Prelock the DLL. EPRINTF("Step 2"); - if (dst_emc_entry->burst_regs.emc_cfg_dig_dll_idx & 1) + if (dst_emc_entry->burst_regs.emc_cfg_dig_dll & 1) _digital_dll_prelock(dst_emc_entry, needs_tristate_training, selected_clk_src_emc); // Prelock enabled for target frequency. else { @@ -2748,7 +2766,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e // Step 7 - Bug 200024907 - Patch RP R2P. EPRINTF("Step 7"); - if (needs_ca_or_cavref_training && dram_dev_num == TWO_RANK) + if (needs_ca_combo_training && dram_dev_num == TWO_RANK) EMC(EMC_PIN) = 0x107; u32 R2P_war = 0; @@ -2777,33 +2795,33 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e u32 tRTM = src_emc_entry->dram_timings.rl + div_o3(3600, src_clock_period) + deltaTWATM + tRPST + nRTP + 1; - if (tRTM <= src_emc_entry->burst_regs.emc_rp_idx + src_emc_entry->burst_regs.emc_r2p_idx) + if (tRTM <= src_emc_entry->burst_regs.emc_rp + src_emc_entry->burst_regs.emc_r2p) { - TRPab_war = src_emc_entry->burst_regs.emc_trpab_idx; - R2P_war = src_emc_entry->burst_regs.emc_r2p_idx; - RP_war = src_emc_entry->burst_regs.emc_rp_idx; + TRPab_war = src_emc_entry->burst_regs.emc_trpab; + R2P_war = src_emc_entry->burst_regs.emc_r2p; + RP_war = src_emc_entry->burst_regs.emc_rp; } else { - R2P_war = tRTM - src_emc_entry->burst_regs.emc_rp_idx; - TRPab_war = src_emc_entry->burst_regs.emc_trpab_idx; - RP_war = src_emc_entry->burst_regs.emc_rp_idx; + R2P_war = tRTM - src_emc_entry->burst_regs.emc_rp; + TRPab_war = src_emc_entry->burst_regs.emc_trpab; + RP_war = src_emc_entry->burst_regs.emc_rp; if (R2P_war > 63) { RP_war = tRTM - 63; R2P_war = 63; - if (src_emc_entry->burst_regs.emc_trpab_idx < tRTM - 63) + if (src_emc_entry->burst_regs.emc_trpab < tRTM - 63) TRPab_war = tRTM - 63; else - TRPab_war = src_emc_entry->burst_regs.emc_trpab_idx; + TRPab_war = src_emc_entry->burst_regs.emc_trpab; } } if (RP_war >= deltaTWATM) - W2P_war = src_emc_entry->burst_regs.emc_w2p_idx; + W2P_war = src_emc_entry->burst_regs.emc_w2p; else { - u32 W2P_war_temp = deltaTWATM + src_emc_entry->burst_regs.emc_w2p_idx; + u32 W2P_war_temp = deltaTWATM + src_emc_entry->burst_regs.emc_w2p; W2P_war = W2P_war_temp - RP_war; if (W2P_war > 63) { @@ -2814,10 +2832,10 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e } } - if ( src_emc_entry->burst_regs.emc_w2p_idx != W2P_war - || src_emc_entry->burst_regs.emc_rp_idx != RP_war - || src_emc_entry->burst_regs.emc_r2p_idx != R2P_war - || src_emc_entry->burst_regs.emc_trpab_idx != TRPab_war) + if ( src_emc_entry->burst_regs.emc_w2p != W2P_war + || src_emc_entry->burst_regs.emc_rp != RP_war + || src_emc_entry->burst_regs.emc_r2p != R2P_war + || src_emc_entry->burst_regs.emc_trpab != TRPab_war) { EMC(EMC_DBG) = emc_dbg_o | 2; EMC(EMC_RP) = RP_war; @@ -2831,7 +2849,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e // Step 7.2 - Program FSP reference registers and send MRWs to new FSPWR. EPRINTF("Step 7.2"); - if (fsp_for_src_freq) + if (enable_fsp_opwr) { mr13_flip_fspop = dst_emc_entry->emc_mrw3 | 0xC0; mr13_flip_fspwr = (dst_emc_entry->emc_mrw3 & 0xFFFFFF3F) | 0x40; @@ -2849,7 +2867,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e else mr13_catr_enable = (mr13_flip_fspwr & 0x3FFFFFFF) | 0x80000001; - if (needs_ca_or_cavref_training) + if (needs_ca_combo_training) { if (needs_swap_rank_training) mr13_flip_fspop = (mr13_flip_fspop & 0x3FFFFFFF) | 0x80000000; @@ -2878,11 +2896,11 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e reg_addr = burst_regs_emc_addr_table[i]; if (needs_tristate_training) { - if (needs_ca_or_cavref_training) + if (needs_ca_combo_training) reg_val = dst_burst_regs->shadow_regs_ca_train[i]; - else if (needs_training & 0xC) + else if (needs_training & NEEDS_TRAINING_QUSE_COMBO) reg_val = dst_burst_regs->shadow_regs_quse_train[i]; - else if (needs_training & 0xF0) + else if (needs_training & (NEEDS_TRAINING_WR_COMBO | NEEDS_TRAINING_RD_COMBO)) reg_val = dst_burst_regs->shadow_regs_rdwr_train[i]; else continue; @@ -3058,19 +3076,19 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e // Step 9 - LPDDR4. EPRINTF("Step 9"); - EMC(EMC_ZCAL_INTERVAL) = src_emc_entry->burst_regs.emc_zcal_interval_idx & 0xFF000000; - EMC(EMC_ZCAL_WAIT_CNT) = dst_emc_entry->burst_regs.emc_zcal_wait_cnt_idx & 0xFFFFF800; + EMC(EMC_ZCAL_INTERVAL) = src_emc_entry->burst_regs.emc_zcal_interval & 0xFF000000; + EMC(EMC_ZCAL_WAIT_CNT) = dst_emc_entry->burst_regs.emc_zcal_wait_cnt & 0xFFFFF800; EMC(EMC_DBG) = emc_dbg_o | 0x40000002; - EMC(EMC_ZCAL_INTERVAL) = src_emc_entry->burst_regs.emc_zcal_interval_idx & 0xFF000000; + EMC(EMC_ZCAL_INTERVAL) = src_emc_entry->burst_regs.emc_zcal_interval & 0xFF000000; EMC(EMC_DBG) = emc_dbg_o; if (needs_tristate_training) { EMC(EMC_DBG) = emc_dbg_o | 2; - EMC(EMC_PMACRO_AUTOCAL_CFG_COMMON) = dst_emc_entry->burst_regs.emc_pmacro_autocal_cfg_common_idx | 0x10000; + EMC(EMC_PMACRO_AUTOCAL_CFG_COMMON) = dst_emc_entry->burst_regs.emc_pmacro_autocal_cfg_common | 0x10000; - if (needs_ca_or_cavref_training) - EMC(EMC_FBIO_CFG5) = src_emc_entry->burst_regs.emc_fbio_cfg5_idx | 0x8000000; + if (needs_ca_combo_training) + EMC(EMC_FBIO_CFG5) = src_emc_entry->burst_regs.emc_fbio_cfg5 | 0x8000000; EMC(EMC_DBG) = emc_dbg_o; @@ -3084,15 +3102,15 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e EPRINTF("Step 10"); _ccfifo_write(EMC_SELF_REF, 0x101, 0); - if (!needs_ca_or_cavref_training && (dst_clock_period <= 2000)) + if (!needs_ca_combo_training && (dst_clock_period <= 2000)) { _ccfifo_write(EMC_MRW3, mr13_flip_fspwr ^ 0x40, 0); - _ccfifo_write(EMC_MRW6, (src_emc_entry->burst_regs.emc_mrw6_idx & 0xC0C0) | (dst_emc_entry->burst_regs.emc_mrw6_idx & 0xFFFF3F3F), 0); - _ccfifo_write(EMC_MRW14, (src_emc_entry->burst_regs.emc_mrw14_idx & 0x3838) | (dst_emc_entry->burst_regs.emc_mrw14_idx & 0xFFFF0707), 0); + _ccfifo_write(EMC_MRW6, (src_emc_entry->burst_regs.emc_mrw6 & 0xC0C0) | (dst_emc_entry->burst_regs.emc_mrw6 & 0xFFFF3F3F), 0); + _ccfifo_write(EMC_MRW14, (src_emc_entry->burst_regs.emc_mrw14 & 0x3838) | (dst_emc_entry->burst_regs.emc_mrw14 & 0xFFFF0707), 0); if (dram_dev_num == TWO_RANK) { - _ccfifo_write(EMC_MRW7, (src_emc_entry->burst_regs.emc_mrw7_idx & 0xC0C0) | (dst_emc_entry->burst_regs.emc_mrw7_idx & 0xFFFF3F3F), 0); - _ccfifo_write(EMC_MRW15, (src_emc_entry->burst_regs.emc_mrw15_idx & 0x3838) | (dst_emc_entry->burst_regs.emc_mrw15_idx & 0xFFFF0707), 0); + _ccfifo_write(EMC_MRW7, (src_emc_entry->burst_regs.emc_mrw7 & 0xC0C0) | (dst_emc_entry->burst_regs.emc_mrw7 & 0xFFFF3F3F), 0); + _ccfifo_write(EMC_MRW15, (src_emc_entry->burst_regs.emc_mrw15 & 0x3838) | (dst_emc_entry->burst_regs.emc_mrw15 & 0xFFFF0707), 0); } if (dram_dev_num == ONE_RANK || zcal_resistor_shared) @@ -3114,9 +3132,9 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e _ccfifo_write(EMC_DBG, emc_dbg_val, 0); } - if (needs_ca_or_cavref_training) + if (needs_ca_combo_training) { - _ccfifo_write(EMC_PMACRO_DATA_RX_TERM_MODE, src_emc_entry->burst_regs.emc_pmacro_data_rx_term_mode_idx & 0xFFFFFCCC, 0); + _ccfifo_write(EMC_PMACRO_DATA_RX_TERM_MODE, src_emc_entry->burst_regs.emc_pmacro_data_rx_term_mode & 0xFFFFFCCC, 0); if (dram_dev_num == TWO_RANK && needs_swap_rank_training) { @@ -3160,7 +3178,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e // Step 14 - Bringup CKE pins. EPRINTF("Step 14"); u32 emc_pin_val_final = 0; - if (needs_ca_or_cavref_training) + if (needs_ca_combo_training) { emc_pin_val_final = emc_pin_o & 0xFFFFFFF8; if (dram_dev_num == TWO_RANK) @@ -3180,7 +3198,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e // Step 15 - Zqlatch. EPRINTF("Step 15"); - if (!needs_ca_or_cavref_training) + if (!needs_ca_combo_training) { s32 zq_latch_dvfs_wait_time; u32 T_PDEX_timing = div_o3(dst_emc_entry->dram_timings.t_pdex * 1000, dst_clock_period); @@ -3270,7 +3288,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e if (needs_wr_training) training_command |= (1 << 3); // WR: Initiates WR Training. if (needs_wr_vref_training) - training_command |= (1 << 6); // WR_VREF: Initiates OB (wrire) DRAM_VREF Training. + training_command |= (1 << 6); // WR_VREF: Initiates OB (write) DRAM_VREF Training. if (needs_rd_training) training_command |= (1 << 2); // RD: Initiates RD Training. if (needs_rd_vref_training) @@ -3283,15 +3301,15 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e { if (enable_bg_regulator) _ccfifo_write(EMC_PMACRO_BG_BIAS_CTRL_0, - src_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0_idx & 0xFFFFFFFE, 0); + src_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0 & 0xFFFFFFFE, 0); else _ccfifo_write(EMC_PMACRO_BG_BIAS_CTRL_0, - src_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0_idx & 0xFFFFFFFB, 0); + src_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0 & 0xFFFFFFFB, 0); } _ccfifo_write(EMC_SWITCH_BACK_CTRL, 1, 0); - if (!needs_ca_or_cavref_training || needs_swap_rank_training) + if (!needs_ca_combo_training || needs_swap_rank_training) { _ccfifo_write(EMC_MRW3, mr13_flip_fspop ^ 0xC0, 0); _ccfifo_write(EMC_INTSTATUS, 0, 1000000 / dst_clock_period); @@ -3315,13 +3333,13 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e else _ccfifo_write(EMC_PIN, (emc_pin_o & 0xFFFFFFF8) | 1, 0); - if (needs_ca_or_cavref_training) + if (needs_ca_combo_training) { _ccfifo_write(EMC_TR_CTRL_0, 0x4A, 200000 / src_clock_period); _ccfifo_write(EMC_TR_CTRL_0, 0x40, 1000000 / src_clock_period); _ccfifo_write(EMC_MRW3, mr13_catr_enable & 0xFFFFFFFE, 0); _ccfifo_write(EMC_INTSTATUS, 0, 1000000 / src_clock_period); - _ccfifo_write(EMC_PMACRO_DATA_RX_TERM_MODE, src_emc_entry->burst_regs.emc_pmacro_data_rx_term_mode_idx, 0); + _ccfifo_write(EMC_PMACRO_DATA_RX_TERM_MODE, src_emc_entry->burst_regs.emc_pmacro_data_rx_term_mode, 0); } _ccfifo_write(EMC_DBG, emc_dbg_o, 0); @@ -3329,14 +3347,14 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e _ccfifo_write(EMC_ZQ_CAL, 0x80000001, 0); _ccfifo_write(EMC_ZQ_CAL, 0x80000002, 1000000 / src_clock_period); - if ((!needs_ca_or_cavref_training || needs_swap_rank_training) && dram_dev_num == TWO_RANK) + if ((!needs_ca_combo_training || needs_swap_rank_training) && dram_dev_num == TWO_RANK) { _ccfifo_write(EMC_ZQ_CAL, 0x40000001, 0); _ccfifo_write(EMC_ZQ_CAL, 0x40000002, 1000000 / src_clock_period); } - if (!needs_ca_or_cavref_training) + if (!needs_ca_combo_training) _ccfifo_write(EMC_MRW3, (mr13_flip_fspop & 0xF3FFFFF7) ^ 0xC0000C0, 0); _ccfifo_write(EMC_SELF_REF, 0, 0); // Was 0x100. @@ -3353,14 +3371,14 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e { bg_regulator_switch_complete_wait_clks = 1250000 / src_clock_period; _ccfifo_write(EMC_PMACRO_BG_BIAS_CTRL_0, - src_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0_idx, bg_regulator_switch_complete_wait_clks); + src_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0, bg_regulator_switch_complete_wait_clks); } else { if (ramp_up_wait <= 1250000) bg_regulator_switch_complete_wait_clks = (1250000 - ramp_up_wait) / dst_clock_period; _ccfifo_write(EMC_PMACRO_BG_BIAS_CTRL_0, - dst_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0_idx, bg_regulator_switch_complete_wait_clks); + dst_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0, bg_regulator_switch_complete_wait_clks); } _ccfifo_write(EMC_DBG, emc_dbg_o, 0); @@ -3376,9 +3394,9 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e _ccfifo_write(EMC_DBG, emc_dbg_o | 2, 0); if (needs_tristate_training) - _ccfifo_write(EMC_ZCAL_INTERVAL, src_emc_entry->burst_regs.emc_zcal_interval_idx, 0); + _ccfifo_write(EMC_ZCAL_INTERVAL, src_emc_entry->burst_regs.emc_zcal_interval, 0); - _ccfifo_write(EMC_CFG, dst_emc_entry->burst_regs.emc_cfg_idx & 0xEFFFFFFF, 0); + _ccfifo_write(EMC_CFG, dst_emc_entry->burst_regs.emc_cfg & 0xEFFFFFFF, 0); // Step 22 - Restore EMC_CFG_PIPE_CLK. EPRINTF("Step 22"); @@ -3392,9 +3410,9 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e if (bg_regulator_mode_change) { if (enable_bg_regulator) - EMC(EMC_PMACRO_BG_BIAS_CTRL_0) = dst_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0_idx & 0xFFFFFFFB; + EMC(EMC_PMACRO_BG_BIAS_CTRL_0) = dst_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0 & 0xFFFFFFFB; else - EMC(EMC_PMACRO_BG_BIAS_CTRL_0) = dst_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0_idx & 0xFFFFFFFE; + EMC(EMC_PMACRO_BG_BIAS_CTRL_0) = dst_emc_entry->burst_regs.emc_pmacro_bg_bias_ctrl_0 & 0xFFFFFFFE; } // Step 23 - Clock Change. @@ -3452,15 +3470,15 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e if (!in_self_refresh) { EMC(EMC_DBG) = emc_dbg_o | 2; - EMC(EMC_ZCAL_WAIT_CNT) = dst_emc_entry->burst_regs.emc_zcal_wait_cnt_idx; - EMC(EMC_ZCAL_INTERVAL) = dst_emc_entry->burst_regs.emc_zcal_interval_idx; + EMC(EMC_ZCAL_WAIT_CNT) = dst_emc_entry->burst_regs.emc_zcal_wait_cnt; + EMC(EMC_ZCAL_INTERVAL) = dst_emc_entry->burst_regs.emc_zcal_interval; EMC(EMC_DBG) = emc_dbg_o; } // Step 27 - Restore EMC_CFG, FDPD regs. EPRINTF("Step 27"); EMC(EMC_DBG) = emc_dbg_o | 2; - EMC(EMC_CFG) = dst_emc_entry->burst_regs.emc_cfg_idx; + EMC(EMC_CFG) = dst_emc_entry->burst_regs.emc_cfg; EMC(EMC_DBG) = emc_dbg_o; EMC(EMC_FDPD_CTRL_CMD_NO_RAMP) = dst_emc_entry->emc_fdpd_ctrl_cmd_no_ramp; EMC(EMC_SEL_DPD_CTRL) = dst_emc_entry->emc_sel_dpd_ctrl; @@ -3470,10 +3488,10 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e if (needs_tristate_training) { EMC(EMC_DBG) = emc_dbg_o | 2; - EMC(EMC_CFG) = dst_emc_entry->burst_regs.emc_cfg_idx; + EMC(EMC_CFG) = dst_emc_entry->burst_regs.emc_cfg; EMC(EMC_SEL_DPD_CTRL) = dst_emc_entry->emc_sel_dpd_ctrl; - EMC(EMC_ZCAL_WAIT_CNT) = src_emc_entry->burst_regs.emc_zcal_wait_cnt_idx; - EMC(EMC_ZCAL_INTERVAL) = src_emc_entry->burst_regs.emc_zcal_interval_idx; + EMC(EMC_ZCAL_WAIT_CNT) = src_emc_entry->burst_regs.emc_zcal_wait_cnt; + EMC(EMC_ZCAL_INTERVAL) = src_emc_entry->burst_regs.emc_zcal_interval; EMC(EMC_AUTO_CAL_CONFIG2) = src_emc_entry->emc_auto_cal_config2; EMC(EMC_AUTO_CAL_CONFIG3) = src_emc_entry->emc_auto_cal_config3; EMC(EMC_AUTO_CAL_CONFIG4) = src_emc_entry->emc_auto_cal_config4; @@ -3482,11 +3500,11 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e EMC(EMC_AUTO_CAL_CONFIG7) = src_emc_entry->emc_auto_cal_config7; EMC(EMC_AUTO_CAL_CONFIG8) = src_emc_entry->emc_auto_cal_config8; EMC(EMC_DBG) = emc_dbg_o; - EMC(EMC_TR_DVFS) = dst_emc_entry->burst_regs.emc_tr_dvfs_idx & 0xFFFFFFFE; + EMC(EMC_TR_DVFS) = dst_emc_entry->burst_regs.emc_tr_dvfs & 0xFFFFFFFE; } EMC(EMC_DBG) = emc_dbg_o | 2; - EMC(EMC_PMACRO_AUTOCAL_CFG_COMMON) = dst_emc_entry->burst_regs.emc_pmacro_autocal_cfg_common_idx; + EMC(EMC_PMACRO_AUTOCAL_CFG_COMMON) = dst_emc_entry->burst_regs.emc_pmacro_autocal_cfg_common; EMC(EMC_DBG) = emc_dbg_o; // Step 29 - Power fix WAR. @@ -3496,16 +3514,13 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e EMC(EMC_PMACRO_TRAINING_CTRL_1) = CH0_TRAINING_E_WRPTR; EMC(EMC_PMACRO_CFG_PM_GLOBAL_0) = 0; - // Step 30 - Re-enable autocal and Restore FSP to account for switch back (training). + // Step 30 - Re-enable autocal. EPRINTF("Step 30"); if (needs_tristate_training) - { EMC(EMC_AUTO_CAL_CONFIG) = src_emc_entry->emc_auto_cal_config; - fsp_for_src_freq = !fsp_for_src_freq; - } else { - if (dst_emc_entry->burst_regs.emc_cfg_dig_dll_idx & 1) + if (dst_emc_entry->burst_regs.emc_cfg_dig_dll & 1) _digital_dll_enable_rs(channel1_enabled); EMC(EMC_AUTO_CAL_CONFIG) = dst_emc_entry->emc_auto_cal_config; } @@ -3515,7 +3530,7 @@ static u32 _minerva_set_clock(emc_table_t *src_emc_entry, emc_table_t *dst_emc_e static void _minerva_train_patterns(emc_table_t *src_emc_entry, emc_table_t *dst_emc_entry, bool switch_rate, u32 selected_clk_src_emc) { - u32 needs_training_idx = 0; + u32 needs_training_num = 0; u32 emc_cfg_dig_dll_val = 0; u32 needs_training_emc_table[8] = {0}; @@ -3536,24 +3551,29 @@ static void _minerva_train_patterns(emc_table_t *src_emc_entry, emc_table_t *dst if (!dst_emc_entry->trained) { - if (needs_training & 3) + if (needs_training & NEEDS_TRAINING_CA_COMBO) { - needs_training_emc_table[needs_training_idx++] = needs_training & 0x203; + needs_training_emc_table[needs_training_num++] = + needs_training & (NEEDS_TRAINING_CA_COMBO | NEEDS_TRAINING_IN_SELF_REFRESH); if (MC(MC_EMEM_ADR_CFG) & 1) // if mapping W8 (1KB page). - needs_training_emc_table[needs_training_idx++] = needs_training & 0x303; + needs_training_emc_table[needs_training_num++] = + needs_training & (NEEDS_TRAINING_CA_COMBO | NEEDS_TRAINING_SWAP_RANK | NEEDS_TRAINING_IN_SELF_REFRESH); } - if (needs_training & 0xC) + if (needs_training & NEEDS_TRAINING_QUSE_COMBO) { - needs_training_emc_table[needs_training_idx++] = needs_training & 0x20C; + needs_training_emc_table[needs_training_num++] = + needs_training & (NEEDS_TRAINING_QUSE_COMBO | NEEDS_TRAINING_IN_SELF_REFRESH); if (MC(MC_EMEM_ADR_CFG) & 1) - needs_training_emc_table[needs_training_idx++] = needs_training & 0x204; + needs_training_emc_table[needs_training_num++] = + needs_training & (NEEDS_TRAINING_QUSE | NEEDS_TRAINING_IN_SELF_REFRESH); } - if (needs_training & 0xF0) - needs_training_emc_table[needs_training_idx++] = needs_training & 0x2F0; + if (needs_training & (NEEDS_TRAINING_WR_COMBO | NEEDS_TRAINING_RD_COMBO)) + needs_training_emc_table[needs_training_num++] = + needs_training & (NEEDS_TRAINING_WR_COMBO | NEEDS_TRAINING_RD_COMBO | NEEDS_TRAINING_IN_SELF_REFRESH); - for (u32 i = 0; needs_training_idx > i; i++) // Runs more than once for needs_training & 0xF + for (u32 i = 0; needs_training_num > i; i++) // Runs more than once for needs_training CA/QUSE/WR/RD. { _minerva_set_clock(src_emc_entry, dst_emc_entry, needs_training_emc_table[i], selected_clk_src_emc); @@ -3569,7 +3589,7 @@ static void _minerva_train_patterns(emc_table_t *src_emc_entry, emc_table_t *dst _timing_update(dual_channel); emc_cfg_dig_dll_val = EMC(EMC_CFG_DIG_DLL) & 0xFFFFFFFE; - if (dst_emc_entry->burst_regs.emc_cfg_dig_dll_idx == 1) + if (dst_emc_entry->burst_regs.emc_cfg_dig_dll == 1) emc_cfg_dig_dll_val = EMC(EMC_CFG_DIG_DLL) | 1; EMC(EMC_CFG_DIG_DLL) = (emc_cfg_dig_dll_val & 0xFFFFFF3F) | 0x80; _timing_update(dual_channel); @@ -3578,10 +3598,10 @@ static void _minerva_train_patterns(emc_table_t *src_emc_entry, emc_table_t *dst ; // Bug 200024907. - EMC(EMC_RP) = src_emc_entry->burst_regs.emc_rp_idx; - EMC(EMC_R2P) = src_emc_entry->burst_regs.emc_r2p_idx; - EMC(EMC_W2P) = src_emc_entry->burst_regs.emc_w2p_idx; - EMC(EMC_TRPAB) = src_emc_entry->burst_regs.emc_trpab_idx; + EMC(EMC_RP) = src_emc_entry->burst_regs.emc_rp; + EMC(EMC_R2P) = src_emc_entry->burst_regs.emc_r2p; + EMC(EMC_W2P) = src_emc_entry->burst_regs.emc_w2p; + EMC(EMC_TRPAB) = src_emc_entry->burst_regs.emc_trpab; _timing_update(dual_channel); } @@ -3602,14 +3622,14 @@ void _minerva_do_over_temp_compensation(mtc_config_t *mtc_cfg) if (dram_type != DRAM_TYPE_LPDDR4) return; - u32 dram_temp = _get_dram_temperature(); + s32 dram_temp = _get_dram_temperature(); - if (mtc_cfg->prev_temp == dram_temp || dram_temp < 0) + if (dram_temp < 0 || mtc_cfg->prev_temp == (u32)dram_temp) return; - u32 refr = mtc_cfg->current_emc_table->burst_regs.emc_refresh_idx; - u32 pre_refr = mtc_cfg->current_emc_table->burst_regs.emc_pre_refresh_req_cnt_idx; - u32 dyn_self_ref = mtc_cfg->current_emc_table->burst_regs.emc_dyn_self_ref_control_idx; + u32 refr = mtc_cfg->current_emc_table->burst_regs.emc_refresh; + u32 pre_refr = mtc_cfg->current_emc_table->burst_regs.emc_pre_refresh_req_cnt; + u32 dyn_self_ref = mtc_cfg->current_emc_table->burst_regs.emc_dyn_self_ref_control; switch (dram_temp) { @@ -3620,7 +3640,7 @@ void _minerva_do_over_temp_compensation(mtc_config_t *mtc_cfg) case 3: if (mtc_cfg->prev_temp < 4) { - mtc_cfg->prev_temp = dram_temp; + mtc_cfg->prev_temp = (u32)dram_temp; return; } break; @@ -3653,7 +3673,7 @@ u32 _minerva_do_periodic_compensation(emc_table_t *mtc_table_entry) { u32 dram_dev_num = (MC(MC_EMEM_ADR_CFG) & 1) + 1; u32 pd_mask = (dram_dev_num == TWO_RANK) ? IN_POWERDOWN_BOTH_MASK : IN_POWERDOWN_1DEV_MASK; - bool channel1_enabled = (mtc_table_entry->burst_regs.emc_fbio_cfg7_idx >> 2) & 1; + bool channel1_enabled = (mtc_table_entry->burst_regs.emc_fbio_cfg7 >> 2) & 1; (void)EMC(EMC_DBG); @@ -3726,8 +3746,9 @@ static u32 _minerva_set_rate(mtc_config_t *mtc_cfg) u32 src_emc_entry_idx = 999; u32 dst_emc_entry_idx = 999; u32 selected_clk_src_emc; - u32 selected_emc_2x_clk_src; + u32 emc_clk_src; bool freq_changed = false; + bool src_is_pllmb; emc_table_t *src_emc_entry; emc_table_t *dst_emc_entry; @@ -3760,32 +3781,34 @@ static u32 _minerva_set_rate(mtc_config_t *mtc_cfg) freq_changed = _check_freq_changed(dst_rate_khz, dst_clk_src_emc, src_rate_khz, src_clk_src_emc); EPRINTFARGS("Requested freq change from %d to %d.", src_rate_khz, dst_rate_khz); + // Get current clock source. + emc_clk_src = CLOCK(CLK_RST_CONTROLLER_CLK_SOURCE_EMC) >> EMC_2X_CLK_SRC_SHIFT; + src_is_pllmb = emc_clk_src == PLLMB_UD || emc_clk_src == PLLMB_OUT0; + if (freq_changed) { - selected_emc_2x_clk_src = src_clk_src_emc >> EMC_2X_CLK_SRC_SHIFT; - if (selected_emc_2x_clk_src & 3) + if (emc_clk_src == PLLM_UD || + emc_clk_src == PLLM_OUT0) // Clock source is PLLM. Switch based on src_is_pllmb. { - if (selected_emc_2x_clk_src - PLLMB_UD <= 1) - emc_2X_clk_src_is_pllmb = 0; + src_is_pllmb = !src_is_pllmb; } - else + else if (emc_clk_src == PLLMB_UD || + emc_clk_src == PLLMB_OUT0) // Clock source is PLLMB. Switch to PLLM. { - emc_2X_clk_src_is_pllmb = !emc_2X_clk_src_is_pllmb; + src_is_pllmb = false; } - selected_clk_src_emc = _pllm_clk_base_cfg(dst_rate_khz, dst_clk_src_emc, emc_2X_clk_src_is_pllmb); + selected_clk_src_emc = _pllm_clk_base_cfg(dst_rate_khz, dst_clk_src_emc, src_is_pllmb); } else { selected_clk_src_emc = dst_clk_src_emc; - selected_emc_2x_clk_src = selected_clk_src_emc >> EMC_2X_CLK_SRC_SHIFT; - if (selected_emc_2x_clk_src != PLLMB_OUT0 && selected_emc_2x_clk_src) + emc_clk_src = selected_clk_src_emc >> EMC_2X_CLK_SRC_SHIFT; + if (src_is_pllmb) { - if (selected_emc_2x_clk_src - PLLM_UD <= PLLC_OUT0 && emc_2X_clk_src_is_pllmb) + if (emc_clk_src == PLLM_UD || emc_clk_src == PLLMB_UD) selected_clk_src_emc = (selected_clk_src_emc & 0x1FFFFFFF) | (PLLMB_UD << EMC_2X_CLK_SRC_SHIFT); - } - else if (emc_2X_clk_src_is_pllmb) - { - selected_clk_src_emc = (selected_clk_src_emc & 0x1FFFFFFF) | (PLLMB_OUT0 << EMC_2X_CLK_SRC_SHIFT); + else if (emc_clk_src == PLLM_OUT0 || emc_clk_src == PLLMB_OUT0) + selected_clk_src_emc = (selected_clk_src_emc & 0x1FFFFFFF) | (PLLMB_OUT0 << EMC_2X_CLK_SRC_SHIFT); } } @@ -3800,8 +3823,6 @@ static u32 _minerva_set_rate(mtc_config_t *mtc_cfg) return 0; case OP_TRAIN: _minerva_train_patterns(src_emc_entry, dst_emc_entry, false, selected_clk_src_emc); - if (freq_changed) - emc_2X_clk_src_is_pllmb = !emc_2X_clk_src_is_pllmb; return 0; case OP_TRAIN_SWITCH: _minerva_train_patterns(src_emc_entry, dst_emc_entry, true, selected_clk_src_emc); @@ -3817,6 +3838,8 @@ static u32 _minerva_set_rate(mtc_config_t *mtc_cfg) static void _minerva_get_table(mtc_config_t *mtc_cfg) { + memset(mtc_cfg->mtc_table, 0, EMC_TABLE_ENTRY_SIZE_R7 * 10); + switch (mtc_cfg->sdram_id) { case DRAM_4GB_HYNIX_H9HCNNNBPUMLHR_NLN: @@ -3826,12 +3849,48 @@ static void _minerva_get_table(mtc_config_t *mtc_cfg) case DRAM_4GB_MICRON_MT53B512M32D2NP_062_WT: case DRAM_4GB_COPPER_SAMSUNG: case DRAM_6GB_SAMSUNG_K4FHE3D4HM_MFCH: + case DRAM_8GB_SAMSUNG_K4FBE3D4HM_MGXX: default: memcpy(mtc_cfg->mtc_table, nx_abca2_0_3_10NoCfgVersion_V9_8_7_V1_6, EMC_TABLE_SIZE_R7); + if (mtc_cfg->sdram_id == DRAM_8GB_SAMSUNG_K4FBE3D4HM_MGXX) + { + for (u32 i = 0; i < EMC_TABLE_SIZE_R7 / EMC_TABLE_ENTRY_SIZE_R7; i++) + { + emc_table_t *table = &mtc_cfg->mtc_table[i]; + u32 period = 1000000000 / table->rate_khz; + + table->burst_regs.emc_rfc = 280000 / period; + table->shadow_regs_ca_train.emc_rfc = 280000 / period; + table->shadow_regs_quse_train.emc_rfc = 280000 / period; + table->shadow_regs_rdwr_train.emc_rfc = 280000 / period; + + table->burst_regs.emc_rfcpb = 140000 / period; + table->shadow_regs_ca_train.emc_rfcpb = 140000 / period; + table->shadow_regs_quse_train.emc_rfcpb = 140000 / period; + table->shadow_regs_rdwr_train.emc_rfcpb = 140000 / period; + + table->burst_regs.emc_txsr = 287500 / period; + table->shadow_regs_ca_train.emc_txsr = 287500 / period; + table->shadow_regs_quse_train.emc_txsr = 287500 / period; + table->shadow_regs_rdwr_train.emc_txsr = 287500 / period; + + table->burst_regs.emc_txsrdll = table->burst_regs.emc_txsr; + table->shadow_regs_ca_train.emc_txsrdll = table->shadow_regs_ca_train.emc_txsr; + table->shadow_regs_quse_train.emc_txsrdll = table->shadow_regs_quse_train.emc_txsr; + table->shadow_regs_rdwr_train.emc_txsrdll = table->shadow_regs_rdwr_train.emc_txsr; + + table->burst_regs.emc_dyn_self_ref_control &= 0x7FFFFFFF; + table->shadow_regs_ca_train.emc_dyn_self_ref_control &= 0x7FFFFFFF; + table->shadow_regs_quse_train.emc_dyn_self_ref_control &= 0x7FFFFFFF; + table->shadow_regs_rdwr_train.emc_dyn_self_ref_control &= 0x7FFFFFFF; + + table->dram_timings.t_rfc = 280; + } + } break; } - mtc_cfg->table_entries = 10; + mtc_cfg->table_entries = EMC_TABLE_SIZE_R7 / EMC_TABLE_ENTRY_SIZE_R7; mtc_cfg->rate_to = 0; mtc_cfg->rate_from = 0; mtc_cfg->train_mode = 0; @@ -3839,8 +3898,6 @@ static void _minerva_get_table(mtc_config_t *mtc_cfg) mtc_cfg->current_emc_table = NULL; // Important! - mtc_cfg->emc_2X_clk_src_is_pllmb = false; - mtc_cfg->fsp_for_src_freq = false; mtc_cfg->train_ram_patterns = true; mtc_cfg->init_done = MTC_INIT_MAGIC; } @@ -3850,8 +3907,6 @@ void _minerva_init(mtc_config_t *mtc_cfg, bdkParams_t bp) EPRINTF("-- Minerva Training Cell --"); train_ram_patterns = mtc_cfg->train_ram_patterns; - fsp_for_src_freq = mtc_cfg->fsp_for_src_freq; - emc_2X_clk_src_is_pllmb = mtc_cfg->emc_2X_clk_src_is_pllmb; if (mtc_cfg->init_done != MTC_INIT_MAGIC) { @@ -3911,6 +3966,4 @@ void _minerva_init(mtc_config_t *mtc_cfg, bdkParams_t bp) #endif mtc_cfg->train_ram_patterns = train_ram_patterns; - mtc_cfg->fsp_for_src_freq = fsp_for_src_freq; - mtc_cfg->emc_2X_clk_src_is_pllmb = emc_2X_clk_src_is_pllmb; } diff --git a/modules/hekate_libsys_minerva/types.h b/modules/hekate_libsys_minerva/types.h index 9a4d414..00c7662 100644 --- a/modules/hekate_libsys_minerva/types.h +++ b/modules/hekate_libsys_minerva/types.h @@ -20,6 +20,7 @@ #define NULL ((void *)0) #define ALIGN(x, a) (((x) + (a) - 1) & ~((a) - 1)) +#define BIT(n) (1U << (n)) #define MAX(a, b) ((a) > (b) ? (a) : (b)) #define MIN(a, b) ((a) < (b) ? (a) : (b)) diff --git a/modules/simple_sample/Makefile b/modules/simple_sample/Makefile index da65320..2c0d7d7 100644 --- a/modules/simple_sample/Makefile +++ b/modules/simple_sample/Makefile @@ -35,7 +35,7 @@ $(BUILD)/%.o: ./%.c $(TARGET).bso: $(OBJS) @$(CC) $(LDFLAGS) -e _modInit $^ -o $(OUTPUT)/$(TARGET).bso @$(STRIP) -g $(OUTPUT)/$(TARGET).bso - @echo "-------------\nBuilt module: "$(TARGET)".bso\n-------------" + @echo -e "-------------\nBuilt module: "$(TARGET)".bso\n-------------" clean: @rm -rf $(OUTPUT)/$(TARGET).bso diff --git a/modules/simple_sample/gfx/gfx.c b/modules/simple_sample/gfx/gfx.c index 5c30ba7..0557f45 100644 --- a/modules/simple_sample/gfx/gfx.c +++ b/modules/simple_sample/gfx/gfx.c @@ -326,9 +326,9 @@ void gfx_printf(const char *fmt, ...) int fill, fcnt; va_start(ap, fmt); - while(*fmt) + while (*fmt) { - if(*fmt == '%') + if (*fmt == '%') { fmt++; fill = 0; @@ -400,17 +400,17 @@ void gfx_hexdump(u32 base, const u8 *buf, u32 len) u8 prevFontSize = gfx_con.fntsz; gfx_con.fntsz = 8; - for(u32 i = 0; i < len; i++) + for (u32 i = 0; i < len; i++) { - if(i % 0x10 == 0) + if (i % 0x10 == 0) { - if(i != 0) + if (i != 0) { gfx_puts("| "); - for(u32 j = 0; j < 0x10; j++) + for (u32 j = 0; j < 0x10; j++) { u8 c = buf[i - 0x10 + j]; - if(c >= 32 && c <= 126) + if (c >= 32 && c <= 126) gfx_putc(c); else gfx_putc('.'); @@ -431,10 +431,10 @@ void gfx_hexdump(u32 base, const u8 *buf, u32 len) gfx_puts(" "); } gfx_puts("| "); - for(u32 j = 0; j < (ln ? k : k + 1); j++) + for (u32 j = 0; j < (ln ? k : k + 1); j++) { u8 c = buf[i - k + j]; - if(c >= 32 && c <= 126) + if (c >= 32 && c <= 126) gfx_putc(c); else gfx_putc('.'); diff --git a/nyx/Makefile b/nyx/Makefile index 983a43b..71709c5 100644 --- a/nyx/Makefile +++ b/nyx/Makefile @@ -33,10 +33,11 @@ OBJS = $(addprefix $(BUILDDIR)/$(TARGET)/, \ # Hardware. OBJS += $(addprefix $(BUILDDIR)/$(TARGET)/, \ - bpmp.o ccplex.o clock.o di.o gpio.o i2c.o irq.o pinmux.o pmc.o se.o smmu.o tsec.o uart.o \ + bpmp.o ccplex.o clock.o di.o vic.o i2c.o irq.o timer.o \ + gpio.o pinmux.o pmc.o se.o smmu.o tsec.o uart.o \ fuse.o kfuse.o \ mc.o sdram.o minerva.o ramdisk.o \ - sdmmc.o sdmmc_driver.o nx_emmc.o nx_emmc_bis.o nx_sd.o \ + sdmmc.o sdmmc_driver.o emmc.o sd.o nx_emmc_bis.o \ bm92t36.o bq24193.o max17050.o max7762x.o max77620-rtc.o regulator_5v.o \ touch.o joycon.o tmp451.o fan.o \ usbd.o xusbd.o usb_descriptors.o usb_gadget_ums.o usb_gadget_hid.o \ @@ -52,7 +53,6 @@ OBJS += $(addprefix $(BUILDDIR)/$(TARGET)/, \ # Horizon. OBJS += $(addprefix $(BUILDDIR)/$(TARGET)/, \ - nx_emmc.o \ hos.o pkg1.o pkg2.o \ ) @@ -77,8 +77,11 @@ FFCFG_INC := '"../nyx/$(SOURCEDIR)/libs/fatfs/ffconf.h"' ################################################################################ CUSTOMDEFINES := -DNYX_LOAD_ADDR=$(NYX_LOAD_ADDR) -DNYX_MAGIC=$(NYX_MAGIC) -CUSTOMDEFINES += -DNYX_VER_MJ=$(NYXVERSION_MAJOR) -DNYX_VER_MN=$(NYXVERSION_MINOR) -DNYX_VER_HF=$(NYXVERSION_HOTFX) -DNYX_RESERVED=$(NYXVERSION_RSVD) -CUSTOMDEFINES += -DNYX -DGFX_INC=$(GFX_INC) -DFFCFG_INC=$(FFCFG_INC) +CUSTOMDEFINES += -DNYX_VER_MJ=$(NYXVERSION_MAJOR) -DNYX_VER_MN=$(NYXVERSION_MINOR) -DNYX_VER_HF=$(NYXVERSION_HOTFX) -DNYX_VER_RL=$(NYXVERSION_REL) + +# BDK defines. +CUSTOMDEFINES += -DBDK_MC_ENABLE_AHB_REDIRECT -DBDK_MINERVA_CFG_FROM_RAM -DBDK_HW_EXTRA_DEINIT -DBDK_SDMMC_EXTRA_PRINT +CUSTOMDEFINES += -DGFX_INC=$(GFX_INC) -DFFCFG_INC=$(FFCFG_INC) #CUSTOMDEFINES += -DDEBUG @@ -90,10 +93,12 @@ CUSTOMDEFINES += -DNYX -DGFX_INC=$(GFX_INC) -DFFCFG_INC=$(FFCFG_INC) #CUSTOMDEFINES += -DDEBUG_UART_LV_LOG #TODO: Considering reinstating some of these when pointer warnings have been fixed. -WARNINGS := -Wall -Wno-array-bounds -Wno-stringop-overread -Wno-stringop-overflow +WARNINGS := -Wall -Wsign-compare -Wtype-limits -Wno-array-bounds -Wno-stringop-overread -Wno-stringop-overflow +#-fno-delete-null-pointer-checks +#-Wstack-usage=byte-size -fstack-usage -ARCH := -march=armv4t -mtune=arm7tdmi -mthumb-interwork -CFLAGS = $(ARCH) -O2 -g -nostdlib -ffunction-sections -fdata-sections -fomit-frame-pointer -std=gnu11 $(WARNINGS) $(CUSTOMDEFINES) +ARCH := -march=armv4t -mtune=arm7tdmi -mthumb-interwork $(WARNINGS) +CFLAGS = $(ARCH) -O2 -g -gdwarf-4 -nostdlib -ffunction-sections -fdata-sections -fomit-frame-pointer -std=gnu11 $(CUSTOMDEFINES) LDFLAGS = $(ARCH) -nostartfiles -lgcc -Wl,--nmagic,--gc-sections -Xlinker --defsym=NYX_LOAD_ADDR=$(NYX_LOAD_ADDR) ################################################################################ @@ -102,7 +107,7 @@ LDFLAGS = $(ARCH) -nostartfiles -lgcc -Wl,--nmagic,--gc-sections -Xlinker --defs all: $(TARGET).bin @echo "--------------------------------------" - @echo -n "Nyx size: " + @echo -n "Nyx size: " $(eval BIN_SIZE = $(shell wc -c < $(OUTPUTDIR)/$(TARGET).bin)) @echo $(BIN_SIZE)" Bytes" @echo "--------------------------------------" @@ -113,11 +118,11 @@ clean: @rm -rf $(OUTPUTDIR) $(TARGET).bin: $(BUILDDIR)/$(TARGET)/$(TARGET).elf - $(OBJCOPY) -S -O binary $< $(OUTPUTDIR)/$@ + @$(OBJCOPY) -S -O binary $< $(OUTPUTDIR)/$@ $(BUILDDIR)/$(TARGET)/$(TARGET).elf: $(OBJS) @$(CC) $(LDFLAGS) -T $(SOURCEDIR)/link.ld $^ -o $@ - @echo "Nyx was built with the following flags:\nCFLAGS: "$(CFLAGS)"\nLDFLAGS: "$(LDFLAGS) + @printf "$(TARGET) was built with the following flags:\nCFLAGS: $(CFLAGS)\nLDFLAGS: $(LDFLAGS)\n" $(BUILDDIR)/$(TARGET)/%.o: %.c @echo Building $@ diff --git a/nyx/README_RES.md b/nyx/README_RES.md index 4538adf..f4f54e3 100644 --- a/nyx/README_RES.md +++ b/nyx/README_RES.md @@ -2,10 +2,14 @@ The background for Nyx, must be a 1280 x 720 32-bit BMP. Alpha blending is taken into account. For that reason, if a solid background is required, that value must be 0xFF. There are sites that can produce the correct bmp. -The icons supported are 192 x 192 32-bit BMP. You can utilize transparency at will and make nice mixes with the button background. +The icons supported are 192 x 192 32-bit BMP. You can utilize transparency at will and make nice mixes with the button background. Additionally, using the `icon={sd path}`, the icon will get colorized if the name ends in `_hue.bmp`. That only works nicely if the icon is a white layout with transparency. +If `_nobox.bmp` is used then the button background is removed. Useful for icon themes that aim for a specific style. + +A combo of both can be enabled via `_hue_nobox.bmp` suffix. + The default system icons (`icon_switch.bmp` and `icon_payload.bmp`) can be replaced with white layouts that have transparency. They can also be replaced with normal icons if the following exist: `icon_switch_custom.bmp` or/and `icon_payload_custom.bmp` @@ -13,4 +17,4 @@ The default system icons (`icon_switch.bmp` and `icon_payload.bmp`) can be repla The background must go to /bootloader/res/background.bmp -The icons can be utilized either via `[boot entries names]` -> `boot entries names.bmp` or by using `icon={sd path}`, which should point at a bmp. +The icons can be utilized either via `[boot entries names]` -> `boot entries names.bmp` or by using `icon={sd path}` (preferred method), which should point at a bmp. diff --git a/nyx/nyx_gui/config.c b/nyx/nyx_gui/config.c index 7ddf771..b70d437 100644 --- a/nyx/nyx_gui/config.c +++ b/nyx/nyx_gui/config.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2023 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,57 +17,53 @@ #include #include +#include + #include "config.h" -#include -#include #include -#include -#include -#include -#include -#include -#include -#include -#include extern hekate_config h_cfg; extern nyx_config n_cfg; void set_default_configuration() { - h_cfg.autoboot = 0; + h_cfg.t210b01 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01; + + h_cfg.autoboot = 0; h_cfg.autoboot_list = 0; - h_cfg.bootwait = 3; - h_cfg.backlight = 100; - h_cfg.autohosoff = 0; - h_cfg.autonogc = 1; - h_cfg.updater2p = 0; - h_cfg.bootprotect = 0; + h_cfg.bootwait = 3; + h_cfg.noticker = 0; + h_cfg.backlight = 100; + h_cfg.autohosoff = h_cfg.t210b01 ? 1 : 0; + h_cfg.autonogc = 1; + h_cfg.updater2p = 0; + h_cfg.bootprotect = 0; + h_cfg.errors = 0; h_cfg.eks = NULL; h_cfg.rcm_patched = fuse_check_patched_rcm(); + h_cfg.autorcm_enabled = false; h_cfg.emummc_force_disable = false; - h_cfg.t210b01 = hw_get_chip_id() == GP_HIDREV_MAJOR_T210B01; sd_power_cycle_time_start = 0; } void set_nyx_default_configuration() { - n_cfg.themecolor = 167; - n_cfg.timeoff = 0; - n_cfg.home_screen = 0; - n_cfg.verification = 1; - n_cfg.ums_emmc_rw = 0; - n_cfg.jc_disable = 0; - n_cfg.bpmp_clock = 0; + n_cfg.theme_bg = 0x2D2D2D; + n_cfg.theme_color = 167; + n_cfg.entries_5_col = 0; + n_cfg.timeoff = 0; + n_cfg.home_screen = 0; + n_cfg.verification = 1; + n_cfg.ums_emmc_rw = 0; + n_cfg.jc_disable = 0; + n_cfg.jc_force_right = 0; + n_cfg.bpmp_clock = 0; } int create_config_entry() { - if (!sd_mount()) - return 1; - char lbuf[64]; FIL fp; bool mainIniFound = false; @@ -120,6 +116,10 @@ int create_config_entry() itoa(h_cfg.backlight, lbuf, 10); f_puts(lbuf, &fp); + f_puts("\nnoticker=", &fp); + itoa(h_cfg.noticker, lbuf, 10); + f_puts(lbuf, &fp); + f_puts("\nautohosoff=", &fp); itoa(h_cfg.autohosoff, lbuf, 10); f_puts(lbuf, &fp); @@ -135,6 +135,7 @@ int create_config_entry() f_puts("\nbootprotect=", &fp); itoa(h_cfg.bootprotect, lbuf, 10); f_puts(lbuf, &fp); + f_puts("\n", &fp); if (mainIniFound) @@ -175,10 +176,11 @@ int create_config_entry() break; } } + + ini_free(&ini_sections); } f_close(&fp); - sd_unmount(); return 0; } @@ -200,27 +202,46 @@ int create_nyx_config_entry(bool force_unmount) return 1; // Add config entry. - f_puts("[config]\nthemecolor=", &fp); - itoa(n_cfg.themecolor, lbuf, 10); + f_puts("[config]\nthemebg=", &fp); + itoa(n_cfg.theme_bg, lbuf, 16); f_puts(lbuf, &fp); + + f_puts("\nthemecolor=", &fp); + itoa(n_cfg.theme_color, lbuf, 10); + f_puts(lbuf, &fp); + + f_puts("\nentries5col=", &fp); + itoa(n_cfg.entries_5_col, lbuf, 10); + f_puts(lbuf, &fp); + f_puts("\ntimeoff=", &fp); itoa(n_cfg.timeoff, lbuf, 16); f_puts(lbuf, &fp); + f_puts("\nhomescreen=", &fp); itoa(n_cfg.home_screen, lbuf, 10); f_puts(lbuf, &fp); + f_puts("\nverification=", &fp); itoa(n_cfg.verification, lbuf, 10); f_puts(lbuf, &fp); + f_puts("\numsemmcrw=", &fp); itoa(n_cfg.ums_emmc_rw, lbuf, 10); f_puts(lbuf, &fp); + f_puts("\njcdisable=", &fp); itoa(n_cfg.jc_disable, lbuf, 10); f_puts(lbuf, &fp); + + f_puts("\njcforceright=", &fp); + itoa(n_cfg.jc_force_right, lbuf, 10); + f_puts(lbuf, &fp); + f_puts("\nbpmpclock=", &fp); itoa(n_cfg.bpmp_clock, lbuf, 10); f_puts(lbuf, &fp); + f_puts("\n", &fp); f_close(&fp); diff --git a/nyx/nyx_gui/config.h b/nyx/nyx_gui/config.h index aa23dec..d2076e8 100644 --- a/nyx/nyx_gui/config.h +++ b/nyx/nyx_gui/config.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2023 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,8 +17,9 @@ #ifndef _CONFIG_H_ #define _CONFIG_H_ +#include + #include "hos/hos.h" -#include typedef struct _hekate_config { @@ -26,6 +27,7 @@ typedef struct _hekate_config u32 autoboot; u32 autoboot_list; u32 bootwait; + u32 noticker; u32 backlight; u32 autohosoff; u32 autonogc; @@ -35,18 +37,22 @@ typedef struct _hekate_config bool t210b01; bool emummc_force_disable; bool rcm_patched; + bool autorcm_enabled; u32 errors; hos_eks_mbr_t *eks; } hekate_config; typedef struct _nyx_config { - u32 themecolor; + u32 theme_bg; + u32 theme_color; + u32 entries_5_col; u32 timeoff; u32 home_screen; u32 verification; u32 ums_emmc_rw; u32 jc_disable; + u32 jc_force_right; u32 bpmp_clock; } nyx_config; diff --git a/nyx/nyx_gui/frontend/fe_emmc_tools.c b/nyx/nyx_gui/frontend/fe_emmc_tools.c index f89beda..2264f8a 100644 --- a/nyx/nyx_gui/frontend/fe_emmc_tools.c +++ b/nyx/nyx_gui/frontend/fe_emmc_tools.c @@ -1,7 +1,7 @@ /* * Copyright (c) 2018 naehrwert * Copyright (c) 2018 Rajko Stojadinovic - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -21,22 +21,13 @@ #include #include +#include + #include "gui.h" #include "fe_emmc_tools.h" #include "fe_emummc_tools.h" -#include #include "../config.h" #include -#include -#include -#include -#include -#include "../storage/nx_emmc.h" -#include -#include -#include -#include -#include #define NUM_SECTORS_PER_ITER 8192 // 4MB Cache. #define OUT_FILENAME_SZ 128 @@ -49,7 +40,7 @@ extern char *emmcsn_path_impl(char *path, char *sub_dir, char *filename, sdmmc_s static void _get_valid_partition(u32 *sector_start, u32 *sector_size, u32 *part_idx, bool backup) { sd_mount(); - mbr_t *mbr = (mbr_t *)calloc(sizeof(mbr_t), 1); + mbr_t *mbr = (mbr_t *)zalloc(sizeof(mbr_t)); sdmmc_storage_read(&sd_storage, 0, 1, mbr); *part_idx = 0; @@ -62,19 +53,19 @@ static void _get_valid_partition(u32 *sector_start, u32 *sector_size, u32 *part_ *sector_start = mbr->partitions[i].start_sct; u8 type = mbr->partitions[i].type; u32 sector_size_safe = backup ? 0x400000 : (*sector_size) + 0x8000; // 2GB min safe size for backup. - if ((curr_part_size >= sector_size_safe) && *sector_start && type != 0x83 && (!backup || type == 0xE0)) + if ((curr_part_size >= sector_size_safe) && (*sector_start) && type != 0x83 && (!backup || type == 0xE0)) { if (backup) { - u8 gpt_check[512] = { 0 }; - sdmmc_storage_read(&sd_storage, *sector_start + 0xC001, 1, gpt_check); + u8 gpt_check[SD_BLOCKSIZE] = { 0 }; + sdmmc_storage_read(&sd_storage, (*sector_start) + 0xC001, 1, gpt_check); if (!memcmp(gpt_check, "EFI PART", 8)) { *sector_size = curr_part_size; - *sector_start = *sector_start + 0x8000; + *sector_start = (*sector_start) + 0x8000; break; } - sdmmc_storage_read(&sd_storage, *sector_start + 0x4001, 1, gpt_check); + sdmmc_storage_read(&sd_storage, (*sector_start) + 0x4001, 1, gpt_check); if (!memcmp(gpt_check, "EFI PART", 8)) { *sector_size = curr_part_size; @@ -99,8 +90,8 @@ static void _get_valid_partition(u32 *sector_start, u32 *sector_size, u32 *part_ // Get emuMMC GPP size. if (backup && *part_idx && *sector_size) { - gpt_t *gpt = (gpt_t *)calloc(sizeof(gpt_t), 1); - sdmmc_storage_read(&sd_storage, *sector_start + 0x4001, 1, gpt); + gpt_t *gpt = (gpt_t *)zalloc(sizeof(gpt_t)); + sdmmc_storage_read(&sd_storage, (*sector_start) + 0x4001, 1, gpt); u32 new_size = gpt->header.alt_lba + 1; if (*sector_size > new_size) @@ -111,16 +102,16 @@ static void _get_valid_partition(u32 *sector_start, u32 *sector_size, u32 *part_ free(gpt); } else if (!backup && *part_idx) - *sector_start = *sector_start + 0x8000; + *sector_start = (*sector_start) + 0x8000; } -static lv_obj_t *create_mbox_text(char *text, bool button_ok) +static lv_obj_t *create_mbox_text(const char *text, bool button_ok) { lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL); lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char *mbox_btn_map[] = { "\211", "\222OK", "\211", "" }; + static const char *mbox_btn_map[] = { "\251", "\222OK", "\251", "" }; lv_obj_t *mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); lv_obj_set_width(mbox, LV_HOR_RES / 9 * 6); @@ -146,7 +137,7 @@ static void _update_filename(char *outFilename, u32 sdPathLen, u32 currPartIdx) itoa(currPartIdx, &outFilename[sdPathLen], 10); } -static int _dump_emmc_verify(emmc_tool_gui_t *gui, sdmmc_storage_t *storage, u32 lba_curr, char *outFilename, emmc_part_t *part) +static int _dump_emmc_verify(emmc_tool_gui_t *gui, sdmmc_storage_t *storage, u32 lba_curr, const char *outFilename, const emmc_part_t *part) { FIL fp; FIL hashFp; @@ -154,7 +145,7 @@ static int _dump_emmc_verify(emmc_tool_gui_t *gui, sdmmc_storage_t *storage, u32 u32 prevPct = 200; u32 sdFileSector = 0; int res = 0; - const char hexa[] = "0123456789abcdef"; + static const char hexa[] = "0123456789abcdef"; DWORD *clmt = NULL; u8 hashEm[SE_SHA_256_SIZE]; @@ -183,7 +174,7 @@ static int _dump_emmc_verify(emmc_tool_gui_t *gui, sdmmc_storage_t *storage, u32 } char chunkSizeAscii[10]; - itoa(NUM_SECTORS_PER_ITER * NX_EMMC_BLOCKSIZE, chunkSizeAscii, 10); + itoa(NUM_SECTORS_PER_ITER * EMMC_BLOCKSIZE, chunkSizeAscii, 10); chunkSizeAscii[9] = '\0'; f_puts("# chunksize: ", &hashFp); @@ -204,7 +195,7 @@ static int _dump_emmc_verify(emmc_tool_gui_t *gui, sdmmc_storage_t *storage, u32 lv_label_set_text(gui->label_pct, gui->txt_buf); manual_system_maintenance(true); - clmt = f_expand_cltbl(&fp, 0x400000, 0); + clmt = f_expand_cltbl(&fp, SZ_4M, 0); u32 num = 0; while (totalSectorsVer > 0) @@ -337,7 +328,7 @@ static int _dump_emmc_verify(emmc_tool_gui_t *gui, sdmmc_storage_t *storage, u32 } else { - s_printf(gui->txt_buf, "#FFDD00 File not found or could not be loaded!#\n#FFDD00 Verification failed..#\n"); + s_printf(gui->txt_buf, "\n#FFDD00 File not found or could not be loaded!#\n#FFDD00 Verification failed..#\n"); lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); manual_system_maintenance(true); @@ -349,8 +340,8 @@ bool partial_sd_full_unmount = false; static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part, sdmmc_storage_t *storage, emmc_part_t *part) { - const u32 FAT32_FILESIZE_LIMIT = 0xFFFFFFFF; - const u32 SECTORS_TO_MIB_COEFF = 11; + static const u32 FAT32_FILESIZE_LIMIT = 0xFFFFFFFF; + static const u32 SECTORS_TO_MIB_COEFF = 11; partial_sd_full_unmount = false; @@ -395,7 +386,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part, } s_printf(gui->txt_buf, "#96FF00 SD Card free space:# %d MiB\n#96FF00 Total backup size:# %d MiB\n\n", - sd_fs.free_clst * sd_fs.csize >> SECTORS_TO_MIB_COEFF, + (u32)(sd_fs.free_clst * sd_fs.csize >> SECTORS_TO_MIB_COEFF), totalSectors >> SECTORS_TO_MIB_COEFF); lv_label_ins_text(gui->label_info, LV_LABEL_POS_LAST, gui->txt_buf); manual_system_maintenance(true); @@ -410,7 +401,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part, if ((sd_storage.csd.capacity >> (20 - sd_storage.csd.read_blkbits)) <= 8192) multipartSplitSize = (1u << 30); // Maximum parts fitting the free space available. - maxSplitParts = (sd_fs.free_clst * sd_fs.csize) / (multipartSplitSize / NX_EMMC_BLOCKSIZE); + maxSplitParts = (sd_fs.free_clst * sd_fs.csize) / (multipartSplitSize / EMMC_BLOCKSIZE); // Check if the USER partition or the RAW eMMC fits the sd card free space. if (totalSectors > (sd_fs.free_clst * sd_fs.csize)) @@ -431,7 +422,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part, } } // Check if we are continuing a previous raw eMMC or USER partition backup in progress. - if (f_open(&partialIdxFp, partialIdxFilename, FA_READ) == FR_OK && totalSectors > (FAT32_FILESIZE_LIMIT / NX_EMMC_BLOCKSIZE)) + if (f_open(&partialIdxFp, partialIdxFilename, FA_READ) == FR_OK && totalSectors > (FAT32_FILESIZE_LIMIT / EMMC_BLOCKSIZE)) { s_printf(gui->txt_buf, "\n#AEFD14 Partial Backup in progress. Continuing...#\n"); lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); @@ -464,9 +455,9 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part, } // Check if filesystem is FAT32 or the free space is smaller and backup in parts. - if (((sd_fs.fs_type != FS_EXFAT) && totalSectors > (FAT32_FILESIZE_LIMIT / NX_EMMC_BLOCKSIZE)) || isSmallSdCard) + if (((sd_fs.fs_type != FS_EXFAT) && totalSectors > (FAT32_FILESIZE_LIMIT / EMMC_BLOCKSIZE)) || isSmallSdCard) { - u32 multipartSplitSectors = multipartSplitSize / NX_EMMC_BLOCKSIZE; + u32 multipartSplitSectors = multipartSplitSize / EMMC_BLOCKSIZE; numSplitParts = (totalSectors + multipartSplitSectors - 1) / multipartSplitSectors; outFilename[sdPathLen++] = '.'; @@ -520,15 +511,15 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part, // Continue from where we left, if Partial Backup in progress. if (partialDumpInProgress) { - lba_curr += currPartIdx * (multipartSplitSize / NX_EMMC_BLOCKSIZE); - totalSectors -= currPartIdx * (multipartSplitSize / NX_EMMC_BLOCKSIZE); + lba_curr += currPartIdx * (multipartSplitSize / EMMC_BLOCKSIZE); + totalSectors -= currPartIdx * (multipartSplitSize / EMMC_BLOCKSIZE); lbaStartPart = lba_curr; // Update the start LBA for verification. } u64 totalSize = (u64)((u64)totalSectors << 9); if (!isSmallSdCard && (sd_fs.fs_type == FS_EXFAT || totalSize <= FAT32_FILESIZE_LIMIT)) - clmt = f_expand_cltbl(&fp, 0x400000, totalSize); + clmt = f_expand_cltbl(&fp, SZ_4M, totalSize); else - clmt = f_expand_cltbl(&fp, 0x400000, MIN(totalSize, multipartSplitSize)); + clmt = f_expand_cltbl(&fp, SZ_4M, MIN(totalSize, multipartSplitSize)); u32 num = 0; u32 pct = 0; @@ -572,7 +563,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part, } else { - s_printf(gui->txt_buf, "#FF0000 Error creating partial.idx file!#\n"); + s_printf(gui->txt_buf, "\n#FF0000 Error creating partial.idx file!#\n"); lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); manual_system_maintenance(true); @@ -617,7 +608,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part, bytesWritten = 0; totalSize = (u64)((u64)totalSectors << 9); - clmt = f_expand_cltbl(&fp, 0x400000, MIN(totalSize, multipartSplitSize)); + clmt = f_expand_cltbl(&fp, SZ_4M, MIN(totalSize, multipartSplitSize)); } retryCount = 0; @@ -631,10 +622,20 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part, while (res_read) { - s_printf(gui->txt_buf, - "\n#FFDD00 Error reading %d blocks @ LBA %08X,#\n" - "#FFDD00 from eMMC (try %d). #", - num, lba_curr, ++retryCount); + if (!gui->raw_emummc) + { + s_printf(gui->txt_buf, + "\n#FFDD00 Error reading %d blocks @ LBA %08X,#\n" + "#FFDD00 from eMMC (try %d). #", + num, lba_curr, ++retryCount); + } + else + { + s_printf(gui->txt_buf, + "\n#FFDD00 Error reading %d blocks @ LBA %08X,#\n" + "#FFDD00 from emuMMC @ %08X (try %d). #", + num, lba_curr + sd_sector_off, lba_curr, ++retryCount); + } lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); manual_system_maintenance(true); @@ -660,7 +661,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part, } manual_system_maintenance(false); - res = f_write_fast(&fp, buf, NX_EMMC_BLOCKSIZE * num); + res = f_write_fast(&fp, buf, EMMC_BLOCKSIZE * num); if (res) { @@ -690,7 +691,7 @@ static int _dump_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part, lba_curr += num; totalSectors -= num; - bytesWritten += num * NX_EMMC_BLOCKSIZE; + bytesWritten += num * EMMC_BLOCKSIZE; // Force a flush after a lot of data if not splitting. if (numSplitParts == 0 && bytesWritten >= multipartSplitSize) @@ -759,10 +760,10 @@ void dump_emmc_selected(emmcPartType_t dumpType, emmc_tool_gui_t *gui) int res = 0; u32 timer = 0; - char *txt_buf = (char *)malloc(0x4000); + char *txt_buf = (char *)malloc(SZ_16K); gui->txt_buf = txt_buf; - s_printf(txt_buf, ""); + txt_buf[0] = 0; lv_label_set_text(gui->label_log, txt_buf); lv_label_set_text(gui->label_info, "Checking for available free space..."); @@ -777,7 +778,7 @@ void dump_emmc_selected(emmcPartType_t dumpType, emmc_tool_gui_t *gui) // Get SD Card free space for Partial Backup. f_getfree("", &sd_fs.free_clst, NULL); - if (!sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400)) + if (!emmc_initialize(false)) { lv_label_set_text(gui->label_info, "#FFDD00 Failed to init eMMC!#"); goto out; @@ -787,7 +788,10 @@ void dump_emmc_selected(emmcPartType_t dumpType, emmc_tool_gui_t *gui) char sdPath[OUT_FILENAME_SZ]; // Create Restore folders, if they do not exist. emmcsn_path_impl(sdPath, "/restore", "", &emmc_storage); + emmcsn_path_impl(sdPath, "/restore/emummc", "", &emmc_storage); emmcsn_path_impl(sdPath, "/restore/partitions", "", &emmc_storage); + + // Set folder to backup/{emmc_sn}. emmcsn_path_impl(sdPath, "", "", &emmc_storage); gui->base_path = (char *)malloc(strlen(sdPath) + 1); strcpy(gui->base_path, sdPath); @@ -796,11 +800,15 @@ void dump_emmc_selected(emmcPartType_t dumpType, emmc_tool_gui_t *gui) if (dumpType & PART_BOOT) { const u32 BOOT_PART_SIZE = emmc_storage.ext_csd.boot_mult << 17; + const u32 BOOT_PART_SECTORS = 0x2000; // Force 4 MiB for emuMMC. emmc_part_t bootPart; memset(&bootPart, 0, sizeof(bootPart)); bootPart.lba_start = 0; - bootPart.lba_end = (BOOT_PART_SIZE / NX_EMMC_BLOCKSIZE) - 1; + if (!gui->raw_emummc) + bootPart.lba_end = (BOOT_PART_SIZE / EMMC_BLOCKSIZE) - 1; + else + bootPart.lba_end = BOOT_PART_SECTORS - 1; for (i = 0; i < 2; i++) { strcpy(bootPart.name, "BOOT"); @@ -814,9 +822,14 @@ void dump_emmc_selected(emmcPartType_t dumpType, emmc_tool_gui_t *gui) lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf); manual_system_maintenance(true); - sdmmc_storage_set_mmc_partition(&emmc_storage, i + 1); + emmc_set_partition(i + 1); + + // Set filename to backup/{emmc_sn}/BOOT0/1 or backup/{emmc_sn}/emummc/BOOT0/1. + if (!gui->raw_emummc) + emmcsn_path_impl(sdPath, "", bootPart.name, &emmc_storage); + else + emmcsn_path_impl(sdPath, "/emummc", bootPart.name, &emmc_storage); - emmcsn_path_impl(sdPath, "", bootPart.name, &emmc_storage); res = _dump_emmc_part(gui, sdPath, i, &emmc_storage, &bootPart); if (!res) @@ -831,7 +844,7 @@ void dump_emmc_selected(emmcPartType_t dumpType, emmc_tool_gui_t *gui) if ((dumpType & PART_SYSTEM) || (dumpType & PART_USER) || (dumpType & PART_RAW)) { - sdmmc_storage_set_mmc_partition(&emmc_storage, EMMC_GPP); + emmc_set_partition(EMMC_GPP); if ((dumpType & PART_SYSTEM) || (dumpType & PART_USER)) { @@ -840,7 +853,7 @@ void dump_emmc_selected(emmcPartType_t dumpType, emmc_tool_gui_t *gui) strcpy(gui->base_path, sdPath); LIST_INIT(gpt); - nx_emmc_gpt_parse(&gpt, &emmc_storage); + emmc_gpt_parse(&gpt); LIST_FOREACH_ENTRY(emmc_part_t, part, &gpt, link) { if ((dumpType & PART_USER) == 0 && !strcmp(part->name, "USER")) @@ -871,7 +884,7 @@ void dump_emmc_selected(emmcPartType_t dumpType, emmc_tool_gui_t *gui) lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf); manual_system_maintenance(true); } - nx_emmc_gpt_free(&gpt); + emmc_gpt_free(&gpt); } if (dumpType & PART_RAW) @@ -894,7 +907,12 @@ void dump_emmc_selected(emmcPartType_t dumpType, emmc_tool_gui_t *gui) i++; - emmcsn_path_impl(sdPath, "", rawPart.name, &emmc_storage); + // Set filename to backup/{emmc_sn}/rawnand.bin or backup/{emmc_sn}/emummc/rawnand.bin. + if (!gui->raw_emummc) + emmcsn_path_impl(sdPath, "", rawPart.name, &emmc_storage); + else + emmcsn_path_impl(sdPath, "/emummc", rawPart.name, &emmc_storage); + res = _dump_emmc_part(gui, sdPath, 2, &emmc_storage, &rawPart); if (!res) @@ -909,7 +927,7 @@ void dump_emmc_selected(emmcPartType_t dumpType, emmc_tool_gui_t *gui) } timer = get_tmr_s() - timer; - sdmmc_storage_end(&emmc_storage); + emmc_end(); if (res && n_cfg.verification && !gui->raw_emummc) s_printf(txt_buf, "Time taken: %dm %ds.\n#96FF00 Finished and verified!#", timer / 60, timer % 60); @@ -934,7 +952,7 @@ out: static int _restore_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_part, sdmmc_storage_t *storage, emmc_part_t *part, bool allow_multi_part) { - const u32 SECTORS_TO_MIB_COEFF = 11; + static const u32 SECTORS_TO_MIB_COEFF = 11; u32 lba_end = part->lba_end; u32 totalSectors = part->lba_end - part->lba_start + 1; @@ -959,124 +977,125 @@ static int _restore_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_pa bool use_multipart = false; bool check_4MB_aligned = true; - if (allow_multi_part) + if (!allow_multi_part) + goto multipart_not_allowed; + + // Check to see if there is a combined file and if so then use that. + if (f_stat(outFilename, &fno)) { - // Check to see if there is a combined file and if so then use that. - if (f_stat(outFilename, &fno)) + // If not, check if there are partial files and the total size matches. + s_printf(gui->txt_buf, "\nNo single file, checking for part files...\n"); + lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); + manual_system_maintenance(true); + + outFilename[sdPathLen++] = '.'; + + _update_filename(outFilename, sdPathLen, numSplitParts); + + s_printf(gui->txt_buf, "#96FF00 Filepath:#\n%s\n#96FF00 Filename:# #FF8000 %s#", + gui->base_path, outFilename + strlen(gui->base_path)); + lv_label_ins_text(gui->label_info, LV_LABEL_POS_LAST, gui->txt_buf); + + // Stat total size of the part files. + while ((u32)((u64)totalCheckFileSize >> (u64)9) != totalSectors) { - // If not, check if there are partial files and the total size matches. - s_printf(gui->txt_buf, "\nNo single file, checking for part files...\n"); - lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); - manual_system_maintenance(true); - - outFilename[sdPathLen++] = '.'; - _update_filename(outFilename, sdPathLen, numSplitParts); - s_printf(gui->txt_buf, "#96FF00 Filepath:#\n%s\n#96FF00 Filename:# #FF8000 %s#", - gui->base_path, outFilename + strlen(gui->base_path)); + s_printf(gui->txt_buf, "%s#", outFilename + strlen(gui->base_path)); + lv_label_cut_text(gui->label_info, + strlen(lv_label_get_text(gui->label_info)) - strlen(outFilename + strlen(gui->base_path)) - 1, + strlen(outFilename + strlen(gui->base_path)) + 1); lv_label_ins_text(gui->label_info, LV_LABEL_POS_LAST, gui->txt_buf); + manual_system_maintenance(true); - // Stat total size of the part files. - while ((u32)((u64)totalCheckFileSize >> (u64)9) != totalSectors) + if ((u32)((u64)totalCheckFileSize >> (u64)9) > totalSectors) { - _update_filename(outFilename, sdPathLen, numSplitParts); - - s_printf(gui->txt_buf, "%s#", outFilename + strlen(gui->base_path)); - lv_label_cut_text(gui->label_info, - strlen(lv_label_get_text(gui->label_info)) - strlen(outFilename + strlen(gui->base_path)) - 1, - strlen(outFilename + strlen(gui->base_path)) + 1); - lv_label_ins_text(gui->label_info, LV_LABEL_POS_LAST, gui->txt_buf); + s_printf(gui->txt_buf, "\n#FF8000 Size of SD Card split backup exceeds#\n#FF8000 eMMC's selected part size!#\n#FFDD00 Aborting...#"); + lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); manual_system_maintenance(true); - if ((u32)((u64)totalCheckFileSize >> (u64)9) > totalSectors) + return 0; + } + else if (f_stat(outFilename, &fno)) + { + if (!gui->raw_emummc) { - s_printf(gui->txt_buf, "#FF8000 Size of SD Card split backup exceeds#\n#FF8000 eMMC's selected part size!#\n#FFDD00 Aborting...#"); + s_printf(gui->txt_buf, "\n#FFDD00 Error (%d) file not found#\n#FFDD00 %s.#\n\n", res, outFilename); lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); manual_system_maintenance(true); - return 0; - } - else if (f_stat(outFilename, &fno)) - { - if (!gui->raw_emummc) - { - s_printf(gui->txt_buf, "#FFDD00 Error (%d) file not found#\n#FFDD00 %s.#\n\n", res, outFilename); - lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); - manual_system_maintenance(true); - - // Attempt a smaller restore. - if (numSplitParts) - break; - } - else - { - // Set new total sectors and lba end sector for percentage calculations. - totalSectors = (u32)((u64)totalCheckFileSize >> (u64)9); - lba_end = totalSectors + part->lba_start - 1; - } - - // Restore folder is empty. - if (!numSplitParts) - { - s_printf(gui->txt_buf, "#FFDD00 Restore folder is empty.#\n\n"); - lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); - manual_system_maintenance(true); - - return 0; - } + // Attempt a smaller restore. + if (numSplitParts) + break; } else { - totalCheckFileSize += (u64)fno.fsize; - - if (check_4MB_aligned && (((u64)fno.fsize) % 0x400000)) - { - s_printf(gui->txt_buf, "#FFDD00 The split file must be a#\n#FFDD00 multiple of 4 MiB.#\n#FFDD00 Aborting...#", res, outFilename); - lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); - manual_system_maintenance(true); - - return 0; - } - - check_4MB_aligned = false; + // Set new total sectors and lba end sector for percentage calculations. + totalSectors = (u32)((u64)totalCheckFileSize >> (u64)9); + lba_end = totalSectors + part->lba_start - 1; } - numSplitParts++; - } - - s_printf(gui->txt_buf, "%X sectors total.\n", (u32)((u64)totalCheckFileSize >> (u64)9)); - lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); - manual_system_maintenance(true); - - if ((u32)((u64)totalCheckFileSize >> (u64)9) != totalSectors) - { - lv_obj_t *warn_mbox_bg = create_mbox_text( - "#FF8000 Size of SD Card split backup does not match#\n#FF8000 eMMC's selected part size!#\n\n" - "#FFDD00 The backup might be corrupted,#\n#FFDD00 or missing files!#\n#FFDD00 Aborting is suggested!#\n\n" - "Press #FF8000 POWER# to Continue.\nPress #FF8000 VOL# to abort.", false); - manual_system_maintenance(true); - - if (!(btn_wait() & BTN_POWER)) + // Restore folder is empty. + if (!numSplitParts) { - lv_obj_del(warn_mbox_bg); - s_printf(gui->txt_buf, "#FF0000 Size of SD Card split backup does not match#\n#FF0000 eMMC's selected part size!#\n"); + s_printf(gui->txt_buf, "\n#FFDD00 Restore folder is empty.#\n\n"); lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); manual_system_maintenance(true); return 0; } - lv_obj_del(warn_mbox_bg); - - // Set new total sectors and lba end sector for percentage calculations. - totalSectors = (u32)((u64)totalCheckFileSize >> (u64)9); - lba_end = totalSectors + part->lba_start - 1; } - use_multipart = true; - _update_filename(outFilename, sdPathLen, 0); + else + { + totalCheckFileSize += (u64)fno.fsize; + + if (check_4MB_aligned && (((u64)fno.fsize) % SZ_4M)) + { + s_printf(gui->txt_buf, "\n#FFDD00 The split file must be a#\n#FFDD00 multiple of 4 MiB.#\n#FFDD00 Aborting...#"); + lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); + manual_system_maintenance(true); + + return 0; + } + + check_4MB_aligned = false; + } + + numSplitParts++; } + + s_printf(gui->txt_buf, "%X sectors total.\n", (u32)((u64)totalCheckFileSize >> (u64)9)); + lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); + manual_system_maintenance(true); + + if ((u32)((u64)totalCheckFileSize >> (u64)9) != totalSectors) + { + lv_obj_t *warn_mbox_bg = create_mbox_text( + "#FF8000 Size of SD Card split backup does not match#\n#FF8000 eMMC's selected part size!#\n\n" + "#FFDD00 The backup might be corrupted,#\n#FFDD00 or missing files!#\n#FFDD00 Aborting is suggested!#\n\n" + "Press #FF8000 POWER# to Continue.\nPress #FF8000 VOL# to abort.", false); + manual_system_maintenance(true); + + if (!(btn_wait() & BTN_POWER)) + { + lv_obj_del(warn_mbox_bg); + s_printf(gui->txt_buf, "\n#FF0000 Size of SD Card split backup does not match#\n#FF0000 eMMC's selected part size!#\n"); + lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); + manual_system_maintenance(true); + + return 0; + } + lv_obj_del(warn_mbox_bg); + + // Set new total sectors and lba end sector for percentage calculations. + totalSectors = (u32)((u64)totalCheckFileSize >> (u64)9); + lba_end = totalSectors + part->lba_start - 1; + } + use_multipart = true; + _update_filename(outFilename, sdPathLen, 0); } +multipart_not_allowed: res = f_open(&fp, outFilename, FA_READ); if (use_multipart) { @@ -1109,13 +1128,13 @@ static int _restore_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_pa manual_system_maintenance(true); } - return 0; + return -1; } else if (!use_multipart && (((u32)((u64)f_size(&fp) >> (u64)9)) != totalSectors)) // Check total restore size vs emmc size. { if (((u32)((u64)f_size(&fp) >> (u64)9)) > totalSectors) { - s_printf(gui->txt_buf, "#FF8000 Size of SD Card backup exceeds#\n#FF8000 eMMC's selected part size!#\n#FFDD00 Aborting...#"); + s_printf(gui->txt_buf, "\n#FF8000 Size of SD Card backup exceeds#\n#FF8000 eMMC's selected part size!#\n#FFDD00 Aborting...#"); lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); manual_system_maintenance(true); @@ -1134,7 +1153,7 @@ static int _restore_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_pa if (!(btn_wait() & BTN_POWER)) { lv_obj_del(warn_mbox_bg); - s_printf(gui->txt_buf, "\n#FF0000 Size of the SD Card backup does not match#\n#FF0000 eMMC's selected part size.#\n", res); + s_printf(gui->txt_buf, "\n#FF0000 Size of the SD Card backup does not match#\n#FF0000 eMMC's selected part size.#\n"); lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); manual_system_maintenance(true); @@ -1167,7 +1186,7 @@ static int _restore_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_pa u32 num = 0; u32 pct = 0; - DWORD *clmt = f_expand_cltbl(&fp, 0x400000, 0); + DWORD *clmt = f_expand_cltbl(&fp, SZ_4M, 0); u32 sector_start = 0, part_idx = 0; u32 sector_size = totalSectors; @@ -1237,7 +1256,7 @@ static int _restore_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_pa } fileSize = (u64)f_size(&fp); bytesWritten = 0; - clmt = f_expand_cltbl(&fp, 0x400000, 0); + clmt = f_expand_cltbl(&fp, SZ_4M, 0); } retryCount = 0; @@ -1269,8 +1288,8 @@ static int _restore_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_pa while (res) { s_printf(gui->txt_buf, - "\n#FFDD00 Error reading %d blocks @ LBA %08X,#\n" - "#FFDD00 from eMMC (try %d).\n#", + "\n#FFDD00 Error writing %d blocks @ LBA %08X,#\n" + "#FFDD00 from eMMC (try %d). #", num, lba_curr, ++retryCount); lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); manual_system_maintenance(true); @@ -1312,7 +1331,7 @@ static int _restore_emmc_part(emmc_tool_gui_t *gui, char *sd_path, int active_pa lba_curr += num; totalSectors -= num; - bytesWritten += num * NX_EMMC_BLOCKSIZE; + bytesWritten += num * EMMC_BLOCKSIZE; } lv_bar_set_value(gui->bar, 100); lv_label_set_text(gui->label_pct, " "SYMBOL_DOT" 100%"); @@ -1363,10 +1382,10 @@ void restore_emmc_selected(emmcPartType_t restoreType, emmc_tool_gui_t *gui) int res = 0; u32 timer = 0; - char *txt_buf = (char *)malloc(0x4000); + char *txt_buf = (char *)malloc(SZ_16K); gui->txt_buf = txt_buf; - s_printf(txt_buf, ""); + txt_buf[0] = 0; lv_label_set_text(gui->label_log, txt_buf); manual_system_maintenance(true); @@ -1415,7 +1434,7 @@ void restore_emmc_selected(emmcPartType_t restoreType, emmc_tool_gui_t *gui) goto out; } - if (!sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400)) + if (!emmc_initialize(false)) { lv_label_set_text(gui->label_info, "#FFDD00 Failed to init eMMC!#"); goto out; @@ -1423,8 +1442,10 @@ void restore_emmc_selected(emmcPartType_t restoreType, emmc_tool_gui_t *gui) int i = 0; char sdPath[OUT_FILENAME_SZ]; - - emmcsn_path_impl(sdPath, "/restore", "", &emmc_storage); + if (!gui->raw_emummc) + emmcsn_path_impl(sdPath, "/restore", "", &emmc_storage); + else + emmcsn_path_impl(sdPath, "/restore/emummc", "", &emmc_storage); gui->base_path = (char *)malloc(strlen(sdPath) + 1); strcpy(gui->base_path, sdPath); @@ -1432,11 +1453,15 @@ void restore_emmc_selected(emmcPartType_t restoreType, emmc_tool_gui_t *gui) if (restoreType & PART_BOOT) { const u32 BOOT_PART_SIZE = emmc_storage.ext_csd.boot_mult << 17; + const u32 BOOT_PART_SECTORS = 0x2000; // Force 4 MiB for emuMMC. emmc_part_t bootPart; memset(&bootPart, 0, sizeof(bootPart)); bootPart.lba_start = 0; - bootPart.lba_end = (BOOT_PART_SIZE / NX_EMMC_BLOCKSIZE) - 1; + if (!gui->raw_emummc) + bootPart.lba_end = (BOOT_PART_SIZE / EMMC_BLOCKSIZE) - 1; + else + bootPart.lba_end = BOOT_PART_SECTORS - 1; for (i = 0; i < 2; i++) { strcpy(bootPart.name, "BOOT"); @@ -1450,17 +1475,23 @@ void restore_emmc_selected(emmcPartType_t restoreType, emmc_tool_gui_t *gui) lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf); manual_system_maintenance(true); - sdmmc_storage_set_mmc_partition(&emmc_storage, i + 1); + emmc_set_partition(i + 1); - emmcsn_path_impl(sdPath, "/restore", bootPart.name, &emmc_storage); + if (!gui->raw_emummc) + emmcsn_path_impl(sdPath, "/restore", bootPart.name, &emmc_storage); + else + emmcsn_path_impl(sdPath, "/restore/emummc", bootPart.name, &emmc_storage); res = _restore_emmc_part(gui, sdPath, i, &emmc_storage, &bootPart, false); if (!res) s_printf(txt_buf, "#FFDD00 Failed!#\n"); - else + else if (res > 0) s_printf(txt_buf, "Done!\n"); - lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf); + if (res >= 0) + lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf); + else + res = 0; manual_system_maintenance(true); } } @@ -1471,10 +1502,10 @@ void restore_emmc_selected(emmcPartType_t restoreType, emmc_tool_gui_t *gui) gui->base_path = (char *)malloc(strlen(sdPath) + 1); strcpy(gui->base_path, sdPath); - sdmmc_storage_set_mmc_partition(&emmc_storage, EMMC_GPP); + emmc_set_partition(EMMC_GPP); LIST_INIT(gpt); - nx_emmc_gpt_parse(&gpt, &emmc_storage); + emmc_gpt_parse(&gpt); LIST_FOREACH_ENTRY(emmc_part_t, part, &gpt, link) { s_printf(txt_buf, "#00DDFF %02d: %s#\n#00DDFF Range: 0x%08X - 0x%08X#\n\n\n\n\n", @@ -1490,13 +1521,16 @@ void restore_emmc_selected(emmcPartType_t restoreType, emmc_tool_gui_t *gui) if (!res) s_printf(txt_buf, "#FFDD00 Failed!#\n"); - else + else if (res > 0) s_printf(txt_buf, "Done!\n"); - lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf); + if (res >= 0) + lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf); + else + res = 0; manual_system_maintenance(true); } - nx_emmc_gpt_free(&gpt); + emmc_gpt_free(&gpt); } if (restoreType & PART_RAW) @@ -1518,21 +1552,27 @@ void restore_emmc_selected(emmcPartType_t restoreType, emmc_tool_gui_t *gui) manual_system_maintenance(true); i++; - emmcsn_path_impl(sdPath, "/restore", rawPart.name, &emmc_storage); + if (!gui->raw_emummc) + emmcsn_path_impl(sdPath, "/restore", rawPart.name, &emmc_storage); + else + emmcsn_path_impl(sdPath, "/restore/emummc", rawPart.name, &emmc_storage); res = _restore_emmc_part(gui, sdPath, 2, &emmc_storage, &rawPart, true); if (!res) s_printf(txt_buf, "#FFDD00 Failed!#\n"); - else + else if (res > 0) s_printf(txt_buf, "Done!\n"); - lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf); + if (res >= 0) + lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf); + else + res = 0; manual_system_maintenance(true); } } timer = get_tmr_s() - timer; - sdmmc_storage_end(&emmc_storage); + emmc_end(); if (res && n_cfg.verification && !gui->raw_emummc) s_printf(txt_buf, "Time taken: %dm %ds.\n#96FF00 Finished and verified!#", timer / 60, timer % 60); diff --git a/nyx/nyx_gui/frontend/fe_emummc_tools.c b/nyx/nyx_gui/frontend/fe_emummc_tools.c index ae9be6c..2fd7006 100644 --- a/nyx/nyx_gui/frontend/fe_emummc_tools.c +++ b/nyx/nyx_gui/frontend/fe_emummc_tools.c @@ -1,7 +1,7 @@ /* * Copyright (c) 2018 naehrwert * Copyright (c) 2018 Rajko Stojadinovic - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -21,22 +21,13 @@ #include #include +#include + #include "gui.h" #include "fe_emummc_tools.h" #include "../config.h" -#include #include #include -#include -#include -#include -#include "../storage/nx_emmc.h" -#include "../storage/nx_emmc_bis.h" -#include -#include -#include -#include -#include #define OUT_FILENAME_SZ 128 #define NAND_PATROL_SECTOR 0xC20 @@ -51,28 +42,38 @@ void load_emummc_cfg(emummc_cfg_t *emu_info) // Parse emuMMC configuration. LIST_INIT(ini_sections); - if (ini_parse(&ini_sections, "emuMMC/emummc.ini", false)) + if (!ini_parse(&ini_sections, "emuMMC/emummc.ini", false)) + return; + + LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sections, link) { - LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sections, link) + if (!strcmp(ini_sec->name, "emummc")) { - if (!strcmp(ini_sec->name, "emummc")) + LIST_FOREACH_ENTRY(ini_kv_t, kv, &ini_sec->kvs, link) { - LIST_FOREACH_ENTRY(ini_kv_t, kv, &ini_sec->kvs, link) + if (!strcmp("enabled", kv->key)) + emu_info->enabled = atoi(kv->val); + else if (!strcmp("sector", kv->key)) + emu_info->sector = strtol(kv->val, NULL, 16); + else if (!strcmp("id", kv->key)) + emu_info->id = strtol(kv->val, NULL, 16); + else if (!strcmp("path", kv->key)) { - if (!strcmp("enabled", kv->key)) - emu_info->enabled = atoi(kv->val); - else if (!strcmp("sector", kv->key)) - emu_info->sector = strtol(kv->val, NULL, 16); - else if (!strcmp("id", kv->key)) - emu_info->id = strtol(kv->val, NULL, 16); - else if (!strcmp("path", kv->key)) - emu_info->path = kv->val; - else if (!strcmp("nintendo_path", kv->key)) - emu_info->nintendo_path = kv->val; + emu_info->path = (char *)malloc(strlen(kv->val) + 1); + strcpy(emu_info->path, kv->val); + } + else if (!strcmp("nintendo_path", kv->key)) + { + emu_info->nintendo_path = (char *)malloc(strlen(kv->val) + 1); + strcpy(emu_info->nintendo_path, kv->val); } } + + break; } } + + ini_free(&ini_sections); } void save_emummc_cfg(u32 part_idx, u32 sector_start, const char *path) @@ -92,7 +93,7 @@ void save_emummc_cfg(u32 part_idx, u32 sector_start, const char *path) itoa(part_idx, lbuf, 10); f_puts(lbuf, &fp); } - else if(path) + else if (path) f_puts("1", &fp); else f_puts("0", &fp); @@ -113,7 +114,7 @@ void save_emummc_cfg(u32 part_idx, u32 sector_start, const char *path) // Get ID from path. u32 id_from_path = 0; - if (strlen(path) >= 4) + if (path && strlen(path) >= 4) memcpy(&id_from_path, path + strlen(path) - 4, 4); f_puts("\nid=0x", &fp); itoa(id_from_path, lbuf, 16); @@ -142,7 +143,7 @@ void update_emummc_base_folder(char *outFilename, u32 sdPathLen, u32 currPartIdx itoa(currPartIdx, &outFilename[sdPathLen], 10); } -static int _dump_emummc_file_part(emmc_tool_gui_t *gui, char *sd_path, sdmmc_storage_t *storage, emmc_part_t *part) +static int _dump_emummc_file_part(emmc_tool_gui_t *gui, char *sd_path, sdmmc_storage_t *storage, const emmc_part_t *part) { static const u32 FAT32_FILESIZE_LIMIT = 0xFFFFFFFF; static const u32 SECTORS_TO_MIB_COEFF = 11; @@ -155,8 +156,8 @@ static int _dump_emummc_file_part(emmc_tool_gui_t *gui, char *sd_path, sdmmc_sto char *outFilename = sd_path; u32 sdPathLen = strlen(sd_path); - s_printf(gui->txt_buf, "#96FF00 SD Card free space:# %d MiB\n#96FF00 Total backup size:# %d MiB\n\n", - sd_fs.free_clst * sd_fs.csize >> SECTORS_TO_MIB_COEFF, + s_printf(gui->txt_buf, "#96FF00 SD Card free space:# %d MiB\n#96FF00 Total size:# %d MiB\n\n", + (u32)(sd_fs.free_clst * sd_fs.csize >> SECTORS_TO_MIB_COEFF), totalSectors >> SECTORS_TO_MIB_COEFF); lv_label_ins_text(gui->label_info, LV_LABEL_POS_LAST, gui->txt_buf); manual_system_maintenance(true); @@ -168,20 +169,20 @@ static int _dump_emummc_file_part(emmc_tool_gui_t *gui, char *sd_path, sdmmc_sto // Check if the USER partition or the RAW eMMC fits the sd card free space. if (totalSectors > (sd_fs.free_clst * sd_fs.csize)) { - s_printf(gui->txt_buf, "\n#FFDD00 Not enough free space for Partial Backup!#\n"); + s_printf(gui->txt_buf, "\n#FFDD00 Not enough free space for file based emuMMC!#\n"); lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); manual_system_maintenance(true); return 0; } - // Check if filesystem is FAT32 or the free space is smaller and backup in parts. - if (totalSectors > (FAT32_FILESIZE_LIMIT / NX_EMMC_BLOCKSIZE)) + // Check if filesystem is FAT32 or the free space is smaller and dump in parts. + if (totalSectors > (FAT32_FILESIZE_LIMIT / EMMC_BLOCKSIZE)) { - u32 multipartSplitSectors = multipartSplitSize / NX_EMMC_BLOCKSIZE; + u32 multipartSplitSectors = multipartSplitSize / EMMC_BLOCKSIZE; numSplitParts = (totalSectors + multipartSplitSectors - 1) / multipartSplitSectors; - // Continue from where we left, if Partial Backup in progress. + // Get first part filename. update_emummc_base_folder(outFilename, sdPathLen, 0); } @@ -211,9 +212,9 @@ static int _dump_emummc_file_part(emmc_tool_gui_t *gui, char *sd_path, sdmmc_sto u64 totalSize = (u64)((u64)totalSectors << 9); if (totalSize <= FAT32_FILESIZE_LIMIT) - clmt = f_expand_cltbl(&fp, 0x400000, totalSize); + clmt = f_expand_cltbl(&fp, SZ_4M, totalSize); else - clmt = f_expand_cltbl(&fp, 0x400000, MIN(totalSize, multipartSplitSize)); + clmt = f_expand_cltbl(&fp, SZ_4M, MIN(totalSize, multipartSplitSize)); u32 num = 0; u32 pct = 0; @@ -250,7 +251,7 @@ static int _dump_emummc_file_part(emmc_tool_gui_t *gui, char *sd_path, sdmmc_sto bytesWritten = 0; totalSize = (u64)((u64)totalSectors << 9); - clmt = f_expand_cltbl(&fp, 0x400000, MIN(totalSize, multipartSplitSize)); + clmt = f_expand_cltbl(&fp, SZ_4M, MIN(totalSize, multipartSplitSize)); } // Check for cancellation combo. @@ -271,6 +272,7 @@ static int _dump_emummc_file_part(emmc_tool_gui_t *gui, char *sd_path, sdmmc_sto retryCount = 0; num = MIN(totalSectors, NUM_SECTORS_PER_ITER); + while (!sdmmc_storage_read(storage, lba_curr, num, buf)) { s_printf(gui->txt_buf, @@ -303,7 +305,7 @@ static int _dump_emummc_file_part(emmc_tool_gui_t *gui, char *sd_path, sdmmc_sto manual_system_maintenance(false); - res = f_write_fast(&fp, buf, NX_EMMC_BLOCKSIZE * num); + res = f_write_fast(&fp, buf, EMMC_BLOCKSIZE * num); manual_system_maintenance(false); @@ -332,7 +334,7 @@ static int _dump_emummc_file_part(emmc_tool_gui_t *gui, char *sd_path, sdmmc_sto lba_curr += num; totalSectors -= num; - bytesWritten += num * NX_EMMC_BLOCKSIZE; + bytesWritten += num * EMMC_BLOCKSIZE; // Force a flush after a lot of data if not splitting. if (numSplitParts == 0 && bytesWritten >= multipartSplitSize) @@ -347,7 +349,7 @@ static int _dump_emummc_file_part(emmc_tool_gui_t *gui, char *sd_path, sdmmc_sto lv_label_set_text(gui->label_pct, " "SYMBOL_DOT" 100%"); manual_system_maintenance(true); - // Backup operation ended successfully. + // Operation ended successfully. f_close(&fp); free(clmt); @@ -360,11 +362,11 @@ void dump_emummc_file(emmc_tool_gui_t *gui) int base_len = 0; u32 timer = 0; - char *txt_buf = (char *)malloc(0x4000); + char *txt_buf = (char *)malloc(SZ_16K); gui->base_path = (char *)malloc(OUT_FILENAME_SZ); gui->txt_buf = txt_buf; - s_printf(txt_buf, ""); + txt_buf[0] = 0; lv_label_set_text(gui->label_log, txt_buf); manual_system_maintenance(true); @@ -378,10 +380,10 @@ void dump_emummc_file(emmc_tool_gui_t *gui) lv_label_set_text(gui->label_info, "Checking for available free space..."); manual_system_maintenance(true); - // Get SD Card free space for Partial Backup. + // Get SD Card free space for file based emuMMC. f_getfree("", &sd_fs.free_clst, NULL); - if (!sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400)) + if (!emmc_initialize(false)) { lv_label_set_text(gui->label_info, "#FFDD00 Failed to init eMMC!#"); goto out; @@ -397,7 +399,7 @@ void dump_emummc_file(emmc_tool_gui_t *gui) for (int j = 0; j < 100; j++) { update_emummc_base_folder(sdPath, base_len, j); - if(f_stat(sdPath, NULL) == FR_NO_FILE) + if (f_stat(sdPath, NULL) == FR_NO_FILE) break; } @@ -408,12 +410,13 @@ void dump_emummc_file(emmc_tool_gui_t *gui) strcpy(gui->base_path, sdPath); timer = get_tmr_s(); - const u32 BOOT_PART_SIZE = emmc_storage.ext_csd.boot_mult << 17; + const u32 BOOT_PART_SECTORS = 0x2000; // Force 4 MiB. emmc_part_t bootPart; memset(&bootPart, 0, sizeof(bootPart)); bootPart.lba_start = 0; - bootPart.lba_end = (BOOT_PART_SIZE / NX_EMMC_BLOCKSIZE) - 1; + bootPart.lba_end = BOOT_PART_SECTORS - 1; + for (i = 0; i < 2; i++) { strcpy(bootPart.name, "BOOT"); @@ -427,7 +430,7 @@ void dump_emummc_file(emmc_tool_gui_t *gui) lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf); manual_system_maintenance(true); - sdmmc_storage_set_mmc_partition(&emmc_storage, i + 1); + emmc_set_partition(i + 1); strcat(sdPath, bootPart.name); res = _dump_emummc_file_part(gui, sdPath, &emmc_storage, &bootPart); @@ -447,7 +450,7 @@ void dump_emummc_file(emmc_tool_gui_t *gui) } // Get GP partition size dynamically. - sdmmc_storage_set_mmc_partition(&emmc_storage, EMMC_GPP); + emmc_set_partition(EMMC_GPP); // Get GP partition size dynamically. const u32 RAW_AREA_NUM_SECTORS = emmc_storage.sec_cnt; @@ -457,28 +460,27 @@ void dump_emummc_file(emmc_tool_gui_t *gui) rawPart.lba_start = 0; rawPart.lba_end = RAW_AREA_NUM_SECTORS - 1; strcpy(rawPart.name, "GPP"); - { - s_printf(txt_buf, "#00DDFF %02d: %s#\n#00DDFF Range: 0x%08X - 0x%08X#\n\n", - i, rawPart.name, rawPart.lba_start, rawPart.lba_end); - lv_label_set_text(gui->label_info, txt_buf); - s_printf(txt_buf, "%02d: %s... ", i, rawPart.name); - lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf); - manual_system_maintenance(true); - res = _dump_emummc_file_part(gui, sdPath, &emmc_storage, &rawPart); + s_printf(txt_buf, "#00DDFF %02d: %s#\n#00DDFF Range: 0x%08X - 0x%08X#\n\n", + i, rawPart.name, rawPart.lba_start, rawPart.lba_end); + lv_label_set_text(gui->label_info, txt_buf); + s_printf(txt_buf, "%02d: %s... ", i, rawPart.name); + lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf); + manual_system_maintenance(true); - if (!res) - s_printf(txt_buf, "#FFDD00 Failed!#\n"); - else - s_printf(txt_buf, "Done!\n"); + res = _dump_emummc_file_part(gui, sdPath, &emmc_storage, &rawPart); - lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf); - manual_system_maintenance(true); - } + if (!res) + s_printf(txt_buf, "#FFDD00 Failed!#\n"); + else + s_printf(txt_buf, "Done!\n"); + + lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf); + manual_system_maintenance(true); out_failed: timer = get_tmr_s() - timer; - sdmmc_storage_end(&emmc_storage); + emmc_end(); if (res) { @@ -504,7 +506,7 @@ out: sd_unmount(); } -static int _dump_emummc_raw_part(emmc_tool_gui_t *gui, int active_part, int part_idx, u32 sd_part_off, sdmmc_storage_t *storage, emmc_part_t *part, u32 resized_count) +static int _dump_emummc_raw_part(emmc_tool_gui_t *gui, int active_part, int part_idx, u32 sd_part_off, emmc_part_t *part, u32 resized_count) { u32 num = 0; u32 pct = 0; @@ -536,8 +538,8 @@ static int _dump_emummc_raw_part(emmc_tool_gui_t *gui, int active_part, int part { // Get USER partition info. LIST_INIT(gpt_parsed); - nx_emmc_gpt_parse(&gpt_parsed, storage); - emmc_part_t *user_part = nx_emmc_part_find(&gpt_parsed, "USER"); + emmc_gpt_parse(&gpt_parsed); + emmc_part_t *user_part = emmc_part_find(&gpt_parsed, "USER"); if (!user_part) { s_printf(gui->txt_buf, "\n#FFDD00 USER partition not found!#\n"); @@ -549,7 +551,7 @@ static int _dump_emummc_raw_part(emmc_tool_gui_t *gui, int active_part, int part user_offset = user_part->lba_start; part->lba_end = user_offset - 1; - nx_emmc_gpt_free(&gpt_parsed); + emmc_gpt_free(&gpt_parsed); } u32 totalSectors = part->lba_end - part->lba_start + 1; @@ -571,7 +573,7 @@ static int _dump_emummc_raw_part(emmc_tool_gui_t *gui, int active_part, int part num = MIN(totalSectors, NUM_SECTORS_PER_ITER); // Read data from eMMC. - while (!sdmmc_storage_read(storage, lba_curr, num, buf)) + while (!sdmmc_storage_read(&emmc_storage, lba_curr, num, buf)) { s_printf(gui->txt_buf, "\n#FFDD00 Error reading %d blocks @LBA %08X,#\n" @@ -662,6 +664,7 @@ static int _dump_emummc_raw_part(emmc_tool_gui_t *gui, int active_part, int part // Calculate USER size and set it for FatFS. u32 user_sectors = resized_count - user_offset - 33; + user_sectors = ALIGN_DOWN(user_sectors, 0x20); // Align down to cluster size. disk_set_info(DRIVE_EMU, SET_SECTOR_COUNT, &user_sectors); // Initialize BIS for emuMMC. BIS keys should be already in place. @@ -676,8 +679,8 @@ static int _dump_emummc_raw_part(emmc_tool_gui_t *gui, int active_part, int part manual_system_maintenance(true); // Format USER partition. - u8 *buff = malloc(0x400000); - int mkfs_error = f_mkfs("emu:", FM_FAT32 | FM_SFD | FM_PRF2, 16384, buff, 0x400000); + u8 *buff = malloc(SZ_4M); + int mkfs_error = f_mkfs("emu:", FM_FAT32 | FM_SFD | FM_PRF2, 16384, buff, SZ_4M); free(buff); // Mount sd card back. @@ -702,11 +705,11 @@ static int _dump_emummc_raw_part(emmc_tool_gui_t *gui, int active_part, int part // Read MBR, GPT and backup GPT. mbr_t mbr; - gpt_t *gpt = calloc(1, sizeof(gpt_t)); + gpt_t *gpt = zalloc(sizeof(gpt_t)); gpt_header_t gpt_hdr_backup; - sdmmc_storage_read(storage, 0, 1, &mbr); - sdmmc_storage_read(storage, 1, sizeof(gpt_t) >> 9, gpt); - sdmmc_storage_read(storage, gpt->header.alt_lba, 1, &gpt_hdr_backup); + sdmmc_storage_read(&emmc_storage, 0, 1, &mbr); + sdmmc_storage_read(&emmc_storage, 1, sizeof(gpt_t) >> 9, gpt); + sdmmc_storage_read(&emmc_storage, gpt->header.alt_lba, 1, &gpt_hdr_backup); // Find USER partition. u32 gpt_entry_idx = 0; @@ -725,7 +728,7 @@ static int _dump_emummc_raw_part(emmc_tool_gui_t *gui, int active_part, int part // Set new emuMMC size and USER size. mbr.partitions[0].size_sct = resized_count; - gpt->entries[gpt_entry_idx].lba_end = user_offset + user_sectors - 1; + gpt->entries[gpt_entry_idx].lba_end = user_part.lba_end; // Update Main GPT. gpt->header.alt_lba = resized_count - 1; @@ -754,7 +757,7 @@ static int _dump_emummc_raw_part(emmc_tool_gui_t *gui, int active_part, int part sdmmc_storage_write(&sd_storage, sd_sector_off, 1, &mbr); // Clear nand patrol. - memset(buf, 0, NX_EMMC_BLOCKSIZE); + memset(buf, 0, EMMC_BLOCKSIZE); sdmmc_storage_write(&sd_storage, sd_part_off + NAND_PATROL_SECTOR, 1, buf); free(gpt); @@ -770,37 +773,37 @@ static int _emummc_raw_derive_bis_keys(emmc_tool_gui_t *gui, u32 resized_count) bool error = false; - char *txt_buf = (char *)malloc(0x4000); + char *txt_buf = (char *)malloc(SZ_16K); txt_buf[0] = 0; // Generate BIS keys. hos_bis_keygen(); - u8 *cal0_buf = malloc(0x10000); + u8 *cal0_buff = malloc(SZ_64K); // Read and decrypt CAL0 for validation of working BIS keys. - sdmmc_storage_set_mmc_partition(&emmc_storage, EMMC_GPP); + emmc_set_partition(EMMC_GPP); LIST_INIT(gpt); - nx_emmc_gpt_parse(&gpt, &emmc_storage); - emmc_part_t *cal0_part = nx_emmc_part_find(&gpt, "PRODINFO"); // check if null + emmc_gpt_parse(&gpt); + emmc_part_t *cal0_part = emmc_part_find(&gpt, "PRODINFO"); // check if null nx_emmc_bis_init(cal0_part, false, 0); - nx_emmc_bis_read(0, 0x40, cal0_buf); + nx_emmc_bis_read(0, 0x40, cal0_buff); nx_emmc_bis_end(); - nx_emmc_gpt_free(&gpt); + emmc_gpt_free(&gpt); - nx_emmc_cal0_t *cal0 = (nx_emmc_cal0_t *)cal0_buf; + nx_emmc_cal0_t *cal0 = (nx_emmc_cal0_t *)cal0_buff; // Check keys validity. if (memcmp(&cal0->magic, "CAL0", 4)) { // Clear EKS keys. - hos_eks_clear(KB_FIRMWARE_VERSION_MAX); + hos_eks_clear(HOS_KB_VERSION_MAX); strcpy(txt_buf, "#FFDD00 BIS keys validation failed!#\n"); error = true; } - free(cal0_buf); + free(cal0_buff); if (error) { @@ -808,7 +811,7 @@ static int _emummc_raw_derive_bis_keys(emmc_tool_gui_t *gui, u32 resized_count) lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char * mbox_btn_map[] = { "\211", "\222Close", "\211", "" }; + static const char * mbox_btn_map[] = { "\251", "\222Close", "\251", "" }; lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); lv_obj_set_width(mbox, LV_HOR_RES / 9 * 5); @@ -842,11 +845,11 @@ void dump_emummc_raw(emmc_tool_gui_t *gui, int part_idx, u32 sector_start, u32 r int res = 0; u32 timer = 0; - char *txt_buf = (char *)malloc(0x4000); + char *txt_buf = (char *)malloc(SZ_16K); gui->base_path = (char *)malloc(OUT_FILENAME_SZ); gui->txt_buf = txt_buf; - s_printf(txt_buf, ""); + txt_buf[0] = 0; lv_label_set_text(gui->label_log, txt_buf); manual_system_maintenance(true); @@ -857,7 +860,7 @@ void dump_emummc_raw(emmc_tool_gui_t *gui, int part_idx, u32 sector_start, u32 r goto out; } - if (!sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400)) + if (!emmc_initialize(false)) { lv_label_set_text(gui->label_info, "#FFDD00 Failed to init eMMC!#"); goto out; @@ -867,7 +870,7 @@ void dump_emummc_raw(emmc_tool_gui_t *gui, int part_idx, u32 sector_start, u32 r { s_printf(gui->txt_buf, "#FFDD00 For formatting USER partition,#\n#FFDD00 BIS keys are needed!#\n"); lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, gui->txt_buf); - sdmmc_storage_end(&emmc_storage); + emmc_end(); goto out; } @@ -881,15 +884,15 @@ void dump_emummc_raw(emmc_tool_gui_t *gui, int part_idx, u32 sector_start, u32 r strcpy(gui->base_path, sdPath); timer = get_tmr_s(); - const u32 BOOT_PART_SIZE = emmc_storage.ext_csd.boot_mult << 17; + const u32 BOOT_PART_SECTORS = 0x2000; // Force 4 MiB. emmc_part_t bootPart; memset(&bootPart, 0, sizeof(bootPart)); bootPart.lba_start = 0; - bootPart.lba_end = (BOOT_PART_SIZE / NX_EMMC_BLOCKSIZE) - 1; + bootPart.lba_end = BOOT_PART_SECTORS - 1; // Clear partition start. - memset((u8 *)MIXD_BUF_ALIGNED, 0, 0x1000000); + memset((u8 *)MIXD_BUF_ALIGNED, 0, SZ_16M); sdmmc_storage_write(&sd_storage, sector_start - 0x8000, 0x8000, (u8 *)MIXD_BUF_ALIGNED); for (i = 0; i < 2; i++) @@ -905,10 +908,10 @@ void dump_emummc_raw(emmc_tool_gui_t *gui, int part_idx, u32 sector_start, u32 r lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf); manual_system_maintenance(true); - sdmmc_storage_set_mmc_partition(&emmc_storage, i + 1); + emmc_set_partition(i + 1); strcat(sdPath, bootPart.name); - res = _dump_emummc_raw_part(gui, i, part_idx, sector_start, &emmc_storage, &bootPart, 0); + res = _dump_emummc_raw_part(gui, i, part_idx, sector_start, &bootPart, 0); if (!res) { @@ -924,7 +927,7 @@ void dump_emummc_raw(emmc_tool_gui_t *gui, int part_idx, u32 sector_start, u32 r strcpy(sdPath, gui->base_path); } - sdmmc_storage_set_mmc_partition(&emmc_storage, EMMC_GPP); + emmc_set_partition(EMMC_GPP); // Get GP partition size dynamically. const u32 RAW_AREA_NUM_SECTORS = emmc_storage.sec_cnt; @@ -942,7 +945,7 @@ void dump_emummc_raw(emmc_tool_gui_t *gui, int part_idx, u32 sector_start, u32 r lv_label_ins_text(gui->label_log, LV_LABEL_POS_LAST, txt_buf); manual_system_maintenance(true); - res = _dump_emummc_raw_part(gui, 2, part_idx, sector_start, &emmc_storage, &rawPart, resized_count); + res = _dump_emummc_raw_part(gui, 2, part_idx, sector_start, &rawPart, resized_count); if (!res) s_printf(txt_buf, "#FFDD00 Failed!#\n"); @@ -955,7 +958,7 @@ void dump_emummc_raw(emmc_tool_gui_t *gui, int part_idx, u32 sector_start, u32 r out_failed: timer = get_tmr_s() - timer; - sdmmc_storage_end(&emmc_storage); + emmc_end(); if (res) { diff --git a/nyx/nyx_gui/frontend/gui.c b/nyx/nyx_gui/frontend/gui.c index ccc089c..47bef3b 100644 --- a/nyx/nyx_gui/frontend/gui.c +++ b/nyx/nyx_gui/frontend/gui.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2025 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,6 +16,8 @@ #include +#include + #include "gui.h" #include "gui_emummc_tools.h" #include "gui_tools.h" @@ -26,30 +28,7 @@ #include "../gfx/logos-gui.h" #include "../config.h" -#include -#include -#include -#include -#include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include extern hekate_config h_cfg; extern nyx_config n_cfg; @@ -59,7 +38,7 @@ extern volatile nyx_storage_t *nyx_str; extern lv_res_t launch_payload(lv_obj_t *list); static bool disp_init_done = false; -static bool do_reload = false; +static bool do_auto_reload = false; lv_style_t hint_small_style; lv_style_t hint_small_style_white; @@ -83,20 +62,13 @@ lv_style_t mbox_darken; char *text_color; -typedef struct _gui_status_bar_ctx -{ - lv_obj_t *mid; - lv_obj_t *time_temp; - lv_obj_t *temp_symbol; - lv_obj_t *temp_degrees; - lv_obj_t *battery; - lv_obj_t *battery_more; -} gui_status_bar_ctx; - typedef struct _jc_lv_driver_t { - lv_indev_t *indev; - bool centering_done; + lv_indev_t *indev_jc; + lv_indev_t *indev_touch; +// LV_INDEV_READ_PERIOD * JC_CAL_MAX_STEPS = 264 ms. +#define JC_CAL_MAX_STEPS 8 + u32 calibration_step; u16 cx_max; u16 cx_min; u16 cy_max; @@ -113,13 +85,34 @@ typedef struct _jc_lv_driver_t static jc_lv_driver_t jc_drv_ctx; -static gui_status_bar_ctx status_bar; +gui_status_bar_ctx status_bar; static void _nyx_disp_init() { + vic_surface_t vic_sfc; + vic_sfc.src_buf = NYX_FB2_ADDRESS; + vic_sfc.dst_buf = NYX_FB_ADDRESS; + vic_sfc.width = 1280; + vic_sfc.height = 720; + vic_sfc.pix_fmt = VIC_PIX_FORMAT_X8R8G8B8; + vic_sfc.rotation = VIC_ROTATION_270; + + // Set hardware rotation via VIC. + vic_init(); + vic_set_surface(&vic_sfc); + + // Turn off backlight to hide the transition. display_backlight_brightness(0, 1000); - display_init_framebuffer_pitch_inv(); - display_init_framebuffer_log(); + + // Rotate and copy the first frame. + vic_compose(); + + // Switch to new window configuration. + display_init_window_a_pitch_vic(); + + // Enable logging on window D. + display_init_window_d_console(); + // Switch back the backlight. display_backlight_brightness(h_cfg.backlight - 20, 1000); } @@ -141,11 +134,11 @@ static void _save_log_to_bmp(char *fname) if (!log_changed) return; - const u32 file_size = 0x334000 + 0x36; + const u32 file_size = LOG_FB_SZ + 0x36; u8 *bitmap = malloc(file_size); - // Reconstruct FB for bottom-top, landscape bmp. - u32 *fb = malloc(0x334000); + // Reconstruct FB for bottom-top, landscape bmp. Rotation: 656x1280 -> 1280x656. + u32 *fb = malloc(LOG_FB_SZ); for (int x = 1279; x > - 1; x--) { for (int y = 655; y > -1; y--) @@ -154,7 +147,7 @@ static void _save_log_to_bmp(char *fname) manual_system_maintenance(true); - memcpy(bitmap + 0x36, fb, 0x334000); + memcpy(bitmap + 0x36, fb, LOG_FB_SZ); typedef struct _bmp_t { @@ -186,7 +179,7 @@ static void _save_log_to_bmp(char *fname) bmp->planes = 1; bmp->pxl_bits = 32; bmp->comp = 0; - bmp->img_size = 0x334000; + bmp->img_size = LOG_FB_SZ; bmp->res_h = 2834; bmp->res_v = 2834; bmp->rsvd2 = 0; @@ -207,19 +200,23 @@ static void _save_fb_to_bmp() if (get_tmr_ms() < timer) return; - if (do_reload) - return; + if (do_auto_reload) + goto exit; - const u32 file_size = 0x384000 + 0x36; + // Invalidate data. + bpmp_mmu_maintenance(BPMP_MMU_MAINT_INVALID_WAY, false); + + const u32 file_size = NYX_FB_SZ + 0x36; u8 *bitmap = malloc(file_size); - u32 *fb = malloc(0x384000); - u32 *fb_ptr = (u32 *)NYX_FB_ADDRESS; + u32 *fb = malloc(NYX_FB_SZ); + u32 *fb_ptr = (u32 *)NYX_FB2_ADDRESS; + u32 line_bytes = 1280 * sizeof(u32); - // Reconstruct FB for bottom-top, landscape bmp. - for (u32 x = 0; x < 1280; x++) + // Reconstruct FB for bottom-top, landscape bmp. No rotation. + for (int y = 719; y > -1; y--) { - for (int y = 719; y > -1; y--) - fb[y * 1280 + x] = *fb_ptr++; + memcpy(&fb[y * 1280], fb_ptr, line_bytes); + fb_ptr += line_bytes / sizeof(u32); } // Create notification box. @@ -237,7 +234,7 @@ static void _save_fb_to_bmp() manual_system_maintenance(true); - memcpy(bitmap + 0x36, fb, 0x384000); + memcpy(bitmap + 0x36, fb, NYX_FB_SZ); typedef struct _bmp_t { @@ -269,7 +266,7 @@ static void _save_fb_to_bmp() bmp->planes = 1; bmp->pxl_bits = 32; bmp->comp = 0; - bmp->img_size = 0x384000; + bmp->img_size = NYX_FB_SZ; bmp->res_h = 2834; bmp->res_v = 2834; bmp->rsvd2 = 0; @@ -286,12 +283,7 @@ static void _save_fb_to_bmp() // Create date/time name. char fname[32]; rtc_time_t time; - max77620_rtc_get_time(&time); - if (n_cfg.timeoff) - { - u32 epoch = max77620_rtc_date_to_epoch(&time) + (s32)n_cfg.timeoff; - max77620_rtc_epoch_to_date(epoch, &time); - } + max77620_rtc_get_time_adjusted(&time); s_printf(fname, "%04d%02d%02d_%02d%02d%02d", time.year, time.month, time.day, time.hour, time.min, time.sec); s_printf(path + strlen(path), "/nyx%s.bmp", fname); @@ -312,14 +304,19 @@ static void _save_fb_to_bmp() manual_system_maintenance(true); lv_mbox_start_auto_close(mbox, 4000); +exit: // Set timer to 2s. timer = get_tmr_ms() + 2000; } static void _disp_fb_flush(int32_t x1, int32_t y1, int32_t x2, int32_t y2, const lv_color_t *color_p) { - // Draw to framebuffer. - gfx_set_rect_land_pitch((u32 *)NYX_FB_ADDRESS, (u32 *)color_p, 720, x1, y1, x2, y2); //pitch + // Draw to intermediate non-rotated framebuffer. + gfx_set_rect_pitch((u32 *)NYX_FB2_ADDRESS, (u32 *)color_p, 1280, x1, y1, x2, y2); + + // Rotate and copy to visible framebuffer. + if (disp_init_done) + vic_compose(); // Check if display init was done. If it's the first big draw, init. if (!disp_init_done && ((x2 - x1 + 1) > 600)) @@ -353,14 +350,15 @@ static bool _fts_touch_read(lv_indev_data_t *data) if (console_enabled) { - gfx_con_getpos(&gfx_con.savedx, &gfx_con.savedy); - gfx_con_setpos(32, 638); + // Print input debugging in console. + gfx_con_getpos(&gfx_con.savedx, &gfx_con.savedy, &gfx_con.savedcol); + gfx_con_setpos(32, 638, GFX_COL_AUTO); gfx_con.fntsz = 8; gfx_printf("x: %4d, y: %4d | z: %3d | ", touchpad.x, touchpad.y, touchpad.z); - gfx_printf("1: %02x, 2: %02x, 3: %02x, ", touchpad.raw[1], touchpad.raw[2], touchpad.raw[3]); - gfx_printf("4: %02X, 5: %02x, 6: %02x, 7: %02x", + gfx_printf("1: %02X, 2: %02X, 3: %02X, ", touchpad.raw[1], touchpad.raw[2], touchpad.raw[3]); + gfx_printf("4: %02X, 5: %02X, 6: %02X, 7: %02X", touchpad.raw[4], touchpad.raw[5], touchpad.raw[6], touchpad.raw[7]); - gfx_con_setpos(gfx_con.savedx, gfx_con.savedy); + gfx_con_setpos(gfx_con.savedx, gfx_con.savedy, gfx_con.savedcol); gfx_con.fntsz = 16; return false; @@ -413,20 +411,35 @@ static bool _jc_virt_mouse_read(lv_indev_data_t *data) } // Calibrate left stick. - if (!jc_drv_ctx.centering_done) + if (jc_drv_ctx.calibration_step != JC_CAL_MAX_STEPS) { - if (jc_pad->conn_l - && jc_pad->lstick_x > 0x400 && jc_pad->lstick_y > 0x400 - && jc_pad->lstick_x < 0xC00 && jc_pad->lstick_y < 0xC00) + if (n_cfg.jc_force_right) { + if (jc_pad->conn_r + && jc_pad->rstick_x > 0x400 && jc_pad->rstick_y > 0x400 + && jc_pad->rstick_x < 0xC00 && jc_pad->rstick_y < 0xC00) + { + jc_drv_ctx.calibration_step++; + jc_drv_ctx.cx_max = jc_pad->rstick_x + 0x96; + jc_drv_ctx.cx_min = jc_pad->rstick_x - 0x96; + jc_drv_ctx.cy_max = jc_pad->rstick_y + 0x96; + jc_drv_ctx.cy_min = jc_pad->rstick_y - 0x96; + jc_drv_ctx.cursor_timeout = 0; + } + } + else if (jc_pad->conn_l + && jc_pad->lstick_x > 0x400 && jc_pad->lstick_y > 0x400 + && jc_pad->lstick_x < 0xC00 && jc_pad->lstick_y < 0xC00) + { + jc_drv_ctx.calibration_step++; jc_drv_ctx.cx_max = jc_pad->lstick_x + 0x96; jc_drv_ctx.cx_min = jc_pad->lstick_x - 0x96; jc_drv_ctx.cy_max = jc_pad->lstick_y + 0x96; jc_drv_ctx.cy_min = jc_pad->lstick_y - 0x96; - jc_drv_ctx.centering_done = true; jc_drv_ctx.cursor_timeout = 0; } - else + + if (jc_drv_ctx.calibration_step != JC_CAL_MAX_STEPS) { data->state = LV_INDEV_STATE_REL; return false; @@ -434,8 +447,10 @@ static bool _jc_virt_mouse_read(lv_indev_data_t *data) } // Re-calibrate on disconnection. - if (!jc_pad->conn_l) - jc_drv_ctx.centering_done = 0; + if (n_cfg.jc_force_right && !jc_pad->conn_r) + jc_drv_ctx.calibration_step = 0; + else if (!n_cfg.jc_force_right && !jc_pad->conn_l) + jc_drv_ctx.calibration_step = 0; // Set button presses. if (jc_pad->a || jc_pad->zl || jc_pad->zr) @@ -450,16 +465,16 @@ static bool _jc_virt_mouse_read(lv_indev_data_t *data) { if (!console_enabled) { - display_activate_console(); + display_window_d_console_enable(); console_enabled = true; - gfx_con_getpos(&gfx_con.savedx, &gfx_con.savedy); - gfx_con_setpos(964, 630); + gfx_con_getpos(&gfx_con.savedx, &gfx_con.savedy, &gfx_con.savedcol); + gfx_con_setpos(964, 630, GFX_COL_AUTO); gfx_printf("Press -/+ to close"); - gfx_con_setpos(gfx_con.savedx, gfx_con.savedy); + gfx_con_setpos(gfx_con.savedx, gfx_con.savedy, gfx_con.savedcol); } else { - display_deactivate_console(); + display_window_d_console_disable(); console_enabled = false; } @@ -472,14 +487,14 @@ static bool _jc_virt_mouse_read(lv_indev_data_t *data) if (console_enabled) { - gfx_con_getpos(&gfx_con.savedx, &gfx_con.savedy); - gfx_con_setpos(32, 630); + // Print input debugging in console. + gfx_con_getpos(&gfx_con.savedx, &gfx_con.savedy, &gfx_con.savedcol); + gfx_con_setpos(32, 630, GFX_COL_AUTO); gfx_con.fntsz = 8; - gfx_printf("x: %4X, y: %4X | b: %06X | bt: %d %0d | cx: %03X - %03x, cy: %03X - %03x", - jc_pad->lstick_x, jc_pad->lstick_y, jc_pad->buttons, - jc_pad->batt_info_l, jc_pad->batt_info_r, - jc_drv_ctx.cx_min, jc_drv_ctx.cx_max, jc_drv_ctx.cy_min, jc_drv_ctx.cy_max); - gfx_con_setpos(gfx_con.savedx, gfx_con.savedy); + gfx_printf("x: %4X, y: %4X | rx: %4X, ry: %4X | b: %06X | bt: %d %d", + jc_pad->lstick_x, jc_pad->lstick_y, jc_pad->rstick_x, jc_pad->rstick_y, + jc_pad->buttons, jc_pad->batt_info_l, jc_pad->batt_info_r); + gfx_con_setpos(gfx_con.savedx, gfx_con.savedy, gfx_con.savedcol); gfx_con.fntsz = 16; data->state = LV_INDEV_STATE_REL; @@ -487,19 +502,66 @@ static bool _jc_virt_mouse_read(lv_indev_data_t *data) } // Calculate new cursor position. - if (jc_pad->lstick_x <= jc_drv_ctx.cx_max && jc_pad->lstick_x >= jc_drv_ctx.cx_min) - jc_drv_ctx.pos_x += 0; - else if (jc_pad->lstick_x > jc_drv_ctx.cx_max) - jc_drv_ctx.pos_x += ((jc_pad->lstick_x - jc_drv_ctx.cx_max) / 30); - else - jc_drv_ctx.pos_x -= ((jc_drv_ctx.cx_min - jc_pad->lstick_x) / 30); + if (!n_cfg.jc_force_right) + { + // Left stick X. + if (jc_pad->lstick_x <= jc_drv_ctx.cx_max && jc_pad->lstick_x >= jc_drv_ctx.cx_min) + jc_drv_ctx.pos_x += 0; + else if (jc_pad->lstick_x > jc_drv_ctx.cx_max) + jc_drv_ctx.pos_x += ((jc_pad->lstick_x - jc_drv_ctx.cx_max) / 30); + else + jc_drv_ctx.pos_x -= ((jc_drv_ctx.cx_min - jc_pad->lstick_x) / 30); - if (jc_pad->lstick_y <= jc_drv_ctx.cy_max && jc_pad->lstick_y >= jc_drv_ctx.cy_min) - jc_drv_ctx.pos_y += 0; - else if (jc_pad->lstick_y > jc_drv_ctx.cy_max) - jc_drv_ctx.pos_y -= ((jc_pad->lstick_y - jc_drv_ctx.cy_max) / 30); + // Left stick Y. + if (jc_pad->lstick_y <= jc_drv_ctx.cy_max && jc_pad->lstick_y >= jc_drv_ctx.cy_min) + jc_drv_ctx.pos_y += 0; + else if (jc_pad->lstick_y > jc_drv_ctx.cy_max) + { + s16 val = (jc_pad->lstick_y - jc_drv_ctx.cy_max) / 30; + // Hoag has inverted Y axis. + if (jc_pad->sio_mode) + val *= -1; + jc_drv_ctx.pos_y -= val; + } + else + { + s16 val = (jc_drv_ctx.cy_min - jc_pad->lstick_y) / 30; + // Hoag has inverted Y axis. + if (jc_pad->sio_mode) + val *= -1; + jc_drv_ctx.pos_y += val; + } + } else - jc_drv_ctx.pos_y += ((jc_drv_ctx.cy_min - jc_pad->lstick_y) / 30); + { + // Right stick X. + if (jc_pad->rstick_x <= jc_drv_ctx.cx_max && jc_pad->rstick_x >= jc_drv_ctx.cx_min) + jc_drv_ctx.pos_x += 0; + else if (jc_pad->rstick_x > jc_drv_ctx.cx_max) + jc_drv_ctx.pos_x += ((jc_pad->rstick_x - jc_drv_ctx.cx_max) / 30); + else + jc_drv_ctx.pos_x -= ((jc_drv_ctx.cx_min - jc_pad->rstick_x) / 30); + + // Right stick Y. + if (jc_pad->rstick_y <= jc_drv_ctx.cy_max && jc_pad->rstick_y >= jc_drv_ctx.cy_min) + jc_drv_ctx.pos_y += 0; + else if (jc_pad->rstick_y > jc_drv_ctx.cy_max) + { + s16 val = (jc_pad->rstick_y - jc_drv_ctx.cy_max) / 30; + // Hoag has inverted Y axis. + if (jc_pad->sio_mode) + val *= -1; + jc_drv_ctx.pos_y -= val; + } + else + { + s16 val = (jc_drv_ctx.cy_min - jc_pad->rstick_y) / 30; + // Hoag has inverted Y axis. + if (jc_pad->sio_mode) + val *= -1; + jc_drv_ctx.pos_y += val; + } + } // Ensure value inside screen limits. if (jc_drv_ctx.pos_x < 0) @@ -524,7 +586,7 @@ static bool _jc_virt_mouse_read(lv_indev_data_t *data) jc_drv_ctx.cursor_hidden = false; jc_drv_ctx.cursor_timeout = get_tmr_ms(); - lv_indev_set_cursor(jc_drv_ctx.indev, jc_drv_ctx.cursor); + lv_indev_set_cursor(jc_drv_ctx.indev_jc, jc_drv_ctx.cursor); // Un hide cursor. lv_obj_set_opa_scale_enable(jc_drv_ctx.cursor, false); @@ -536,7 +598,7 @@ static bool _jc_virt_mouse_read(lv_indev_data_t *data) if (((u32)get_tmr_ms() - jc_drv_ctx.cursor_timeout) > 3000) { // Remove cursor and hide it. - lv_indev_set_cursor(jc_drv_ctx.indev, NULL); + lv_indev_set_cursor(jc_drv_ctx.indev_jc, NULL); lv_obj_set_opa_scale_enable(jc_drv_ctx.cursor, true); lv_obj_set_opa_scale(jc_drv_ctx.cursor, LV_OPA_TRANSP); @@ -577,7 +639,7 @@ void manual_system_maintenance(bool refresh) for (u32 task_idx = 0; task_idx < (sizeof(system_maintenance_tasks_t) / sizeof(lv_task_t *)); task_idx++) { lv_task_t *task = system_tasks.tasks[task_idx]; - if(task && (lv_tick_elaps(task->last_run) >= task->period)) + if (task && (lv_tick_elaps(task->last_run) >= task->period)) { task->last_run = lv_tick_get(); task->task(task->param); @@ -633,7 +695,7 @@ lv_img_dsc_t *bmp_to_lvimg_obj(const char *path) img_desc->header.always_zero = 0; img_desc->header.w = bmpData.size_x; img_desc->header.h = bmpData.size_y; - img_desc->header.cf = (bitmap[28] == 32) ? LV_IMG_CF_TRUE_COLOR_ALPHA : LV_IMG_CF_TRUE_COLOR; + img_desc->header.cf = (bitmap[28] == 32) ? LV_IMG_CF_TRUE_COLOR_ALPHA : LV_IMG_CF_TRUE_COLOR; // Only LV_IMG_CF_TRUE_COLOR_ALPHA is actually allowed. img_desc->data_size = bmpData.size - bmpData.offset; img_desc->data = (u8 *)offset_copy; @@ -733,7 +795,7 @@ bool nyx_emmc_check_battery_enough() lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char * mbox_btn_map[] = { "\211", "\222OK", "\211", "" }; + static const char * mbox_btn_map[] = { "\251", "\222OK", "\251", "" }; lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); @@ -754,21 +816,21 @@ bool nyx_emmc_check_battery_enough() return true; } -static void nyx_sd_card_issues(void *param) +static void _nyx_sd_card_issues_warning(void *param) { lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL); lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char * mbox_btn_map[] = { "\211", "\222OK", "\211", "" }; + static const char * mbox_btn_map[] = { "\251", "\222OK", "\251", "" }; lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); lv_mbox_set_text(mbox, - "#FF8000 SD Card Issues Check#\n\n" + "#FF8000 SD Card Issues Warning#\n\n" "#FFDD00 The SD Card is initialized in 1-bit mode!#\n" "#FFDD00 This might mean detached or broken connector!#\n\n" - "You might want to check\n#C7EA46 Console Info# -> #C7EA46 SD Card#"); + "You might want to check\n#C7EA46 Console Info# -> #C7EA46 microSD#"); lv_mbox_add_btns(mbox, mbox_btn_map, mbox_action); lv_obj_set_width(mbox, LV_HOR_RES / 9 * 5); @@ -805,11 +867,11 @@ void nyx_window_toggle_buttons(lv_obj_t *win, bool disable) } } -lv_res_t lv_win_close_action_custom(lv_obj_t * btn) +lv_res_t nyx_win_close_action_custom(lv_obj_t * btn) { - close_btn = NULL; + close_btn = NULL; - return lv_win_close_action(btn); + return lv_win_close_action(btn); } lv_obj_t *nyx_create_standard_window(const char *win_title) @@ -825,7 +887,7 @@ lv_obj_t *nyx_create_standard_window(const char *win_title) lv_win_set_style(win, LV_WIN_STYLE_BG, &win_bg_style); lv_obj_set_size(win, LV_HOR_RES, LV_VER_RES); - close_btn = lv_win_add_btn(win, NULL, SYMBOL_CLOSE" Close", lv_win_close_action_custom); + close_btn = lv_win_add_btn(win, NULL, SYMBOL_CLOSE" Close", nyx_win_close_action_custom); return win; } @@ -862,13 +924,32 @@ static void _launch_hos(u8 autoboot, u8 autoboot_list) sd_end(); - hw_reinit_workaround(false, 0); + hw_deinit(false, 0); (*main_ptr)(); } -void reload_nyx() +void reload_nyx(lv_obj_t *obj, bool force) { + if (!force) + { + sd_mount(); + + // Check that Nyx still exists. + if (f_stat("bootloader/sys/nyx.bin", NULL)) + { + sd_unmount(); + + // Remove lvgl object in case of being invoked from a window. + if (obj) + lv_obj_del(obj); + + do_auto_reload = false; + + return; + } + } + b_cfg->boot_cfg = BOOT_CFG_AUTOBOOT_EN; b_cfg->autoboot = 0; b_cfg->autoboot_list = 0; @@ -878,10 +959,7 @@ void reload_nyx() sd_end(); - hw_reinit_workaround(false, 0); - - // Some cards (Sandisk U1), do not like a fast power cycle. Wait min 100ms. - sdmmc_storage_init_wait_sd(); + hw_deinit(false, 0); (*main_ptr)(); } @@ -889,7 +967,7 @@ void reload_nyx() static lv_res_t reload_action(lv_obj_t *btns, const char *txt) { if (!lv_btnm_get_pressed(btns)) - reload_nyx(); + reload_nyx(NULL, false); return mbox_action(btns, txt); } @@ -911,7 +989,7 @@ static lv_res_t _removed_sd_action(lv_obj_t *btns, const char *txt) break; case 2: sd_end(); - do_reload = false; + do_auto_reload = false; break; } @@ -920,32 +998,64 @@ static lv_res_t _removed_sd_action(lv_obj_t *btns, const char *txt) static void _check_sd_card_removed(void *params) { + static lv_obj_t *dark_bg = NULL; + // The following checks if SDMMC_1 is initialized. // If yes and card was removed, shows a message box, // that will reload Nyx, when the card is inserted again. - if (!do_reload && sd_get_card_removed()) + if (!do_auto_reload && sd_get_card_removed()) { - lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL); + dark_bg = lv_obj_create(lv_scr_act(), NULL); lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); static const char * mbox_btn_map[] = { "\221Reboot (RCM)", "\221Power Off", "\221Do not reload", "" }; + static const char * mbox_btn_map_rcm_patched[] = { "\221Reboot", "\221Power Off", "\221Do not reload", "" }; lv_obj_t *mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); lv_obj_set_width(mbox, LV_HOR_RES * 6 / 9); - lv_mbox_set_text(mbox, "\n#FF8000 SD card was removed!#\n\n#96FF00 Nyx will reload after inserting it.#\n"); - lv_mbox_add_btns(mbox, mbox_btn_map, _removed_sd_action); + lv_mbox_set_text(mbox, "\n#FF8000 SD card was removed!#\n\n#96FF00 Nyx will reload after inserting it.#\n\nReminder that you can use UMS instead of removing it.\n"); + lv_mbox_add_btns(mbox, h_cfg.rcm_patched ? mbox_btn_map_rcm_patched : mbox_btn_map, _removed_sd_action); lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); lv_obj_set_top(mbox, true); - do_reload = true; + do_auto_reload = true; } // If in reload state and card was inserted, reload nyx. - if (do_reload && !sd_get_card_removed()) - reload_nyx(); + if (do_auto_reload && !sd_get_card_removed()) + reload_nyx(dark_bg, false); +} + +lv_task_t *task_emmc_errors; +static void _nyx_emmc_issues_warning(void *params) +{ + if (emmc_get_mode() < EMMC_MMC_HS400) + { + // Remove task. + lv_task_del(task_emmc_errors); + + lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL); + lv_obj_set_style(dark_bg, &mbox_darken); + lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); + + static const char * mbox_btn_map[] = { "\251", "\222OK", "\251", "" }; + lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); + lv_mbox_set_recolor_text(mbox, true); + + lv_mbox_set_text(mbox, + "#FF8000 eMMC Issues Warning#\n\n" + "#FFDD00 Your eMMC is initialized in a slower mode!#\n" + "#FFDD00 This might mean hardware issues!#\n\n" + "You might want to check\n#C7EA46 Console Info# -> #C7EA46 eMMC#"); + + lv_mbox_add_btns(mbox, mbox_btn_map, mbox_action); + lv_obj_set_width(mbox, LV_HOR_RES / 9 * 5); + lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); + lv_obj_set_top(mbox, true); + } } static lv_res_t _reboot_action(lv_obj_t *btns, const char *txt) @@ -1005,6 +1115,7 @@ static lv_res_t _create_mbox_reboot(lv_obj_t *btn) lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); static const char * mbox_btn_map[] = { "\221OFW", "\221RCM", "\221Cancel", "" }; + static const char * mbox_btn_map_autorcm[] = { "\261OFW", "\221RCM", "\221Cancel", "" }; static const char * mbox_btn_map_patched[] = { "\221OFW", "\221Normal", "\221Cancel", "" }; lv_obj_t *mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); @@ -1012,7 +1123,10 @@ static lv_res_t _create_mbox_reboot(lv_obj_t *btn) lv_mbox_set_text(mbox, "#FF8000 Choose where to reboot:#"); - lv_mbox_add_btns(mbox, h_cfg.rcm_patched ? mbox_btn_map_patched : mbox_btn_map, _reboot_action); + if (h_cfg.rcm_patched) + lv_mbox_add_btns(mbox, mbox_btn_map_patched, _reboot_action); + else + lv_mbox_add_btns(mbox, !h_cfg.autorcm_enabled ? mbox_btn_map : mbox_btn_map_autorcm, _reboot_action); lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); lv_obj_set_top(mbox, true); @@ -1059,7 +1173,7 @@ void nyx_create_onoff_button(lv_theme_t *th, lv_obj_t *parent, lv_obj_t *btn, co btn_onoff_pr_hos_style.body.opa = 35; } else - btn_onoff_pr_hos_style.body.main_color = LV_COLOR_HEX(0x3D3D3D); + btn_onoff_pr_hos_style.body.main_color = LV_COLOR_HEX(theme_bg_color ? (theme_bg_color + 0x101010) : 0x2D2D2D); btn_onoff_pr_hos_style.body.grad_color = btn_onoff_pr_hos_style.body.main_color; btn_onoff_pr_hos_style.text.color = th->btn.pr->text.color; btn_onoff_pr_hos_style.body.empty = 0; @@ -1109,7 +1223,7 @@ static void _create_text_button(lv_theme_t *th, lv_obj_t *parent, lv_obj_t *btn, btn_onoff_pr_hos_style.body.opa = 35; } else - btn_onoff_pr_hos_style.body.main_color = LV_COLOR_HEX(0x3D3D3D); + btn_onoff_pr_hos_style.body.main_color = LV_COLOR_HEX(theme_bg_color ? (theme_bg_color + 0x101010) : 0x2D2D2D); btn_onoff_pr_hos_style.body.grad_color = btn_onoff_pr_hos_style.body.main_color; btn_onoff_pr_hos_style.text.color = th->btn.pr->text.color; btn_onoff_pr_hos_style.body.empty = 0; @@ -1139,10 +1253,10 @@ static void _create_tab_about(lv_theme_t * th, lv_obj_t * parent) lv_label_set_style(lbl_credits, &monospace_text); lv_label_set_recolor(lbl_credits, true); lv_label_set_static_text(lbl_credits, - "#C7EA46 hekate# (c) 2018, #C7EA46 naehrwert#, #C7EA46 st4rk#\n" - " (c) 2018-2021, #C7EA46 CTCaer#\n" + "#C7EA46 hekate# (c) 2018, #C7EA46 naehrwert#, #C7EA46 st4rk#\n" + " (c) 2018-2025, #C7EA46 CTCaer#\n" "\n" - "#C7EA46 Nyx GUI# (c) 2019-2021, #C7EA46 CTCaer#\n" + "#C7EA46 Nyx# (c) 2019-2025, #C7EA46 CTCaer#\n" "\n" "Thanks to: #00CCFF derrek, nedwill, plutoo, #\n" " #00CCFF shuffle2, smea, thexyz, yellows8 #\n" @@ -1150,18 +1264,19 @@ static void _create_tab_about(lv_theme_t * th, lv_obj_t * parent) "Greetings to: fincs, hexkyz, SciresM,\n" " Shiny Quagsire, WinterMute\n" "\n" - "Open source and free packages used:\n\n" + "Open source and free packages used: \n" // Label width alignment padding. + " - Littlev Graphics Library,\n" + " Copyright (c) 2016-2018, Gabor Kiss-Vamosi\n\n" " - FatFs R0.13c,\n" - " Copyright (c) 2018, ChaN\n\n" + " Copyright (c) 2006-2018, ChaN\n" + " Copyright (c) 2018-2022, CTCaer\n\n" " - bcl-1.2.0,\n" " Copyright (c) 2003-2006, Marcus Geelnard\n\n" - " - Atmosphere (Exosphere types/panic, proc id patches),\n" - " Copyright (c) 2018-2019, Atmosphere-NX\n\n" + " - blz,\n" + " Copyright (c) 2018, SciresM\n\n" " - elfload,\n" " Copyright (c) 2014, Owen Shepherd\n" - " Copyright (c) 2018, M4xw\n\n" - " - Littlev Graphics Library,\n" - " Copyright (c) 2016 Gabor Kiss-Vamosi" + " Copyright (c) 2018, M4xw" ); lv_obj_t * lbl_octopus = lv_label_create(parent, NULL); @@ -1199,7 +1314,7 @@ static void _create_tab_about(lv_theme_t * th, lv_obj_t * parent) lv_obj_align(ctcaer_img, lbl_octopus, LV_ALIGN_OUT_BOTTOM_RIGHT, 0, LV_DPI * 2 / 3); char version[32]; - s_printf(version, "Nyx v%d.%d.%d", NYX_VER_MJ, NYX_VER_MN, NYX_VER_HF); + s_printf(version, "Nyx %s%d.%d.%d%c", NYX_VER_RL ? "v" : "", NYX_VER_MJ, NYX_VER_MN, NYX_VER_HF, NYX_VER_RL > 'A' ? NYX_VER_RL : 0); lv_obj_t * lbl_ver = lv_label_create(parent, NULL); lv_obj_align(lbl_ver, ctcaer_img, LV_ALIGN_OUT_BOTTOM_RIGHT, -LV_DPI / 20, LV_DPI / 4); lv_label_set_style(lbl_ver, &monospace_text); @@ -1208,7 +1323,7 @@ static void _create_tab_about(lv_theme_t * th, lv_obj_t * parent) static void _update_status_bar(void *params) { - char *label = (char *)malloc(128); + static char *label = NULL; u16 soc_temp = 0; u32 batt_percent = 0; @@ -1218,26 +1333,19 @@ static void _update_status_bar(void *params) rtc_time_t time; // Get sensor data. - max77620_rtc_get_time(&time); - if (n_cfg.timeoff) - { - u32 epoch = max77620_rtc_date_to_epoch(&time) + (s32)n_cfg.timeoff; - max77620_rtc_epoch_to_date(epoch, &time); - } + max77620_rtc_get_time_adjusted(&time); soc_temp = tmp451_get_soc_temp(false); bq24193_get_property(BQ24193_ChargeStatus, &charge_status); max17050_get_property(MAX17050_RepSOC, (int *)&batt_percent); max17050_get_property(MAX17050_VCELL, &batt_volt); max17050_get_property(MAX17050_Current, &batt_curr); - // Enable fan if more than 46 oC. - u32 soc_temp_dec = (soc_temp >> 8); - if (soc_temp_dec > 51) - set_fan_duty(102); - else if (soc_temp_dec > 46) - set_fan_duty(51); - else if (soc_temp_dec < 40) - set_fan_duty(0); + // Enable fan if more than 41 oC. + u32 soc_temp_dec = soc_temp >> 8; + fan_set_from_temp(soc_temp_dec); + + if (!label) + label = (char *)malloc(512); // Set time and SoC temperature. s_printf(label, "%02d:%02d "SYMBOL_DOT" "SYMBOL_TEMPERATURE" %02d.%d", @@ -1271,10 +1379,7 @@ static void _update_status_bar(void *params) lv_obj_realign(status_bar.battery); // Set battery current draw and voltage. - if (batt_curr >= 0) - s_printf(label, "#96FF00 +%d", batt_curr / 1000); - else - s_printf(label, "#FF3C28 -%d", (~batt_curr + 1) / 1000); + s_printf(label, "#%s%d", batt_curr >= 0 ? "96FF00 +" : "FF3C28 ", batt_curr / 1000); bool voltage_empty = batt_volt < 3200; s_printf(label + strlen(label), " mA# (%s%d mV%s)", @@ -1282,8 +1387,6 @@ static void _update_status_bar(void *params) lv_label_set_text(status_bar.battery_more, label); lv_obj_realign(status_bar.battery_more); - - free(label); } static lv_res_t _create_mbox_payloads(lv_obj_t *btn) @@ -1292,7 +1395,7 @@ static lv_res_t _create_mbox_payloads(lv_obj_t *btn) lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char * mbox_btn_map[] = { "\211", "\222Cancel", "\211", "" }; + static const char * mbox_btn_map[] = { "\251", "\222Cancel", "\251", "" }; lv_obj_t *mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); lv_obj_set_width(mbox, LV_HOR_RES * 5 / 9); @@ -1313,23 +1416,20 @@ static lv_res_t _create_mbox_payloads(lv_obj_t *btn) goto out_end; } - char *dir = (char *)malloc(256); - strcpy(dir, "bootloader/payloads"); - - char *filelist = dirlist(dir, NULL, false, false); + dirlist_t *filelist = dirlist("bootloader/payloads", NULL, false, false); sd_unmount(); u32 i = 0; - if (filelist) { while (true) { - if (!filelist[i * 256]) + if (!filelist->name[i]) break; - lv_list_add(list, NULL, &filelist[i * 256], launch_payload); + lv_list_add(list, NULL, filelist->name[i], launch_payload); i++; } + free(filelist); } out_end: @@ -1342,8 +1442,8 @@ out_end: } typedef struct _launch_menu_entries_t { - lv_obj_t *btn[16]; - lv_obj_t *label[16]; + lv_obj_t *btn[20]; + lv_obj_t *label[20]; } launch_menu_entries_t; static launch_menu_entries_t launch_ctxt; @@ -1362,15 +1462,15 @@ static lv_res_t _launch_more_cfg_action(lv_obj_t *btn) static lv_res_t _win_launch_close_action(lv_obj_t * btn) { // Cleanup icons. - for (u32 i = 0; i < 8; i++) + for (u32 i = 0; i < (n_cfg.entries_5_col ? 10 : 8); i++) { - lv_obj_t *btn = launch_ctxt.btn[i]; - lv_btn_ext_t *ext = lv_obj_get_ext_attr(btn); + lv_obj_t *btns = launch_ctxt.btn[i]; + lv_btn_ext_t *ext = lv_obj_get_ext_attr(btns); if (ext->idx) { // This gets latest object, which is the button overlay. So iterate 2 times. - lv_obj_t * img = lv_obj_get_child(btn, NULL); - img = lv_obj_get_child(btn, img); + lv_obj_t * img = lv_obj_get_child(btns, NULL); + img = lv_obj_get_child(btns, img); lv_img_dsc_t *src = (lv_img_dsc_t *)lv_img_get_src(img); @@ -1474,24 +1574,49 @@ typedef struct _launch_button_pos_t u16 btn_y; u16 lbl_x; u16 lbl_y; - } launch_button_pos_t; -static const launch_button_pos_t launch_button_pos[8] = { +static const launch_button_pos_t launch_button_pos8[8] = { + // First row. { 19, 36, 0, 245 }, { 340, 36, 321, 245 }, { 661, 36, 642, 245 }, { 982, 36, 963, 245 }, + // Second row. { 19, 313, 0, 522 }, { 340, 313, 321, 522 }, { 661, 313, 642, 522 }, { 982, 313, 963, 522 } }; +static const launch_button_pos_t launch_button_pos10[10] = { + // First row. + { 19, 36, 0, 245}, + {260, 36, 241, 245}, + {501, 36, 482, 245}, + {742, 36, 723, 245}, + {983, 36, 964, 245}, + // Second row. + { 19, 313, 0, 522}, + {260, 313, 241, 522}, + {501, 313, 482, 522}, + {742, 313, 723, 522}, + {983, 313, 964, 522} +}; + static lv_res_t _create_window_home_launch(lv_obj_t *btn) { + const u32 max_entries = n_cfg.entries_5_col ? 10 : 8; + const launch_button_pos_t *launch_button_pos = n_cfg.entries_5_col ? launch_button_pos10 : launch_button_pos8; + char *icon_path; + static lv_style_t btn_home_noborder_rel; + lv_style_copy(&btn_home_noborder_rel, lv_theme_get_current()->btn.rel); + btn_home_noborder_rel.body.opa = LV_OPA_0; + btn_home_noborder_rel.body.border.width = 4; + btn_home_noborder_rel.body.border.opa = LV_OPA_0; + static lv_style_t btn_home_transp_rel; lv_style_copy(&btn_home_transp_rel, lv_theme_get_current()->btn.rel); btn_home_transp_rel.body.opa = LV_OPA_0; @@ -1542,14 +1667,12 @@ static lv_res_t _create_window_home_launch(lv_obj_t *btn) lv_cont_set_fit(lv_page_get_scrl(lv_win_get_content(win)), false, false); lv_page_set_scrl_height(lv_win_get_content(win), 572); + lv_btn_ext_t * ext; lv_obj_t *btn_boot_entry; lv_obj_t *boot_entry_lbl_cont; lv_obj_t *boot_entry_label; bool no_boot_entries = false; - u32 max_entries = 8; - lv_btn_ext_t * ext; - // Create CFW buttons. // Buttons are 200 x 200 with 4 pixel borders. // Icons must be <= 192 x 192. @@ -1575,7 +1698,7 @@ static lv_res_t _create_window_home_launch(lv_obj_t *btn) lv_obj_set_style(boot_entry_lbl_cont, &btn_label_home_transp); // Create the rest of the buttons. - for (u32 btn_idx = 1; btn_idx < 8; btn_idx++) + for (u32 btn_idx = 1; btn_idx < (n_cfg.entries_5_col ? 10 : 8); btn_idx++) { btn_boot_entry = lv_btn_create(win, btn_boot_entry); launch_ctxt.btn[btn_idx] = btn_boot_entry; @@ -1587,10 +1710,10 @@ static lv_res_t _create_window_home_launch(lv_obj_t *btn) launch_ctxt.label[btn_idx] = boot_entry_label; } - // Create colorized icon style based on its parrent style. + // Create colorized icon style based on its parent style. static lv_style_t img_style; lv_style_copy(&img_style, &lv_style_plain); - img_style.image.color = lv_color_hsv_to_rgb(n_cfg.themecolor, 100, 100); + img_style.image.color = lv_color_hsv_to_rgb(n_cfg.theme_color, 100, 100); img_style.image.intense = LV_OPA_COVER; // Parse ini boot entries and set buttons/icons. @@ -1598,149 +1721,199 @@ static lv_res_t _create_window_home_launch(lv_obj_t *btn) u32 curr_btn_idx = 0; // Active buttons. LIST_INIT(ini_sections); - if (sd_mount()) + if (!sd_mount()) + goto failed_sd_mount; + + // Check if we use custom system icons. + bool icon_sw_custom = !f_stat("bootloader/res/icon_switch_custom.bmp", NULL); + bool icon_pl_custom = !f_stat("bootloader/res/icon_payload_custom.bmp", NULL); + + // Choose what to parse. + bool ini_parse_success = false; + if (!more_cfg) + ini_parse_success = ini_parse(&ini_sections, "bootloader/hekate_ipl.ini", false); + else + ini_parse_success = ini_parse(&ini_sections, "bootloader/ini", true); + + if (combined_cfg && !ini_parse_success) { - // Check if we use custom system icons. - bool icon_sw_custom = !f_stat("bootloader/res/icon_switch_custom.bmp", NULL); - bool icon_pl_custom = !f_stat("bootloader/res/icon_payload_custom.bmp", NULL); - - // Choose what to parse. - bool ini_parse_success = false; - if (!more_cfg) - ini_parse_success = ini_parse(&ini_sections, "bootloader/hekate_ipl.ini", false); - else - ini_parse_success = ini_parse(&ini_sections, "bootloader/ini", true); - - if (combined_cfg && !ini_parse_success) - { ini_parsing: - // Reinit list. - ini_sections.prev = &ini_sections; - ini_sections.next = &ini_sections; - ini_parse_success = ini_parse(&ini_sections, "bootloader/ini", true); - more_cfg = true; - } - - if (ini_parse_success) - { - // Iterate to all boot entries and load icons. - u32 entry_idx = 1; - - LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sections, link) - { - if (!strcmp(ini_sec->name, "config") || (ini_sec->type != INI_CHOICE)) - continue; - - icon_path = NULL; - bool payload = false; - bool img_colorize = false; - lv_img_dsc_t *bmp = NULL; - lv_obj_t *img = NULL; - - // Check for icons. - LIST_FOREACH_ENTRY(ini_kv_t, kv, &ini_sec->kvs, link) - { - if (!strcmp("icon", kv->key)) - icon_path = kv->val; - else if (!strcmp("payload", kv->key)) - payload = true; - } - - // If icon not found, check res folder for section_name.bmp. - // If not, use defaults. - if (!icon_path) - { - s_printf(tmp_path, "bootloader/res/%s.bmp", ini_sec->name); - bmp = bmp_to_lvimg_obj(tmp_path); - if (!bmp) - { - s_printf(tmp_path, "bootloader/res/%s_hue.bmp", ini_sec->name); - bmp = bmp_to_lvimg_obj(tmp_path); - if (bmp) - img_colorize = true; - } - - if (!bmp && payload) - { - bmp = icon_payload; - - if (!icon_pl_custom) - img_colorize = true; - } - } - else - { - bmp = bmp_to_lvimg_obj(icon_path); - - // Check if colorization is enabled. - if (bmp && strlen(icon_path) > 8 && !memcmp(icon_path + strlen(icon_path) - 8, "_hue", 4)) - img_colorize = true; - } - - // Enable button. - lv_obj_set_opa_scale(launch_ctxt.btn[curr_btn_idx], LV_OPA_COVER); - - // Default to switch logo if no icon found at all. - if (!bmp) - { - bmp = icon_switch; - - if (!icon_sw_custom) - img_colorize = true; - } - - //Set icon. - if (bmp) - { - img = lv_img_create(launch_ctxt.btn[curr_btn_idx], NULL); - - if (img_colorize) - lv_img_set_style(img, &img_style); - - lv_img_set_src(img, bmp); - } - - // Add button mask/radius and align icon. - lv_obj_t *btn = lv_btn_create(launch_ctxt.btn[curr_btn_idx], NULL); - lv_obj_set_size(btn, 200, 200); - lv_btn_set_style(btn, LV_BTN_STYLE_REL, &btn_home_transp_rel); - lv_btn_set_style(btn, LV_BTN_STYLE_PR, &btn_home_transp_pr); - if (img) - lv_obj_align(img, NULL, LV_ALIGN_CENTER, 0, 0); - - // Set autoboot index. - ext = lv_obj_get_ext_attr(btn); - ext->idx = entry_idx; - ext = lv_obj_get_ext_attr(launch_ctxt.btn[curr_btn_idx]); // Redundancy. - ext->idx = entry_idx; - - // Set action. - if (!more_cfg) - lv_btn_set_action(btn, LV_BTN_ACTION_CLICK, _launch_action); - else - lv_btn_set_action(btn, LV_BTN_ACTION_CLICK, _launch_more_cfg_action); - - // Set button's label text. - lv_label_set_text(launch_ctxt.label[curr_btn_idx], ini_sec->name); - lv_obj_set_opa_scale(launch_ctxt.label[curr_btn_idx], LV_OPA_COVER); - - // Set rolling text if name is big. - if (strlen(ini_sec->name) > 22) - lv_label_set_long_mode(launch_ctxt.label[curr_btn_idx], LV_LABEL_LONG_ROLL); - - entry_idx++; - curr_btn_idx++; - - // Check if we exceed max buttons. - if (curr_btn_idx >= max_entries) - break; - } - } - // Reiterate the loop with more cfgs if combined. - if (combined_cfg && (curr_btn_idx < 8) && !more_cfg) - goto ini_parsing; + list_init(&ini_sections); + ini_parse_success = ini_parse(&ini_sections, "bootloader/ini", true); + more_cfg = true; } + if (!ini_parse_success) + goto ini_parse_failed; + + // Iterate to all boot entries and load icons. + u32 entry_idx = 1; + LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sections, link) + { + if (!strcmp(ini_sec->name, "config") || (ini_sec->type != INI_CHOICE)) + continue; + + icon_path = NULL; + bool payload = false; + bool img_colorize = false; + bool img_noborder = false; + lv_img_dsc_t *bmp = NULL; + lv_obj_t *img = NULL; + + // Check for icons. + LIST_FOREACH_ENTRY(ini_kv_t, kv, &ini_sec->kvs, link) + { + if (!strcmp("icon", kv->key)) + icon_path = kv->val; + else if (!strcmp("payload", kv->key)) + payload = true; + } + + // If icon not found, check res folder for section_name.bmp. + // If not, use defaults. + if (!icon_path) + { + s_printf(tmp_path, "bootloader/res/%s.bmp", ini_sec->name); + bmp = bmp_to_lvimg_obj(tmp_path); + if (!bmp) + { + s_printf(tmp_path, "bootloader/res/%s_hue_nobox.bmp", ini_sec->name); + bmp = bmp_to_lvimg_obj(tmp_path); + if (bmp) + { + img_noborder = true; + img_colorize = true; + } + if (!bmp) + { + s_printf(tmp_path, "bootloader/res/%s_hue.bmp", ini_sec->name); + bmp = bmp_to_lvimg_obj(tmp_path); + if (bmp) + img_colorize = true; + } + if (!bmp) + { + s_printf(tmp_path, "bootloader/res/%s_nobox.bmp", ini_sec->name); + bmp = bmp_to_lvimg_obj(tmp_path); + if (bmp) + img_noborder = true; + } + } + + if (!bmp && payload) + { + bmp = icon_payload; + + if (!icon_pl_custom) + img_colorize = true; + } + } + else + { + bmp = bmp_to_lvimg_obj(icon_path); + + // Check if both colorization and border are enabled. + if (bmp && strlen(icon_path) > 14 && !memcmp(icon_path + strlen(icon_path) - 14, "_hue_nobox", 10)) + { + img_colorize = true; + img_noborder = true; + } + else + { + // Check if colorization is enabled. + if (bmp && strlen(icon_path) > 8 && !memcmp(icon_path + strlen(icon_path) - 8, "_hue", 4)) + img_colorize = true; + + // Check if no border is enabled. + if (bmp && strlen(icon_path) > 10 && !memcmp(icon_path + strlen(icon_path) - 10, "_nobox", 6)) + img_noborder = true; + } + } + + // Enable button. + lv_obj_set_opa_scale(launch_ctxt.btn[curr_btn_idx], LV_OPA_COVER); + + // Default to switch logo if no icon found at all. + if (!bmp) + { + bmp = icon_switch; + + if (!icon_sw_custom) + img_colorize = true; + } + + //Set icon. + if (bmp) + { + img = lv_img_create(launch_ctxt.btn[curr_btn_idx], NULL); + + if (img_colorize) + lv_img_set_style(img, &img_style); + + lv_img_set_src(img, bmp); + } + + // Add button mask/radius and align icon. + lv_obj_t *btns = lv_btn_create(launch_ctxt.btn[curr_btn_idx], NULL); + u32 btn_width = 200; + u32 btn_height = 200; + if (img_noborder) + { + btn_width = bmp->header.w + 4; + btn_height = bmp->header.h + 4; + + if (btn_width > 200) + btn_width = 200; + if (btn_height > 200) + btn_height = 200; + + lv_btn_set_style(launch_ctxt.btn[curr_btn_idx], LV_BTN_STYLE_REL, &btn_home_noborder_rel); + lv_btn_set_style(launch_ctxt.btn[curr_btn_idx], LV_BTN_STYLE_PR, &btn_home_noborder_rel); + } + lv_obj_set_size(btns, btn_width, btn_height); + lv_btn_set_style(btns, LV_BTN_STYLE_REL, img_noborder ? &btn_home_noborder_rel : &btn_home_transp_rel); + lv_btn_set_style(btns, LV_BTN_STYLE_PR, &btn_home_transp_pr); + if (img) + lv_obj_align(img, NULL, LV_ALIGN_CENTER, 0, 0); + if (img_noborder) + lv_obj_align(btns, NULL, LV_ALIGN_CENTER, 0, 0); + + // Set autoboot index. + ext = lv_obj_get_ext_attr(btns); + ext->idx = entry_idx; + ext = lv_obj_get_ext_attr(launch_ctxt.btn[curr_btn_idx]); // Redundancy. + ext->idx = entry_idx; + + // Set action. + if (!more_cfg) + lv_btn_set_action(btns, LV_BTN_ACTION_CLICK, _launch_action); + else + lv_btn_set_action(btns, LV_BTN_ACTION_CLICK, _launch_more_cfg_action); + + // Set button's label text. + lv_label_set_text(launch_ctxt.label[curr_btn_idx], ini_sec->name); + lv_obj_set_opa_scale(launch_ctxt.label[curr_btn_idx], LV_OPA_COVER); + + // Set rolling text if name is big. + if (strlen(ini_sec->name) > 22) + lv_label_set_long_mode(launch_ctxt.label[curr_btn_idx], LV_LABEL_LONG_ROLL); + + entry_idx++; + curr_btn_idx++; + + // Check if we exceed max buttons. + if (curr_btn_idx >= max_entries) + break; + } + + ini_free(&ini_sections); + +ini_parse_failed: + // Reiterate the loop with more cfgs if combined. + if (combined_cfg && (curr_btn_idx < (n_cfg.entries_5_col ? 10 : 8)) && !more_cfg) + goto ini_parsing; + +failed_sd_mount: if (curr_btn_idx < 1) no_boot_entries = true; @@ -1845,7 +2018,7 @@ static void _create_tab_home(lv_theme_t *th, lv_obj_t *parent) // lv_btn_set_action(btn_quick_launch, LV_BTN_ACTION_CLICK, NULL); lv_obj_t *btn_nyx_options = lv_btn_create(parent, NULL); - _create_text_button(th, NULL, btn_nyx_options, SYMBOL_SETTINGS" Nyx Options", NULL); + _create_text_button(th, NULL, btn_nyx_options, SYMBOL_SETTINGS" Nyx Settings", NULL); //lv_obj_set_width(btn_nyx_options, 256); lv_btn_set_action(btn_nyx_options, LV_BTN_ACTION_CLICK, create_win_nyx_options); lv_obj_align(btn_nyx_options, NULL, LV_ALIGN_IN_BOTTOM_LEFT, LV_DPI / 4, -LV_DPI / 12); @@ -1901,11 +2074,14 @@ static void _create_tab_home(lv_theme_t *th, lv_obj_t *parent) static lv_res_t _save_options_action(lv_obj_t *btn) { - static const char * mbox_btn_map[] = {"\211", "\222OK!", "\211", ""}; + static const char * mbox_btn_map[] = {"\251", "\222OK!", "\251", ""}; lv_obj_t * mbox = lv_mbox_create(lv_scr_act(), NULL); lv_mbox_set_recolor_text(mbox, true); - int res = !create_config_entry(); + int res = 0; + + if (sd_mount()) + res = !create_config_entry(); if (res) lv_mbox_set_text(mbox, "#FF8000 hekate Configuration#\n\n#96FF00 The configuration was saved to sd card!#"); @@ -1916,6 +2092,8 @@ static lv_res_t _save_options_action(lv_obj_t *btn) nyx_options_clear_ini_changes_made(); + sd_unmount(); + return LV_RES_OK; } @@ -1923,6 +2101,7 @@ static void _create_status_bar(lv_theme_t * th) { static lv_obj_t *status_bar_bg; status_bar_bg = lv_cont_create(lv_layer_top(), NULL); + status_bar.bar_bg = status_bar_bg; static lv_style_t status_bar_style; lv_style_copy(&status_bar_style, &lv_style_plain_color); @@ -1975,9 +2154,9 @@ static void _create_status_bar(lv_theme_t * th) lv_obj_set_size(btn_mid, LV_DPI * 5 / 2, LV_DPI / 2); lv_obj_align(btn_mid, NULL, LV_ALIGN_CENTER, 0, 0); status_bar.mid = btn_mid; - lv_obj_set_opa_scale(status_bar.mid, LV_OPA_0); - lv_obj_set_opa_scale_enable(status_bar.mid, true); - lv_obj_set_click(status_bar.mid, false); + lv_obj_set_opa_scale(btn_mid, LV_OPA_0); + lv_obj_set_opa_scale_enable(btn_mid, true); + lv_obj_set_click(btn_mid, false); lv_btn_set_action(btn_mid, LV_BTN_ACTION_CLICK, _save_options_action); } @@ -2023,6 +2202,7 @@ static lv_res_t _show_hide_save_button(lv_obj_t *tv, uint16_t tab_idx) { if (tab_idx == 4) // Options. { + lv_btn_set_action(status_bar.mid, LV_BTN_ACTION_CLICK, _save_options_action); lv_obj_set_opa_scale(status_bar.mid, LV_OPA_COVER); lv_obj_set_click(status_bar.mid, true); } @@ -2103,17 +2283,20 @@ static void _nyx_set_default_styles(lv_theme_t * th) tabview_btn_tgl_pr.body.grad_color = tabview_btn_tgl_pr.body.main_color; tabview_btn_tgl_pr.body.opa = 35; - lv_color_t tmp_color = lv_color_hsv_to_rgb(n_cfg.themecolor, 100, 100); + lv_color_t tmp_color = lv_color_hsv_to_rgb(n_cfg.theme_color, 100, 100); text_color = malloc(32); - s_printf(text_color, "#%06X", tmp_color.full & 0xFFFFFF); + s_printf(text_color, "#%06X", (u32)(tmp_color.full & 0xFFFFFF)); } lv_task_t *task_bpmp_clock; void first_time_bpmp_clock(void *param) { + // Remove task. + lv_task_del(task_bpmp_clock); + + // Max clock seems fine. Save it. n_cfg.bpmp_clock = 1; create_nyx_config_entry(false); - lv_task_del(task_bpmp_clock); } static void _nyx_main_menu(lv_theme_t * th) @@ -2157,7 +2340,9 @@ static void _nyx_main_menu(lv_theme_t * th) // Add all tabs content. char version[32]; - s_printf(version, "hekate v%d.%d.%d", nyx_str->version & 0xFF, (nyx_str->version >> 8) & 0xFF, (nyx_str->version >> 16) & 0xFF); + char rel = (nyx_str->version >> 24) & 0xFF; + s_printf(version, "hekate %s%d.%d.%d%c", + rel ? "v" : "", nyx_str->version & 0xFF, (nyx_str->version >> 8) & 0xFF, (nyx_str->version >> 16) & 0xFF, rel > 'A' ? rel : 0); lv_obj_t *tab_about = lv_tabview_add_tab(tv, version); lv_obj_t *tab_home = lv_tabview_add_tab(tv, SYMBOL_HOME" Home"); @@ -2192,6 +2377,9 @@ static void _nyx_main_menu(lv_theme_t * th) lv_task_create(_check_sd_card_removed, 2000, LV_TASK_PRIO_LOWEST, NULL); + task_emmc_errors = lv_task_create(_nyx_emmc_issues_warning, 2000, LV_TASK_PRIO_LOWEST, NULL); + lv_task_ready(task_emmc_errors); + // Create top level global line separators. lv_obj_t *line = lv_cont_create(lv_layer_top(), NULL); @@ -2232,7 +2420,7 @@ static void _nyx_main_menu(lv_theme_t * th) } if (!n_cfg.bpmp_clock) - task_bpmp_clock = lv_task_create(first_time_bpmp_clock, 5000, LV_TASK_PRIO_LOWEST, NULL); + task_bpmp_clock = lv_task_create(first_time_bpmp_clock, 10000, LV_TASK_PRIO_LOWEST, NULL); } void nyx_load_and_run() @@ -2259,7 +2447,7 @@ void nyx_load_and_run() indev_drv_jc.type = LV_INDEV_TYPE_POINTER; indev_drv_jc.read = _jc_virt_mouse_read; memset(&jc_drv_ctx, 0, sizeof(jc_lv_driver_t)); - jc_drv_ctx.indev = lv_indev_drv_register(&indev_drv_jc); + jc_drv_ctx.indev_jc = lv_indev_drv_register(&indev_drv_jc); close_btn = NULL; // Initialize touch. @@ -2268,14 +2456,14 @@ void nyx_load_and_run() lv_indev_drv_init(&indev_drv_touch); indev_drv_touch.type = LV_INDEV_TYPE_POINTER; indev_drv_touch.read = _fts_touch_read; - lv_indev_drv_register(&indev_drv_touch); + jc_drv_ctx.indev_touch = lv_indev_drv_register(&indev_drv_touch); touchpad.touch = false; // Initialize temperature sensor. tmp451_init(); // Set hekate theme based on chosen hue. - lv_theme_t *th = lv_theme_hekate_init(n_cfg.themecolor, NULL); + lv_theme_t *th = lv_theme_hekate_init(n_cfg.theme_bg, n_cfg.theme_color, NULL); lv_theme_set_current(th); // Create main menu @@ -2289,16 +2477,19 @@ void nyx_load_and_run() // Check if sd card issues. if (sd_get_mode() == SD_1BIT_HS25) { - lv_task_t *task_run_sd_errors = lv_task_create(nyx_sd_card_issues, LV_TASK_ONESHOT, LV_TASK_PRIO_LOWEST, NULL); + lv_task_t *task_run_sd_errors = lv_task_create(_nyx_sd_card_issues_warning, LV_TASK_ONESHOT, LV_TASK_PRIO_LOWEST, NULL); lv_task_once(task_run_sd_errors); } // Gui loop. if (h_cfg.t210b01) { - // Minerva not supported on T210B01 yet. No power saving. + // Minerva not supported on T210B01 yet. Slight power saving via spinlock. while (true) + { lv_task_handler(); + usleep(400); + } } else { diff --git a/nyx/nyx_gui/frontend/gui.h b/nyx/nyx_gui/frontend/gui.h index 0990113..3f13444 100644 --- a/nyx/nyx_gui/frontend/gui.h +++ b/nyx/nyx_gui/frontend/gui.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2019 CTCaer + * Copyright (c) 2018-2025 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -30,10 +30,21 @@ typedef struct _emmc_tool_gui_t lv_style_t *bar_teal_ind; lv_style_t *bar_white_ind; char *txt_buf; - char *base_path; + char *base_path; bool raw_emummc; } emmc_tool_gui_t; +typedef struct _gui_status_bar_ctx +{ + lv_obj_t *bar_bg; + lv_obj_t *mid; + lv_obj_t *time_temp; + lv_obj_t *temp_symbol; + lv_obj_t *temp_degrees; + lv_obj_t *battery; + lv_obj_t *battery_more; +} gui_status_bar_ctx; + extern lv_style_t hint_small_style; extern lv_style_t hint_small_style_white; extern lv_style_t monospace_text; @@ -56,10 +67,13 @@ extern lv_style_t mbox_darken; extern char *text_color; +extern gui_status_bar_ctx status_bar; + void reload_nyx(); lv_img_dsc_t *bmp_to_lvimg_obj(const char *path); lv_res_t mbox_action(lv_obj_t * btns, const char * txt); bool nyx_emmc_check_battery_enough(); +lv_res_t nyx_win_close_action_custom(lv_obj_t * btn); void nyx_window_toggle_buttons(lv_obj_t *win, bool disable); lv_obj_t *nyx_create_standard_window(const char *win_title); lv_obj_t *nyx_create_window_custom_close_btn(const char *win_title, lv_action_t rel_action); diff --git a/nyx/nyx_gui/frontend/gui_emmc_tools.c b/nyx/nyx_gui/frontend/gui_emmc_tools.c index 749c6ba..9a4df69 100644 --- a/nyx/nyx_gui/frontend/gui_emmc_tools.c +++ b/nyx/nyx_gui/frontend/gui_emmc_tools.c @@ -16,6 +16,8 @@ #include +#include + #include "gui.h" #include "gui_emmc_tools.h" #include "gui_tools.h" @@ -25,21 +27,12 @@ #include "../hos/pkg2.h" #include "../hos/hos.h" #include -#include -#include -#include -#include -#include -#include -#include extern boot_cfg_t b_cfg; extern hekate_config h_cfg; extern char *emmcsn_path_impl(char *path, char *sub_dir, char *filename, sdmmc_storage_t *storage); -lv_obj_t *ums_mbox; - typedef struct _emmc_backup_buttons_t { lv_obj_t *emmc_boot; @@ -162,7 +155,7 @@ static void _create_window_backup_restore(emmcPartType_t type, const char* win_l // Refresh AutoRCM button. if (emmc_btn_ctxt.restore && (type == PART_BOOT) && !emmc_btn_ctxt.raw_emummc) { - if (get_autorcm_status(false)) + if (get_set_autorcm_status(false)) lv_btn_set_state(autorcm_btn, LV_BTN_STATE_TGL_REL); else lv_btn_set_state(autorcm_btn, LV_BTN_STATE_REL); diff --git a/nyx/nyx_gui/frontend/gui_emummc_tools.c b/nyx/nyx_gui/frontend/gui_emummc_tools.c index 3bdeab0..4182b22 100644 --- a/nyx/nyx_gui/frontend/gui_emummc_tools.c +++ b/nyx/nyx_gui/frontend/gui_emummc_tools.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021 CTCaer + * Copyright (c) 2019-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,21 +16,12 @@ #include +#include + #include "gui.h" #include "fe_emummc_tools.h" #include "gui_tools_partition_manager.h" -#include -#include #include -#include -#include -#include "../storage/nx_emmc_bis.h" -#include -#include -#include -#include -#include -#include extern char *emmcsn_path_impl(char *path, char *sub_dir, char *filename, sdmmc_storage_t *storage); @@ -44,15 +35,14 @@ typedef struct _mbr_ctxt_t u32 sector_start; } mbr_ctxt_t; +static bool emummc_backup; static mbr_ctxt_t mbr_ctx; - static lv_obj_t *emummc_manage_window; static lv_res_t (*emummc_tools)(lv_obj_t *btn); static lv_res_t _action_emummc_window_close(lv_obj_t *btn) { - lv_win_close_action(btn); - close_btn = NULL; + nyx_win_close_action_custom(btn); // Delete and relaunch main emuMMC window. lv_obj_del(emummc_manage_window); @@ -217,7 +207,7 @@ static void _create_mbox_emummc_raw() lv_mbox_set_recolor_text(mbox, true); lv_obj_set_width(mbox, LV_HOR_RES / 9 * 6); - char *txt_buf = (char *)malloc(0x4000); + char *txt_buf = (char *)malloc(SZ_16K); mbr_t *mbr = (mbr_t *)malloc(sizeof(mbr_t)); memset(&mbr_ctx, 0, sizeof(mbr_ctxt_t)); @@ -226,11 +216,11 @@ static void _create_mbox_emummc_raw() sdmmc_storage_read(&sd_storage, 0, 1, mbr); sd_unmount(); - sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400); + emmc_initialize(false); u32 emmc_size_safe = emmc_storage.sec_cnt + 0xC000; // eMMC GPP size + BOOT0/1. - sdmmc_storage_end(&emmc_storage); + emmc_end(); for (int i = 1; i < 4; i++) { @@ -397,7 +387,7 @@ static void _create_emummc_migrated_mbox() lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char *mbox_btn_map[] = { "\211", "OK", "\211", "" }; + static const char *mbox_btn_map[] = { "\251", "OK", "\251", "" }; lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); lv_obj_set_width(mbox, LV_HOR_RES / 9 * 4); @@ -512,7 +502,7 @@ static void _migrate_sd_backup_file_based() for (int j = 0; j < 100; j++) { update_emummc_base_folder(emu_path, base_len, j); - if(f_stat(emu_path, NULL) == FR_NO_FILE) + if (f_stat(emu_path, NULL) == FR_NO_FILE) break; } base_len = strlen(emu_path); @@ -522,24 +512,31 @@ static void _migrate_sd_backup_file_based() f_mkdir(emu_path); FIL fp; + // Create file based flag. strcpy(emu_path + base_len, "/file_based"); f_open(&fp, "emuMMC/BK00/file_based", FA_CREATE_ALWAYS | FA_WRITE); f_close(&fp); - emmcsn_path_impl(backup_path, "", "", NULL); + if (!emummc_backup) + emmcsn_path_impl(backup_path, "", "", NULL); + else + emmcsn_path_impl(backup_path, "/emummc", "", NULL); + // Move BOOT0. s_printf(backup_file_path, "%s/BOOT0", backup_path); strcpy(emu_path + base_len, "/eMMC/BOOT0"); f_rename(backup_file_path, emu_path); + // Move BOOT1. s_printf(backup_file_path, "%s/BOOT1", backup_path); strcpy(emu_path + base_len, "/eMMC/BOOT1"); f_rename(backup_file_path, emu_path); + // Move raw GPP. bool multipart = false; s_printf(backup_file_path, "%s/rawnand.bin", backup_path); - if(f_stat(backup_file_path, NULL)) + if (f_stat(backup_file_path, NULL)) multipart = true; if (!multipart) @@ -685,18 +682,23 @@ static lv_res_t _create_emummc_migrate_action(lv_obj_t * btns, const char * txt) static const char *mbox_btn_map[] = { "\222Continue", "\222Cancel", "" }; static const char *mbox_btn_map1[] = { "\222SD File", "\222SD Partition", "\222Cancel", "" }; - static const char *mbox_btn_map3[] = { "\211", "OK", "\211", "" }; + static const char *mbox_btn_map3[] = { "\251", "OK", "\251", "" }; lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); lv_obj_set_width(mbox, LV_HOR_RES / 9 * 6); - char *txt_buf = (char *)malloc(0x4000); + char *txt_buf = (char *)malloc(SZ_16K); if (backup) { - s_printf(txt_buf, - "#C7EA46 Found suitable backup for emuMMC!#\n\n" - "#FF8000 Do you want to migrate it?#\n"); + if (!emummc_backup) + s_printf(txt_buf, + "#C7EA46 Found suitable eMMC backup!#\n\n" + "#FF8000 Do you want to migrate it?#\n"); + else + s_printf(txt_buf, + "#C7EA46 Found suitable emuMMC backup!#\n\n" + "#FF8000 Do you want to migrate it?#\n"); lv_mbox_add_btns(mbox, mbox_btn_map, _create_emummc_mig4_action); } else if (emummc) @@ -746,7 +748,7 @@ static lv_res_t _create_emummc_migrate_action(lv_obj_t * btns, const char * txt) typedef struct _emummc_images_t { - char *dirlist; + dirlist_t *dirlist; u32 part_sector[3]; u32 part_type[3]; u32 part_end[3]; @@ -777,7 +779,7 @@ static lv_res_t _create_mbox_emummc_migrate(lv_obj_t *btn) sd_mount(); sdmmc_storage_read(&sd_storage, 0, 1, mbr); - sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400); + emmc_initialize(false); em_raw = false; em_file = false; @@ -788,29 +790,31 @@ static lv_res_t _create_mbox_emummc_migrate(lv_obj_t *btn) mbr_ctx.sector_start = 0; mbr_ctx.part_idx = 0; + // Try to find a partition based emuMMC. for (int i = 1; i < 4; i++) { mbr_ctx.sector_start = mbr->partitions[i].start_sct; - if (mbr_ctx.sector_start) + + if (!mbr_ctx.sector_start) + continue; + + sdmmc_storage_read(&sd_storage, mbr_ctx.sector_start + 0xC001, 1, efi_part); + if (!memcmp(efi_part, "EFI PART", 8)) { - sdmmc_storage_read(&sd_storage, mbr_ctx.sector_start + 0xC001, 1, efi_part); + mbr_ctx.sector_start += 0x8000; + emummc = true; + mbr_ctx.part_idx = i; + break; + } + else + { + sdmmc_storage_read(&sd_storage, mbr_ctx.sector_start + 0x4001, 1, efi_part); if (!memcmp(efi_part, "EFI PART", 8)) { - mbr_ctx.sector_start += 0x8000; emummc = true; mbr_ctx.part_idx = i; break; } - else - { - sdmmc_storage_read(&sd_storage, mbr_ctx.sector_start + 0x4001, 1, efi_part); - if (!memcmp(efi_part, "EFI PART", 8)) - { - emummc = true; - mbr_ctx.part_idx = i; - break; - } - } } } @@ -823,25 +827,47 @@ static lv_res_t _create_mbox_emummc_migrate(lv_obj_t *btn) s_printf(path_buf, "%c%c%c%c%s", 's', 'x', 'o','s', "/emunand/boot0.bin"); - if(!f_stat(path_buf, NULL)) + if (!f_stat(path_buf, NULL)) em_file = true; + emummc_backup = false; + emmcsn_path_impl(path_buf, "", "BOOT0", &emmc_storage); - if(!f_stat(path_buf, NULL)) + if (!f_stat(path_buf, NULL)) backup = true; emmcsn_path_impl(path_buf, "", "rawnand.bin", &emmc_storage); - if(!f_stat(path_buf, NULL)) + if (!f_stat(path_buf, NULL)) rawnand_backup = true; emmcsn_path_impl(path_buf, "", "rawnand.bin.00", &emmc_storage); - if(!f_stat(path_buf, NULL)) + if (!f_stat(path_buf, NULL)) rawnand_backup = true; backup = backup && rawnand_backup; + if (!backup) + { + rawnand_backup = false; + emummc_backup = true; + + emmcsn_path_impl(path_buf, "/emummc", "BOOT0", &emmc_storage); + if (!f_stat(path_buf, NULL)) + backup = true; + + emmcsn_path_impl(path_buf, "/emummc", "rawnand.bin", &emmc_storage); + if (!f_stat(path_buf, NULL)) + rawnand_backup = true; + + emmcsn_path_impl(path_buf, "/emummc", "rawnand.bin.00", &emmc_storage); + if (!f_stat(path_buf, NULL)) + rawnand_backup = true; + + backup = backup && rawnand_backup; + } + sd_unmount(); - sdmmc_storage_end(&emmc_storage); + emmc_end(); // Check available types and enable the corresponding buttons. if (backup) @@ -892,7 +918,7 @@ static void _create_emummc_saved_mbox() lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char *mbox_btn_map[] = { "\211", "OK", "\211", "" }; + static const char *mbox_btn_map[] = { "\251", "OK", "\251", "" }; lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); lv_obj_set_width(mbox, LV_HOR_RES / 9 * 4); @@ -982,11 +1008,11 @@ static lv_res_t _create_change_emummc_window(lv_obj_t *btn_caller) FIL fp; // Check for sd raw partitions, based on the folders in /emuMMC. - while (emummc_img->dirlist[emummc_idx * 256]) + while (emummc_img->dirlist->name[emummc_idx]) { - s_printf(path, "emuMMC/%s/raw_based", &emummc_img->dirlist[emummc_idx * 256]); + s_printf(path, "emuMMC/%s/raw_based", emummc_img->dirlist->name[emummc_idx]); - if(!f_stat(path, NULL)) + if (!f_stat(path, NULL)) { f_open(&fp, path, FA_READ); u32 curr_list_sector = 0; @@ -997,21 +1023,21 @@ static lv_res_t _create_change_emummc_window(lv_obj_t *btn_caller) if ((curr_list_sector == 2) || (emummc_img->part_sector[0] && curr_list_sector >= emummc_img->part_sector[0] && curr_list_sector < emummc_img->part_end[0] && emummc_img->part_type[0] != 0x83)) { - s_printf(&emummc_img->part_path[0], "emuMMC/%s", &emummc_img->dirlist[emummc_idx * 256]); + s_printf(&emummc_img->part_path[0], "emuMMC/%s", emummc_img->dirlist->name[emummc_idx]); emummc_img->part_sector[0] = curr_list_sector; emummc_img->part_end[0] = 0; } else if (emummc_img->part_sector[1] && curr_list_sector >= emummc_img->part_sector[1] && curr_list_sector < emummc_img->part_end[1] && emummc_img->part_type[1] != 0x83) { - s_printf(&emummc_img->part_path[1 * 128], "emuMMC/%s", &emummc_img->dirlist[emummc_idx * 256]); + s_printf(&emummc_img->part_path[1 * 128], "emuMMC/%s", emummc_img->dirlist->name[emummc_idx]); emummc_img->part_sector[1] = curr_list_sector; emummc_img->part_end[1] = 0; } else if (emummc_img->part_sector[2] && curr_list_sector >= emummc_img->part_sector[2] && curr_list_sector < emummc_img->part_end[2] && emummc_img->part_type[2] != 0x83) { - s_printf(&emummc_img->part_path[2 * 128], "emuMMC/%s", &emummc_img->dirlist[emummc_idx * 256]); + s_printf(&emummc_img->part_path[2 * 128], "emuMMC/%s", emummc_img->dirlist->name[emummc_idx]); emummc_img->part_sector[2] = curr_list_sector; emummc_img->part_end[2] = 0; } @@ -1023,19 +1049,19 @@ static lv_res_t _create_change_emummc_window(lv_obj_t *btn_caller) u32 file_based_idx = 0; // Sanitize the directory list with sd file based ones. - while (emummc_img->dirlist[emummc_idx * 256]) + while (emummc_img->dirlist->name[emummc_idx]) { - s_printf(path, "emuMMC/%s/file_based", &emummc_img->dirlist[emummc_idx * 256]); + s_printf(path, "emuMMC/%s/file_based", emummc_img->dirlist->name[emummc_idx]); - if(!f_stat(path, NULL)) + if (!f_stat(path, NULL)) { - char *tmp = &emummc_img->dirlist[emummc_idx * 256]; - memcpy(&emummc_img->dirlist[file_based_idx * 256], tmp, strlen(tmp) + 1); + char *tmp = emummc_img->dirlist->name[emummc_idx]; + memcpy(emummc_img->dirlist->name[file_based_idx], tmp, strlen(tmp) + 1); file_based_idx++; } emummc_idx++; } - emummc_img->dirlist[file_based_idx * 256] = 0; + emummc_img->dirlist->name[file_based_idx] = NULL; out0:; static lv_style_t h_style; @@ -1070,7 +1096,7 @@ out0:; lv_btn_ext_t *ext; lv_obj_t *btn_label = NULL; lv_obj_t *lv_desc = NULL; - char *txt_buf = malloc(0x4000); + char *txt_buf = malloc(SZ_16K); // Create RAW buttons. for (u32 raw_btn_idx = 0; raw_btn_idx < 3; raw_btn_idx++) @@ -1117,6 +1143,7 @@ out0:; lv_label_set_text(lv_desc, txt_buf); lv_obj_align(lv_desc, btn, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 5); } + free(txt_buf); // Create SD File Based container. lv_obj_t *h2 = lv_cont_create(win, NULL); @@ -1151,9 +1178,9 @@ out0:; emummc_idx = 0; // Add file based to the list. - while (emummc_img->dirlist[emummc_idx * 256]) + while (emummc_img->dirlist->name[emummc_idx]) { - s_printf(path, "emuMMC/%s", &emummc_img->dirlist[emummc_idx * 256]); + s_printf(path, "emuMMC/%s", emummc_img->dirlist->name[emummc_idx]); lv_list_add(list_sd_based, NULL, path, _save_file_emummc_cfg_action); @@ -1218,7 +1245,7 @@ lv_res_t create_win_emummc_tools(lv_obj_t *btn) lv_obj_t *label_txt2 = lv_label_create(h1, NULL); lv_label_set_recolor(label_txt2, true); - char *txt_buf = (char *)malloc(0x4000); + char *txt_buf = (char *)malloc(SZ_16K); if (emu_info.enabled) { @@ -1236,6 +1263,10 @@ lv_res_t create_win_emummc_tools(lv_obj_t *btn) lv_label_set_static_text(label_txt2, "emuMMC is disabled and eMMC will be used for boot.\n\n"); } + if (emu_info.path) + free(emu_info.path); + if (emu_info.nintendo_path) + free(emu_info.nintendo_path); free(txt_buf); lv_obj_set_style(label_txt2, &hint_small_style); diff --git a/nyx/nyx_gui/frontend/gui_info.c b/nyx/nyx_gui/frontend/gui_info.c index 718408f..d7351ab 100644 --- a/nyx/nyx_gui/frontend/gui_info.c +++ b/nyx/nyx_gui/frontend/gui_info.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2025 CTCaer * Copyright (c) 2018 balika011 * * This program is free software; you can redistribute it and/or modify it @@ -16,36 +16,15 @@ * along with this program. If not, see . */ +#include + #include "gui.h" -#include #include "../config.h" #include "../hos/hos.h" #include "../hos/pkg1.h" #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../storage/nx_emmc_bis.h" -#include -#include -#include -#include -#include + +#include #define SECTORS_TO_MIB_COEFF 11 @@ -56,20 +35,18 @@ extern volatile nyx_storage_t *nyx_str; extern lv_res_t launch_payload(lv_obj_t *list); extern char *emmcsn_path_impl(char *path, char *sub_dir, char *filename, sdmmc_storage_t *storage); -static u8 *cal0_buf = NULL; - static lv_res_t _create_window_dump_done(int error, char *dump_filenames) { lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL); lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char * mbox_btn_map[] = { "\211", "\222OK", "\211", "" }; + static const char * mbox_btn_map[] = { "\251", "\222OK", "\251", "" }; lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); lv_obj_set_width(mbox, LV_HOR_RES / 9 * 5); - char *txt_buf = (char *)malloc(0x1000); + char *txt_buf = (char *)malloc(SZ_4K); if (error) s_printf(txt_buf, "#FFDD00 Failed to dump to# %s#FFDD00 !#\nError: %d", dump_filenames, error); @@ -79,6 +56,7 @@ static lv_res_t _create_window_dump_done(int error, char *dump_filenames) s_printf(txt_buf, "Dumping to SD card finished!\nFiles: #C7EA46 backup/%s/dumps/#\n%s", sn, dump_filenames); } lv_mbox_set_text(mbox, txt_buf); + free(txt_buf); lv_mbox_add_btns(mbox, mbox_btn_map, mbox_action); // Important. After set_text. @@ -102,7 +80,7 @@ static lv_res_t _cal0_dump_window_action(lv_obj_t *btns, const char * txt) { char path[64]; emmcsn_path_impl(path, "/dumps", "cal0.bin", NULL); - error = sd_save_to_file((u8 *)cal0_buf, 0x8000, path); + error = sd_save_to_file((u8 *)cal0_buf, SZ_32K, path); sd_unmount(); } @@ -121,25 +99,9 @@ static lv_res_t _battery_dump_window_action(lv_obj_t * btn) if (!error) { char path[64]; - u8 *buf = (u8 *)malloc(0x100 * 2); + void *buf = malloc(0x100 * 2); - // Unlock model table. - u16 unlock = 0x59; - i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_MODELEnable1, (u8 *)&unlock, 2); - unlock = 0xC4; - i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_MODELEnable2, (u8 *)&unlock, 2); - - // Dump all battery fuel gauge registers. - for (int i = 0; i < 0x200; i += 2) - { - i2c_recv_buf_small(buf + i, 2, I2C_1, MAXIM17050_I2C_ADDR, i >> 1); - msleep(1); - } - - // Lock model table. - unlock = 0; - i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_MODELEnable1, (u8 *)&unlock, 2); - i2c_send_buf_small(I2C_1, MAXIM17050_I2C_ADDR, MAX17050_MODELEnable2, (u8 *)&unlock, 2); + max17050_dump_regs(buf); emmcsn_path_impl(path, "/dumps", "fuel_gauge.bin", NULL); error = sd_save_to_file((u8 *)buf, 0x200, path); @@ -172,20 +134,20 @@ static lv_res_t _bootrom_dump_window_action(lv_obj_t * btn) error = 255; emmcsn_path_impl(path, "/dumps", "bootrom_patched.bin", NULL); - int res = sd_save_to_file((u8 *)BOOTROM_BASE, BOOTROM_SIZE, path); + int res = sd_save_to_file((u8 *)IROM_BASE, BOOTROM_SIZE, path); if (!error) error = res; - u32 ipatch_backup[14]; - memcpy(ipatch_backup, (void *)IPATCH_BASE, sizeof(ipatch_backup)); - memset((void*)IPATCH_BASE, 0, sizeof(ipatch_backup)); + u32 ipatch_cam[IPATCH_CAM_ENTRIES + 1]; + memcpy(ipatch_cam, (void *)IPATCH_BASE, sizeof(ipatch_cam)); + memset((void*)IPATCH_BASE, 0, sizeof(ipatch_cam)); // Zeroing valid entries is enough but zero everything. emmcsn_path_impl(path, "/dumps", "bootrom_unpatched.bin", NULL); - res = sd_save_to_file((u8 *)BOOTROM_BASE, BOOTROM_SIZE, path); + res = sd_save_to_file((u8 *)IROM_BASE, BOOTROM_SIZE, path); if (!error) error = res; - memcpy((void*)IPATCH_BASE, ipatch_backup, sizeof(ipatch_backup)); + memcpy((void*)IPATCH_BASE, ipatch_cam, sizeof(ipatch_cam)); sd_unmount(); } @@ -196,7 +158,7 @@ static lv_res_t _bootrom_dump_window_action(lv_obj_t * btn) static lv_res_t _fuse_dump_window_action(lv_obj_t * btn) { - const u32 fuse_array_size = (h_cfg.t210b01 ? 256 : 192) * sizeof(u32); + const u32 fuse_array_size = (h_cfg.t210b01 ? FUSE_ARRAY_WORDS_NUM_B01 : FUSE_ARRAY_WORDS_NUM) * sizeof(u32); int error = !sd_mount(); if (!error) @@ -216,7 +178,7 @@ static lv_res_t _fuse_dump_window_action(lv_obj_t * btn) error = sd_save_to_file((u8 *)0x7000F900, 0x300, path); } - u32 words[256]; + u32 words[FUSE_ARRAY_WORDS_NUM_B01]; fuse_read_array(words); if (!h_cfg.t210b01) emmcsn_path_impl(path, "/dumps", "fuse_array_raw_t210.bin", NULL); @@ -232,7 +194,7 @@ static lv_res_t _fuse_dump_window_action(lv_obj_t * btn) if (!h_cfg.t210b01) _create_window_dump_done(error, "fuse_cached_t210.bin, fuse_array_raw_t210.bin"); else - _create_window_dump_done(error, "fuse_cached_t210b01_partX.bin, fuse_array_raw_t210b01.bin"); + _create_window_dump_done(error, "fuse_cached_t210b01_x*.bin, fuse_array_raw_t210b01.bin"); return LV_RES_OK; } @@ -265,66 +227,42 @@ static lv_res_t _create_mbox_cal0(lv_obj_t *btn) lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char * mbox_btn_map[] = { "\211", "\222Dump", "\222Close", "\211", "" }; + static const char * mbox_btn_map[] = { "\251", "\222Dump", "\222Close", "\251", "" }; lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); lv_obj_set_width(mbox, LV_HOR_RES / 9 * 5); lv_mbox_set_text(mbox, "#C7EA46 CAL0 Info#"); - char *txt_buf = (char *)malloc(0x4000); + char *txt_buf = (char *)malloc(SZ_16K); txt_buf[0] = 0; lv_obj_t * lb_desc = lv_label_create(mbox, NULL); lv_label_set_long_mode(lb_desc, LV_LABEL_LONG_BREAK); lv_label_set_recolor(lb_desc, true); lv_label_set_style(lb_desc, &monospace_text); - lv_obj_set_width(lb_desc, LV_HOR_RES / 9 * 3); + lv_obj_set_width(lb_desc, LV_HOR_RES / 9 * 4); sd_mount(); - // Init eMMC. - if (!sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400)) + // Dump CAL0. + int cal0_res = hos_dump_cal0(); + + // Check result. Don't error if hash doesn't match. + if (cal0_res == 1) { lv_label_set_text(lb_desc, "#FFDD00 Failed to init eMMC!#"); goto out; } - - // Generate BIS keys - hos_bis_keygen(); - - if (!cal0_buf) - cal0_buf = malloc(0x10000); - - // Read and decrypt CAL0. - sdmmc_storage_set_mmc_partition(&emmc_storage, EMMC_GPP); - LIST_INIT(gpt); - nx_emmc_gpt_parse(&gpt, &emmc_storage); - emmc_part_t *cal0_part = nx_emmc_part_find(&gpt, "PRODINFO"); // check if null - nx_emmc_bis_init(cal0_part, false, 0); - nx_emmc_bis_read(0, 0x40, cal0_buf); - nx_emmc_bis_end(); - nx_emmc_gpt_free(&gpt); - - // Clear BIS keys slots. - hos_bis_keys_clear(); - - nx_emmc_cal0_t *cal0 = (nx_emmc_cal0_t *)cal0_buf; - - // Check keys validity. - if (memcmp(&cal0->magic, "CAL0", 4)) + else if (cal0_res == 2) { - free(cal0_buf); - cal0_buf = NULL; - - // Clear EKS keys. - hos_eks_clear(KB_FIRMWARE_VERSION_MAX); - lv_label_set_text(lb_desc, "#FFDD00 CAL0 is corrupt or wrong keys!#\n"); goto out; } + nx_emmc_cal0_t *cal0 = (nx_emmc_cal0_t *)cal0_buf; + u32 hash[8]; se_calc_sha256_oneshot(hash, (u8 *)cal0 + 0x40, cal0->body_size); @@ -334,14 +272,14 @@ static lv_res_t _create_mbox_cal0(lv_obj_t *btn) "#FF8000 Serial Number:# %s\n" "#FF8000 WLAN MAC:# %02X:%02X:%02X:%02X:%02X:%02X\n" "#FF8000 Bluetooth MAC:# %02X:%02X:%02X:%02X:%02X:%02X\n" - "#FF8000 Battery LOT:# %s\n" + "#FF8000 Battery LOT:# %s (%d)\n" "#FF8000 LCD Vendor:# ", cal0->version, cal0->update_cnt, cal0->serial_number, cal0->wlan_mac[0], cal0->wlan_mac[1], cal0->wlan_mac[2], cal0->wlan_mac[3], cal0->wlan_mac[4], cal0->wlan_mac[5], cal0->bd_mac[0], cal0->bd_mac[1], cal0->bd_mac[2], cal0->bd_mac[3], cal0->bd_mac[4], cal0->bd_mac[5], - cal0->battery_lot); + cal0->battery_lot, cal0->battery_ver); - u8 display_rev = (cal0->lcd_vendor >> 8) & 0xFF; + // Prepare display info. u32 display_id = (cal0->lcd_vendor & 0xFF) << 8 | (cal0->lcd_vendor & 0xFF0000) >> 16; switch (display_id) { @@ -352,43 +290,22 @@ static lv_res_t _create_mbox_cal0(lv_obj_t *btn) strcat(txt_buf, "JDI LPM062M326A"); break; case PANEL_INL_P062CCA_AZ1: - strcat(txt_buf, "InnoLux P062CCA-AZ"); - switch (display_rev) - { - case 0x93: - strcat(txt_buf, "1"); - break; - case 0x95: - strcat(txt_buf, "2"); - break; - case 0x96: - strcat(txt_buf, "3"); - break; - default: - strcat(txt_buf, "X"); - break; - } + strcat(txt_buf, "InnoLux P062CCA-AZX"); break; case PANEL_AUO_A062TAN01: - strcat(txt_buf, "AUO A062TAN0"); - switch (display_rev) - { - case 0x94: - strcat(txt_buf, "1"); - break; - case 0x95: - strcat(txt_buf, "2"); - break; - default: - strcat(txt_buf, "X"); - break; - } + strcat(txt_buf, "AUO A062TAN0X"); break; case PANEL_INL_2J055IA_27A: strcat(txt_buf, "InnoLux 2J055IA-27A"); break; case PANEL_AUO_A055TAN01: - strcat(txt_buf, "AUO A055TAN01"); + strcat(txt_buf, "AUO A055TAN0X"); + break; + case PANEL_SHP_LQ055T1SW10: + strcat(txt_buf, "Sharp LQ055T1SW10"); + break; + case PANEL_SAM_AMS699VC01: + strcat(txt_buf, "Samsung AMS699VC01"); break; default: switch (cal0->lcd_vendor & 0xFF) @@ -403,20 +320,30 @@ static lv_res_t _create_mbox_cal0(lv_obj_t *btn) case (PANEL_AUO_A062TAN01 & 0xFF): strcat(txt_buf, "AUO "); break; + case (PANEL_SAM_AMS699VC01 & 0xFF): + strcat(txt_buf, "Samsung "); + break; } strcat(txt_buf, "Unknown"); break; } + s_printf(txt_buf + strlen(txt_buf), + " (%06X)\n#FF8000 Touch Vendor:# %d\n" + "#FF8000 IMU Type/Mount:# %d / %d\n" + "#FF8000 Stick L/R Type:# %02X / %02X\n", + cal0->lcd_vendor, cal0->touch_ic_vendor_id, + cal0->console_6axis_sensor_type, cal0->console_6axis_sensor_mount_type, + cal0->analog_stick_type_l, cal0->analog_stick_type_r); + bool valid_cal0 = !memcmp(hash, cal0->body_sha256, 0x20); - s_printf(txt_buf + strlen(txt_buf), " (%06X)\n#FF8000 SHA256 Hash Match:# %s", cal0->lcd_vendor, valid_cal0 ? "Pass" : "Failed"); + s_printf(txt_buf + strlen(txt_buf), "#FF8000 SHA256 Hash Match:# %s", valid_cal0 ? "Pass" : "Failed"); lv_label_set_text(lb_desc, txt_buf); out: free(txt_buf); sd_unmount(); - sdmmc_storage_end(&emmc_storage); lv_mbox_add_btns(mbox, mbox_btn_map, _cal0_dump_window_action); @@ -426,9 +353,21 @@ out: return LV_RES_OK; } -static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) +static lv_obj_t *hw_info_ver = NULL; +static lv_res_t _action_win_hw_info_status_close(lv_obj_t *btn) { - lv_obj_t *win = nyx_create_standard_window(SYMBOL_CHIP" HW & Cached Fuses Info"); + if (hw_info_ver) + { + lv_obj_del(hw_info_ver); + hw_info_ver = NULL; + } + + return nyx_win_close_action_custom(btn); +} + +static lv_res_t _create_window_hw_info_status(lv_obj_t *btn) +{ + lv_obj_t *win = nyx_create_window_custom_close_btn(SYMBOL_CHIP" HW & Fuses Info", _action_win_hw_info_status_close); lv_win_add_btn(win, NULL, SYMBOL_DOWNLOAD" Dump fuses", _fuse_dump_window_action); lv_win_add_btn(win, NULL, SYMBOL_INFO" CAL0 Info", _create_mbox_cal0); @@ -440,17 +379,27 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) lv_label_set_recolor(lb_desc, true); lv_label_set_style(lb_desc, &monospace_text); + char version[32]; + s_printf(version, "%s%d.%d.%d%c", NYX_VER_RL ? "v" : "", NYX_VER_MJ, NYX_VER_MN, NYX_VER_HF, NYX_VER_RL > 'A' ? NYX_VER_RL : 0); + lv_obj_t * lbl_ver = lv_label_create(lv_scr_act(), NULL); + lv_label_set_style(lbl_ver, &hint_small_style_white); + lv_label_set_text(lbl_ver, version); + lv_obj_align(lbl_ver, status_bar.bar_bg, LV_ALIGN_OUT_TOP_RIGHT, -LV_DPI * 9 / 23, -LV_DPI * 2 / 13); + hw_info_ver = lbl_ver; + lv_label_set_static_text(lb_desc, - "SKU:\n" - "DRAM ID:\n" + "#FF8000 SoC:#\n" + "#FF8000 SKU:#\n" + "#FF8000 DRAM ID:#\n" "#FF8000 Burnt Fuses (ODM 7/6):#\n" "ODM Fields (4, 6, 7):\n" - "Secure Boot key (SBK):\n" - "Device key (DK):\n" + "Secure Boot Key (SBK):\n" + "Device Key (DK):\n" + "Public Key (PK SHA256):\n\n" + "HOS Keygen Revision:\n" "USB Stack:\n" "Final Test Revision:\n" "Chip Probing Revision:\n" - "Bootrom ipatches size:\n" "CPU Speedo 0 (CPU Val):\n" "CPU Speedo 1:\n" "CPU Speedo 2 (GPU Val):\n" @@ -463,66 +412,65 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) "Vendor Code:\n" "FAB Code:\n" "LOT Code 0:\n" - "LOT Code 1:\n" "Wafer ID:\n" "X Coordinate:\n" - "Y Coordinate:\n" - "#FF8000 Chip ID Revision:#" + "Y Coordinate:" ); lv_obj_set_width(lb_desc, lv_obj_get_width(desc)); lv_obj_t *val = lv_cont_create(win, NULL); - lv_obj_set_size(val, LV_HOR_RES / 11 * 3, LV_VER_RES - (LV_DPI * 11 / 7) - 5); + lv_obj_set_size(val, LV_HOR_RES / 7 * 2 + LV_DPI / 11, LV_VER_RES - (LV_DPI * 11 / 7) - 5); lv_obj_t * lb_val = lv_label_create(val, lb_desc); - char *txt_buf = (char *)malloc(0x4000); + char *txt_buf = (char *)malloc(SZ_16K); // Decode fuses. char *sku; - char dram_man[32]; + char dram_man[64]; char fuses_hos_version[64]; u8 dram_id = fuse_read_dramid(true); switch (fuse_read_hw_type()) { case FUSE_NX_HW_TYPE_ICOSA: - sku = "Icosa (Erista)"; + sku = "Icosa - Odin"; break; case FUSE_NX_HW_TYPE_IOWA: - sku = "Iowa (Mariko)"; + sku = "Iowa - Modin"; break; case FUSE_NX_HW_TYPE_HOAG: - sku = "Hoag (Mariko)"; + sku = "Hoag - Vali"; break; case FUSE_NX_HW_TYPE_AULA: - sku = "Aula (Mariko)"; + sku = "Aula - Fric"; break; default: sku = "#FF8000 Unknown#"; break; } + // Prepare dram id info. if (!h_cfg.t210b01) { switch (dram_id) { // LPDDR4 3200Mbps. case LPDDR4_ICOSA_4GB_SAMSUNG_K4F6E304HB_MGCH: - case LPDDR4_COPPER_4GB_SAMSUNG_K4F6E304HB_MGCH: strcpy(dram_man, "Samsung K4F6E304HB-MGCH 4GB"); break; case LPDDR4_ICOSA_4GB_HYNIX_H9HCNNNBPUMLHR_NLE: - case LPDDR4_COPPER_4GB_HYNIX_H9HCNNNBPUMLHR_NLE: strcpy(dram_man, "Hynix H9HCNNNBPUMLHR-NLE 4GB"); break; - case LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WT: - case LPDDR4_COPPER_4GB_MICRON_MT53B512M32D2NP_062_WT: - strcpy(dram_man, "Micron MT53B512M32D2NP-062"); + case LPDDR4_ICOSA_4GB_MICRON_MT53B512M32D2NP_062_WTC: + strcpy(dram_man, "Micron MT53B512M32D2NP-062 WT:C"); break; case LPDDR4_ICOSA_6GB_SAMSUNG_K4FHE3D4HM_MGCH: strcpy(dram_man, "Samsung K4FHE3D4HM-MGCH 6GB"); break; + case LPDDR4_ICOSA_8GB_SAMSUNG_K4FBE3D4HM_MGXX: + strcpy(dram_man, "Samsung K4FBE3D4HM-MGXX 8GB"); + break; default: strcpy(dram_man, "#FF8000 Unknown#"); break; @@ -533,9 +481,6 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) switch (dram_id) { // LPDDR4X 3733Mbps. - case LPDDR4X_IOWA_4GB_SAMSUNG_X1X2: - strcpy(dram_man, "Samsung X1X2 4GB"); - break; case LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AM_MGCJ: case LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AM_MGCJ: strcpy(dram_man, "Samsung K4U6E3S4AM-MGCJ 4GB"); @@ -548,15 +493,12 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) case LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLHR_NME: strcpy(dram_man, "Hynix H9HCNNNBKMMLHR-NME 4GB"); break; - case LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WT: // 4266Mbps. - case LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WT: // 4266Mbps. - strcpy(dram_man, "Micron MT53E512M32D2NP-046 4GB"); + case LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTE: // 4266Mbps. + case LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTE: // 4266Mbps. + strcpy(dram_man, "Micron MT53E512M32D2NP-046 WT:E"); break; // LPDDR4X 4266Mbps - case LPDDR4X_IOWA_4GB_SAMSUNG_Y: - strcpy(dram_man, "Samsung Y 4GB"); - break; case LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AA_MGCL: case LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AA_MGCL: case LPDDR4X_AULA_4GB_SAMSUNG_K4U6E3S4AA_MGCL: @@ -567,27 +509,34 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) case LPDDR4X_AULA_8GB_SAMSUNG_K4UBE3D4AA_MGCL: strcpy(dram_man, "Samsung K4UBE3D4AA-MGCL 8GB"); break; - case LPDDR4X_IOWA_4GB_SAMSUNG_1Y_Y: - strcpy(dram_man, "Samsung 1y Y 4GB"); + case LPDDR4X_IOWA_4GB_SAMSUNG_K4U6E3S4AB_MGCL: + case LPDDR4X_HOAG_4GB_SAMSUNG_K4U6E3S4AB_MGCL: + case LPDDR4X_AULA_4GB_SAMSUNG_K4U6E3S4AB_MGCL: + strcpy(dram_man, "Samsung K4U6E3S4AB-MGCL 4GB"); break; - case LPDDR4X_IOWA_8GB_SAMSUNG_1Y_Y: - strcpy(dram_man, "Samsung 1y Y 8GB"); + case LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D2NP_046_WTF: + case LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D2NP_046_WTF: + case LPDDR4X_AULA_4GB_MICRON_MT53E512M32D2NP_046_WTF: + strcpy(dram_man, "Micron MT53E512M32D2NP-046 WT:F"); break; - // case LPDDR4X_AULA_8GB_SAMSUNG_1Y_A: // Unused. - // strcpy(dram_man, "Samsung 1y A 4GB"); - // break; - case LPDDR4X_IOWA_4GB_MICRON_1Y_A: - case LPDDR4X_HOAG_4GB_MICRON_1Y_A: - case LPDDR4X_AULA_4GB_MICRON_1Y_A: - strcpy(dram_man, "Micron 1y A 4GB"); + case LPDDR4X_HOAG_4GB_HYNIX_H9HCNNNBKMMLXR_NEE: // Replaced from Copper. + case LPDDR4X_AULA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE: // Replaced from Copper. + case LPDDR4X_IOWA_4GB_HYNIX_H9HCNNNBKMMLXR_NEE: // Replaced from Copper. + strcpy(dram_man, "Hynix H9HCNNNBKMMLXR-NEE 4GB"); break; - case LPDDR4X_IOWA_4GB_HYNIX_1Y_A: // Replaced from Copper. - case LPDDR4X_HOAG_4GB_HYNIX_1Y_A: // Replaced from Copper. - case LPDDR4X_AULA_4GB_HYNIX_1Y_A: // Replaced from Copper. - strcpy(dram_man, "Hynix 1y A 4GB"); + case LPDDR4X_IOWA_4GB_HYNIX_H54G46CYRBX267: + case LPDDR4X_HOAG_4GB_HYNIX_H54G46CYRBX267: + case LPDDR4X_AULA_4GB_HYNIX_H54G46CYRBX267: + strcpy(dram_man, "Hynix H54G46CYRBX267 4GB"); break; + case LPDDR4X_IOWA_4GB_MICRON_MT53E512M32D1NP_046_WTB: + case LPDDR4X_HOAG_4GB_MICRON_MT53E512M32D1NP_046_WTB: + case LPDDR4X_AULA_4GB_MICRON_MT53E512M32D1NP_046_WTB: + strcpy(dram_man, "Micron MT53E512M32D1NP-046 WT:B"); + break; + default: - strcpy(dram_man, "#FF8000 Unknown#"); + strcpy(dram_man, "#FF8000 Contact me!#"); break; } } @@ -599,6 +548,7 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) // Check if overburnt. u8 burnt_fuses_hos = (fuse_read_odm(7) & ~bit_count_mask(burnt_fuses_7)) ? 255 : burnt_fuses_7; + //! TODO: Update on anti-downgrade fuses change. switch (burnt_fuses_hos) { case 0: @@ -647,7 +597,25 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) strcpy(fuses_hos_version, "11.0.0 - 12.0.1"); break; case 15: - strcpy(fuses_hos_version, "12.0.2+"); + strcpy(fuses_hos_version, "12.0.2 - 13.2.0"); + break; + case 16: + strcpy(fuses_hos_version, "13.2.1 - 14.1.2"); + break; + case 17: + strcpy(fuses_hos_version, "15.0.0 - 15.0.1"); + break; + case 18: + strcpy(fuses_hos_version, "16.0.0 - 16.1.0"); + break; + case 19: + strcpy(fuses_hos_version, "17.0.0 - 18.1.0"); + break; + case 20: + strcpy(fuses_hos_version, "19.0.0 - 19.0.1"); + break; + case 21: + strcpy(fuses_hos_version, "20.0.0+"); break; case 255: strcpy(fuses_hos_version, "#FFD000 Overburnt#"); @@ -671,26 +639,34 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) u32 chip_id = APB_MISC(APB_MISC_GP_HIDREV); // Parse fuses and display them. s_printf(txt_buf, - "%X - %s - %s\n%02d: %s\n%d - %d (HOS: %s)\n%08X %08X %08X\n%08X%08X%08X%08X\n%08X\n" - "%s\n%d.%02d (0x%X)\n%d.%02d (0x%X)\n%d\n%d\n%d\n%d\n%d\n0x%X\n%d\n%d\n%d\n%d\n" - "%d\n%d\n%d (0x%X)\n%d\n%d\n%d\n%d\n" - "ID: %02X, Major: A0%d, Minor: %d", + "%02X - %s - M%d A%02d\n" + "%X - %s - %s\n%02d - %s\n%d | %d - HOS: %s\n%08X %08X %08X\n%08X%08X%08X%08X\n%08X\n%08X%08X%08X%08X\n%08X%08X%08X%08X\n%d\n" + "%s\n%d.%02d (0x%X)\n%d.%02d (0x%X)\n%d\n%d\n%d\n%d\n0x%X\n%d\n%d (%d)\n%d (%d)\n%d (%d)\n" + "%d\n%d\n%d (0x%X)\n%d\n%d\n%d", + (chip_id >> 8) & 0xFF, + hw_get_chip_id() == GP_HIDREV_MAJOR_T210 ? "T210 (Erista)" : "T210B01 (Mariko)", + (chip_id >> 4) & 0xF, (chip_id >> 16) & 0xF, FUSE(FUSE_SKU_INFO), sku, fuse_read_hw_state() ? "Dev" : "Retail", dram_id, dram_man, burnt_fuses_7, burnt_fuses_6, fuses_hos_version, fuse_read_odm(4), fuse_read_odm(6), fuse_read_odm(7), byte_swap_32(FUSE(FUSE_PRIVATE_KEY0)), byte_swap_32(FUSE(FUSE_PRIVATE_KEY1)), byte_swap_32(FUSE(FUSE_PRIVATE_KEY2)), byte_swap_32(FUSE(FUSE_PRIVATE_KEY3)), byte_swap_32(FUSE(FUSE_PRIVATE_KEY4)), + byte_swap_32(FUSE(FUSE_PUBLIC_KEY0)), byte_swap_32(FUSE(FUSE_PUBLIC_KEY1)), + byte_swap_32(FUSE(FUSE_PUBLIC_KEY2)), byte_swap_32(FUSE(FUSE_PUBLIC_KEY3)), + byte_swap_32(FUSE(FUSE_PUBLIC_KEY4)), byte_swap_32(FUSE(FUSE_PUBLIC_KEY5)), + byte_swap_32(FUSE(FUSE_PUBLIC_KEY6)), byte_swap_32(FUSE(FUSE_PUBLIC_KEY7)), + fuse_read_odm_keygen_rev(), ((FUSE(FUSE_RESERVED_SW) & 0x80) || h_cfg.t210b01) ? "XUSB" : "USB2", (FUSE(FUSE_OPT_FT_REV) >> 5) & 0x3F, FUSE(FUSE_OPT_FT_REV) & 0x1F, FUSE(FUSE_OPT_FT_REV), (FUSE(FUSE_OPT_CP_REV) >> 5) & 0x3F, FUSE(FUSE_OPT_CP_REV) & 0x1F, FUSE(FUSE_OPT_CP_REV), - FUSE(FUSE_FIRST_BOOTROM_PATCH_SIZE) & 0x7F, FUSE(FUSE_CPU_SPEEDO_0_CALIB), FUSE(FUSE_CPU_SPEEDO_1_CALIB), FUSE(FUSE_CPU_SPEEDO_2_CALIB), FUSE(FUSE_SOC_SPEEDO_0_CALIB), FUSE(FUSE_SOC_SPEEDO_1_CALIB), FUSE(FUSE_SOC_SPEEDO_2_CALIB), - FUSE(FUSE_CPU_IDDQ_CALIB), FUSE(FUSE_SOC_IDDQ_CALIB), FUSE(FUSE_GPU_IDDQ_CALIB), + FUSE(FUSE_CPU_IDDQ_CALIB), FUSE(FUSE_CPU_IDDQ_CALIB) * 4, + FUSE(FUSE_SOC_IDDQ_CALIB), FUSE(FUSE_SOC_IDDQ_CALIB) * 4, + FUSE(FUSE_GPU_IDDQ_CALIB), FUSE(FUSE_GPU_IDDQ_CALIB) * 5, FUSE(FUSE_OPT_VENDOR_CODE), FUSE(FUSE_OPT_FAB_CODE), lot_bin, FUSE(FUSE_OPT_LOT_CODE_0), - FUSE(FUSE_OPT_LOT_CODE_1), FUSE(FUSE_OPT_WAFER_ID), FUSE(FUSE_OPT_X_COORDINATE), FUSE(FUSE_OPT_Y_COORDINATE), - (chip_id >> 8) & 0xFF, (chip_id >> 4) & 0xF, (chip_id >> 16) & 0xF); + FUSE(FUSE_OPT_WAFER_ID), FUSE(FUSE_OPT_X_COORDINATE), FUSE(FUSE_OPT_Y_COORDINATE)); lv_label_set_text(lb_val, txt_buf); @@ -704,16 +680,16 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) lv_label_set_long_mode(lb_desc2, LV_LABEL_LONG_BREAK); lv_label_set_recolor(lb_desc2, true); - // DRAM info. - emc_mr_data_t ram_vendor = sdram_read_mrx(MR5_MAN_ID); - emc_mr_data_t ram_rev0 = sdram_read_mrx(MR6_REV_ID1); - emc_mr_data_t ram_rev1 = sdram_read_mrx(MR7_REV_ID2); + // Prepare DRAM info. + emc_mr_data_t ram_vendor = sdram_read_mrx(MR5_MAN_ID); + emc_mr_data_t ram_rev0 = sdram_read_mrx(MR6_REV_ID1); + emc_mr_data_t ram_rev1 = sdram_read_mrx(MR7_REV_ID2); emc_mr_data_t ram_density = sdram_read_mrx(MR8_DENSITY); - u32 ranks = EMC(EMC_ADR_CFG) + 1; + u32 ranks = EMC(EMC_ADR_CFG) + 1; u32 channels = (EMC(EMC_FBIO_CFG7) >> 1) & 3; - u32 die_channels = ranks * ((channels & 1) + ((channels & 2) >> 1)); - s_printf(txt_buf, "#00DDFF %s SDRAM ##FF8000 (Ch 0 | Ch 1):#\n#FF8000 Vendor:# ", dram_id > 6 ? "LPDDR4X" : "LPDDR4"); - switch (ram_vendor.rank0_ch0) + channels = (channels & 1) + ((channels & 2) >> 1); + s_printf(txt_buf, "#00DDFF %s SDRAM ##FF8000 (Module 0 | 1):#\n#FF8000 Vendor:# ", h_cfg.t210b01 ? "LPDDR4X" : "LPDDR4"); + switch (ram_vendor.chip0.rank0_ch0) { case 1: strcat(txt_buf, "Samsung"); @@ -733,12 +709,24 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) case 9: strcat(txt_buf, "ESMT"); break; + case 19: + strcat(txt_buf, "CXMT"); + break; case 26: - strcat(txt_buf, "Xi'an UniIC Semiconductors Co., Ltd"); + strcat(txt_buf, "Xi'an UniIC"); + break; + case 27: + strcat(txt_buf, "ISSI"); break; case 28: strcat(txt_buf, "JSC"); break; + case 197: + strcat(txt_buf, "SINKER"); + break; + case 229: + strcat(txt_buf, "Dosilicon"); + break; case 248: strcat(txt_buf, "Fidelix"); break; @@ -753,11 +741,11 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) strcat(txt_buf, "Micron"); break; default: - s_printf(txt_buf + strlen(txt_buf), "#FF8000 Unknown# (%d)", ram_vendor.rank0_ch0); + s_printf(txt_buf + strlen(txt_buf), "#FF8000 Unknown# (%d)", ram_vendor.chip0.rank0_ch0); break; } strcat(txt_buf, " #FF8000 |# "); - switch (ram_vendor.rank0_ch1) + switch (ram_vendor.chip1.rank0_ch0) { case 1: strcat(txt_buf, "Samsung"); @@ -769,57 +757,84 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) strcat(txt_buf, "Micron"); break; default: - s_printf(txt_buf + strlen(txt_buf), "#FF8000 Unknown# (%d)", ram_vendor.rank0_ch1); + s_printf(txt_buf + strlen(txt_buf), "#FF8000 Unknown# (%d)", ram_vendor.chip1.rank0_ch0); break; } - s_printf(txt_buf + strlen(txt_buf), "\n#FF8000 Rev ID:# %X.%02X #FF8000 |# %X.%02X\n#FF8000 Density:# %d", - ram_rev0.rank0_ch0, ram_rev1.rank0_ch0, ram_rev0.rank0_ch1, ram_rev1.rank0_ch1, die_channels); - switch ((ram_density.rank0_ch0 & 0x3C) >> 2) + + s_printf(txt_buf + strlen(txt_buf), "\n#FF8000 Rev ID:# %X.%02X #FF8000 |# %X.%02X\n#FF8000 Density:# ", + ram_rev0.chip0.rank0_ch0, ram_rev1.chip0.rank0_ch0, ram_rev0.chip1.rank0_ch0, ram_rev1.chip1.rank0_ch0); + + u32 actual_ranks = (ram_vendor.chip0.rank0_ch0 == ram_vendor.chip0.rank1_ch0 && + ram_vendor.chip0.rank0_ch1 == ram_vendor.chip0.rank1_ch1 && + ram_rev0.chip0.rank0_ch0 == ram_rev0.chip0.rank1_ch0 && + ram_rev0.chip0.rank0_ch1 == ram_rev0.chip0.rank1_ch1 && + ram_rev1.chip0.rank0_ch0 == ram_rev1.chip0.rank1_ch0 && + ram_rev1.chip0.rank0_ch1 == ram_rev1.chip0.rank1_ch1 && + ram_density.chip0.rank0_ch0 == ram_density.chip0.rank1_ch0 && + ram_density.chip0.rank0_ch1 == ram_density.chip0.rank1_ch1) + ? 2 : 1; + bool rank_bad = ranks != actual_ranks; + s_printf(txt_buf + strlen(txt_buf), "%s %d x %s", rank_bad ? "#FFDD00" : "", actual_ranks * channels, rank_bad ? "#" : ""); + + switch ((ram_density.chip0.rank0_ch0 & 0x3C) >> 2) { case 2: - strcat(txt_buf, " x 512MB"); + strcat(txt_buf, "512MB"); break; case 3: - strcat(txt_buf, " x 768MB"); + strcat(txt_buf, "768MB"); break; case 4: - strcat(txt_buf, " x 1GB"); + strcat(txt_buf, "1GB"); break; case 5: - strcat(txt_buf, " x 1.5GB"); + strcat(txt_buf, "1.5GB"); break; case 6: - strcat(txt_buf, " x 2GB"); + strcat(txt_buf, "2GB"); break; default: - s_printf(txt_buf + strlen(txt_buf), " x Unk (%d)", (ram_density.rank0_ch0 & 0x3C) >> 2); + s_printf(txt_buf + strlen(txt_buf), "Unk (%d)", (ram_density.chip0.rank0_ch0 & 0x3C) >> 2); break; } - s_printf(txt_buf + strlen(txt_buf), " #FF8000 |# %d", die_channels); - switch ((ram_density.rank0_ch1 & 0x3C) >> 2) + + actual_ranks = (ram_vendor.chip1.rank0_ch0 == ram_vendor.chip1.rank1_ch0 && + ram_vendor.chip1.rank0_ch1 == ram_vendor.chip1.rank1_ch1 && + ram_rev0.chip1.rank0_ch0 == ram_rev0.chip1.rank1_ch0 && + ram_rev0.chip1.rank0_ch1 == ram_rev0.chip1.rank1_ch1 && + ram_rev1.chip1.rank0_ch0 == ram_rev1.chip1.rank1_ch0 && + ram_rev1.chip1.rank0_ch1 == ram_rev1.chip1.rank1_ch1 && + ram_density.chip1.rank0_ch0 == ram_density.chip1.rank1_ch0 && + ram_density.chip1.rank0_ch1 == ram_density.chip1.rank1_ch1) + ? 2 : 1; + rank_bad = ranks != actual_ranks; + + s_printf(txt_buf + strlen(txt_buf), " #FF8000 |# %s %d x %s", rank_bad ? "#FFDD00" : "", actual_ranks * channels, rank_bad ? "#" : ""); + + switch ((ram_density.chip1.rank0_ch0 & 0x3C) >> 2) { case 2: - strcat(txt_buf, " x 512MB"); + strcat(txt_buf, "512MB"); break; case 3: - strcat(txt_buf, " x 768MB"); + strcat(txt_buf, "768MB"); break; case 4: - strcat(txt_buf, " x 1GB"); + strcat(txt_buf, "1GB"); break; case 5: - strcat(txt_buf, " x 1.5GB"); + strcat(txt_buf, "1.5GB"); break; case 6: - strcat(txt_buf, " x 2GB"); + strcat(txt_buf, "2GB"); break; default: - s_printf(txt_buf + strlen(txt_buf), " x Unk (%d)", (ram_density.rank0_ch1 & 0x3C) >> 2); + s_printf(txt_buf + strlen(txt_buf), "Unk (%d)", (ram_density.chip1.rank0_ch0 & 0x3C) >> 2); break; } strcat(txt_buf, "\n\n"); - // Display info. + // Prepare display info. u8 display_rev = (nyx_str->info.disp_id >> 8) & 0xFF; u32 display_id = ((nyx_str->info.disp_id >> 8) & 0xFF00) | (nyx_str->info.disp_id & 0xFF); @@ -846,23 +861,41 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) case 0x96: strcat(txt_buf, "-AZ3"); break; + case 0x97: + strcat(txt_buf, "-???"); + break; case 0x98: strcat(txt_buf, "-???"); break; + case 0x99: + strcat(txt_buf, "-???"); + break; default: strcat(txt_buf, " #FFDD00 Contact me!#"); break; } break; case PANEL_AUO_A062TAN01: - strcat(txt_buf, "AUO A062"); + strcat(txt_buf, "AUO A062TAN"); switch (display_rev) { + case 0x93: + strcat(txt_buf, "00"); + break; case 0x94: - strcat(txt_buf, "TAN01"); + strcat(txt_buf, "01"); break; case 0x95: - strcat(txt_buf, "TAN02"); + strcat(txt_buf, "02"); + break; + case 0x96: + strcat(txt_buf, "??"); + break; + case 0x97: + strcat(txt_buf, "??"); + break; + case 0x98: + strcat(txt_buf, "??"); break; default: strcat(txt_buf, " #FFDD00 Contact me!#"); @@ -873,7 +906,26 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) strcat(txt_buf, "InnoLux 2J055IA-27A"); break; case PANEL_AUO_A055TAN01: - strcat(txt_buf, "AUO A055TAN01"); + strcat(txt_buf, "AUO A055TAN"); + s_printf(txt_buf + strlen(txt_buf), "%02d", display_rev - 0x92); + break; + case PANEL_SHP_LQ055T1SW10: + strcat(txt_buf, "Sharp LQ055T1SW10"); + break; + case PANEL_SAM_AMS699VC01: + strcat(txt_buf, "Samsung AMS699VC01"); + break; + case PANEL_OEM_CLONE_6_2: + strcat(txt_buf, "#FFDD00 OEM Clone 6.2\"#"); + break; + case PANEL_OEM_CLONE_5_5: + strcat(txt_buf, "#FFDD00 OEM Clone 5.5\"#"); + break; + case PANEL_OEM_CLONE: + strcat(txt_buf, "#FFDD00 OEM Clone#"); + break; + case 0xCCCC: + strcat(txt_buf, "#FFDD00 Failed to get info!#"); break; default: switch (display_id & 0xFF) @@ -887,6 +939,9 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) case (PANEL_AUO_A062TAN01 & 0xFF): strcat(txt_buf, "AUO "); break; + case (PANEL_SAM_AMS699VC01 & 0xFF): + strcat(txt_buf, "Samsung "); + break; } strcat(txt_buf, "Unknown #FFDD00 Contact me!#"); break; @@ -899,6 +954,7 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) touch_panel_info_t *touch_panel; bool panel_ic_paired = false; + // Prepare touch panel/ic info. if (!touch_get_fw_info(&touch_fw)) { strcat(txt_buf, "\n\n#00DDFF Touch Panel:#\n#FF8000 Model:# "); @@ -906,7 +962,7 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) touch_panel = touch_get_panel_vendor(); if (touch_panel) { - if (touch_panel->idx == -2) // Touch panel not found, print gpios. + if ((u8)touch_panel->idx == (u8)-2) // Touch panel not found, print gpios. { s_printf(txt_buf + strlen(txt_buf), "%2X%2X%2X #FFDD00 Contact me!#", touch_panel->gpio0, touch_panel->gpio1, touch_panel->gpio2); @@ -918,42 +974,46 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) else strcat(txt_buf, "#FFDD00 Error!#"); - s_printf(txt_buf + strlen(txt_buf), "\n#FF8000 ID:# %08X (", touch_fw.fw_id); + s_printf(txt_buf + strlen(txt_buf), "\n#FF8000 ID:# %02X.%02X.%02X.%02X (", + (touch_fw.fw_id >> 24) & 0xFF, (touch_fw.fw_id >> 16) & 0xFF, (touch_fw.fw_id >> 8) & 0xFF, touch_fw.fw_id & 0xFF); + // Check panel pair info. switch (touch_fw.fw_id) { case 0x00100100: - strcat(txt_buf, "4CD 1601"); + strcat(txt_buf, "4CD60D/0"); if (touch_panel) - panel_ic_paired = touch_panel->idx == -1; + panel_ic_paired = (u8)touch_panel->idx == (u8)-1; break; case 0x00100200: // 4CD 1602. case 0x00120100: case 0x32000001: - strcat(txt_buf, "4CD 1801"); + strcat(txt_buf, "4CD60D/1"); if (touch_panel) panel_ic_paired = touch_panel->idx == 0; // NISSHA NFT-K12D. break; - case 0x98000004: // New 6.2" panel? - strcat(txt_buf, "FST2 UNK"); - if (touch_panel) - panel_ic_paired = touch_panel->idx == 0; - break; + // case 0x98000004: // New 6.2" panel? + // case 0x50000001: + // case 0x50000002: + // strcat(txt_buf, "FST2 UNK"); + // if (touch_panel) + // panel_ic_paired = touch_panel->idx == 0; + // break; case 0x001A0300: case 0x32000102: - strcat(txt_buf, "4CD 2602"); + strcat(txt_buf, "4CD60D/2"); if (touch_panel) panel_ic_paired = touch_panel->idx == 1; // GiS GGM6 B2X. break; case 0x00290100: case 0x32000302: - strcat(txt_buf, "4CD 3801"); + strcat(txt_buf, "4CD60D/3"); if (touch_panel) panel_ic_paired = touch_panel->idx == 2; // NISSHA NBF-K9A. break; case 0x31051820: case 0x32000402: - strcat(txt_buf, "4CD 4602"); // Assumed. Official is XXXX. + strcat(txt_buf, "4CD60D/4"); if (touch_panel) panel_ic_paired = touch_panel->idx == 3; // GiS 5.5". break; @@ -961,17 +1021,19 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) case 0x33000502: case 0x33000503: case 0x33000510: - strcat(txt_buf, "4CD UNKN"); + strcat(txt_buf, "4CD60D/5"); if (touch_panel) - panel_ic_paired = touch_panel->idx == 4; // Unknown Aula 7.0". + panel_ic_paired = touch_panel->idx == 4; // Samsung BH2109. break; default: - strcat(txt_buf, "#FF8000 Unknown#"); + strcat(txt_buf, "#FF8000 Contact me#"); break; } s_printf(txt_buf + strlen(txt_buf), " - %s)\n#FF8000 FTB ver:# %04X\n#FF8000 FW rev:# %04X", - panel_ic_paired ? "Paired" : "#FFDD00 Error#", touch_fw.ftb_ver, touch_fw.fw_rev); + panel_ic_paired ? "Paired" : "#FFDD00 Error#", + touch_fw.ftb_ver, + byte_swap_16(touch_fw.fw_rev)); // Byte swapping makes more sense here. } else strcat(txt_buf, "\n\n#FFDD00 Failed to get touch info!#"); @@ -987,10 +1049,7 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) free(txt_buf); lv_obj_set_width(lb_desc2, lv_obj_get_width(desc2)); - lv_obj_align(desc2, val, LV_ALIGN_OUT_RIGHT_MID, LV_DPI / 2, 0); - - if (!btn) - _create_mbox_cal0(NULL); + lv_obj_align(desc2, val, LV_ALIGN_OUT_RIGHT_MID, LV_DPI / 4, 0); return LV_RES_OK; } @@ -998,13 +1057,16 @@ static lv_res_t _create_window_fuses_info_status(lv_obj_t *btn) static char *ipatches_txt; static void _ipatch_process(u32 offset, u32 value) { - s_printf(ipatches_txt + strlen(ipatches_txt), "%6X %4X ", BOOTROM_BASE + offset, value); + s_printf(ipatches_txt + strlen(ipatches_txt), "%6X %4X ", IROM_BASE + offset, value); u8 lo = value & 0xFF; switch (value >> 8) { case 0x20: s_printf(ipatches_txt + strlen(ipatches_txt), "MOVS R0, ##0x%02X", lo); break; + case 0x21: + s_printf(ipatches_txt + strlen(ipatches_txt), "MOVS R1, ##0x%02X", lo); + break; case 0xDF: s_printf(ipatches_txt + strlen(ipatches_txt), "SVC ##0x%02X", lo); break; @@ -1025,7 +1087,7 @@ static lv_res_t _create_window_bootrom_info_status(lv_obj_t *btn) lv_label_set_recolor(lb_desc, true); lv_label_set_style(lb_desc, &monospace_text); - char *txt_buf = (char *)malloc(0x1000); + char *txt_buf = (char *)malloc(SZ_4K); ipatches_txt = txt_buf; s_printf(txt_buf, "#00DDFF Ipatches:#\n#FF8000 Address "SYMBOL_DOT" Val "SYMBOL_DOT" Instruction#\n"); @@ -1069,7 +1131,7 @@ static lv_res_t _create_mbox_lockpick(lv_obj_t *btn) lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char * mbox_btn_map[] = { "\211", "\222Continue", "\222Close", "\211", "" }; + static const char * mbox_btn_map[] = { "\251", "\222Continue", "\222Close", "\251", "" }; lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); @@ -1096,16 +1158,16 @@ static lv_res_t _create_mbox_emmc_sandisk_report(lv_obj_t * btn) lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char * mbox_btn_map[] = { "\211", "\222Close", "\211", "" }; + static const char * mbox_btn_map[] = { "\251", "\222Close", "\251", "" }; lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); lv_obj_set_width(mbox, LV_HOR_RES / 9 * 8); lv_mbox_set_text(mbox, "#C7EA46 Sandisk Device Report#"); - u8 *buf = calloc(512, 1); - char *txt_buf = (char *)malloc(0x8000); - char *txt_buf2 = (char *)malloc(0x8000); + u8 *buf = zalloc(EMMC_BLOCKSIZE); + char *txt_buf = (char *)malloc(SZ_32K); + char *txt_buf2 = (char *)malloc(SZ_32K); txt_buf[0] = 0; txt_buf2[0] = 0; @@ -1131,7 +1193,7 @@ static lv_res_t _create_mbox_emmc_sandisk_report(lv_obj_t * btn) lv_obj_align(lb_desc2, lb_desc, LV_ALIGN_OUT_RIGHT_TOP, 0, 0); - if (!sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400)) + if (!emmc_initialize(false)) { lv_label_set_text(lb_desc, "#FFDD00 Failed to init eMMC!#"); @@ -1139,7 +1201,7 @@ static lv_res_t _create_mbox_emmc_sandisk_report(lv_obj_t * btn) } int res = sdmmc_storage_vendor_sandisk_report(&emmc_storage, buf); - sdmmc_storage_end(&emmc_storage); + emmc_end(); if (!res) { @@ -1258,7 +1320,7 @@ static lv_res_t _create_mbox_emmc_sandisk_report(lv_obj_t * btn) rpt->advanced.health_pct_mlc ? 101 - rpt->advanced.health_pct_mlc : 0); } else - strcpy(txt_buf2, "#00DDFF Device report#\n#FFDD00 Empty!#"); + strcpy(txt_buf2, "#00DDFF Advanced Health Status#\n#FFDD00 Empty!#"); lv_label_set_text(lb_desc, txt_buf); lv_label_set_text(lb_desc2, txt_buf2); @@ -1283,15 +1345,14 @@ static lv_res_t _create_mbox_benchmark(bool sd_bench) lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char * mbox_btn_map[] = { "\211", "\222OK", "\211", "" }; + static const char * mbox_btn_map[] = { "\251", "\222OK", "\251", "" }; lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); - lv_obj_set_width(mbox, LV_HOR_RES / 7 * 4); + lv_obj_set_width(mbox, LV_HOR_RES * 3 / 7); - char *txt_buf = (char *)malloc(0x4000); + char *txt_buf = (char *)malloc(SZ_16K); - s_printf(txt_buf, "#FF8000 %s Benchmark#\n[Raw Reads] Abort: VOL- & VOL+", - sd_bench ? "SD Card" : "eMMC"); + s_printf(txt_buf, "#FF8000 %s Benchmark#\n[Raw Reads] Abort: VOL- & VOL+", sd_bench ? "SD Card" : "eMMC"); lv_mbox_set_text(mbox, txt_buf); txt_buf[0] = 0; @@ -1329,200 +1390,277 @@ static lv_res_t _create_mbox_benchmark(bool sd_bench) else { storage = &emmc_storage; - res = !sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400); + res = !emmc_initialize(false); if (!res) - sdmmc_storage_set_mmc_partition(&emmc_storage, EMMC_GPP); + emmc_set_partition(EMMC_GPP); } if (res) - lv_mbox_set_text(mbox, "#FFDD00 Failed to init Storage!#"); - else { - int error = 0; - u32 iters = 3; - u32 offset_chunk_start = ALIGN_DOWN(storage->sec_cnt / 3, 0x8000); // Align to 16MB. - if (storage->sec_cnt < 0xC00000) - iters -= 2; // 4GB card. + lv_mbox_set_text(mbox, "#FFDD00 Failed to init Storage!#"); + goto out; + } - for (u32 iter_curr = 0; iter_curr < iters; iter_curr++) + // Set benchmark parameters. + const u32 sct_blk_seq = 0x8000; // 16MB. A2 spec denotes 4MB, but using older big AU. + const u32 sct_blk_4kb = 8; // 4KB. + const u32 sct_rem_seq = 0x200000; // 1GB. A2 spec. + const u32 sct_rem_4kb = 0x80000; // 256MB. A2 spec. + const u32 sct_num_1mb = 0x800; // 1MB. + const u32 size_bytes_seq = sct_rem_seq * SDMMC_DAT_BLOCKSIZE; + const u32 size_bytes_4kb = sct_rem_4kb * SDMMC_DAT_BLOCKSIZE; + + // Set calculation divider. 1000 or 1024. (Does not affect IOPS). + u32 mb_div = 1000; // Unfortunately most software uses fake MB. + + char *mbs_text; + switch (mb_div) + { + case 1000: + mbs_text = "MB/s"; + break; + case 1024: + mbs_text = "MiB/s"; + break; + } + + // Set actual div in MB/MiB. + mb_div *= mb_div; + + int error = 0; + u32 iters = 3; + u32 offset_chunk_start = ALIGN_DOWN(storage->sec_cnt / 3, sct_blk_seq); // Align to block. + if (storage->sec_cnt < 0xC00000) + iters -= 2; // 4GB card. + + u32 rnd_off_cnt = sct_rem_4kb / sct_blk_4kb; + u32 *random_offsets = malloc(rnd_off_cnt * sizeof(u32)); + u32 *times_taken_4k = malloc(rnd_off_cnt * sizeof(u32)); + + for (u32 iter_curr = 0; iter_curr < iters; iter_curr++) + { + u32 pct = 0; + u32 prevPct = 200; + u32 timer = 0; + u32 lba_curr = 0; + u32 sector_off = offset_chunk_start * iter_curr; + u32 sector_num = sct_blk_seq; + u32 data_remaining = sct_rem_seq; + + s_printf(txt_buf + strlen(txt_buf), "#C7EA46 %d/3# - Sector Offset #C7EA46 %08X#:\n", iter_curr + 1, sector_off); + + u32 render_min_ms = 66; + u32 render_timer = get_tmr_ms() + render_min_ms; + while (data_remaining) { - u32 pct = 0; - u32 prevPct = 200; - u32 timer = 0; - u32 lba_curr = 0; - u32 sector = offset_chunk_start * iter_curr; - u32 sector_num = 0x8000; // 16MB chunks. - u32 data_remaining = 0x200000; // 1GB. + u32 time_taken = get_tmr_us(); + error = !sdmmc_storage_read(storage, sector_off + lba_curr, sector_num, (u8 *)MIXD_BUF_ALIGNED); + time_taken = get_tmr_us() - time_taken; + timer += time_taken; - s_printf(txt_buf + strlen(txt_buf), "#C7EA46 %d/3# - Sector Offset #C7EA46 %08X#:\n", iter_curr + 1, sector); + manual_system_maintenance(false); + data_remaining -= sector_num; + lba_curr += sector_num; - while (data_remaining) + pct = (lba_curr * 100) / sct_rem_seq; + if (pct != prevPct && render_timer < get_tmr_ms()) { - u32 time_taken = get_tmr_us(); - error = !sdmmc_storage_read(storage, sector + lba_curr, sector_num, (u8 *)MIXD_BUF_ALIGNED); - time_taken = get_tmr_us() - time_taken; - timer += time_taken; + lv_bar_set_value(bar, pct); + manual_system_maintenance(true); + render_timer = get_tmr_ms() + render_min_ms; - manual_system_maintenance(false); - data_remaining -= sector_num; - lba_curr += sector_num; + prevPct = pct; - pct = (lba_curr * 100) / 0x200000; - if (pct != prevPct) - { - lv_bar_set_value(bar, pct); - manual_system_maintenance(true); - - prevPct = pct; - - if (btn_read_vol() == (BTN_VOL_UP | BTN_VOL_DOWN)) - error = -1; - } - - if (error) - goto error; - } - lv_bar_set_value(bar, 100); - - u32 rate_1k = ((u64)1024 * 1000 * 1000 * 1000) / timer; - s_printf(txt_buf + strlen(txt_buf), - " Sequential 16MiB - Rate: #C7EA46 %3d.%02d MiB/s#\n", - rate_1k / 1000, (rate_1k % 1000) / 10); - lv_label_set_text(lbl_status, txt_buf); - lv_obj_align(lbl_status, NULL, LV_ALIGN_CENTER, 0, 0); - lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); - manual_system_maintenance(true); - - pct = 0; - prevPct = 200; - timer = 0; - lba_curr = 0; - sector_num = 8; // 4KB chunks. - data_remaining = 0x100000; // 512MB. - - while (data_remaining) - { - u32 time_taken = get_tmr_us(); - error = !sdmmc_storage_read(storage, sector + lba_curr, sector_num, (u8 *)MIXD_BUF_ALIGNED); - time_taken = get_tmr_us() - time_taken; - timer += time_taken; - - manual_system_maintenance(false); - data_remaining -= sector_num; - lba_curr += sector_num; - - pct = (lba_curr * 100) / 0x100000; - if (pct != prevPct) - { - lv_bar_set_value(bar, pct); - manual_system_maintenance(true); - - prevPct = pct; - - if (btn_read_vol() == (BTN_VOL_UP | BTN_VOL_DOWN)) - error = -1; - } - - if (error) - goto error; - } - lv_bar_set_value(bar, 100); - - rate_1k = ((u64)512 * 1000 * 1000 * 1000) / timer; - u32 iops_1k = ((u64)512 * 1024 * 1000 * 1000 * 1000) / (4096 / 1024) / timer / 1000; - s_printf(txt_buf + strlen(txt_buf), - " Sequential 4KiB - Rate: #C7EA46 %3d.%02d MiB/s#, IOPS: #C7EA46 %4d#\n", - rate_1k / 1000, (rate_1k % 1000) / 10, iops_1k); - lv_label_set_text(lbl_status, txt_buf); - lv_obj_align(lbl_status, NULL, LV_ALIGN_CENTER, 0, 0); - lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); - manual_system_maintenance(true); - - u32 lba_idx = 0; - u32 *random_offsets = malloc(0x20000 * sizeof(u32)); - u32 random_numbers[4]; - for (u32 i = 0; i < 0x20000; i += 4) - { - // Generate new random numbers. - while (!se_gen_prng128(random_numbers)) - ; - // Clamp offsets to 512MBrange. - random_offsets[i + 0] = random_numbers[0] % 0x100000; - random_offsets[i + 1] = random_numbers[1] % 0x100000; - random_offsets[i + 2] = random_numbers[2] % 0x100000; - random_offsets[i + 3] = random_numbers[3] % 0x100000; + if (btn_read_vol() == (BTN_VOL_UP | BTN_VOL_DOWN)) + error = -1; } - pct = 0; - prevPct = 200; - timer = 0; - data_remaining = 0x100000; // 512MB. - - while (data_remaining) - { - u32 time_taken = get_tmr_us(); - error = !sdmmc_storage_read(storage, sector + random_offsets[lba_idx], sector_num, (u8 *)MIXD_BUF_ALIGNED); - time_taken = get_tmr_us() - time_taken; - timer += time_taken; - - manual_system_maintenance(false); - data_remaining -= sector_num; - lba_idx++; - - pct = (lba_idx * 100) / 0x20000; - if (pct != prevPct) - { - lv_bar_set_value(bar, pct); - manual_system_maintenance(true); - - prevPct = pct; - - if (btn_read_vol() == (BTN_VOL_UP | BTN_VOL_DOWN)) - error = -1; - } - - if (error) - { - free(random_offsets); - goto error; - } - } - lv_bar_set_value(bar, 100); - - // Calculate rate and IOPS for 512MB transfer. - rate_1k = ((u64)512 * 1000 * 1000 * 1000) / timer; - iops_1k = ((u64)512 * 1024 * 1000 * 1000 * 1000) / (4096 / 1024) / timer / 1000; - s_printf(txt_buf + strlen(txt_buf), - " Random 4KiB - Rate: #C7EA46 %3d.%02d MiB/s#, IOPS: #C7EA46 %4d#\n", - rate_1k / 1000, (rate_1k % 1000) / 10, iops_1k); - if (iter_curr == iters - 1) - txt_buf[strlen(txt_buf) - 1] = 0; // Cut off last line change. - lv_label_set_text(lbl_status, txt_buf); - lv_obj_align(lbl_status, NULL, LV_ALIGN_CENTER, 0, 0); - lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); - manual_system_maintenance(true); - free(random_offsets); + if (error) + goto error; } + lv_bar_set_value(bar, 100); + + // Calculate rate for transfer. + u32 rate_1k = (u64)size_bytes_seq * 1000 * 1000 * 1000 / mb_div / timer; + s_printf(txt_buf + strlen(txt_buf), " SEQ 16MB - Rate: #C7EA46 %3d.%02d %s#", + rate_1k / 1000, (rate_1k % 1000) / 10, mbs_text); + lv_label_set_text(lbl_status, txt_buf); + lv_obj_align(lbl_status, NULL, LV_ALIGN_CENTER, 0, 0); + lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); + manual_system_maintenance(true); + + pct = 0; + prevPct = 200; + timer = 0; + lba_curr = 0; + sector_num = sct_blk_4kb; + data_remaining = sct_rem_4kb; + + u32 loop_idx = 0; + render_timer = get_tmr_ms() + render_min_ms; + while (data_remaining) + { + u32 time_taken = get_tmr_us(); + error = !sdmmc_storage_read(storage, sector_off + lba_curr, sector_num, (u8 *)MIXD_BUF_ALIGNED); + time_taken = get_tmr_us() - time_taken; + + timer += time_taken; + times_taken_4k[loop_idx++] = time_taken; + + manual_system_maintenance(false); + data_remaining -= sector_num; + lba_curr += sector_num; + + pct = (lba_curr * 100) / sct_rem_4kb; + if (pct != prevPct && render_timer < get_tmr_ms()) + { + lv_bar_set_value(bar, pct); + manual_system_maintenance(true); + render_timer = get_tmr_ms() + render_min_ms; + + prevPct = pct; + + if (btn_read_vol() == (BTN_VOL_UP | BTN_VOL_DOWN)) + error = -1; + } + + if (error) + goto error; + } + lv_bar_set_value(bar, 100); + + qsort(times_taken_4k, loop_idx, sizeof(u32), qsort_compare_int); // Use int for faster compare. Value can't exceed 2s. + + u32 pct95 = 0; + for (u32 i = 0; i < loop_idx * 95 / 100; i++) + pct95 += times_taken_4k[i]; + pct95 /= loop_idx * 95 / 100; + + u32 pct05 = 0; + for (u32 i = 0; i < loop_idx * 5 / 100; i++) + pct05 += times_taken_4k[loop_idx - 1 - i]; + pct05 /= loop_idx * 5 / 100; + + // Calculate rate and IOPS for transfer. + rate_1k = (u64)size_bytes_4kb * 1000 * 1000 * 1000 / mb_div / timer; + u32 iops = ((u64)(sct_rem_4kb / sct_num_1mb) * 1024 * 1000 * 1000 * 1000) / (4096 / 1024) / timer / 1000; + s_printf(txt_buf + strlen(txt_buf), " AVG #C7EA46 95th# #FF3C28 5th#\n"); + s_printf(txt_buf + strlen(txt_buf), " SEQ 4KB - Rate: #C7EA46 %3d.%02d %s# IOPS: #C7EA46 %4d# %4d %4d \n", + rate_1k / 1000, (rate_1k % 1000) / 10, mbs_text, iops, 1000000 / pct95, 1000000 / pct05); + lv_label_set_text(lbl_status, txt_buf); + lv_obj_align(lbl_status, NULL, LV_ALIGN_CENTER, 0, 0); + lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); + manual_system_maintenance(true); + + u32 lba_idx = 0; + u32 random_numbers[4]; + for (u32 i = 0; i < rnd_off_cnt; i += 4) + { + // Generate new random numbers. + while (!se_gen_prng128(random_numbers)) + ; + // Clamp offsets to 256MB range. + random_offsets[i + 0] = random_numbers[0] % sct_rem_4kb; + random_offsets[i + 1] = random_numbers[1] % sct_rem_4kb; + random_offsets[i + 2] = random_numbers[2] % sct_rem_4kb; + random_offsets[i + 3] = random_numbers[3] % sct_rem_4kb; + } + + pct = 0; + prevPct = 200; + timer = 0; + data_remaining = sct_rem_4kb; + + loop_idx = 0; + render_timer = get_tmr_ms() + render_min_ms; + while (data_remaining) + { + u32 time_taken = get_tmr_us(); + error = !sdmmc_storage_read(storage, sector_off + random_offsets[lba_idx], sector_num, (u8 *)MIXD_BUF_ALIGNED); + time_taken = get_tmr_us() - time_taken; + + timer += time_taken; + times_taken_4k[loop_idx++] = time_taken; + + manual_system_maintenance(false); + data_remaining -= sector_num; + lba_idx++; + + pct = (lba_idx * 100) / rnd_off_cnt; + if (pct != prevPct && render_timer < get_tmr_ms()) + { + lv_bar_set_value(bar, pct); + manual_system_maintenance(true); + render_timer = get_tmr_ms() + render_min_ms; + + prevPct = pct; + + if (btn_read_vol() == (BTN_VOL_UP | BTN_VOL_DOWN)) + error = -1; + } + + if (error) + goto error; + } + lv_bar_set_value(bar, 100); + + qsort(times_taken_4k, loop_idx, sizeof(u32), qsort_compare_int); // Use int for faster compare. Value can't exceed 2s. + + pct95 = 0; + for (u32 i = 0; i < loop_idx * 95 / 100; i++) + pct95 += times_taken_4k[i]; + pct95 /= loop_idx * 95 / 100; + + pct05 = 0; + for (u32 i = 0; i < loop_idx * 5 / 100; i++) + pct05 += times_taken_4k[loop_idx - 1 - i]; + pct05 /= loop_idx * 5 / 100; + + // Calculate rate and IOPS for transfer. + rate_1k = (u64)size_bytes_4kb * 1000 * 1000 * 1000 / mb_div / timer; + iops = ((u64)(sct_rem_4kb / sct_num_1mb) * 1024 * 1000 * 1000 * 1000) / (4096 / 1024) / timer / 1000; + s_printf(txt_buf + strlen(txt_buf), " RND 4KB - Rate: #C7EA46 %3d.%02d %s# IOPS: #C7EA46 %4d# %4d %4d \n", + rate_1k / 1000, (rate_1k % 1000) / 10, mbs_text, iops, 1000000 / pct95, 1000000 / pct05); + if (iter_curr == iters - 1) + txt_buf[strlen(txt_buf) - 1] = 0; // Cut off last new line. + lv_label_set_text(lbl_status, txt_buf); + lv_obj_align(lbl_status, NULL, LV_ALIGN_CENTER, 0, 0); + lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); + manual_system_maintenance(true); + } error: - if (error) - { - if (error == -1) - s_printf(txt_buf + strlen(txt_buf), "\n#FFDD00 Aborted!#"); - else - s_printf(txt_buf + strlen(txt_buf), "\n#FFDD00 IO Error occurred!#"); + free(random_offsets); + free(times_taken_4k); - lv_label_set_text(lbl_status, txt_buf); - lv_obj_align(lbl_status, NULL, LV_ALIGN_CENTER, 0, 0); - } - - lv_obj_del(bar); - - if (sd_bench) - sd_unmount(); + if (error) + { + if (error == -1) + s_printf(txt_buf + strlen(txt_buf), "\n#FFDD00 Aborted!#"); else - sdmmc_storage_end(&emmc_storage); + s_printf(txt_buf + strlen(txt_buf), "\n#FFDD00 IO Error occurred!#"); + + lv_label_set_text(lbl_status, txt_buf); + lv_obj_align(lbl_status, NULL, LV_ALIGN_CENTER, 0, 0); } + + lv_obj_del(bar); + + if (sd_bench && error && error != -1) + sd_end(); + if (sd_bench) + { + if (error && error != -1) + sd_end(); + else + sd_unmount(); + } + else + emmc_end(); + +out: + s_printf(txt_buf, "#FF8000 %s Benchmark#\n[Raw Reads]", sd_bench ? "SD Card" : "eMMC"); + lv_mbox_set_text(mbox, txt_buf); free(txt_buf); lv_mbox_add_btns(mbox, mbox_btn_map, mbox_action); // Important. After set_text. @@ -1557,206 +1695,252 @@ static lv_res_t _create_window_emmc_info_status(lv_obj_t *btn) lv_label_set_long_mode(lb_desc, LV_LABEL_LONG_BREAK); lv_label_set_recolor(lb_desc, true); - char *txt_buf = (char *)malloc(0x4000); + char *txt_buf = (char *)malloc(SZ_16K); txt_buf[0] = '\n'; txt_buf[1] = 0; + u16 *emmc_errors; - if (!sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400)) + if (!emmc_initialize(false)) { lv_label_set_text(lb_desc, "#FFDD00 Failed to init eMMC!#"); lv_obj_set_width(lb_desc, lv_obj_get_width(desc)); + emmc_errors = emmc_get_error_count(); + + goto out_error; } - else + + u32 speed = 0; + char *rsvd_blocks; + char life_a_txt[8]; + char life_b_txt[8]; + u32 cache = emmc_storage.ext_csd.cache_size; + u32 life_a = emmc_storage.ext_csd.dev_life_est_a; + u32 life_b = emmc_storage.ext_csd.dev_life_est_b; + u16 card_type = emmc_storage.ext_csd.card_type; + char card_type_support[96]; + card_type_support[0] = 0; + + // Identify manufacturer. Only official eMMCs. + switch (emmc_storage.cid.manfid) { - u32 speed = 0; - char *rsvd_blocks; - char life_a_txt[8]; - char life_b_txt[8]; - u32 cache = emmc_storage.ext_csd.cache_size; - u32 life_a = emmc_storage.ext_csd.dev_life_est_a; - u32 life_b = emmc_storage.ext_csd.dev_life_est_b; - u16 card_type = emmc_storage.ext_csd.card_type; - char card_type_support[96]; - card_type_support[0] = 0; - - // Identify manufacturer. Only official eMMCs. - switch (emmc_storage.cid.manfid) - { - case 0x11: - strcat(txt_buf, "Toshiba "); - break; - case 0x15: - strcat(txt_buf, "Samsung "); - break; - case 0x45: // Unofficial. - strcat(txt_buf, "SanDisk "); - lv_win_add_btn(win, NULL, SYMBOL_FILE_ALT" Device Report", _create_mbox_emmc_sandisk_report); - break; - case 0x90: - strcat(txt_buf, "SK Hynix "); - break; - } - - s_printf(txt_buf + strlen(txt_buf), "(%02X)\n%c%c%c%c%c%c\n%d.%d\n%04X\n%02d/%04d\n\n", - emmc_storage.cid.manfid, - emmc_storage.cid.prod_name[0], emmc_storage.cid.prod_name[1], emmc_storage.cid.prod_name[2], - emmc_storage.cid.prod_name[3], emmc_storage.cid.prod_name[4], emmc_storage.cid.prod_name[5], - emmc_storage.cid.prv & 0xF, emmc_storage.cid.prv >> 4, - emmc_storage.cid.serial, emmc_storage.cid.month, emmc_storage.cid.year); - - if (card_type & EXT_CSD_CARD_TYPE_HS_26) - { - strcat(card_type_support, "HS26"); - speed = (26 << 16) | 26; - } - if (card_type & EXT_CSD_CARD_TYPE_HS_52) - { - strcat(card_type_support, ", HS52"); - speed = (52 << 16) | 52; - } - if (card_type & EXT_CSD_CARD_TYPE_DDR_1_8V) - { - strcat(card_type_support, ", DDR52 1.8V"); - speed = (52 << 16) | 104; - } - if (card_type & EXT_CSD_CARD_TYPE_HS200_1_8V) - { - strcat(card_type_support, ", HS200 1.8V"); - speed = (200 << 16) | 200; - } - if (card_type & EXT_CSD_CARD_TYPE_HS400_1_8V) - { - strcat(card_type_support, ", HS400 1.8V"); - speed = (200 << 16) | 400; - } - - strcpy(life_a_txt, "-"); - strcpy(life_b_txt, "-"); - - // Normalize cells life. - if (life_a) // SK Hynix is 0 (undefined). - { - life_a--; - life_a = (10 - life_a) * 10; - s_printf(life_a_txt, "%d%%", life_a); - } - - if (life_b) // Toshiba is 0 (undefined). - { - life_b--; - life_b = (10 - life_b) * 10; - s_printf(life_b_txt, "%d%%", life_b); - } - - switch (emmc_storage.ext_csd.pre_eol_info) - { - case 1: - rsvd_blocks = "Normal (< 80%)"; - break; - case 2: - rsvd_blocks = "Warning (> 80%)"; - break; - case 3: - rsvd_blocks = "Critical (> 90%)"; - break; - default: - rsvd_blocks = "#FF8000 Unknown#"; - break; - } - - s_printf(txt_buf + strlen(txt_buf), - "#00DDFF V1.%d (rev 1.%d)#\n%02X\n%d MB/s (%d MHz)\n%d MB/s\n%s\n%d %s\n%d MiB\nA: %s, B: %s\n%s", - emmc_storage.ext_csd.ext_struct, emmc_storage.ext_csd.rev, - emmc_storage.csd.cmdclass, speed & 0xFFFF, (speed >> 16) & 0xFFFF, - emmc_storage.csd.busspeed, card_type_support, - !(cache % 1024) ? (cache / 1024) : cache, !(cache % 1024) ? "MiB" : "KiB", - emmc_storage.ext_csd.max_enh_mult * 512 / 1024, - life_a_txt, life_b_txt, rsvd_blocks); - - lv_label_set_static_text(lb_desc, - "#00DDFF CID:#\n" - "Vendor ID:\n" - "Model:\n" - "Prod Rev:\n" - "S/N:\n" - "Month/Year:\n\n" - "#00DDFF Ext CSD:#\n" - "Cmd Classes:\n" - "Max Rate:\n" - "Current Rate:\n" - "Type Support:\n\n" - "Write Cache:\n" - "Enhanced Area:\n" - "Estimated Life:\n" - "Reserved Used:" - ); - lv_obj_set_width(lb_desc, lv_obj_get_width(desc)); - - lv_obj_t *val = lv_cont_create(win, NULL); - lv_obj_set_size(val, LV_HOR_RES / 11 * 3, LV_VER_RES - (LV_DPI * 11 / 7) - 5); - - lv_obj_t * lb_val = lv_label_create(val, lb_desc); - - lv_label_set_text(lb_val, txt_buf); - - lv_obj_set_width(lb_val, lv_obj_get_width(val)); - lv_obj_align(val, desc, LV_ALIGN_OUT_RIGHT_MID, 0, 0); - - lv_obj_t *desc2 = lv_cont_create(win, NULL); - lv_obj_set_size(desc2, LV_HOR_RES / 2 / 4 * 4, LV_VER_RES - (LV_DPI * 11 / 7) - 5); - - lv_obj_t * lb_desc2 = lv_label_create(desc2, lb_desc); - lv_label_set_style(lb_desc2, &monospace_text); - - u32 boot_size = emmc_storage.ext_csd.boot_mult << 17; - u32 rpmb_size = emmc_storage.ext_csd.rpmb_mult << 17; - strcpy(txt_buf, "#00DDFF eMMC Physical Partitions:#\n"); - s_printf(txt_buf + strlen(txt_buf), "1: #96FF00 BOOT0# Size: %6d KiB (Sect: 0x%08X)\n", boot_size / 1024, boot_size / 512); - s_printf(txt_buf + strlen(txt_buf), "2: #96FF00 BOOT1# Size: %6d KiB (Sect: 0x%08X)\n", boot_size / 1024, boot_size / 512); - s_printf(txt_buf + strlen(txt_buf), "3: #96FF00 RPMB# Size: %6d KiB (Sect: 0x%08X)\n", rpmb_size / 1024, rpmb_size / 512); - s_printf(txt_buf + strlen(txt_buf), "0: #96FF00 GPP# Size: %6d MiB (Sect: 0x%08X)\n", emmc_storage.sec_cnt >> SECTORS_TO_MIB_COEFF, emmc_storage.sec_cnt); - strcat(txt_buf, "\n#00DDFF GPP (eMMC USER) Partition Table:#\n"); - - sdmmc_storage_set_mmc_partition(&emmc_storage, EMMC_GPP); - LIST_INIT(gpt); - nx_emmc_gpt_parse(&gpt, &emmc_storage); - - u32 idx = 0; - LIST_FOREACH_ENTRY(emmc_part_t, part, &gpt, link) - { - if (idx > 10) - { - strcat(txt_buf, "#FFDD00 Table does not fit on screen!#"); - break; - } - - if (part->index < 2) - { - s_printf(txt_buf + strlen(txt_buf), "%02d: #96FF00 %s#%s Size: %d MiB (Sect: 0x%X), Start: %06X\n", - part->index, part->name, !part->name[8] ? " " : "", - (part->lba_end - part->lba_start + 1) >> SECTORS_TO_MIB_COEFF, - part->lba_end - part->lba_start + 1, part->lba_start); - } - else - { - s_printf(txt_buf + strlen(txt_buf), "%02d: #96FF00 %s#\n Size: %7d MiB (Sect: 0x%07X), Start: %07X\n", - part->index, part->name, (part->lba_end - part->lba_start + 1) >> SECTORS_TO_MIB_COEFF, - part->lba_end - part->lba_start + 1, part->lba_start); - } - - idx++; - } - if (!idx) - strcat(txt_buf, "#FFDD00 Partition table is empty!#"); - - nx_emmc_gpt_free(&gpt); - - lv_label_set_text(lb_desc2, txt_buf); - lv_obj_set_width(lb_desc2, lv_obj_get_width(desc2)); - lv_obj_align(desc2, val, LV_ALIGN_OUT_RIGHT_MID, LV_DPI / 6, 0); + case 0x11: + strcat(txt_buf, "Toshiba "); + break; + case 0x15: + strcat(txt_buf, "Samsung "); + break; + case 0x45: // Unofficial. + strcat(txt_buf, "SanDisk "); + lv_win_add_btn(win, NULL, SYMBOL_FILE_ALT" Device Report", _create_mbox_emmc_sandisk_report); + break; + case 0x90: + strcat(txt_buf, "SK Hynix "); + break; + default: + strcat(txt_buf, "Unknown "); + break; } - sdmmc_storage_end(&emmc_storage); + s_printf(txt_buf + strlen(txt_buf), "(%02X)\n%c%c%c%c%c%c (%02X)\n%d.%d\n%04X\n%02d/%04d\n\n", + emmc_storage.cid.manfid, + emmc_storage.cid.prod_name[0], emmc_storage.cid.prod_name[1], emmc_storage.cid.prod_name[2], + emmc_storage.cid.prod_name[3], emmc_storage.cid.prod_name[4], emmc_storage.cid.prod_name[5], + emmc_storage.cid.oemid, + emmc_storage.cid.prv & 0xF, emmc_storage.cid.prv >> 4, + emmc_storage.cid.serial, emmc_storage.cid.month, emmc_storage.cid.year); + + if (card_type & EXT_CSD_CARD_TYPE_HS_26) + { + strcat(card_type_support, "HS26"); + speed = (26 << 16) | 26; + } + if (card_type & EXT_CSD_CARD_TYPE_HS_52) + { + strcat(card_type_support, ", HS52"); + speed = (52 << 16) | 52; + } + if (card_type & EXT_CSD_CARD_TYPE_DDR_1_8V) + { + strcat(card_type_support, ", DDR52 1.8V"); + speed = (52 << 16) | 104; + } + if (card_type & EXT_CSD_CARD_TYPE_HS200_1_8V) + { + strcat(card_type_support, ", HS200 1.8V"); + speed = (200 << 16) | 200; + } + if (card_type & EXT_CSD_CARD_TYPE_HS400_1_8V) + { + strcat(card_type_support, ", HS400 1.8V"); + speed = (200 << 16) | 400; + } + + strcpy(life_a_txt, "-"); + strcpy(life_b_txt, "-"); + + // Normalize cells life. + if (life_a) // SK Hynix is 0 (undefined). + { + life_a--; + life_a = (10 - life_a) * 10; + s_printf(life_a_txt, "%d%%", life_a); + } + + if (life_b) // Toshiba is 0 (undefined). + { + life_b--; + life_b = (10 - life_b) * 10; + s_printf(life_b_txt, "%d%%", life_b); + } + + switch (emmc_storage.ext_csd.pre_eol_info) + { + case 1: + rsvd_blocks = "Normal (< 80%)"; + break; + case 2: + rsvd_blocks = "Warning (> 80%)"; + break; + case 3: + rsvd_blocks = "Critical (> 90%)"; + break; + default: + rsvd_blocks = "#FF8000 Unknown#"; + break; + } + + s_printf(txt_buf + strlen(txt_buf), + "#00DDFF V1.%d (rev 1.%d)#\n%02X\n%d MB/s (%d MHz)\n%d MB/s\n%s\n%d %s\n%d MiB\nA: %s, B: %s\n%s", + emmc_storage.ext_csd.ext_struct, emmc_storage.ext_csd.rev, + emmc_storage.csd.cmdclass, speed & 0xFFFF, (speed >> 16) & 0xFFFF, + emmc_storage.csd.busspeed, card_type_support, + !(cache % 1024) ? (cache / 1024) : cache, !(cache % 1024) ? "MiB" : "KiB", + emmc_storage.ext_csd.max_enh_mult * EMMC_BLOCKSIZE / 1024, + life_a_txt, life_b_txt, rsvd_blocks); + + lv_label_set_static_text(lb_desc, + "#00DDFF CID:#\n" + "Vendor ID:\n" + "Model:\n" + "Prod Rev:\n" + "S/N:\n" + "Month/Year:\n\n" + "#00DDFF Ext CSD:#\n" + "Cmd Classes:\n" + "Max Rate:\n" + "Current Rate:\n" + "Type Support:\n\n" + "Write Cache:\n" + "Enhanced Area:\n" + "Estimated Life:\n" + "Reserved Used:" + ); + lv_obj_set_width(lb_desc, lv_obj_get_width(desc)); + + lv_obj_t *val = lv_cont_create(win, NULL); + lv_obj_set_size(val, LV_HOR_RES / 11 * 3, LV_VER_RES - (LV_DPI * 11 / 7) - 5); + + lv_obj_t * lb_val = lv_label_create(val, lb_desc); + + lv_label_set_text(lb_val, txt_buf); + + lv_obj_set_width(lb_val, lv_obj_get_width(val)); + lv_obj_align(val, desc, LV_ALIGN_OUT_RIGHT_MID, 0, 0); + + lv_obj_t *desc2 = lv_cont_create(win, NULL); + lv_obj_set_size(desc2, LV_HOR_RES / 2 / 4 * 4, LV_VER_RES - (LV_DPI * 11 / 7) - 5); + + lv_obj_t * lb_desc2 = lv_label_create(desc2, lb_desc); + lv_label_set_style(lb_desc2, &monospace_text); + + u32 boot_size = emmc_storage.ext_csd.boot_mult << 17; + u32 rpmb_size = emmc_storage.ext_csd.rpmb_mult << 17; + strcpy(txt_buf, "#00DDFF eMMC Physical Partitions:#\n"); + s_printf(txt_buf + strlen(txt_buf), "1: #96FF00 BOOT0# Size: %6d KiB Sectors: 0x%08X\n", boot_size / 1024, boot_size / EMMC_BLOCKSIZE); + s_printf(txt_buf + strlen(txt_buf), "2: #96FF00 BOOT1# Size: %6d KiB Sectors: 0x%08X\n", boot_size / 1024, boot_size / EMMC_BLOCKSIZE); + s_printf(txt_buf + strlen(txt_buf), "3: #96FF00 RPMB# Size: %6d KiB Sectors: 0x%08X\n", rpmb_size / 1024, rpmb_size / EMMC_BLOCKSIZE); + s_printf(txt_buf + strlen(txt_buf), "0: #96FF00 GPP# Size: %6d MiB Sectors: 0x%08X\n", emmc_storage.sec_cnt >> SECTORS_TO_MIB_COEFF, emmc_storage.sec_cnt); + strcat(txt_buf, "\n#00DDFF GPP (eMMC USER) Partition Table:#\n"); + + emmc_set_partition(EMMC_GPP); + LIST_INIT(gpt); + emmc_gpt_parse(&gpt); + + u32 idx = 0; + int lines_left = 20; + s_printf(txt_buf + strlen(txt_buf), "#FFBA00 Idx Name Size Offset Sectors#\n"); + LIST_FOREACH_ENTRY(emmc_part_t, part, &gpt, link) + { + int lines = strlen(part->name) > 25 ? 2 : 1; + if ((lines_left - lines) <= 0) + { + strcat(txt_buf, "#FFDD00 Table does not fit on screen!#"); + break; + } + + if (lines == 2) + { + s_printf(txt_buf + strlen(txt_buf), "%02d: #96FF00 %s#\n %6d MiB %8Xh %8Xh\n", + part->index, part->name, (part->lba_end - part->lba_start + 1) >> SECTORS_TO_MIB_COEFF, + part->lba_start, part->lba_end - part->lba_start + 1); + } + else + { + s_printf(txt_buf + strlen(txt_buf), "%02d: #96FF00 %.25s# %6d MiB %8Xh %8Xh\n", + part->index, part->name, (part->lba_end - part->lba_start + 1) >> SECTORS_TO_MIB_COEFF, + part->lba_start, part->lba_end - part->lba_start + 1); + } + + lines_left -= lines; + idx++; + } + if (!idx) + strcat(txt_buf, "#FFDD00 Partition table is empty!#"); + + emmc_gpt_free(&gpt); + + lv_label_set_text(lb_desc2, txt_buf); + lv_obj_set_width(lb_desc2, lv_obj_get_width(desc2)); + lv_obj_align(desc2, val, LV_ALIGN_OUT_RIGHT_MID, LV_DPI / 6, 0); + + emmc_errors = emmc_get_error_count(); + if (emmc_get_mode() < EMMC_MMC_HS400 || + emmc_errors[EMMC_ERROR_INIT_FAIL] || + emmc_errors[EMMC_ERROR_RW_FAIL] || + emmc_errors[EMMC_ERROR_RW_RETRY]) + { +out_error: + lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL); + lv_obj_set_style(dark_bg, &mbox_darken); + lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); + + static const char * mbox_btn_map[] = { "\251", "\222OK", "\251", "" }; + lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); + lv_mbox_set_recolor_text(mbox, true); + + s_printf(txt_buf, + "#FF8000 eMMC Issues Warning#\n\n" + "#FFDD00 Your eMMC is initialized in a slower mode,#\n" + "#FFDD00 or init/read/write errors occurred!#\n" + "#FFDD00 This might mean hardware issues!#\n\n" + "#00DDFF Bus Speed:# %d MB/s\n\n" + "#00DDFF SDMMC4 Errors:#\n" + "Init fails: %d\n" + "Read/Write fails: %d\n" + "Read/Write errors: %d", + emmc_storage.csd.busspeed, + emmc_errors[EMMC_ERROR_INIT_FAIL], + emmc_errors[EMMC_ERROR_RW_FAIL], + emmc_errors[EMMC_ERROR_RW_RETRY]); + + lv_mbox_set_text(mbox, txt_buf); + lv_mbox_add_btns(mbox, mbox_btn_map, mbox_action); + lv_obj_set_width(mbox, LV_HOR_RES / 9 * 5); + lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); + lv_obj_set_top(mbox, true); + } + + emmc_end(); free(txt_buf); return LV_RES_OK; @@ -1768,7 +1952,7 @@ static lv_res_t _create_window_sdcard_info_status(lv_obj_t *btn) lv_win_add_btn(win, NULL, SYMBOL_SD" Benchmark", _create_mbox_sd_bench); lv_obj_t *desc = lv_cont_create(win, NULL); - lv_obj_set_size(desc, LV_HOR_RES / 2 / 5 * 2, LV_VER_RES - (LV_DPI * 11 / 8) * 5 / 2); + lv_obj_set_size(desc, LV_HOR_RES / 2 / 6 * 2, LV_VER_RES - (LV_DPI * 11 / 8) * 5 / 2); lv_obj_t * lb_desc = lv_label_create(desc, NULL); lv_label_set_long_mode(lb_desc, LV_LABEL_LONG_BREAK); @@ -1783,298 +1967,384 @@ static lv_res_t _create_window_sdcard_info_status(lv_obj_t *btn) manual_system_maintenance(true); if (!sd_mount()) - lv_label_set_text(lb_desc, "#FFDD00 Failed to init SD!#"); - else { - lv_label_set_text(lb_desc, - "#00DDFF Card IDentification:#\n" - "Vendor ID:\n" - "Model:\n" - "OEM ID:\n" - "HW rev:\n" - "FW rev:\n" - "S/N:\n" - "Month/Year:\n\n" - "Bootloader bus:" - ); - - lv_obj_t *val = lv_cont_create(win, NULL); - lv_obj_set_size(val, LV_HOR_RES / 9 * 2, LV_VER_RES - (LV_DPI * 11 / 8) * 5 / 2); - - lv_obj_t * lb_val = lv_label_create(val, lb_desc); - - char *txt_buf = (char *)malloc(0x4000); - txt_buf[0] = '\n'; - txt_buf[1] = 0; - - // Identify manufacturer. - switch (sd_storage.cid.manfid) - { - case 0x00: - strcat(txt_buf, "Fake "); - break; - case 0x01: - strcat(txt_buf, "Panasonic "); - break; - case 0x02: - strcat(txt_buf, "Toshiba "); - break; - case 0x03: - strcat(txt_buf, "SanDisk "); - break; - case 0x06: - strcat(txt_buf, "Ritek "); - break; - case 0x09: - strcat(txt_buf, "ATP "); - break; - case 0x13: - strcat(txt_buf, "Kingmax "); - break; - case 0x19: - strcat(txt_buf, "Dynacard "); - break; - case 0x1A: - strcat(txt_buf, "Power Quotient "); - break; - case 0x1B: - strcat(txt_buf, "Samsung "); - break; - case 0x1D: - strcat(txt_buf, "AData "); - break; - case 0x27: - strcat(txt_buf, "Phison "); - break; - case 0x28: - strcat(txt_buf, "Barun Electronics "); - break; - case 0x31: - strcat(txt_buf, "Silicon Power "); - break; - case 0x41: - strcat(txt_buf, "Kingston "); - break; - case 0x51: - strcat(txt_buf, "STEC "); - break; - case 0x5D: - strcat(txt_buf, "SwissBit "); - break; - case 0x61: - strcat(txt_buf, "Netlist "); - break; - case 0x63: - strcat(txt_buf, "Cactus "); - break; - case 0x73: - strcat(txt_buf, "Bongiovi "); - break; - case 0x74: - strcat(txt_buf, "Jiaelec "); - break; - case 0x76: - strcat(txt_buf, "Patriot "); - break; - case 0x82: - strcat(txt_buf, "Jiang Tay "); - break; - case 0x83: - strcat(txt_buf, "Netcom "); - break; - case 0x84: - strcat(txt_buf, "Strontium "); - break; - //TODO: Investigate which OEM/ODM makes these. - case 0x9C: // BE, Angelbird | Barun Electronics? What about 0x28? - // LX512 SO, Lexar, Angelbird, Hoodman, Sony | Solidgear? - strcat(txt_buf, "Solidgear "); - break; - case 0x9F: - strcat(txt_buf, "Taishin "); - break; - case 0xAD: // Lexar LX512 LS. Longsys? - strcat(txt_buf, "Longsys "); - break; - default: - strcat(txt_buf, "Unknown "); - break; - } - - s_printf(txt_buf + strlen(txt_buf), "(%02X)\n%c%c%c%c%c\n%c%c\n%X\n%X\n%08x\n%02d/%04d\n\n", - sd_storage.cid.manfid, - sd_storage.cid.prod_name[0], sd_storage.cid.prod_name[1], sd_storage.cid.prod_name[2], - sd_storage.cid.prod_name[3], sd_storage.cid.prod_name[4], - (sd_storage.cid.oemid >> 8) & 0xFF, sd_storage.cid.oemid & 0xFF, - sd_storage.cid.hwrev, sd_storage.cid.fwrev, sd_storage.cid.serial, - sd_storage.cid.month, sd_storage.cid.year); - - switch (nyx_str->info.sd_init) - { - case SD_1BIT_HS25: - strcat(txt_buf, "HS25 1bit"); - break; - case SD_4BIT_HS25: - strcat(txt_buf, "HS25"); - break; - case SD_UHS_SDR82: // Report as SDR104. - case SD_UHS_SDR104: - strcat(txt_buf, "SDR104"); - break; - case 0: - default: - strcat(txt_buf, "Undefined"); - break; - } - - lv_label_set_text(lb_val, txt_buf); - - lv_obj_set_width(lb_val, lv_obj_get_width(val)); - lv_obj_align(val, desc, LV_ALIGN_OUT_RIGHT_MID, 0, 0); - - lv_obj_t *desc2 = lv_cont_create(win, NULL); - lv_obj_set_size(desc2, LV_HOR_RES / 2 / 4 * 2, LV_VER_RES - (LV_DPI * 11 / 8) * 5 / 2); - - lv_obj_t * lb_desc2 = lv_label_create(desc2, lb_desc); - - lv_label_set_static_text(lb_desc2, - "#00DDFF Card-Specific Data#\n" - "Cmd Classes:\n" - "Capacity:\n" - "Capacity (LBA):\n" - "Bus Width:\n" - "Current Rate:\n" - "Speed Class:\n" - "UHS Grade:\n" - "Video Class:\n" - "App perf class:\n" - "Write Protect:" - ); - lv_obj_set_width(lb_desc2, lv_obj_get_width(desc2)); - lv_obj_align(desc2, val, LV_ALIGN_OUT_RIGHT_MID, LV_DPI / 2, 0); - - lv_obj_t *val2 = lv_cont_create(win, NULL); - lv_obj_set_size(val2, LV_HOR_RES / 13 * 3, LV_VER_RES - (LV_DPI * 11 / 8) * 5 / 2); - - lv_obj_t * lb_val2 = lv_label_create(val2, lb_desc); - - char *wp_info; - switch (sd_storage.csd.write_protect) - { - case 1: - wp_info = "Temporary"; - break; - case 2: - case 3: - wp_info = "Permanent"; - break; - default: - wp_info = "None"; - break; - } - - bool uhs_au_mb = false; - u32 uhs_au_size = sd_storage_get_ssr_au(&sd_storage); - if (uhs_au_size >= 1024) - { - uhs_au_mb = true; - uhs_au_size /= 1024; - } - - s_printf(txt_buf, - "#00DDFF v%d.0#\n%02X\n%d MiB\n%X (CP %X)\n%d\n%d MB/s (%d MHz)\n%d (AU: %d %s\nU%d\nV%d\nA%d\n%s", - sd_storage.csd.structure + 1, sd_storage.csd.cmdclass, - sd_storage.sec_cnt >> 11, sd_storage.sec_cnt, sd_storage.ssr.protected_size >> 9, - sd_storage.ssr.bus_width, sd_storage.csd.busspeed, - (sd_storage.csd.busspeed > 10) ? (sd_storage.csd.busspeed * 2) : 50, - sd_storage.ssr.speed_class, uhs_au_size, uhs_au_mb ? "MiB)" : "KiB)", sd_storage.ssr.uhs_grade, - sd_storage.ssr.video_class, sd_storage.ssr.app_class, wp_info); - - lv_label_set_text(lb_val2, txt_buf); - - lv_obj_set_width(lb_val2, lv_obj_get_width(val2)); - lv_obj_align(val2, desc2, LV_ALIGN_OUT_RIGHT_MID, 0, 0); - - lv_obj_t *line_sep = lv_line_create(win, NULL); - static const lv_point_t line_pp[] = { {0, 0}, { LV_HOR_RES - (LV_DPI - (LV_DPI / 4)) * 12, 0} }; - lv_line_set_points(line_sep, line_pp, 2); - lv_line_set_style(line_sep, lv_theme_get_current()->line.decor); - lv_obj_align(line_sep, desc, LV_ALIGN_OUT_BOTTOM_LEFT, LV_DPI * 410 / 100, LV_DPI / 7); - - lv_obj_t *desc3 = lv_cont_create(win, NULL); - lv_obj_set_size(desc3, LV_HOR_RES / 2 / 2 * 2, LV_VER_RES - (LV_DPI * 11 / 8) * 4); - - lv_obj_t * lb_desc3 = lv_label_create(desc3, lb_desc); - lv_label_set_text(lb_desc3, "#D4FF00 Acquiring FAT volume info...#"); - lv_obj_set_width(lb_desc3, lv_obj_get_width(desc3)); - - lv_obj_align(desc3, desc, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 2); - - manual_system_maintenance(true); - - f_getfree("", &sd_fs.free_clst, NULL); - - lv_label_set_text(lb_desc3, - "#00DDFF Found FAT volume:#\n" - "Filesystem:\n" - "Cluster:\n" - "Free:" - ); - lv_obj_set_size(desc3, LV_HOR_RES / 2 / 5 * 2, LV_VER_RES - (LV_DPI * 11 / 8) * 4); - lv_obj_set_width(lb_desc3, lv_obj_get_width(desc3)); - lv_obj_align(desc3, desc, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 2); - - lv_obj_t *val3 = lv_cont_create(win, NULL); - lv_obj_set_size(val3, LV_HOR_RES / 13 * 3, LV_VER_RES - (LV_DPI * 11 / 8) * 4); - - lv_obj_t * lb_val3 = lv_label_create(val3, lb_desc); - - s_printf(txt_buf, "\n%s\n%d %s\n%d MiB", - sd_fs.fs_type == FS_EXFAT ? ("exFAT "SYMBOL_SHRK) : ("FAT32"), - (sd_fs.csize > 1) ? (sd_fs.csize >> 1) : 512, - (sd_fs.csize > 1) ? "KiB" : "B", - sd_fs.free_clst * sd_fs.csize >> SECTORS_TO_MIB_COEFF); - - lv_label_set_text(lb_val3, txt_buf); - - lv_obj_set_width(lb_val3, lv_obj_get_width(val3)); - lv_obj_align(val3, desc3, LV_ALIGN_OUT_RIGHT_MID, 0, 0); - - lv_obj_t *desc4 = lv_cont_create(win, NULL); - lv_obj_set_size(desc4, LV_HOR_RES / 2 / 2 * 2, LV_VER_RES - (LV_DPI * 11 / 8) * 4); - - lv_obj_t * lb_desc4 = lv_label_create(desc4, lb_desc); - lv_label_set_text(lb_desc4, "#D4FF00 Acquiring FAT volume info...#"); - lv_obj_set_width(lb_desc4, lv_obj_get_width(desc4)); - - lv_label_set_text(lb_desc4, - "#00DDFF SDMMC1 Errors:#\n" - "Init fails:\n" - "Read/Write fails:\n" - "Read/Write errors:" - ); - lv_obj_set_size(desc4, LV_HOR_RES / 2 / 5 * 2, LV_VER_RES - (LV_DPI * 11 / 8) * 4); - lv_obj_set_width(lb_desc4, lv_obj_get_width(desc4)); - lv_obj_align(desc4, val3, LV_ALIGN_OUT_RIGHT_MID, LV_DPI / 2, 0); - - lv_obj_t *val4 = lv_cont_create(win, NULL); - lv_obj_set_size(val4, LV_HOR_RES / 13 * 3, LV_VER_RES - (LV_DPI * 11 / 8) * 4); - - lv_obj_t * lb_val4 = lv_label_create(val4, lb_desc); - - u16 *sd_errors = sd_get_error_count(); - s_printf(txt_buf, "\n%d (%d)\n%d (%d)\n%d (%d)", - sd_errors[0], nyx_str->info.sd_errors[0], sd_errors[1], nyx_str->info.sd_errors[1], sd_errors[2], nyx_str->info.sd_errors[2]); - - lv_label_set_text(lb_val4, txt_buf); - - lv_obj_set_width(lb_val4, lv_obj_get_width(val4)); - lv_obj_align(val4, desc4, LV_ALIGN_OUT_RIGHT_MID, LV_DPI / 2, 0); - - free(txt_buf); - sd_unmount(); + lv_label_set_text(lb_desc, "#FFDD00 Failed to init SD!#"); + goto failed; } + lv_label_set_text(lb_desc, + "#00DDFF Card ID:#\n" + "Vendor ID:\n" + "Model:\n" + "OEM ID:\n" + "HW rev:\n" + "FW rev:\n" + "S/N:\n" + "Month/Year:\n\n" + "Max Power:\n" + "Initial bus:" + ); + + lv_obj_t *val = lv_cont_create(win, NULL); + lv_obj_set_size(val, LV_HOR_RES / 12 * 3, LV_VER_RES - (LV_DPI * 11 / 8) * 5 / 2); + + lv_obj_t * lb_val = lv_label_create(val, lb_desc); + + char *txt_buf = (char *)malloc(SZ_16K); + txt_buf[0] = '\n'; + txt_buf[1] = 0; + + // Identify manufacturer. + switch (sd_storage.cid.manfid) + { + case 0x00: + strcat(txt_buf, "Fake "); + break; + case 0x01: + strcat(txt_buf, "Panasonic "); + break; + case 0x02: + strcat(txt_buf, "Toshiba "); + break; + case 0x03: + if (!memcmp(&sd_storage.cid.oemid, "DW", 2)) + strcat(txt_buf, "Western Digital "); // WD. + else + strcat(txt_buf, "SanDisk "); + break; + case 0x06: + strcat(txt_buf, "Ritek "); + break; + case 0x09: + strcat(txt_buf, "ATP "); + break; + case 0x13: + strcat(txt_buf, "Kingmax "); + break; + case 0x19: + strcat(txt_buf, "Dynacard "); + break; + case 0x1A: + strcat(txt_buf, "Power Quotient "); + break; + case 0x1B: + strcat(txt_buf, "Samsung "); + break; + case 0x1D: + strcat(txt_buf, "AData "); + break; + case 0x27: + strcat(txt_buf, "Phison "); + break; + case 0x28: + strcat(txt_buf, "Barun Electronics "); + break; + case 0x31: + strcat(txt_buf, "Silicon Power "); + break; + case 0x41: + strcat(txt_buf, "Kingston "); + break; + case 0x51: + strcat(txt_buf, "STEC "); + break; + case 0x5D: + strcat(txt_buf, "SwissBit "); + break; + case 0x61: + strcat(txt_buf, "Netlist "); + break; + case 0x63: + strcat(txt_buf, "Cactus "); + break; + case 0x73: + strcat(txt_buf, "Bongiovi "); + break; + case 0x74: + strcat(txt_buf, "Jiaelec "); + break; + case 0x76: + strcat(txt_buf, "Patriot "); + break; + case 0x82: + strcat(txt_buf, "Jiang Tay "); + break; + case 0x83: + strcat(txt_buf, "Netcom "); + break; + case 0x84: + strcat(txt_buf, "Strontium "); + break; + case 0x9C: + if (!memcmp(&sd_storage.cid.oemid, "OS", 2)) + strcat(txt_buf, "Sony "); // SO. + else + strcat(txt_buf, "Barun Electronics "); // BE. + break; + case 0x9F: + strcat(txt_buf, "Taishin "); + break; + case 0xAD: + strcat(txt_buf, "Longsys "); + break; + default: + strcat(txt_buf, "Unknown "); + break; + } + + // UHS-I max power limit is 400mA, no matter what the card says. + u32 max_power_nominal = sd_storage.max_power > 400 ? 400 : sd_storage.max_power; + + s_printf(txt_buf + strlen(txt_buf), "(%02X)\n%c%c%c%c%c\n%c%c (%04X)\n%X\n%X\n%08x\n%02d/%04d\n\n%d mW (%d mA)\n", + sd_storage.cid.manfid, + sd_storage.cid.prod_name[0], sd_storage.cid.prod_name[1], sd_storage.cid.prod_name[2], + sd_storage.cid.prod_name[3], sd_storage.cid.prod_name[4], + (sd_storage.cid.oemid >> 8) & 0xFF, sd_storage.cid.oemid & 0xFF, sd_storage.cid.oemid, + sd_storage.cid.hwrev, sd_storage.cid.fwrev, sd_storage.cid.serial, + sd_storage.cid.month, sd_storage.cid.year, + max_power_nominal * 3600 / 1000, sd_storage.max_power); + + switch (nyx_str->info.sd_init) + { + case SD_1BIT_HS25: + strcat(txt_buf, "HS25 1bit"); + break; + case SD_4BIT_HS25: + strcat(txt_buf, "HS25"); + break; + case SD_UHS_SDR82: // Report as SDR104. + case SD_UHS_SDR104: + strcat(txt_buf, "SDR104"); + break; + case 0: + default: + strcat(txt_buf, "Undefined"); + break; + } + + lv_label_set_text(lb_val, txt_buf); + + lv_obj_set_width(lb_val, lv_obj_get_width(val)); + lv_obj_align(val, desc, LV_ALIGN_OUT_RIGHT_MID, 0, 0); + + lv_obj_t *desc2 = lv_cont_create(win, NULL); + lv_obj_set_size(desc2, LV_HOR_RES / 2 / 11 * 5, LV_VER_RES - (LV_DPI * 11 / 8) * 5 / 2); + + lv_obj_t * lb_desc2 = lv_label_create(desc2, lb_desc); + + lv_label_set_static_text(lb_desc2, + "#00DDFF Card-Specific Data#\n" + "Cmd Classes:\n" + "Capacity:\n" + "Capacity (LBA):\n" + "Bus Width:\n" + "Current Rate:\n" + "Speed Class:\n" + "UHS Classes:\n" + "Max Bus Speed:\n\n" + "Write Protect:" + ); + lv_obj_set_width(lb_desc2, lv_obj_get_width(desc2)); + lv_obj_align(desc2, val, LV_ALIGN_OUT_RIGHT_MID, LV_DPI / 5 * 3, 0); + + lv_obj_t *val2 = lv_cont_create(win, NULL); + lv_obj_set_size(val2, LV_HOR_RES / 4, LV_VER_RES - (LV_DPI * 11 / 8) * 5 / 2); + + lv_obj_t * lb_val2 = lv_label_create(val2, lb_desc); + + char *wp_info; + switch (sd_storage.csd.write_protect) + { + case 1: + wp_info = "Temporary"; + break; + case 2: + case 3: + wp_info = "Permanent"; + break; + default: + wp_info = "None"; + break; + } + + bool uhs_au_mb = false; + u32 uhs_au_size = sd_storage_get_ssr_au(&sd_storage); + if (uhs_au_size >= 1024) + { + uhs_au_mb = true; + uhs_au_size /= 1024; + } + + sd_func_modes_t fmodes = { 0 }; + sd_storage_get_fmodes(&sd_storage, NULL, &fmodes); + + char *bus_speed; + if (fmodes.cmd_system & SD_MODE_UHS_DDR200) + bus_speed = "DDR200"; + else if (fmodes.access_mode & SD_MODE_UHS_SDR104) + bus_speed = "SDR104"; + else if (fmodes.access_mode & SD_MODE_UHS_SDR50) + bus_speed = "SDR50"; + else if (fmodes.access_mode & SD_MODE_UHS_DDR50) + bus_speed = "DDR50"; + else if (fmodes.access_mode & SD_MODE_UHS_SDR25) + bus_speed = "SDR25"; + else + bus_speed = "SDR12"; + + char *cpe = NULL; + if (sd_storage.ssr.app_class == 2) + { + u8 *buf = zalloc(512); + + // Directly get and parse ext reg for performance enhance. + sd_storage_parse_perf_enhance(&sd_storage, 2, 0, 0, buf); + + bool has_perf_enhance = sd_storage.ser.cache && + sd_storage.ser.cmdq && + sd_storage.ser.cache == sd_storage.ser.cache_ext && + sd_storage.ser.cmdq == sd_storage.ser.cmdq_ext; + if (has_perf_enhance) + cpe = "#FFDD00 "; // CMDQ/CACHE support via a quirk. + else + cpe = "#FF3C28 "; // Broken. + + // Get and parse ext reg for performance enhance in spec. + sd_storage_get_ext_regs(&sd_storage, buf); + + if (sd_storage.ser.valid) + { + has_perf_enhance = sd_storage.ser.cache && + sd_storage.ser.cmdq && + sd_storage.ser.cache == sd_storage.ser.cache_ext && + sd_storage.ser.cmdq == sd_storage.ser.cmdq_ext; + + if (has_perf_enhance) + cpe = NULL; // CMDQ/CACHE support in spec. + else + cpe = "#FF3C28 "; // Broken. + } + + free(buf); + } + + s_printf(txt_buf, + "#00DDFF v%d.0#\n" + "%02X\n" + "%d MiB\n" + "%X (CP %X)\n" + "%d\n" + "%d MB/s (%d MHz)\n" + "%d (AU: %d %s\n" + "U%d V%d %sA%d%s\n" + "%s\n\n" + "%s", + sd_storage.csd.structure + 1, + sd_storage.csd.cmdclass, + sd_storage.sec_cnt >> 11, + sd_storage.sec_cnt, sd_storage.ssr.protected_size >> 9, + sd_storage.ssr.bus_width, + sd_storage.csd.busspeed, + (sd_storage.csd.busspeed > 10) ? (sd_storage.csd.busspeed * 2) : 50, + sd_storage.ssr.speed_class, uhs_au_size, uhs_au_mb ? "MiB)" : "KiB)", + sd_storage.ssr.uhs_grade, sd_storage.ssr.video_class, cpe ? cpe : "", sd_storage.ssr.app_class, cpe ? "#" : "", + bus_speed, + wp_info); + + lv_label_set_text(lb_val2, txt_buf); + + lv_obj_set_width(lb_val2, lv_obj_get_width(val2)); + lv_obj_align(val2, desc2, LV_ALIGN_OUT_RIGHT_MID, 0, 0); + + lv_obj_t *line_sep = lv_line_create(win, NULL); + static const lv_point_t line_pp[] = { {0, 0}, { LV_HOR_RES - (LV_DPI - (LV_DPI / 4)) * 12, 0} }; + lv_line_set_points(line_sep, line_pp, 2); + lv_line_set_style(line_sep, lv_theme_get_current()->line.decor); + lv_obj_align(line_sep, desc, LV_ALIGN_OUT_BOTTOM_LEFT, LV_DPI * 410 / 100, LV_DPI / 7); + + lv_obj_t *desc3 = lv_cont_create(win, NULL); + lv_obj_set_size(desc3, LV_HOR_RES / 2 / 2 * 2, LV_VER_RES - (LV_DPI * 11 / 8) * 4); + + lv_obj_t * lb_desc3 = lv_label_create(desc3, lb_desc); + lv_label_set_text(lb_desc3, "#D4FF00 Acquiring info...#"); + lv_obj_set_width(lb_desc3, lv_obj_get_width(desc3)); + + lv_obj_align(desc3, desc, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 2); + + manual_system_maintenance(true); + + lv_obj_set_size(desc3, LV_HOR_RES / 2 / 6 * 2, LV_VER_RES - (LV_DPI * 11 / 8) * 4); + lv_obj_align(desc3, desc, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 2); + + lv_obj_t *val3 = lv_cont_create(win, NULL); + lv_obj_set_size(val3, LV_HOR_RES / 12 * 3, LV_VER_RES - (LV_DPI * 11 / 8) * 4); + + lv_obj_t * lb_val3 = lv_label_create(val3, lb_desc); + lv_label_set_text(lb_val3, ""); + + lv_obj_align(val3, desc3, LV_ALIGN_OUT_RIGHT_MID, 0, 0); + + lv_obj_t *desc4 = lv_cont_create(win, NULL); + lv_obj_set_size(desc4, LV_HOR_RES / 2 / 2 * 2, LV_VER_RES - (LV_DPI * 11 / 8) * 4); + + lv_obj_t * lb_desc4 = lv_label_create(desc4, lb_desc); + lv_label_set_text(lb_desc4, " "); + lv_obj_set_width(lb_desc4, lv_obj_get_width(desc4)); + + lv_label_set_text(lb_desc4, + "#00DDFF SDMMC1 Errors:#\n" + "Init fails:\n" + "Read/Write fails:\n" + "Read/Write errors:" + ); + lv_obj_set_size(desc4, LV_HOR_RES / 2 / 11 * 5, LV_VER_RES - (LV_DPI * 11 / 8) * 4); + lv_obj_set_width(lb_desc4, lv_obj_get_width(desc4)); + lv_obj_align(desc4, val3, LV_ALIGN_OUT_RIGHT_MID, LV_DPI / 5 * 3, 0); + + lv_obj_t *val4 = lv_cont_create(win, NULL); + lv_obj_set_size(val4, LV_HOR_RES / 4, LV_VER_RES - (LV_DPI * 11 / 8) * 4); + + lv_obj_t * lb_val4 = lv_label_create(val4, lb_desc); + + u16 *sd_errors = sd_get_error_count(); + s_printf(txt_buf, "\n%d (%d)\n%d (%d)\n%d (%d)", + sd_errors[SD_ERROR_INIT_FAIL], nyx_str->info.sd_errors[SD_ERROR_INIT_FAIL], + sd_errors[SD_ERROR_RW_FAIL], nyx_str->info.sd_errors[SD_ERROR_RW_FAIL], + sd_errors[SD_ERROR_RW_RETRY], nyx_str->info.sd_errors[SD_ERROR_RW_RETRY]); + + lv_label_set_text(lb_val4, txt_buf); + + lv_obj_set_width(lb_val4, lv_obj_get_width(val4)); + lv_obj_align(val4, desc4, LV_ALIGN_OUT_RIGHT_MID, 0, 0); + + manual_system_maintenance(true); + + f_getfree("", &sd_fs.free_clst, NULL); + + lv_label_set_text(lb_desc3, + "#00DDFF Found FAT FS:#\n" + "Filesystem:\n" + "Cluster:\n" + "Size free/total:" + ); + + lv_obj_set_width(lb_desc3, lv_obj_get_width(desc3)); + + s_printf(txt_buf, "\n%s\n%d %s\n%d/%d MiB", + sd_fs.fs_type == FS_EXFAT ? ("exFAT "SYMBOL_SHRK) : ("FAT32"), + (sd_fs.csize > 1) ? (sd_fs.csize >> 1) : SD_BLOCKSIZE, + (sd_fs.csize > 1) ? "KiB" : "B", + (u32)(sd_fs.free_clst * sd_fs.csize >> SECTORS_TO_MIB_COEFF), + (u32)(sd_fs.n_fatent * sd_fs.csize >> SECTORS_TO_MIB_COEFF)); + + lv_label_set_text(lb_val3, txt_buf); + + lv_obj_set_width(lb_val3, lv_obj_get_width(val3)); + + free(txt_buf); + sd_unmount(); + +failed: nyx_window_toggle_buttons(win, false); return LV_RES_OK; @@ -2116,36 +2386,33 @@ static lv_res_t _create_window_battery_status(lv_obj_t *btn) lv_obj_t * lb_val = lv_label_create(val, lb_desc); - char *txt_buf = (char *)malloc(0x4000); + char *txt_buf = (char *)malloc(SZ_16K); int value = 0; int cap_pct = 0; + // Fuel gauge IC info. max17050_get_property(MAX17050_RepSOC, &cap_pct); max17050_get_property(MAX17050_RepCap, &value); - s_printf(txt_buf, "\n%d mAh [%d %]\n", value, cap_pct >> 8); + s_printf(txt_buf, "\n%d mAh [%d %%]\n", value, cap_pct >> 8); max17050_get_property(MAX17050_FullCAP, &value); s_printf(txt_buf + strlen(txt_buf), "%d mAh\n", value); max17050_get_property(MAX17050_DesignCap, &value); - s_printf(txt_buf + strlen(txt_buf), "%d mAh\n", value); + bool design_cap_init = value == 1000; + s_printf(txt_buf + strlen(txt_buf), "%s%d mAh%s\n", + design_cap_init ? "#FF8000 " : "", value, design_cap_init ? " - Init "SYMBOL_WARNING"#" : ""); max17050_get_property(MAX17050_Current, &value); - if (value >= 0) - s_printf(txt_buf + strlen(txt_buf), "%d mA\n", value / 1000); - else - s_printf(txt_buf + strlen(txt_buf), "-%d mA\n", (~value + 1) / 1000); + s_printf(txt_buf + strlen(txt_buf), "%d mA\n", value / 1000); max17050_get_property(MAX17050_AvgCurrent, &value); - if (value >= 0) - s_printf(txt_buf + strlen(txt_buf), "%d mA\n", value / 1000); - else - s_printf(txt_buf + strlen(txt_buf), "-%d mA\n", (~value + 1) / 1000); + s_printf(txt_buf + strlen(txt_buf), "%d mA\n", value / 1000); max17050_get_property(MAX17050_VCELL, &value); bool voltage_empty = value < 3200; s_printf(txt_buf + strlen(txt_buf), "%s%d mV%s\n", - voltage_empty ? "#FF8000 " : "", value, voltage_empty ? " "SYMBOL_WARNING"#" : ""); + voltage_empty ? "#FF8000 " : "", value, voltage_empty ? " - Low "SYMBOL_WARNING"#" : ""); max17050_get_property(MAX17050_OCVInternal, &value); s_printf(txt_buf + strlen(txt_buf), "%d mV\n", value); @@ -2160,11 +2427,9 @@ static lv_res_t _create_window_battery_status(lv_obj_t *btn) s_printf(txt_buf + strlen(txt_buf), "%d mV\n", value); max17050_get_property(MAX17050_TEMP, &value); - if (value >= 0) - s_printf(txt_buf + strlen(txt_buf), "%d.%d oC\n\n\n", value / 10, value % 10); - else - s_printf(txt_buf + strlen(txt_buf), "-%d.%d oC\n\n\n", (~value + 1) / 10, (~value + 1) % 10); + s_printf(txt_buf + strlen(txt_buf), "%d.%d oC\n\n\n", value / 10, (value >= 0 ? value : (~value + 1)) % 10); + // Main Pmic IC info. value = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CID4); u32 main_pmic_version = i2c_recv_byte(I2C_5, MAX77620_I2C_ADDR, MAX77620_REG_CID3) & 0xF; @@ -2175,19 +2440,20 @@ static lv_res_t _create_window_battery_status(lv_obj_t *btn) else s_printf(txt_buf + strlen(txt_buf), "max77620 v%d\n#FF8000 Unknown OTP# (%02X)\n", main_pmic_version, value); - u32 cpu_gpu_pmic_type = h_cfg.t210b01 ? (FUSE(FUSE_RESERVED_ODM28_T210B01) & 1) + 1 : 0; + // CPU/GPU/DRAM Pmic IC info. + u32 cpu_gpu_pmic_type = h_cfg.t210b01 ? (FUSE(FUSE_RESERVED_ODM28_B01) & 1) + 1 : 0; switch (cpu_gpu_pmic_type) { case 0: s_printf(txt_buf + strlen(txt_buf), "max77621 v%d", - i2c_recv_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_CHIPID1_REG)); + i2c_recv_byte(I2C_5, MAX77621_CPU_I2C_ADDR, MAX77621_REG_CHIPID1)); break; case 1: - s_printf(txt_buf + strlen(txt_buf), "max77812-2 v%d", + s_printf(txt_buf + strlen(txt_buf), "max77812-2 v%d", // High power GPU. 2 Outputs, phases 3 1. i2c_recv_byte(I2C_5, MAX77812_PHASE31_CPU_I2C_ADDR, MAX77812_REG_VERSION) & 7); break; case 2: - s_printf(txt_buf + strlen(txt_buf), "max77812-3 v%d.0", + s_printf(txt_buf + strlen(txt_buf), "max77812-3 v%d.0", // Low power GPU. 3 Outputs, phases 2 1 1. i2c_recv_byte(I2C_5, MAX77812_PHASE211_CPU_I2C_ADDR, MAX77812_REG_VERSION) & 7); break; } @@ -2204,10 +2470,9 @@ static lv_res_t _create_window_battery_status(lv_obj_t *btn) lv_label_set_static_text(lb_desc2, "#00DDFF Battery Charger IC Info:#\n" - "Input voltage limit:\n" "Input current limit:\n" - "Min voltage limit:\n" - "Fast charge current limit:\n" + "System voltage limit:\n" + "Charge current limit:\n" "Charge voltage limit:\n" "Charge status:\n" "Temperature status:\n\n" @@ -2224,12 +2489,10 @@ static lv_res_t _create_window_battery_status(lv_obj_t *btn) lv_obj_t * lb_val2 = lv_label_create(val2, lb_desc); - bq24193_get_property(BQ24193_InputVoltageLimit, &value); - s_printf(txt_buf, "\n%d mV\n", value); - + // Charger IC info. int iinlim = 0; bq24193_get_property(BQ24193_InputCurrentLimit, &iinlim); - s_printf(txt_buf + strlen(txt_buf), "%d mA\n", iinlim); + s_printf(txt_buf, "\n%d mA\n", iinlim); bq24193_get_property(BQ24193_SystemMinimumVoltage, &value); s_printf(txt_buf + strlen(txt_buf), "%d mV\n", value); @@ -2273,16 +2536,17 @@ static lv_res_t _create_window_battery_status(lv_obj_t *btn) strcat(txt_buf, "Cool"); break; case 5: - strcat(txt_buf, "Cold"); + strcat(txt_buf, "#FF8000 Cold#"); break; case 6: - strcat(txt_buf, "Hot"); + strcat(txt_buf, "#FF8000 Hot#"); break; default: s_printf(txt_buf + strlen(txt_buf), "Unknown (%d)", value); break; } + // USB-PD IC info. bool inserted; u32 wattage = 0; usb_pd_objects_t usb_pd; @@ -2298,8 +2562,8 @@ static lv_res_t _create_window_battery_status(lv_obj_t *btn) if (!usb_pd.pdo_no) strcat(txt_buf, "\nNon PD"); - // Limit to 5 profiles so it can fit. - usb_pd.pdo_no = MIN(usb_pd.pdo_no, 5); + // Limit to 6 profiles so it can fit. + usb_pd.pdo_no = MIN(usb_pd.pdo_no, 6); for (u32 i = 0; i < usb_pd.pdo_no; i++) { @@ -2450,7 +2714,7 @@ void create_tab_info(lv_theme_t *th, lv_obj_t *parent) lv_btn_set_fit(btn3, true, true); lv_label_set_static_text(label_btn, SYMBOL_CIRCUIT" HW & Fuses"); lv_obj_align(btn3, line_sep, LV_ALIGN_OUT_BOTTOM_LEFT, LV_DPI / 4, LV_DPI / 2); - lv_btn_set_action(btn3, LV_BTN_ACTION_CLICK, _create_window_fuses_info_status); + lv_btn_set_action(btn3, LV_BTN_ACTION_CLICK, _create_window_hw_info_status); // Create KFuses button. lv_obj_t *btn4 = lv_btn_create(h1, btn); diff --git a/nyx/nyx_gui/frontend/gui_info.h b/nyx/nyx_gui/frontend/gui_info.h index ac64cbd..d0f102e 100644 --- a/nyx/nyx_gui/frontend/gui_info.h +++ b/nyx/nyx_gui/frontend/gui_info.h @@ -20,5 +20,6 @@ #include void create_tab_info(lv_theme_t *th, lv_obj_t *parent); +int dump_cal0(); #endif diff --git a/nyx/nyx_gui/frontend/gui_options.c b/nyx/nyx_gui/frontend/gui_options.c index 854bb64..15feeac 100644 --- a/nyx/nyx_gui/frontend/gui_options.c +++ b/nyx/nyx_gui/frontend/gui_options.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2025 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,18 +16,17 @@ #include +#include + #include "gui.h" +#include "gui_info.h" #include "../config.h" -#include -#include -#include +#include #include -#include -#include -#include -#include -#include -#include + +#define CLOCK_MIN_YEAR 2025 +#define CLOCK_MAX_YEAR (CLOCK_MIN_YEAR + 10) +#define CLOCK_YEARLIST "2025\n2026\n2027\n2028\n2029\n2030\n2031\n2032\n2033\n2034\n2035" extern hekate_config h_cfg; extern nyx_config n_cfg; @@ -116,7 +115,7 @@ lv_obj_t *create_window_autoboot(const char *win_title) static lv_style_t win_bg_style; lv_style_copy(&win_bg_style, &lv_style_plain); - win_bg_style.body.main_color = LV_COLOR_HEX(0x2D2D2D);// TODO: COLOR_HOS_BG + win_bg_style.body.main_color = LV_COLOR_HEX(theme_bg_color); win_bg_style.body.grad_color = win_bg_style.body.main_color; lv_obj_t *win = lv_win_create(lv_scr_act(), NULL); @@ -129,7 +128,6 @@ lv_obj_t *create_window_autoboot(const char *win_title) return win; } -// TODO: instant update of button for these. static lv_res_t _autoboot_disable_action(lv_obj_t *btn) { h_cfg.autoboot = 0; @@ -143,6 +141,8 @@ static lv_res_t _autoboot_disable_action(lv_obj_t *btn) lv_obj_del(win); + close_btn = NULL; + return LV_RES_OK; } @@ -162,6 +162,8 @@ static lv_res_t _autoboot_enable_main_action(lv_obj_t *btn) obj = lv_obj_get_parent(obj); lv_obj_del(obj); + close_btn = NULL; + return LV_RES_INV; } @@ -179,6 +181,8 @@ static lv_res_t _autoboot_enable_more_action(lv_obj_t *btn) obj = lv_obj_get_parent(obj); lv_obj_del(obj); + close_btn = NULL; + return LV_RES_INV; } @@ -225,6 +229,7 @@ static void _create_autoboot_window() sd_mount(); + // Parse hekate main configuration. LIST_INIT(ini_sections); if (ini_parse(&ini_sections, "bootloader/hekate_ipl.ini", false)) { @@ -235,6 +240,8 @@ static void _create_autoboot_window() lv_list_add(list_main, NULL, ini_sec->name, _autoboot_enable_main_action); } + + ini_free(&ini_sections); } // More configuration container. @@ -266,6 +273,7 @@ static void _create_autoboot_window() lv_obj_set_size(list_more_cfg, LV_HOR_RES * 4 / 10, LV_VER_RES * 4 / 7); lv_list_set_single_mode(list_more_cfg, true); + // Parse all .ini files in ini folder. LIST_INIT(ini_list_sections); if (ini_parse(&ini_list_sections, "bootloader/ini", true)) { @@ -276,6 +284,8 @@ static void _create_autoboot_window() lv_list_add(list_more_cfg, NULL, ini_sec->name, _autoboot_enable_more_action); } + + ini_free(&ini_list_sections); } sd_unmount(); @@ -330,9 +340,24 @@ static lv_res_t _data_verification_action(lv_obj_t *ddlist) return LV_RES_OK; } +static lv_res_t _entries_columns_action(lv_obj_t *btn) +{ + n_cfg.entries_5_col = !n_cfg.entries_5_col; + nyx_changes_made = true; + + if (!n_cfg.entries_5_col) + lv_btn_set_state(btn, LV_BTN_STATE_REL); + else + lv_btn_set_state(btn, LV_BTN_STATE_TGL_REL); + + nyx_generic_onoff_toggle(btn); + + return LV_RES_OK; +} + static lv_res_t _save_nyx_options_action(lv_obj_t *btn) { - static const char * mbox_btn_map[] = {"\211", "\222OK!", "\211", ""}; + static const char * mbox_btn_map[] = {"\251", "\222OK!", "\251", ""}; lv_obj_t * mbox = lv_mbox_create(lv_scr_act(), NULL); lv_mbox_set_recolor_text(mbox, true); @@ -384,7 +409,11 @@ void create_flat_button(lv_obj_t *parent, lv_obj_t *btn, lv_color_t color, lv_ac typedef struct _color_test_ctxt { + u32 bg; u16 hue; + lv_obj_t *window; + lv_obj_t *header1; + lv_obj_t *header2; lv_obj_t *label; lv_obj_t *icons; lv_obj_t *slider; @@ -397,38 +426,78 @@ color_test_ctxt color_test; static lv_res_t _save_theme_color_action(lv_obj_t *btn) { - n_cfg.themecolor = color_test.hue; + n_cfg.theme_bg = color_test.bg; + n_cfg.theme_color = color_test.hue; // Save nyx config. create_nyx_config_entry(true); - reload_nyx(); + reload_nyx(NULL, false); return LV_RES_OK; } -static void _test_nyx_color(u16 hue) +static void _show_new_nyx_color(u32 bg, u16 hue, bool update_bg) { - lv_color_t color = lv_color_hsv_to_rgb(hue, 100, 100); - static lv_style_t btn_tgl_test; - lv_style_copy(&btn_tgl_test, lv_btn_get_style(color_test.button, LV_BTN_STATE_TGL_PR)); - btn_tgl_test.body.border.color = color; - btn_tgl_test.text.color = color; - lv_btn_set_style(color_test.button, LV_BTN_STATE_TGL_PR, &btn_tgl_test); + lv_color_t bgc = LV_COLOR_HEX(bg); + lv_color_t bgc_light = LV_COLOR_HEX(bg ? (bg + 0x101010) : 0x2D2D2D); + lv_color_t bg_border = LV_COLOR_HEX(bg ? (bg + 0x202020) : 0x3D3D3D); + lv_color_t color = lv_color_hsv_to_rgb(hue, 100, 100); - static lv_style_t txt_test; - lv_style_copy(&txt_test, lv_label_get_style(color_test.label)); - txt_test.text.color = color; - lv_obj_set_style(color_test.label, &txt_test); - lv_obj_set_style(color_test.icons, &txt_test); + if (update_bg) + { + static lv_style_t win_bg_test; + lv_style_copy(&win_bg_test, lv_win_get_style(color_test.window, LV_WIN_STYLE_BG)); + win_bg_test.body.main_color = bgc; + win_bg_test.body.grad_color = win_bg_test.body.main_color; + lv_win_set_style(color_test.window, LV_WIN_STYLE_BG, &win_bg_test); - static lv_style_t slider_test, slider_ind; + static lv_style_t win_hdr_test; + lv_style_copy(&win_hdr_test, lv_win_get_style(color_test.window, LV_WIN_STYLE_HEADER)); + win_hdr_test.body.main_color = bgc; + win_hdr_test.body.grad_color = win_hdr_test.body.main_color; + lv_win_set_style(color_test.window, LV_WIN_STYLE_HEADER, &win_hdr_test); + + static lv_style_t hdr1_bg_test; + lv_style_copy(&hdr1_bg_test, lv_cont_get_style(color_test.header1)); + hdr1_bg_test.body.main_color = bgc; + hdr1_bg_test.body.grad_color = hdr1_bg_test.body.main_color; + lv_cont_set_style(color_test.header1, &hdr1_bg_test); + + static lv_style_t hdr2_bg_test; + lv_style_copy(&hdr2_bg_test, lv_cont_get_style(color_test.header2)); + hdr2_bg_test.body.main_color = bgc; + hdr2_bg_test.body.grad_color = hdr2_bg_test.body.main_color; + lv_cont_set_style(color_test.header2, &hdr2_bg_test); + } + else + { + static lv_style_t txt_test; + lv_style_copy(&txt_test, lv_label_get_style(color_test.label)); + txt_test.text.color = color; + lv_obj_set_style(color_test.label, &txt_test); + lv_obj_set_style(color_test.icons, &txt_test); + } + + static lv_style_t btn_tgl_pr_test; + lv_style_copy(&btn_tgl_pr_test, lv_btn_get_style(color_test.button, LV_BTN_STATE_TGL_PR)); + btn_tgl_pr_test.body.main_color = bgc_light; + btn_tgl_pr_test.body.grad_color = btn_tgl_pr_test.body.main_color; + btn_tgl_pr_test.body.border.color = color; + btn_tgl_pr_test.text.color = color; + lv_btn_set_style(color_test.button, LV_BTN_STATE_TGL_PR, &btn_tgl_pr_test); + + static lv_style_t slider_bg, slider_test, slider_ind; + lv_style_copy(&slider_bg, lv_slider_get_style(color_test.slider, LV_SLIDER_STYLE_BG)); lv_style_copy(&slider_test, lv_slider_get_style(color_test.slider, LV_SLIDER_STYLE_KNOB)); lv_style_copy(&slider_ind, lv_slider_get_style(color_test.slider, LV_SLIDER_STYLE_INDIC)); + slider_bg.body.main_color = bg_border; + slider_bg.body.grad_color = slider_bg.body.main_color; slider_test.body.main_color = color; slider_test.body.grad_color = slider_test.body.main_color; slider_ind.body.main_color = lv_color_hsv_to_rgb(hue, 100, 72); slider_ind.body.grad_color = slider_ind.body.main_color; + lv_slider_set_style(color_test.slider, LV_SLIDER_STYLE_BG, &slider_bg); lv_slider_set_style(color_test.slider, LV_SLIDER_STYLE_KNOB, &slider_test); lv_slider_set_style(color_test.slider, LV_SLIDER_STYLE_INDIC, &slider_ind); } @@ -438,7 +507,7 @@ static lv_res_t _slider_hue_action(lv_obj_t *slider) if (color_test.hue != lv_slider_get_value(slider)) { color_test.hue = lv_slider_get_value(slider); - _test_nyx_color(color_test.hue); + _show_new_nyx_color(color_test.bg, color_test.hue, false); char hue[8]; s_printf(hue, "%03d", color_test.hue); lv_label_set_text(color_test.hue_label, hue); @@ -447,6 +516,18 @@ static lv_res_t _slider_hue_action(lv_obj_t *slider) return LV_RES_OK; } +static lv_res_t _preset_bg_action(lv_obj_t *btn) +{ + //! TODO: Support a range? + if (color_test.bg) + color_test.bg = 0; + else + color_test.bg = COLOR_HOS_BG; + _show_new_nyx_color(color_test.bg, color_test.hue, true); + + return LV_RES_OK; +} + static lv_res_t _preset_hue_action(lv_obj_t *btn) { lv_btn_ext_t *ext = lv_obj_get_ext_attr(btn); @@ -454,7 +535,7 @@ static lv_res_t _preset_hue_action(lv_obj_t *btn) if (color_test.hue != ext->idx) { color_test.hue = ext->idx; - _test_nyx_color(color_test.hue); + _show_new_nyx_color(color_test.bg, color_test.hue, false); char hue[8]; s_printf(hue, "%03d", color_test.hue); lv_label_set_text(color_test.hue_label, hue); @@ -464,17 +545,20 @@ static lv_res_t _preset_hue_action(lv_obj_t *btn) return LV_RES_OK; } -const u16 theme_colors[17] = { +static const u16 theme_colors[17] = { 4, 13, 23, 33, 43, 54, 66, 89, 124, 167, 187, 200, 208, 231, 261, 291, 341 }; static lv_res_t _create_window_nyx_colors(lv_obj_t *btn) { - lv_obj_t *win = nyx_create_standard_window(SYMBOL_COPY" Choose a Nyx Color Theme"); + lv_obj_t *win = nyx_create_standard_window(SYMBOL_COPY" Nyx Color Theme"); + lv_win_add_btn(win, NULL, SYMBOL_HINT" Toggle Background", _preset_bg_action); lv_win_add_btn(win, NULL, SYMBOL_SAVE" Save & Reload", _save_theme_color_action); + color_test.window = win; - // Set current color. - color_test.hue = n_cfg.themecolor; + // Set current theme colors. + color_test.bg = n_cfg.theme_bg; + color_test.hue = n_cfg.theme_color; lv_obj_t *sep = lv_label_create(win, NULL); lv_label_set_static_text(sep, ""); @@ -483,6 +567,7 @@ static lv_res_t _create_window_nyx_colors(lv_obj_t *btn) // Create container to keep content inside. lv_obj_t *h1 = lv_cont_create(win, NULL); lv_obj_set_size(h1, LV_HOR_RES - (LV_DPI * 8 / 10), LV_VER_RES / 7); + color_test.header1 = h1; // Create color preset buttons. lv_obj_t *color_btn = lv_btn_create(h1, NULL); @@ -525,6 +610,7 @@ static lv_res_t _create_window_nyx_colors(lv_obj_t *btn) lv_obj_t *h2 = lv_cont_create(win, NULL); lv_obj_set_size(h2, LV_HOR_RES - (LV_DPI * 8 / 10), LV_VER_RES / 3); lv_obj_align(h2, slider, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI); + color_test.header2 = h2; lv_obj_t *lbl_sample = lv_label_create(h2, NULL); lv_label_set_static_text(lbl_sample, "Sample:"); @@ -563,7 +649,7 @@ static lv_res_t _create_window_nyx_colors(lv_obj_t *btn) lv_obj_set_click(btn_test, false); color_test.button = btn_test; - _test_nyx_color(color_test.hue); + _show_new_nyx_color(color_test.bg, color_test.hue, false); return LV_RES_OK; } @@ -589,11 +675,11 @@ static lv_res_t _action_clock_edit(lv_obj_t *btns, const char * txt) max77620_rtc_get_time(&time); u32 epoch = max77620_rtc_date_to_epoch(&time); - u32 year = lv_roller_get_selected(clock_ctxt.year); + u32 year = lv_roller_get_selected(clock_ctxt.year); u32 month = lv_roller_get_selected(clock_ctxt.month) + 1; - u32 day = lv_roller_get_selected(clock_ctxt.day) + 1; - u32 hour = lv_roller_get_selected(clock_ctxt.hour); - u32 min = lv_roller_get_selected(clock_ctxt.min); + u32 day = lv_roller_get_selected(clock_ctxt.day) + 1; + u32 hour = lv_roller_get_selected(clock_ctxt.hour); + u32 min = lv_roller_get_selected(clock_ctxt.min); switch (month) { @@ -605,25 +691,29 @@ static lv_res_t _action_clock_edit(lv_obj_t *btns, const char * txt) break; case 4: case 6: - case 8: - case 10: - case 12: + case 9: + case 11: if (day > 30) day = 30; break; } - time.year = year + 2020; + time.year = year + CLOCK_MIN_YEAR; time.month = month; - time.day = day; - time.hour = hour; - time.min = min; + time.day = day; + time.hour = hour; + time.min = min; u32 new_epoch = max77620_rtc_date_to_epoch(&time); + // Stored in u32 and allow overflow for integer offset casting. n_cfg.timeoff = new_epoch - epoch; + + // If canceled set 1 for invalidating first boot clock edit. if (!n_cfg.timeoff) n_cfg.timeoff = 1; + else + max77620_rtc_set_epoch_offset((int)n_cfg.timeoff); nyx_changes_made = true; } @@ -650,47 +740,36 @@ static lv_res_t _create_mbox_clock_edit(lv_obj_t *btn) lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char * mbox_btn_map[] = { "\211", "\222Done", "\222Cancel", "\211", "" }; + static const char *mbox_btn_map[] = { "\251", "\222Done", "\222Cancel", "\251", "" }; lv_obj_t *mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); lv_obj_set_width(mbox, LV_HOR_RES / 9 * 6); lv_mbox_set_text(mbox, "Enter #C7EA46 Date# and #C7EA46 Time# for Nyx\nThis will not alter the actual HW clock!"); + // Get current time. rtc_time_t time; - max77620_rtc_get_time(&time); - if (n_cfg.timeoff) - { - u32 epoch = max77620_rtc_date_to_epoch(&time) + (s32)n_cfg.timeoff; - max77620_rtc_epoch_to_date(epoch, &time); - } - if (time.year < 2020) - time.year = 2020; - else if (time.year > 2030) - time.year = 2030; + max77620_rtc_get_time_adjusted(&time); - time.year -= 2020; + // Normalize year if out of range. + if (time.year < CLOCK_MIN_YEAR) + time.year = CLOCK_MIN_YEAR; + else if (time.year > CLOCK_MAX_YEAR) + time.year = CLOCK_MAX_YEAR; + + time.year -= CLOCK_MIN_YEAR; lv_obj_t *h1 = lv_cont_create(mbox, NULL); lv_cont_set_fit(h1, true, true); + // Create year roller. lv_obj_t *roller_year = lv_roller_create(h1, NULL); - lv_roller_set_options(roller_year, - "2020\n" - "2021\n" - "2022\n" - "2023\n" - "2024\n" - "2025\n" - "2026\n" - "2027\n" - "2028\n" - "2029\n" - "2030"); + lv_roller_set_options(roller_year, CLOCK_YEARLIST); lv_roller_set_selected(roller_year, time.year, false); lv_roller_set_visible_row_count(roller_year, 3); clock_ctxt.year = roller_year; + // Create month roller. lv_obj_t *roller_month = lv_roller_create(h1, roller_year); lv_roller_set_options(roller_month, "January\n" @@ -709,6 +788,7 @@ static lv_res_t _create_mbox_clock_edit(lv_obj_t *btn) lv_obj_align(roller_month, roller_year, LV_ALIGN_OUT_RIGHT_MID, 0, 0); clock_ctxt.month = roller_month; + // Create day roller. static char days[256]; days[0] = 0; for (u32 i = 1; i < 32; i++) @@ -720,6 +800,7 @@ static lv_res_t _create_mbox_clock_edit(lv_obj_t *btn) lv_obj_align(roller_day, roller_month, LV_ALIGN_OUT_RIGHT_MID, 0, 0); clock_ctxt.day = roller_day; + // Create hours roller. static char hours[256]; hours[0] = 0; for (u32 i = 0; i < 24; i++) @@ -731,6 +812,7 @@ static lv_res_t _create_mbox_clock_edit(lv_obj_t *btn) lv_obj_align(roller_hour, roller_day, LV_ALIGN_OUT_RIGHT_MID, LV_DPI / 2, 0); clock_ctxt.hour = roller_hour; + // Create minutes roller. static char minutes[512]; minutes[0] = 0; for (u32 i = 0; i < 60; i++) @@ -759,20 +841,37 @@ void first_time_clock_edit(void *param) static lv_res_t _joycon_info_dump_action(lv_obj_t * btn) { FIL fp; - int error; + int error = 0; + int cal_error = 0; bool is_l_hos = false; bool is_r_hos = false; + bool nx_hoag = fuse_read_hw_type() == FUSE_NX_HW_TYPE_HOAG; jc_gamepad_rpt_t *jc_pad = jc_get_bt_pairing_info(&is_l_hos, &is_r_hos); - char *data = (char *)malloc(0x4000); - char *txt_buf = (char *)malloc(0x1000); + char *data = (char *)malloc(SZ_16K); + char *txt_buf = (char *)malloc(SZ_4K); - if (!jc_pad) - { + if (!nx_hoag && !jc_pad) error = 255; - goto disabled; + + // Try 2 times to get factory calibration data. + for (u32 i = 0; i < 2; i++) + { + if (!error) + cal_error = hos_dump_cal0(); + if (!cal_error) + break; } + if (cal_error && nx_hoag) + error = cal_error; + + if (error) + goto disabled_or_cal0_issue; + + if (nx_hoag) + goto save_data; + // Count valid joycon. u32 joycon_found = jc_pad->bt_conn_l.type ? 1 : 0; if (jc_pad->bt_conn_r.type) @@ -782,101 +881,223 @@ static lv_res_t _joycon_info_dump_action(lv_obj_t * btn) jc_pad->bt_conn_l.type = is_l_hos ? jc_pad->bt_conn_l.type : 0; jc_pad->bt_conn_r.type = is_r_hos ? jc_pad->bt_conn_r.type : 0; - error = !sd_mount(); +save_data: + error = !sd_mount() ? 5 : 0; if (!error) { - // Save binary dump. - memcpy(data, &jc_pad->bt_conn_l, sizeof(jc_bt_conn_t)); - memcpy(data + sizeof(jc_bt_conn_t), &jc_pad->bt_conn_r, sizeof(jc_bt_conn_t)); + nx_emmc_cal0_t *cal0 = (nx_emmc_cal0_t *)cal0_buf; f_mkdir("switchroot"); - error = sd_save_to_file((u8 *)data, sizeof(jc_bt_conn_t) * 2, "switchroot/joycon_mac.bin"); - // Save readable dump. - jc_bt_conn_t *bt = &jc_pad->bt_conn_l; - s_printf(data, - "[joycon_00]\ntype=%d\nmac=%02X:%02X:%02X:%02X:%02X:%02X\n" - "host=%02X:%02X:%02X:%02X:%02X:%02X\n" - "ltk=%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X\n\n", - bt->type, bt->mac[0], bt->mac[1], bt->mac[2], bt->mac[3], bt->mac[4], bt->mac[5], - bt->host_mac[0], bt->host_mac[1], bt->host_mac[2], bt->host_mac[3], bt->host_mac[4], bt->host_mac[5], - bt->ltk[0], bt->ltk[1], bt->ltk[2], bt->ltk[3], bt->ltk[4], bt->ltk[5], bt->ltk[6], bt->ltk[7], - bt->ltk[8], bt->ltk[9], bt->ltk[10], bt->ltk[11], bt->ltk[12], bt->ltk[13], bt->ltk[14], bt->ltk[15]); - bt = &jc_pad->bt_conn_r; - s_printf(data + strlen(data), - "[joycon_01]\ntype=%d\nmac=%02X:%02X:%02X:%02X:%02X:%02X\n" - "host=%02X:%02X:%02X:%02X:%02X:%02X\n" - "ltk=%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X\n", - bt->type, bt->mac[0], bt->mac[1], bt->mac[2], bt->mac[3], bt->mac[4], bt->mac[5], - bt->host_mac[0], bt->host_mac[1], bt->host_mac[2], bt->host_mac[3], bt->host_mac[4], bt->host_mac[5], - bt->ltk[0], bt->ltk[1], bt->ltk[2], bt->ltk[3], bt->ltk[4], bt->ltk[5], bt->ltk[6], bt->ltk[7], - bt->ltk[8], bt->ltk[9], bt->ltk[10], bt->ltk[11], bt->ltk[12], bt->ltk[13], bt->ltk[14], bt->ltk[15]); - - if (!error) - error = f_open(&fp, "switchroot/joycon_mac.ini", FA_WRITE | FA_CREATE_ALWAYS); - if (!error) + if (!nx_hoag) { - f_puts(data, &fp); - f_close(&fp); + // Save binary dump. + memcpy(data, &jc_pad->bt_conn_l, sizeof(jc_bt_conn_t)); + memcpy(data + sizeof(jc_bt_conn_t), &jc_pad->bt_conn_r, sizeof(jc_bt_conn_t)); + + error = sd_save_to_file((u8 *)data, sizeof(jc_bt_conn_t) * 2, "switchroot/joycon_mac.bin") ? 4 : 0; + + // Save readable dump. + jc_bt_conn_t *bt = &jc_pad->bt_conn_l; + s_printf(data, + "[joycon_00]\ntype=%d\nmac=%02X:%02X:%02X:%02X:%02X:%02X\n" + "host=%02X:%02X:%02X:%02X:%02X:%02X\n" + "ltk=%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X\n\n", + bt->type, bt->mac[0], bt->mac[1], bt->mac[2], bt->mac[3], bt->mac[4], bt->mac[5], + bt->host_mac[0], bt->host_mac[1], bt->host_mac[2], bt->host_mac[3], bt->host_mac[4], bt->host_mac[5], + bt->ltk[0], bt->ltk[1], bt->ltk[2], bt->ltk[3], bt->ltk[4], bt->ltk[5], bt->ltk[6], bt->ltk[7], + bt->ltk[8], bt->ltk[9], bt->ltk[10], bt->ltk[11], bt->ltk[12], bt->ltk[13], bt->ltk[14], bt->ltk[15]); + bt = &jc_pad->bt_conn_r; + s_printf(data + strlen(data), + "[joycon_01]\ntype=%d\nmac=%02X:%02X:%02X:%02X:%02X:%02X\n" + "host=%02X:%02X:%02X:%02X:%02X:%02X\n" + "ltk=%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X%02X\n", + bt->type, bt->mac[0], bt->mac[1], bt->mac[2], bt->mac[3], bt->mac[4], bt->mac[5], + bt->host_mac[0], bt->host_mac[1], bt->host_mac[2], bt->host_mac[3], bt->host_mac[4], bt->host_mac[5], + bt->ltk[0], bt->ltk[1], bt->ltk[2], bt->ltk[3], bt->ltk[4], bt->ltk[5], bt->ltk[6], bt->ltk[7], + bt->ltk[8], bt->ltk[9], bt->ltk[10], bt->ltk[11], bt->ltk[12], bt->ltk[13], bt->ltk[14], bt->ltk[15]); + + if (!error) + error = f_open(&fp, "switchroot/joycon_mac.ini", FA_WRITE | FA_CREATE_ALWAYS) ? 4 : 0; + if (!error) + { + f_puts(data, &fp); + f_close(&fp); + } + + f_mkdir("switchroot"); + + // Save IMU Calibration data. + if (!error && !cal_error) + { + s_printf(data, + "imu_type=%d\n\n" + "acc_cal_off_x=0x%X\n" + "acc_cal_off_y=0x%X\n" + "acc_cal_off_z=0x%X\n" + "acc_cal_scl_x=0x%X\n" + "acc_cal_scl_y=0x%X\n" + "acc_cal_scl_z=0x%X\n\n" + + "gyr_cal_off_x=0x%X\n" + "gyr_cal_off_y=0x%X\n" + "gyr_cal_off_z=0x%X\n" + "gyr_cal_scl_x=0x%X\n" + "gyr_cal_scl_y=0x%X\n" + "gyr_cal_scl_z=0x%X\n\n" + + "device_bt_mac=%02X:%02X:%02X:%02X:%02X:%02X\n", + cal0->console_6axis_sensor_type, + cal0->acc_offset[0], cal0->acc_offset[1], cal0->acc_offset[2], + cal0->acc_scale[0], cal0->acc_scale[1], cal0->acc_scale[2], + cal0->gyro_offset[0], cal0->gyro_offset[1], cal0->gyro_offset[2], + cal0->gyro_scale[0], cal0->gyro_scale[1], cal0->gyro_scale[2], + cal0->bd_mac[0], cal0->bd_mac[1], cal0->bd_mac[2], cal0->bd_mac[3], cal0->bd_mac[4], cal0->bd_mac[5]); + + error = f_open(&fp, "switchroot/switch.cal", FA_WRITE | FA_CREATE_ALWAYS) ? 4 : 0; + if (!error) + { + f_puts(data, &fp); + f_close(&fp); + } + } + } + else + { + jc_calib_t *stick_cal_l = (jc_calib_t *)cal0->analog_stick_cal_l; + jc_calib_t *stick_cal_r = (jc_calib_t *)cal0->analog_stick_cal_r; + + // Save Lite Gamepad and IMU Calibration data. + // Actual max/min are right/left and up/down offsets. + s_printf(data, + "lite_cal_l_type=0x%X\n" + "lite_cal_lx_lof=0x%X\n" + "lite_cal_lx_cnt=0x%X\n" + "lite_cal_lx_rof=0x%X\n" + "lite_cal_ly_dof=0x%X\n" + "lite_cal_ly_cnt=0x%X\n" + "lite_cal_ly_uof=0x%X\n\n" + + "lite_cal_r_type=0x%X\n" + "lite_cal_rx_lof=0x%X\n" + "lite_cal_rx_cnt=0x%X\n" + "lite_cal_rx_rof=0x%X\n" + "lite_cal_ry_dof=0x%X\n" + "lite_cal_ry_cnt=0x%X\n" + "lite_cal_ry_uof=0x%X\n\n" + + "imu_type=%d\n\n" + "acc_cal_off_x=0x%X\n" + "acc_cal_off_y=0x%X\n" + "acc_cal_off_z=0x%X\n" + "acc_cal_scl_x=0x%X\n" + "acc_cal_scl_y=0x%X\n" + "acc_cal_scl_z=0x%X\n\n" + + "gyr_cal_off_x=0x%X\n" + "gyr_cal_off_y=0x%X\n" + "gyr_cal_off_z=0x%X\n" + "gyr_cal_scl_x=0x%X\n" + "gyr_cal_scl_y=0x%X\n" + "gyr_cal_scl_z=0x%X\n\n" + + "device_bt_mac=%02X:%02X:%02X:%02X:%02X:%02X\n", + cal0->analog_stick_type_l, + stick_cal_l->x_min, stick_cal_l->x_center, stick_cal_l->x_max, + stick_cal_l->y_min, stick_cal_l->y_center, stick_cal_l->y_max, + cal0->analog_stick_type_r, + stick_cal_r->x_min, stick_cal_r->x_center, stick_cal_r->x_max, + stick_cal_r->y_min, stick_cal_r->y_center, stick_cal_r->y_max, + cal0->console_6axis_sensor_type, + cal0->acc_offset[0], cal0->acc_offset[1], cal0->acc_offset[2], + cal0->acc_scale[0], cal0->acc_scale[1], cal0->acc_scale[2], + cal0->gyro_offset[0], cal0->gyro_offset[1], cal0->gyro_offset[2], + cal0->gyro_scale[0], cal0->gyro_scale[1], cal0->gyro_scale[2], + cal0->bd_mac[0], cal0->bd_mac[1], cal0->bd_mac[2], cal0->bd_mac[3], cal0->bd_mac[4], cal0->bd_mac[5]); + if (!error) + error = f_open(&fp, "switchroot/switch.cal", FA_WRITE | FA_CREATE_ALWAYS) ? 4 : 0; + if (!error) + { + f_puts(data, &fp); + f_close(&fp); + } } sd_unmount(); } -disabled:; +disabled_or_cal0_issue:; lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL); lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char * mbox_btn_map[] = { "\211", "\222OK", "\211", "" }; + static const char *mbox_btn_map[] = { "\251", "\222OK", "\251", "" }; lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); lv_obj_set_width(mbox, LV_HOR_RES / 9 * 5); if (!error) { - s_printf(txt_buf, - "Dumping to SD card finished!\n" - "Saved to: #C7EA46 switchroot/joycon_mac.[bin/ini]#\n\n"); - - bool success = true; - - // Check if pairing info was found. - if (joycon_found == 2) - strcat(txt_buf, "#C7EA46 Success!#\n#C7EA46 Found 2 out of 2 Joy-Con pairing data!#\n"); - else + if (!nx_hoag) { - s_printf(txt_buf + strlen(txt_buf), "#FF8000 Failed!#\n#FF8000 Warning:# Found #FFDD00 %d out of 2# pairing data!\n", joycon_found); - success = false; - } + s_printf(txt_buf, + "Dumping to SD card finished!\n" + "Saved to: #C7EA46 switchroot/joycon_mac.[bin/ini]#\n\n"); - // Check if pairing was done in HOS. - if (is_l_hos && is_r_hos) - strcat(txt_buf, "#C7EA46 Both pairing data are HOS based!#"); - else if (!is_l_hos && is_r_hos) - { - strcat(txt_buf, "#FF8000 Warning:# #FFDD00 Left# pairing data is not HOS based!"); - success = false; - } - else if (is_l_hos && !is_r_hos) - { - strcat(txt_buf, "#FF8000 Warning:# #FFDD00 Right# pairing data is not HOS based!"); - success = false; + bool success = true; + + // Check if pairing info was found. + if (joycon_found == 2) + strcat(txt_buf, "#C7EA46 Success!#\n#C7EA46 Found 2 out of 2 Joy-Con pairing data!#\n"); + else + { + s_printf(txt_buf + strlen(txt_buf), "#FF8000 Failed!#\n#FF8000 Warning:# Found #FFDD00 %d out of 2# pairing data!\n", joycon_found); + success = false; + } + + // Check if pairing was done in HOS. + if (is_l_hos && is_r_hos) + strcat(txt_buf, "#C7EA46 Both pairing data are HOS based!#"); + else if (!is_l_hos && is_r_hos) + { + strcat(txt_buf, "#FF8000 Warning:# #FFDD00 Left# pairing data is not HOS based!"); + success = false; + } + else if (is_l_hos && !is_r_hos) + { + strcat(txt_buf, "#FF8000 Warning:# #FFDD00 Right# pairing data is not HOS based!"); + success = false; + } + else + { + strcat(txt_buf, "#FF8000 Warning:# #FFDD00 No# pairing data is HOS based!"); + success = false; + } + + if (!success) + strcat(txt_buf, + "\n\n#FFDD00 Make sure that both Joy-Con are connected,#\n" + "#FFDD00 and that you paired them in HOS!#"); + + if (cal_error) + s_printf(txt_buf + strlen(txt_buf), "\n\n#FF8000 Warning: Failed (%d) to get IMU calibration!#", cal_error); } else { - strcat(txt_buf, "#FF8000 Warning:# #FFDD00 No# pairing data is HOS based!"); - success = false; + s_printf(txt_buf, + "Dumping to SD card finished!\n" + "Saved to: #C7EA46 switchroot/switch.cal#\n\n"); + strcat(txt_buf, "#C7EA46 Success!#\n#C7EA46 Found Lite Gamepad data!#\n"); } - - if (!success) - strcat(txt_buf, - "\n\n#FFDD00 Make sure that both Joy-Con are connected,#\n" - "#FFDD00 and that you paired them in HOS!#"); } else - s_printf(txt_buf, "#FFDD00 Failed to dump Joy-Con pairing info!#\n#FFDD00 Error: %d#", error); + { + if (!nx_hoag) + s_printf(txt_buf, "#FFDD00 Failed to dump Joy-Con pairing info!#\n#FFDD00 Error: %d#", error); + else + s_printf(txt_buf, "#FFDD00 Failed to get Lite Gamepad info!#\n#FFDD00 Error: %d#", error); + } lv_mbox_set_text(mbox, txt_buf); @@ -943,20 +1164,22 @@ static void _check_nyx_changes() static lv_res_t _action_win_nyx_options_close(lv_obj_t *btn) { - lv_win_close_action(btn); + // Hide status bar options save button. + lv_obj_set_opa_scale(status_bar.mid, LV_OPA_0); + lv_obj_set_click(status_bar.mid, false); - close_btn = NULL; + lv_res_t res = nyx_win_close_action_custom(btn); _check_nyx_changes(); - return LV_RES_INV; + return res; } lv_res_t create_win_nyx_options(lv_obj_t *parrent_btn) { lv_theme_t *th = lv_theme_get_current(); - lv_obj_t *win = nyx_create_window_custom_close_btn(SYMBOL_HOME" Nyx Options", _action_win_nyx_options_close); + lv_obj_t *win = nyx_create_window_custom_close_btn(SYMBOL_HOME" Nyx Settings", _action_win_nyx_options_close); static lv_style_t h_style; lv_style_copy(&h_style, &lv_style_transp); @@ -990,6 +1213,7 @@ lv_res_t create_win_nyx_options(lv_obj_t *parrent_btn) lv_obj_t *label_sep = lv_label_create(sw_h2, NULL); lv_label_set_static_text(label_sep, ""); + // Create theme button. lv_obj_t *btn = lv_btn_create(sw_h2, NULL); lv_obj_t *label_btn = lv_label_create(btn, NULL); lv_btn_set_fit(btn, true, true); @@ -1003,6 +1227,7 @@ lv_res_t create_win_nyx_options(lv_obj_t *parrent_btn) lv_obj_set_style(label_txt2, &hint_small_style); lv_obj_align(label_txt2, btn, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 3 - 8); + // Create home screen settings list. lv_obj_t *line_sep = lv_line_create(sw_h2, NULL); static const lv_point_t line_pp[] = { {0, 0}, { LV_HOR_RES - (LV_DPI - (LV_DPI / 4)) * 2, 0} }; lv_line_set_points(line_sep, line_pp, 2); @@ -1038,22 +1263,24 @@ lv_res_t create_win_nyx_options(lv_obj_t *parrent_btn) line_sep = lv_line_create(sw_h2, line_sep); lv_obj_align(line_sep, label_txt2, LV_ALIGN_OUT_BOTTOM_LEFT, -(LV_DPI / 4), LV_DPI / 4); + // Create entries per line button. lv_obj_t *btn2 = lv_btn_create(sw_h2, NULL); - lv_obj_t *label_btn2 = lv_label_create(btn2, NULL); - lv_btn_set_fit(btn2, true, true); - lv_label_set_static_text(label_btn2, SYMBOL_CLOCK" Clock (Offset)"); - lv_obj_align(btn2, line_sep, LV_ALIGN_OUT_BOTTOM_LEFT, LV_DPI / 4, LV_DPI / 4); - lv_btn_set_action(btn2, LV_BTN_ACTION_CLICK, _create_mbox_clock_edit); + nyx_create_onoff_button(th, sw_h2, btn2, SYMBOL_GPS" Extended Boot Entries", _entries_columns_action, true); + lv_obj_align(btn2, line_sep, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 10); + if (n_cfg.entries_5_col) + lv_btn_set_state(btn2, LV_BTN_STATE_TGL_REL); + nyx_generic_onoff_toggle(btn2); label_txt2 = lv_label_create(sw_h2, NULL); lv_label_set_recolor(label_txt2, true); lv_label_set_static_text(label_txt2, - "Change clock offset manually.\n" - "#C7EA46 The entered Date and Time will be converted to an offset#\n" - "#C7EA46 automatically. This will be also used for FatFS operations.#"); + "Sets the boot entries per line to 5. (Default is 4)\n" + "#C7EA46 This allows a total of 10 boot entries to be shown in Launch#\n" + "#C7EA46 and More Configs sections.#\n\n\n"); lv_obj_set_style(label_txt2, &hint_small_style); - lv_obj_align(label_txt2, btn2, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 4); + lv_obj_align(label_txt2, btn2, LV_ALIGN_OUT_BOTTOM_LEFT, LV_DPI / 4, LV_DPI / 12); + // Create the second column. label_sep = lv_label_create(sw_h3, NULL); lv_label_set_static_text(label_sep, ""); @@ -1103,12 +1330,27 @@ lv_res_t create_win_nyx_options(lv_obj_t *parrent_btn) line_sep = lv_line_create(sw_h3, line_sep); lv_obj_align(line_sep, label_txt2, LV_ALIGN_OUT_BOTTOM_LEFT, -(LV_DPI / 4), LV_DPI / 4); + // Create clock edit button. lv_obj_t *btn5 = lv_btn_create(sw_h3, NULL); lv_obj_t *label_btn5 = lv_label_create(btn5, NULL); lv_btn_set_fit(btn5, true, true); - lv_label_set_static_text(label_btn5, SYMBOL_EDIT" Save Options"); - lv_obj_align(btn5, line_sep, LV_ALIGN_OUT_BOTTOM_LEFT, LV_DPI * 31 / 21, LV_DPI * 6 / 8); - lv_btn_set_action(btn5, LV_BTN_ACTION_CLICK, _save_nyx_options_action); + lv_label_set_static_text(label_btn5, SYMBOL_CLOCK" Clock (Offset)"); + lv_obj_align(btn5, line_sep, LV_ALIGN_OUT_BOTTOM_LEFT, LV_DPI / 4, LV_DPI / 4); + lv_btn_set_action(btn5, LV_BTN_ACTION_CLICK, _create_mbox_clock_edit); + + label_txt2 = lv_label_create(sw_h3, NULL); + lv_label_set_recolor(label_txt2, true); + lv_label_set_static_text(label_txt2, + "Change clock offset manually.\n" + "#C7EA46 The entered Date and Time will be converted to an offset#\n" + "#C7EA46 automatically. This will be also used for FatFS operations.#"); + lv_obj_set_style(label_txt2, &hint_small_style); + lv_obj_align(label_txt2, btn5, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 4); + + // Enable save options button in status bar and set action. + lv_btn_set_action(status_bar.mid, LV_BTN_ACTION_CLICK, _save_nyx_options_action); + lv_obj_set_opa_scale(status_bar.mid, LV_OPA_COVER); + lv_obj_set_click(status_bar.mid, true); lv_obj_set_top(l_cont, true); // Set the ddlist container at top. lv_obj_set_parent(ddlist, l_cont); // Reorder ddlist. @@ -1227,7 +1469,7 @@ void create_tab_options(lv_theme_t *th, lv_obj_t *parent) // Create Auto NoGC button. lv_obj_t *btn2 = lv_btn_create(sw_h2, NULL); - nyx_create_onoff_button(th, sw_h2, btn2, SYMBOL_SHRK" Auto NoGC", auto_nogc_toggle, true); + nyx_create_onoff_button(th, sw_h2, btn2, SYMBOL_CHIP" Auto NoGC", auto_nogc_toggle, true); lv_obj_align(btn2, line_sep, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 10); label_txt2 = lv_label_create(sw_h2, NULL); diff --git a/nyx/nyx_gui/frontend/gui_tools.c b/nyx/nyx_gui/frontend/gui_tools.c index 7a50fa4..3229814 100644 --- a/nyx/nyx_gui/frontend/gui_tools.c +++ b/nyx/nyx_gui/frontend/gui_tools.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,36 +17,25 @@ #include +#include + #include "gui.h" #include "gui_tools.h" #include "gui_tools_partition_manager.h" #include "gui_emmc_tools.h" #include "fe_emummc_tools.h" -#include #include "../config.h" -#include #include "../hos/pkg1.h" #include "../hos/pkg2.h" #include "../hos/hos.h" -#include #include -#include -#include -#include -#include -#include -#include "../storage/nx_emmc.h" -#include -#include -#include -#include -#include -#include extern volatile boot_cfg_t *b_cfg; extern hekate_config h_cfg; extern nyx_config n_cfg; +lv_obj_t *ums_mbox; + extern char *emmcsn_path_impl(char *path, char *sub_dir, char *filename, sdmmc_storage_t *storage); static lv_obj_t *_create_container(lv_obj_t *parent) @@ -67,19 +56,20 @@ static lv_obj_t *_create_container(lv_obj_t *parent) return h1; } -bool get_autorcm_status(bool change) +bool get_set_autorcm_status(bool toggle) { + u32 sector; u8 corr_mod0, mod1; bool enabled = false; if (h_cfg.t210b01) return false; - sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400); + emmc_initialize(false); u8 *tempbuf = (u8 *)malloc(0x200); - sdmmc_storage_set_mmc_partition(&emmc_storage, EMMC_BOOT0); - sdmmc_storage_read(&emmc_storage, 0x200 / NX_EMMC_BLOCKSIZE, 1, tempbuf); + emmc_set_partition(EMMC_BOOT0); + sdmmc_storage_read(&emmc_storage, 0x200 / EMMC_BLOCKSIZE, 1, tempbuf); // Get the correct RSA modulus byte masks. nx_emmc_get_autorcm_masks(&corr_mod0, &mod1); @@ -91,29 +81,54 @@ bool get_autorcm_status(bool change) if (tempbuf[0x10] != corr_mod0) enabled = true; - // Change autorcm status if requested. - if (change) + // Toggle autorcm status if requested. + if (toggle) { - int i, sect = 0; - // Iterate BCTs. - for (i = 0; i < 4; i++) + for (u32 i = 0; i < 4; i++) { - sect = (0x200 + (0x4000 * i)) / NX_EMMC_BLOCKSIZE; - sdmmc_storage_read(&emmc_storage, sect, 1, tempbuf); + sector = (0x200 + (0x4000 * i)) / EMMC_BLOCKSIZE; // 0x4000 bct + 0x200 offset. + sdmmc_storage_read(&emmc_storage, sector, 1, tempbuf); if (!enabled) tempbuf[0x10] = 0; else tempbuf[0x10] = corr_mod0; - sdmmc_storage_write(&emmc_storage, sect, 1, tempbuf); + sdmmc_storage_write(&emmc_storage, sector, 1, tempbuf); } - enabled = !(enabled); + enabled = !enabled; + } + + // Check if RCM is patched and protect from a possible brick. + if (enabled && h_cfg.rcm_patched && hw_get_chip_id() != GP_HIDREV_MAJOR_T210B01) + { + // Iterate BCTs. + for (u32 i = 0; i < 4; i++) + { + sector = (0x200 + (0x4000 * i)) / EMMC_BLOCKSIZE; // 0x4000 bct + 0x200 offset. + sdmmc_storage_read(&emmc_storage, sector, 1, tempbuf); + + // Check if 2nd byte of modulus is correct. + if (tempbuf[0x11] != mod1) + continue; + + // If AutoRCM is enabled, disable it. + if (tempbuf[0x10] != corr_mod0) + { + tempbuf[0x10] = corr_mod0; + + sdmmc_storage_write(&emmc_storage, sector, 1, tempbuf); + } + } + + enabled = false; } out: free(tempbuf); - sdmmc_storage_end(&emmc_storage); + emmc_end(); + + h_cfg.autorcm_enabled = enabled; return enabled; } @@ -124,11 +139,11 @@ static lv_res_t _create_mbox_autorcm_status(lv_obj_t *btn) lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char * mbox_btn_map[] = { "\211", "\222OK", "\211", "" }; + static const char * mbox_btn_map[] = { "\251", "\222OK", "\251", "" }; lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); - bool enabled = get_autorcm_status(true); + bool enabled = get_set_autorcm_status(true); if (enabled) { @@ -164,12 +179,12 @@ static lv_res_t _create_mbox_hid(usb_ctxt_t *usbs) lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char *mbox_btn_map[] = { "\211", "\262Close", "\211", "" }; - static const char *mbox_btn_map2[] = { "\211", "\222Close", "\211", "" }; + static const char *mbox_btn_map[] = { "\251", "\262Close", "\251", "" }; + static const char *mbox_btn_map2[] = { "\251", "\222Close", "\251", "" }; lv_obj_t *mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); - char *txt_buf = malloc(0x1000); + char *txt_buf = malloc(SZ_4K); s_printf(txt_buf, "#FF8000 HID Emulation#\n\n#C7EA46 Device:# "); @@ -209,12 +224,12 @@ static lv_res_t _create_mbox_ums(usb_ctxt_t *usbs) lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char *mbox_btn_map[] = { "\211", "\262Close", "\211", "" }; - static const char *mbox_btn_map2[] = { "\211", "\222Close", "\211", "" }; + static const char *mbox_btn_map[] = { "\251", "\262Close", "\251", "" }; + static const char *mbox_btn_map2[] = { "\251", "\222Close", "\251", "" }; lv_obj_t *mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); - char *txt_buf = malloc(0x1000); + char *txt_buf = malloc(SZ_4K); s_printf(txt_buf, "#FF8000 USB Mass Storage#\n\n#C7EA46 Device:# "); @@ -311,7 +326,7 @@ static lv_res_t _create_mbox_ums_error(int error) lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char *mbox_btn_map[] = { "\211", "\222OK", "\211", "" }; + static const char *mbox_btn_map[] = { "\251", "\222OK", "\251", "" }; lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); @@ -347,7 +362,7 @@ static lv_res_t _action_hid_jc(lv_obj_t *btn) // Reduce BPMP, RAM and backlight and power off SDMMC1 to conserve power. sd_end(); minerva_change_freq(FREQ_800); - bpmp_freq_t prev_fid = bpmp_clk_rate_set(BPMP_CLK_NORMAL); + bpmp_clk_rate_relaxed(true); display_backlight_brightness(10, 1000); usb_ctxt_t usbs; @@ -359,7 +374,7 @@ static lv_res_t _action_hid_jc(lv_obj_t *btn) // Restore BPMP, RAM and backlight. minerva_change_freq(FREQ_1600); - bpmp_clk_rate_set(prev_fid); + bpmp_clk_rate_relaxed(false); display_backlight_brightness(h_cfg.backlight - 20, 1000); return LV_RES_OK; @@ -371,7 +386,7 @@ static lv_res_t _action_hid_touch(lv_obj_t *btn) // Reduce BPMP, RAM and backlight and power off SDMMC1 to conserve power. sd_end(); minerva_change_freq(FREQ_800); - bpmp_freq_t prev_fid = bpmp_clk_rate_set(BPMP_CLK_NORMAL); + bpmp_clk_rate_relaxed(true); display_backlight_brightness(10, 1000); usb_ctxt_t usbs; @@ -383,7 +398,7 @@ static lv_res_t _action_hid_touch(lv_obj_t *btn) // Restore BPMP, RAM and backlight. minerva_change_freq(FREQ_1600); - bpmp_clk_rate_set(prev_fid); + bpmp_clk_rate_relaxed(false); display_backlight_brightness(h_cfg.backlight - 20, 1000); return LV_RES_OK; @@ -416,7 +431,7 @@ static lv_res_t _action_ums_emmc_boot0(lv_obj_t *btn) usbs.type = MMC_EMMC; usbs.partition = EMMC_BOOT0 + 1; usbs.offset = 0; - usbs.sectors = 0x2000; + usbs.sectors = 0; usbs.ro = usb_msc_emmc_read_only; usbs.system_maintenance = &manual_system_maintenance; usbs.set_text = &usb_gadget_set_text; @@ -435,7 +450,7 @@ static lv_res_t _action_ums_emmc_boot1(lv_obj_t *btn) usbs.type = MMC_EMMC; usbs.partition = EMMC_BOOT1 + 1; usbs.offset = 0; - usbs.sectors = 0x2000; + usbs.sectors = 0; usbs.ro = usb_msc_emmc_read_only; usbs.system_maintenance = &manual_system_maintenance; usbs.set_text = &usb_gadget_set_text; @@ -487,6 +502,11 @@ static lv_res_t _action_ums_emuemmc_boot0(lv_obj_t *btn) usbs.offset = emu_info.sector; } } + + if (emu_info.path) + free(emu_info.path); + if (emu_info.nintendo_path) + free(emu_info.nintendo_path); } sd_unmount(); @@ -496,7 +516,7 @@ static lv_res_t _action_ums_emuemmc_boot0(lv_obj_t *btn) { usbs.type = MMC_SD; usbs.partition = EMMC_BOOT0 + 1; - usbs.sectors = 0x2000; + usbs.sectors = 0x2000; // Forced 4MB. usbs.ro = usb_msc_emmc_read_only; usbs.system_maintenance = &manual_system_maintenance; usbs.set_text = &usb_gadget_set_text; @@ -529,6 +549,11 @@ static lv_res_t _action_ums_emuemmc_boot1(lv_obj_t *btn) usbs.offset = emu_info.sector + 0x2000; } } + + if (emu_info.path) + free(emu_info.path); + if (emu_info.nintendo_path) + free(emu_info.nintendo_path); } sd_unmount(); @@ -538,7 +563,7 @@ static lv_res_t _action_ums_emuemmc_boot1(lv_obj_t *btn) { usbs.type = MMC_SD; usbs.partition = EMMC_BOOT1 + 1; - usbs.sectors = 0x2000; + usbs.sectors = 0x2000; // Forced 4MB. usbs.ro = usb_msc_emmc_read_only; usbs.system_maintenance = &manual_system_maintenance; usbs.set_text = &usb_gadget_set_text; @@ -570,7 +595,7 @@ static lv_res_t _action_ums_emuemmc_gpp(lv_obj_t *btn) error = 1; usbs.offset = emu_info.sector + 0x4000; - u8 *gpt = malloc(512); + u8 *gpt = malloc(SD_BLOCKSIZE); if (sdmmc_storage_read(&sd_storage, usbs.offset + 1, 1, gpt)) { if (!memcmp(gpt, "EFI PART", 8)) @@ -581,6 +606,11 @@ static lv_res_t _action_ums_emuemmc_gpp(lv_obj_t *btn) } } } + + if (emu_info.path) + free(emu_info.path); + if (emu_info.nintendo_path) + free(emu_info.nintendo_path); } sd_unmount(); @@ -676,7 +706,7 @@ static lv_res_t _create_window_usb_tools(lv_obj_t *parent) lv_line_set_style(line_sep, lv_theme_get_current()->line.decor); lv_obj_align(line_sep, label_txt, LV_ALIGN_OUT_BOTTOM_LEFT, -(LV_DPI / 4), LV_DPI / 8); - // Create UMS buttons. + // Create SD UMS button. lv_obj_t *btn1 = lv_btn_create(h1, NULL); lv_obj_t *label_btn = lv_label_create(btn1, NULL); lv_btn_set_fit(btn1, true, true); @@ -701,30 +731,35 @@ static lv_res_t _create_window_usb_tools(lv_obj_t *parent) lv_obj_align(btn_gpp, label_txt2, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 2); lv_btn_set_action(btn_gpp, LV_BTN_ACTION_CLICK, _action_ums_emmc_gpp); + // Create BOOT0 button. lv_obj_t *btn_boot0 = lv_btn_create(h1, btn1); label_btn = lv_label_create(btn_boot0, NULL); lv_label_set_static_text(label_btn, "BOOT0"); lv_obj_align(btn_boot0, btn_gpp, LV_ALIGN_OUT_RIGHT_MID, LV_DPI / 10, 0); lv_btn_set_action(btn_boot0, LV_BTN_ACTION_CLICK, _action_ums_emmc_boot0); + // Create BOOT1 button. lv_obj_t *btn_boot1 = lv_btn_create(h1, btn1); label_btn = lv_label_create(btn_boot1, NULL); lv_label_set_static_text(label_btn, "BOOT1"); lv_obj_align(btn_boot1, btn_boot0, LV_ALIGN_OUT_RIGHT_MID, LV_DPI / 10, 0); lv_btn_set_action(btn_boot1, LV_BTN_ACTION_CLICK, _action_ums_emmc_boot1); + // Create emuMMC RAW GPP button. lv_obj_t *btn_emu_gpp = lv_btn_create(h1, btn1); label_btn = lv_label_create(btn_emu_gpp, NULL); lv_label_set_static_text(label_btn, SYMBOL_MODULES_ALT" emu RAW GPP"); lv_obj_align(btn_emu_gpp, btn_gpp, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 2); lv_btn_set_action(btn_emu_gpp, LV_BTN_ACTION_CLICK, _action_ums_emuemmc_gpp); + // Create emuMMC BOOT0 button. lv_obj_t *btn_emu_boot0 = lv_btn_create(h1, btn1); label_btn = lv_label_create(btn_emu_boot0, NULL); lv_label_set_static_text(label_btn, "BOOT0"); lv_obj_align(btn_emu_boot0, btn_boot0, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 2); lv_btn_set_action(btn_emu_boot0, LV_BTN_ACTION_CLICK, _action_ums_emuemmc_boot0); + // Create emuMMC BOOT1 button. lv_obj_t *btn_emu_boot1 = lv_btn_create(h1, btn1); label_btn = lv_label_create(btn_emu_boot1, NULL); lv_label_set_static_text(label_btn, "BOOT1"); @@ -747,6 +782,7 @@ static lv_res_t _create_window_usb_tools(lv_obj_t *parent) lv_cont_set_layout(h_write, LV_LAYOUT_OFF); lv_obj_align(h_write, label_txt2, LV_ALIGN_OUT_RIGHT_MID, LV_DPI / 10, 0); + // Create read/write access button. lv_obj_t *btn_write_access = lv_btn_create(h_write, NULL); nyx_create_onoff_button(lv_theme_get_current(), h_write, btn_write_access, SYMBOL_EDIT" Read-Only", _emmc_read_only_toggle, false); @@ -824,6 +860,14 @@ static int _fix_attributes(lv_obj_t *lb_val, char *path, u32 *total) return res; dirLength = strlen(path); + + // Hard limit path to 1024 characters. Do not result to error. + if (dirLength > 1024) + { + total[2]++; + goto out; + } + for (;;) { // Clear file or folder path. @@ -853,14 +897,18 @@ static int _fix_attributes(lv_obj_t *lb_val, char *path, u32 *total) { if (!(fno.fattrib & AM_ARC)) { - total[0]++; - f_chmod(path, AM_ARC, AM_ARC); + if (!f_chmod(path, AM_ARC, AM_ARC)) + total[0]++; + else + total[3]++; } } else if (fno.fattrib & AM_ARC) // If not, clear the archive bit. { - total[1]++; - f_chmod(path, 0, AM_ARC); + if (!f_chmod(path, 0, AM_ARC)) + total[1]++; + else + total[3]++; } lv_label_set_text(lb_val, path); @@ -873,6 +921,7 @@ static int _fix_attributes(lv_obj_t *lb_val, char *path, u32 *total) } } +out: f_closedir(&dir); return res; @@ -907,14 +956,14 @@ static lv_res_t _create_window_unset_abit_tool(lv_obj_t *btn) lv_obj_t * lb_val = lv_label_create(val, lb_desc); - char *path = malloc(1024); + char *path = malloc(0x1000); path[0] = 0; lv_label_set_text(lb_val, ""); lv_obj_set_width(lb_val, lv_obj_get_width(val)); lv_obj_align(val, desc, LV_ALIGN_OUT_BOTTOM_LEFT, 0, 0); - u32 total[2] = { 0 }; + u32 total[4] = { 0 }; _fix_attributes(lb_val, path, total); sd_unmount(); @@ -925,7 +974,18 @@ static lv_res_t _create_window_unset_abit_tool(lv_obj_t *btn) char *txt_buf = (char *)malloc(0x500); - s_printf(txt_buf, "#96FF00 Total archive bits fixed:# #FF8000 %d unset, %d set!#", total[1], total[0]); + if (!total[0] && !total[1]) + s_printf(txt_buf, "#96FF00 Done! No change was needed.#"); + else + s_printf(txt_buf, "#96FF00 Done! Archive bits fixed:# #FF8000 %d unset and %d set!#", total[1], total[0]); + + // Check errors. + if (total[2] || total[3]) + { + s_printf(txt_buf, "\n\n#FFDD00 Errors: folder accesses: %d, arc bit fixes: %d!#\n" + "#FFDD00 Filesystem should be checked for errors.#", + total[2], total[3]); + } lv_label_set_text(lb_desc2, txt_buf); lv_obj_set_width(lb_desc2, lv_obj_get_width(desc2)); @@ -947,11 +1007,11 @@ static lv_res_t _create_mbox_fix_touchscreen(lv_obj_t *btn) lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char *mbox_btn_map[] = { "\211", "\222OK", "\211", "" }; + static const char *mbox_btn_map[] = { "\251", "\222OK", "\251", "" }; lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); - char *txt_buf = malloc(0x4000); + char *txt_buf = malloc(SZ_16K); strcpy(txt_buf, "#FF8000 Don't touch the screen!#\n\nThe tuning process will start in "); u32 text_idx = strlen(txt_buf); lv_mbox_set_text(mbox, txt_buf); @@ -982,66 +1042,67 @@ static lv_res_t _create_mbox_fix_touchscreen(lv_obj_t *btn) } u8 err[2]; - if (touch_panel_ito_test(err)) + if (!touch_panel_ito_test(err)) + goto ito_failed; + + if (!err[0] && !err[1]) { - if (!err[0] && !err[1]) - { - res = touch_execute_autotune(); - if (res) - goto out; - } - else - { - touch_sense_enable(); + res = touch_execute_autotune(); + if (res) + goto out; + } + else + { + touch_sense_enable(); - s_printf(txt_buf, "#FFFF00 ITO Test: "); - switch (err[0]) - { - case ITO_FORCE_OPEN: - strcat(txt_buf, "Force Open"); - break; - case ITO_SENSE_OPEN: - strcat(txt_buf, "Sense Open"); - break; - case ITO_FORCE_SHRT_GND: - strcat(txt_buf, "Force Short to GND"); - break; - case ITO_SENSE_SHRT_GND: - strcat(txt_buf, "Sense Short to GND"); - break; - case ITO_FORCE_SHRT_VCM: - strcat(txt_buf, "Force Short to VDD"); - break; - case ITO_SENSE_SHRT_VCM: - strcat(txt_buf, "Sense Short to VDD"); - break; - case ITO_FORCE_SHRT_FORCE: - strcat(txt_buf, "Force Short to Force"); - break; - case ITO_SENSE_SHRT_SENSE: - strcat(txt_buf, "Sense Short to Sense"); - break; - case ITO_F2E_SENSE: - strcat(txt_buf, "Force Short to Sense"); - break; - case ITO_FPC_FORCE_OPEN: - strcat(txt_buf, "FPC Force Open"); - break; - case ITO_FPC_SENSE_OPEN: - strcat(txt_buf, "FPC Sense Open"); - break; - default: - strcat(txt_buf, "Unknown"); - break; + s_printf(txt_buf, "#FFFF00 ITO Test: "); + switch (err[0]) + { + case ITO_FORCE_OPEN: + strcat(txt_buf, "Force Open"); + break; + case ITO_SENSE_OPEN: + strcat(txt_buf, "Sense Open"); + break; + case ITO_FORCE_SHRT_GND: + strcat(txt_buf, "Force Short to GND"); + break; + case ITO_SENSE_SHRT_GND: + strcat(txt_buf, "Sense Short to GND"); + break; + case ITO_FORCE_SHRT_VCM: + strcat(txt_buf, "Force Short to VDD"); + break; + case ITO_SENSE_SHRT_VCM: + strcat(txt_buf, "Sense Short to VDD"); + break; + case ITO_FORCE_SHRT_FORCE: + strcat(txt_buf, "Force Short to Force"); + break; + case ITO_SENSE_SHRT_SENSE: + strcat(txt_buf, "Sense Short to Sense"); + break; + case ITO_F2E_SENSE: + strcat(txt_buf, "Force Short to Sense"); + break; + case ITO_FPC_FORCE_OPEN: + strcat(txt_buf, "FPC Force Open"); + break; + case ITO_FPC_SENSE_OPEN: + strcat(txt_buf, "FPC Sense Open"); + break; + default: + strcat(txt_buf, "Unknown"); + break; - } - s_printf(txt_buf + strlen(txt_buf), " (%d), Chn: %d#\n\n", err[0], err[1]); - strcat(txt_buf, "#FFFF00 The touchscreen calibration failed!"); - lv_mbox_set_text(mbox, txt_buf); - goto out2; } + s_printf(txt_buf + strlen(txt_buf), " (%d), Chn: %d#\n\n", err[0], err[1]); + strcat(txt_buf, "#FFFF00 The touchscreen calibration failed!"); + lv_mbox_set_text(mbox, txt_buf); + goto out2; } +ito_failed: touch_sense_enable(); out: @@ -1084,31 +1145,31 @@ static lv_res_t _create_window_dump_pk12_tool(lv_obj_t *btn) char path[128]; u8 kb = 0; - u8 *pkg1 = (u8 *)calloc(1, 0x40000); - u8 *warmboot = (u8 *)calloc(1, 0x40000); - u8 *secmon = (u8 *)calloc(1, 0x40000); - u8 *loader = (u8 *)calloc(1, 0x40000); + u8 *pkg1 = (u8 *)zalloc(SZ_256K); + u8 *warmboot = (u8 *)zalloc(SZ_256K); + u8 *secmon = (u8 *)zalloc(SZ_256K); + u8 *loader = (u8 *)zalloc(SZ_256K); u8 *pkg2 = NULL; - char *txt_buf = (char *)malloc(0x4000); + char *txt_buf = (char *)malloc(SZ_16K); - if (!sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400)) + if (!emmc_initialize(false)) { lv_label_set_text(lb_desc, "#FFDD00 Failed to init eMMC!#"); goto out_free; } - sdmmc_storage_set_mmc_partition(&emmc_storage, EMMC_BOOT0); + emmc_set_partition(EMMC_BOOT0); // Read package1. - static const u32 BOOTLOADER_SIZE = 0x40000; + static const u32 BOOTLOADER_SIZE = SZ_256K; static const u32 BOOTLOADER_MAIN_OFFSET = 0x100000; static const u32 HOS_KEYBLOBS_OFFSET = 0x180000; char *build_date = malloc(32); u32 pk1_offset = h_cfg.t210b01 ? sizeof(bl_hdr_t210b01_t) : 0; // Skip T210B01 OEM header. - sdmmc_storage_read(&emmc_storage, BOOTLOADER_MAIN_OFFSET / NX_EMMC_BLOCKSIZE, BOOTLOADER_SIZE / NX_EMMC_BLOCKSIZE, pkg1); + sdmmc_storage_read(&emmc_storage, BOOTLOADER_MAIN_OFFSET / EMMC_BLOCKSIZE, BOOTLOADER_SIZE / EMMC_BLOCKSIZE, pkg1); const pkg1_id_t *pkg1_id = pkg1_identify(pkg1 + pk1_offset, build_date); @@ -1144,17 +1205,16 @@ static lv_res_t _create_window_dump_pk12_tool(lv_obj_t *btn) tsec_ctxt.fw = (void *)(pkg1 + pkg1_id->tsec_off); tsec_ctxt.pkg1 = (void *)pkg1; tsec_ctxt.pkg11_off = pkg1_id->pkg11_off; - tsec_ctxt.secmon_base = pkg1_id->secmon_base; // Read keyblob. - u8 *keyblob = (u8 *)calloc(NX_EMMC_BLOCKSIZE, 1); - sdmmc_storage_read(&emmc_storage, HOS_KEYBLOBS_OFFSET / NX_EMMC_BLOCKSIZE + kb, 1, keyblob); + u8 *keyblob = (u8 *)zalloc(EMMC_BLOCKSIZE); + sdmmc_storage_read(&emmc_storage, HOS_KEYBLOBS_OFFSET / EMMC_BLOCKSIZE + kb, 1, keyblob); // Decrypt. hos_keygen(keyblob, kb, &tsec_ctxt); free(keyblob); - if (h_cfg.t210b01 || kb <= KB_FIRMWARE_VERSION_600) + if (h_cfg.t210b01 || kb <= HOS_KB_VERSION_600) { if (!pkg1_decrypt(pkg1_id, pkg1)) { @@ -1166,24 +1226,11 @@ static lv_res_t _create_window_dump_pk12_tool(lv_obj_t *btn) } } - if (h_cfg.t210b01 || kb <= KB_FIRMWARE_VERSION_620) + if (h_cfg.t210b01 || kb <= HOS_KB_VERSION_620) { - const u8 *sec_map = pkg1_unpack(warmboot, secmon, loader, pkg1_id, pkg1 + pk1_offset); - + pkg1_unpack(warmboot, secmon, loader, pkg1_id, pkg1 + pk1_offset); pk11_hdr_t *hdr_pk11 = (pk11_hdr_t *)(pkg1 + pk1_offset + pkg1_id->pkg11_off + 0x20); - // Use correct sizes. - u32 sec_size[3] = { hdr_pk11->wb_size, hdr_pk11->ldr_size, hdr_pk11->sm_size }; - for (u32 i = 0; i < 3; i++) - { - if (sec_map[i] == PK11_SECTION_WB) - hdr_pk11->wb_size = sec_size[i]; - else if (sec_map[i] == PK11_SECTION_LD) - hdr_pk11->ldr_size = sec_size[i]; - else if (sec_map[i] == PK11_SECTION_SM) - hdr_pk11->sm_size = sec_size[i]; - } - // Display info. s_printf(txt_buf + strlen(txt_buf), "#C7EA46 NX Bootloader size: #0x%05X\n" @@ -1198,7 +1245,7 @@ static lv_res_t _create_window_dump_pk12_tool(lv_obj_t *btn) // Dump package1.1. emmcsn_path_impl(path, "/pkg1", "pkg1_decr.bin", &emmc_storage); - if (sd_save_to_file(pkg1, 0x40000, path)) + if (sd_save_to_file(pkg1, SZ_256K, path)) goto out_free; strcat(txt_buf, "pkg1 dumped to pkg1_decr.bin\n"); lv_label_set_text(lb_desc, txt_buf); @@ -1241,26 +1288,26 @@ static lv_res_t _create_window_dump_pk12_tool(lv_obj_t *btn) } // Dump package2.1. - sdmmc_storage_set_mmc_partition(&emmc_storage, EMMC_GPP); + emmc_set_partition(EMMC_GPP); // Parse eMMC GPT. LIST_INIT(gpt); - nx_emmc_gpt_parse(&gpt, &emmc_storage); + emmc_gpt_parse(&gpt); // Find package2 partition. - emmc_part_t *pkg2_part = nx_emmc_part_find(&gpt, "BCPKG2-1-Normal-Main"); + emmc_part_t *pkg2_part = emmc_part_find(&gpt, "BCPKG2-1-Normal-Main"); if (!pkg2_part) goto out; // Read in package2 header and get package2 real size. - u8 *tmp = (u8 *)malloc(NX_EMMC_BLOCKSIZE); - nx_emmc_part_read(&emmc_storage, pkg2_part, 0x4000 / NX_EMMC_BLOCKSIZE, 1, tmp); + u8 *tmp = (u8 *)malloc(EMMC_BLOCKSIZE); + emmc_part_read(pkg2_part, 0x4000 / EMMC_BLOCKSIZE, 1, tmp); u32 *hdr_pkg2_raw = (u32 *)(tmp + 0x100); u32 pkg2_size = hdr_pkg2_raw[0] ^ hdr_pkg2_raw[2] ^ hdr_pkg2_raw[3]; free(tmp); // Read in package2. - u32 pkg2_size_aligned = ALIGN(pkg2_size, NX_EMMC_BLOCKSIZE); + u32 pkg2_size_aligned = ALIGN(pkg2_size, EMMC_BLOCKSIZE); pkg2 = malloc(pkg2_size_aligned); - nx_emmc_part_read(&emmc_storage, pkg2_part, 0x4000 / NX_EMMC_BLOCKSIZE, - pkg2_size_aligned / NX_EMMC_BLOCKSIZE, pkg2); + emmc_part_read(pkg2_part, 0x4000 / EMMC_BLOCKSIZE, + pkg2_size_aligned / EMMC_BLOCKSIZE, pkg2); // Dump encrypted package2. emmcsn_path_impl(path, "/pkg2", "pkg2_encr.bin", &emmc_storage); @@ -1313,12 +1360,12 @@ static lv_res_t _create_window_dump_pk12_tool(lv_obj_t *btn) manual_system_maintenance(true); // Dump INI1. - u32 ini1_off = pkg2_hdr->sec_size[PKG2_SEC_KERNEL]; + u32 ini1_off = pkg2_hdr->sec_size[PKG2_SEC_KERNEL]; u32 ini1_size = pkg2_hdr->sec_size[PKG2_SEC_INI1]; if (!ini1_size) { pkg2_get_newkern_info(pkg2_hdr->data); - ini1_off = pkg2_newkern_ini1_start; + ini1_off = pkg2_newkern_ini1_start; ini1_size = pkg2_newkern_ini1_end - pkg2_newkern_ini1_start; } @@ -1342,7 +1389,7 @@ static lv_res_t _create_window_dump_pk12_tool(lv_obj_t *btn) ptr += sizeof(pkg2_ini1_t); // Dump all kips. - u8 *kip_buffer = (u8 *)malloc(0x400000); + u8 *kip_buffer = (u8 *)malloc(SZ_4M); for (u32 i = 0; i < ini1->num_procs; i++) { @@ -1372,7 +1419,7 @@ static lv_res_t _create_window_dump_pk12_tool(lv_obj_t *btn) free(kip_buffer); out: - nx_emmc_gpt_free(&gpt); + emmc_gpt_free(&gpt); out_free: free(pkg1); free(secmon); @@ -1380,10 +1427,10 @@ out_free: free(loader); free(pkg2); free(txt_buf); - sdmmc_storage_end(&emmc_storage); + emmc_end(); sd_unmount(); - if (kb >= KB_FIRMWARE_VERSION_620) + if (kb >= HOS_KB_VERSION_620) se_aes_key_clear(8); out_end: // Enable buttons. @@ -1531,7 +1578,7 @@ static void _create_tab_tools_arc_autorcm(lv_theme_t *th, lv_obj_t *parent) lv_line_set_style(line_sep, th->line.decor); lv_obj_align(line_sep, label_txt, LV_ALIGN_OUT_BOTTOM_LEFT, -(LV_DPI / 4), LV_DPI / 8); - // Create Unset archive bit button. + // Create fix archive bit button. lv_obj_t *btn = lv_btn_create(h1, NULL); if (hekate_bg) { @@ -1601,7 +1648,7 @@ static void _create_tab_tools_arc_autorcm(lv_theme_t *th, lv_obj_t *parent) lv_btn_set_action(btn3, LV_BTN_ACTION_CLICK, _create_mbox_autorcm_status); // Set default state for AutoRCM and lock it out if patched unit. - if (get_autorcm_status(false)) + if (get_set_autorcm_status(false)) lv_btn_set_state(btn3, LV_BTN_STATE_TGL_REL); else lv_btn_set_state(btn3, LV_BTN_STATE_REL); @@ -1614,7 +1661,7 @@ static void _create_tab_tools_arc_autorcm(lv_theme_t *th, lv_obj_t *parent) } autorcm_btn = btn3; - char *txt_buf = (char *)malloc(0x1000); + char *txt_buf = (char *)malloc(SZ_4K); s_printf(txt_buf, "Allows you to enter RCM without using #C7EA46 VOL+# & #C7EA46 HOME# (jig).\n" diff --git a/nyx/nyx_gui/frontend/gui_tools.h b/nyx/nyx_gui/frontend/gui_tools.h index c841708..ae4bbf1 100644 --- a/nyx/nyx_gui/frontend/gui_tools.h +++ b/nyx/nyx_gui/frontend/gui_tools.h @@ -23,7 +23,7 @@ extern lv_obj_t *ums_mbox; void create_tab_tools(lv_theme_t *th, lv_obj_t *parent); void nyx_run_ums(void *param); -bool get_autorcm_status(bool change); +bool get_set_autorcm_status(bool change); lv_res_t action_ums_sd(lv_obj_t *btn); #endif diff --git a/nyx/nyx_gui/frontend/gui_tools_partition_manager.c b/nyx/nyx_gui/frontend/gui_tools_partition_manager.c index 479b45e..3ea91cb 100644 --- a/nyx/nyx_gui/frontend/gui_tools_partition_manager.c +++ b/nyx/nyx_gui/frontend/gui_tools_partition_manager.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019-2021 CTCaer + * Copyright (c) 2019-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -16,24 +16,21 @@ #include +#include + #include "gui.h" #include "gui_tools.h" #include "gui_tools_partition_manager.h" #include #include -#include -#include -#include -#include -#include -#include -#include "../storage/nx_emmc.h" -#include -#include -#include -#include -#include -#include + +#define AU_ALIGN_SECTORS 0x8000 // 16MB. +#define AU_ALIGN_BYTES (AU_ALIGN_SECTORS * SD_BLOCKSIZE) + +#define SECTORS_PER_GB 0x200000 + +#define HOS_MIN_SIZE_MB 2048 +#define ANDROID_SYSTEM_SIZE_MB 6144 // 6 GB. Fits both Legacy (4912MB) and Dynamic (6144MB) partition schemes. extern volatile boot_cfg_t *b_cfg; extern volatile nyx_storage_t *nyx_str; @@ -50,6 +47,9 @@ typedef struct _partition_ctxt_t u32 and_size; bool emu_double; + bool emmc_is_64gb; + + bool and_dynamic; mbr_t mbr_old; @@ -71,8 +71,6 @@ typedef struct _partition_ctxt_t lv_obj_t *lbl_emu; lv_obj_t *lbl_l4t; lv_obj_t *lbl_and; - - lv_obj_t *btn_partition; } partition_ctxt_t; typedef struct _l4t_flasher_ctxt_t @@ -87,7 +85,46 @@ l4t_flasher_ctxt_t l4t_flash_ctxt; lv_obj_t *btn_flash_l4t; lv_obj_t *btn_flash_android; -static int _backup_and_restore_files(char *path, u32 *total_files, u32 *total_size, const char *dst, const char *src, lv_obj_t **labels) +int _copy_file(const char *src, const char *dst, const char *path) +{ + FIL fp_src; + FIL fp_dst; + int res; + + // Open file for reading. + f_chdrive(src); + res = f_open(&fp_src, path, FA_READ); + if (res != FR_OK) + return res; + + u32 file_bytes_left = f_size(&fp_src); + + // Open file for writing. + f_chdrive(dst); + f_open(&fp_dst, path, FA_CREATE_ALWAYS | FA_WRITE); + f_lseek(&fp_dst, f_size(&fp_src)); + f_lseek(&fp_dst, 0); + + while (file_bytes_left) + { + u32 chunk_size = MIN(file_bytes_left, SZ_4M); // 4MB chunks. + file_bytes_left -= chunk_size; + + // Copy file to buffer. + f_read(&fp_src, (void *)SDXC_BUF_ALIGNED, chunk_size, NULL); + + // Write file to disk. + f_write(&fp_dst, (void *)SDXC_BUF_ALIGNED, chunk_size, NULL); + } + + f_close(&fp_dst); + f_chdrive(src); + f_close(&fp_src); + + return FR_OK; +} + +static int _stat_and_copy_files(const char *src, const char *dst, char *path, u32 *total_files, u32 *total_size, lv_obj_t **labels) { FRESULT res; FIL fp_src; @@ -96,8 +133,7 @@ static int _backup_and_restore_files(char *path, u32 *total_files, u32 *total_si u32 dirLength = 0; static FILINFO fno; - if (src) - f_chdrive(src); + f_chdrive(src); // Open directory. res = f_opendir(&dir, path); @@ -108,6 +144,11 @@ static int _backup_and_restore_files(char *path, u32 *total_files, u32 *total_si lv_label_set_text(labels[0], path); dirLength = strlen(path); + + // Hard limit path to 1024 characters. Do not result to error. + if (dirLength > 1024) + goto out; + for (;;) { // Clear file path. @@ -139,7 +180,7 @@ static int _backup_and_restore_files(char *path, u32 *total_files, u32 *total_si if ((file_size + *total_size) < *total_size) { // Set size to > 1GB, skip next folders and return. - *total_size = 0x80000000; + *total_size = SZ_2G; res = -1; break; } @@ -147,9 +188,9 @@ static int _backup_and_restore_files(char *path, u32 *total_files, u32 *total_si *total_size += file_size; *total_files += 1; - if (src && dst) + if (dst) { - u32 file_size = fno.fsize; + u32 file_bytes_left = fno.fsize; // Open file for writing. f_chdrive(dst); @@ -161,10 +202,10 @@ static int _backup_and_restore_files(char *path, u32 *total_files, u32 *total_si f_chdrive(src); f_open(&fp_src, path, FA_READ); - while (file_size) + while (file_bytes_left) { - u32 chunk_size = MIN(file_size, 0x400000); // 4MB chunks. - file_size -= chunk_size; + u32 chunk_size = MIN(file_bytes_left, SZ_4M); // 4MB chunks. + file_bytes_left -= chunk_size; // Copy file to buffer. f_read(&fp_src, (void *)SDXC_BUF_ALIGNED, chunk_size, NULL); @@ -173,7 +214,6 @@ static int _backup_and_restore_files(char *path, u32 *total_files, u32 *total_si // Write file to disk. f_write(&fp_dst, (void *)SDXC_BUF_ALIGNED, chunk_size, NULL); } - f_close(&fp_src); // Finalize copied file. f_close(&fp_dst); @@ -181,10 +221,11 @@ static int _backup_and_restore_files(char *path, u32 *total_files, u32 *total_si f_chmod(path, fno.fattrib, 0xFF); f_chdrive(src); + f_close(&fp_src); } // If total is > 1GB exit. - if (*total_size > (RAM_DISK_SZ - 0x1000000)) // 0x2400000. + if (*total_size > (RAM_DISK_SZ - SZ_16M)) // 0x2400000. { // Skip next folders and return. res = -1; @@ -201,9 +242,11 @@ static int _backup_and_restore_files(char *path, u32 *total_files, u32 *total_si { f_chdrive(dst); f_mkdir(path); + f_chmod(path, fno.fattrib, 0xFF); } + // Enter the directory. - res = _backup_and_restore_files(path, total_files, total_size, dst, src, labels); + res = _stat_and_copy_files(src, dst, path, total_files, total_size, labels); if (res != FR_OK) break; @@ -216,11 +259,39 @@ static int _backup_and_restore_files(char *path, u32 *total_files, u32 *total_si } } +out: f_closedir(&dir); return res; } +static void _create_gpt_partition(gpt_t *gpt, u8 *gpt_idx, u32 *curr_part_lba, u32 size_lba, const char *name, int name_size) +{ + static const u8 linux_part_guid[] = { 0xAF, 0x3D, 0xC6, 0x0F, 0x83, 0x84, 0x72, 0x47, 0x8E, 0x79, 0x3D, 0x69, 0xD8, 0x47, 0x7D, 0xE4 }; + u8 random_number[16]; + + // Create GPT partition. + memcpy(gpt->entries[*gpt_idx].type_guid, linux_part_guid, 16); + + // Set randomly created GUID + se_gen_prng128(random_number); + memcpy(gpt->entries[*gpt_idx].part_guid, random_number, 16); + + // Set partition start and end. + gpt->entries[*gpt_idx].lba_start = *curr_part_lba; + gpt->entries[*gpt_idx].lba_end = *curr_part_lba + size_lba - 1; + + // Set name. + memcpy(gpt->entries[*gpt_idx].name, name, name_size); + + // Wipe the first 1MB to sanitize it as raw-empty partition. + sdmmc_storage_write(&sd_storage, *curr_part_lba, 0x800, (void *)SDMMC_UPPER_BUFFER); + + // Prepare for next. + (*curr_part_lba) += size_lba; + (*gpt_idx)++; +} + static void _prepare_and_flash_mbr_gpt() { mbr_t mbr; @@ -234,8 +305,8 @@ static void _prepare_and_flash_mbr_gpt() memcpy(&mbr.bootstrap[0x80], &part_info.mbr_old.bootstrap[0x80], 304); // Clear the first 16MB. - memset((void *)SDMMC_UPPER_BUFFER, 0, 0x8000); - sdmmc_storage_write(&sd_storage, 0, 0x8000, (void *)SDMMC_UPPER_BUFFER); + memset((void *)SDMMC_UPPER_BUFFER, 0, AU_ALIGN_BYTES); + sdmmc_storage_write(&sd_storage, 0, AU_ALIGN_SECTORS, (void *)SDMMC_UPPER_BUFFER); u8 mbr_idx = 1; se_gen_prng128(random_number); @@ -245,7 +316,7 @@ static void _prepare_and_flash_mbr_gpt() if (part_info.l4t_size && !part_info.and_size) { mbr.partitions[mbr_idx].type = 0x83; // Linux system partition. - mbr.partitions[mbr_idx].start_sct = 0x8000 + ((u32)part_info.hos_size << 11); + mbr.partitions[mbr_idx].start_sct = AU_ALIGN_SECTORS + ((u32)part_info.hos_size << 11); mbr.partitions[mbr_idx].size_sct = part_info.l4t_size << 11; sdmmc_storage_write(&sd_storage, mbr.partitions[mbr_idx].start_sct, 0x800, (void *)SDMMC_UPPER_BUFFER); // Clear the first 1MB. mbr_idx++; @@ -255,7 +326,7 @@ static void _prepare_and_flash_mbr_gpt() if (part_info.emu_size) { mbr.partitions[mbr_idx].type = 0xE0; // emuMMC partition. - mbr.partitions[mbr_idx].start_sct = 0x8000 + ((u32)part_info.hos_size << 11) + (part_info.l4t_size << 11) + (part_info.and_size << 11); + mbr.partitions[mbr_idx].start_sct = AU_ALIGN_SECTORS + ((u32)part_info.hos_size << 11) + (part_info.l4t_size << 11) + (part_info.and_size << 11); if (!part_info.emu_double) mbr.partitions[mbr_idx].size_sct = (part_info.emu_size << 11) - 0x800; // Reserve 1MB. @@ -274,10 +345,11 @@ static void _prepare_and_flash_mbr_gpt() if (part_info.and_size) { - gpt_t *gpt = calloc(1, sizeof(gpt_t)); + gpt_t *gpt = zalloc(sizeof(gpt_t)); gpt_header_t gpt_hdr_backup = { 0 }; - mbr.partitions[mbr_idx].type = 0xEE; // GPT protective partition. + // Set GPT protective partition in MBR. + mbr.partitions[mbr_idx].type = 0xEE; mbr.partitions[mbr_idx].start_sct = 1; mbr.partitions[mbr_idx].size_sct = sd_storage.sec_cnt - 1; mbr_idx++; @@ -296,8 +368,8 @@ static void _prepare_and_flash_mbr_gpt() gpt->header.part_ent_lba = 2; gpt->header.part_ent_size = 128; - // Set GPT partitions. - u8 basic_part_guid[] = { 0xA2, 0xA0, 0xD0, 0xEB, 0xE5, 0xB9, 0x33, 0x44, 0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7 }; + // Set FAT GPT partition manually. + const u8 basic_part_guid[] = { 0xA2, 0xA0, 0xD0, 0xEB, 0xE5, 0xB9, 0x33, 0x44, 0x87, 0xC0, 0x68, 0xB6, 0xB7, 0x26, 0x99, 0xC7 }; memcpy(gpt->entries[0].type_guid, basic_part_guid, 16); se_gen_prng128(random_number); memcpy(gpt->entries[0].part_guid, random_number, 16); @@ -309,127 +381,79 @@ static void _prepare_and_flash_mbr_gpt() gpt->entries[0].lba_end = mbr.partitions[0].start_sct + mbr.partitions[0].size_sct - 1; memcpy(gpt->entries[0].name, (char[]) { 'h', 0, 'o', 0, 's', 0, '_', 0, 'd', 0, 'a', 0, 't', 0, 'a', 0 }, 16); - u8 gpt_idx = 1; - u32 curr_part_lba = 0x8000 + ((u32)part_info.hos_size << 11); - u8 android_part_guid[] = { 0xAF, 0x3D, 0xC6, 0x0F, 0x83, 0x84, 0x72, 0x47, 0x8E, 0x79, 0x3D, 0x69, 0xD8, 0x47, 0x7D, 0xE4 }; - if (part_info.l4t_size) - { - memcpy(gpt->entries[gpt_idx].type_guid, android_part_guid, 16); - se_gen_prng128(random_number); - memcpy(gpt->entries[gpt_idx].part_guid, random_number, 16); - gpt->entries[gpt_idx].lba_start = curr_part_lba; - gpt->entries[gpt_idx].lba_end = curr_part_lba + (part_info.l4t_size << 11) - 1; - memcpy(gpt->entries[gpt_idx].name, (char[]) { 'l', 0, '4', 0, 't', 0 }, 6); - sdmmc_storage_write(&sd_storage, curr_part_lba, 0x800, (void *)SDMMC_UPPER_BUFFER); // Clear the first 1MB. + // Set the rest of GPT partitions. + u8 gpt_idx = 1; + u32 curr_part_lba = AU_ALIGN_SECTORS + ((u32)part_info.hos_size << 11); - curr_part_lba += (part_info.l4t_size << 11); - gpt_idx++; + // L4T partition. + if (part_info.l4t_size) + _create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, part_info.l4t_size << 11, (char[]) { 'l', 0, '4', 0, 't', 0 }, 6); + + if (part_info.and_dynamic) + { + // Android Linux Kernel partition. 64MB. + _create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x20000, (char[]) { 'b', 0, 'o', 0, 'o', 0, 't', 0 }, 8); + + // Android Recovery partition. 64MB. + _create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x20000, (char[]) { 'r', 0, 'e', 0, 'c', 0, 'o', 0, 'v', 0, 'e', 0, 'r', 0, 'y', 0 }, 16); + + // Android Device Tree Reference partition. 1MB. + _create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x800, (char[]) { 'd', 0, 't', 0, 'b', 0 }, 6); + + // Android Misc partition. 3MB. + _create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x1800, (char[]) { 'm', 0, 'i', 0, 's', 0, 'c', 0 }, 8); + + // Android Cache partition. 60MB. + _create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x1E000, (char[]) { 'c', 0, 'a', 0, 'c', 0, 'h', 0, 'e', 0 }, 10); + + // Android Super dynamic partition. 5922MB. + _create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0xB91000, (char[]) { 's', 0, 'u', 0, 'p', 0, 'e', 0, 'r', 0 }, 10); + + // Android Userdata partition. + u32 uda_size = (part_info.and_size << 11) - 0xC00000; // Subtract the other partitions (6144MB). + if (!part_info.emu_size) + uda_size -= 0x800; // Reserve 1MB. + _create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, uda_size, (char[]) { 'u', 0, 's', 0, 'e', 0, 'r', 0, 'd', 0, 'a', 0, 't', 0, 'a', 0 }, 16); + } + else + { + // Android Vendor partition. 1GB + _create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x200000, (char[]) { 'v', 0, 'e', 0, 'n', 0, 'd', 0, 'o', 0, 'r', 0 }, 12); + + // Android System partition. 3GB. + _create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x600000, (char[]) { 'A', 0, 'P', 0, 'P', 0 }, 6); + + // Android Linux Kernel partition. 32MB. + _create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x10000, (char[]) { 'L', 0, 'N', 0, 'X', 0 }, 6); + + // Android Recovery partition. 64MB. + _create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x20000, (char[]) { 'S', 0, 'O', 0, 'S', 0 }, 6); + + // Android Device Tree Reference partition. 1MB. + _create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x800, (char[]) { 'D', 0, 'T', 0, 'B', 0 }, 6); + + // Android Encryption partition. 16MB. + // Note: 16MB size is for aligning UDA. If any other tiny partition must be added, it should split the MDA one. + sdmmc_storage_write(&sd_storage, curr_part_lba, 0x8000, (void *)SDMMC_UPPER_BUFFER); // Clear the whole of it. + _create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x8000, (char[]) { 'M', 0, 'D', 0, 'A', 0 }, 6); + + // Android Cache partition. 700MB. + _create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x15E000, (char[]) { 'C', 0, 'A', 0, 'C', 0 }, 6); + + // Android Misc partition. 3MB. + _create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, 0x1800, (char[]) { 'M', 0, 'S', 0, 'C', 0 }, 6); + + // Android Userdata partition. + u32 uda_size = (part_info.and_size << 11) - 0x998000; // Subtract the other partitions (4912MB). + if (!part_info.emu_size) + uda_size -= 0x800; // Reserve 1MB. + _create_gpt_partition(gpt, &gpt_idx, &curr_part_lba, uda_size, (char[]) { 'U', 0, 'D', 0, 'A', 0 }, 6); } - // Android Vendor partition. - memcpy(gpt->entries[gpt_idx].type_guid, android_part_guid, 16); - se_gen_prng128(random_number); - memcpy(gpt->entries[gpt_idx].part_guid, random_number, 16); - gpt->entries[gpt_idx].lba_start = curr_part_lba; - gpt->entries[gpt_idx].lba_end = curr_part_lba + 0x200000 - 1; // 1GB. - memcpy(gpt->entries[gpt_idx].name, (char[]) { 'v', 0, 'e', 0, 'n', 0, 'd', 0, 'o', 0, 'r', 0 }, 12); - sdmmc_storage_write(&sd_storage, curr_part_lba, 0x800, (void *)SDMMC_UPPER_BUFFER); // Clear the first 1MB. - curr_part_lba += 0x200000; - gpt_idx++; - - // Android System partition. - memcpy(gpt->entries[gpt_idx].type_guid, android_part_guid, 16); - se_gen_prng128(random_number); - memcpy(gpt->entries[gpt_idx].part_guid, random_number, 16); - gpt->entries[gpt_idx].lba_start = curr_part_lba; - gpt->entries[gpt_idx].lba_end = curr_part_lba + 0x400000 - 1; // 2GB. - memcpy(gpt->entries[gpt_idx].name, (char[]) { 'A', 0, 'P', 0, 'P', 0 }, 6); - sdmmc_storage_write(&sd_storage, curr_part_lba, 0x800, (void *)SDMMC_UPPER_BUFFER); // Clear the first 1MB. - curr_part_lba += 0x400000; - gpt_idx++; - - // Android Linux Kernel partition. - memcpy(gpt->entries[gpt_idx].type_guid, android_part_guid, 16); - se_gen_prng128(random_number); - memcpy(gpt->entries[gpt_idx].part_guid, random_number, 16); - gpt->entries[gpt_idx].lba_start = curr_part_lba; - gpt->entries[gpt_idx].lba_end = curr_part_lba + 0x10000 - 1; // 32MB. - memcpy(gpt->entries[gpt_idx].name, (char[]) { 'L', 0, 'N', 0, 'X', 0 }, 6); - sdmmc_storage_write(&sd_storage, curr_part_lba, 0x800, (void *)SDMMC_UPPER_BUFFER); // Clear the first 1MB. - curr_part_lba += 0x10000; - gpt_idx++; - - // Android Recovery partition. - memcpy(gpt->entries[gpt_idx].type_guid, android_part_guid, 16); - se_gen_prng128(random_number); - memcpy(gpt->entries[gpt_idx].part_guid, random_number, 16); - gpt->entries[gpt_idx].lba_start = curr_part_lba; - gpt->entries[gpt_idx].lba_end = curr_part_lba + 0x20000 - 1; // 64MB. - memcpy(gpt->entries[gpt_idx].name, (char[]) { 'S', 0, 'O', 0, 'S', 0 }, 6); - sdmmc_storage_write(&sd_storage, curr_part_lba, 0x800, (void *)SDMMC_UPPER_BUFFER); // Clear the first 1MB. - curr_part_lba += 0x20000; - gpt_idx++; - - // Android Device Tree Reference partition. - memcpy(gpt->entries[gpt_idx].type_guid, android_part_guid, 16); - se_gen_prng128(random_number); - memcpy(gpt->entries[gpt_idx].part_guid, random_number, 16); - gpt->entries[gpt_idx].lba_start = curr_part_lba; - gpt->entries[gpt_idx].lba_end = curr_part_lba + 0x800 - 1; // 1MB. - memcpy(gpt->entries[gpt_idx].name, (char[]) { 'D', 0, 'T', 0, 'B', 0 }, 6); - sdmmc_storage_write(&sd_storage, curr_part_lba, 0x800, (void *)SDMMC_UPPER_BUFFER); // Clear the first 1MB. - curr_part_lba += 0x800; - gpt_idx++; - - // Android Encryption partition. - memcpy(gpt->entries[gpt_idx].type_guid, android_part_guid, 16); - se_gen_prng128(random_number); - memcpy(gpt->entries[gpt_idx].part_guid, random_number, 16); - gpt->entries[gpt_idx].lba_start = curr_part_lba; - gpt->entries[gpt_idx].lba_end = curr_part_lba + 0x8000 - 1; // 16MB. - memcpy(gpt->entries[gpt_idx].name, (char[]) { 'M', 0, 'D', 0, 'A', 0 }, 6); - sdmmc_storage_write(&sd_storage, curr_part_lba, 0x8000, (void *)SDMMC_UPPER_BUFFER); // Clear 16MB. - curr_part_lba += 0x8000; - gpt_idx++; - - // Android Cache partition. - memcpy(gpt->entries[gpt_idx].type_guid, android_part_guid, 16); - se_gen_prng128(random_number); - memcpy(gpt->entries[gpt_idx].part_guid, random_number, 16); - gpt->entries[gpt_idx].lba_start = curr_part_lba; - gpt->entries[gpt_idx].lba_end = curr_part_lba + 0x15E000 - 1; // 700MB. - memcpy(gpt->entries[gpt_idx].name, (char[]) { 'C', 0, 'A', 0, 'C', 0 }, 6); - sdmmc_storage_write(&sd_storage, curr_part_lba, 0x800, (void *)SDMMC_UPPER_BUFFER); // Clear the first 1MB. - curr_part_lba += 0x15E000; - gpt_idx++; - - // Android Misc partition. - memcpy(gpt->entries[gpt_idx].type_guid, android_part_guid, 16); - se_gen_prng128(random_number); - memcpy(gpt->entries[gpt_idx].part_guid, random_number, 16); - gpt->entries[gpt_idx].lba_start = curr_part_lba; - gpt->entries[gpt_idx].lba_end = curr_part_lba + 0x1800 - 1; // 3MB. - memcpy(gpt->entries[gpt_idx].name, (char[]) { 'M', 0, 'S', 0, 'C', 0 }, 6); - sdmmc_storage_write(&sd_storage, curr_part_lba, 0x800, (void *)SDMMC_UPPER_BUFFER); // Clear the first 1MB. - curr_part_lba += 0x1800; - gpt_idx++; - - // Android Userdata partition. - u32 user_size = (part_info.and_size << 11) - 0x798000; // Subtract the other partitions (3888MB). - if (!part_info.emu_size) - user_size -= 0x800; // Reserve 1MB. - memcpy(gpt->entries[gpt_idx].type_guid, android_part_guid, 16); - se_gen_prng128(random_number); - memcpy(gpt->entries[gpt_idx].part_guid, random_number, 16); - gpt->entries[gpt_idx].lba_start = curr_part_lba; - gpt->entries[gpt_idx].lba_end = curr_part_lba + user_size - 1; - memcpy(gpt->entries[gpt_idx].name, (char[]) { 'U', 0, 'D', 0, 'A', 0 }, 6); - sdmmc_storage_write(&sd_storage, curr_part_lba, 0x800, (void *)SDMMC_UPPER_BUFFER); // Clear the first 1MB. - curr_part_lba += user_size; - gpt_idx++; - + // Handle emuMMC partitions manually. if (part_info.emu_size) { + // Set 1st emuMMC. u8 emu_part_guid[] = { 0x00, 0x7E, 0xCA, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 'e', 'm', 'u', 'M', 'M', 'C' }; memcpy(gpt->entries[gpt_idx].type_guid, emu_part_guid, 16); se_gen_prng128(random_number); @@ -442,6 +466,7 @@ static void _prepare_and_flash_mbr_gpt() memcpy(gpt->entries[gpt_idx].name, (char[]) { 'e', 0, 'm', 0, 'u', 0, 'm', 0, 'm', 0, 'c', 0 }, 12); gpt_idx++; + // Set 2nd emuMMC. if (part_info.emu_double) { curr_part_lba += (part_info.emu_size << 10); @@ -456,11 +481,12 @@ static void _prepare_and_flash_mbr_gpt() } // Set final GPT header parameters. - gpt->header.num_part_ents = 128; - gpt->header.part_ents_crc32 = crc32_calc(0, (const u8 *)gpt->entries, sizeof(gpt_entry_t) * 128); + gpt->header.num_part_ents = gpt_idx; + gpt->header.part_ents_crc32 = crc32_calc(0, (const u8 *)gpt->entries, sizeof(gpt_entry_t) * gpt->header.num_part_ents); gpt->header.crc32 = 0; // Set to 0 for calculation. gpt->header.crc32 = crc32_calc(0, (const u8 *)&gpt->header, gpt->header.size); + // Set final backup GPT header parameters. memcpy(&gpt_hdr_backup, &gpt->header, sizeof(gpt_header_t)); gpt_hdr_backup.my_lba = sd_storage.sec_cnt - 1; gpt_hdr_backup.alt_lba = 1; @@ -488,17 +514,13 @@ static lv_res_t _action_part_manager_ums_sd(lv_obj_t *btn) { action_ums_sd(btn); - if (lv_btn_get_state(part_info.btn_partition) != LV_BTN_STATE_INA) - { - lv_action_t close_btn_action = lv_btn_get_action(close_btn, LV_BTN_ACTION_CLICK); - close_btn_action(close_btn); - lv_obj_del(ums_mbox); - create_window_partition_manager(NULL); + // Close and reopen partition manager. + lv_action_t close_btn_action = lv_btn_get_action(close_btn, LV_BTN_ACTION_CLICK); + close_btn_action(close_btn); + lv_obj_del(ums_mbox); + create_window_partition_manager(NULL); - return LV_RES_INV; - } - - return LV_RES_OK; + return LV_RES_INV; } static lv_res_t _action_delete_linux_installer_files(lv_obj_t * btns, const char * txt) @@ -555,183 +577,190 @@ static lv_res_t _action_flash_linux_data(lv_obj_t * btns, const char * txt) bool succeeded = false; + if (btn_idx) + return LV_RES_INV; + // Flash Linux. - if (!btn_idx) + lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL); + lv_obj_set_style(dark_bg, &mbox_darken); + lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); + + static const char *mbox_btn_map[] = { "\251", "\222OK", "\251", "" }; + static const char *mbox_btn_map2[] = { "\223Delete Installation Files", "\221OK", "" }; + lv_obj_t *mbox = lv_mbox_create(dark_bg, NULL); + lv_mbox_set_recolor_text(mbox, true); + lv_obj_set_width(mbox, LV_HOR_RES / 10 * 5); + + lv_mbox_set_text(mbox, "#FF8000 Linux Flasher#"); + + lv_obj_t *lbl_status = lv_label_create(mbox, NULL); + lv_label_set_recolor(lbl_status, true); + lv_label_set_text(lbl_status, "#C7EA46 Status:# Flashing Linux..."); + + // Create container to keep content inside. + lv_obj_t *h1 = lv_cont_create(mbox, NULL); + lv_cont_set_fit(h1, true, true); + lv_cont_set_style(h1, &lv_style_transp_tight); + + lv_obj_t *bar = lv_bar_create(h1, NULL); + lv_obj_set_size(bar, LV_DPI * 30 / 10, LV_DPI / 5); + lv_bar_set_range(bar, 0, 100); + lv_bar_set_value(bar, 0); + + lv_obj_t *label_pct = lv_label_create(h1, NULL); + lv_label_set_recolor(label_pct, true); + lv_label_set_text(label_pct, " "SYMBOL_DOT" 0%"); + lv_label_set_style(label_pct, lv_theme_get_current()->label.prim); + lv_obj_align(label_pct, bar, LV_ALIGN_OUT_RIGHT_MID, LV_DPI / 20, 0); + + lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); + lv_obj_set_top(mbox, true); + + sd_mount(); + + int res = 0; + char *path = malloc(1024); + char *txt_buf = malloc(SZ_4K); + strcpy(path, "switchroot/install/l4t.00"); + u32 path_len = strlen(path) - 2; + + FIL fp; + + res = f_open(&fp, path, FA_READ); + if (res) { - lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL); - lv_obj_set_style(dark_bg, &mbox_darken); - lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); + lv_label_set_text(lbl_status, "#FFDD00 Error:# Failed to open 1st part!"); - static const char *mbox_btn_map[] = { "\211", "\222OK", "\211", "" }; - static const char *mbox_btn_map2[] = { "\223Delete Installation Files", "\221OK", "" }; - lv_obj_t *mbox = lv_mbox_create(dark_bg, NULL); - lv_mbox_set_recolor_text(mbox, true); - lv_obj_set_width(mbox, LV_HOR_RES / 10 * 5); + goto exit; + } - lv_mbox_set_text(mbox, "#FF8000 Linux Flasher#"); + u64 fileSize = (u64)f_size(&fp); - lv_obj_t *lbl_status = lv_label_create(mbox, NULL); - lv_label_set_recolor(lbl_status, true); - lv_label_set_text(lbl_status, "#C7EA46 Status:# Flashing Linux..."); + u32 num = 0; + u32 pct = 0; + u32 lba_curr = 0; + u32 bytesWritten = 0; + u32 currPartIdx = 0; + u32 prevPct = 200; + int retryCount = 0; + u32 total_size_sct = l4t_flash_ctxt.image_size_sct; - // Create container to keep content inside. - lv_obj_t *h1 = lv_cont_create(mbox, NULL); - lv_cont_set_fit(h1, true, true); - lv_cont_set_style(h1, &lv_style_transp_tight); + u8 *buf = (u8 *)MIXD_BUF_ALIGNED; + DWORD *clmt = f_expand_cltbl(&fp, SZ_4M, 0); - lv_obj_t *bar = lv_bar_create(h1, NULL); - lv_obj_set_size(bar, LV_DPI * 30 / 10, LV_DPI / 5); - lv_bar_set_range(bar, 0, 100); - lv_bar_set_value(bar, 0); + // Start flashing L4T. + while (total_size_sct > 0) + { + // If we have more than one part, check the size for the split parts and make sure that the bytes written is not more than that. + if (bytesWritten >= fileSize) + { + // If we have more bytes written then close the file pointer and increase the part index we are using + f_close(&fp); + free(clmt); + memset(&fp, 0, sizeof(fp)); + currPartIdx++; - lv_obj_t *label_pct = lv_label_create(h1, NULL); - lv_label_set_recolor(label_pct, true); - lv_label_set_text(label_pct, " "SYMBOL_DOT" 0%"); - lv_label_set_style(label_pct, lv_theme_get_current()->label.prim); - lv_obj_align(label_pct, bar, LV_ALIGN_OUT_RIGHT_MID, LV_DPI / 20, 0); + if (currPartIdx < 10) + { + path[path_len] = '0'; + itoa(currPartIdx, &path[path_len + 1], 10); + } + else + itoa(currPartIdx, &path[path_len], 10); - lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); - lv_obj_set_top(mbox, true); + // Try to open the next file part + res = f_open(&fp, path, FA_READ); + if (res) + { + s_printf(txt_buf, "#FFDD00 Error:# Failed to open part %d#", currPartIdx); + lv_label_set_text(lbl_status, txt_buf); + manual_system_maintenance(true); - sd_mount(); + goto exit; + } + fileSize = (u64)f_size(&fp); + bytesWritten = 0; + clmt = f_expand_cltbl(&fp, SZ_4M, 0); + } - int res = 0; - char *path = malloc(1024); - char *txt_buf = malloc(0x1000); - strcpy(path, "switchroot/install/l4t.00"); - u32 path_len = strlen(path) - 2; + retryCount = 0; + num = MIN(total_size_sct, 8192); - FIL fp; + // Read next data block from SD. + res = f_read_fast(&fp, buf, num << 9); + manual_system_maintenance(false); - res = f_open(&fp, path, FA_READ); if (res) { - lv_label_set_text(lbl_status, "#FFDD00 Error:# Failed to open 1st part!"); + lv_label_set_text(lbl_status, "#FFDD00 Error:# Reading from SD!"); + manual_system_maintenance(true); + f_close(&fp); + free(clmt); goto exit; } - u64 fileSize = (u64)f_size(&fp); + // Write data block to L4T partition. + res = !sdmmc_storage_write(&sd_storage, lba_curr + l4t_flash_ctxt.offset_sct, num, buf); - u32 num = 0; - u32 pct = 0; - u32 lba_curr = 0; - u32 bytesWritten = 0; - u32 currPartIdx = 0; - u32 prevPct = 200; - int retryCount = 0; - u32 total_size_sct = l4t_flash_ctxt.image_size_sct; + manual_system_maintenance(false); - u8 *buf = (u8 *)MIXD_BUF_ALIGNED; - DWORD *clmt = f_expand_cltbl(&fp, 0x400000, 0); - - while (total_size_sct > 0) + // If failed, retry 3 more times. + while (res) { - // If we have more than one part, check the size for the split parts and make sure that the bytes written is not more than that. - if (bytesWritten >= fileSize) + msleep(150); + manual_system_maintenance(true); + + if (retryCount >= 3) { - // If we have more bytes written then close the file pointer and increase the part index we are using - f_close(&fp); - free(clmt); - memset(&fp, 0, sizeof(fp)); - currPartIdx++; - - if (currPartIdx < 10) - { - path[path_len] = '0'; - itoa(currPartIdx, &path[path_len + 1], 10); - } - else - itoa(currPartIdx, &path[path_len], 10); - - // Try to open the next file part - res = f_open(&fp, path, FA_READ); - if (res) - { - s_printf(txt_buf, "#FFDD00 Error:# Failed to open part %d#", currPartIdx); - lv_label_set_text(lbl_status, txt_buf); - manual_system_maintenance(true); - - goto exit; - } - fileSize = (u64)f_size(&fp); - bytesWritten = 0; - clmt = f_expand_cltbl(&fp, 0x400000, 0); - } - - retryCount = 0; - num = MIN(total_size_sct, 8192); - - res = f_read_fast(&fp, buf, num << 9); - manual_system_maintenance(false); - - if (res) - { - lv_label_set_text(lbl_status, "#FFDD00 Error:# Reading from SD!"); + lv_label_set_text(lbl_status, "#FFDD00 Error:# Writing to SD!"); manual_system_maintenance(true); f_close(&fp); free(clmt); goto exit; } + res = !sdmmc_storage_write(&sd_storage, lba_curr + l4t_flash_ctxt.offset_sct, num, buf); - manual_system_maintenance(false); - - while (res) - { - msleep(150); - manual_system_maintenance(true); - - if (retryCount >= 3) - { - lv_label_set_text(lbl_status, "#FFDD00 Error:# Writing to SD!"); - manual_system_maintenance(true); - - f_close(&fp); - free(clmt); - goto exit; - } - - res = !sdmmc_storage_write(&sd_storage, lba_curr + l4t_flash_ctxt.offset_sct, num, buf); - manual_system_maintenance(false); - } - pct = (u64)((u64)lba_curr * 100u) / (u64)l4t_flash_ctxt.image_size_sct; - if (pct != prevPct) - { - lv_bar_set_value(bar, pct); - s_printf(txt_buf, " #DDDDDD "SYMBOL_DOT"# %d%%", pct); - lv_label_set_text(label_pct, txt_buf); - manual_system_maintenance(true); - prevPct = pct; - } - - lba_curr += num; - total_size_sct -= num; - bytesWritten += num * NX_EMMC_BLOCKSIZE; } - lv_bar_set_value(bar, 100); - lv_label_set_text(label_pct, " "SYMBOL_DOT" 100%"); - manual_system_maintenance(true); - // Restore operation ended successfully. - f_close(&fp); - free(clmt); + // Update completion percentage. + pct = (u64)((u64)lba_curr * 100u) / (u64)l4t_flash_ctxt.image_size_sct; + if (pct != prevPct) + { + lv_bar_set_value(bar, pct); + s_printf(txt_buf, " #DDDDDD "SYMBOL_DOT"# %d%%", pct); + lv_label_set_text(label_pct, txt_buf); + manual_system_maintenance(true); + prevPct = pct; + } - succeeded = true; + lba_curr += num; + total_size_sct -= num; + bytesWritten += num * EMMC_BLOCKSIZE; + } + lv_bar_set_value(bar, 100); + lv_label_set_text(label_pct, " "SYMBOL_DOT" 100%"); + manual_system_maintenance(true); + + // Restore operation ended successfully. + f_close(&fp); + free(clmt); + + succeeded = true; exit: - free(path); - free(txt_buf); + free(path); + free(txt_buf); - if (!succeeded) - lv_mbox_add_btns(mbox, mbox_btn_map, mbox_action); - else - lv_mbox_add_btns(mbox, mbox_btn_map2, _action_delete_linux_installer_files); - lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); + if (!succeeded) + lv_mbox_add_btns(mbox, mbox_btn_map, mbox_action); + else + lv_mbox_add_btns(mbox, mbox_btn_map2, _action_delete_linux_installer_files); + lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); - sd_unmount(); - } + sd_unmount(); return LV_RES_INV; } @@ -739,7 +768,7 @@ exit: static u32 _get_available_l4t_partition() { mbr_t mbr = { 0 }; - gpt_t *gpt = calloc(1, sizeof(gpt_t)); + gpt_t *gpt = zalloc(sizeof(gpt_t)); memset(&l4t_flash_ctxt, 0, sizeof(l4t_flasher_ctxt_t)); @@ -784,9 +813,9 @@ static u32 _get_available_l4t_partition() return size_sct; } -static bool _get_available_android_partition() +static int _get_available_android_partition() { - gpt_t *gpt = calloc(1, sizeof(gpt_t)); + gpt_t *gpt = zalloc(sizeof(gpt_t)); // Read main GPT. sdmmc_storage_read(&sd_storage, 1, sizeof(gpt_t) >> 9, gpt); @@ -798,11 +827,17 @@ static bool _get_available_android_partition() // Find kernel partition. for (u32 i = 0; i < gpt->header.num_part_ents; i++) { - if (gpt->entries[i].lba_start && !memcmp(gpt->entries[i].name, (char[]) { 'L', 0, 'N', 0, 'X', 0 }, 6)) + if (gpt->entries[i].lba_start) { - free(gpt); + int found = !memcmp(gpt->entries[i].name, (char[]) { 'b', 0, 'o', 0, 'o', 0, 't', 0 }, 8) ? 2 : 0; + found |= !memcmp(gpt->entries[i].name, (char[]) { 'L', 0, 'N', 0, 'X', 0 }, 6) ? 1 : 0; - return true; + if (found) + { + free(gpt); + + return found; + } } if (i > 126) @@ -824,7 +859,7 @@ static lv_res_t _action_check_flash_linux(lv_obj_t *btn) lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char *mbox_btn_map[] = { "\211", "\222OK", "\211", "" }; + static const char *mbox_btn_map[] = { "\251", "\222OK", "\251", "" }; static const char *mbox_btn_map2[] = { "\222Continue", "\222Cancel", "" }; lv_obj_t *mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); @@ -843,6 +878,7 @@ static lv_res_t _action_check_flash_linux(lv_obj_t *btn) sd_mount(); + // Check if L4T image exists. strcpy(path, "switchroot/install/l4t.00"); if (f_stat(path, NULL)) { @@ -850,9 +886,9 @@ static lv_res_t _action_check_flash_linux(lv_obj_t *btn) goto error; } + // Find an applicable partition for L4T. u32 size_sct = _get_available_l4t_partition(); - - if (!l4t_flash_ctxt.offset_sct || !size_sct || size_sct < 0x800000) + if (!l4t_flash_ctxt.offset_sct || size_sct < 0x800000) { lv_label_set_text(lbl_status, "#FFDD00 Error:# No partition found!"); goto error; @@ -860,6 +896,8 @@ static lv_res_t _action_check_flash_linux(lv_obj_t *btn) u32 idx = 0; path[23] = 0; + + // Validate L4T images and consolidate their info. while (true) { if (idx < 10) @@ -871,46 +909,46 @@ static lv_res_t _action_check_flash_linux(lv_obj_t *btn) itoa(idx, &path[23], 10); // Check for alignment. - if (!f_stat(path, &fno)) - { - if ((u64)fno.fsize % 0x400000) - { - // Check if last part. - idx++; - if (idx < 10) - { - path[23] = '0'; - itoa(idx, &path[23 + 1], 10); - } - else - itoa(idx, &path[23], 10); - - // If not the last part, unaligned size is not permitted. - if (!f_stat(path, NULL)) // NULL: Don't override current part fs info. - { - lv_label_set_text(lbl_status, "#FFDD00 Error:# The image is not aligned to 4 MiB!"); - goto error; - } - - // Last part. Align size to LBA (512 bytes). - fno.fsize = ALIGN((u64)fno.fsize, 512); - idx--; - } - l4t_flash_ctxt.image_size_sct += (u64)fno.fsize >> 9; - } - else + if (f_stat(path, &fno)) break; + // Check if current part is unaligned. + if ((u64)fno.fsize % SZ_4M) + { + // Get next part filename. + idx++; + if (idx < 10) + { + path[23] = '0'; + itoa(idx, &path[23 + 1], 10); + } + else + itoa(idx, &path[23], 10); + + // If it exists, unaligned size for current part is not permitted. + if (!f_stat(path, NULL)) // NULL: Don't override current part fs info. + { + lv_label_set_text(lbl_status, "#FFDD00 Error:# The image is not aligned to 4 MiB!"); + goto error; + } + + // Last part. Align size to LBA (SD_BLOCKSIZE). + fno.fsize = ALIGN((u64)fno.fsize, SD_BLOCKSIZE); + idx--; + } + l4t_flash_ctxt.image_size_sct += (u64)fno.fsize >> 9; + idx++; } + // Check if image size is bigger than the partition available. if (l4t_flash_ctxt.image_size_sct > size_sct) { lv_label_set_text(lbl_status, "#FFDD00 Error:# The image is bigger than the partition!"); goto error; } - char *txt_buf = malloc(0x1000); + char *txt_buf = malloc(SZ_4K); s_printf(txt_buf, "#C7EA46 Status:# Found installation files and partition.\n" "#00DDFF Offset:# %08x, #00DDFF Size:# %X, #00DDFF Image size:# %d MiB\n" @@ -931,7 +969,7 @@ exit: return LV_RES_OK; } -static lv_res_t _action_reboot_twrp(lv_obj_t * btns, const char * txt) +static lv_res_t _action_reboot_recovery(lv_obj_t * btns, const char * txt) { int btn_idx = lv_btnm_get_pressed(btns); @@ -940,18 +978,22 @@ static lv_res_t _action_reboot_twrp(lv_obj_t * btns, const char * txt) if (!btn_idx) { + // Set custom reboot type to Android Recovery. PMC(APBDEV_PMC_SCRATCH0) |= PMC_SCRATCH0_MODE_RECOVERY; + // Enable hekate boot configuration. b_cfg->boot_cfg = BOOT_CFG_FROM_ID | BOOT_CFG_AUTOBOOT_EN; + // Set id to Android. strcpy((char *)b_cfg->id, "SWANDR"); void (*main_ptr)() = (void *)nyx_str->hekate; + // Deinit hardware. sd_end(); + hw_deinit(false, 0); - hw_reinit_workaround(false, 0); - + // Chainload to hekate main. (*main_ptr)(); } @@ -961,240 +1003,269 @@ static lv_res_t _action_reboot_twrp(lv_obj_t * btns, const char * txt) static lv_res_t _action_flash_android_data(lv_obj_t * btns, const char * txt) { int btn_idx = lv_btnm_get_pressed(btns); + bool boot_recovery = false; // Delete parent mbox. mbox_action(btns, txt); + if (btn_idx) + return LV_RES_INV; + // Flash Android components. - if (!btn_idx) + char path[128]; + gpt_t *gpt = zalloc(sizeof(gpt_t)); + char *txt_buf = malloc(SZ_4K); + + lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL); + lv_obj_set_style(dark_bg, &mbox_darken); + lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); + + static const char *mbox_btn_map[] = { "\251", "\222OK", "\251", "" }; + static const char *mbox_btn_map2[] = { "\222Continue", "\222No", "" }; + lv_obj_t *mbox = lv_mbox_create(dark_bg, NULL); + lv_mbox_set_recolor_text(mbox, true); + lv_obj_set_width(mbox, LV_HOR_RES / 9 * 6); + + lv_mbox_set_text(mbox, "#FF8000 Android Flasher#"); + + lv_obj_t *lbl_status = lv_label_create(mbox, NULL); + lv_label_set_recolor(lbl_status, true); + lv_label_set_text(lbl_status, "#C7EA46 Status:# Searching for files and partitions..."); + + lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); + lv_obj_set_top(mbox, true); + + manual_system_maintenance(true); + + sd_mount(); + + // Read main GPT. + sdmmc_storage_read(&sd_storage, 1, sizeof(gpt_t) >> 9, gpt); + + // Validate GPT header. + if (memcmp(&gpt->header.signature, "EFI PART", 8) || gpt->header.num_part_ents > 128) { - char path[128]; - gpt_t *gpt = calloc(1, sizeof(gpt_t)); - char *txt_buf = malloc(0x1000); + lv_label_set_text(lbl_status, "#FFDD00 Error:# No Android GPT was found!"); + goto error; + } - lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL); - lv_obj_set_style(dark_bg, &mbox_darken); - lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); + u32 offset_sct = 0; + u32 size_sct = 0; - static const char *mbox_btn_map[] = { "\211", "\222OK", "\211", "" }; - static const char *mbox_btn_map2[] = { "\222Continue", "\222No", "" }; - lv_obj_t *mbox = lv_mbox_create(dark_bg, NULL); - lv_mbox_set_recolor_text(mbox, true); - lv_obj_set_width(mbox, LV_HOR_RES / 9 * 6); + // Check if Kernel image should be flashed. + strcpy(path, "switchroot/install/boot.img"); + if (f_stat(path, NULL)) + { + s_printf(txt_buf, "#FF8000 Warning:# Kernel image not found!\n"); + goto boot_img_not_found; + } - lv_mbox_set_text(mbox, "#FF8000 Android Flasher#"); - - lv_obj_t *lbl_status = lv_label_create(mbox, NULL); - lv_label_set_recolor(lbl_status, true); - lv_label_set_text(lbl_status, "#C7EA46 Status:# Searching for files and partitions..."); - - lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); - lv_obj_set_top(mbox, true); - - manual_system_maintenance(true); - - sd_mount(); - - // Read main GPT. - sdmmc_storage_read(&sd_storage, 1, sizeof(gpt_t) >> 9, gpt); - - bool boot_twrp = false; - if (memcmp(&gpt->header.signature, "EFI PART", 8) || gpt->header.num_part_ents > 128) + // Find Kernel partition. + for (u32 i = 0; i < gpt->header.num_part_ents; i++) + { + if (!memcmp(gpt->entries[i].name, (char[]) { 'L', 0, 'N', 0, 'X', 0 }, 6) || !memcmp(gpt->entries[i].name, (char[]) { 'b', 0, 'o', 0, 'o', 0, 't', 0 }, 8)) { - lv_label_set_text(lbl_status, "#FFDD00 Error:# No Android GPT was found!"); - goto error; + offset_sct = gpt->entries[i].lba_start; + size_sct = (gpt->entries[i].lba_end + 1) - gpt->entries[i].lba_start; + break; } - strcpy(path, "switchroot/install/boot.img"); - if (!f_stat(path, NULL)) + if (i > 126) + break; + } + + // Flash Kernel. + if (offset_sct && size_sct) + { + u32 file_size = 0; + u8 *buf = sd_file_read(path, &file_size); + + if (file_size % 0x200) { - u32 offset_sct = 0; - u32 size_sct = 0; - for (u32 i = 0; i < gpt->header.num_part_ents; i++) - { - if (!memcmp(gpt->entries[i].name, (char[]) { 'L', 0, 'N', 0, 'X', 0 }, 6)) - { - offset_sct = gpt->entries[i].lba_start; - size_sct = (gpt->entries[i].lba_end + 1) - gpt->entries[i].lba_start; - break; - } - - if (i > 126) - break; - } - - if (offset_sct && size_sct) - { - u32 file_size = 0; - u8 *buf = sd_file_read(path, &file_size); - - if (file_size % 0x200) - { - file_size = ALIGN(file_size, 0x200); - u8 *buf_tmp = calloc(file_size, 1); - memcpy(buf_tmp, buf, file_size); - free(buf); - buf = buf_tmp; - } - - if ((file_size >> 9) > size_sct) - s_printf(txt_buf, "#FF8000 Warning:# Kernel image too big!\n"); - else - { - sdmmc_storage_write(&sd_storage, offset_sct, file_size >> 9, buf); - - s_printf(txt_buf, "#C7EA46 Success:# Kernel image flashed!\n"); - f_unlink(path); - } - - free(buf); - } - else - s_printf(txt_buf, "#FF8000 Warning:# Kernel partition not found!\n"); + file_size = ALIGN(file_size, 0x200); + u8 *buf_tmp = zalloc(file_size); + memcpy(buf_tmp, buf, file_size); + free(buf); + buf = buf_tmp; } + + if ((file_size >> 9) > size_sct) + s_printf(txt_buf, "#FF8000 Warning:# Kernel image too big!\n"); else - s_printf(txt_buf, "#FF8000 Warning:# Kernel image not found!\n"); + { + sdmmc_storage_write(&sd_storage, offset_sct, file_size >> 9, buf); - lv_label_set_text(lbl_status, txt_buf); - manual_system_maintenance(true); + s_printf(txt_buf, "#C7EA46 Success:# Kernel image flashed!\n"); + f_unlink(path); + } + free(buf); + } + else + s_printf(txt_buf, "#FF8000 Warning:# Kernel partition not found!\n"); + +boot_img_not_found: + lv_label_set_text(lbl_status, txt_buf); + manual_system_maintenance(true); + + // Check if Recovery should be flashed. + strcpy(path, "switchroot/install/recovery.img"); + if (f_stat(path, NULL)) + { + // Not found, try twrp.img instead. strcpy(path, "switchroot/install/twrp.img"); - if (!f_stat(path, NULL)) + if (f_stat(path, NULL)) { - u32 offset_sct = 0; - u32 size_sct = 0; - for (u32 i = 0; i < gpt->header.num_part_ents; i++) - { - if (!memcmp(gpt->entries[i].name, (char[]) { 'S', 0, 'O', 0, 'S', 0 }, 6)) - { - offset_sct = gpt->entries[i].lba_start; - size_sct = (gpt->entries[i].lba_end + 1) - gpt->entries[i].lba_start; - break; - } - - if (i > 126) - break; - } - - if (offset_sct && size_sct) - { - u32 file_size = 0; - u8 *buf = sd_file_read(path, &file_size); - - if (file_size % 0x200) - { - file_size = ALIGN(file_size, 0x200); - u8 *buf_tmp = calloc(file_size, 1); - memcpy(buf_tmp, buf, file_size); - free(buf); - buf = buf_tmp; - } - - if ((file_size >> 9) > size_sct) - strcat(txt_buf, "#FF8000 Warning:# TWRP image too big!\n"); - else - { - sdmmc_storage_write(&sd_storage, offset_sct, file_size >> 9, buf); - strcat(txt_buf, "#C7EA46 Success:# TWRP image flashed!\n"); - f_unlink(path); - } - - free(buf); - } - else - strcat(txt_buf, "#FF8000 Warning:# TWRP partition not found!\n"); + strcat(txt_buf, "#FF8000 Warning:# Recovery image not found!\n"); + goto recovery_not_found; } + } + + offset_sct = 0; + size_sct = 0; + + // Find Recovery partition. + for (u32 i = 0; i < gpt->header.num_part_ents; i++) + { + if (!memcmp(gpt->entries[i].name, (char[]) { 'S', 0, 'O', 0, 'S', 0 }, 6) || !memcmp(gpt->entries[i].name, (char[]) { 'r', 0, 'e', 0, 'c', 0, 'o', 0, 'v', 0, 'e', 0, 'r', 0, 'y', 0 }, 16)) + { + offset_sct = gpt->entries[i].lba_start; + size_sct = (gpt->entries[i].lba_end + 1) - gpt->entries[i].lba_start; + break; + } + + if (i > 126) + break; + } + + // Flash Recovery. + if (offset_sct && size_sct) + { + u32 file_size = 0; + u8 *buf = sd_file_read(path, &file_size); + + if (file_size % 0x200) + { + file_size = ALIGN(file_size, 0x200); + u8 *buf_tmp = zalloc(file_size); + memcpy(buf_tmp, buf, file_size); + free(buf); + buf = buf_tmp; + } + + if ((file_size >> 9) > size_sct) + strcat(txt_buf, "#FF8000 Warning:# Recovery image too big!\n"); else - strcat(txt_buf, "#FF8000 Warning:# TWRP image not found!\n"); + { + sdmmc_storage_write(&sd_storage, offset_sct, file_size >> 9, buf); + strcat(txt_buf, "#C7EA46 Success:# Recovery image flashed!\n"); + f_unlink(path); + } - lv_label_set_text(lbl_status, txt_buf); - manual_system_maintenance(true); + free(buf); + } + else + strcat(txt_buf, "#FF8000 Warning:# Recovery partition not found!\n"); +recovery_not_found: + lv_label_set_text(lbl_status, txt_buf); + manual_system_maintenance(true); + + // Check if Device Tree should be flashed. + strcpy(path, "switchroot/install/nx-plat.dtimg"); + if (f_stat(path, NULL)) + { strcpy(path, "switchroot/install/tegra210-icosa.dtb"); - if (!f_stat(path, NULL)) + if (f_stat(path, NULL)) { - u32 offset_sct = 0; - u32 size_sct = 0; - for (u32 i = 0; i < gpt->header.num_part_ents; i++) - { - if (!memcmp(gpt->entries[i].name, (char[]) { 'D', 0, 'T', 0, 'B', 0 }, 6)) - { - offset_sct = gpt->entries[i].lba_start; - size_sct = (gpt->entries[i].lba_end + 1) - gpt->entries[i].lba_start; - break; - } - - if (i > 126) - break; - } - - if (offset_sct && size_sct) - { - u32 file_size = 0; - u8 *buf = sd_file_read(path, &file_size); - - if (file_size % 0x200) - { - file_size = ALIGN(file_size, 0x200); - u8 *buf_tmp = calloc(file_size, 1); - memcpy(buf_tmp, buf, file_size); - free(buf); - buf = buf_tmp; - } - - if ((file_size >> 9) > size_sct) - strcat(txt_buf, "#FF8000 Warning:# DTB image too big!"); - else - { - sdmmc_storage_write(&sd_storage, offset_sct, file_size >> 9, buf); - strcat(txt_buf, "#C7EA46 Success:# DTB image flashed!"); - f_unlink(path); - } - - free(buf); - } - else - strcat(txt_buf, "#FF8000 Warning:# DTB partition not found!"); - } - else strcat(txt_buf, "#FF8000 Warning:# DTB image not found!"); - - lv_label_set_text(lbl_status, txt_buf); - - // Check if TWRP is flashed unconditionally. - for (u32 i = 0; i < gpt->header.num_part_ents; i++) - { - if (!memcmp(gpt->entries[i].name, (char[]) { 'S', 0, 'O', 0, 'S', 0 }, 6)) - { - u8 *buf = malloc(512); - sdmmc_storage_read(&sd_storage, gpt->entries[i].lba_start, 1, buf); - if (!memcmp(buf, "ANDROID", 7)) - boot_twrp = true; - free(buf); - break; - } - - if (i > 126) - break; + goto dtb_not_found; } + } + + offset_sct = 0; + size_sct = 0; + + // Find Device Tree partition. + for (u32 i = 0; i < gpt->header.num_part_ents; i++) + { + if (!memcmp(gpt->entries[i].name, (char[]) { 'D', 0, 'T', 0, 'B', 0 }, 6) || !memcmp(gpt->entries[i].name, (char[]) { 'd', 0, 't', 0, 'b', 0 }, 6)) + { + offset_sct = gpt->entries[i].lba_start; + size_sct = (gpt->entries[i].lba_end + 1) - gpt->entries[i].lba_start; + break; + } + + if (i > 126) + break; + } + + // Flash Device Tree. + if (offset_sct && size_sct) + { + u32 file_size = 0; + u8 *buf = sd_file_read(path, &file_size); + + if (file_size % 0x200) + { + file_size = ALIGN(file_size, 0x200); + u8 *buf_tmp = zalloc(file_size); + memcpy(buf_tmp, buf, file_size); + free(buf); + buf = buf_tmp; + } + + if ((file_size >> 9) > size_sct) + strcat(txt_buf, "#FF8000 Warning:# DTB image too big!"); + else + { + sdmmc_storage_write(&sd_storage, offset_sct, file_size >> 9, buf); + strcat(txt_buf, "#C7EA46 Success:# DTB image flashed!"); + f_unlink(path); + } + + free(buf); + } + else + strcat(txt_buf, "#FF8000 Warning:# DTB partition not found!"); + +dtb_not_found: + lv_label_set_text(lbl_status, txt_buf); + + // Check if Recovery is flashed unconditionally. + for (u32 i = 0; i < gpt->header.num_part_ents; i++) + { + if (!memcmp(gpt->entries[i].name, (char[]) { 'S', 0, 'O', 0, 'S', 0 }, 6) || !memcmp(gpt->entries[i].name, (char[]) { 'r', 0, 'e', 0, 'c', 0, 'o', 0, 'v', 0, 'e', 0, 'r', 0, 'y', 0 }, 16)) + { + u8 *buf = malloc(SD_BLOCKSIZE); + sdmmc_storage_read(&sd_storage, gpt->entries[i].lba_start, 1, buf); + if (!memcmp(buf, "ANDROID", 7)) + boot_recovery = true; + free(buf); + break; + } + + if (i > 126) + break; + } error: - if (boot_twrp) - { - strcat(txt_buf,"\n\nDo you want to reboot into TWRP\nto finish Android installation?"); - lv_label_set_text(lbl_status, txt_buf); - lv_mbox_add_btns(mbox, mbox_btn_map2, _action_reboot_twrp); - } - else - lv_mbox_add_btns(mbox, mbox_btn_map, mbox_action); - - lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); - - free(txt_buf); - free(gpt); - - sd_unmount(); + if (boot_recovery) + { + // If a Recovery partition was found, ask user if rebooting into it is wanted. + strcat(txt_buf,"\n\nDo you want to reboot into Recovery\nto finish Android installation?"); + lv_label_set_text(lbl_status, txt_buf); + lv_mbox_add_btns(mbox, mbox_btn_map2, _action_reboot_recovery); } + else + lv_mbox_add_btns(mbox, mbox_btn_map, mbox_action); + + lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); + + free(txt_buf); + free(gpt); + + sd_unmount(); return LV_RES_INV; } @@ -1215,7 +1286,8 @@ static lv_res_t _action_flash_android(lv_obj_t *btn) lv_obj_t *lbl_status = lv_label_create(mbox, NULL); lv_label_set_recolor(lbl_status, true); lv_label_set_text(lbl_status, - "This will flash #C7EA46 Kernel#, #C7EA46 DTB# and #C7EA46 TWRP# if found.\n" + "This will flash #C7EA46 Kernel#, #C7EA46 DTB# and #C7EA46 Recovery# if found.\n" + "These will be deleted after a successful flash.\n" "Do you want to continue?"); lv_mbox_add_btns(mbox, mbox_btn_map, _action_flash_android_data); @@ -1293,13 +1365,65 @@ static lv_res_t _action_part_manager_flash_options2(lv_obj_t *btns, const char * return LV_RES_OK; } +static int _backup_and_restore_files(bool backup, lv_obj_t **labels) +{ + const char *src_drv = backup ? "sd:" : "ram:"; + const char *dst_drv = backup ? "ram:" : "sd:"; + + int res = 0; + u32 total_size = 0; + u32 total_files = 0; + char *path = malloc(0x1000); + path[0] = 0; // Set default as root folder. + + // Check if Mariko Warmboot Storage exists in source drive. + f_chdrive(src_drv); + bool backup_mws = !part_info.backup_possible && !f_stat("warmboot_mariko", NULL); + bool backup_pld = !part_info.backup_possible && !f_stat("payload.bin", NULL); + + if (!part_info.backup_possible) + { + // Change path to hekate/Nyx. + strcpy(path, "bootloader"); + + // Create hekate/Nyx/MWS folders in destination drive. + f_chdrive(dst_drv); + f_mkdir("bootloader"); + if (backup_mws) + f_mkdir("warmboot_mariko"); + } + + // Copy all or hekate/Nyx files. + res = _stat_and_copy_files(src_drv, dst_drv, path, &total_files, &total_size, labels); + + // If incomplete backup mode, copy MWS and payload.bin also. + if (!res) + { + if (backup_mws) + { + strcpy(path, "warmboot_mariko"); + res = _stat_and_copy_files(src_drv, dst_drv, path, &total_files, &total_size, labels); + } + + if (!res && backup_pld) + { + strcpy(path, "payload.bin"); + res = _copy_file(src_drv, dst_drv, path); + } + } + + free(path); + + return res; +} + static lv_res_t _create_mbox_start_partitioning(lv_obj_t *btn) { lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL); lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char *mbox_btn_map[] = { "\211", "\222OK", "\211", "" }; + static const char *mbox_btn_map[] = { "\251", "\222OK", "\251", "" }; static const char *mbox_btn_map1[] = { "\222SD UMS", "\222Flash Linux", "\222Flash Android", "\221OK", "" }; static const char *mbox_btn_map2[] = { "\222SD UMS", "\222Flash Linux", "\221OK", "" }; static const char *mbox_btn_map3[] = { "\222SD UMS", "\222Flash Android", "\221OK", "" }; @@ -1313,36 +1437,35 @@ static lv_res_t _create_mbox_start_partitioning(lv_obj_t *btn) bool buttons_set = false; - if (!part_info.backup_possible) + // Use safety wait if backup is not possible. + char *txt_buf = malloc(SZ_4K); + strcpy(txt_buf, "#FF8000 Partition Manager#\n\nSafety wait ends in "); + lv_mbox_set_text(mbox, txt_buf); + + u32 seconds = 5; + u32 text_idx = strlen(txt_buf); + while (seconds) { - char *txt_buf = malloc(0x1000); - strcpy(txt_buf, "#FF8000 Partition Manager#\n\nSafety wait ends in "); + s_printf(txt_buf + text_idx, "%d seconds...", seconds); lv_mbox_set_text(mbox, txt_buf); - - u32 seconds = 5; - u32 text_idx = strlen(txt_buf); - while (seconds) - { - s_printf(txt_buf + text_idx, "%d seconds...", seconds); - lv_mbox_set_text(mbox, txt_buf); - manual_system_maintenance(true); - msleep(1000); - seconds--; - } - - lv_mbox_set_text(mbox, - "#FF8000 Partition Manager#\n\n" - "#FFDD00 Warning: Do you really want to continue?!#\n\n" - "Press #FF8000 POWER# to Continue.\nPress #FF8000 VOL# to abort."); - lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); manual_system_maintenance(true); - - free(txt_buf); - - if (!(btn_wait() & BTN_POWER)) - goto exit; + msleep(1000); + seconds--; } + lv_mbox_set_text(mbox, + "#FF8000 Partition Manager#\n\n" + "#FFDD00 Warning: Do you really want to continue?!#\n\n" + "Press #FF8000 POWER# to Continue.\nPress #FF8000 VOL# to abort."); + lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); + manual_system_maintenance(true); + + free(txt_buf); + + if (!(btn_wait() & BTN_POWER)) + goto exit; + + // Start partitioning. lv_mbox_set_text(mbox, "#FF8000 Partition Manager#"); lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); manual_system_maintenance(true); @@ -1352,6 +1475,7 @@ static lv_res_t _create_mbox_start_partitioning(lv_obj_t *btn) lv_obj_t *lbl_paths[2]; + // Create backup/restore paths labels. lbl_paths[0] = lv_label_create(mbox, NULL); lv_label_set_text(lbl_paths[0], "/"); lv_label_set_long_mode(lbl_paths[0], LV_LABEL_LONG_DOT); @@ -1368,9 +1492,6 @@ static lv_res_t _create_mbox_start_partitioning(lv_obj_t *btn) sd_mount(); FATFS ram_fs; - char *path = malloc(1024); - u32 total_files = 0; - u32 total_size = 0; // Read current MBR. sdmmc_storage_read(&sd_storage, 0, 1, &part_info.mbr_old); @@ -1379,35 +1500,27 @@ static lv_res_t _create_mbox_start_partitioning(lv_obj_t *btn) lv_label_set_text(lbl_paths[0], "Please wait..."); lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); manual_system_maintenance(true); + + // Initialize RAM disk. if (ram_disk_init(&ram_fs, RAM_DISK_SZ)) { lv_label_set_text(lbl_status, "#FFDD00 Error:# Failed to initialize Ramdisk!"); goto error; } - if (!part_info.backup_possible) - { - strcpy(path, "bootloader"); - f_chdrive("ram:"); - f_mkdir(path); - } - else - path[0] = 0; - lv_label_set_text(lbl_status, "#00DDFF Status:# Backing up files..."); manual_system_maintenance(true); - if (_backup_and_restore_files(path, &total_files, &total_size, "ram:", "sd:", lbl_paths)) + + // Do full or hekate/Nyx backup. + if (_backup_and_restore_files(true, lbl_paths)) { - lv_label_set_text(lbl_status, "#FFDD00 Error:# Failed to back up files!"); + if (part_info.backup_possible) + lv_label_set_text(lbl_status, "#FFDD00 Error:# Failed to back up files!"); + else + lv_label_set_text(lbl_status, "#FFDD00 Error:# Failed to back up files!\nBootloader folder exceeds 1GB or corrupt!"); + goto error; } - total_files = 0; - total_size = 0; - - if (!part_info.backup_possible) - strcpy(path, "bootloader"); - else - path[0] = 0; f_mount(NULL, "sd:", 1); // Unmount SD card. @@ -1418,87 +1531,78 @@ static lv_res_t _create_mbox_start_partitioning(lv_obj_t *btn) // Set reserved size. u32 part_rsvd_size = (part_info.emu_size << 11) + (part_info.l4t_size << 11) + (part_info.and_size << 11); - part_rsvd_size += part_info.alignment; + part_rsvd_size += part_rsvd_size ? part_info.alignment : 0; // Do not reserve alignment space if no extra partitions. disk_set_info(DRIVE_SD, SET_SECTOR_COUNT, &part_rsvd_size); - u8 *buf = malloc(0x400000); + u8 *buf = malloc(SZ_4M); + // Set cluster size to 64KB and try to format. u32 cluster_size = 65536; - u32 mkfs_error = f_mkfs("sd:", FM_FAT32, cluster_size, buf, 0x400000); + u32 mkfs_error = f_mkfs("sd:", FM_FAT32, cluster_size, buf, SZ_4M); + + if (!mkfs_error) + goto mkfs_no_error; + + // Retry formatting by halving cluster size, until one succeeds. + while (cluster_size > 4096) + { + cluster_size /= 2; + mkfs_error = f_mkfs("sd:", FM_FAT32, cluster_size, buf, SZ_4M); + + if (!mkfs_error) + break; + } + if (mkfs_error) { - // Retry by halving cluster size. - while (cluster_size > 4096) + // Failed to format. + s_printf((char *)buf, "#FFDD00 Error:# Failed to format disk (%d)!\n\n" + "Remove the SD card and check that is OK.\nIf not, format it, reinsert it and\npress #FF8000 POWER#!", mkfs_error); + + lv_label_set_text(lbl_status, (char *)buf); + lv_label_set_text(lbl_paths[0], " "); + manual_system_maintenance(true); + + sd_end(); + + while (!(btn_wait() & BTN_POWER)); + + sd_mount(); + + lv_label_set_text(lbl_status, "#00DDFF Status:# Restoring files..."); + manual_system_maintenance(true); + + // Restore backed up files back to SD. + if (_backup_and_restore_files(false, lbl_paths)) { - cluster_size /= 2; - mkfs_error = f_mkfs("sd:", FM_FAT32, cluster_size, buf, 0x400000); - - if (!mkfs_error) - break; - } - - if (mkfs_error) - { - // Failed to format. - s_printf((char *)buf, "#FFDD00 Error:# Failed to format disk (%d)!\n\n" - "Remove the SD card and check that is OK.\nIf not, format it, reinsert it and\npress #FF8000 POWER#!", mkfs_error); - - lv_label_set_text(lbl_status, (char *)buf); - lv_label_set_text(lbl_paths[0], " "); - manual_system_maintenance(true); - - sd_end(); - - while (!(btn_wait() & BTN_POWER)); - - sd_mount(); - - if (!part_info.backup_possible) - { - f_chdrive("sd:"); - f_mkdir(path); - } - - lv_label_set_text(lbl_status, "#00DDFF Status:# Restoring files..."); - manual_system_maintenance(true); - if (_backup_and_restore_files(path, &total_files, &total_size, "sd:", "ram:", NULL)) + // Failed to restore files. Try again once more. + if (_backup_and_restore_files(false, lbl_paths)) { lv_label_set_text(lbl_status, "#FFDD00 Error:# Failed to restore files!"); free(buf); goto error; } - lv_label_set_text(lbl_status, "#00DDFF Status:# Restored files but the operation failed!"); - f_mount(NULL, "ram:", 1); // Unmount ramdisk. - free(buf); - goto error; } + + lv_label_set_text(lbl_status, "#00DDFF Status:# Restored files but the operation failed!"); + f_mount(NULL, "ram:", 1); // Unmount ramdisk. + free(buf); + goto error; } + +mkfs_no_error: free(buf); + // Remount sd card as it was unmounted from formatting it. f_mount(&sd_fs, "sd:", 1); // Mount SD card. - if (!part_info.backup_possible) - { - f_chdrive("sd:"); - f_mkdir(path); - } - lv_label_set_text(lbl_status, "#00DDFF Status:# Restoring files..."); manual_system_maintenance(true); - if (_backup_and_restore_files(path, &total_files, &total_size, "sd:", "ram:", lbl_paths)) + + // Restore backed up files back to SD. + if (_backup_and_restore_files(false, lbl_paths)) { - total_files = 0; - total_size = 0; - - if (!part_info.backup_possible) - { - strcpy(path, "bootloader"); - f_chdrive("sd:"); - f_mkdir(path); - } - else - path[0] = 0; - - if (_backup_and_restore_files(path, &total_files, &total_size, "sd:", "ram:", NULL)) + // Failed to restore files. Try again once more. + if (_backup_and_restore_files(false, lbl_paths)) { lv_label_set_text(lbl_status, "#FFDD00 Error:# Failed to restore files!"); goto error; @@ -1515,6 +1619,8 @@ static lv_res_t _create_mbox_start_partitioning(lv_obj_t *btn) lv_label_set_text(lbl_paths[0], "Please wait..."); lv_label_set_text(lbl_paths[1], " "); manual_system_maintenance(true); + + // Prepare MBR and GPT header and partition entries and flash them. _prepare_and_flash_mbr_gpt(); // Enable/Disable buttons depending on partition layout. @@ -1545,6 +1651,7 @@ static lv_res_t _create_mbox_start_partitioning(lv_obj_t *btn) lv_label_set_text(lbl_status, "#00DDFF Status:# Done!"); manual_system_maintenance(true); + // Set buttons depending on what user chose to create. if (part_info.l4t_size && part_info.and_size) lv_mbox_add_btns(mbox, mbox_btn_map1, _action_part_manager_flash_options0); else if (part_info.l4t_size) @@ -1559,7 +1666,6 @@ static lv_res_t _create_mbox_start_partitioning(lv_obj_t *btn) error: f_chdrive("sd:"); - free(path); out: lv_obj_del(lbl_paths[0]); @@ -1614,7 +1720,7 @@ static lv_res_t _create_mbox_partitioning_option1(lv_obj_t *btns, const char *tx return LV_RES_OK; } -static lv_res_t _create_mbox_partitioning_next(lv_obj_t *btn) +static lv_res_t _create_mbox_partitioning_warn(lv_obj_t *btn) { lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL); lv_obj_set_style(dark_bg, &mbox_darken); @@ -1625,7 +1731,7 @@ static lv_res_t _create_mbox_partitioning_next(lv_obj_t *btn) lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); - char *txt_buf = malloc(0x1000); + char *txt_buf = malloc(SZ_4K); lv_obj_set_width(mbox, LV_HOR_RES / 9 * 6); lv_mbox_set_text(mbox, "#FF8000 Partition Manager#"); @@ -1661,41 +1767,99 @@ static lv_res_t _create_mbox_partitioning_next(lv_obj_t *btn) return LV_RES_OK; } +static lv_res_t _create_mbox_partitioning_android(lv_obj_t *btns, const char *txt) +{ + int btn_idx = lv_btnm_get_pressed(btns); + + mbox_action(btns, txt); + + part_info.and_dynamic = !btn_idx; + _create_mbox_partitioning_warn(NULL); + + return LV_RES_INV; +} + +static lv_res_t _create_mbox_partitioning_andr_part(lv_obj_t *btn) +{ + lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL); + lv_obj_set_style(dark_bg, &mbox_darken); + lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); + + static const char *mbox_btn_map[] = { "\222Dynamic", "\222Legacy", "" }; + lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); + lv_mbox_set_recolor_text(mbox, true); + + lv_obj_set_width(mbox, LV_HOR_RES / 10 * 5); + lv_mbox_set_text(mbox, "#FF8000 Android Partitioning#"); + + lv_obj_t *lbl_status = lv_label_create(mbox, NULL); + lv_label_set_recolor(lbl_status, true); + + lv_label_set_text(lbl_status, + "Please select a partition scheme:\n\n" + "#C7EA46 Dynamic:# Android 13+\n" + "#C7EA46 Legacy:# Android 10-11\n"); + + lv_mbox_add_btns(mbox, mbox_btn_map, _create_mbox_partitioning_android); + lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); + lv_obj_set_top(mbox, true); + + return LV_RES_OK; +} + +static lv_res_t _create_mbox_partitioning_next(lv_obj_t *btn) { + if (part_info.and_size) + return _create_mbox_partitioning_andr_part(NULL); + else + return _create_mbox_partitioning_warn(NULL); +} + static void _update_partition_bar() { lv_obj_t *h1 = lv_obj_get_parent(part_info.bar_hos); - u32 total_size = (part_info.total_sct - 0x8000) / 0x200000; + + // Set widths based on max bar width. + u32 total_size = (part_info.total_sct - AU_ALIGN_SECTORS) / SECTORS_PER_GB; u32 bar_hos_size = lv_obj_get_width(h1) * (part_info.hos_size >> 10) / total_size; u32 bar_emu_size = lv_obj_get_width(h1) * (part_info.emu_size >> 10) / total_size; u32 bar_l4t_size = lv_obj_get_width(h1) * (part_info.l4t_size >> 10) / total_size; u32 bar_and_size = lv_obj_get_width(h1) * (part_info.and_size >> 10) / total_size; + // Update bar widths. lv_obj_set_size(part_info.bar_hos, bar_hos_size, LV_DPI / 2); lv_obj_set_size(part_info.bar_emu, bar_emu_size, LV_DPI / 2); lv_obj_set_size(part_info.bar_l4t, bar_l4t_size, LV_DPI / 2); lv_obj_set_size(part_info.bar_and, bar_and_size, LV_DPI / 2); + // Re-align bars. lv_obj_align(part_info.bar_emu, part_info.bar_hos, LV_ALIGN_OUT_RIGHT_MID, 0, 0); lv_obj_align(part_info.bar_l4t, part_info.bar_emu, LV_ALIGN_OUT_RIGHT_MID, 0, 0); lv_obj_align(part_info.bar_and, part_info.bar_l4t, LV_ALIGN_OUT_RIGHT_MID, 0, 0); + // Set emuMMC blending separator sizes and realign. lv_obj_set_size(part_info.sep_emu, bar_emu_size ? 8 : 0, LV_DPI / 2); lv_obj_align(part_info.sep_emu, part_info.bar_hos, LV_ALIGN_OUT_RIGHT_MID, -4, 0); + // Set L4T blending separator sizes and realign. lv_obj_set_size(part_info.sep_l4t, bar_l4t_size ? 8 : 0, LV_DPI / 2); lv_obj_align(part_info.sep_l4t, part_info.bar_emu, LV_ALIGN_OUT_RIGHT_MID, -4, 0); + // Set Android blending separator sizes and realign. lv_obj_set_size(part_info.sep_and, bar_and_size ? 8 : 0, LV_DPI / 2); lv_obj_align(part_info.sep_and, part_info.bar_l4t, LV_ALIGN_OUT_RIGHT_MID, -4, 0); } static lv_res_t _action_slider_emu(lv_obj_t *slider) { + #define EMUMMC_32GB_FULL 29856 + #define EMUMMC_64GB_FULL (59664 + 1) // 1MB extra for backup GPT. + + static const u32 rsvd_mb = 4 + 4 + 16 + 8; // BOOT0 + BOOT1 + 16MB offset + 8MB alignment. u32 size; char lbl_text[64]; bool prev_emu_double = part_info.emu_double; int slide_val = lv_slider_get_value(slider); - const u32 rsvd_mb = 4 + 4 + 16 + 8; // BOOT0 + BOOT1 + 16MB offset + 8MB alignment. + u32 max_emmc_size = !part_info.emmc_is_64gb ? EMUMMC_32GB_FULL : EMUMMC_64GB_FULL; part_info.emu_double = false; @@ -1711,14 +1875,15 @@ static lv_res_t _action_slider_emu(lv_obj_t *slider) part_info.emu_double = true; } - // Handle special case. + // Handle special cases. 2nd value is for 64GB Aula. if (slide_val == 10) - size = 29856; + size = max_emmc_size; else if (slide_val == 20) - size = 59712; + size = 2 * max_emmc_size; + // Sanitize sizes based on new HOS size. s32 hos_size = (part_info.total_sct >> 11) - 16 - size - part_info.l4t_size - part_info.and_size; - if (hos_size > 2048) + if (hos_size > HOS_MIN_SIZE_MB) { part_info.emu_size = size; part_info.hos_size = hos_size; @@ -1742,9 +1907,9 @@ static lv_res_t _action_slider_emu(lv_obj_t *slider) { u32 emu_size = part_info.emu_size; - if (emu_size == 29856) + if (emu_size == max_emmc_size) emu_size = 10; - else if (emu_size == 59712) + else if (emu_size == 2 * max_emmc_size) emu_size = 20; else if (emu_size) { @@ -1781,7 +1946,8 @@ static lv_res_t _action_slider_l4t(lv_obj_t *slider) s32 hos_size = (part_info.total_sct >> 11) - 16 - part_info.emu_size - size - part_info.and_size; - if (hos_size > 2048) + // Sanitize sizes based on new HOS size. + if (hos_size > HOS_MIN_SIZE_MB) { if (size <= 8192) lv_slider_set_value(slider, size >> 10); @@ -1790,7 +1956,7 @@ static lv_res_t _action_slider_l4t(lv_obj_t *slider) { size = (part_info.total_sct >> 11) - 16 - part_info.emu_size - part_info.and_size - 2048; hos_size = (part_info.total_sct >> 11) - 16 - part_info.emu_size - part_info.and_size - size; - if (hos_size < 2048 || size < 8192) + if (hos_size < HOS_MIN_SIZE_MB || size < 8192) { lv_slider_set_value(slider, part_info.l4t_size >> 10); goto out; @@ -1823,10 +1989,11 @@ static lv_res_t _action_slider_and(lv_obj_t *slider) else if (user_size < 4096) user_size = 4096; - u32 and_size = user_size ? (user_size + 4096) : 0; // Add Android reserved partitions size. + u32 and_size = user_size ? (user_size + ANDROID_SYSTEM_SIZE_MB) : 0; s32 hos_size = (part_info.total_sct >> 11) - 16 - part_info.emu_size - part_info.l4t_size - and_size; - if (hos_size > 2048) + // Sanitize sizes based on new HOS size. + if (hos_size > HOS_MIN_SIZE_MB) { if (user_size <= 4096) lv_slider_set_value(slider, user_size >> 10); @@ -1835,12 +2002,12 @@ static lv_res_t _action_slider_and(lv_obj_t *slider) { and_size = (part_info.total_sct >> 11) - 16 - part_info.emu_size - part_info.l4t_size - 2048; hos_size = (part_info.total_sct >> 11) - 16 - part_info.emu_size - part_info.l4t_size - and_size; - if (hos_size < 2048 || and_size < 8192) + if (hos_size < HOS_MIN_SIZE_MB || and_size < 8192) { lv_slider_set_value(slider, part_info.and_size >> 10); goto out; } - user_size = and_size - 4096; + user_size = and_size - ANDROID_SYSTEM_SIZE_MB; lv_slider_set_value(slider, user_size >> 10); } @@ -1859,27 +2026,43 @@ out: return LV_RES_OK; } -static void create_mbox_check_files_total_size() +static lv_res_t _mbox_check_files_total_size_option(lv_obj_t *btns, const char *txt) +{ + // If "don't backup" button was pressed, disable backup/restore of files. + if (!lv_btnm_get_pressed(btns)) + part_info.backup_possible = false; + + mbox_action(btns, txt); + + return LV_RES_INV; +} + +static void _create_mbox_check_files_total_size() { static lv_style_t bar_hos_ind, bar_emu_ind, bar_l4t_ind, bar_and_ind; static lv_style_t sep_emu_bg, sep_l4t_bg, sep_and_bg; + // Set HOS bar style. lv_style_copy(&bar_hos_ind, lv_theme_get_current()->bar.indic); bar_hos_ind.body.main_color = LV_COLOR_HEX(0x96FF00); bar_hos_ind.body.grad_color = bar_hos_ind.body.main_color; + // Set emuMMC bar style. lv_style_copy(&bar_emu_ind, lv_theme_get_current()->bar.indic); bar_emu_ind.body.main_color = LV_COLOR_HEX(0xFF3C28); bar_emu_ind.body.grad_color = bar_emu_ind.body.main_color; + // Set L4T bar style. lv_style_copy(&bar_l4t_ind, lv_theme_get_current()->bar.indic); bar_l4t_ind.body.main_color = LV_COLOR_HEX(0x00DDFF); bar_l4t_ind.body.grad_color = bar_l4t_ind.body.main_color; + // Set GPT bar style. lv_style_copy(&bar_and_ind, lv_theme_get_current()->bar.indic); - bar_and_ind.body.main_color = LV_COLOR_HEX(0xFF8000); + bar_and_ind.body.main_color = LV_COLOR_HEX(0xC000FF); bar_and_ind.body.grad_color = bar_and_ind.body.main_color; + // Set separator styles. lv_style_copy(&sep_emu_bg, lv_theme_get_current()->cont); sep_emu_bg.body.main_color = LV_COLOR_HEX(0xFF3C28); sep_emu_bg.body.grad_color = sep_emu_bg.body.main_color; @@ -1888,16 +2071,17 @@ static void create_mbox_check_files_total_size() sep_l4t_bg.body.main_color = LV_COLOR_HEX(0x00DDFF); sep_l4t_bg.body.grad_color = sep_l4t_bg.body.main_color; lv_style_copy(&sep_and_bg, &sep_emu_bg); - sep_and_bg.body.main_color = LV_COLOR_HEX(0xFF8000); + sep_and_bg.body.main_color = LV_COLOR_HEX(0xC000FF); sep_and_bg.body.grad_color = sep_and_bg.body.main_color; - char *txt_buf = malloc(0x2000); + char *txt_buf = malloc(SZ_8K); lv_obj_t *dark_bg = lv_obj_create(lv_scr_act(), NULL); lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char *mbox_btn_map[] = { "\211", "\222OK", "\211", "" }; + static const char *mbox_btn_map[] = { "\251", "\222OK", "\251", "" }; + static const char *mbox_btn_map2[] = { "\222Don't Backup", "\222OK", "" }; lv_obj_t *mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); lv_obj_set_width(mbox, LV_HOR_RES / 9 * 6); @@ -1908,16 +2092,16 @@ static void create_mbox_check_files_total_size() lv_obj_set_top(mbox, true); manual_system_maintenance(true); - char *path = malloc(1024); + char *path = malloc(0x1000); u32 total_files = 0; u32 total_size = 0; path[0] = 0; // Check total size of files. - int res = _backup_and_restore_files(path, &total_files, &total_size, NULL, NULL, NULL); + int res = _stat_and_copy_files("sd:", NULL, path, &total_files, &total_size, NULL); // Not more than 1.0GB. - part_info.backup_possible = !res && !(total_size > (RAM_DISK_SZ - 0x1000000)); // 0x2400000 + part_info.backup_possible = !res && !(total_size > (RAM_DISK_SZ - SZ_16M)); if (part_info.backup_possible) { @@ -1930,7 +2114,7 @@ static void create_mbox_check_files_total_size() else { lv_mbox_set_text(mbox, - "#FFDD00 The SD Card cannot be backed up!#\n" + "#FFDD00 The SD Card cannot be backed up automatically!#\n" "#FFDD00 Any other partition will be also wiped!#\n\n" "You will be asked to back up your files later via UMS."); } @@ -1949,23 +2133,24 @@ static void create_mbox_check_files_total_size() mbr_t mbr = { 0 }; sdmmc_storage_read(&sd_storage, 0, 1, &mbr); - total_size = (sd_storage.sec_cnt - 0x8000) / 0x200000; - u32 bar_hos_size = lv_obj_get_width(h1) * (mbr.partitions[0].size_sct / 0x200000) / total_size; + // Calculate MBR partitions size. + total_size = (sd_storage.sec_cnt - AU_ALIGN_SECTORS) / SECTORS_PER_GB; + u32 bar_hos_size = lv_obj_get_width(h1) * (mbr.partitions[0].size_sct / SECTORS_PER_GB) / total_size; u32 bar_emu_size = 0; for (u32 i = 1; i < 4; i++) if (mbr.partitions[i].type == 0xE0) bar_emu_size += mbr.partitions[i].size_sct; - bar_emu_size = lv_obj_get_width(h1) * (bar_emu_size / 0x200000) / total_size; + bar_emu_size = lv_obj_get_width(h1) * (bar_emu_size / SECTORS_PER_GB) / total_size; u32 bar_l4t_size = 0; for (u32 i = 1; i < 4; i++) if (mbr.partitions[i].type == 0x83) bar_l4t_size += mbr.partitions[i].size_sct; - bar_l4t_size = lv_obj_get_width(h1) * (bar_l4t_size / 0x200000) / total_size; + bar_l4t_size = lv_obj_get_width(h1) * (bar_l4t_size / SECTORS_PER_GB) / total_size; u32 bar_and_size = lv_obj_get_width(h1) - bar_hos_size - bar_emu_size - bar_l4t_size; - // Create bar objects. + // Create HOS bar. lv_obj_t *bar_mbr_hos = lv_bar_create(h1, NULL); lv_obj_set_size(bar_mbr_hos, bar_hos_size, LV_DPI / 3); lv_bar_set_range(bar_mbr_hos, 0, 1); @@ -1973,36 +2158,41 @@ static void create_mbox_check_files_total_size() lv_bar_set_style(bar_mbr_hos, LV_BAR_STYLE_INDIC, &bar_hos_ind); lv_obj_align(bar_mbr_hos, lbl_part, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 6); + // Create emuMMC bar. lv_obj_t *bar_mbr_emu = lv_bar_create(h1, bar_mbr_hos); lv_obj_set_size(bar_mbr_emu, bar_emu_size, LV_DPI / 3); lv_bar_set_style(bar_mbr_emu, LV_BAR_STYLE_INDIC, &bar_emu_ind); lv_obj_align(bar_mbr_emu, bar_mbr_hos, LV_ALIGN_OUT_RIGHT_MID, 0, 0); + // Create L4T bar. lv_obj_t *bar_mbr_l4t = lv_bar_create(h1, bar_mbr_hos); lv_obj_set_size(bar_mbr_l4t, bar_l4t_size, LV_DPI / 3); lv_bar_set_style(bar_mbr_l4t, LV_BAR_STYLE_INDIC, &bar_l4t_ind); lv_obj_align(bar_mbr_l4t, bar_mbr_emu, LV_ALIGN_OUT_RIGHT_MID, 0, 0); - lv_obj_t *bar_mbr_rest = lv_bar_create(h1, bar_mbr_hos); - lv_obj_set_size(bar_mbr_rest, bar_and_size > 1 ? bar_and_size : 0, LV_DPI / 3); - lv_bar_set_style(bar_mbr_rest, LV_BAR_STYLE_INDIC, &bar_and_ind); - lv_obj_align(bar_mbr_rest, bar_mbr_l4t, LV_ALIGN_OUT_RIGHT_MID, 0, 0); + // Create GPT bar. + lv_obj_t *bar_mbr_gpt = lv_bar_create(h1, bar_mbr_hos); + lv_obj_set_size(bar_mbr_gpt, bar_and_size > 1 ? bar_and_size : 0, LV_DPI / 3); + lv_bar_set_style(bar_mbr_gpt, LV_BAR_STYLE_INDIC, &bar_and_ind); + lv_obj_align(bar_mbr_gpt, bar_mbr_l4t, LV_ALIGN_OUT_RIGHT_MID, 0, 0); - // Create separator objects. + // Create emuMMC separator. lv_obj_t *sep_mbr_emu = lv_cont_create(h1, NULL); lv_obj_set_size(sep_mbr_emu, bar_emu_size ? 8 : 0, LV_DPI / 3); lv_obj_set_style(sep_mbr_emu, &sep_emu_bg); lv_obj_align(sep_mbr_emu, bar_mbr_hos, LV_ALIGN_OUT_RIGHT_MID, -4, 0); + // Create L4T separator. lv_obj_t *sep_mbr_l4t = lv_cont_create(h1, sep_mbr_emu); lv_obj_set_size(sep_mbr_l4t, bar_l4t_size ? 8 : 0, LV_DPI / 3); lv_obj_set_style(sep_mbr_l4t, &sep_l4t_bg); lv_obj_align(sep_mbr_l4t, bar_mbr_emu, LV_ALIGN_OUT_RIGHT_MID, -4, 0); - lv_obj_t *sep_mbr_rest = lv_cont_create(h1, sep_mbr_emu); - lv_obj_set_size(sep_mbr_rest, bar_and_size ? (bar_and_size > 1 ? 8 : 0) : 0, LV_DPI / 3); - lv_obj_set_style(sep_mbr_rest, &sep_and_bg); - lv_obj_align(sep_mbr_rest, bar_mbr_l4t, LV_ALIGN_OUT_RIGHT_MID, -4, 0); + // Create GPT separator. + lv_obj_t *sep_mbr_gpt = lv_cont_create(h1, sep_mbr_emu); + lv_obj_set_size(sep_mbr_gpt, bar_and_size ? (bar_and_size > 1 ? 8 : 0) : 0, LV_DPI / 3); + lv_obj_set_style(sep_mbr_gpt, &sep_and_bg); + lv_obj_align(sep_mbr_gpt, bar_mbr_l4t, LV_ALIGN_OUT_RIGHT_MID, -4, 0); // Print partition table info. s_printf(txt_buf, @@ -2020,7 +2210,10 @@ static void create_mbox_check_files_total_size() lv_label_set_text(lbl_table, txt_buf); lv_obj_align(lbl_table, h1, LV_ALIGN_IN_TOP_MID, 0, LV_DPI); - lv_mbox_add_btns(mbox, mbox_btn_map, mbox_action); + if (!part_info.backup_possible) + lv_mbox_add_btns(mbox, mbox_btn_map, mbox_action); + else + lv_mbox_add_btns(mbox, mbox_btn_map2, _mbox_check_files_total_size_option); lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); @@ -2034,7 +2227,7 @@ static lv_res_t _action_fix_mbr(lv_obj_t *btn) lv_obj_set_style(dark_bg, &mbox_darken); lv_obj_set_size(dark_bg, LV_HOR_RES, LV_VER_RES); - static const char *mbox_btn_map[] = { "\211", "\222OK", "\211", "" }; + static const char *mbox_btn_map[] = { "\251", "\222OK", "\251", "" }; lv_obj_t * mbox = lv_mbox_create(dark_bg, NULL); lv_mbox_set_recolor_text(mbox, true); @@ -2044,6 +2237,14 @@ static lv_res_t _action_fix_mbr(lv_obj_t *btn) lv_obj_t *lbl_status = lv_label_create(mbox, NULL); lv_label_set_recolor(lbl_status, true); + mbr_t mbr[2] = { 0 }; + gpt_t *gpt = zalloc(sizeof(gpt_t)); + gpt_header_t gpt_hdr_backup = { 0 }; + + bool has_mbr_attributes = false; + bool hybrid_mbr_changed = false; + bool gpt_partition_exists = false; + // Try to init sd card. No need for valid MBR. if (!sd_mount() && !sd_get_card_initialized()) { @@ -2051,9 +2252,6 @@ static lv_res_t _action_fix_mbr(lv_obj_t *btn) goto out; } - mbr_t mbr[2] = { 0 }; - gpt_t *gpt = calloc(1, sizeof(gpt_t)); - sdmmc_storage_read(&sd_storage, 0, 1, &mbr[0]); sdmmc_storage_read(&sd_storage, 1, sizeof(gpt_t) >> 9, gpt); @@ -2061,17 +2259,37 @@ static lv_res_t _action_fix_mbr(lv_obj_t *btn) sd_unmount(); - if (memcmp(&gpt->header.signature, "EFI PART", 8) || gpt->header.num_part_ents > 128) + // Check for secret MBR attributes. + if (gpt->entries[0].part_guid[7]) + has_mbr_attributes = true; + + // Check if there's a GPT Protective partition. + for (u32 i = 0; i < 4; i++) + { + if (mbr[0].partitions[i].type == 0xEE) + gpt_partition_exists = true; + } + + // Check if GPT is valid. + if (!gpt_partition_exists || memcmp(&gpt->header.signature, "EFI PART", 8) || gpt->header.num_part_ents > 128) { lv_label_set_text(lbl_status, "#FFDD00 Warning:# No valid GPT was found!"); - goto out; + + gpt_partition_exists = false; + + if (has_mbr_attributes) + goto check_changes; + else + goto out; } + sdmmc_storage_read(&sd_storage, gpt->header.alt_lba, 1, &gpt_hdr_backup); + // Parse GPT. LIST_INIT(gpt_parsed); for (u32 i = 0; i < gpt->header.num_part_ents; i++) { - emmc_part_t *part = (emmc_part_t *)calloc(sizeof(emmc_part_t), 1); + emmc_part_t *part = (emmc_part_t *)zalloc(sizeof(emmc_part_t)); if (gpt->entries[i].lba_start < gpt->header.first_use_lba) continue; @@ -2087,7 +2305,6 @@ static lv_res_t _action_fix_mbr(lv_obj_t *btn) list_append(&gpt_parsed, &part->link); } - free(gpt); // Set FAT and emuMMC partitions. u32 mbr_idx = 1; @@ -2125,7 +2342,7 @@ static lv_res_t _action_fix_mbr(lv_obj_t *btn) break; } - nx_emmc_gpt_free(&gpt_parsed); + emmc_gpt_free(&gpt_parsed); // Set GPT protective partition. mbr[1].partitions[mbr_idx].type = 0xEE; @@ -2133,26 +2350,27 @@ static lv_res_t _action_fix_mbr(lv_obj_t *btn) mbr[1].partitions[mbr_idx].size_sct = sd_storage.sec_cnt - 1; // Check for differences. - bool changed = false; for (u32 i = 1; i < 4; i++) { if ((mbr[0].partitions[i].type != mbr[1].partitions[i].type) || (mbr[0].partitions[i].start_sct != mbr[1].partitions[i].start_sct) || (mbr[0].partitions[i].size_sct != mbr[1].partitions[i].size_sct)) { - changed = true; + hybrid_mbr_changed = true; break; } } - if (!changed) +check_changes: + if (!hybrid_mbr_changed && !has_mbr_attributes) { lv_label_set_text(lbl_status, "#96FF00 Warning:# The Hybrid MBR needs no change!#"); goto out; } - char *txt_buf = malloc(0x4000); + char *txt_buf = malloc(SZ_16K); + // Current MBR info. s_printf(txt_buf, "#00DDFF Current MBR Layout:#\n"); s_printf(txt_buf + strlen(txt_buf), "Partition 0 - Type: %02x, Start: %08x, Size: %08x\n" @@ -2164,6 +2382,7 @@ static lv_res_t _action_fix_mbr(lv_obj_t *btn) mbr[0].partitions[2].type, mbr[0].partitions[2].start_sct, mbr[0].partitions[2].size_sct, mbr[0].partitions[3].type, mbr[0].partitions[3].start_sct, mbr[0].partitions[3].size_sct); + // New MBR info. s_printf(txt_buf + strlen(txt_buf), "#00DDFF New MBR Layout:#\n"); s_printf(txt_buf + strlen(txt_buf), "Partition 0 - Type: %02x, Start: %08x, Size: %08x\n" @@ -2195,16 +2414,57 @@ static lv_res_t _action_fix_mbr(lv_obj_t *btn) if (btn_wait() & BTN_POWER) { - // Write MBR. sd_mount(); - sdmmc_storage_write(&sd_storage, 0, 1, &mbr[1]); + + // Write MBR. + if (hybrid_mbr_changed) + sdmmc_storage_write(&sd_storage, 0, 1, &mbr[1]); + + // Fix MBR secret attributes. + if (has_mbr_attributes) + { + // Clear secret attributes. + gpt->entries[0].part_guid[7] = 0; + + if (gpt_partition_exists) + { + // Fix CRC32s. + u32 entries_size = sizeof(gpt_entry_t) * gpt->header.num_part_ents; + gpt->header.part_ents_crc32 = crc32_calc(0, (const u8 *)gpt->entries, entries_size); + gpt->header.crc32 = 0; // Set to 0 for calculation. + gpt->header.crc32 = crc32_calc(0, (const u8 *)&gpt->header, gpt->header.size); + + gpt_hdr_backup.part_ents_crc32 = gpt->header.part_ents_crc32; + gpt_hdr_backup.crc32 = 0; // Set to 0 for calculation. + gpt_hdr_backup.crc32 = crc32_calc(0, (const u8 *)&gpt_hdr_backup, gpt_hdr_backup.size); + + // Write main GPT. + u32 aligned_entries_size = ALIGN(entries_size, SD_BLOCKSIZE); + sdmmc_storage_write(&sd_storage, gpt->header.my_lba, (sizeof(gpt_header_t) + aligned_entries_size) >> 9, gpt); + + // Write backup GPT partition table. + sdmmc_storage_write(&sd_storage, gpt_hdr_backup.part_ent_lba, aligned_entries_size >> 9, gpt->entries); + + // Write backup GPT header. + sdmmc_storage_write(&sd_storage, gpt_hdr_backup.my_lba, 1, &gpt_hdr_backup); + } + else + { + // Only write the relevant sector if the only change is MBR attributes. + sdmmc_storage_write(&sd_storage, 2, 1, &gpt->entries[0]); + } + } + sd_unmount(); + lv_label_set_text(lbl_status, "#96FF00 The new Hybrid MBR was written successfully!#"); } else lv_label_set_text(lbl_status, "#FFDD00 Warning: The Hybrid MBR Fix was canceled!#"); out: + free(gpt); + lv_mbox_add_btns(mbox, mbox_btn_map, mbox_action); lv_obj_align(mbox, NULL, LV_ALIGN_CENTER, 0, 0); @@ -2224,6 +2484,7 @@ lv_res_t create_window_partition_manager(lv_obj_t *btn) static lv_style_t bar_hos_btn, bar_emu_btn, bar_l4t_btn, bar_and_btn; static lv_style_t sep_emu_bg, sep_l4t_bg, sep_and_bg; + // Set HOS bar styles. lv_style_copy(&bar_hos_bg, lv_theme_get_current()->bar.bg); bar_hos_bg.body.main_color = LV_COLOR_HEX(0x4A8000); bar_hos_bg.body.grad_color = bar_hos_bg.body.main_color; @@ -2234,6 +2495,7 @@ lv_res_t create_window_partition_manager(lv_obj_t *btn) bar_hos_btn.body.main_color = LV_COLOR_HEX(0x77CC00); bar_hos_btn.body.grad_color = bar_hos_btn.body.main_color; + // Set eMUMMC bar styles. lv_style_copy(&bar_emu_bg, lv_theme_get_current()->bar.bg); bar_emu_bg.body.main_color = LV_COLOR_HEX(0x940F00); bar_emu_bg.body.grad_color = bar_emu_bg.body.main_color; @@ -2248,6 +2510,7 @@ lv_res_t create_window_partition_manager(lv_obj_t *btn) sep_emu_bg.body.grad_color = sep_emu_bg.body.main_color; sep_emu_bg.body.radius = 0; + // Set L4T bar styles. lv_style_copy(&bar_l4t_bg, lv_theme_get_current()->bar.bg); bar_l4t_bg.body.main_color = LV_COLOR_HEX(0x006E80); bar_l4t_bg.body.grad_color = bar_l4t_bg.body.main_color; @@ -2261,6 +2524,7 @@ lv_res_t create_window_partition_manager(lv_obj_t *btn) sep_l4t_bg.body.main_color = LV_COLOR_HEX(0x00DDFF); sep_l4t_bg.body.grad_color = sep_l4t_bg.body.main_color; + // Set Android bar styles. lv_style_copy(&bar_and_bg, lv_theme_get_current()->bar.bg); bar_and_bg.body.main_color = LV_COLOR_HEX(0x804000); bar_and_bg.body.grad_color = bar_and_bg.body.main_color; @@ -2285,26 +2549,30 @@ lv_res_t create_window_partition_manager(lv_obj_t *btn) if (!sd_mount()) { lv_obj_t *lbl = lv_label_create(h1, NULL); + lv_label_set_recolor(lbl, true); lv_label_set_text(lbl, "#FFDD00 Failed to init SD!#"); return LV_RES_OK; } memset(&part_info, 0, sizeof(partition_ctxt_t)); - create_mbox_check_files_total_size(); + _create_mbox_check_files_total_size(); - char *txt_buf = malloc(0x2000); + char *txt_buf = malloc(SZ_8K); part_info.total_sct = sd_storage.sec_cnt; // Align down total size to ensure alignment of all partitions after HOS one. - part_info.alignment = part_info.total_sct - ALIGN_DOWN(part_info.total_sct, 0x8000); + part_info.alignment = part_info.total_sct - ALIGN_DOWN(part_info.total_sct, AU_ALIGN_SECTORS); part_info.total_sct -= part_info.alignment; - u32 extra_sct = 0x8000 + 0x400000; // Reserved 16MB alignment for FAT partition + 2GB. + u32 extra_sct = AU_ALIGN_SECTORS + 0x400000; // Reserved 16MB alignment for FAT partition + 2GB. // Set initial HOS partition size, so the correct cluster size can be selected. part_info.hos_size = (part_info.total_sct >> 11) - 16; // Important if there's no slider change. + // Check if eMMC should be 64GB (Aula). + part_info.emmc_is_64gb = fuse_read_hw_type() == FUSE_NX_HW_TYPE_AULA; + // Read current MBR. mbr_t mbr = { 0 }; sdmmc_storage_read(&sd_storage, 0, 1, &mbr); @@ -2315,8 +2583,11 @@ lv_res_t create_window_partition_manager(lv_obj_t *btn) u32 bar_and_size = 0; lv_obj_t *lbl = lv_label_create(h1, NULL); - lv_label_set_text(lbl, "New partition layout:"); + lv_label_set_recolor(lbl, true); + lv_label_set_text(lbl, "Choose #FFDD00 new# partition layout:"); + // Create disk layout blocks. + // HOS partition block. lv_obj_t *bar_hos = lv_bar_create(h1, NULL); lv_obj_set_size(bar_hos, bar_hos_size, LV_DPI / 2); lv_bar_set_range(bar_hos, 0, 1); @@ -2325,24 +2596,28 @@ lv_res_t create_window_partition_manager(lv_obj_t *btn) lv_obj_align(bar_hos, lbl, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 6); part_info.bar_hos = bar_hos; + // emuMMC partition block. lv_obj_t *bar_emu = lv_bar_create(h1, bar_hos); lv_obj_set_size(bar_emu, bar_emu_size, LV_DPI / 2); lv_bar_set_style(bar_emu, LV_BAR_STYLE_INDIC, &bar_emu_ind); lv_obj_align(bar_emu, bar_hos, LV_ALIGN_OUT_RIGHT_MID, 0, 0); part_info.bar_emu = bar_emu; + // L4T partition block. lv_obj_t *bar_l4t = lv_bar_create(h1, bar_hos); lv_obj_set_size(bar_l4t, bar_l4t_size, LV_DPI / 2); lv_bar_set_style(bar_l4t, LV_BAR_STYLE_INDIC, &bar_l4t_ind); lv_obj_align(bar_l4t, bar_emu, LV_ALIGN_OUT_RIGHT_MID, 0, 0); part_info.bar_l4t = bar_l4t; + // Android partition block. lv_obj_t *bar_and = lv_bar_create(h1, bar_hos); lv_obj_set_size(bar_and, bar_and_size, LV_DPI / 2); lv_bar_set_style(bar_and, LV_BAR_STYLE_INDIC, &bar_and_ind); lv_obj_align(bar_and, bar_l4t, LV_ALIGN_OUT_RIGHT_MID, 0, 0); part_info.bar_and = bar_and; + // HOS partition block. lv_obj_t *sep_emu = lv_cont_create(h1, NULL); lv_cont_set_fit(sep_emu, false, false); lv_obj_set_size(sep_emu, 0, LV_DPI / 2); // 8. @@ -2350,6 +2625,7 @@ lv_res_t create_window_partition_manager(lv_obj_t *btn) lv_obj_align(sep_emu, bar_hos, LV_ALIGN_OUT_RIGHT_MID, -4, 0); part_info.sep_emu = sep_emu; + // Create disk layout blending separators. lv_obj_t *sep_l4t = lv_cont_create(h1, sep_emu); lv_obj_set_style(sep_l4t, &sep_l4t_bg); lv_obj_align(sep_l4t, bar_emu, LV_ALIGN_OUT_RIGHT_MID, -4, 0); @@ -2360,6 +2636,7 @@ lv_res_t create_window_partition_manager(lv_obj_t *btn) lv_obj_align(sep_and, bar_l4t, LV_ALIGN_OUT_RIGHT_MID, -4, 0); part_info.sep_and = sep_and; + // Create slider type labels. lv_obj_t *lbl_hos = lv_label_create(h1, NULL); lv_label_set_recolor(lbl_hos, true); lv_label_set_static_text(lbl_hos, "#96FF00 "SYMBOL_DOT" HOS (FAT32):#"); @@ -2377,15 +2654,17 @@ lv_res_t create_window_partition_manager(lv_obj_t *btn) lv_label_set_static_text(lbl_and, "#FF8000 "SYMBOL_DOT" Android (USER):#"); lv_obj_align(lbl_and, lbl_l4t, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 3); + // Create HOS size slider. Non-interactive. lv_obj_t *slider_bar_hos = lv_bar_create(h1, NULL); lv_obj_set_size(slider_bar_hos, LV_DPI * 7, LV_DPI * 3 / 17); - lv_bar_set_range(slider_bar_hos, 0, (part_info.total_sct - 0x8000) / 0x200000); - lv_bar_set_value(slider_bar_hos, (part_info.total_sct - 0x8000) / 0x200000); + lv_bar_set_range(slider_bar_hos, 0, (part_info.total_sct - AU_ALIGN_SECTORS) / SECTORS_PER_GB); + lv_bar_set_value(slider_bar_hos, (part_info.total_sct - AU_ALIGN_SECTORS) / SECTORS_PER_GB); lv_bar_set_style(slider_bar_hos, LV_SLIDER_STYLE_BG, &bar_hos_bg); lv_bar_set_style(slider_bar_hos, LV_SLIDER_STYLE_INDIC, &bar_hos_ind); lv_obj_align(slider_bar_hos, lbl_hos, LV_ALIGN_OUT_RIGHT_MID, LV_DPI * 6 / 4, 0); part_info.slider_bar_hos = slider_bar_hos; + // Create emuMMC size slider. lv_obj_t *slider_emu = lv_slider_create(h1, NULL); lv_obj_set_size(slider_emu, LV_DPI * 7, LV_DPI / 3); lv_slider_set_range(slider_emu, 0, 20); @@ -2397,9 +2676,10 @@ lv_res_t create_window_partition_manager(lv_obj_t *btn) lv_slider_set_action(slider_emu, _action_slider_emu); part_info.slider_emu = slider_bar_hos; + // Create L4T size slider. lv_obj_t *slider_l4t = lv_slider_create(h1, NULL); lv_obj_set_size(slider_l4t, LV_DPI * 7, LV_DPI / 3); - lv_slider_set_range(slider_l4t, 0, (part_info.total_sct - extra_sct) / 0x200000); + lv_slider_set_range(slider_l4t, 0, (part_info.total_sct - extra_sct) / SECTORS_PER_GB); lv_slider_set_value(slider_l4t, 0); lv_slider_set_style(slider_l4t, LV_SLIDER_STYLE_BG, &bar_l4t_bg); lv_slider_set_style(slider_l4t, LV_SLIDER_STYLE_INDIC, &bar_l4t_ind); @@ -2408,9 +2688,10 @@ lv_res_t create_window_partition_manager(lv_obj_t *btn) lv_slider_set_action(slider_l4t, _action_slider_l4t); part_info.slider_l4t = slider_l4t; + // Create Android size slider. lv_obj_t *slider_and = lv_slider_create(h1, NULL); lv_obj_set_size(slider_and, LV_DPI * 7, LV_DPI / 3); - lv_slider_set_range(slider_and, 0, (part_info.total_sct - extra_sct) / 0x200000 - 4); // Subtract android reserved size. + lv_slider_set_range(slider_and, 0, (part_info.total_sct - extra_sct) / SECTORS_PER_GB - (ANDROID_SYSTEM_SIZE_MB / 1024)); // Subtract android reserved size. lv_slider_set_value(slider_and, 0); lv_slider_set_style(slider_and, LV_SLIDER_STYLE_BG, &bar_and_bg); lv_slider_set_style(slider_and, LV_SLIDER_STYLE_INDIC, &bar_and_ind); @@ -2419,38 +2700,43 @@ lv_res_t create_window_partition_manager(lv_obj_t *btn) lv_slider_set_action(slider_and, _action_slider_and); part_info.slider_and = slider_and; + // Create HOS size label. lv_obj_t *lbl_sl_hos = lv_label_create(h1, NULL); lv_label_set_recolor(lbl_sl_hos, true); - s_printf(txt_buf, "#96FF00 %d GiB#", (part_info.total_sct - 0x8000) >> 11 >> 10); + s_printf(txt_buf, "#96FF00 %d GiB#", (part_info.total_sct - AU_ALIGN_SECTORS) >> 11 >> 10); lv_label_set_text(lbl_sl_hos, txt_buf); lv_obj_align(lbl_sl_hos, slider_bar_hos, LV_ALIGN_OUT_RIGHT_MID, LV_DPI * 4 / 7, 0); part_info.lbl_hos = lbl_sl_hos; + // Create emuMMC size label. lv_obj_t *lbl_sl_emu = lv_label_create(h1, lbl_sl_hos); lv_label_set_text(lbl_sl_emu, "#FF3C28 0 GiB#"); lv_obj_align(lbl_sl_emu, lbl_sl_hos, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 3); part_info.lbl_emu = lbl_sl_emu; + // Create L4T size label. lv_obj_t *lbl_sl_l4t = lv_label_create(h1, lbl_sl_hos); lv_label_set_text(lbl_sl_l4t, "#00DDFF 0 GiB#"); lv_obj_align(lbl_sl_l4t, lbl_sl_emu, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 3); part_info.lbl_l4t = lbl_sl_l4t; + // Create Android size label. lv_obj_t *lbl_sl_and = lv_label_create(h1, lbl_sl_hos); lv_label_set_text(lbl_sl_and, "#FF8000 0 GiB#"); lv_obj_align(lbl_sl_and, lbl_sl_l4t, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 3); part_info.lbl_and = lbl_sl_and; + // Set partition manager notes. lv_obj_t *lbl_notes = lv_label_create(h1, NULL); lv_label_set_recolor(lbl_notes, true); lv_label_set_static_text(lbl_notes, "Note 1: Only up to #C7EA46 1GB# can be backed up. If more, you will be asked to back them manually at the next step.\n" "Note 2: Resized emuMMC formats the USER partition. A save data manager can be used to move them over.\n" - "Note 3: The #C7EA46 Flash Linux# and #C7EA46 Flash Android# will flash files if suitable partitions and installer files are found.\n" - "Note 4: The installation folder is #C7EA46 switchroot/install#. Linux uses #C7EA46 l4t.XX# and Android uses #C7EA46 twrp.img# and #C7EA46 tegra210-icosa.dtb#."); + "Note 3: The #C7EA46 Flash Linux# and #C7EA46 Flash Android# will flash files if suitable partitions and installer files are found.\n"); lv_label_set_style(lbl_notes, &hint_small_style); lv_obj_align(lbl_notes, lbl_and, LV_ALIGN_OUT_BOTTOM_LEFT, 0, LV_DPI / 5); + // Create UMS button. lv_obj_t *btn1 = lv_btn_create(h1, NULL); lv_obj_t *label_btn = lv_label_create(btn1, NULL); lv_btn_set_fit(btn1, true, true); @@ -2458,6 +2744,7 @@ lv_res_t create_window_partition_manager(lv_obj_t *btn) lv_obj_align(btn1, h1, LV_ALIGN_IN_TOP_LEFT, 0, LV_DPI * 5); lv_btn_set_action(btn1, LV_BTN_ACTION_CLICK, _action_part_manager_ums_sd); + // Create Flash Linux button. btn_flash_l4t = lv_btn_create(h1, NULL); lv_obj_t *label_btn2 = lv_label_create(btn_flash_l4t, NULL); lv_btn_set_fit(btn_flash_l4t, true, true); @@ -2467,33 +2754,42 @@ lv_res_t create_window_partition_manager(lv_obj_t *btn) // Disable Flash Linux button if partition not found. u32 size_sct = _get_available_l4t_partition(); - if (!l4t_flash_ctxt.offset_sct || !size_sct || size_sct < 0x800000) + if (!l4t_flash_ctxt.offset_sct || size_sct < 0x800000) { lv_obj_set_click(btn_flash_l4t, false); lv_btn_set_state(btn_flash_l4t, LV_BTN_STATE_INA); } + int part_type_and = _get_available_android_partition(); + + // Create Flash Android button. btn_flash_android = lv_btn_create(h1, NULL); label_btn = lv_label_create(btn_flash_android, NULL); lv_btn_set_fit(btn_flash_android, true, true); - lv_label_set_static_text(label_btn, SYMBOL_DOWNLOAD" Flash Android"); + switch (part_type_and) + { + case 0: // Disable Flash Android button if partition not found. + lv_label_set_static_text(label_btn, SYMBOL_DOWNLOAD" Flash Android"); + lv_obj_set_click(btn_flash_android, false); + lv_btn_set_state(btn_flash_android, LV_BTN_STATE_INA); + break; + case 1: // Android 10/11. + lv_label_set_static_text(label_btn, SYMBOL_DOWNLOAD" Flash Android 10/11"); + break; + case 2: // Android 13+ + lv_label_set_static_text(label_btn, SYMBOL_DOWNLOAD" Flash Android 13+"); + break; + } lv_obj_align(btn_flash_android, btn_flash_l4t, LV_ALIGN_OUT_RIGHT_MID, LV_DPI / 3, 0); lv_btn_set_action(btn_flash_android, LV_BTN_ACTION_CLICK, _action_flash_android); - // Disable Flash Android button if partition not found. - if (!_get_available_android_partition()) - { - lv_obj_set_click(btn_flash_android, false); - lv_btn_set_state(btn_flash_android, LV_BTN_STATE_INA); - } - + // Create next step button. btn1 = lv_btn_create(h1, NULL); label_btn = lv_label_create(btn1, NULL); lv_btn_set_fit(btn1, true, true); lv_label_set_static_text(label_btn, SYMBOL_SD" Next Step"); lv_obj_align(btn1, h1, LV_ALIGN_IN_TOP_RIGHT, 0, LV_DPI * 5); lv_btn_set_action(btn1, LV_BTN_ACTION_CLICK, _create_mbox_partitioning_next); - part_info.btn_partition = btn1; free(txt_buf); diff --git a/nyx/nyx_gui/gfx/gfx.c b/nyx/nyx_gui/gfx/gfx.c index bec4053..548986e 100644 --- a/nyx/nyx_gui/gfx/gfx.c +++ b/nyx/nyx_gui/gfx/gfx.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2022 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,10 +19,14 @@ #include #include "gfx.h" +#define COLUMN2_X 640 + // Global gfx console and context. gfx_ctxt_t gfx_ctxt; gfx_con_t gfx_con; +static bool gfx_con_init_done = false; + static const u8 _gfx_font[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // Char 032 ( ) 0x00, 0x30, 0x30, 0x18, 0x18, 0x00, 0x0C, 0x00, // Char 033 (!) @@ -148,12 +152,15 @@ void gfx_con_init() gfx_con.fntsz = 16; gfx_con.x = 0; gfx_con.y = 0; + gfx_con.col = 0; gfx_con.savedx = 0; gfx_con.savedy = 0; - gfx_con.fgcol = 0xFFFFFFFF; + gfx_con.fgcol = TXT_CLR_DEFAULT; gfx_con.fillbg = 1; - gfx_con.bgcol = 0xFF000000; + gfx_con.bgcol = TXT_CLR_BG; gfx_con.mute = 0; + + gfx_con_init_done = true; } void gfx_con_setcol(u32 fgcol, int fillbg, u32 bgcol) @@ -163,19 +170,34 @@ void gfx_con_setcol(u32 fgcol, int fillbg, u32 bgcol) gfx_con.bgcol = bgcol; } -void gfx_con_getpos(u32 *x, u32 *y) +void gfx_con_getpos(u32 *x, u32 *y, u32 *c) { *x = gfx_con.x; *y = gfx_con.y; + *c = gfx_con.col; } -void gfx_con_setpos(u32 x, u32 y) +void gfx_con_setpos(u32 x, u32 y, u32 c) { gfx_con.x = x; gfx_con.y = y; + + switch (c) + { + case GFX_COL_KEEP: + break; + case GFX_COL_AUTO: + if (x < COLUMN2_X) + gfx_con.col = 0; + else + gfx_con.col = COLUMN2_X; + break; + default: + gfx_con.col = c; + break; + } } -static int gfx_column = 0; void gfx_putc(char c) { // Duplicate code for performance reasons. @@ -209,33 +231,33 @@ void gfx_putc(char c) gfx_con.x += 16; if (gfx_con.x > gfx_ctxt.width - 16) { - gfx_con.x = gfx_column; + gfx_con.x = gfx_con.col; gfx_con.y += 16; if (gfx_con.y > gfx_ctxt.height - 33) { gfx_con.y = 0; - if (!gfx_column) - gfx_column = 640; + if (!gfx_con.col) + gfx_con.col = COLUMN2_X; else - gfx_column = 0; - gfx_con.x = gfx_column; + gfx_con.col = 0; + gfx_con.x = gfx_con.col; } } } else if (c == '\n') { - gfx_con.x = gfx_column; - gfx_con.y +=16; + gfx_con.x = gfx_con.col; + gfx_con.y += 16; if (gfx_con.y > gfx_ctxt.height - 33) { gfx_con.y = 0; - if (!gfx_column) - gfx_column = 640; + if (!gfx_con.col) + gfx_con.col = COLUMN2_X; else - gfx_column = 0; - gfx_con.x = gfx_column; + gfx_con.col = 0; + gfx_con.x = gfx_con.col; } } break; @@ -258,44 +280,44 @@ void gfx_putc(char c) } } gfx_con.x += 8; - if (gfx_con.x > gfx_ctxt.width / 2 + gfx_column - 8) + if (gfx_con.x > gfx_ctxt.width / 2 + gfx_con.col - 8) { - gfx_con.x = gfx_column; + gfx_con.x = gfx_con.col; gfx_con.y += 8; if (gfx_con.y > gfx_ctxt.height - 33) { gfx_con.y = 0; - if (!gfx_column) - gfx_column = 640; + if (!gfx_con.col) + gfx_con.col = COLUMN2_X; else - gfx_column = 0; - gfx_con.x = gfx_column; + gfx_con.col = 0; + gfx_con.x = gfx_con.col; } } } else if (c == '\n') { - gfx_con.x = gfx_column; + gfx_con.x = gfx_con.col; gfx_con.y += 8; if (gfx_con.y > gfx_ctxt.height - 33) { gfx_con.y = 0; - if (!gfx_column) - gfx_column = 640; + if (!gfx_con.col) + gfx_con.col = COLUMN2_X; else - gfx_column = 0; - gfx_con.x = gfx_column; + gfx_con.col = 0; + gfx_con.x = gfx_con.col; } } break; } } -void gfx_puts(char *s) +void gfx_puts(const char *s) { - if (!s || gfx_con.mute) + if (!s || !gfx_con_init_done || gfx_con.mute) return; for (; *s; s++) @@ -304,14 +326,24 @@ void gfx_puts(char *s) static void _gfx_putn(u32 v, int base, char fill, int fcnt) { - char buf[65]; - static const char digits[] = "0123456789ABCDEFghijklmnopqrstuvwxyz"; - char *p; - int c = fcnt; + static const char digits[] = "0123456789ABCDEF"; - if (base > 36) + char *p; + char buf[65]; + int c = fcnt; + bool negative = false; + + if (base != 10 && base != 16) return; + // Account for negative numbers. + if (base == 10 && v & 0x80000000) + { + negative = true; + v = (int)v * -1; + c--; + } + p = buf + 64; *p = 0; do @@ -321,9 +353,12 @@ static void _gfx_putn(u32 v, int base, char fill, int fcnt) v /= base; } while (v); + if (negative) + *--p = '-'; + if (fill != 0) { - while (c > 0) + while (c > 0 && p > buf) { *--p = fill; c--; @@ -335,16 +370,16 @@ static void _gfx_putn(u32 v, int base, char fill, int fcnt) void gfx_printf(const char *fmt, ...) { - if (gfx_con.mute) + if (!gfx_con_init_done || gfx_con.mute) return; va_list ap; int fill, fcnt; va_start(ap, fmt); - while(*fmt) + while (*fmt) { - if(*fmt == '%') + if (*fmt == '%') { fmt++; fill = 0; @@ -409,26 +444,37 @@ void gfx_printf(const char *fmt, ...) va_end(ap); } +static void _gfx_cputs(u32 color, const char *s) +{ + gfx_con.fgcol = color; + gfx_puts(s); + gfx_putc('\n'); + gfx_con.fgcol = TXT_CLR_DEFAULT; +} + +void gfx_wputs(const char *s) { _gfx_cputs(TXT_CLR_WARNING, s); } +void gfx_eputs(const char *s) { _gfx_cputs(TXT_CLR_ERROR, s); } + void gfx_hexdump(u32 base, const void *buf, u32 len) { - if (gfx_con.mute) + if (!gfx_con_init_done || gfx_con.mute) return; u8 *buff = (u8 *)buf; u8 prevFontSize = gfx_con.fntsz; gfx_con.fntsz = 8; - for(u32 i = 0; i < len; i++) + for (u32 i = 0; i < len; i++) { - if(i % 0x10 == 0) + if (i % 0x10 == 0) { - if(i != 0) + if (i != 0) { gfx_puts("| "); - for(u32 j = 0; j < 0x10; j++) + for (u32 j = 0; j < 0x10; j++) { u8 c = buff[i - 0x10 + j]; - if(c >= 32 && c <= 126) + if (c >= 32 && c <= 126) gfx_putc(c); else gfx_putc('.'); @@ -449,10 +495,10 @@ void gfx_hexdump(u32 base, const void *buf, u32 len) gfx_puts(" "); } gfx_puts("| "); - for(u32 j = 0; j < (ln ? k : k + 1); j++) + for (u32 j = 0; j < (ln ? k : k + 1); j++) { u8 c = buff[i - k + j]; - if(c >= 32 && c <= 126) + if (c >= 32 && c <= 126) gfx_putc(c); else gfx_putc('.'); @@ -469,7 +515,19 @@ void gfx_set_pixel(u32 x, u32 y, u32 color) gfx_ctxt.fb[y + (gfx_ctxt.width - x) * gfx_ctxt.stride] = color; } -void __attribute__((optimize("unroll-loops"))) gfx_set_rect_land_pitch(u32 *fb, const u32 *buf, u32 stride, u32 pos_x, u32 pos_y, u32 pos_x2, u32 pos_y2) +void gfx_set_rect_pitch(u32 *fb, const u32 *buf, u32 stride, u32 pos_x, u32 pos_y, u32 pos_x2, u32 pos_y2) +{ + u32 *ptr = (u32 *)buf; + u32 line_size = pos_x2 - pos_x + 1; + //ptr = gfx_debug_rect(buf, pos_x, pos_y, pos_x2, pos_y2); + for (u32 y = pos_y; y <= pos_y2; y++) + { + memcpy(&fb[pos_x + y * stride], ptr, line_size * sizeof(u32)); + ptr += line_size; + } +} + +void gfx_set_rect_land_pitch(u32 *fb, const u32 *buf, u32 stride, u32 pos_x, u32 pos_y, u32 pos_x2, u32 pos_y2) { u32 *ptr = (u32 *)buf; @@ -477,8 +535,8 @@ void __attribute__((optimize("unroll-loops"))) gfx_set_rect_land_pitch(u32 *fb, if (!(pixels_w % 8)) { - for (u32 y = pos_y; y < (pos_y2 + 1); y++) - for (u32 x = pos_x; x < (pos_x2 + 1); x+=8) + for (u32 y = pos_y; y <= pos_y2; y++) + for (u32 x = pos_x; x <= pos_x2; x += 8) { u32 *fbx = &fb[x * stride + y]; @@ -500,7 +558,7 @@ void __attribute__((optimize("unroll-loops"))) gfx_set_rect_land_pitch(u32 *fb, } } -void __attribute__((optimize("unroll-loops"))) gfx_set_rect_land_block(u32 *fb, const u32 *buf, u32 pos_x, u32 pos_y, u32 pos_x2, u32 pos_y2) +void gfx_set_rect_land_block(u32 *fb, const u32 *buf, u32 pos_x, u32 pos_y, u32 pos_x2, u32 pos_y2) { u32 *ptr = (u32 *)buf; u32 GOB_address = 0; @@ -509,9 +567,9 @@ void __attribute__((optimize("unroll-loops"))) gfx_set_rect_land_block(u32 *fb, // Optimized u32 image_width_in_gobs = 655360; //1280 - for (u32 y = pos_y; y < (pos_y2 + 1); y++) + for (u32 y = pos_y; y <= pos_y2; y++) { - for (u32 x = pos_x; x < (pos_x2 + 1); x++) + for (u32 x = pos_x; x <= pos_x2; x++) { GOB_address = (y >> 7) * image_width_in_gobs + ((x >> 4) << 13) + (((y % 128) >> 3) << 9); diff --git a/nyx/nyx_gui/gfx/gfx.h b/nyx/nyx_gui/gfx/gfx.h index ce289d4..e8686e0 100644 --- a/nyx/nyx_gui/gfx/gfx.h +++ b/nyx/nyx_gui/gfx/gfx.h @@ -19,12 +19,30 @@ #ifndef _GFX_H_ #define _GFX_H_ -#include +#include -#define EPRINTF(text) gfx_printf("%k"text"%k\n", 0xFFFF0000, 0xFFCCCCCC) -#define EPRINTFARGS(text, args...) gfx_printf("%k"text"%k\n", 0xFFFF0000, args, 0xFFCCCCCC) -#define WPRINTF(text) gfx_printf("%k"text"%k\n", 0xFFFFDD00, 0xFFCCCCCC) -#define WPRINTFARGS(text, args...) gfx_printf("%k"text"%k\n", 0xFFFFDD00, args, 0xFFCCCCCC) +#define GFX_COL_KEEP 0xFFFE +#define GFX_COL_AUTO 0xFFFF + +#define TXT_CLR_BG 0xFF000000 // Black. +#define TXT_CLR_DEFAULT 0xFFFFFFFF // White. +#define TXT_CLR_WARNING 0xFFFFDD00 // Yellow. +#define TXT_CLR_ERROR 0xFFFF0000 // Red. +#define TXT_CLR_CYAN_L 0xFF00CCFF // Light Cyan. 0xFF0099EE 0xFF00DDFF FF0AB9E6 +#define TXT_CLR_TURQUOISE 0xFF00FFCC // Turquoise. +#define TXT_CLR_ORANGE 0xFFFFBA00 // Orange. +#define TXT_CLR_GREENISH 0xFF96FF00 // Toxic Green. 0xFFAEFD14 0xFFC7EA46 +#define TXT_CLR_GREEN_D 0xFF008800 // Dark Green. +#define TXT_CLR_RED_D 0xFF880000 // Dark Red. 0xFF800000 +#define TXT_CLR_GREY_D 0xFF303030 // Darkest Grey. +#define TXT_CLR_GREY_DM 0xFF444444 // Darker Grey. +#define TXT_CLR_GREY_M 0xFF555555 // Dark Grey. +#define TXT_CLR_GREY 0xFF888888 // Grey. + +#define EPRINTF(text) gfx_eputs(text) +#define EPRINTFARGS(text, args...) gfx_printf("%k"text"%k\n", TXT_CLR_ERROR, args, TXT_CLR_DEFAULT) +#define WPRINTF(text) gfx_wputs(text) +#define WPRINTFARGS(text, args...) gfx_printf("%k"text"%k\n", TXT_CLR_WARNING, args, TXT_CLR_DEFAULT) typedef struct _gfx_ctxt_t { @@ -40,8 +58,10 @@ typedef struct _gfx_con_t u32 fntsz; u32 x; u32 y; + u32 col; u32 savedx; u32 savedy; + u32 savedcol; u32 fgcol; int fillbg; u32 bgcol; @@ -57,15 +77,18 @@ void gfx_clear_grey(u8 color); void gfx_clear_color(u32 color); void gfx_con_init(); void gfx_con_setcol(u32 fgcol, int fillbg, u32 bgcol); -void gfx_con_getpos(u32 *x, u32 *y); -void gfx_con_setpos(u32 x, u32 y); +void gfx_con_getpos(u32 *x, u32 *y, u32 *c); +void gfx_con_setpos(u32 x, u32 y, u32 c); void gfx_putc(char c); -void gfx_puts(char *s); -void gfx_printf(const char *fmt, ...); +void gfx_puts(const char *s); +void gfx_wputs(const char *s); +void gfx_eputs(const char *s); +void gfx_printf(const char *fmt, ...) /* __attribute__((format(printf, 1, 2))) */; void gfx_hexdump(u32 base, const void *buf, u32 len); void gfx_set_pixel(u32 x, u32 y, u32 color); +void gfx_set_rect_pitch(u32 *fb, const u32 *buf, u32 stride, u32 pos_x, u32 pos_y, u32 pos_x2, u32 pos_y2); void gfx_set_rect_land_pitch(u32 *fb, const u32 *buf, u32 stride, u32 pos_x, u32 pos_y, u32 pos_x2, u32 pos_y2); void gfx_set_rect_land_block(u32 *fb, const u32 *buf, u32 pos_x, u32 pos_y, u32 pos_x2, u32 pos_y2); diff --git a/nyx/nyx_gui/gfx/logos-gui.h b/nyx/nyx_gui/gfx/logos-gui.h index 6bae619..de65974 100644 --- a/nyx/nyx_gui/gfx/logos-gui.h +++ b/nyx/nyx_gui/gfx/logos-gui.h @@ -1,11 +1,26 @@ +/* + * Copyright (c) 2018-2024 CTCaer + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + #ifndef _LOGOS_GUI_H_ #define _LOGOS_GUI_H_ -#include +#include #include #include -#include #define HEKATE_LOGO @@ -375,7 +390,7 @@ const u8 touch_cursor_map[] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; -lv_img_dsc_t touch_cursor = { +const lv_img_dsc_t touch_cursor = { .header.always_zero = 0, .header.w = 33, .header.h = 33, @@ -386,7 +401,7 @@ lv_img_dsc_t touch_cursor = { #ifdef HEKATE_LOGO -lv_img_dsc_t hekate_logo = { +const lv_img_dsc_t hekate_logo = { .header.always_zero = 0, .header.w = 193, .header.h = 76, @@ -395,7 +410,7 @@ lv_img_dsc_t hekate_logo = { .data = (const uint8_t *)(NYX_RES_ADDR + 0x1D900), }; -lv_img_dsc_t ctcaer_logo = { +const lv_img_dsc_t ctcaer_logo = { .header.always_zero = 0, .header.w = 147, .header.h = 76, @@ -406,4 +421,4 @@ lv_img_dsc_t ctcaer_logo = { #endif -#endif \ No newline at end of file +#endif diff --git a/nyx/nyx_gui/hos/hos.c b/nyx/nyx_gui/hos/hos.c index 616c93c..cef7bbe 100644 --- a/nyx/nyx_gui/hos/hos.c +++ b/nyx/nyx_gui/hos/hos.c @@ -2,7 +2,7 @@ * Copyright (c) 2018 naehrwert * Copyright (c) 2018 st4rk * Copyright (c) 2018 Ced2911 - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2025 CTCaer * Copyright (c) 2018 balika011 * * This program is free software; you can redistribute it and/or modify it @@ -20,28 +20,14 @@ #include +#include + #include "hos.h" #include "../config.h" -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "../storage/nx_emmc.h" -#include -#include -#include extern hekate_config h_cfg; +u8 *cal0_buf = NULL; static u8 *bis_keys = NULL; typedef struct _tsec_keys_t @@ -66,7 +52,7 @@ typedef struct _kb_t u8 padding[0x150]; } kb_t; -static const u8 keyblob_keyseeds[][SE_KEY_128_SIZE] = { +static const u8 keyblob_keyseeds[HOS_KB_VERSION_600 - HOS_KB_VERSION_100 + 1][SE_KEY_128_SIZE] = { { 0xDF, 0x20, 0x6F, 0x59, 0x44, 0x54, 0xEF, 0xDC, 0x70, 0x74, 0x48, 0x3B, 0x0D, 0xED, 0x9F, 0xD3 }, // 1.0.0. { 0x0C, 0x25, 0x61, 0x5D, 0x68, 0x4C, 0xEB, 0x42, 0x1C, 0x23, 0x79, 0xEA, 0x82, 0x25, 0x12, 0xAC }, // 3.0.0. { 0x33, 0x76, 0x85, 0xEE, 0x88, 0x4A, 0xAE, 0x0A, 0xC2, 0x8A, 0xFD, 0x7D, 0x63, 0xC0, 0x43, 0x3B }, // 3.0.1. @@ -90,10 +76,10 @@ static const u8 master_kekseed_620[SE_KEY_128_SIZE] = //!TODO: Update on mkey changes. static const u8 master_kekseed_t210_max[SE_KEY_128_SIZE] = - { 0x68, 0x3B, 0xCA, 0x54, 0xB8, 0x6F, 0x92, 0x48, 0xC3, 0x05, 0x76, 0x87, 0x88, 0x70, 0x79, 0x23 }; // 13.0.0. + { 0xA1, 0x7D, 0x34, 0xDB, 0x2D, 0x9D, 0xDA, 0xE5, 0xF8, 0x15, 0x63, 0x4C, 0x8F, 0xE7, 0x6C, 0xD8 }; // 20.0.0. //!TODO: Update on mkey changes. -static const u8 master_kekseed_t210b01[][SE_KEY_128_SIZE] = { +static const u8 master_kekseed_t210b01[HOS_KB_VERSION_MAX - HOS_KB_VERSION_600 + 1][SE_KEY_128_SIZE] = { { 0x77, 0x60, 0x5A, 0xD2, 0xEE, 0x6E, 0xF8, 0x3C, 0x3F, 0x72, 0xE2, 0x59, 0x9D, 0xAC, 0x5E, 0x56 }, // 6.0.0. { 0x1E, 0x80, 0xB8, 0x17, 0x3E, 0xC0, 0x60, 0xAA, 0x11, 0xBE, 0x1A, 0x4A, 0xA6, 0x6F, 0xE4, 0xAE }, // 6.2.0. { 0x94, 0x08, 0x67, 0xBD, 0x0A, 0x00, 0x38, 0x84, 0x11, 0xD3, 0x1A, 0xDB, 0xDD, 0x8D, 0xF1, 0x8A }, // 7.0.0. @@ -102,6 +88,13 @@ static const u8 master_kekseed_t210b01[][SE_KEY_128_SIZE] = { { 0x0E, 0x44, 0x0C, 0xED, 0xB4, 0x36, 0xC0, 0x3F, 0xAA, 0x1D, 0xAE, 0xBF, 0x62, 0xB1, 0x09, 0x82 }, // 9.1.0. { 0xE5, 0x41, 0xAC, 0xEC, 0xD1, 0xA7, 0xD1, 0xAB, 0xED, 0x03, 0x77, 0xF1, 0x27, 0xCA, 0xF8, 0xF1 }, // 12.1.0. { 0x52, 0x71, 0x9B, 0xDF, 0xA7, 0x8B, 0x61, 0xD8, 0xD5, 0x85, 0x11, 0xE4, 0x8E, 0x4F, 0x74, 0xC6 }, // 13.0.0. + { 0xD2, 0x68, 0xC6, 0x53, 0x9D, 0x94, 0xF9, 0xA8, 0xA5, 0xA8, 0xA7, 0xC8, 0x8F, 0x53, 0x4B, 0x7A }, // 14.0.0. + { 0xEC, 0x61, 0xBC, 0x82, 0x1E, 0x0F, 0x5A, 0xC3, 0x2B, 0x64, 0x3F, 0x9D, 0xD6, 0x19, 0x22, 0x2D }, // 15.0.0. + { 0xA5, 0xEC, 0x16, 0x39, 0x1A, 0x30, 0x16, 0x08, 0x2E, 0xCF, 0x09, 0x6F, 0x5E, 0x7C, 0xEE, 0xA9 }, // 16.0.0. + { 0x8D, 0xEE, 0x9E, 0x11, 0x36, 0x3A, 0x9B, 0x0A, 0x6A, 0xC7, 0xBB, 0xE9, 0xD1, 0x03, 0xF7, 0x80 }, // 17.0.0. + { 0x4F, 0x41, 0x3C, 0x3B, 0xFB, 0x6A, 0x01, 0x2A, 0x68, 0x9F, 0x83, 0xE9, 0x53, 0xBD, 0x16, 0xD2 }, // 18.0.0. + { 0x31, 0xBE, 0x25, 0xFB, 0xDB, 0xB4, 0xEE, 0x49, 0x5C, 0x77, 0x05, 0xC2, 0x36, 0x9F, 0x34, 0x80 }, // 19.0.0. + { 0x1A, 0x31, 0x62, 0x87, 0xA8, 0x09, 0xCA, 0xF8, 0x69, 0x15, 0x45, 0xC2, 0x6B, 0xAA, 0x5A, 0x8A }, // 20.0.0. }; static const u8 console_keyseed[SE_KEY_128_SIZE] = @@ -114,7 +107,7 @@ const u8 package2_keyseed[SE_KEY_128_SIZE] = { 0xFB, 0x8B, 0x6A, 0x9C, 0x79, 0x00, 0xC8, 0x49, 0xEF, 0xD2, 0x4D, 0x85, 0x4D, 0x30, 0xA0, 0xC7 }; //!TODO: Update on mkey changes. -static const u8 mkey_vectors[KB_FIRMWARE_VERSION_MAX + 1][SE_KEY_128_SIZE] = { +static const u8 mkey_vectors[HOS_KB_VERSION_MAX + 1][SE_KEY_128_SIZE] = { { 0x0C, 0xF0, 0x59, 0xAC, 0x85, 0xF6, 0x26, 0x65, 0xE1, 0xE9, 0x19, 0x55, 0xE6, 0xF2, 0x67, 0x3D }, // Zeroes encrypted with mkey 00. { 0x29, 0x4C, 0x04, 0xC8, 0xEB, 0x10, 0xED, 0x9D, 0x51, 0x64, 0x97, 0xFB, 0xF3, 0x4D, 0x50, 0xDD }, // Mkey 00 encrypted with mkey 01. { 0xDE, 0xCF, 0xEB, 0xEB, 0x10, 0xAE, 0x74, 0xD8, 0xAD, 0x7C, 0xF4, 0x9E, 0x62, 0xE0, 0xE8, 0x72 }, // Mkey 01 encrypted with mkey 02. @@ -128,10 +121,17 @@ static const u8 mkey_vectors[KB_FIRMWARE_VERSION_MAX + 1][SE_KEY_128_SIZE] = { { 0xB8, 0x96, 0x9E, 0x4A, 0x00, 0x0D, 0xD6, 0x28, 0xB3, 0xD1, 0xDB, 0x68, 0x5F, 0xFB, 0xE1, 0x2A }, // Mkey 09 encrypted with mkey 10. { 0xC1, 0x8D, 0x16, 0xBB, 0x2A, 0xE4, 0x1D, 0xD4, 0xC2, 0xC1, 0xB6, 0x40, 0x94, 0x35, 0x63, 0x98 }, // Mkey 10 encrypted with mkey 11. { 0xA3, 0x24, 0x65, 0x75, 0xEA, 0xCC, 0x6E, 0x8D, 0xFB, 0x5A, 0x16, 0x50, 0x74, 0xD2, 0x15, 0x06 }, // Mkey 11 encrypted with mkey 12. + { 0x83, 0x67, 0xAF, 0x01, 0xCF, 0x93, 0xA1, 0xAB, 0x80, 0x45, 0xF7, 0x3F, 0x72, 0xFD, 0x3B, 0x38 }, // Mkey 12 encrypted with mkey 13. + { 0xB1, 0x81, 0xA6, 0x0D, 0x72, 0xC7, 0xEE, 0x15, 0x21, 0xF3, 0xC0, 0xB5, 0x6B, 0x61, 0x6D, 0xE7 }, // Mkey 13 encrypted with mkey 14. + { 0xAF, 0x11, 0x4C, 0x67, 0x17, 0x7A, 0x52, 0x43, 0xF7, 0x70, 0x2F, 0xC7, 0xEF, 0x81, 0x72, 0x16 }, // Mkey 14 encrypted with mkey 15. + { 0x25, 0x12, 0x8B, 0xCB, 0xB5, 0x46, 0xA1, 0xF8, 0xE0, 0x52, 0x15, 0xB7, 0x0B, 0x57, 0x00, 0xBD }, // Mkey 15 encrypted with mkey 16. + { 0x58, 0x15, 0xD2, 0xF6, 0x8A, 0xE8, 0x19, 0xAB, 0xFB, 0x2D, 0x52, 0x9D, 0xE7, 0x55, 0xF3, 0x93 }, // Mkey 16 encrypted with mkey 17. + { 0x4A, 0x01, 0x3B, 0xC7, 0x44, 0x6E, 0x45, 0xBD, 0xE6, 0x5E, 0x2B, 0xEC, 0x07, 0x37, 0x52, 0x86 }, // Mkey 17 encrypted with mkey 18. + { 0x97, 0xE4, 0x11, 0xAB, 0x22, 0x72, 0x1A, 0x1F, 0x70, 0x5C, 0x00, 0xB3, 0x96, 0x30, 0x05, 0x28 }, // Mkey 18 encrypted with mkey 19. }; //!TODO: Update on mkey changes. -static const u8 new_console_keyseed[KB_FIRMWARE_VERSION_MAX - KB_FIRMWARE_VERSION_400 + 1][SE_KEY_128_SIZE] = { +static const u8 new_console_keyseed[HOS_KB_VERSION_MAX - HOS_KB_VERSION_400 + 1][SE_KEY_128_SIZE] = { { 0x8B, 0x4E, 0x1C, 0x22, 0x42, 0x07, 0xC8, 0x73, 0x56, 0x94, 0x08, 0x8B, 0xCC, 0x47, 0x0F, 0x5D }, // 4.x New Device Key Source. { 0x6C, 0xEF, 0xC6, 0x27, 0x8B, 0xEC, 0x8A, 0x91, 0x99, 0xAB, 0x24, 0xAC, 0x4F, 0x1C, 0x8F, 0x1C }, // 5.x New Device Key Source. { 0x70, 0x08, 0x1B, 0x97, 0x44, 0x64, 0xF8, 0x91, 0x54, 0x9D, 0xC6, 0x84, 0x8F, 0x1A, 0xB2, 0xE4 }, // 6.x New Device Key Source. @@ -142,10 +142,17 @@ static const u8 new_console_keyseed[KB_FIRMWARE_VERSION_MAX - KB_FIRMWARE_VERSIO { 0x14, 0xB8, 0x74, 0x12, 0xCB, 0xBD, 0x0B, 0x8F, 0x20, 0xFB, 0x30, 0xDA, 0x27, 0xE4, 0x58, 0x94 }, // 9.1.0 New Device Key Source. { 0xAA, 0xFD, 0xBC, 0xBB, 0x25, 0xC3, 0xA4, 0xEF, 0xE3, 0xEE, 0x58, 0x53, 0xB7, 0xF8, 0xDD, 0xD6 }, // 12.1.0 New Device Key Source. { 0xE4, 0xF3, 0x45, 0x6F, 0x18, 0xA1, 0x89, 0xF8, 0xDA, 0x4C, 0x64, 0x75, 0x68, 0xE6, 0xBD, 0x4F }, // 13.0.0 New Device Key Source. + { 0x5B, 0x94, 0x63, 0xF7, 0xAD, 0x96, 0x1B, 0xA6, 0x23, 0x30, 0x06, 0x4D, 0x01, 0xE4, 0xCE, 0x1D }, // 14.0.0 New Device Key Source. + { 0x5E, 0xC9, 0xC5, 0x0A, 0xD0, 0x5F, 0x8B, 0x7B, 0xA7, 0x39, 0xEA, 0xBC, 0x60, 0x0F, 0x74, 0xE6 }, // 15.0.0 New Device Key Source. + { 0xEA, 0x90, 0x6E, 0xA8, 0xAE, 0x92, 0x99, 0x64, 0x36, 0xC1, 0xF3, 0x1C, 0xC6, 0x32, 0x83, 0x8C }, // 16.0.0 New Device Key Source. + { 0xDA, 0xB9, 0xD6, 0x77, 0x52, 0x2D, 0x1F, 0x78, 0x73, 0xC9, 0x98, 0x5B, 0x06, 0xFE, 0xA0, 0x52 }, // 17.0.0 New Device Key Source. + { 0x14, 0xF5, 0xA5, 0xD0, 0x73, 0x6D, 0x44, 0x80, 0x5F, 0x31, 0x5A, 0x8F, 0x1E, 0xD4, 0x0D, 0x63 }, // 18.0.0 New Device Key Source. + { 0x07, 0x38, 0x9A, 0xEC, 0x9C, 0xBD, 0x50, 0x4A, 0x4C, 0x1F, 0x04, 0xDA, 0x40, 0x68, 0x29, 0xE3 }, // 19.0.0 New Device Key Source. + { 0xA3, 0x6B, 0x0A, 0xB5, 0x6F, 0x57, 0x4C, 0x5E, 0x00, 0xFD, 0x56, 0x21, 0xF5, 0x06, 0x6B, 0xD1 }, // 20.0.0 New Device Key Source. }; //!TODO: Update on mkey changes. -static const u8 new_console_kekseed[KB_FIRMWARE_VERSION_MAX - KB_FIRMWARE_VERSION_400 + 1][SE_KEY_128_SIZE] = { +static const u8 new_console_kekseed[HOS_KB_VERSION_MAX - HOS_KB_VERSION_400 + 1][SE_KEY_128_SIZE] = { { 0x88, 0x62, 0x34, 0x6E, 0xFA, 0xF7, 0xD8, 0x3F, 0xE1, 0x30, 0x39, 0x50, 0xF0, 0xB7, 0x5D, 0x5D }, // 4.x New Device Keygen Source. { 0x06, 0x1E, 0x7B, 0xE9, 0x6D, 0x47, 0x8C, 0x77, 0xC5, 0xC8, 0xE7, 0x94, 0x9A, 0xA8, 0x5F, 0x2E }, // 5.x New Device Keygen Source. { 0x99, 0xFA, 0x98, 0xBD, 0x15, 0x1C, 0x72, 0xFD, 0x7D, 0x9A, 0xD5, 0x41, 0x00, 0xFD, 0xB2, 0xEF }, // 6.x New Device Keygen Source. @@ -156,6 +163,13 @@ static const u8 new_console_kekseed[KB_FIRMWARE_VERSION_MAX - KB_FIRMWARE_VERSIO { 0xCE, 0xFE, 0x41, 0x0F, 0x46, 0x9A, 0x30, 0xD6, 0xF2, 0xE9, 0x0C, 0x6B, 0xB7, 0x15, 0x91, 0x36 }, // 9.1.0 New Device Keygen Source. { 0xC2, 0x65, 0x34, 0x6E, 0xC7, 0xC6, 0x5D, 0x97, 0x3E, 0x34, 0x5C, 0x6B, 0xB3, 0x7E, 0xC6, 0xE3 }, // 12.1.0 New Device Keygen Source. { 0x77, 0x52, 0x92, 0xF0, 0xAA, 0xE3, 0xFB, 0xE0, 0x60, 0x16, 0xB3, 0x78, 0x68, 0x53, 0xF7, 0xA8 }, // 13.0.0 New Device Keygen Source. + { 0x67, 0xD5, 0xD6, 0x0C, 0x08, 0xF5, 0xA3, 0x11, 0xBD, 0x6D, 0x5A, 0xEB, 0x96, 0x24, 0xB0, 0xD2 }, // 14.0.0 New Device Keygen Source. + { 0x7C, 0x30, 0xED, 0x8B, 0x39, 0x25, 0x2C, 0x08, 0x8F, 0x48, 0xDC, 0x28, 0xE6, 0x1A, 0x6B, 0x49 }, // 15.0.0 New Device Keygen Source. + { 0xF0, 0xF3, 0xFF, 0x52, 0x75, 0x2F, 0xBA, 0x4D, 0x09, 0x72, 0x30, 0x89, 0xA9, 0xDF, 0xFE, 0x1F }, // 16.0.0 New Device Keygen Source. + { 0x21, 0xD6, 0x35, 0xF1, 0x0F, 0x7A, 0xF0, 0x5D, 0xDF, 0x79, 0x1C, 0x7A, 0xE4, 0x32, 0x82, 0x9E }, // 17.0.0 New Device Keygen Source. + { 0xE7, 0x85, 0x8C, 0xA2, 0xF4, 0x49, 0xCB, 0x07, 0xD1, 0x8E, 0x48, 0x1B, 0xE8, 0x1E, 0x28, 0x3B }, // 18.0.0 New Device Keygen Source. + { 0x9B, 0xA5, 0xFD, 0x74, 0x7F, 0xCD, 0x23, 0xD1, 0xD9, 0xBD, 0x6C, 0x51, 0x72, 0x5F, 0x3D, 0x1F }, // 19.0.0 New Device Keygen Source. + { 0xDA, 0xFB, 0x61, 0x39, 0x48, 0x2D, 0xC2, 0x7E, 0x0D, 0x8E, 0x8F, 0x98, 0x57, 0x20, 0xB8, 0x15 }, // 20.0.0 New Device Keygen Source. }; static const u8 gen_keyseed[SE_KEY_128_SIZE] = @@ -208,7 +222,7 @@ static void _hos_eks_get() if (!h_cfg.eks) { // Read EKS blob. - u8 *mbr = calloc(512 , 1); + u8 *mbr = zalloc(SD_BLOCKSIZE); if (!hos_eks_rw_try(mbr, false)) goto out; @@ -238,7 +252,7 @@ static void _hos_eks_save() bool new_eks = false; if (!h_cfg.eks) { - h_cfg.eks = calloc(512 , 1); + h_cfg.eks = zalloc(SD_BLOCKSIZE); new_eks = true; } @@ -246,7 +260,7 @@ static void _hos_eks_save() if (h_cfg.eks->enabled != HOS_EKS_TSEC_VER) { // Read EKS blob. - u8 *mbr = calloc(512 , 1); + u8 *mbr = zalloc(SD_BLOCKSIZE); if (!hos_eks_rw_try(mbr, false)) { if (new_eks) @@ -259,8 +273,8 @@ static void _hos_eks_save() } // Get keys. - u8 *keys = (u8 *)calloc(0x2000, 1); - se_get_aes_keys(keys + 0x1000, keys, SE_KEY_128_SIZE); + u8 *keys = (u8 *)zalloc(SZ_8K); + se_get_aes_keys(keys + SZ_4K, keys, SE_KEY_128_SIZE); // Set magic and personalized info. h_cfg.eks->magic = HOS_EKS_MAGIC; @@ -273,7 +287,7 @@ static void _hos_eks_save() memcpy(h_cfg.eks->troot_dev, keys + 11 * SE_KEY_128_SIZE, SE_KEY_128_SIZE); // Encrypt EKS blob. - u8 *eks = calloc(512 , 1); + u8 *eks = zalloc(SD_BLOCKSIZE); memcpy(eks, h_cfg.eks, sizeof(hos_eks_mbr_t)); se_aes_crypt_ecb(14, ENCRYPT, eks, sizeof(hos_eks_mbr_t), eks, sizeof(hos_eks_mbr_t)); @@ -294,13 +308,13 @@ void hos_eks_clear(u32 kb) if (h_cfg.t210b01) return; - if (h_cfg.eks && kb >= KB_FIRMWARE_VERSION_700) + if (h_cfg.eks && kb >= HOS_KB_VERSION_700) { // Check if current Master key is enabled. if (h_cfg.eks->enabled) { // Read EKS blob. - u8 *mbr = calloc(512 , 1); + u8 *mbr = zalloc(SD_BLOCKSIZE); if (!hos_eks_rw_try(mbr, false)) goto out; @@ -308,7 +322,7 @@ void hos_eks_clear(u32 kb) h_cfg.eks->enabled = 0; // Encrypt EKS blob. - u8 *eks = calloc(512 , 1); + u8 *eks = zalloc(SD_BLOCKSIZE); memcpy(eks, h_cfg.eks, sizeof(hos_eks_mbr_t)); se_aes_crypt_ecb(14, ENCRYPT, eks, sizeof(hos_eks_mbr_t), eks, sizeof(hos_eks_mbr_t)); @@ -323,21 +337,6 @@ out: } } -int hos_keygen_t210b01(u32 kb) -{ - // Use SBK as Device key 4x unsealer and KEK for mkey in T210B01 units. - se_aes_unwrap_key(10, 14, console_keyseed_4xx); - - // Derive master key. - se_aes_unwrap_key(7, 12, &master_kekseed_t210b01[kb - KB_FIRMWARE_VERSION_600]); - se_aes_unwrap_key(7, 7, master_keyseed_retail); - - // Derive latest pkg2 key. - se_aes_unwrap_key(8, 7, package2_keyseed); - - return 1; -} - int hos_keygen(void *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt) { u32 retries = 0; @@ -345,11 +344,24 @@ int hos_keygen(void *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt) tsec_keys_t tsec_keys; kb_t *kb_data = (kb_t *)keyblob; - if (kb > KB_FIRMWARE_VERSION_MAX) + if (kb > HOS_KB_VERSION_MAX) return 0; + // Do Mariko keygen. if (h_cfg.t210b01) - return hos_keygen_t210b01(kb); + { + // Use SBK as Device key 4x unsealer and KEK for mkey in T210B01 units. + se_aes_unwrap_key(10, 14, console_keyseed_4xx); + + // Derive master key. + se_aes_unwrap_key(7, 12, master_kekseed_t210b01[kb - HOS_KB_VERSION_600]); + se_aes_unwrap_key(7, 7, master_keyseed_retail); + + // Derive latest pkg2 key. + se_aes_unwrap_key(8, 7, package2_keyseed); + + return 1; + } // Do Erista keygen. @@ -357,21 +369,21 @@ int hos_keygen(void *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt) _hos_eks_get(); // Use tsec keygen for old firmware or if EKS keys does not exist for newer. - if (kb <= KB_FIRMWARE_VERSION_620 || !h_cfg.eks || (h_cfg.eks && h_cfg.eks->enabled != HOS_EKS_TSEC_VER)) + if (kb <= HOS_KB_VERSION_620 || !h_cfg.eks || (h_cfg.eks->enabled != HOS_EKS_TSEC_VER)) use_tsec = true; - if (kb <= KB_FIRMWARE_VERSION_600) + if (kb <= HOS_KB_VERSION_600) { tsec_ctxt->size = 0xF00; tsec_ctxt->type = TSEC_FW_TYPE_OLD; } - else if (kb == KB_FIRMWARE_VERSION_620) + else if (kb == HOS_KB_VERSION_620) { tsec_ctxt->size = 0x2900; tsec_ctxt->type = TSEC_FW_TYPE_EMU; // Prepare smmu tsec page for 6.2.0. - u8 *tsec_paged = (u8 *)page_alloc(3); + u8 *tsec_paged = (u8 *)smmu_page_zalloc(3); memcpy(tsec_paged, (void *)tsec_ctxt->fw, tsec_ctxt->size); tsec_ctxt->fw = tsec_paged; } @@ -415,7 +427,7 @@ int hos_keygen(void *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt) } } - if (kb >= KB_FIRMWARE_VERSION_700) + if (kb >= HOS_KB_VERSION_700) { // For 7.0.0 and up, save EKS slot if it doesn't exist. if (use_tsec) @@ -441,7 +453,7 @@ int hos_keygen(void *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt) // Package2 key. se_aes_unwrap_key(8, 7, package2_keyseed); } - else if (kb == KB_FIRMWARE_VERSION_620) + else if (kb == HOS_KB_VERSION_620) { // Set TSEC key. se_aes_key_set(12, tsec_keys.tsec, SE_KEY_128_SIZE); @@ -498,20 +510,20 @@ int hos_keygen(void *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt) switch (kb) { - case KB_FIRMWARE_VERSION_100: - case KB_FIRMWARE_VERSION_300: - case KB_FIRMWARE_VERSION_301: + case HOS_KB_VERSION_100: + case HOS_KB_VERSION_300: + case HOS_KB_VERSION_301: se_aes_unwrap_key(13, 15, console_keyseed); se_aes_unwrap_key(12, 12, master_keyseed_retail); break; - case KB_FIRMWARE_VERSION_400: + case HOS_KB_VERSION_400: se_aes_unwrap_key(13, 15, console_keyseed_4xx); se_aes_unwrap_key(15, 15, console_keyseed); //se_aes_unwrap_key(14, 12, master_keyseed_4xx); // In this context it's useless. So don't kill SBK. se_aes_unwrap_key(12, 12, master_keyseed_retail); break; - case KB_FIRMWARE_VERSION_500: - case KB_FIRMWARE_VERSION_600: + case HOS_KB_VERSION_500: + case HOS_KB_VERSION_600: se_aes_unwrap_key(10, 15, console_keyseed_4xx); se_aes_unwrap_key(15, 15, console_keyseed); //se_aes_unwrap_key(14, 12, master_keyseed_4xx); // In this context it's useless. So don't kill SBK. @@ -549,7 +561,7 @@ static void _hos_validate_mkey() } while (mkey_idx - 1); se_aes_key_clear(2); - hos_eks_clear(KB_FIRMWARE_VERSION_MAX); + hos_eks_clear(HOS_KB_VERSION_MAX); } static void _hos_bis_print_key(u32 idx, u8 *key) @@ -568,14 +580,14 @@ static void _hos_bis_print_key(u32 idx, u8 *key) int hos_bis_keygen() { u32 keygen_rev = 0; - u32 console_key_slot = 15; // KB_FIRMWARE_VERSION_MAX. Only for Erista. + u32 console_key_slot = 15; // HOS_KB_VERSION_MAX. Only for Erista. tsec_ctxt_t tsec_ctxt = {0}; if (!bis_keys) bis_keys = malloc(SE_KEY_128_SIZE * 6); // Run initial keygen. - hos_keygen(NULL, KB_FIRMWARE_VERSION_MAX, &tsec_ctxt); + hos_keygen(NULL, HOS_KB_VERSION_MAX, &tsec_ctxt); // All Mariko use new device keygen. New keygen was introduced in 4.0.0. // We check unconditionally in order to support downgrades. @@ -589,7 +601,7 @@ int hos_bis_keygen() u32 mkey_idx = sizeof(mkey_vectors) / SE_KEY_128_SIZE; // Keygen revision uses bootloader version, which starts from 1. - keygen_rev -= (KB_FIRMWARE_VERSION_400 + 1); + keygen_rev -= (HOS_KB_VERSION_400 + 1); // Derive mkey 0. do @@ -639,7 +651,7 @@ int hos_bis_keygen() se_aes_crypt_block_ecb(2, DECRYPT, bis_keys + (4 * SE_KEY_128_SIZE), bis_keyseed[4]); se_aes_crypt_block_ecb(2, DECRYPT, bis_keys + (5 * SE_KEY_128_SIZE), bis_keyseed[5]); - // Validate key because KB_FIRMWARE_VERSION_MAX. + // Validate key because HOS_KB_VERSION_MAX. if (!h_cfg.t210b01) _hos_validate_mkey(); @@ -670,4 +682,53 @@ void hos_bis_keys_clear() // Clear all aes bis keyslots. for (u32 i = 0; i < 6; i++) se_aes_key_clear(i); -} \ No newline at end of file +} + +int hos_dump_cal0() +{ + // Init eMMC. + if (!emmc_initialize(false)) + return 1; + + // Generate BIS keys + hos_bis_keygen(); + + if (!cal0_buf) + cal0_buf = malloc(SZ_64K); + + // Read and decrypt CAL0. + emmc_set_partition(EMMC_GPP); + LIST_INIT(gpt); + emmc_gpt_parse(&gpt); + emmc_part_t *cal0_part = emmc_part_find(&gpt, "PRODINFO"); // check if null + nx_emmc_bis_init(cal0_part, false, 0); + nx_emmc_bis_read(0, 0x40, cal0_buf); + nx_emmc_bis_end(); + emmc_gpt_free(&gpt); + + emmc_end(); + + // Clear BIS keys slots. + hos_bis_keys_clear(); + + nx_emmc_cal0_t *cal0 = (nx_emmc_cal0_t *)cal0_buf; + + // Check keys validity. + if (memcmp(&cal0->magic, "CAL0", 4)) + { + free(cal0_buf); + cal0_buf = NULL; + + // Clear EKS keys. + hos_eks_clear(HOS_KB_VERSION_MAX); + + return 2; + } + + u32 hash[8]; + se_calc_sha256_oneshot(hash, (u8 *)cal0 + 0x40, cal0->body_size); + if (memcmp(hash, cal0->body_sha256, 0x20)) + return 3; + + return 0; +} diff --git a/nyx/nyx_gui/hos/hos.h b/nyx/nyx_gui/hos/hos.h index 82bbb14..bdc82b9 100644 --- a/nyx/nyx_gui/hos/hos.h +++ b/nyx/nyx_gui/hos/hos.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,35 +18,43 @@ #ifndef _HOS_H_ #define _HOS_H_ +#include + #include "pkg1.h" #include "pkg2.h" -#include -#include -#include -#include #include -#define KB_FIRMWARE_VERSION_100 0 -#define KB_FIRMWARE_VERSION_300 1 -#define KB_FIRMWARE_VERSION_301 2 -#define KB_FIRMWARE_VERSION_400 3 -#define KB_FIRMWARE_VERSION_500 4 -#define KB_FIRMWARE_VERSION_600 5 -#define KB_FIRMWARE_VERSION_620 6 -#define KB_FIRMWARE_VERSION_700 7 -#define KB_FIRMWARE_VERSION_810 8 -#define KB_FIRMWARE_VERSION_900 9 -#define KB_FIRMWARE_VERSION_910 10 -#define KB_FIRMWARE_VERSION_1210 11 -#define KB_FIRMWARE_VERSION_1300 12 -#define KB_FIRMWARE_VERSION_MAX KB_FIRMWARE_VERSION_1300 //!TODO: Update on mkey changes. +//!TODO: Update on mkey changes. +enum { + HOS_KB_VERSION_100 = 0, + HOS_KB_VERSION_300 = 1, + HOS_KB_VERSION_301 = 2, + HOS_KB_VERSION_400 = 3, + HOS_KB_VERSION_500 = 4, + HOS_KB_VERSION_600 = 5, + HOS_KB_VERSION_620 = 6, + HOS_KB_VERSION_700 = 7, + HOS_KB_VERSION_810 = 8, + HOS_KB_VERSION_900 = 9, + HOS_KB_VERSION_910 = 10, + HOS_KB_VERSION_1210 = 11, + HOS_KB_VERSION_1300 = 12, + HOS_KB_VERSION_1400 = 13, + HOS_KB_VERSION_1500 = 14, + HOS_KB_VERSION_1600 = 15, + HOS_KB_VERSION_1700 = 16, + HOS_KB_VERSION_1800 = 17, + HOS_KB_VERSION_1900 = 18, + HOS_KB_VERSION_2000 = 19, + HOS_KB_VERSION_MAX = HOS_KB_VERSION_2000 +}; #define HOS_TSEC_VERSION 4 //! TODO: Update on TSEC Root Key changes. #define HOS_PKG11_MAGIC 0x31314B50 #define HOS_EKS_MAGIC 0x31534B45 // EKS1. -#define HOS_EKS_TSEC_VER (KB_FIRMWARE_VERSION_700 + HOS_TSEC_VERSION) +#define HOS_EKS_TSEC_VER (HOS_KB_VERSION_700 + HOS_TSEC_VERSION) typedef struct _hos_eks_mbr_t { @@ -85,9 +93,12 @@ typedef struct _launch_ctxt_t ini_sec_t *cfg; } launch_ctxt_t; +extern u8 *cal0_buf; + void hos_eks_clear(u32 kb); int hos_keygen(void *keyblob, u32 kb, tsec_ctxt_t *tsec_ctxt); int hos_bis_keygen(); void hos_bis_keys_clear(); +int hos_dump_cal0(); #endif diff --git a/nyx/nyx_gui/hos/pkg1.c b/nyx/nyx_gui/hos/pkg1.c index cfa8b78..f0a4d53 100644 --- a/nyx/nyx_gui/hos/pkg1.c +++ b/nyx/nyx_gui/hos/pkg1.c @@ -1,7 +1,7 @@ /* * Copyright (c) 2018 naehrwert * Copyright (c) 2018 st4rk - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2025 CTCaer * Copyright (c) 2018 balika011 * * This program is free software; you can redistribute it and/or modify it @@ -19,13 +19,11 @@ #include +#include + #include "hos.h" #include "pkg1.h" #include "../config.h" -#include -#include -#include -#include extern hekate_config h_cfg; @@ -41,41 +39,51 @@ static const u8 sec_map_100[3] = { PK11_SECTION_SM, PK11_SECTION_LD, PK11_SECTIO static const u8 sec_map_2xx[3] = { PK11_SECTION_WB, PK11_SECTION_LD, PK11_SECTION_SM }; static const u8 sec_map_4xx[3] = { PK11_SECTION_LD, PK11_SECTION_SM, PK11_SECTION_WB }; - // ID (Timestamp), KB, TSEC, PK11, SECMON, Warmboot. + // Timestamp KB TSEC PK11 SECMON Warmboot static const pkg1_id_t _pkg1_ids[] = { - { "20161121183008", 0, 0x1900, 0x3FE0, 0x40014020, 0x8000D000 }, // 1.0.0. - { "20170210155124", 0, 0x1900, 0x3FE0, 0x4002D000, 0x8000D000 }, // 2.0.0 - 2.3.0. - { "20170519101410", 1, 0x1A00, 0x3FE0, 0x4002D000, 0x8000D000 }, // 3.0.0. - { "20170710161758", 2, 0x1A00, 0x3FE0, 0x4002D000, 0x8000D000 }, // 3.0.1 - 3.0.2. - { "20170921172629", 3, 0x1800, 0x3FE0, 0x4002B000, 0x4003B000 }, // 4.0.0 - 4.1.0. - { "20180220163747", 4, 0x1900, 0x3FE0, 0x4002B000, 0x4003B000 }, // 5.0.0 - 5.1.0. - { "20180802162753", 5, 0x1900, 0x3FE0, 0x4002B000, 0x4003D800 }, // 6.0.0 - 6.1.0. - { "20181107105733", 6, 0x0E00, 0x6FE0, 0x4002B000, 0x4003D800 }, // 6.2.0. - { "20181218175730", 7, 0x0F00, 0x6FE0, 0x40030000, 0x4003E000 }, // 7.0.0. - { "20190208150037", 7, 0x0F00, 0x6FE0, 0x40030000, 0x4003E000 }, // 7.0.1. - { "20190314172056", 7, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 8.0.0 - 8.0.1. - { "20190531152432", 8, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 8.1.0 - 8.1.1. - { "20190809135709", 9, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 9.0.0 - 9.0.1. - { "20191021113848", 10, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 9.1.0 - 9.2.0. - { "20200303104606", 10, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 10.0.0 - 10.2.0. - { "20201030110855", 10, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 11.0.0 - 11.0.1. - { "20210129111626", 10, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 12.0.0 - 12.0.1. - { "20210422145837", 10, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 12.0.2 - 12.0.3. - { "20210607122020", 11, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 12.1.0. - { "20210805123738", 11, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 13.0.0+ + { "20161121", 0, 0x1900, 0x3FE0, 0x40014020, 0x8000D000 }, // 1.0.0. + { "20170210", 0, 0x1900, 0x3FE0, 0x4002D000, 0x8000D000 }, // 2.0.0 - 2.3.0. + { "20170519", 1, 0x1A00, 0x3FE0, 0x4002D000, 0x8000D000 }, // 3.0.0. + { "20170710", 2, 0x1A00, 0x3FE0, 0x4002D000, 0x8000D000 }, // 3.0.1 - 3.0.2. + { "20170921", 3, 0x1800, 0x3FE0, 0x4002B000, 0x4003B000 }, // 4.0.0 - 4.1.0. + { "20180220", 4, 0x1900, 0x3FE0, 0x4002B000, 0x4003B000 }, // 5.0.0 - 5.1.0. + { "20180802", 5, 0x1900, 0x3FE0, 0x4002B000, 0x4003D800 }, // 6.0.0 - 6.1.0. + { "20181107", 6, 0x0E00, 0x6FE0, 0x4002B000, 0x4003D800 }, // 6.2.0. + { "20181218", 7, 0x0F00, 0x6FE0, 0x40030000, 0x4003E000 }, // 7.0.0. + { "20190208", 7, 0x0F00, 0x6FE0, 0x40030000, 0x4003E000 }, // 7.0.1. + { "20190314", 7, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 8.0.0 - 8.0.1. + { "20190531", 8, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 8.1.0 - 8.1.1. + { "20190809", 9, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 9.0.0 - 9.0.1. + { "20191021", 10, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 9.1.0 - 9.2.0. + { "20200303", 10, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 10.0.0 - 10.2.0. + { "20201030", 10, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 11.0.0 - 11.0.1. + { "20210129", 10, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 12.0.0 - 12.0.1. + { "20210422", 10, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 12.0.2 - 12.0.3. + { "20210607", 11, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 12.1.0. + { "20210805", 12, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 13.0.0 - 13.2.0 + { "20220105", 12, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 13.2.1. + { "20220209", 13, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 14.0.0 - 14.1.2. + { "20220801", 14, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 15.0.0 - 15.0.1. + { "20230111", 15, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 16.0.0 - 16.1.0. + { "20230906", 16, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 17.0.0 - 17.0.1. + { "20240207", 17, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 18.0.0 - 18.1.0. + { "20240808", 18, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 19.0.0 - 19.0.1. + { "20250206", 19, 0x0E00, 0x6FE0, 0x40030000, 0x4003E000 }, // 20.0.0+ }; const pkg1_id_t *pkg1_identify(u8 *pkg1, char *build_date) { + pk1_hdr_t *hdr = (pk1_hdr_t *)pkg1; if (build_date) { - memcpy(build_date, (char *)(pkg1 + 0x10), 14); + memcpy(build_date, hdr->timestamp, 14); build_date[14] = 0; } for (u32 i = 0; i < ARRAY_SIZE(_pkg1_ids); i++) - if (!memcmp(pkg1 + 0x10, _pkg1_ids[i].id, 8)) + if (!memcmp(hdr->timestamp, _pkg1_ids[i].id, 8)) return &_pkg1_ids[i]; + return NULL; } @@ -113,12 +121,11 @@ const u8 *pkg1_unpack(void *wm_dst, void *sm_dst, void *ldr_dst, const pkg1_id_t const pk11_hdr_t *hdr = (pk11_hdr_t *)(pkg1 + id->pkg11_off + 0x20); u32 sec_size[3] = { hdr->wb_size, hdr->ldr_size, hdr->sm_size }; - //u32 sec_off[3] = { hdr->wb_off, hdr->ldr_off, hdr->sm_off }; // Get correct header mapping. - if (id->kb == KB_FIRMWARE_VERSION_100 && !strcmp(id->id, "20161121183008")) + if (id->kb == HOS_KB_VERSION_100 && !memcmp(id->id, "20161121", 8)) sec_map = sec_map_100; - else if (id->kb >= KB_FIRMWARE_VERSION_100 && id->kb <= KB_FIRMWARE_VERSION_301) + else if (id->kb <= HOS_KB_VERSION_301) sec_map = sec_map_2xx; else sec_map = sec_map_4xx; @@ -127,13 +134,23 @@ const u8 *pkg1_unpack(void *wm_dst, void *sm_dst, void *ldr_dst, const pkg1_id_t u8 *pdata = (u8 *)hdr + sizeof(pk11_hdr_t); for (u32 i = 0; i < 3; i++) { - if (sec_map[i] == PK11_SECTION_WB && wm_dst) - memcpy(wm_dst, pdata, sec_size[sec_map[i]]); - else if (sec_map[i] == PK11_SECTION_LD && ldr_dst) - memcpy(ldr_dst, pdata, sec_size[sec_map[i]]); - else if (sec_map[i] == PK11_SECTION_SM && sm_dst) - memcpy(sm_dst, pdata, sec_size[sec_map[i]]); - pdata += sec_size[sec_map[i]]; + u32 ssize = sec_size[sec_map[i]]; + switch (sec_map[i]) + { + case PK11_SECTION_WB: + if (wm_dst) + memcpy(wm_dst, pdata, ssize); + break; + case PK11_SECTION_LD: + if (ldr_dst) + memcpy(ldr_dst, pdata, ssize); + break; + case PK11_SECTION_SM: + if (sm_dst) + memcpy(sm_dst, pdata, ssize); + break; + } + pdata += ssize; } return sec_map; diff --git a/nyx/nyx_gui/hos/pkg1.h b/nyx/nyx_gui/hos/pkg1.h index ca6295d..6d30b58 100644 --- a/nyx/nyx_gui/hos/pkg1.h +++ b/nyx/nyx_gui/hos/pkg1.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2018 naehrwert + * Copyright (c) 2022-2023 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,7 +18,7 @@ #ifndef _PKG1_H_ #define _PKG1_H_ -#include +#include #define PKG1_MAGIC 0x31314B50 @@ -27,17 +28,28 @@ typedef struct _bl_hdr_t210b01_t { - u8 aes_mac[0x10]; - u8 rsa_sig[0x100]; - u8 salt[0x20]; - u8 sha256[0x20]; - u32 version; - u32 size; - u32 load_addr; - u32 entrypoint; - u8 rsvd[0x10]; +/* 0x000 */ u8 aes_mac[0x10]; +/* 0x010 */ u8 rsa_sig[0x100]; +/* 0x110 */ u8 salt[0x20]; +/* 0x130 */ u8 sha256[0x20]; +/* 0x150 */ u32 version; +/* 0x154 */ u32 size; +/* 0x158 */ u32 load_addr; +/* 0x15C */ u32 entrypoint; +/* 0x160 */ u8 rsvd[0x10]; } bl_hdr_t210b01_t; +typedef struct _pk1_hdr_t +{ +/* 0x00 */ u32 si_sha256; // Secure Init. +/* 0x04 */ u32 sm_sha256; // Secure Monitor. +/* 0x08 */ u32 sl_sha256; // Secure Loader. +/* 0x0C */ u32 unk; // what's this? It's not warmboot. +/* 0x10 */ char timestamp[14]; +/* 0x1E */ u8 keygen; +/* 0x1F */ u8 version; +} pk1_hdr_t; + typedef struct _pkg1_id_t { const char *id; diff --git a/nyx/nyx_gui/hos/pkg2.c b/nyx/nyx_gui/hos/pkg2.c index 0fb48c6..7b6d6cb 100644 --- a/nyx/nyx_gui/hos/pkg2.c +++ b/nyx/nyx_gui/hos/pkg2.c @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2024 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -17,27 +17,22 @@ #include +#include + #include "pkg2.h" #include "hos.h" #include "../config.h" #include -#include -#include -#include #include -#include - extern hekate_config h_cfg; extern const u8 package2_keyseed[]; -u32 pkg2_newkern_ini1_val; u32 pkg2_newkern_ini1_start; u32 pkg2_newkern_ini1_end; -/*#include -#define DPRINTF(...) gfx_printf(__VA_ARGS__) +/*#define DPRINTF(...) gfx_printf(__VA_ARGS__) #define DEBUG_PRINTING*/ #define DPRINTF(...) @@ -51,16 +46,26 @@ u32 pkg2_calc_kip1_size(pkg2_kip1_t *kip1) void pkg2_get_newkern_info(u8 *kern_data) { - u32 pkg2_newkern_ini1_off = 0; - pkg2_newkern_ini1_start = 0; + u32 crt_start = 0; + u32 pkg2_newkern_ini1_info = 0; + pkg2_newkern_ini1_start = 0; + + u32 first_op = *(u32 *)kern_data; + if ((first_op & 0xFE000000) == 0x14000000) + crt_start = (first_op & 0x1FFFFFF) << 2; // Find static OP offset that is close to INI1 offset. u32 counter_ops = 0x100; while (counter_ops) { - if (*(u32 *)(kern_data + 0x100 - counter_ops) == PKG2_NEWKERN_GET_INI1_HEURISTIC) + if (*(u32 *)(kern_data + crt_start + 0x100 - counter_ops) == PKG2_NEWKERN_GET_INI1_HEURISTIC) { - pkg2_newkern_ini1_off = 0x100 - counter_ops + 12; // OP found. Add 12 for the INI1 offset. + // OP found. Add 12 for the INI1 info offset. + pkg2_newkern_ini1_info = crt_start + 0x100 - counter_ops + 12; + + // On v2 kernel with dynamic crt there's a NOP after heuristic. Offset one op. + if (crt_start) + pkg2_newkern_ini1_info += 4; break; } @@ -71,49 +76,22 @@ void pkg2_get_newkern_info(u8 *kern_data) if (!counter_ops) return; - u32 info_op = *(u32 *)(kern_data + pkg2_newkern_ini1_off); - pkg2_newkern_ini1_val = ((info_op & 0xFFFF) >> 3) + pkg2_newkern_ini1_off; // Parse ADR and PC. + u32 info_op = *(u32 *)(kern_data + pkg2_newkern_ini1_info); + pkg2_newkern_ini1_info += ((info_op & 0xFFFF) >> 3); // Parse ADR and PC. - pkg2_newkern_ini1_start = *(u32 *)(kern_data + pkg2_newkern_ini1_val); - pkg2_newkern_ini1_end = *(u32 *)(kern_data + pkg2_newkern_ini1_val + 0x8); -} + pkg2_newkern_ini1_start = *(u32 *)(kern_data + pkg2_newkern_ini1_info); + pkg2_newkern_ini1_end = *(u32 *)(kern_data + pkg2_newkern_ini1_info + 0x8); -bool pkg2_parse_kips(link_t *info, pkg2_hdr_t *pkg2, bool *new_pkg2) -{ - u8 *ptr; - // Check for new pkg2 type. - if (!pkg2->sec_size[PKG2_SEC_INI1]) + // On v2 kernel with dynamic crt, values are relative to value address. + if (crt_start) { - pkg2_get_newkern_info(pkg2->data); - - if (!pkg2_newkern_ini1_start) - return false; - - ptr = pkg2->data + pkg2_newkern_ini1_start; - *new_pkg2 = true; + pkg2_newkern_ini1_start += pkg2_newkern_ini1_info; + pkg2_newkern_ini1_end += pkg2_newkern_ini1_info + 0x8; } - else - ptr = pkg2->data + pkg2->sec_size[PKG2_SEC_KERNEL]; - - pkg2_ini1_t *ini1 = (pkg2_ini1_t *)ptr; - ptr += sizeof(pkg2_ini1_t); - - for (u32 i = 0; i < ini1->num_procs; i++) - { - pkg2_kip1_t *kip1 = (pkg2_kip1_t *)ptr; - pkg2_kip1_info_t *ki = (pkg2_kip1_info_t *)malloc(sizeof(pkg2_kip1_info_t)); - ki->kip1 = kip1; - ki->size = pkg2_calc_kip1_size(kip1); - list_append(info, &ki->link); - ptr += ki->size; -DPRINTF(" kip1 %d:%s @ %08X (%08X)\n", i, kip1->name, (u32)kip1, ki->size); - } - - return true; } //!TODO: Update on mkey changes. -static const u8 mkey_vector_7xx[][SE_KEY_128_SIZE] = +static const u8 mkey_vector_7xx[HOS_KB_VERSION_MAX - HOS_KB_VERSION_810 + 1][SE_KEY_128_SIZE] = { // Master key 7 encrypted with 8. (7.0.0 with 8.1.0) { 0xEA, 0x60, 0xB3, 0xEA, 0xCE, 0x8F, 0x24, 0x46, 0x7D, 0x33, 0x9C, 0xD1, 0xBC, 0x24, 0x98, 0x29 }, @@ -125,6 +103,20 @@ static const u8 mkey_vector_7xx[][SE_KEY_128_SIZE] = { 0xC1, 0x8D, 0x16, 0xBB, 0x2A, 0xE4, 0x1D, 0xD4, 0xC2, 0xC1, 0xB6, 0x40, 0x94, 0x35, 0x63, 0x98 }, // Master key 11 encrypted with 12. (12.1.0 with 13.0.0) { 0xA3, 0x24, 0x65, 0x75, 0xEA, 0xCC, 0x6E, 0x8D, 0xFB, 0x5A, 0x16, 0x50, 0x74, 0xD2, 0x15, 0x06 }, + // Master key 12 encrypted with 13. (13.0.0 with 14.0.0) + { 0x83, 0x67, 0xAF, 0x01, 0xCF, 0x93, 0xA1, 0xAB, 0x80, 0x45, 0xF7, 0x3F, 0x72, 0xFD, 0x3B, 0x38 }, + // Master key 13 encrypted with 14. (14.0.0 with 15.0.0) + { 0xB1, 0x81, 0xA6, 0x0D, 0x72, 0xC7, 0xEE, 0x15, 0x21, 0xF3, 0xC0, 0xB5, 0x6B, 0x61, 0x6D, 0xE7 }, + // Master key 14 encrypted with 15. (15.0.0 with 16.0.0) + { 0xAF, 0x11, 0x4C, 0x67, 0x17, 0x7A, 0x52, 0x43, 0xF7, 0x70, 0x2F, 0xC7, 0xEF, 0x81, 0x72, 0x16 }, + // Master key 15 encrypted with 16. (16.0.0 with 17.0.0) + { 0x25, 0x12, 0x8B, 0xCB, 0xB5, 0x46, 0xA1, 0xF8, 0xE0, 0x52, 0x15, 0xB7, 0x0B, 0x57, 0x00, 0xBD }, + // Master key 16 encrypted with 17. (17.0.0 with 18.0.0) + { 0x58, 0x15, 0xD2, 0xF6, 0x8A, 0xE8, 0x19, 0xAB, 0xFB, 0x2D, 0x52, 0x9D, 0xE7, 0x55, 0xF3, 0x93 }, + // Master key 17 encrypted with 18. (18.0.0 with 19.0.0) + { 0x4A, 0x01, 0x3B, 0xC7, 0x44, 0x6E, 0x45, 0xBD, 0xE6, 0x5E, 0x2B, 0xEC, 0x07, 0x37, 0x52, 0x86 }, + // Master key 18 encrypted with 19. (19.0.0 with 20.0.0) + { 0x97, 0xE4, 0x11, 0xAB, 0x22, 0x72, 0x1A, 0x1F, 0x70, 0x5C, 0x00, 0xB3, 0x96, 0x30, 0x05, 0x28 }, }; static bool _pkg2_key_unwrap_validate(pkg2_hdr_t *tmp_test, pkg2_hdr_t *hdr, u8 src_slot, u8 *mkey, const u8 *key_seed) @@ -163,13 +155,13 @@ pkg2_hdr_t *pkg2_decrypt(void *data, u8 kb) goto key_found; // Decrypt older pkg2 via new mkeys. - if ((kb >= KB_FIRMWARE_VERSION_700) && (kb < KB_FIRMWARE_VERSION_MAX)) + if ((kb >= HOS_KB_VERSION_700) && (kb < HOS_KB_VERSION_MAX)) { u8 tmp_mkey[SE_KEY_128_SIZE]; u8 decr_slot = 7; // THK mkey or T210B01 mkey. u8 mkey_seeds_cnt = sizeof(mkey_vector_7xx) / SE_KEY_128_SIZE; u8 mkey_seeds_idx = mkey_seeds_cnt; // Real index + 1. - u8 mkey_seeds_min_idx = mkey_seeds_cnt - (KB_FIRMWARE_VERSION_MAX - kb); + u8 mkey_seeds_min_idx = mkey_seeds_cnt - (HOS_KB_VERSION_MAX - kb); while (mkey_seeds_cnt) { diff --git a/nyx/nyx_gui/hos/pkg2.h b/nyx/nyx_gui/hos/pkg2.h index fddfce7..df24639 100644 --- a/nyx/nyx_gui/hos/pkg2.h +++ b/nyx/nyx_gui/hos/pkg2.h @@ -1,6 +1,6 @@ /* * Copyright (c) 2018 naehrwert - * Copyright (c) 2018-2020 CTCaer + * Copyright (c) 2018-2025 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -18,19 +18,21 @@ #ifndef _PKG2_H_ #define _PKG2_H_ -#include -#include +#include -#define PKG2_MAGIC 0x31324B50 -#define PKG2_SEC_BASE 0x80000000 +#define PKG2_MAGIC 0x31324B50 +#define PKG2_SEC_BASE 0x80000000 #define PKG2_SEC_KERNEL 0 -#define PKG2_SEC_INI1 1 +#define PKG2_SEC_INI1 1 +#define PKG2_SEC_UNUSED 2 #define INI1_MAGIC 0x31494E49 -#define PKG2_NEWKERN_GET_INI1_HEURISTIC 0xD2800015 // Offset of OP + 12 is the INI1 offset. + +//! TODO: Update on kernel change if needed. +// Offset of OP + 12 is the INI1 offset. On v2 with dynamic crt0 it's + 16. +#define PKG2_NEWKERN_GET_INI1_HEURISTIC 0xD2800015 // MOV X21, #0. #define PKG2_NEWKERN_START 0x800 -extern u32 pkg2_newkern_ini1_val; extern u32 pkg2_newkern_ini1_start; extern u32 pkg2_newkern_ini1_end; @@ -91,8 +93,7 @@ typedef struct _pkg2_kip1_info_t } pkg2_kip1_info_t; void pkg2_get_newkern_info(u8 *kern_data); -u32 pkg2_calc_kip1_size(pkg2_kip1_t *kip1); -bool pkg2_parse_kips(link_t *info, pkg2_hdr_t *pkg2, bool *new_pkg2); +u32 pkg2_calc_kip1_size(pkg2_kip1_t *kip1); pkg2_hdr_t *pkg2_decrypt(void *data, u8 kb); diff --git a/nyx/nyx_gui/libs/fatfs/diskio.c b/nyx/nyx_gui/libs/fatfs/diskio.c index 3d37f7d..c877800 100644 --- a/nyx/nyx_gui/libs/fatfs/diskio.c +++ b/nyx/nyx_gui/libs/fatfs/diskio.c @@ -1,5 +1,7 @@ /*-----------------------------------------------------------------------*/ -/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2016 */ +/* Low level disk I/O module skeleton for FatFs */ +/* (C) ChaN, 2016 */ +/* (C) CTCaer, 2018-2020 */ /*-----------------------------------------------------------------------*/ /* If a working storage control module is available, it should be */ /* attached to the FatFs via a glue function rather than modifying it. */ @@ -9,12 +11,9 @@ #include +#include + #include /* FatFs lower layer API */ -#include -#include "../../storage/nx_emmc_bis.h" -#include -#include -#include static u32 sd_rsvd_sectors = 0; static u32 ramdisk_sectors = 0; @@ -139,6 +138,18 @@ DRESULT disk_ioctl ( break; } } + else // Catch all for unknown devices. + { + switch (cmd) + { + case CTRL_SYNC: + break; + case GET_SECTOR_COUNT: + case GET_BLOCK_SIZE: + *buf = 0; // Zero value to force default or abort. + break; + } + } return RES_OK; } diff --git a/nyx/nyx_gui/libs/fatfs/ffconf.h b/nyx/nyx_gui/libs/fatfs/ffconf.h index 8e417ad..d0c6f70 100644 --- a/nyx/nyx_gui/libs/fatfs/ffconf.h +++ b/nyx/nyx_gui/libs/fatfs/ffconf.h @@ -257,7 +257,7 @@ #define FF_FS_NORTC 0 #define FF_NORTC_MON 1 #define FF_NORTC_MDAY 1 -#define FF_NORTC_YEAR 2021 +#define FF_NORTC_YEAR 2024 /* The option FF_FS_NORTC switches timestamp function. If the system does not have / any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable / the timestamp function. Every object modified by FatFs will have a fixed timestamp diff --git a/nyx/nyx_gui/nyx.c b/nyx/nyx_gui/nyx.c index a8a026d..05275a2 100644 --- a/nyx/nyx_gui/nyx.c +++ b/nyx/nyx_gui/nyx.c @@ -1,7 +1,7 @@ /* * Copyright (c) 2018 naehrwert * - * Copyright (c) 2018-2021 CTCaer + * Copyright (c) 2018-2023 CTCaer * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -19,50 +19,23 @@ #include #include -#include +#include #include "config.h" -#include -#include #include "hos/hos.h" #include #include #include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "storage/nx_emmc.h" -#include -#include -#include -#include -#include -#include #include "frontend/fe_emmc_tools.h" #include "frontend/gui.h" -#ifdef MENU_LOGO_ENABLE -u8 *Kc_MENU_LOGO; -#endif //MENU_LOGO_ENABLE - nyx_config n_cfg; hekate_config h_cfg; const volatile ipl_ver_meta_t __attribute__((section ("._ipl_version"))) ipl_ver = { .magic = NYX_MAGIC, - .version = (NYX_VER_MJ + '0') | ((NYX_VER_MN + '0') << 8) | ((NYX_VER_HF + '0') << 16), + .version = (NYX_VER_MJ + '0') | ((NYX_VER_MN + '0') << 8) | ((NYX_VER_HF + '0') << 16) | ((NYX_VER_RL) << 24), .rsvd0 = 0, .rsvd1 = 0 }; @@ -81,12 +54,12 @@ char *emmcsn_path_impl(char *path, char *sub_dir, char *filename, sdmmc_storage_ // Get actual eMMC S/N. if (!storage) { - if (!sdmmc_storage_init_mmc(&emmc_storage, &emmc_sdmmc, SDMMC_BUS_WIDTH_8, SDHCI_TIMING_MMC_HS400)) + if (!emmc_initialize(false)) strcpy(emmc_sn, "00000000"); else { itoa(emmc_storage.cid.serial, emmc_sn, 16); - sdmmc_storage_end(&emmc_storage); + emmc_end(); } } else @@ -126,7 +99,7 @@ create_dir: #define EXT_PAYLOAD_ADDR 0xC0000000 #define RCM_PAYLOAD_ADDR (EXT_PAYLOAD_ADDR + ALIGN(PATCHED_RELOC_SZ, 0x10)) #define COREBOOT_END_ADDR 0xD0000000 -#define CBFS_DRAM_EN_ADDR 0x4003e000 +#define CBFS_DRAM_EN_ADDR 0x4003E000 #define CBFS_DRAM_MAGIC 0x4452414D // "DRAM" static void *coreboot_addr; @@ -144,7 +117,7 @@ void reloc_patcher(u32 payload_dst, u32 payload_src, u32 payload_size) if (payload_size == 0x7000) { - memcpy((u8 *)(payload_src + ALIGN(PATCHED_RELOC_SZ, 0x10)), coreboot_addr, 0x7000); //Bootblock + memcpy((u8 *)(payload_src + ALIGN(PATCHED_RELOC_SZ, 0x10)), coreboot_addr, 0x7000); // Bootblock. *(vu32 *)CBFS_DRAM_EN_ADDR = CBFS_DRAM_MAGIC; } } @@ -161,145 +134,198 @@ lv_res_t launch_payload(lv_obj_t *list) strcpy(path,"bootloader/payloads/"); strcat(path, filename); - if (sd_mount()) + if (!sd_mount()) + goto out; + + FIL fp; + if (f_open(&fp, path, FA_READ)) { - FIL fp; - if (f_open(&fp, path, FA_READ)) - { - EPRINTFARGS("Payload file is missing!\n(%s)", path); + EPRINTFARGS("Payload file is missing!\n(%s)", path); - goto out; - } + goto out; + } - // Read and copy the payload to our chosen address - void *buf; - u32 size = f_size(&fp); + // Read and copy the payload to our chosen address + void *buf; + u32 size = f_size(&fp); - if (size < 0x30000) - buf = (void *)RCM_PAYLOAD_ADDR; - else - { - coreboot_addr = (void *)(COREBOOT_END_ADDR - size); - buf = coreboot_addr; - if (h_cfg.t210b01) - { - f_close(&fp); - - EPRINTF("Coreboot not allowed on Mariko!"); - - goto out; - } - } - - if (f_read(&fp, buf, size, NULL)) + if (size < 0x30000) + buf = (void *)RCM_PAYLOAD_ADDR; + else + { + coreboot_addr = (void *)(COREBOOT_END_ADDR - size); + buf = coreboot_addr; + if (h_cfg.t210b01) { f_close(&fp); + EPRINTF("Coreboot not allowed on Mariko!"); + goto out; } + } + if (f_read(&fp, buf, size, NULL)) + { f_close(&fp); - sd_end(); - - if (size < 0x30000) - { - reloc_patcher(PATCHED_RELOC_ENTRY, EXT_PAYLOAD_ADDR, ALIGN(size, 0x10)); - hw_reinit_workaround(false, byte_swap_32(*(u32 *)(buf + size - sizeof(u32)))); - } - else - { - reloc_patcher(PATCHED_RELOC_ENTRY, EXT_PAYLOAD_ADDR, 0x7000); - hw_reinit_workaround(true, 0); - } - - void (*ext_payload_ptr)() = (void *)EXT_PAYLOAD_ADDR; - - // Some cards (Sandisk U1), do not like a fast power cycle. Wait min 100ms. - sdmmc_storage_init_wait_sd(); - - // Launch our payload. - (*ext_payload_ptr)(); + goto out; } + f_close(&fp); + + sd_end(); + + if (size < 0x30000) + { + reloc_patcher(PATCHED_RELOC_ENTRY, EXT_PAYLOAD_ADDR, ALIGN(size, 0x10)); + hw_deinit(false, byte_swap_32(*(u32 *)(buf + size - sizeof(u32)))); + } + else + { + reloc_patcher(PATCHED_RELOC_ENTRY, EXT_PAYLOAD_ADDR, 0x7000); + hw_deinit(true, 0); + } + + void (*ext_payload_ptr)() = (void *)EXT_PAYLOAD_ADDR; + + // Some cards (Sandisk U1), do not like a fast power cycle. Wait min 100ms. + sdmmc_storage_init_wait_sd(); + + // Launch our payload. + (*ext_payload_ptr)(); + out: sd_unmount(); return LV_RES_OK; } -void load_saved_configuration() +static void _load_saved_configuration() { LIST_INIT(ini_sections); LIST_INIT(ini_nyx_sections); - // Load hekate configuration. - if (ini_parse(&ini_sections, "bootloader/hekate_ipl.ini", false)) + if (!ini_parse(&ini_sections, "bootloader/hekate_ipl.ini", false)) { - LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sections, link) - { - // Only parse config section. - if (ini_sec->type == INI_CHOICE && !strcmp(ini_sec->name, "config")) - { - LIST_FOREACH_ENTRY(ini_kv_t, kv, &ini_sec->kvs, link) - { - if (!strcmp("autoboot", kv->key)) - h_cfg.autoboot = atoi(kv->val); - else if (!strcmp("autoboot_list", kv->key)) - h_cfg.autoboot_list = atoi(kv->val); - else if (!strcmp("bootwait", kv->key)) - h_cfg.bootwait = atoi(kv->val); - else if (!strcmp("backlight", kv->key)) - { - h_cfg.backlight = atoi(kv->val); - if (h_cfg.backlight <= 20) - h_cfg.backlight = 30; - } - else if (!strcmp("autohosoff", kv->key)) - h_cfg.autohosoff = atoi(kv->val); - else if (!strcmp("autonogc", kv->key)) - h_cfg.autonogc = atoi(kv->val); - else if (!strcmp("updater2p", kv->key)) - h_cfg.updater2p = atoi(kv->val); - else if (!strcmp("bootprotect", kv->key)) - h_cfg.bootprotect = atoi(kv->val); - } + create_config_entry(); + goto skip_main_cfg_parse; + } - break; + // Load hekate configuration. + LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_sections, link) + { + // Only parse config section. + if (ini_sec->type == INI_CHOICE && !strcmp(ini_sec->name, "config")) + { + LIST_FOREACH_ENTRY(ini_kv_t, kv, &ini_sec->kvs, link) + { + if (!strcmp("autoboot", kv->key)) + h_cfg.autoboot = atoi(kv->val); + else if (!strcmp("autoboot_list", kv->key)) + h_cfg.autoboot_list = atoi(kv->val); + else if (!strcmp("bootwait", kv->key)) + h_cfg.bootwait = atoi(kv->val); + else if (!strcmp("backlight", kv->key)) + { + h_cfg.backlight = atoi(kv->val); + if (h_cfg.backlight <= 20) + h_cfg.backlight = 30; + } + else if (!strcmp("noticker", kv->key)) + h_cfg.noticker = atoi(kv->val); + else if (!strcmp("autohosoff", kv->key)) + h_cfg.autohosoff = atoi(kv->val); + else if (!strcmp("autonogc", kv->key)) + h_cfg.autonogc = atoi(kv->val); + else if (!strcmp("updater2p", kv->key)) + h_cfg.updater2p = atoi(kv->val); + else if (!strcmp("bootprotect", kv->key)) + h_cfg.bootprotect = atoi(kv->val); } + + break; } } + ini_free(&ini_sections); + +skip_main_cfg_parse: + if (!ini_parse(&ini_nyx_sections, "bootloader/nyx.ini", false)) + return; + // Load Nyx configuration. - if (ini_parse(&ini_nyx_sections, "bootloader/nyx.ini", false)) + LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_nyx_sections, link) { - LIST_FOREACH_ENTRY(ini_sec_t, ini_sec, &ini_nyx_sections, link) + // Only parse config section. + if (ini_sec->type == INI_CHOICE && !strcmp(ini_sec->name, "config")) { - // Only parse config section. - if (ini_sec->type == INI_CHOICE && !strcmp(ini_sec->name, "config")) + LIST_FOREACH_ENTRY(ini_kv_t, kv, &ini_sec->kvs, link) { - LIST_FOREACH_ENTRY(ini_kv_t, kv, &ini_sec->kvs, link) + if (!strcmp("themebg", kv->key)) + n_cfg.theme_bg = strtol(kv->val, NULL, 16); + else if (!strcmp("themecolor", kv->key)) + n_cfg.theme_color = atoi(kv->val); + else if (!strcmp("entries5col", kv->key)) + n_cfg.entries_5_col = atoi(kv->val) == 1; + else if (!strcmp("timeoff", kv->key)) { - if (!strcmp("themecolor", kv->key)) - n_cfg.themecolor = atoi(kv->val); - else if (!strcmp("timeoff", kv->key)) - n_cfg.timeoff = strtol(kv->val, NULL, 16); - else if (!strcmp("homescreen", kv->key)) - n_cfg.home_screen = atoi(kv->val); - else if (!strcmp("verification", kv->key)) - n_cfg.verification = atoi(kv->val); - else if (!strcmp("umsemmcrw", kv->key)) - n_cfg.ums_emmc_rw = atoi(kv->val) == 1; - else if (!strcmp("jcdisable", kv->key)) - n_cfg.jc_disable = atoi(kv->val) == 1; - else if (!strcmp("bpmpclock", kv->key)) - n_cfg.bpmp_clock = strtol(kv->val, NULL, 10); + n_cfg.timeoff = strtol(kv->val, NULL, 16); + if (n_cfg.timeoff != 1) + max77620_rtc_set_epoch_offset((int)n_cfg.timeoff); } - - break; + else if (!strcmp("homescreen", kv->key)) + n_cfg.home_screen = atoi(kv->val); + else if (!strcmp("verification", kv->key)) + n_cfg.verification = atoi(kv->val); + else if (!strcmp("umsemmcrw", kv->key)) + n_cfg.ums_emmc_rw = atoi(kv->val) == 1; + else if (!strcmp("jcdisable", kv->key)) + n_cfg.jc_disable = atoi(kv->val) == 1; + else if (!strcmp("jcforceright", kv->key)) + n_cfg.jc_force_right = atoi(kv->val) == 1; + else if (!strcmp("bpmpclock", kv->key)) + n_cfg.bpmp_clock = atoi(kv->val); } + + break; } } + + ini_free(&ini_nyx_sections); +} + +static int nyx_load_resources() +{ + FIL fp; + int res; + + res = f_open(&fp, "bootloader/sys/res.pak", FA_READ); + if (res) + return res; + + res = f_read(&fp, (void *)NYX_RES_ADDR, f_size(&fp), NULL); + f_close(&fp); + + return res; +} + +static void nyx_load_bg_icons() +{ + // If no custom switch icon exists, load normal. + if (!f_stat("bootloader/res/icon_switch_custom.bmp", NULL)) + icon_switch = bmp_to_lvimg_obj("bootloader/res/icon_switch_custom.bmp"); + else + icon_switch = bmp_to_lvimg_obj("bootloader/res/icon_switch.bmp"); + + // If no custom payload icon exists, load normal. + if (!f_stat("bootloader/res/icon_payload_custom.bmp", NULL)) + icon_payload = bmp_to_lvimg_obj("bootloader/res/icon_payload_custom.bmp"); + else + icon_payload = bmp_to_lvimg_obj("bootloader/res/icon_payload.bmp"); + + // Load background resource if any. + hekate_bg = bmp_to_lvimg_obj("bootloader/res/background.bmp"); } #define EXCP_EN_ADDR 0x4003FFFC @@ -311,21 +337,43 @@ void load_saved_configuration() #define EXCP_TYPE_DABRT 0x54424144 // DABT #define EXCP_LR_ADDR 0x4003FFF4 -static void _show_errors() +enum { + SD_NO_ERROR = 0, + SD_MOUNT_ERROR = 1, + SD_FILE_ERROR = 2 +}; + +static void _show_errors(int sd_error) { u32 *excp_enabled = (u32 *)EXCP_EN_ADDR; u32 *excp_type = (u32 *)EXCP_TYPE_ADDR; u32 *excp_lr = (u32 *)EXCP_LR_ADDR; - if (*excp_enabled == EXCP_MAGIC) + if (*excp_enabled == EXCP_MAGIC || sd_error) { gfx_clear_grey(0); - gfx_con_setpos(0, 0); - display_backlight_brightness(100, 1000); + gfx_con_setpos(0, 0, 0); + display_backlight_brightness(150, 1000); + display_init_window_d_console(); + display_window_d_console_enable(); + } - display_activate_console(); + switch (sd_error) + { + case SD_MOUNT_ERROR: + WPRINTF("Failed to init or mount SD!\n"); + goto error_occured; + case SD_FILE_ERROR: + WPRINTF("Failed to load GUI resources!\nres.pak not found or corrupted.\n"); + goto error_occured; + case SD_NO_ERROR: + default: + break; + } - WPRINTFARGS("An exception occurred (LR %08X):\n", *excp_lr); + if (*excp_enabled == EXCP_MAGIC) + { + WPRINTFARGS("Nyx exception occurred (LR %08X):\n", *excp_lr); switch (*excp_type) { case EXCP_TYPE_RESET: @@ -341,19 +389,20 @@ static void _show_errors() WPRINTF("DABRT"); break; } - WPRINTF("\n"); + gfx_puts("\n"); // Clear the exception. *excp_lr = 0; *excp_type = 0; *excp_enabled = 0; - WPRINTF("Press any key..."); +error_occured: + WPRINTF("Press any key to reload Nyx..."); - msleep(2000); + msleep(1000); btn_wait(); - reload_nyx(); + reload_nyx(NULL, true); } } @@ -388,91 +437,95 @@ void nyx_init_load_res() gfx_con_init(); // Show exception errors if any. - _show_errors(); + _show_errors(SD_NO_ERROR); - sd_mount(); + // Try 2 times to mount SD card. + if (!sd_mount()) + { + // Restore speed to SDR104. + sd_end(); + + // Retry. + if (!sd_mount()) + _show_errors(SD_MOUNT_ERROR); // Fatal. + } // Train DRAM and switch to max frequency. minerva_init(); - load_saved_configuration(); + // Load hekate/Nyx configuration. + _load_saved_configuration(); - // Initialize nyx cfg to lower clock for T210. + // Load Nyx resources. + if (nyx_load_resources()) + { + // Try again. + if (nyx_load_resources()) + _show_errors(SD_FILE_ERROR); // Fatal since resources are mandatory. + } + + // Initialize nyx cfg to lower clock on first boot. // In case of lower binned SoC, this can help with hangs. if (!n_cfg.bpmp_clock) { - n_cfg.bpmp_clock = h_cfg.t210b01 ? 1 : 2; // Set lower clock for T210. + // Set lower clock and save it. + n_cfg.bpmp_clock = 2; create_nyx_config_entry(false); - n_cfg.bpmp_clock = h_cfg.t210b01 ? 1 : 0; // Restore for T210 and keep for T210B01. + + // Start at max clock and test it. + n_cfg.bpmp_clock = 0; } - // Restore clock to max. - if (n_cfg.bpmp_clock < 2) - bpmp_clk_rate_set(BPMP_CLK_DEFAULT_BOOST); - - FIL fp; - if (!f_open(&fp, "bootloader/sys/res.pak", FA_READ)) + // Set selected clock. + switch (n_cfg.bpmp_clock) { - f_read(&fp, (void *)NYX_RES_ADDR, f_size(&fp), NULL); - f_close(&fp); + case 0: + case 1: + bpmp_clk_rate_set(BPMP_CLK_DEFAULT_BOOST); + break; + case 2: + bpmp_clk_rate_set(BPMP_CLK_LOWER_BOOST); + break; + case 3: + default: + bpmp_clk_rate_set(BPMP_CLK_LOWEST_BOOST); + break; } - // If no custom switch icon exists, load normal. - if (f_stat("bootloader/res/icon_switch_custom.bmp", NULL)) - icon_switch = bmp_to_lvimg_obj("bootloader/res/icon_switch.bmp"); - else - icon_switch = bmp_to_lvimg_obj("bootloader/res/icon_switch_custom.bmp"); - - // If no custom payload icon exists, load normal. - if (f_stat("bootloader/res/icon_payload_custom.bmp", NULL)) - icon_payload = bmp_to_lvimg_obj("bootloader/res/icon_payload.bmp"); - else - icon_payload = bmp_to_lvimg_obj("bootloader/res/icon_payload_custom.bmp"); - - // Load background resource if any. - hekate_bg = bmp_to_lvimg_obj("bootloader/res/background.bmp"); + // Load default launch icons and background if it exists. + nyx_load_bg_icons(); + // Unmount FAT partition. sd_unmount(); } -#if (LV_LOG_PRINTF == 1) - #include - #include - #include -#endif - void ipl_main() { - //Tegra/Horizon configuration goes to 0x80000000+, package2 goes to 0xA9800000, we place our heap in between. - heap_init(IPL_HEAP_START); - + // Set heap address. + heap_init((void *)IPL_HEAP_START); b_cfg = (boot_cfg_t *)(nyx_str->hekate + 0x94); - // Important: Preserve version header! - __asm__ ("" : : "" (ipl_ver)); - #ifdef DEBUG_UART_PORT - #if DEBUG_UART_PORT == UART_B + // Enable the selected uart debug port. + #if (DEBUG_UART_PORT == UART_B) gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_SPIO); - gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_GPIO); - #endif - #if DEBUG_UART_PORT == UART_C - gpio_config(GPIO_PORT_G, GPIO_PIN_0, GPIO_MODE_GPIO); + #elif (DEBUG_UART_PORT == UART_C) gpio_config(GPIO_PORT_D, GPIO_PIN_1, GPIO_MODE_SPIO); #endif pinmux_config_uart(DEBUG_UART_PORT); clock_enable_uart(DEBUG_UART_PORT); - uart_init(DEBUG_UART_PORT, DEBUG_UART_BAUDRATE); + uart_init(DEBUG_UART_PORT, DEBUG_UART_BAUDRATE, UART_AO_TX_AO_RX); uart_invert(DEBUG_UART_PORT, DEBUG_UART_INVERT, UART_INVERT_TXD); uart_send(DEBUG_UART_PORT, (u8 *)"hekate-NYX: Hello!\r\n", 20); - uart_wait_idle(DEBUG_UART_PORT, UART_TX_IDLE); + uart_wait_xfer(DEBUG_UART_PORT, UART_TX_IDLE); #endif - // Initialize the rest of hw and load nyx's resources. + // Initialize the rest of hw and load Nyx resources. nyx_init_load_res(); + // Initialize Nyx GUI and show it. nyx_load_and_run(); // Halt BPMP if we managed to get out of execution. diff --git a/nyx/nyx_gui/start.S b/nyx/nyx_gui/start.S index 0d1eebf..c2333f7 100644 --- a/nyx/nyx_gui/start.S +++ b/nyx/nyx_gui/start.S @@ -61,7 +61,7 @@ _reloc_ipl: _real_start: /* We place our stack in SDRAM. */ - LDR SP, =0x83100000 + LDR SP, =0x4003F000 LDR R0, =__bss_start EOR R1, R1, R1 LDR R2, =__bss_end diff --git a/nyx/nyx_gui/storage/nx_emmc.c b/nyx/nyx_gui/storage/nx_emmc.c deleted file mode 100644 index f7a2a94..0000000 --- a/nyx/nyx_gui/storage/nx_emmc.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * Copyright (c) 2018 naehrwert - * Copyright (c) 2019-2020 CTCaer - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see . - */ - -#include - -#include "nx_emmc.h" -#include -#include -#include -#include - -sdmmc_t emmc_sdmmc; -sdmmc_storage_t emmc_storage; -FATFS emmc_fs; - -void nx_emmc_gpt_parse(link_t *gpt, sdmmc_storage_t *storage) -{ - gpt_t *gpt_buf = (gpt_t *)calloc(NX_GPT_NUM_BLOCKS, NX_EMMC_BLOCKSIZE); - - sdmmc_storage_read(storage, NX_GPT_FIRST_LBA, NX_GPT_NUM_BLOCKS, gpt_buf); - - // Check if no GPT or more than max allowed entries. - if (memcmp(&gpt_buf->header.signature, "EFI PART", 8) || gpt_buf->header.num_part_ents > 128) - goto out; - - for (u32 i = 0; i < gpt_buf->header.num_part_ents; i++) - { - emmc_part_t *part = (emmc_part_t *)calloc(sizeof(emmc_part_t), 1); - - if (gpt_buf->entries[i].lba_start < gpt_buf->header.first_use_lba) - continue; - - part->index = i; - part->lba_start = gpt_buf->entries[i].lba_start; - part->lba_end = gpt_buf->entries[i].lba_end; - part->attrs = gpt_buf->entries[i].attrs; - - // ASCII conversion. Copy only the LSByte of the UTF-16LE name. - for (u32 j = 0; j < 36; j++) - part->name[j] = gpt_buf->entries[i].name[j]; - part->name[35] = 0; - - list_append(gpt, &part->link); - } - -out: - free(gpt_buf); -} - -void nx_emmc_gpt_free(link_t *gpt) -{ - LIST_FOREACH_SAFE(iter, gpt) - free(CONTAINER_OF(iter, emmc_part_t, link)); -} - -emmc_part_t *nx_emmc_part_find(link_t *gpt, const char *name) -{ - LIST_FOREACH_ENTRY(emmc_part_t, part, gpt, link) - if (!strcmp(part->name, name)) - return part; - return NULL; -} - -int nx_emmc_part_read(sdmmc_storage_t *storage, emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf) -{ - // The last LBA is inclusive. - if (part->lba_start + sector_off > part->lba_end) - return 0; - return sdmmc_storage_read(storage, part->lba_start + sector_off, num_sectors, buf); -} - -int nx_emmc_part_write(sdmmc_storage_t *storage, emmc_part_t *part, u32 sector_off, u32 num_sectors, void *buf) -{ - // The last LBA is inclusive. - if (part->lba_start + sector_off > part->lba_end) - return 0; - return sdmmc_storage_write(storage, part->lba_start + sector_off, num_sectors, buf); -} - -void nx_emmc_get_autorcm_masks(u8 *mod0, u8 *mod1) -{ - if (fuse_read_hw_state() == FUSE_NX_HW_STATE_PROD) - { - *mod0 = 0xF7; - *mod1 = 0x86; - } - else - { - *mod0 = 0x37; - *mod1 = 0x84; - } -} diff --git a/res/hekate_ipl_template.ini b/res/hekate_ipl_template.ini index 7670d6e..fcb886a 100644 --- a/res/hekate_ipl_template.ini +++ b/res/hekate_ipl_template.ini @@ -2,16 +2,20 @@ autoboot=0 autoboot_list=0 bootwait=3 +noticker=0 backlight=100 -autohosoff=0 +autohosoff=1 autonogc=1 updater2p=1 bootprotect=0 +# Only include above what you want to change from defaults. +# config.c in bootloader and Nyx have all the defaults. + {-------- Stock -------} [Stock] -fss0=atmosphere/package3 +pkg3=atmosphere/package3 stock=1 emummc_force_disable=1 @@ -25,7 +29,7 @@ emummc_force_disable=1 {-- Custom Firmwares --} [Atmo Vanilla] -fss0=atmosphere/package3 +pkg3=atmosphere/package3 kip1=atmosphere/kips/* # Note: @@ -35,11 +39,11 @@ kip1=atmosphere/kips/* [Atmo EMU] -fss0=atmosphere/package3 +pkg3=atmosphere/package3 emummcforce=1 [Atmo SYS] -fss0=atmosphere/package3 +pkg3=atmosphere/package3 emummc_force_disable=1 # Note: @@ -54,7 +58,7 @@ emummc_force_disable=1 [Atmo EMU2] -fss0=atmosphere/package3 +pkg3=atmosphere/package3 emupath=emuMMC/SD02 emummcforce=1 @@ -62,30 +66,31 @@ emummcforce=1 # The above allows you to swap emuMMC on the fly while booting. # The path defined is the main path of emuMMC folder, for example # emuMMC/RAW1, emuMMC/RAW2, emuMMC/SD00, emuMMC/TEST, etc. +# Only works with emuMMC created/migrated via hekate. [Atmo with extra kips] -fss0=atmosphere/package3 +pkg3=atmosphere/package3 kip1=cfw/mods/mods_extra/* kip1=cfw/mods/mods_extra/single/extra.kip # Note: -# The above can be used with any fss0 entry. Like the ones above. -# You can even override atmosphere (fss0) kips with this. - +# The above can be used with any pkg3 entry. Like the ones above. +# You can even override atmosphere (pkg3) kips with this. +# The wildcard '*' like above can be used to load all kips from a selected directory. {-- Custom Firmwares Old methods --} -[CFW FSS0 extra kips & patches] -fss0=atmosphere/package3 +[CFW PKG3 extra kips & patches] +pkg3=atmosphere/package3 kip1patch=name_of_patch kip1=cfw/mods/mods_extra/* kip1=cfw/mods/mods_extra/single/extra.kip # Note: # Both options for kip1 can be used. Wildcard and single. -# You can override kips loaded from FSS0 if you define them after the fss0 key. +# You can override kips loaded from PKG3/FSS0 if you define them after the pkg3 key. # If kip1 patch resides in patches.ini and that file OR the patch for # current HOS version does not exist, it will error out. @@ -104,7 +109,7 @@ atmosphere=1 # Note: # All kips defined method. This can be changed to what is below also. -# atmosphere=1 key is IMPORTANT when no FFS0 is defined. +# atmosphere=1 key is IMPORTANT when no PKG3/FSS0 is defined. @@ -126,7 +131,7 @@ payload=bootloader/payloads/Lockpick_RCM.bin -# hekate - CTCaer mod v5.6.0 .ini template +# hekate - CTCaer mod v5.8.0 .ini template # # All entries in this template can have these stylistic keys: # like logopath= key which is for bootlogo and icon= key for Nyx icon. diff --git a/res/patches_template.ini b/res/patches_template.ini index 0ebe8bd..786fcc8 100644 --- a/res/patches_template.ini +++ b/res/patches_template.ini @@ -21,132 +21,3 @@ .nosigchk=0:0x194A0:0x4:BA090094,E0031F2A .nosigchk=0:0x3A79C:0x4:E0060036,1F2003D5 -#FS Patches for 2.0.0 -[FS:cd7bbe18d6130b28] -.nosigchk=0:0x15DF4:0x4:BC0A0094,E0031F2A -.nosigchk=0:0x3F720:0x4:00060036,1F2003D5 - -#FS Patches for 2.0.0 exfat -[FS:e76692dfaa0420e9] -.nosigchk=0:0x15DF4:0x4:BC0A0094,E0031F2A -.nosigchk=0:0x3F720:0x4:00060036,1F2003D5 - -#FS Patches for 2.1.0 -[FS:0d7005627b07767c] -.nosigchk=0:0x15F64:0x4:DF0A0094,E0031F2A -.nosigchk=0:0x3FAF8:0x4:00060036,1F2003D5 - -#FS Patches for 2.1.0 exfat -[FS:dbd85fcacc193da8] -.nosigchk=0:0x15F64:0x4:DF0A0094,E0031F2A -.nosigchk=0:0x3FAF8:0x4:00060036,1F2003D5 - -#FS Patches for 3.0.0 -[FS:a86da5e87ef1097b] -.nosigchk=0:0x18E24:0x4:520C0094,E0031F2A -.nosigchk=0:0x49EC8:0x4:40040036,1F2003D5 - -#FS Patches for 3.0.0 exfat -[FS:981c57e7f02f70f7] -.nosigchk=0:0x18E24:0x4:520C0094,E0031F2A -.nosigchk=0:0x49EC8:0x4:40040036,1F2003D5 - -#FS Patches for 3.0.1 -[FS:57397c063f10b631] -.nosigchk=0:0x18E90:0x4:520C0094,E0031F2A -.nosigchk=0:0x49F34:0x4:E0030036,1F2003D5 - -#FS Patches for 3.0.1 exfat -[FS:073099d7c6ad7d89] -.nosigchk=0:0x18E90:0x4:520C0094,E0031F2A -.nosigchk=0:0x49F34:0x4:E0030036,1F2003D5 - -#FS Patches for 4.0.0 -[FS:06e90719595a010c] -.nosigchk=0:0x1C4FC:0x4:3C2F0094,E0031F2A -.nosigchk=0:0x57934:0x4:E0020036,1F2003D5 - -#FS Patches for 4.0.0 exfat -[FS:549b0f8d6f72c4e9] -.nosigchk=0:0x1C4FC:0x4:3C2F0094,E0031F2A -.nosigchk=0:0x57934:0x4:E0020036,1F2003D5 - -#FS Patches for 4.1.0 -[FS:8096af7c6a35aa82] -.nosigchk=0:0x1C4FC:0x4:3C2F0094,E0031F2A -.nosigchk=0:0x57934:0x4:E0020036,1F2003D5 - -#FS Patches for 4.1.0 exfat -[FS:02d5abaafd20c8b0] -.nosigchk=0:0x1C4FC:0x4:3C2F0094,E0031F2A -.nosigchk=0:0x57934:0x4:E0020036,1F2003D5 - -#FS Patches for 5.0.0 -[FS:a6f27ad9ac7c73ad] -.nosigchk=0:0x22DDC:0x4:7D3E0094,E0031F2A -.nosigchk=0:0x7D490:0x4:40030036,1F2003D5 - -#FS Patches for 5.0.0 exfat -[FS:ce3ecba2f2f062f5] -.nosigchk=0:0x22DDC:0x4:7D3E0094,E0031F2A -.nosigchk=0:0x7D490:0x4:40030036,1F2003D5 - -#FS Patches for 5.1.0 -[FS:76f87402c9387c0f] -.nosigchk=0:0x22E0C:0x4:853E0094,E0031F2A -.nosigchk=0:0x7D860:0x4:40030036,1F2003D5 - -#FS Patches for 5.1.0 exfat -[FS:10b2d81605488599] -.nosigchk=0:0x22E0C:0x4:853E0094,E0031F2A -.nosigchk=0:0x7D860:0x4:40030036,1F2003D5 - -#FS Patches for 6.0.0 - 4 -[FS:1b82cb221867cb52] -.nosigchk=0:0x712A8:0x4:8E3E0094,E0031F2A -.nosigchk=0:0xEB08C:0x4:C0030036,1F2003D5 - -#FS Patches for 6.0.0 - 4 exfat -[FS:966add3d20b62713] -.nosigchk=0:0x7C9A8:0x4:8E3E0094,E0031F2A -.nosigchk=0:0xF678C:0x4:C0030036,1F2003D5 - -#FS Patches for 6.0.0 - 5 -[FS:3a574d436186191d] -.nosigchk=0:0x712A8:0x4:8E3E0094,E0031F2A -.nosigchk=0:0xEB08C:0x4:C0030036,1F2003D5 - -#FS Patches for 6.0.0 - 5 exfat -[FS:330553f6b5fb55c4] -.nosigchk=0:0x7C9A8:0x4:8E3E0094,E0031F2A -.nosigchk=0:0xF678C:0x4:C0030036,1F2003D5 - -#FS Patches for 7.0.0 -[FS:2ADBE97E9B5F4177] -.nosigchk=0:0x74A2C:0x4:31430094,E0031F2A -.nosigchk=0:0xF25E4:0x4:C0030036,1F2003D5 - -#FS Patches for 7.0.0 exfat -[FS:2CCE659CEC536A8E] -.nosigchk=0:0x7FFDC:0x4:31430094,E0031F2A -.nosigchk=0:0xFDB94:0x4:C0030036,1F2003D5 - -#FS Patches for 8.0.0 -[FS:B2F5176B3548364D] -.nosigchk=0:0x7630C:0x4:51440094,E0031F2A -.nosigchk=0:0xF49A4:0x4:C0030036,1F2003D5 - -#FS Patches for 8.0.0 exfat -[FS:DBD941C0C53C52CC] -.nosigchk=0:0x818BC:0x4:51440094,E0031F2A -.nosigchk=0:0xFFF54:0x4:C0030036,1F2003D5 - -#FS Patches for 8.1.0 -[FS:6B09B67B29C02024] -.nosigchk=0:0x7630C:0x4:51440094,E0031F2A -.nosigchk=0:0xF49A4:0x4:C0030036,1F2003D5 - -#FS Patches for 8.1.0 exfat -[FS:B4CAE1F24965D92E] -.nosigchk=0:0x818BC:0x4:51440094,E0031F2A -.nosigchk=0:0xFFF54:0x4:C0030036,1F2003D5